1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2014 Marvell Technology Group Ltd. |
4 | * |
5 | * Antoine Tenart <antoine.tenart@free-electrons.com> |
6 | * Jisheng Zhang <jszhang@marvell.com> |
7 | */ |
8 | |
9 | #include <linux/io.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/phy/phy.h> |
13 | #include <linux/platform_device.h> |
14 | #include <linux/property.h> |
15 | #include <linux/reset.h> |
16 | |
17 | #define USB_PHY_PLL 0x04 |
18 | #define USB_PHY_PLL_CONTROL 0x08 |
19 | #define USB_PHY_TX_CTRL0 0x10 |
20 | #define USB_PHY_TX_CTRL1 0x14 |
21 | #define USB_PHY_TX_CTRL2 0x18 |
22 | #define USB_PHY_RX_CTRL 0x20 |
23 | #define USB_PHY_ANALOG 0x34 |
24 | |
25 | /* USB_PHY_PLL */ |
26 | #define CLK_REF_DIV(x) ((x) << 4) |
27 | #define FEEDBACK_CLK_DIV(x) ((x) << 8) |
28 | |
29 | /* USB_PHY_PLL_CONTROL */ |
30 | #define CLK_STABLE BIT(0) |
31 | #define PLL_CTRL_PIN BIT(1) |
32 | #define PLL_CTRL_REG BIT(2) |
33 | #define PLL_ON BIT(3) |
34 | #define PHASE_OFF_TOL_125 (0x0 << 5) |
35 | #define PHASE_OFF_TOL_250 BIT(5) |
36 | #define KVC0_CALIB (0x0 << 9) |
37 | #define KVC0_REG_CTRL BIT(9) |
38 | #define KVC0_HIGH (0x0 << 10) |
39 | #define KVC0_LOW (0x3 << 10) |
40 | #define CLK_BLK_EN BIT(13) |
41 | |
42 | /* USB_PHY_TX_CTRL0 */ |
43 | #define EXT_HS_RCAL_EN BIT(3) |
44 | #define EXT_FS_RCAL_EN BIT(4) |
45 | #define IMPCAL_VTH_DIV(x) ((x) << 5) |
46 | #define EXT_RS_RCAL_DIV(x) ((x) << 8) |
47 | #define EXT_FS_RCAL_DIV(x) ((x) << 12) |
48 | |
49 | /* USB_PHY_TX_CTRL1 */ |
50 | #define TX_VDD15_14 (0x0 << 4) |
51 | #define TX_VDD15_15 BIT(4) |
52 | #define TX_VDD15_16 (0x2 << 4) |
53 | #define TX_VDD15_17 (0x3 << 4) |
54 | #define TX_VDD12_VDD (0x0 << 6) |
55 | #define TX_VDD12_11 BIT(6) |
56 | #define TX_VDD12_12 (0x2 << 6) |
57 | #define TX_VDD12_13 (0x3 << 6) |
58 | #define LOW_VDD_EN BIT(8) |
59 | #define TX_OUT_AMP(x) ((x) << 9) |
60 | |
61 | /* USB_PHY_TX_CTRL2 */ |
62 | #define TX_CHAN_CTRL_REG(x) ((x) << 0) |
63 | #define DRV_SLEWRATE(x) ((x) << 4) |
64 | #define IMP_CAL_FS_HS_DLY_0 (0x0 << 6) |
65 | #define IMP_CAL_FS_HS_DLY_1 BIT(6) |
66 | #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6) |
67 | #define IMP_CAL_FS_HS_DLY_3 (0x3 << 6) |
68 | #define FS_DRV_EN_MASK(x) ((x) << 8) |
69 | #define HS_DRV_EN_MASK(x) ((x) << 12) |
70 | |
71 | /* USB_PHY_RX_CTRL */ |
72 | #define PHASE_FREEZE_DLY_2_CL (0x0 << 0) |
73 | #define PHASE_FREEZE_DLY_4_CL BIT(0) |
74 | #define ACK_LENGTH_8_CL (0x0 << 2) |
75 | #define ACK_LENGTH_12_CL BIT(2) |
76 | #define ACK_LENGTH_16_CL (0x2 << 2) |
77 | #define ACK_LENGTH_20_CL (0x3 << 2) |
78 | #define SQ_LENGTH_3 (0x0 << 4) |
79 | #define SQ_LENGTH_6 BIT(4) |
80 | #define SQ_LENGTH_9 (0x2 << 4) |
81 | #define SQ_LENGTH_12 (0x3 << 4) |
82 | #define DISCON_THRESHOLD_260 (0x0 << 6) |
83 | #define DISCON_THRESHOLD_270 BIT(6) |
84 | #define DISCON_THRESHOLD_280 (0x2 << 6) |
85 | #define DISCON_THRESHOLD_290 (0x3 << 6) |
86 | #define SQ_THRESHOLD(x) ((x) << 8) |
87 | #define LPF_COEF(x) ((x) << 12) |
88 | #define INTPL_CUR_10 (0x0 << 14) |
89 | #define INTPL_CUR_20 BIT(14) |
90 | #define INTPL_CUR_30 (0x2 << 14) |
91 | #define INTPL_CUR_40 (0x3 << 14) |
92 | |
93 | /* USB_PHY_ANALOG */ |
94 | #define ANA_PWR_UP BIT(1) |
95 | #define ANA_PWR_DOWN BIT(2) |
96 | #define V2I_VCO_RATIO(x) ((x) << 7) |
97 | #define R_ROTATE_90 (0x0 << 10) |
98 | #define R_ROTATE_0 BIT(10) |
99 | #define MODE_TEST_EN BIT(11) |
100 | #define ANA_TEST_DC_CTRL(x) ((x) << 12) |
101 | |
102 | static const u32 phy_berlin_pll_dividers[] = { |
103 | /* Berlin 2 */ |
104 | CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55), |
105 | /* Berlin 2CD/Q */ |
106 | CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54), |
107 | }; |
108 | |
109 | struct phy_berlin_usb_priv { |
110 | void __iomem *base; |
111 | struct reset_control *rst_ctrl; |
112 | u32 pll_divider; |
113 | }; |
114 | |
115 | static int phy_berlin_usb_power_on(struct phy *phy) |
116 | { |
117 | struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy); |
118 | |
119 | reset_control_reset(rstc: priv->rst_ctrl); |
120 | |
121 | writel(val: priv->pll_divider, |
122 | addr: priv->base + USB_PHY_PLL); |
123 | writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL | |
124 | CLK_BLK_EN, addr: priv->base + USB_PHY_PLL_CONTROL); |
125 | writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5), |
126 | addr: priv->base + USB_PHY_ANALOG); |
127 | writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 | |
128 | DISCON_THRESHOLD_270 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) | |
129 | INTPL_CUR_30, addr: priv->base + USB_PHY_RX_CTRL); |
130 | |
131 | writel(TX_VDD12_13 | TX_OUT_AMP(0x3), addr: priv->base + USB_PHY_TX_CTRL1); |
132 | writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), |
133 | addr: priv->base + USB_PHY_TX_CTRL0); |
134 | |
135 | writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) | |
136 | EXT_FS_RCAL_DIV(0x2), addr: priv->base + USB_PHY_TX_CTRL0); |
137 | |
138 | writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), |
139 | addr: priv->base + USB_PHY_TX_CTRL0); |
140 | writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 | |
141 | FS_DRV_EN_MASK(0xd), addr: priv->base + USB_PHY_TX_CTRL2); |
142 | |
143 | return 0; |
144 | } |
145 | |
146 | static const struct phy_ops phy_berlin_usb_ops = { |
147 | .power_on = phy_berlin_usb_power_on, |
148 | .owner = THIS_MODULE, |
149 | }; |
150 | |
151 | static const struct of_device_id phy_berlin_usb_of_match[] = { |
152 | { |
153 | .compatible = "marvell,berlin2-usb-phy" , |
154 | .data = &phy_berlin_pll_dividers[0], |
155 | }, |
156 | { |
157 | .compatible = "marvell,berlin2cd-usb-phy" , |
158 | .data = &phy_berlin_pll_dividers[1], |
159 | }, |
160 | { }, |
161 | }; |
162 | MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match); |
163 | |
164 | static int phy_berlin_usb_probe(struct platform_device *pdev) |
165 | { |
166 | struct phy_berlin_usb_priv *priv; |
167 | struct phy *phy; |
168 | struct phy_provider *phy_provider; |
169 | |
170 | priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL); |
171 | if (!priv) |
172 | return -ENOMEM; |
173 | |
174 | priv->base = devm_platform_ioremap_resource(pdev, index: 0); |
175 | if (IS_ERR(ptr: priv->base)) |
176 | return PTR_ERR(ptr: priv->base); |
177 | |
178 | priv->rst_ctrl = devm_reset_control_get(dev: &pdev->dev, NULL); |
179 | if (IS_ERR(ptr: priv->rst_ctrl)) |
180 | return PTR_ERR(ptr: priv->rst_ctrl); |
181 | |
182 | priv->pll_divider = *((u32 *)device_get_match_data(dev: &pdev->dev)); |
183 | |
184 | phy = devm_phy_create(dev: &pdev->dev, NULL, ops: &phy_berlin_usb_ops); |
185 | if (IS_ERR(ptr: phy)) { |
186 | dev_err(&pdev->dev, "failed to create PHY\n" ); |
187 | return PTR_ERR(ptr: phy); |
188 | } |
189 | |
190 | phy_set_drvdata(phy, data: priv); |
191 | |
192 | phy_provider = |
193 | devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); |
194 | return PTR_ERR_OR_ZERO(ptr: phy_provider); |
195 | } |
196 | |
197 | static struct platform_driver phy_berlin_usb_driver = { |
198 | .probe = phy_berlin_usb_probe, |
199 | .driver = { |
200 | .name = "phy-berlin-usb" , |
201 | .of_match_table = phy_berlin_usb_of_match, |
202 | }, |
203 | }; |
204 | module_platform_driver(phy_berlin_usb_driver); |
205 | |
206 | MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>" ); |
207 | MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB" ); |
208 | MODULE_LICENSE("GPL" ); |
209 | |