1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/bitops.h>
23#include <linux/gpio/driver.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinconf.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/pinctrl/pinconf-generic.h>
31#include <linux/irqchip/chained_irq.h>
32#include <linux/clk.h>
33#include <linux/regmap.h>
34#include <linux/mfd/syscon.h>
35#include <linux/string_helpers.h>
36
37#include <dt-bindings/pinctrl/rockchip.h>
38
39#include "core.h"
40#include "pinconf.h"
41#include "pinctrl-rockchip.h"
42
43/*
44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
45 * register 31:16 area.
46 */
47#define WRITE_MASK_VAL(h, l, v) \
48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
49
50/*
51 * Encode variants of iomux registers into a type variable
52 */
53#define IOMUX_GPIO_ONLY BIT(0)
54#define IOMUX_WIDTH_4BIT BIT(1)
55#define IOMUX_SOURCE_PMU BIT(2)
56#define IOMUX_UNROUTED BIT(3)
57#define IOMUX_WIDTH_3BIT BIT(4)
58#define IOMUX_WIDTH_2BIT BIT(5)
59#define IOMUX_L_SOURCE_PMU BIT(6)
60
61#define PIN_BANK(id, pins, label) \
62 { \
63 .bank_num = id, \
64 .nr_pins = pins, \
65 .name = label, \
66 .iomux = { \
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
71 }, \
72 }
73
74#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
75 { \
76 .bank_num = id, \
77 .nr_pins = pins, \
78 .name = label, \
79 .iomux = { \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
84 }, \
85 }
86
87#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
88 iom1, iom2, iom3, \
89 offset0, offset1, \
90 offset2, offset3, pull0, \
91 pull1, pull2, pull3) \
92 { \
93 .bank_num = id, \
94 .nr_pins = pins, \
95 .name = label, \
96 .iomux = { \
97 { .type = iom0, .offset = offset0 }, \
98 { .type = iom1, .offset = offset1 }, \
99 { .type = iom2, .offset = offset2 }, \
100 { .type = iom3, .offset = offset3 }, \
101 }, \
102 .pull_type[0] = pull0, \
103 .pull_type[1] = pull1, \
104 .pull_type[2] = pull2, \
105 .pull_type[3] = pull3, \
106 }
107
108#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
109 { \
110 .bank_num = id, \
111 .nr_pins = pins, \
112 .name = label, \
113 .iomux = { \
114 { .offset = -1 }, \
115 { .offset = -1 }, \
116 { .offset = -1 }, \
117 { .offset = -1 }, \
118 }, \
119 .drv = { \
120 { .drv_type = type0, .offset = -1 }, \
121 { .drv_type = type1, .offset = -1 }, \
122 { .drv_type = type2, .offset = -1 }, \
123 { .drv_type = type3, .offset = -1 }, \
124 }, \
125 }
126
127#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
128 iom2, iom3, pull0, pull1, \
129 pull2, pull3) \
130 { \
131 .bank_num = id, \
132 .nr_pins = pins, \
133 .name = label, \
134 .iomux = { \
135 { .type = iom0, .offset = -1 }, \
136 { .type = iom1, .offset = -1 }, \
137 { .type = iom2, .offset = -1 }, \
138 { .type = iom3, .offset = -1 }, \
139 }, \
140 .pull_type[0] = pull0, \
141 .pull_type[1] = pull1, \
142 .pull_type[2] = pull2, \
143 .pull_type[3] = pull3, \
144 }
145
146#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
147 drv2, drv3, pull0, pull1, \
148 pull2, pull3) \
149 { \
150 .bank_num = id, \
151 .nr_pins = pins, \
152 .name = label, \
153 .iomux = { \
154 { .offset = -1 }, \
155 { .offset = -1 }, \
156 { .offset = -1 }, \
157 { .offset = -1 }, \
158 }, \
159 .drv = { \
160 { .drv_type = drv0, .offset = -1 }, \
161 { .drv_type = drv1, .offset = -1 }, \
162 { .drv_type = drv2, .offset = -1 }, \
163 { .drv_type = drv3, .offset = -1 }, \
164 }, \
165 .pull_type[0] = pull0, \
166 .pull_type[1] = pull1, \
167 .pull_type[2] = pull2, \
168 .pull_type[3] = pull3, \
169 }
170
171#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
172 iom3, offset0, offset1, offset2, \
173 offset3) \
174 { \
175 .bank_num = id, \
176 .nr_pins = pins, \
177 .name = label, \
178 .iomux = { \
179 { .type = iom0, .offset = offset0 }, \
180 { .type = iom1, .offset = offset1 }, \
181 { .type = iom2, .offset = offset2 }, \
182 { .type = iom3, .offset = offset3 }, \
183 }, \
184 }
185
186#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
187 iom2, iom3, drv0, drv1, drv2, \
188 drv3, offset0, offset1, \
189 offset2, offset3) \
190 { \
191 .bank_num = id, \
192 .nr_pins = pins, \
193 .name = label, \
194 .iomux = { \
195 { .type = iom0, .offset = -1 }, \
196 { .type = iom1, .offset = -1 }, \
197 { .type = iom2, .offset = -1 }, \
198 { .type = iom3, .offset = -1 }, \
199 }, \
200 .drv = { \
201 { .drv_type = drv0, .offset = offset0 }, \
202 { .drv_type = drv1, .offset = offset1 }, \
203 { .drv_type = drv2, .offset = offset2 }, \
204 { .drv_type = drv3, .offset = offset3 }, \
205 }, \
206 }
207
208#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
209 label, iom0, iom1, iom2, \
210 iom3, drv0, drv1, drv2, \
211 drv3, offset0, offset1, \
212 offset2, offset3, pull0, \
213 pull1, pull2, pull3) \
214 { \
215 .bank_num = id, \
216 .nr_pins = pins, \
217 .name = label, \
218 .iomux = { \
219 { .type = iom0, .offset = -1 }, \
220 { .type = iom1, .offset = -1 }, \
221 { .type = iom2, .offset = -1 }, \
222 { .type = iom3, .offset = -1 }, \
223 }, \
224 .drv = { \
225 { .drv_type = drv0, .offset = offset0 }, \
226 { .drv_type = drv1, .offset = offset1 }, \
227 { .drv_type = drv2, .offset = offset2 }, \
228 { .drv_type = drv3, .offset = offset3 }, \
229 }, \
230 .pull_type[0] = pull0, \
231 .pull_type[1] = pull1, \
232 .pull_type[2] = pull2, \
233 .pull_type[3] = pull3, \
234 }
235
236#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
237 { \
238 .bank_num = ID, \
239 .pin = PIN, \
240 .func = FUNC, \
241 .route_offset = REG, \
242 .route_val = VAL, \
243 .route_location = FLAG, \
244 }
245
246#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
247 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
248
249#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
250 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
251
252#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
253 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
254
255#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
256 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
257
258static struct regmap_config rockchip_regmap_config = {
259 .reg_bits = 32,
260 .val_bits = 32,
261 .reg_stride = 4,
262};
263
264static inline const struct rockchip_pin_group *pinctrl_name_to_group(
265 const struct rockchip_pinctrl *info,
266 const char *name)
267{
268 int i;
269
270 for (i = 0; i < info->ngroups; i++) {
271 if (!strcmp(info->groups[i].name, name))
272 return &info->groups[i];
273 }
274
275 return NULL;
276}
277
278/*
279 * given a pin number that is local to a pin controller, find out the pin bank
280 * and the register base of the pin bank.
281 */
282static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
283 unsigned pin)
284{
285 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
286
287 while (pin >= (b->pin_base + b->nr_pins))
288 b++;
289
290 return b;
291}
292
293static struct rockchip_pin_bank *bank_num_to_bank(
294 struct rockchip_pinctrl *info,
295 unsigned num)
296{
297 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
298 int i;
299
300 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
301 if (b->bank_num == num)
302 return b;
303 }
304
305 return ERR_PTR(error: -EINVAL);
306}
307
308/*
309 * Pinctrl_ops handling
310 */
311
312static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
313{
314 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
315
316 return info->ngroups;
317}
318
319static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
320 unsigned selector)
321{
322 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
323
324 return info->groups[selector].name;
325}
326
327static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
328 unsigned selector, const unsigned **pins,
329 unsigned *npins)
330{
331 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
332
333 if (selector >= info->ngroups)
334 return -EINVAL;
335
336 *pins = info->groups[selector].pins;
337 *npins = info->groups[selector].npins;
338
339 return 0;
340}
341
342static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
343 struct device_node *np,
344 struct pinctrl_map **map, unsigned *num_maps)
345{
346 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
347 const struct rockchip_pin_group *grp;
348 struct device *dev = info->dev;
349 struct pinctrl_map *new_map;
350 struct device_node *parent;
351 int map_num = 1;
352 int i;
353
354 /*
355 * first find the group of this node and check if we need to create
356 * config maps for pins
357 */
358 grp = pinctrl_name_to_group(info, name: np->name);
359 if (!grp) {
360 dev_err(dev, "unable to find group for node %pOFn\n", np);
361 return -EINVAL;
362 }
363
364 map_num += grp->npins;
365
366 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
367 if (!new_map)
368 return -ENOMEM;
369
370 *map = new_map;
371 *num_maps = map_num;
372
373 /* create mux map */
374 parent = of_get_parent(node: np);
375 if (!parent) {
376 kfree(objp: new_map);
377 return -EINVAL;
378 }
379 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
380 new_map[0].data.mux.function = parent->name;
381 new_map[0].data.mux.group = np->name;
382 of_node_put(node: parent);
383
384 /* create config map */
385 new_map++;
386 for (i = 0; i < grp->npins; i++) {
387 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
388 new_map[i].data.configs.group_or_pin =
389 pin_get_name(pctldev, pin: grp->pins[i]);
390 new_map[i].data.configs.configs = grp->data[i].configs;
391 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
392 }
393
394 dev_dbg(dev, "maps: function %s group %s num %d\n",
395 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
396
397 return 0;
398}
399
400static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
401 struct pinctrl_map *map, unsigned num_maps)
402{
403 kfree(objp: map);
404}
405
406static const struct pinctrl_ops rockchip_pctrl_ops = {
407 .get_groups_count = rockchip_get_groups_count,
408 .get_group_name = rockchip_get_group_name,
409 .get_group_pins = rockchip_get_group_pins,
410 .dt_node_to_map = rockchip_dt_node_to_map,
411 .dt_free_map = rockchip_dt_free_map,
412};
413
414/*
415 * Hardware access
416 */
417
418static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
419 {
420 .num = 1,
421 .pin = 0,
422 .reg = 0x418,
423 .bit = 0,
424 .mask = 0x3
425 }, {
426 .num = 1,
427 .pin = 1,
428 .reg = 0x418,
429 .bit = 2,
430 .mask = 0x3
431 }, {
432 .num = 1,
433 .pin = 2,
434 .reg = 0x418,
435 .bit = 4,
436 .mask = 0x3
437 }, {
438 .num = 1,
439 .pin = 3,
440 .reg = 0x418,
441 .bit = 6,
442 .mask = 0x3
443 }, {
444 .num = 1,
445 .pin = 4,
446 .reg = 0x418,
447 .bit = 8,
448 .mask = 0x3
449 }, {
450 .num = 1,
451 .pin = 5,
452 .reg = 0x418,
453 .bit = 10,
454 .mask = 0x3
455 }, {
456 .num = 1,
457 .pin = 6,
458 .reg = 0x418,
459 .bit = 12,
460 .mask = 0x3
461 }, {
462 .num = 1,
463 .pin = 7,
464 .reg = 0x418,
465 .bit = 14,
466 .mask = 0x3
467 }, {
468 .num = 1,
469 .pin = 8,
470 .reg = 0x41c,
471 .bit = 0,
472 .mask = 0x3
473 }, {
474 .num = 1,
475 .pin = 9,
476 .reg = 0x41c,
477 .bit = 2,
478 .mask = 0x3
479 },
480};
481
482static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
483 {
484 .num = 0,
485 .pin = 20,
486 .reg = 0x10000,
487 .bit = 0,
488 .mask = 0xf
489 },
490 {
491 .num = 0,
492 .pin = 21,
493 .reg = 0x10000,
494 .bit = 4,
495 .mask = 0xf
496 },
497 {
498 .num = 0,
499 .pin = 22,
500 .reg = 0x10000,
501 .bit = 8,
502 .mask = 0xf
503 },
504 {
505 .num = 0,
506 .pin = 23,
507 .reg = 0x10000,
508 .bit = 12,
509 .mask = 0xf
510 },
511};
512
513static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
514 {
515 .num = 2,
516 .pin = 20,
517 .reg = 0xe8,
518 .bit = 0,
519 .mask = 0x7
520 }, {
521 .num = 2,
522 .pin = 21,
523 .reg = 0xe8,
524 .bit = 4,
525 .mask = 0x7
526 }, {
527 .num = 2,
528 .pin = 22,
529 .reg = 0xe8,
530 .bit = 8,
531 .mask = 0x7
532 }, {
533 .num = 2,
534 .pin = 23,
535 .reg = 0xe8,
536 .bit = 12,
537 .mask = 0x7
538 }, {
539 .num = 2,
540 .pin = 24,
541 .reg = 0xd4,
542 .bit = 12,
543 .mask = 0x7
544 },
545};
546
547static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
548 {
549 /* gpio1b6_sel */
550 .num = 1,
551 .pin = 14,
552 .reg = 0x28,
553 .bit = 12,
554 .mask = 0xf
555 }, {
556 /* gpio1b7_sel */
557 .num = 1,
558 .pin = 15,
559 .reg = 0x2c,
560 .bit = 0,
561 .mask = 0x3
562 }, {
563 /* gpio1c2_sel */
564 .num = 1,
565 .pin = 18,
566 .reg = 0x30,
567 .bit = 4,
568 .mask = 0xf
569 }, {
570 /* gpio1c3_sel */
571 .num = 1,
572 .pin = 19,
573 .reg = 0x30,
574 .bit = 8,
575 .mask = 0xf
576 }, {
577 /* gpio1c4_sel */
578 .num = 1,
579 .pin = 20,
580 .reg = 0x30,
581 .bit = 12,
582 .mask = 0xf
583 }, {
584 /* gpio1c5_sel */
585 .num = 1,
586 .pin = 21,
587 .reg = 0x34,
588 .bit = 0,
589 .mask = 0xf
590 }, {
591 /* gpio1c6_sel */
592 .num = 1,
593 .pin = 22,
594 .reg = 0x34,
595 .bit = 4,
596 .mask = 0xf
597 }, {
598 /* gpio1c7_sel */
599 .num = 1,
600 .pin = 23,
601 .reg = 0x34,
602 .bit = 8,
603 .mask = 0xf
604 }, {
605 /* gpio2a2_sel */
606 .num = 2,
607 .pin = 2,
608 .reg = 0x40,
609 .bit = 4,
610 .mask = 0x3
611 }, {
612 /* gpio2a3_sel */
613 .num = 2,
614 .pin = 3,
615 .reg = 0x40,
616 .bit = 6,
617 .mask = 0x3
618 }, {
619 /* gpio2c0_sel */
620 .num = 2,
621 .pin = 16,
622 .reg = 0x50,
623 .bit = 0,
624 .mask = 0x3
625 }, {
626 /* gpio3b2_sel */
627 .num = 3,
628 .pin = 10,
629 .reg = 0x68,
630 .bit = 4,
631 .mask = 0x3
632 }, {
633 /* gpio3b3_sel */
634 .num = 3,
635 .pin = 11,
636 .reg = 0x68,
637 .bit = 6,
638 .mask = 0x3
639 }, {
640 /* gpio3b4_sel */
641 .num = 3,
642 .pin = 12,
643 .reg = 0x68,
644 .bit = 8,
645 .mask = 0xf
646 }, {
647 /* gpio3b5_sel */
648 .num = 3,
649 .pin = 13,
650 .reg = 0x68,
651 .bit = 12,
652 .mask = 0xf
653 },
654};
655
656static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
657 {
658 /* gpio2_b7_sel */
659 .num = 2,
660 .pin = 15,
661 .reg = 0x28,
662 .bit = 0,
663 .mask = 0x7
664 }, {
665 /* gpio2_c7_sel */
666 .num = 2,
667 .pin = 23,
668 .reg = 0x30,
669 .bit = 14,
670 .mask = 0x3
671 }, {
672 /* gpio3_b1_sel */
673 .num = 3,
674 .pin = 9,
675 .reg = 0x44,
676 .bit = 2,
677 .mask = 0x3
678 }, {
679 /* gpio3_b2_sel */
680 .num = 3,
681 .pin = 10,
682 .reg = 0x44,
683 .bit = 4,
684 .mask = 0x3
685 }, {
686 /* gpio3_b3_sel */
687 .num = 3,
688 .pin = 11,
689 .reg = 0x44,
690 .bit = 6,
691 .mask = 0x3
692 }, {
693 /* gpio3_b4_sel */
694 .num = 3,
695 .pin = 12,
696 .reg = 0x44,
697 .bit = 8,
698 .mask = 0x3
699 }, {
700 /* gpio3_b5_sel */
701 .num = 3,
702 .pin = 13,
703 .reg = 0x44,
704 .bit = 10,
705 .mask = 0x3
706 }, {
707 /* gpio3_b6_sel */
708 .num = 3,
709 .pin = 14,
710 .reg = 0x44,
711 .bit = 12,
712 .mask = 0x3
713 }, {
714 /* gpio3_b7_sel */
715 .num = 3,
716 .pin = 15,
717 .reg = 0x44,
718 .bit = 14,
719 .mask = 0x3
720 },
721};
722
723static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
724 int *reg, u8 *bit, int *mask)
725{
726 struct rockchip_pinctrl *info = bank->drvdata;
727 struct rockchip_pin_ctrl *ctrl = info->ctrl;
728 struct rockchip_mux_recalced_data *data;
729 int i;
730
731 for (i = 0; i < ctrl->niomux_recalced; i++) {
732 data = &ctrl->iomux_recalced[i];
733 if (data->num == bank->bank_num &&
734 data->pin == pin)
735 break;
736 }
737
738 if (i >= ctrl->niomux_recalced)
739 return;
740
741 *reg = data->reg;
742 *mask = data->mask;
743 *bit = data->bit;
744}
745
746static struct rockchip_mux_route_data px30_mux_route_data[] = {
747 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
748 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
749 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
750 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
751 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
752 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
753 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
754 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
755 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
756 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
757 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
758 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
759 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
760 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
761 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
762 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
763 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
764 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
765 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
766 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
767 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
768 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
769 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
770 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
771 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
772 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
773 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
774 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
775 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
776 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
777 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
778 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
779 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
780 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
781 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
782 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
783 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
784 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
785 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
786 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
787 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
788 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
789 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
790 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
791 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
792 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
793 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
794 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
795};
796
797static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
798 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
799 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
800
801 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
802 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
803 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
804
805 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
806 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
807
808 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
809 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
810
811 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
812 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
813
814 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
815 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
816 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
817
818 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
819 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
820
821 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
822 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
823 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
824
825 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
826 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
827 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
828
829 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
830 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
831
832 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
833 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
834
835 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
836 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
837
838 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
839 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
840
841 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
842 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
843
844 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
845 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
846
847 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
848 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
849
850 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
851 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
852 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
853
854 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
855 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
856 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
857
858 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
859 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
860 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
861
862 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
863 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
864
865 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
866 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
867
868 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
869 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
870
871 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
872 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
873
874 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
875 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
876
877 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
878 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
879
880 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
881 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
882
883 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
884 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
885
886 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
887 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
888 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
889
890 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
891 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
892};
893
894static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
895 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
896 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
897 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
898 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
899 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
901 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
902};
903
904static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
905 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
906 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
907};
908
909static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
910 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
911 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
912 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
913 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
914 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
915 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
916 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
917 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
918 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
919 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
920 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
921 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
922 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
923 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
924 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
925 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
926 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
927 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
928};
929
930static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
931 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
932 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
933};
934
935static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
936 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
937 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
938 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
939 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
940 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
941 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
942 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
943 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
944 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
945 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
946 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
947 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
948 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
949};
950
951static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
952 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
953 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
954 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
955 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
956 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
957 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
958 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
959 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
960 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
961 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
962 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
963 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
964};
965
966static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
967 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
968 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
969 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
970 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
971 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
972};
973
974static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
975 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
976 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
977 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
978 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
979 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
980 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
981 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
982 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
983 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
984 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
985 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
986 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
987 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
988 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
989 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
990 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
991 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
992 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
993 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
994 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
995 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
996 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
997 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
998 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
999 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1000 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1001 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1002 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1003 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1004 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1005 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1006 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1007 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1008 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1009 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1010 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1011 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1012 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1013 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1014 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1015 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1016 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1017 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1018 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1019 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1020 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1021 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1022 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1023 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1024 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1025 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1026 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1027 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1028 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1029 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1030 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1031 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1032 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1033 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1034 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1035 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1036 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1037 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1038 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1039 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1040 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1041 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1042 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1043 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1044 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1045 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1046 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1047 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1048 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1049 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1050 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1051 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1052 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1053 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1054 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1055 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1056 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1057 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1058 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1059 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1060 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1061 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1062 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1063 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1064 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1065 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1066 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1067 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1068};
1069
1070static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1071 int mux, u32 *loc, u32 *reg, u32 *value)
1072{
1073 struct rockchip_pinctrl *info = bank->drvdata;
1074 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1075 struct rockchip_mux_route_data *data;
1076 int i;
1077
1078 for (i = 0; i < ctrl->niomux_routes; i++) {
1079 data = &ctrl->iomux_routes[i];
1080 if ((data->bank_num == bank->bank_num) &&
1081 (data->pin == pin) && (data->func == mux))
1082 break;
1083 }
1084
1085 if (i >= ctrl->niomux_routes)
1086 return false;
1087
1088 *loc = data->route_location;
1089 *reg = data->route_offset;
1090 *value = data->route_val;
1091
1092 return true;
1093}
1094
1095static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1096{
1097 struct rockchip_pinctrl *info = bank->drvdata;
1098 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1099 int iomux_num = (pin / 8);
1100 struct regmap *regmap;
1101 unsigned int val;
1102 int reg, ret, mask, mux_type;
1103 u8 bit;
1104
1105 if (iomux_num > 3)
1106 return -EINVAL;
1107
1108 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1109 dev_err(info->dev, "pin %d is unrouted\n", pin);
1110 return -EINVAL;
1111 }
1112
1113 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1114 return RK_FUNC_GPIO;
1115
1116 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1117 regmap = info->regmap_pmu;
1118 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1119 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1120 else
1121 regmap = info->regmap_base;
1122
1123 /* get basic quadrupel of mux registers and the correct reg inside */
1124 mux_type = bank->iomux[iomux_num].type;
1125 reg = bank->iomux[iomux_num].offset;
1126 if (mux_type & IOMUX_WIDTH_4BIT) {
1127 if ((pin % 8) >= 4)
1128 reg += 0x4;
1129 bit = (pin % 4) * 4;
1130 mask = 0xf;
1131 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1132 if ((pin % 8) >= 5)
1133 reg += 0x4;
1134 bit = (pin % 8 % 5) * 3;
1135 mask = 0x7;
1136 } else {
1137 bit = (pin % 8) * 2;
1138 mask = 0x3;
1139 }
1140
1141 if (bank->recalced_mask & BIT(pin))
1142 rockchip_get_recalced_mux(bank, pin, reg: &reg, bit: &bit, mask: &mask);
1143
1144 if (ctrl->type == RK3576) {
1145 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1146 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1147 }
1148
1149 if (ctrl->type == RK3588) {
1150 if (bank->bank_num == 0) {
1151 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1152 u32 reg0 = 0;
1153
1154 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1155 ret = regmap_read(map: regmap, reg: reg0, val: &val);
1156 if (ret)
1157 return ret;
1158
1159 if (!(val & BIT(8)))
1160 return ((val >> bit) & mask);
1161
1162 reg = reg + 0x8000; /* BUS_IOC_BASE */
1163 regmap = info->regmap_base;
1164 }
1165 } else if (bank->bank_num > 0) {
1166 reg += 0x8000; /* BUS_IOC_BASE */
1167 }
1168 }
1169
1170 ret = regmap_read(map: regmap, reg, val: &val);
1171 if (ret)
1172 return ret;
1173
1174 return ((val >> bit) & mask);
1175}
1176
1177static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1178 int pin, int mux)
1179{
1180 struct rockchip_pinctrl *info = bank->drvdata;
1181 struct device *dev = info->dev;
1182 int iomux_num = (pin / 8);
1183
1184 if (iomux_num > 3)
1185 return -EINVAL;
1186
1187 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1188 dev_err(dev, "pin %d is unrouted\n", pin);
1189 return -EINVAL;
1190 }
1191
1192 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1193 if (mux != RK_FUNC_GPIO) {
1194 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1195 return -ENOTSUPP;
1196 }
1197 }
1198
1199 return 0;
1200}
1201
1202/*
1203 * Set a new mux function for a pin.
1204 *
1205 * The register is divided into the upper and lower 16 bit. When changing
1206 * a value, the previous register value is not read and changed. Instead
1207 * it seems the changed bits are marked in the upper 16 bit, while the
1208 * changed value gets set in the same offset in the lower 16 bit.
1209 * All pin settings seem to be 2 bit wide in both the upper and lower
1210 * parts.
1211 * @bank: pin bank to change
1212 * @pin: pin to change
1213 * @mux: new mux function to set
1214 */
1215static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1216{
1217 struct rockchip_pinctrl *info = bank->drvdata;
1218 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1219 struct device *dev = info->dev;
1220 int iomux_num = (pin / 8);
1221 struct regmap *regmap;
1222 int reg, ret, mask, mux_type;
1223 u8 bit;
1224 u32 data, rmask, route_location, route_reg, route_val;
1225
1226 ret = rockchip_verify_mux(bank, pin, mux);
1227 if (ret < 0)
1228 return ret;
1229
1230 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1231 return 0;
1232
1233 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1234
1235 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1236 regmap = info->regmap_pmu;
1237 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1238 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1239 else
1240 regmap = info->regmap_base;
1241
1242 /* get basic quadrupel of mux registers and the correct reg inside */
1243 mux_type = bank->iomux[iomux_num].type;
1244 reg = bank->iomux[iomux_num].offset;
1245 if (mux_type & IOMUX_WIDTH_4BIT) {
1246 if ((pin % 8) >= 4)
1247 reg += 0x4;
1248 bit = (pin % 4) * 4;
1249 mask = 0xf;
1250 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1251 if ((pin % 8) >= 5)
1252 reg += 0x4;
1253 bit = (pin % 8 % 5) * 3;
1254 mask = 0x7;
1255 } else {
1256 bit = (pin % 8) * 2;
1257 mask = 0x3;
1258 }
1259
1260 if (bank->recalced_mask & BIT(pin))
1261 rockchip_get_recalced_mux(bank, pin, reg: &reg, bit: &bit, mask: &mask);
1262
1263 if (ctrl->type == RK3576) {
1264 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1265 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1266 }
1267
1268 if (ctrl->type == RK3588) {
1269 if (bank->bank_num == 0) {
1270 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1271 if (mux < 8) {
1272 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1273 data = (mask << (bit + 16));
1274 rmask = data | (data >> 16);
1275 data |= (mux & mask) << bit;
1276 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
1277 } else {
1278 u32 reg0 = 0;
1279
1280 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1281 data = (mask << (bit + 16));
1282 rmask = data | (data >> 16);
1283 data |= 8 << bit;
1284 ret = regmap_update_bits(map: regmap, reg: reg0, mask: rmask, val: data);
1285
1286 reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1287 data = (mask << (bit + 16));
1288 rmask = data | (data >> 16);
1289 data |= mux << bit;
1290 regmap = info->regmap_base;
1291 ret |= regmap_update_bits(map: regmap, reg: reg0, mask: rmask, val: data);
1292 }
1293 } else {
1294 data = (mask << (bit + 16));
1295 rmask = data | (data >> 16);
1296 data |= (mux & mask) << bit;
1297 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
1298 }
1299 return ret;
1300 } else if (bank->bank_num > 0) {
1301 reg += 0x8000; /* BUS_IOC_BASE */
1302 }
1303 }
1304
1305 if (mux > mask)
1306 return -EINVAL;
1307
1308 if (bank->route_mask & BIT(pin)) {
1309 if (rockchip_get_mux_route(bank, pin, mux, loc: &route_location,
1310 reg: &route_reg, value: &route_val)) {
1311 struct regmap *route_regmap = regmap;
1312
1313 /* handle special locations */
1314 switch (route_location) {
1315 case ROCKCHIP_ROUTE_PMU:
1316 route_regmap = info->regmap_pmu;
1317 break;
1318 case ROCKCHIP_ROUTE_GRF:
1319 route_regmap = info->regmap_base;
1320 break;
1321 }
1322
1323 ret = regmap_write(map: route_regmap, reg: route_reg, val: route_val);
1324 if (ret)
1325 return ret;
1326 }
1327 }
1328
1329 data = (mask << (bit + 16));
1330 rmask = data | (data >> 16);
1331 data |= (mux & mask) << bit;
1332 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
1333
1334 return ret;
1335}
1336
1337#define PX30_PULL_PMU_OFFSET 0x10
1338#define PX30_PULL_GRF_OFFSET 0x60
1339#define PX30_PULL_BITS_PER_PIN 2
1340#define PX30_PULL_PINS_PER_REG 8
1341#define PX30_PULL_BANK_STRIDE 16
1342
1343static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1344 int pin_num, struct regmap **regmap,
1345 int *reg, u8 *bit)
1346{
1347 struct rockchip_pinctrl *info = bank->drvdata;
1348
1349 /* The first 32 pins of the first bank are located in PMU */
1350 if (bank->bank_num == 0) {
1351 *regmap = info->regmap_pmu;
1352 *reg = PX30_PULL_PMU_OFFSET;
1353 } else {
1354 *regmap = info->regmap_base;
1355 *reg = PX30_PULL_GRF_OFFSET;
1356
1357 /* correct the offset, as we're starting with the 2nd bank */
1358 *reg -= 0x10;
1359 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1360 }
1361
1362 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1363 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1364 *bit *= PX30_PULL_BITS_PER_PIN;
1365
1366 return 0;
1367}
1368
1369#define PX30_DRV_PMU_OFFSET 0x20
1370#define PX30_DRV_GRF_OFFSET 0xf0
1371#define PX30_DRV_BITS_PER_PIN 2
1372#define PX30_DRV_PINS_PER_REG 8
1373#define PX30_DRV_BANK_STRIDE 16
1374
1375static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1376 int pin_num, struct regmap **regmap,
1377 int *reg, u8 *bit)
1378{
1379 struct rockchip_pinctrl *info = bank->drvdata;
1380
1381 /* The first 32 pins of the first bank are located in PMU */
1382 if (bank->bank_num == 0) {
1383 *regmap = info->regmap_pmu;
1384 *reg = PX30_DRV_PMU_OFFSET;
1385 } else {
1386 *regmap = info->regmap_base;
1387 *reg = PX30_DRV_GRF_OFFSET;
1388
1389 /* correct the offset, as we're starting with the 2nd bank */
1390 *reg -= 0x10;
1391 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1392 }
1393
1394 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1395 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1396 *bit *= PX30_DRV_BITS_PER_PIN;
1397
1398 return 0;
1399}
1400
1401#define PX30_SCHMITT_PMU_OFFSET 0x38
1402#define PX30_SCHMITT_GRF_OFFSET 0xc0
1403#define PX30_SCHMITT_PINS_PER_PMU_REG 16
1404#define PX30_SCHMITT_BANK_STRIDE 16
1405#define PX30_SCHMITT_PINS_PER_GRF_REG 8
1406
1407static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1408 int pin_num,
1409 struct regmap **regmap,
1410 int *reg, u8 *bit)
1411{
1412 struct rockchip_pinctrl *info = bank->drvdata;
1413 int pins_per_reg;
1414
1415 if (bank->bank_num == 0) {
1416 *regmap = info->regmap_pmu;
1417 *reg = PX30_SCHMITT_PMU_OFFSET;
1418 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1419 } else {
1420 *regmap = info->regmap_base;
1421 *reg = PX30_SCHMITT_GRF_OFFSET;
1422 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1423 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1424 }
1425
1426 *reg += ((pin_num / pins_per_reg) * 4);
1427 *bit = pin_num % pins_per_reg;
1428
1429 return 0;
1430}
1431
1432#define RV1108_PULL_PMU_OFFSET 0x10
1433#define RV1108_PULL_OFFSET 0x110
1434#define RV1108_PULL_PINS_PER_REG 8
1435#define RV1108_PULL_BITS_PER_PIN 2
1436#define RV1108_PULL_BANK_STRIDE 16
1437
1438static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1439 int pin_num, struct regmap **regmap,
1440 int *reg, u8 *bit)
1441{
1442 struct rockchip_pinctrl *info = bank->drvdata;
1443
1444 /* The first 24 pins of the first bank are located in PMU */
1445 if (bank->bank_num == 0) {
1446 *regmap = info->regmap_pmu;
1447 *reg = RV1108_PULL_PMU_OFFSET;
1448 } else {
1449 *reg = RV1108_PULL_OFFSET;
1450 *regmap = info->regmap_base;
1451 /* correct the offset, as we're starting with the 2nd bank */
1452 *reg -= 0x10;
1453 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1454 }
1455
1456 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1457 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1458 *bit *= RV1108_PULL_BITS_PER_PIN;
1459
1460 return 0;
1461}
1462
1463#define RV1108_DRV_PMU_OFFSET 0x20
1464#define RV1108_DRV_GRF_OFFSET 0x210
1465#define RV1108_DRV_BITS_PER_PIN 2
1466#define RV1108_DRV_PINS_PER_REG 8
1467#define RV1108_DRV_BANK_STRIDE 16
1468
1469static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1470 int pin_num, struct regmap **regmap,
1471 int *reg, u8 *bit)
1472{
1473 struct rockchip_pinctrl *info = bank->drvdata;
1474
1475 /* The first 24 pins of the first bank are located in PMU */
1476 if (bank->bank_num == 0) {
1477 *regmap = info->regmap_pmu;
1478 *reg = RV1108_DRV_PMU_OFFSET;
1479 } else {
1480 *regmap = info->regmap_base;
1481 *reg = RV1108_DRV_GRF_OFFSET;
1482
1483 /* correct the offset, as we're starting with the 2nd bank */
1484 *reg -= 0x10;
1485 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1486 }
1487
1488 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1489 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1490 *bit *= RV1108_DRV_BITS_PER_PIN;
1491
1492 return 0;
1493}
1494
1495#define RV1108_SCHMITT_PMU_OFFSET 0x30
1496#define RV1108_SCHMITT_GRF_OFFSET 0x388
1497#define RV1108_SCHMITT_BANK_STRIDE 8
1498#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1499#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1500
1501static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1502 int pin_num,
1503 struct regmap **regmap,
1504 int *reg, u8 *bit)
1505{
1506 struct rockchip_pinctrl *info = bank->drvdata;
1507 int pins_per_reg;
1508
1509 if (bank->bank_num == 0) {
1510 *regmap = info->regmap_pmu;
1511 *reg = RV1108_SCHMITT_PMU_OFFSET;
1512 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1513 } else {
1514 *regmap = info->regmap_base;
1515 *reg = RV1108_SCHMITT_GRF_OFFSET;
1516 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1517 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1518 }
1519 *reg += ((pin_num / pins_per_reg) * 4);
1520 *bit = pin_num % pins_per_reg;
1521
1522 return 0;
1523}
1524
1525#define RV1126_PULL_PMU_OFFSET 0x40
1526#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1527#define RV1126_PULL_PINS_PER_REG 8
1528#define RV1126_PULL_BITS_PER_PIN 2
1529#define RV1126_PULL_BANK_STRIDE 16
1530#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1531
1532static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1533 int pin_num, struct regmap **regmap,
1534 int *reg, u8 *bit)
1535{
1536 struct rockchip_pinctrl *info = bank->drvdata;
1537
1538 /* The first 24 pins of the first bank are located in PMU */
1539 if (bank->bank_num == 0) {
1540 if (RV1126_GPIO_C4_D7(pin_num)) {
1541 *regmap = info->regmap_base;
1542 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1543 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1544 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1545 *bit *= RV1126_PULL_BITS_PER_PIN;
1546 return 0;
1547 }
1548 *regmap = info->regmap_pmu;
1549 *reg = RV1126_PULL_PMU_OFFSET;
1550 } else {
1551 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1552 *regmap = info->regmap_base;
1553 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1554 }
1555
1556 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1557 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1558 *bit *= RV1126_PULL_BITS_PER_PIN;
1559
1560 return 0;
1561}
1562
1563#define RV1126_DRV_PMU_OFFSET 0x20
1564#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1565#define RV1126_DRV_BITS_PER_PIN 4
1566#define RV1126_DRV_PINS_PER_REG 4
1567#define RV1126_DRV_BANK_STRIDE 32
1568
1569static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1570 int pin_num, struct regmap **regmap,
1571 int *reg, u8 *bit)
1572{
1573 struct rockchip_pinctrl *info = bank->drvdata;
1574
1575 /* The first 24 pins of the first bank are located in PMU */
1576 if (bank->bank_num == 0) {
1577 if (RV1126_GPIO_C4_D7(pin_num)) {
1578 *regmap = info->regmap_base;
1579 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1580 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1581 *reg -= 0x4;
1582 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1583 *bit *= RV1126_DRV_BITS_PER_PIN;
1584 return 0;
1585 }
1586 *regmap = info->regmap_pmu;
1587 *reg = RV1126_DRV_PMU_OFFSET;
1588 } else {
1589 *regmap = info->regmap_base;
1590 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1591 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1592 }
1593
1594 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1595 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1596 *bit *= RV1126_DRV_BITS_PER_PIN;
1597
1598 return 0;
1599}
1600
1601#define RV1126_SCHMITT_PMU_OFFSET 0x60
1602#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1603#define RV1126_SCHMITT_BANK_STRIDE 16
1604#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
1605#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
1606
1607static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1608 int pin_num,
1609 struct regmap **regmap,
1610 int *reg, u8 *bit)
1611{
1612 struct rockchip_pinctrl *info = bank->drvdata;
1613 int pins_per_reg;
1614
1615 if (bank->bank_num == 0) {
1616 if (RV1126_GPIO_C4_D7(pin_num)) {
1617 *regmap = info->regmap_base;
1618 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1619 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1620 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1621 return 0;
1622 }
1623 *regmap = info->regmap_pmu;
1624 *reg = RV1126_SCHMITT_PMU_OFFSET;
1625 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1626 } else {
1627 *regmap = info->regmap_base;
1628 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1629 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1630 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1631 }
1632 *reg += ((pin_num / pins_per_reg) * 4);
1633 *bit = pin_num % pins_per_reg;
1634
1635 return 0;
1636}
1637
1638#define RK3308_SCHMITT_PINS_PER_REG 8
1639#define RK3308_SCHMITT_BANK_STRIDE 16
1640#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1641
1642static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1643 int pin_num, struct regmap **regmap,
1644 int *reg, u8 *bit)
1645{
1646 struct rockchip_pinctrl *info = bank->drvdata;
1647
1648 *regmap = info->regmap_base;
1649 *reg = RK3308_SCHMITT_GRF_OFFSET;
1650
1651 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1652 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1653 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1654
1655 return 0;
1656}
1657
1658#define RK2928_PULL_OFFSET 0x118
1659#define RK2928_PULL_PINS_PER_REG 16
1660#define RK2928_PULL_BANK_STRIDE 8
1661
1662static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1663 int pin_num, struct regmap **regmap,
1664 int *reg, u8 *bit)
1665{
1666 struct rockchip_pinctrl *info = bank->drvdata;
1667
1668 *regmap = info->regmap_base;
1669 *reg = RK2928_PULL_OFFSET;
1670 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1671 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1672
1673 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1674
1675 return 0;
1676};
1677
1678#define RK3128_PULL_OFFSET 0x118
1679
1680static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1681 int pin_num, struct regmap **regmap,
1682 int *reg, u8 *bit)
1683{
1684 struct rockchip_pinctrl *info = bank->drvdata;
1685
1686 *regmap = info->regmap_base;
1687 *reg = RK3128_PULL_OFFSET;
1688 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1689 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1690
1691 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1692
1693 return 0;
1694}
1695
1696#define RK3188_PULL_OFFSET 0x164
1697#define RK3188_PULL_BITS_PER_PIN 2
1698#define RK3188_PULL_PINS_PER_REG 8
1699#define RK3188_PULL_BANK_STRIDE 16
1700#define RK3188_PULL_PMU_OFFSET 0x64
1701
1702static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1703 int pin_num, struct regmap **regmap,
1704 int *reg, u8 *bit)
1705{
1706 struct rockchip_pinctrl *info = bank->drvdata;
1707
1708 /* The first 12 pins of the first bank are located elsewhere */
1709 if (bank->bank_num == 0 && pin_num < 12) {
1710 *regmap = info->regmap_pmu ? info->regmap_pmu
1711 : bank->regmap_pull;
1712 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1713 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1714 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1715 *bit *= RK3188_PULL_BITS_PER_PIN;
1716 } else {
1717 *regmap = info->regmap_pull ? info->regmap_pull
1718 : info->regmap_base;
1719 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1720
1721 /* correct the offset, as it is the 2nd pull register */
1722 *reg -= 4;
1723 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1724 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1725
1726 /*
1727 * The bits in these registers have an inverse ordering
1728 * with the lowest pin being in bits 15:14 and the highest
1729 * pin in bits 1:0
1730 */
1731 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1732 *bit *= RK3188_PULL_BITS_PER_PIN;
1733 }
1734
1735 return 0;
1736}
1737
1738#define RK3288_PULL_OFFSET 0x140
1739static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1740 int pin_num, struct regmap **regmap,
1741 int *reg, u8 *bit)
1742{
1743 struct rockchip_pinctrl *info = bank->drvdata;
1744
1745 /* The first 24 pins of the first bank are located in PMU */
1746 if (bank->bank_num == 0) {
1747 *regmap = info->regmap_pmu;
1748 *reg = RK3188_PULL_PMU_OFFSET;
1749
1750 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1751 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1752 *bit *= RK3188_PULL_BITS_PER_PIN;
1753 } else {
1754 *regmap = info->regmap_base;
1755 *reg = RK3288_PULL_OFFSET;
1756
1757 /* correct the offset, as we're starting with the 2nd bank */
1758 *reg -= 0x10;
1759 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1760 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1761
1762 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1763 *bit *= RK3188_PULL_BITS_PER_PIN;
1764 }
1765
1766 return 0;
1767}
1768
1769#define RK3288_DRV_PMU_OFFSET 0x70
1770#define RK3288_DRV_GRF_OFFSET 0x1c0
1771#define RK3288_DRV_BITS_PER_PIN 2
1772#define RK3288_DRV_PINS_PER_REG 8
1773#define RK3288_DRV_BANK_STRIDE 16
1774
1775static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1776 int pin_num, struct regmap **regmap,
1777 int *reg, u8 *bit)
1778{
1779 struct rockchip_pinctrl *info = bank->drvdata;
1780
1781 /* The first 24 pins of the first bank are located in PMU */
1782 if (bank->bank_num == 0) {
1783 *regmap = info->regmap_pmu;
1784 *reg = RK3288_DRV_PMU_OFFSET;
1785
1786 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1787 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1788 *bit *= RK3288_DRV_BITS_PER_PIN;
1789 } else {
1790 *regmap = info->regmap_base;
1791 *reg = RK3288_DRV_GRF_OFFSET;
1792
1793 /* correct the offset, as we're starting with the 2nd bank */
1794 *reg -= 0x10;
1795 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1796 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1797
1798 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1799 *bit *= RK3288_DRV_BITS_PER_PIN;
1800 }
1801
1802 return 0;
1803}
1804
1805#define RK3228_PULL_OFFSET 0x100
1806
1807static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1808 int pin_num, struct regmap **regmap,
1809 int *reg, u8 *bit)
1810{
1811 struct rockchip_pinctrl *info = bank->drvdata;
1812
1813 *regmap = info->regmap_base;
1814 *reg = RK3228_PULL_OFFSET;
1815 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1816 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1817
1818 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1819 *bit *= RK3188_PULL_BITS_PER_PIN;
1820
1821 return 0;
1822}
1823
1824#define RK3228_DRV_GRF_OFFSET 0x200
1825
1826static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1827 int pin_num, struct regmap **regmap,
1828 int *reg, u8 *bit)
1829{
1830 struct rockchip_pinctrl *info = bank->drvdata;
1831
1832 *regmap = info->regmap_base;
1833 *reg = RK3228_DRV_GRF_OFFSET;
1834 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1835 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1836
1837 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1838 *bit *= RK3288_DRV_BITS_PER_PIN;
1839
1840 return 0;
1841}
1842
1843#define RK3308_PULL_OFFSET 0xa0
1844
1845static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1846 int pin_num, struct regmap **regmap,
1847 int *reg, u8 *bit)
1848{
1849 struct rockchip_pinctrl *info = bank->drvdata;
1850
1851 *regmap = info->regmap_base;
1852 *reg = RK3308_PULL_OFFSET;
1853 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1854 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1855
1856 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1857 *bit *= RK3188_PULL_BITS_PER_PIN;
1858
1859 return 0;
1860}
1861
1862#define RK3308_DRV_GRF_OFFSET 0x100
1863
1864static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1865 int pin_num, struct regmap **regmap,
1866 int *reg, u8 *bit)
1867{
1868 struct rockchip_pinctrl *info = bank->drvdata;
1869
1870 *regmap = info->regmap_base;
1871 *reg = RK3308_DRV_GRF_OFFSET;
1872 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1873 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1874
1875 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1876 *bit *= RK3288_DRV_BITS_PER_PIN;
1877
1878 return 0;
1879}
1880
1881#define RK3368_PULL_GRF_OFFSET 0x100
1882#define RK3368_PULL_PMU_OFFSET 0x10
1883
1884static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1885 int pin_num, struct regmap **regmap,
1886 int *reg, u8 *bit)
1887{
1888 struct rockchip_pinctrl *info = bank->drvdata;
1889
1890 /* The first 32 pins of the first bank are located in PMU */
1891 if (bank->bank_num == 0) {
1892 *regmap = info->regmap_pmu;
1893 *reg = RK3368_PULL_PMU_OFFSET;
1894
1895 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1896 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1897 *bit *= RK3188_PULL_BITS_PER_PIN;
1898 } else {
1899 *regmap = info->regmap_base;
1900 *reg = RK3368_PULL_GRF_OFFSET;
1901
1902 /* correct the offset, as we're starting with the 2nd bank */
1903 *reg -= 0x10;
1904 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1905 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1906
1907 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1908 *bit *= RK3188_PULL_BITS_PER_PIN;
1909 }
1910
1911 return 0;
1912}
1913
1914#define RK3368_DRV_PMU_OFFSET 0x20
1915#define RK3368_DRV_GRF_OFFSET 0x200
1916
1917static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1918 int pin_num, struct regmap **regmap,
1919 int *reg, u8 *bit)
1920{
1921 struct rockchip_pinctrl *info = bank->drvdata;
1922
1923 /* The first 32 pins of the first bank are located in PMU */
1924 if (bank->bank_num == 0) {
1925 *regmap = info->regmap_pmu;
1926 *reg = RK3368_DRV_PMU_OFFSET;
1927
1928 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1929 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1930 *bit *= RK3288_DRV_BITS_PER_PIN;
1931 } else {
1932 *regmap = info->regmap_base;
1933 *reg = RK3368_DRV_GRF_OFFSET;
1934
1935 /* correct the offset, as we're starting with the 2nd bank */
1936 *reg -= 0x10;
1937 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1938 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1939
1940 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1941 *bit *= RK3288_DRV_BITS_PER_PIN;
1942 }
1943
1944 return 0;
1945}
1946
1947#define RK3399_PULL_GRF_OFFSET 0xe040
1948#define RK3399_PULL_PMU_OFFSET 0x40
1949#define RK3399_DRV_3BITS_PER_PIN 3
1950
1951static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1952 int pin_num, struct regmap **regmap,
1953 int *reg, u8 *bit)
1954{
1955 struct rockchip_pinctrl *info = bank->drvdata;
1956
1957 /* The bank0:16 and bank1:32 pins are located in PMU */
1958 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1959 *regmap = info->regmap_pmu;
1960 *reg = RK3399_PULL_PMU_OFFSET;
1961
1962 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1963
1964 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1965 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1966 *bit *= RK3188_PULL_BITS_PER_PIN;
1967 } else {
1968 *regmap = info->regmap_base;
1969 *reg = RK3399_PULL_GRF_OFFSET;
1970
1971 /* correct the offset, as we're starting with the 3rd bank */
1972 *reg -= 0x20;
1973 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1974 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1975
1976 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1977 *bit *= RK3188_PULL_BITS_PER_PIN;
1978 }
1979
1980 return 0;
1981}
1982
1983static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1984 int pin_num, struct regmap **regmap,
1985 int *reg, u8 *bit)
1986{
1987 struct rockchip_pinctrl *info = bank->drvdata;
1988 int drv_num = (pin_num / 8);
1989
1990 /* The bank0:16 and bank1:32 pins are located in PMU */
1991 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1992 *regmap = info->regmap_pmu;
1993 else
1994 *regmap = info->regmap_base;
1995
1996 *reg = bank->drv[drv_num].offset;
1997 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1998 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1999 *bit = (pin_num % 8) * 3;
2000 else
2001 *bit = (pin_num % 8) * 2;
2002
2003 return 0;
2004}
2005
2006#define RK3528_DRV_BITS_PER_PIN 8
2007#define RK3528_DRV_PINS_PER_REG 2
2008#define RK3528_DRV_GPIO0_OFFSET 0x100
2009#define RK3528_DRV_GPIO1_OFFSET 0x20120
2010#define RK3528_DRV_GPIO2_OFFSET 0x30160
2011#define RK3528_DRV_GPIO3_OFFSET 0x20190
2012#define RK3528_DRV_GPIO4_OFFSET 0x101C0
2013
2014static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2015 int pin_num, struct regmap **regmap,
2016 int *reg, u8 *bit)
2017{
2018 struct rockchip_pinctrl *info = bank->drvdata;
2019
2020 *regmap = info->regmap_base;
2021
2022 if (bank->bank_num == 0)
2023 *reg = RK3528_DRV_GPIO0_OFFSET;
2024 else if (bank->bank_num == 1)
2025 *reg = RK3528_DRV_GPIO1_OFFSET;
2026 else if (bank->bank_num == 2)
2027 *reg = RK3528_DRV_GPIO2_OFFSET;
2028 else if (bank->bank_num == 3)
2029 *reg = RK3528_DRV_GPIO3_OFFSET;
2030 else if (bank->bank_num == 4)
2031 *reg = RK3528_DRV_GPIO4_OFFSET;
2032 else
2033 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2034
2035 *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
2036 *bit = pin_num % RK3528_DRV_PINS_PER_REG;
2037 *bit *= RK3528_DRV_BITS_PER_PIN;
2038
2039 return 0;
2040}
2041
2042#define RK3528_PULL_BITS_PER_PIN 2
2043#define RK3528_PULL_PINS_PER_REG 8
2044#define RK3528_PULL_GPIO0_OFFSET 0x200
2045#define RK3528_PULL_GPIO1_OFFSET 0x20210
2046#define RK3528_PULL_GPIO2_OFFSET 0x30220
2047#define RK3528_PULL_GPIO3_OFFSET 0x20230
2048#define RK3528_PULL_GPIO4_OFFSET 0x10240
2049
2050static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2051 int pin_num, struct regmap **regmap,
2052 int *reg, u8 *bit)
2053{
2054 struct rockchip_pinctrl *info = bank->drvdata;
2055
2056 *regmap = info->regmap_base;
2057
2058 if (bank->bank_num == 0)
2059 *reg = RK3528_PULL_GPIO0_OFFSET;
2060 else if (bank->bank_num == 1)
2061 *reg = RK3528_PULL_GPIO1_OFFSET;
2062 else if (bank->bank_num == 2)
2063 *reg = RK3528_PULL_GPIO2_OFFSET;
2064 else if (bank->bank_num == 3)
2065 *reg = RK3528_PULL_GPIO3_OFFSET;
2066 else if (bank->bank_num == 4)
2067 *reg = RK3528_PULL_GPIO4_OFFSET;
2068 else
2069 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2070
2071 *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
2072 *bit = pin_num % RK3528_PULL_PINS_PER_REG;
2073 *bit *= RK3528_PULL_BITS_PER_PIN;
2074
2075 return 0;
2076}
2077
2078#define RK3528_SMT_BITS_PER_PIN 1
2079#define RK3528_SMT_PINS_PER_REG 8
2080#define RK3528_SMT_GPIO0_OFFSET 0x400
2081#define RK3528_SMT_GPIO1_OFFSET 0x20410
2082#define RK3528_SMT_GPIO2_OFFSET 0x30420
2083#define RK3528_SMT_GPIO3_OFFSET 0x20430
2084#define RK3528_SMT_GPIO4_OFFSET 0x10440
2085
2086static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2087 int pin_num,
2088 struct regmap **regmap,
2089 int *reg, u8 *bit)
2090{
2091 struct rockchip_pinctrl *info = bank->drvdata;
2092
2093 *regmap = info->regmap_base;
2094
2095 if (bank->bank_num == 0)
2096 *reg = RK3528_SMT_GPIO0_OFFSET;
2097 else if (bank->bank_num == 1)
2098 *reg = RK3528_SMT_GPIO1_OFFSET;
2099 else if (bank->bank_num == 2)
2100 *reg = RK3528_SMT_GPIO2_OFFSET;
2101 else if (bank->bank_num == 3)
2102 *reg = RK3528_SMT_GPIO3_OFFSET;
2103 else if (bank->bank_num == 4)
2104 *reg = RK3528_SMT_GPIO4_OFFSET;
2105 else
2106 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2107
2108 *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
2109 *bit = pin_num % RK3528_SMT_PINS_PER_REG;
2110 *bit *= RK3528_SMT_BITS_PER_PIN;
2111
2112 return 0;
2113}
2114
2115#define RK3562_DRV_BITS_PER_PIN 8
2116#define RK3562_DRV_PINS_PER_REG 2
2117#define RK3562_DRV_GPIO0_OFFSET 0x20070
2118#define RK3562_DRV_GPIO1_OFFSET 0x200
2119#define RK3562_DRV_GPIO2_OFFSET 0x240
2120#define RK3562_DRV_GPIO3_OFFSET 0x10280
2121#define RK3562_DRV_GPIO4_OFFSET 0x102C0
2122
2123static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2124 int pin_num, struct regmap **regmap,
2125 int *reg, u8 *bit)
2126{
2127 struct rockchip_pinctrl *info = bank->drvdata;
2128
2129 *regmap = info->regmap_base;
2130 switch (bank->bank_num) {
2131 case 0:
2132 *reg = RK3562_DRV_GPIO0_OFFSET;
2133 break;
2134
2135 case 1:
2136 *reg = RK3562_DRV_GPIO1_OFFSET;
2137 break;
2138
2139 case 2:
2140 *reg = RK3562_DRV_GPIO2_OFFSET;
2141 break;
2142
2143 case 3:
2144 *reg = RK3562_DRV_GPIO3_OFFSET;
2145 break;
2146
2147 case 4:
2148 *reg = RK3562_DRV_GPIO4_OFFSET;
2149 break;
2150
2151 default:
2152 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2153 break;
2154 }
2155
2156 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
2157 *bit = pin_num % RK3562_DRV_PINS_PER_REG;
2158 *bit *= RK3562_DRV_BITS_PER_PIN;
2159
2160 return 0;
2161}
2162
2163#define RK3562_PULL_BITS_PER_PIN 2
2164#define RK3562_PULL_PINS_PER_REG 8
2165#define RK3562_PULL_GPIO0_OFFSET 0x20020
2166#define RK3562_PULL_GPIO1_OFFSET 0x80
2167#define RK3562_PULL_GPIO2_OFFSET 0x90
2168#define RK3562_PULL_GPIO3_OFFSET 0x100A0
2169#define RK3562_PULL_GPIO4_OFFSET 0x100B0
2170
2171static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2172 int pin_num, struct regmap **regmap,
2173 int *reg, u8 *bit)
2174{
2175 struct rockchip_pinctrl *info = bank->drvdata;
2176
2177 *regmap = info->regmap_base;
2178 switch (bank->bank_num) {
2179 case 0:
2180 *reg = RK3562_PULL_GPIO0_OFFSET;
2181 break;
2182
2183 case 1:
2184 *reg = RK3562_PULL_GPIO1_OFFSET;
2185 break;
2186
2187 case 2:
2188 *reg = RK3562_PULL_GPIO2_OFFSET;
2189 break;
2190
2191 case 3:
2192 *reg = RK3562_PULL_GPIO3_OFFSET;
2193 break;
2194
2195 case 4:
2196 *reg = RK3562_PULL_GPIO4_OFFSET;
2197 break;
2198
2199 default:
2200 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2201 break;
2202 }
2203
2204 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
2205 *bit = pin_num % RK3562_PULL_PINS_PER_REG;
2206 *bit *= RK3562_PULL_BITS_PER_PIN;
2207
2208 return 0;
2209}
2210
2211#define RK3562_SMT_BITS_PER_PIN 2
2212#define RK3562_SMT_PINS_PER_REG 8
2213#define RK3562_SMT_GPIO0_OFFSET 0x20030
2214#define RK3562_SMT_GPIO1_OFFSET 0xC0
2215#define RK3562_SMT_GPIO2_OFFSET 0xD0
2216#define RK3562_SMT_GPIO3_OFFSET 0x100E0
2217#define RK3562_SMT_GPIO4_OFFSET 0x100F0
2218
2219static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2220 int pin_num,
2221 struct regmap **regmap,
2222 int *reg, u8 *bit)
2223{
2224 struct rockchip_pinctrl *info = bank->drvdata;
2225
2226 *regmap = info->regmap_base;
2227 switch (bank->bank_num) {
2228 case 0:
2229 *reg = RK3562_SMT_GPIO0_OFFSET;
2230 break;
2231
2232 case 1:
2233 *reg = RK3562_SMT_GPIO1_OFFSET;
2234 break;
2235
2236 case 2:
2237 *reg = RK3562_SMT_GPIO2_OFFSET;
2238 break;
2239
2240 case 3:
2241 *reg = RK3562_SMT_GPIO3_OFFSET;
2242 break;
2243
2244 case 4:
2245 *reg = RK3562_SMT_GPIO4_OFFSET;
2246 break;
2247
2248 default:
2249 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2250 break;
2251 }
2252
2253 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
2254 *bit = pin_num % RK3562_SMT_PINS_PER_REG;
2255 *bit *= RK3562_SMT_BITS_PER_PIN;
2256
2257 return 0;
2258}
2259
2260#define RK3568_PULL_PMU_OFFSET 0x20
2261#define RK3568_PULL_GRF_OFFSET 0x80
2262#define RK3568_PULL_BITS_PER_PIN 2
2263#define RK3568_PULL_PINS_PER_REG 8
2264#define RK3568_PULL_BANK_STRIDE 0x10
2265
2266static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2267 int pin_num, struct regmap **regmap,
2268 int *reg, u8 *bit)
2269{
2270 struct rockchip_pinctrl *info = bank->drvdata;
2271
2272 if (bank->bank_num == 0) {
2273 *regmap = info->regmap_pmu;
2274 *reg = RK3568_PULL_PMU_OFFSET;
2275 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2276 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2277
2278 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
2279 *bit *= RK3568_PULL_BITS_PER_PIN;
2280 } else {
2281 *regmap = info->regmap_base;
2282 *reg = RK3568_PULL_GRF_OFFSET;
2283 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2284 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2285
2286 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2287 *bit *= RK3568_PULL_BITS_PER_PIN;
2288 }
2289
2290 return 0;
2291}
2292
2293#define RK3568_DRV_PMU_OFFSET 0x70
2294#define RK3568_DRV_GRF_OFFSET 0x200
2295#define RK3568_DRV_BITS_PER_PIN 8
2296#define RK3568_DRV_PINS_PER_REG 2
2297#define RK3568_DRV_BANK_STRIDE 0x40
2298
2299static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2300 int pin_num, struct regmap **regmap,
2301 int *reg, u8 *bit)
2302{
2303 struct rockchip_pinctrl *info = bank->drvdata;
2304
2305 /* The first 32 pins of the first bank are located in PMU */
2306 if (bank->bank_num == 0) {
2307 *regmap = info->regmap_pmu;
2308 *reg = RK3568_DRV_PMU_OFFSET;
2309 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2310
2311 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
2312 *bit *= RK3568_DRV_BITS_PER_PIN;
2313 } else {
2314 *regmap = info->regmap_base;
2315 *reg = RK3568_DRV_GRF_OFFSET;
2316 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2317 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2318
2319 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2320 *bit *= RK3568_DRV_BITS_PER_PIN;
2321 }
2322
2323 return 0;
2324}
2325
2326#define RK3576_DRV_BITS_PER_PIN 4
2327#define RK3576_DRV_PINS_PER_REG 4
2328#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
2329#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
2330#define RK3576_DRV_GPIO1_OFFSET 0x6020
2331#define RK3576_DRV_GPIO2_OFFSET 0x6040
2332#define RK3576_DRV_GPIO3_OFFSET 0x6060
2333#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
2334#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
2335#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
2336
2337static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2338 int pin_num, struct regmap **regmap,
2339 int *reg, u8 *bit)
2340{
2341 struct rockchip_pinctrl *info = bank->drvdata;
2342
2343 *regmap = info->regmap_base;
2344
2345 if (bank->bank_num == 0 && pin_num < 12)
2346 *reg = RK3576_DRV_GPIO0_AL_OFFSET;
2347 else if (bank->bank_num == 0)
2348 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2349 else if (bank->bank_num == 1)
2350 *reg = RK3576_DRV_GPIO1_OFFSET;
2351 else if (bank->bank_num == 2)
2352 *reg = RK3576_DRV_GPIO2_OFFSET;
2353 else if (bank->bank_num == 3)
2354 *reg = RK3576_DRV_GPIO3_OFFSET;
2355 else if (bank->bank_num == 4 && pin_num < 16)
2356 *reg = RK3576_DRV_GPIO4_AL_OFFSET;
2357 else if (bank->bank_num == 4 && pin_num < 24)
2358 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2359 else if (bank->bank_num == 4)
2360 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2361 else
2362 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2363
2364 *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
2365 *bit = pin_num % RK3576_DRV_PINS_PER_REG;
2366 *bit *= RK3576_DRV_BITS_PER_PIN;
2367
2368 return 0;
2369}
2370
2371#define RK3576_PULL_BITS_PER_PIN 2
2372#define RK3576_PULL_PINS_PER_REG 8
2373#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
2374#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
2375#define RK3576_PULL_GPIO1_OFFSET 0x6110
2376#define RK3576_PULL_GPIO2_OFFSET 0x6120
2377#define RK3576_PULL_GPIO3_OFFSET 0x6130
2378#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
2379#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
2380#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
2381
2382static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2383 int pin_num, struct regmap **regmap,
2384 int *reg, u8 *bit)
2385{
2386 struct rockchip_pinctrl *info = bank->drvdata;
2387
2388 *regmap = info->regmap_base;
2389
2390 if (bank->bank_num == 0 && pin_num < 12)
2391 *reg = RK3576_PULL_GPIO0_AL_OFFSET;
2392 else if (bank->bank_num == 0)
2393 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2394 else if (bank->bank_num == 1)
2395 *reg = RK3576_PULL_GPIO1_OFFSET;
2396 else if (bank->bank_num == 2)
2397 *reg = RK3576_PULL_GPIO2_OFFSET;
2398 else if (bank->bank_num == 3)
2399 *reg = RK3576_PULL_GPIO3_OFFSET;
2400 else if (bank->bank_num == 4 && pin_num < 16)
2401 *reg = RK3576_PULL_GPIO4_AL_OFFSET;
2402 else if (bank->bank_num == 4 && pin_num < 24)
2403 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2404 else if (bank->bank_num == 4)
2405 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2406 else
2407 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2408
2409 *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
2410 *bit = pin_num % RK3576_PULL_PINS_PER_REG;
2411 *bit *= RK3576_PULL_BITS_PER_PIN;
2412
2413 return 0;
2414}
2415
2416#define RK3576_SMT_BITS_PER_PIN 1
2417#define RK3576_SMT_PINS_PER_REG 8
2418#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
2419#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
2420#define RK3576_SMT_GPIO1_OFFSET 0x6210
2421#define RK3576_SMT_GPIO2_OFFSET 0x6220
2422#define RK3576_SMT_GPIO3_OFFSET 0x6230
2423#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
2424#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
2425#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
2426
2427static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2428 int pin_num,
2429 struct regmap **regmap,
2430 int *reg, u8 *bit)
2431{
2432 struct rockchip_pinctrl *info = bank->drvdata;
2433
2434 *regmap = info->regmap_base;
2435
2436 if (bank->bank_num == 0 && pin_num < 12)
2437 *reg = RK3576_SMT_GPIO0_AL_OFFSET;
2438 else if (bank->bank_num == 0)
2439 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2440 else if (bank->bank_num == 1)
2441 *reg = RK3576_SMT_GPIO1_OFFSET;
2442 else if (bank->bank_num == 2)
2443 *reg = RK3576_SMT_GPIO2_OFFSET;
2444 else if (bank->bank_num == 3)
2445 *reg = RK3576_SMT_GPIO3_OFFSET;
2446 else if (bank->bank_num == 4 && pin_num < 16)
2447 *reg = RK3576_SMT_GPIO4_AL_OFFSET;
2448 else if (bank->bank_num == 4 && pin_num < 24)
2449 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
2450 else if (bank->bank_num == 4)
2451 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
2452 else
2453 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2454
2455 *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
2456 *bit = pin_num % RK3576_SMT_PINS_PER_REG;
2457 *bit *= RK3576_SMT_BITS_PER_PIN;
2458
2459 return 0;
2460}
2461
2462#define RK3588_PMU1_IOC_REG (0x0000)
2463#define RK3588_PMU2_IOC_REG (0x4000)
2464#define RK3588_BUS_IOC_REG (0x8000)
2465#define RK3588_VCCIO1_4_IOC_REG (0x9000)
2466#define RK3588_VCCIO3_5_IOC_REG (0xA000)
2467#define RK3588_VCCIO2_IOC_REG (0xB000)
2468#define RK3588_VCCIO6_IOC_REG (0xC000)
2469#define RK3588_EMMC_IOC_REG (0xD000)
2470
2471static const u32 rk3588_ds_regs[][2] = {
2472 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2473 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2474 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2475 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2476 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2477 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2478 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2479 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2480 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2481 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2482 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2483 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2484 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2485 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2486 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2487 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2488 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2489 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2490 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2491 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2492 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2493 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2494 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2495 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2496 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2497 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2498 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2499 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2500 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2501 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2502 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2503 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2504 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2505 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2506 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2507 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2508 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2509 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2510 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2511 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2512 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
2513};
2514
2515static const u32 rk3588_p_regs[][2] = {
2516 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2517 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2518 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2519 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2520 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2521 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2522 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2523 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2524 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2525 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2526 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2527 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2528 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2529 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2530 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2531 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2532 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2533 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2534 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2535 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2536 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2537 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2538 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2539};
2540
2541static const u32 rk3588_smt_regs[][2] = {
2542 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2543 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2544 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2545 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2546 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2547 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2548 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2549 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2550 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2551 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2552 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2553 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2554 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2555 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2556 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2557 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2558 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2559 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2560 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2561 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2562 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2563 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2564 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2565};
2566
2567#define RK3588_PULL_BITS_PER_PIN 2
2568#define RK3588_PULL_PINS_PER_REG 8
2569
2570static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2571 int pin_num, struct regmap **regmap,
2572 int *reg, u8 *bit)
2573{
2574 struct rockchip_pinctrl *info = bank->drvdata;
2575 u8 bank_num = bank->bank_num;
2576 u32 pin = bank_num * 32 + pin_num;
2577 int i;
2578
2579 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
2580 if (pin >= rk3588_p_regs[i][0]) {
2581 *reg = rk3588_p_regs[i][1];
2582 *regmap = info->regmap_base;
2583 *bit = pin_num % RK3588_PULL_PINS_PER_REG;
2584 *bit *= RK3588_PULL_BITS_PER_PIN;
2585 return 0;
2586 }
2587 }
2588
2589 return -EINVAL;
2590}
2591
2592#define RK3588_DRV_BITS_PER_PIN 4
2593#define RK3588_DRV_PINS_PER_REG 4
2594
2595static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2596 int pin_num, struct regmap **regmap,
2597 int *reg, u8 *bit)
2598{
2599 struct rockchip_pinctrl *info = bank->drvdata;
2600 u8 bank_num = bank->bank_num;
2601 u32 pin = bank_num * 32 + pin_num;
2602 int i;
2603
2604 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
2605 if (pin >= rk3588_ds_regs[i][0]) {
2606 *reg = rk3588_ds_regs[i][1];
2607 *regmap = info->regmap_base;
2608 *bit = pin_num % RK3588_DRV_PINS_PER_REG;
2609 *bit *= RK3588_DRV_BITS_PER_PIN;
2610 return 0;
2611 }
2612 }
2613
2614 return -EINVAL;
2615}
2616
2617#define RK3588_SMT_BITS_PER_PIN 1
2618#define RK3588_SMT_PINS_PER_REG 8
2619
2620static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2621 int pin_num,
2622 struct regmap **regmap,
2623 int *reg, u8 *bit)
2624{
2625 struct rockchip_pinctrl *info = bank->drvdata;
2626 u8 bank_num = bank->bank_num;
2627 u32 pin = bank_num * 32 + pin_num;
2628 int i;
2629
2630 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
2631 if (pin >= rk3588_smt_regs[i][0]) {
2632 *reg = rk3588_smt_regs[i][1];
2633 *regmap = info->regmap_base;
2634 *bit = pin_num % RK3588_SMT_PINS_PER_REG;
2635 *bit *= RK3588_SMT_BITS_PER_PIN;
2636 return 0;
2637 }
2638 }
2639
2640 return -EINVAL;
2641}
2642
2643static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2644 { 2, 4, 8, 12, -1, -1, -1, -1 },
2645 { 3, 6, 9, 12, -1, -1, -1, -1 },
2646 { 5, 10, 15, 20, -1, -1, -1, -1 },
2647 { 4, 6, 8, 10, 12, 14, 16, 18 },
2648 { 4, 7, 10, 13, 16, 19, 22, 26 }
2649};
2650
2651static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2652 int pin_num)
2653{
2654 struct rockchip_pinctrl *info = bank->drvdata;
2655 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2656 struct device *dev = info->dev;
2657 struct regmap *regmap;
2658 int reg, ret;
2659 u32 data, temp, rmask_bits;
2660 u8 bit;
2661 int drv_type = bank->drv[pin_num / 8].drv_type;
2662
2663 ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2664 if (ret)
2665 return ret;
2666
2667 switch (drv_type) {
2668 case DRV_TYPE_IO_1V8_3V0_AUTO:
2669 case DRV_TYPE_IO_3V3_ONLY:
2670 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2671 switch (bit) {
2672 case 0 ... 12:
2673 /* regular case, nothing to do */
2674 break;
2675 case 15:
2676 /*
2677 * drive-strength offset is special, as it is
2678 * spread over 2 registers
2679 */
2680 ret = regmap_read(map: regmap, reg, val: &data);
2681 if (ret)
2682 return ret;
2683
2684 ret = regmap_read(map: regmap, reg: reg + 0x4, val: &temp);
2685 if (ret)
2686 return ret;
2687
2688 /*
2689 * the bit data[15] contains bit 0 of the value
2690 * while temp[1:0] contains bits 2 and 1
2691 */
2692 data >>= 15;
2693 temp &= 0x3;
2694 temp <<= 1;
2695 data |= temp;
2696
2697 return rockchip_perpin_drv_list[drv_type][data];
2698 case 18 ... 21:
2699 /* setting fully enclosed in the second register */
2700 reg += 4;
2701 bit -= 16;
2702 break;
2703 default:
2704 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2705 bit, drv_type);
2706 return -EINVAL;
2707 }
2708
2709 break;
2710 case DRV_TYPE_IO_DEFAULT:
2711 case DRV_TYPE_IO_1V8_OR_3V0:
2712 case DRV_TYPE_IO_1V8_ONLY:
2713 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2714 break;
2715 default:
2716 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2717 return -EINVAL;
2718 }
2719
2720 ret = regmap_read(map: regmap, reg, val: &data);
2721 if (ret)
2722 return ret;
2723
2724 data >>= bit;
2725 data &= (1 << rmask_bits) - 1;
2726
2727 return rockchip_perpin_drv_list[drv_type][data];
2728}
2729
2730static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2731 int pin_num, int strength)
2732{
2733 struct rockchip_pinctrl *info = bank->drvdata;
2734 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2735 struct device *dev = info->dev;
2736 struct regmap *regmap;
2737 int reg, ret, i;
2738 u32 data, rmask, rmask_bits, temp;
2739 u8 bit;
2740 int drv_type = bank->drv[pin_num / 8].drv_type;
2741
2742 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2743 bank->bank_num, pin_num, strength);
2744
2745 ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2746 if (ret)
2747 return ret;
2748 if (ctrl->type == RK3588) {
2749 rmask_bits = RK3588_DRV_BITS_PER_PIN;
2750 ret = strength;
2751 goto config;
2752 } else if (ctrl->type == RK3528 ||
2753 ctrl->type == RK3562 ||
2754 ctrl->type == RK3568) {
2755 rmask_bits = RK3568_DRV_BITS_PER_PIN;
2756 ret = (1 << (strength + 1)) - 1;
2757 goto config;
2758 } else if (ctrl->type == RK3576) {
2759 rmask_bits = RK3576_DRV_BITS_PER_PIN;
2760 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
2761 goto config;
2762 }
2763
2764 if (ctrl->type == RV1126) {
2765 rmask_bits = RV1126_DRV_BITS_PER_PIN;
2766 ret = strength;
2767 goto config;
2768 }
2769
2770 ret = -EINVAL;
2771 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2772 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2773 ret = i;
2774 break;
2775 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2776 ret = rockchip_perpin_drv_list[drv_type][i];
2777 break;
2778 }
2779 }
2780
2781 if (ret < 0) {
2782 dev_err(dev, "unsupported driver strength %d\n", strength);
2783 return ret;
2784 }
2785
2786 switch (drv_type) {
2787 case DRV_TYPE_IO_1V8_3V0_AUTO:
2788 case DRV_TYPE_IO_3V3_ONLY:
2789 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2790 switch (bit) {
2791 case 0 ... 12:
2792 /* regular case, nothing to do */
2793 break;
2794 case 15:
2795 /*
2796 * drive-strength offset is special, as it is spread
2797 * over 2 registers, the bit data[15] contains bit 0
2798 * of the value while temp[1:0] contains bits 2 and 1
2799 */
2800 data = (ret & 0x1) << 15;
2801 temp = (ret >> 0x1) & 0x3;
2802
2803 rmask = BIT(15) | BIT(31);
2804 data |= BIT(31);
2805 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2806 if (ret)
2807 return ret;
2808
2809 rmask = 0x3 | (0x3 << 16);
2810 temp |= (0x3 << 16);
2811 reg += 0x4;
2812 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: temp);
2813
2814 return ret;
2815 case 18 ... 21:
2816 /* setting fully enclosed in the second register */
2817 reg += 4;
2818 bit -= 16;
2819 break;
2820 default:
2821 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2822 bit, drv_type);
2823 return -EINVAL;
2824 }
2825 break;
2826 case DRV_TYPE_IO_DEFAULT:
2827 case DRV_TYPE_IO_1V8_OR_3V0:
2828 case DRV_TYPE_IO_1V8_ONLY:
2829 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2830 break;
2831 default:
2832 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2833 return -EINVAL;
2834 }
2835
2836config:
2837 /* enable the write to the equivalent lower bits */
2838 data = ((1 << rmask_bits) - 1) << (bit + 16);
2839 rmask = data | (data >> 16);
2840 data |= (ret << bit);
2841
2842 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2843
2844 return ret;
2845}
2846
2847static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2848 {
2849 PIN_CONFIG_BIAS_DISABLE,
2850 PIN_CONFIG_BIAS_PULL_UP,
2851 PIN_CONFIG_BIAS_PULL_DOWN,
2852 PIN_CONFIG_BIAS_BUS_HOLD
2853 },
2854 {
2855 PIN_CONFIG_BIAS_DISABLE,
2856 PIN_CONFIG_BIAS_PULL_DOWN,
2857 PIN_CONFIG_BIAS_DISABLE,
2858 PIN_CONFIG_BIAS_PULL_UP
2859 },
2860};
2861
2862static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2863{
2864 struct rockchip_pinctrl *info = bank->drvdata;
2865 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2866 struct device *dev = info->dev;
2867 struct regmap *regmap;
2868 int reg, ret, pull_type;
2869 u8 bit;
2870 u32 data;
2871
2872 /* rk3066b does support any pulls */
2873 if (ctrl->type == RK3066B)
2874 return PIN_CONFIG_BIAS_DISABLE;
2875
2876 ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2877 if (ret)
2878 return ret;
2879
2880 ret = regmap_read(map: regmap, reg, val: &data);
2881 if (ret)
2882 return ret;
2883
2884 switch (ctrl->type) {
2885 case RK2928:
2886 case RK3128:
2887 return !(data & BIT(bit))
2888 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2889 : PIN_CONFIG_BIAS_DISABLE;
2890 case PX30:
2891 case RV1108:
2892 case RK3188:
2893 case RK3288:
2894 case RK3308:
2895 case RK3328:
2896 case RK3368:
2897 case RK3399:
2898 case RK3528:
2899 case RK3562:
2900 case RK3568:
2901 case RK3576:
2902 case RK3588:
2903 pull_type = bank->pull_type[pin_num / 8];
2904 data >>= bit;
2905 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2906 /*
2907 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2908 * where that pull up value becomes 3.
2909 */
2910 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2911 if (data == 3)
2912 data = 1;
2913 }
2914
2915 return rockchip_pull_list[pull_type][data];
2916 default:
2917 dev_err(dev, "unsupported pinctrl type\n");
2918 return -EINVAL;
2919 };
2920}
2921
2922static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2923 int pin_num, int pull)
2924{
2925 struct rockchip_pinctrl *info = bank->drvdata;
2926 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2927 struct device *dev = info->dev;
2928 struct regmap *regmap;
2929 int reg, ret, i, pull_type;
2930 u8 bit;
2931 u32 data, rmask;
2932
2933 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2934
2935 /* rk3066b does support any pulls */
2936 if (ctrl->type == RK3066B)
2937 return pull ? -EINVAL : 0;
2938
2939 ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2940 if (ret)
2941 return ret;
2942
2943 switch (ctrl->type) {
2944 case RK2928:
2945 case RK3128:
2946 data = BIT(bit + 16);
2947 if (pull == PIN_CONFIG_BIAS_DISABLE)
2948 data |= BIT(bit);
2949 ret = regmap_write(map: regmap, reg, val: data);
2950 break;
2951 case PX30:
2952 case RV1108:
2953 case RV1126:
2954 case RK3188:
2955 case RK3288:
2956 case RK3308:
2957 case RK3328:
2958 case RK3368:
2959 case RK3399:
2960 case RK3528:
2961 case RK3562:
2962 case RK3568:
2963 case RK3576:
2964 case RK3588:
2965 pull_type = bank->pull_type[pin_num / 8];
2966 ret = -EINVAL;
2967 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2968 i++) {
2969 if (rockchip_pull_list[pull_type][i] == pull) {
2970 ret = i;
2971 break;
2972 }
2973 }
2974 /*
2975 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2976 * where that pull up value becomes 3.
2977 */
2978 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2979 if (ret == 1)
2980 ret = 3;
2981 }
2982
2983 if (ret < 0) {
2984 dev_err(dev, "unsupported pull setting %d\n", pull);
2985 return ret;
2986 }
2987
2988 /* enable the write to the equivalent lower bits */
2989 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2990 rmask = data | (data >> 16);
2991 data |= (ret << bit);
2992
2993 ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2994 break;
2995 default:
2996 dev_err(dev, "unsupported pinctrl type\n");
2997 return -EINVAL;
2998 }
2999
3000 return ret;
3001}
3002
3003#define RK3328_SCHMITT_BITS_PER_PIN 1
3004#define RK3328_SCHMITT_PINS_PER_REG 16
3005#define RK3328_SCHMITT_BANK_STRIDE 8
3006#define RK3328_SCHMITT_GRF_OFFSET 0x380
3007
3008static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3009 int pin_num,
3010 struct regmap **regmap,
3011 int *reg, u8 *bit)
3012{
3013 struct rockchip_pinctrl *info = bank->drvdata;
3014
3015 *regmap = info->regmap_base;
3016 *reg = RK3328_SCHMITT_GRF_OFFSET;
3017
3018 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
3019 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
3020 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
3021
3022 return 0;
3023}
3024
3025#define RK3568_SCHMITT_BITS_PER_PIN 2
3026#define RK3568_SCHMITT_PINS_PER_REG 8
3027#define RK3568_SCHMITT_BANK_STRIDE 0x10
3028#define RK3568_SCHMITT_GRF_OFFSET 0xc0
3029#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
3030
3031static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3032 int pin_num,
3033 struct regmap **regmap,
3034 int *reg, u8 *bit)
3035{
3036 struct rockchip_pinctrl *info = bank->drvdata;
3037
3038 if (bank->bank_num == 0) {
3039 *regmap = info->regmap_pmu;
3040 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
3041 } else {
3042 *regmap = info->regmap_base;
3043 *reg = RK3568_SCHMITT_GRF_OFFSET;
3044 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
3045 }
3046
3047 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
3048 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
3049 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
3050
3051 return 0;
3052}
3053
3054static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
3055{
3056 struct rockchip_pinctrl *info = bank->drvdata;
3057 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3058 struct regmap *regmap;
3059 int reg, ret;
3060 u8 bit;
3061 u32 data;
3062
3063 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
3064 if (ret)
3065 return ret;
3066
3067 ret = regmap_read(map: regmap, reg, val: &data);
3068 if (ret)
3069 return ret;
3070
3071 data >>= bit;
3072 switch (ctrl->type) {
3073 case RK3562:
3074 case RK3568:
3075 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
3076 default:
3077 break;
3078 }
3079
3080 return data & 0x1;
3081}
3082
3083static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
3084 int pin_num, int enable)
3085{
3086 struct rockchip_pinctrl *info = bank->drvdata;
3087 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3088 struct device *dev = info->dev;
3089 struct regmap *regmap;
3090 int reg, ret;
3091 u8 bit;
3092 u32 data, rmask;
3093
3094 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
3095 bank->bank_num, pin_num, enable);
3096
3097 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
3098 if (ret)
3099 return ret;
3100
3101 /* enable the write to the equivalent lower bits */
3102 switch (ctrl->type) {
3103 case RK3562:
3104 case RK3568:
3105 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
3106 rmask = data | (data >> 16);
3107 data |= ((enable ? 0x2 : 0x1) << bit);
3108 break;
3109 default:
3110 data = BIT(bit + 16) | (enable << bit);
3111 rmask = BIT(bit + 16) | BIT(bit);
3112 break;
3113 }
3114
3115 return regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
3116}
3117
3118/*
3119 * Pinmux_ops handling
3120 */
3121
3122static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
3123{
3124 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3125
3126 return info->nfunctions;
3127}
3128
3129static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
3130 unsigned selector)
3131{
3132 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3133
3134 return info->functions[selector].name;
3135}
3136
3137static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
3138 unsigned selector, const char * const **groups,
3139 unsigned * const num_groups)
3140{
3141 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3142
3143 *groups = info->functions[selector].groups;
3144 *num_groups = info->functions[selector].ngroups;
3145
3146 return 0;
3147}
3148
3149static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
3150 unsigned group)
3151{
3152 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3153 const unsigned int *pins = info->groups[group].pins;
3154 const struct rockchip_pin_config *data = info->groups[group].data;
3155 struct device *dev = info->dev;
3156 struct rockchip_pin_bank *bank;
3157 int cnt, ret = 0;
3158
3159 dev_dbg(dev, "enable function %s group %s\n",
3160 info->functions[selector].name, info->groups[group].name);
3161
3162 /*
3163 * for each pin in the pin group selected, program the corresponding
3164 * pin function number in the config register.
3165 */
3166 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
3167 bank = pin_to_bank(info, pin: pins[cnt]);
3168 ret = rockchip_set_mux(bank, pin: pins[cnt] - bank->pin_base,
3169 mux: data[cnt].func);
3170 if (ret)
3171 break;
3172 }
3173
3174 if (ret) {
3175 /* revert the already done pin settings */
3176 for (cnt--; cnt >= 0; cnt--) {
3177 bank = pin_to_bank(info, pin: pins[cnt]);
3178 rockchip_set_mux(bank, pin: pins[cnt] - bank->pin_base, mux: 0);
3179 }
3180
3181 return ret;
3182 }
3183
3184 return 0;
3185}
3186
3187static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
3188 struct pinctrl_gpio_range *range,
3189 unsigned offset,
3190 bool input)
3191{
3192 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3193 struct rockchip_pin_bank *bank;
3194
3195 bank = pin_to_bank(info, pin: offset);
3196 return rockchip_set_mux(bank, pin: offset - bank->pin_base, RK_FUNC_GPIO);
3197}
3198
3199static const struct pinmux_ops rockchip_pmx_ops = {
3200 .get_functions_count = rockchip_pmx_get_funcs_count,
3201 .get_function_name = rockchip_pmx_get_func_name,
3202 .get_function_groups = rockchip_pmx_get_groups,
3203 .set_mux = rockchip_pmx_set,
3204 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
3205};
3206
3207/*
3208 * Pinconf_ops handling
3209 */
3210
3211static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
3212 enum pin_config_param pull)
3213{
3214 switch (ctrl->type) {
3215 case RK2928:
3216 case RK3128:
3217 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
3218 pull == PIN_CONFIG_BIAS_DISABLE);
3219 case RK3066B:
3220 return pull ? false : true;
3221 case PX30:
3222 case RV1108:
3223 case RV1126:
3224 case RK3188:
3225 case RK3288:
3226 case RK3308:
3227 case RK3328:
3228 case RK3368:
3229 case RK3399:
3230 case RK3528:
3231 case RK3562:
3232 case RK3568:
3233 case RK3576:
3234 case RK3588:
3235 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
3236 }
3237
3238 return false;
3239}
3240
3241static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
3242 unsigned int pin, u32 param, u32 arg)
3243{
3244 struct rockchip_pin_deferred *cfg;
3245
3246 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
3247 if (!cfg)
3248 return -ENOMEM;
3249
3250 cfg->pin = pin;
3251 cfg->param = param;
3252 cfg->arg = arg;
3253
3254 list_add_tail(new: &cfg->head, head: &bank->deferred_pins);
3255
3256 return 0;
3257}
3258
3259/* set the pin config settings for a specified pin */
3260static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3261 unsigned long *configs, unsigned num_configs)
3262{
3263 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3264 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3265 struct gpio_chip *gpio = &bank->gpio_chip;
3266 enum pin_config_param param;
3267 u32 arg;
3268 int i;
3269 int rc;
3270
3271 for (i = 0; i < num_configs; i++) {
3272 param = pinconf_to_config_param(config: configs[i]);
3273 arg = pinconf_to_config_argument(config: configs[i]);
3274
3275 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
3276 /*
3277 * Check for gpio driver not being probed yet.
3278 * The lock makes sure that either gpio-probe has completed
3279 * or the gpio driver hasn't probed yet.
3280 */
3281 mutex_lock(&bank->deferred_lock);
3282 if (!gpio || !gpio->direction_output) {
3283 rc = rockchip_pinconf_defer_pin(bank, pin: pin - bank->pin_base, param,
3284 arg);
3285 mutex_unlock(lock: &bank->deferred_lock);
3286 if (rc)
3287 return rc;
3288
3289 break;
3290 }
3291 mutex_unlock(lock: &bank->deferred_lock);
3292 }
3293
3294 switch (param) {
3295 case PIN_CONFIG_BIAS_DISABLE:
3296 rc = rockchip_set_pull(bank, pin_num: pin - bank->pin_base,
3297 pull: param);
3298 if (rc)
3299 return rc;
3300 break;
3301 case PIN_CONFIG_BIAS_PULL_UP:
3302 case PIN_CONFIG_BIAS_PULL_DOWN:
3303 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3304 case PIN_CONFIG_BIAS_BUS_HOLD:
3305 if (!rockchip_pinconf_pull_valid(ctrl: info->ctrl, pull: param))
3306 return -ENOTSUPP;
3307
3308 if (!arg)
3309 return -EINVAL;
3310
3311 rc = rockchip_set_pull(bank, pin_num: pin - bank->pin_base,
3312 pull: param);
3313 if (rc)
3314 return rc;
3315 break;
3316 case PIN_CONFIG_OUTPUT:
3317 rc = rockchip_set_mux(bank, pin: pin - bank->pin_base,
3318 RK_FUNC_GPIO);
3319 if (rc != RK_FUNC_GPIO)
3320 return -EINVAL;
3321
3322 rc = gpio->direction_output(gpio, pin - bank->pin_base,
3323 arg);
3324 if (rc)
3325 return rc;
3326 break;
3327 case PIN_CONFIG_INPUT_ENABLE:
3328 rc = rockchip_set_mux(bank, pin: pin - bank->pin_base,
3329 RK_FUNC_GPIO);
3330 if (rc != RK_FUNC_GPIO)
3331 return -EINVAL;
3332
3333 rc = gpio->direction_input(gpio, pin - bank->pin_base);
3334 if (rc)
3335 return rc;
3336 break;
3337 case PIN_CONFIG_DRIVE_STRENGTH:
3338 /* rk3288 is the first with per-pin drive-strength */
3339 if (!info->ctrl->drv_calc_reg)
3340 return -ENOTSUPP;
3341
3342 rc = rockchip_set_drive_perpin(bank,
3343 pin_num: pin - bank->pin_base, strength: arg);
3344 if (rc < 0)
3345 return rc;
3346 break;
3347 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3348 if (!info->ctrl->schmitt_calc_reg)
3349 return -ENOTSUPP;
3350
3351 rc = rockchip_set_schmitt(bank,
3352 pin_num: pin - bank->pin_base, enable: arg);
3353 if (rc < 0)
3354 return rc;
3355 break;
3356 default:
3357 return -ENOTSUPP;
3358 break;
3359 }
3360 } /* for each config */
3361
3362 return 0;
3363}
3364
3365/* get the pin config settings for a specified pin */
3366static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
3367 unsigned long *config)
3368{
3369 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3370 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3371 struct gpio_chip *gpio = &bank->gpio_chip;
3372 enum pin_config_param param = pinconf_to_config_param(config: *config);
3373 u16 arg;
3374 int rc;
3375
3376 switch (param) {
3377 case PIN_CONFIG_BIAS_DISABLE:
3378 if (rockchip_get_pull(bank, pin_num: pin - bank->pin_base) != param)
3379 return -EINVAL;
3380
3381 arg = 0;
3382 break;
3383 case PIN_CONFIG_BIAS_PULL_UP:
3384 case PIN_CONFIG_BIAS_PULL_DOWN:
3385 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3386 case PIN_CONFIG_BIAS_BUS_HOLD:
3387 if (!rockchip_pinconf_pull_valid(ctrl: info->ctrl, pull: param))
3388 return -ENOTSUPP;
3389
3390 if (rockchip_get_pull(bank, pin_num: pin - bank->pin_base) != param)
3391 return -EINVAL;
3392
3393 arg = 1;
3394 break;
3395 case PIN_CONFIG_OUTPUT:
3396 rc = rockchip_get_mux(bank, pin: pin - bank->pin_base);
3397 if (rc != RK_FUNC_GPIO)
3398 return -EINVAL;
3399
3400 if (!gpio || !gpio->get) {
3401 arg = 0;
3402 break;
3403 }
3404
3405 rc = gpio->get(gpio, pin - bank->pin_base);
3406 if (rc < 0)
3407 return rc;
3408
3409 arg = rc ? 1 : 0;
3410 break;
3411 case PIN_CONFIG_DRIVE_STRENGTH:
3412 /* rk3288 is the first with per-pin drive-strength */
3413 if (!info->ctrl->drv_calc_reg)
3414 return -ENOTSUPP;
3415
3416 rc = rockchip_get_drive_perpin(bank, pin_num: pin - bank->pin_base);
3417 if (rc < 0)
3418 return rc;
3419
3420 arg = rc;
3421 break;
3422 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3423 if (!info->ctrl->schmitt_calc_reg)
3424 return -ENOTSUPP;
3425
3426 rc = rockchip_get_schmitt(bank, pin_num: pin - bank->pin_base);
3427 if (rc < 0)
3428 return rc;
3429
3430 arg = rc;
3431 break;
3432 default:
3433 return -ENOTSUPP;
3434 break;
3435 }
3436
3437 *config = pinconf_to_config_packed(param, argument: arg);
3438
3439 return 0;
3440}
3441
3442static const struct pinconf_ops rockchip_pinconf_ops = {
3443 .pin_config_get = rockchip_pinconf_get,
3444 .pin_config_set = rockchip_pinconf_set,
3445 .is_generic = true,
3446};
3447
3448static const struct of_device_id rockchip_bank_match[] = {
3449 { .compatible = "rockchip,gpio-bank" },
3450 { .compatible = "rockchip,rk3188-gpio-bank0" },
3451 {},
3452};
3453
3454static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
3455 struct device_node *np)
3456{
3457 struct device_node *child;
3458
3459 for_each_child_of_node(np, child) {
3460 if (of_match_node(matches: rockchip_bank_match, node: child))
3461 continue;
3462
3463 info->nfunctions++;
3464 info->ngroups += of_get_child_count(np: child);
3465 }
3466}
3467
3468static int rockchip_pinctrl_parse_groups(struct device_node *np,
3469 struct rockchip_pin_group *grp,
3470 struct rockchip_pinctrl *info,
3471 u32 index)
3472{
3473 struct device *dev = info->dev;
3474 struct rockchip_pin_bank *bank;
3475 int size;
3476 const __be32 *list;
3477 int num;
3478 int i, j;
3479 int ret;
3480
3481 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3482
3483 /* Initialise group */
3484 grp->name = np->name;
3485
3486 /*
3487 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
3488 * do sanity check and calculate pins number
3489 */
3490 list = of_get_property(node: np, name: "rockchip,pins", lenp: &size);
3491 /* we do not check return since it's safe node passed down */
3492 size /= sizeof(*list);
3493 if (!size || size % 4)
3494 return dev_err_probe(dev, err: -EINVAL,
3495 fmt: "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n",
3496 np, size);
3497
3498 grp->npins = size / 4;
3499
3500 grp->pins = devm_kcalloc(dev, n: grp->npins, size: sizeof(*grp->pins), GFP_KERNEL);
3501 grp->data = devm_kcalloc(dev, n: grp->npins, size: sizeof(*grp->data), GFP_KERNEL);
3502 if (!grp->pins || !grp->data)
3503 return -ENOMEM;
3504
3505 for (i = 0, j = 0; i < size; i += 4, j++) {
3506 const __be32 *phandle;
3507 struct device_node *np_config;
3508
3509 num = be32_to_cpu(*list++);
3510 bank = bank_num_to_bank(info, num);
3511 if (IS_ERR(ptr: bank))
3512 return PTR_ERR(ptr: bank);
3513
3514 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3515 grp->data[j].func = be32_to_cpu(*list++);
3516
3517 phandle = list++;
3518 if (!phandle)
3519 return -EINVAL;
3520
3521 np_config = of_find_node_by_phandle(be32_to_cpup(p: phandle));
3522 ret = pinconf_generic_parse_dt_config(np: np_config, NULL,
3523 configs: &grp->data[j].configs, nconfigs: &grp->data[j].nconfigs);
3524 of_node_put(node: np_config);
3525 if (ret)
3526 return ret;
3527 }
3528
3529 return 0;
3530}
3531
3532static int rockchip_pinctrl_parse_functions(struct device_node *np,
3533 struct rockchip_pinctrl *info,
3534 u32 index)
3535{
3536 struct device *dev = info->dev;
3537 struct rockchip_pmx_func *func;
3538 struct rockchip_pin_group *grp;
3539 int ret;
3540 static u32 grp_index;
3541 u32 i = 0;
3542
3543 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3544
3545 func = &info->functions[index];
3546
3547 /* Initialise function */
3548 func->name = np->name;
3549 func->ngroups = of_get_child_count(np);
3550 if (func->ngroups <= 0)
3551 return 0;
3552
3553 func->groups = devm_kcalloc(dev, n: func->ngroups, size: sizeof(*func->groups), GFP_KERNEL);
3554 if (!func->groups)
3555 return -ENOMEM;
3556
3557 for_each_child_of_node_scoped(np, child) {
3558 func->groups[i] = child->name;
3559 grp = &info->groups[grp_index++];
3560 ret = rockchip_pinctrl_parse_groups(np: child, grp, info, index: i++);
3561 if (ret)
3562 return ret;
3563 }
3564
3565 return 0;
3566}
3567
3568static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
3569 struct rockchip_pinctrl *info)
3570{
3571 struct device *dev = &pdev->dev;
3572 struct device_node *np = dev->of_node;
3573 int ret;
3574 int i;
3575
3576 rockchip_pinctrl_child_count(info, np);
3577
3578 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
3579 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3580
3581 info->functions = devm_kcalloc(dev, n: info->nfunctions, size: sizeof(*info->functions), GFP_KERNEL);
3582 if (!info->functions)
3583 return -ENOMEM;
3584
3585 info->groups = devm_kcalloc(dev, n: info->ngroups, size: sizeof(*info->groups), GFP_KERNEL);
3586 if (!info->groups)
3587 return -ENOMEM;
3588
3589 i = 0;
3590
3591 for_each_child_of_node_scoped(np, child) {
3592 if (of_match_node(matches: rockchip_bank_match, node: child))
3593 continue;
3594
3595 ret = rockchip_pinctrl_parse_functions(np: child, info, index: i++);
3596 if (ret) {
3597 dev_err(dev, "failed to parse function\n");
3598 return ret;
3599 }
3600 }
3601
3602 return 0;
3603}
3604
3605static int rockchip_pinctrl_register(struct platform_device *pdev,
3606 struct rockchip_pinctrl *info)
3607{
3608 struct pinctrl_desc *ctrldesc = &info->pctl;
3609 struct pinctrl_pin_desc *pindesc, *pdesc;
3610 struct rockchip_pin_bank *pin_bank;
3611 struct device *dev = &pdev->dev;
3612 char **pin_names;
3613 int pin, bank, ret;
3614 int k;
3615
3616 ctrldesc->name = "rockchip-pinctrl";
3617 ctrldesc->owner = THIS_MODULE;
3618 ctrldesc->pctlops = &rockchip_pctrl_ops;
3619 ctrldesc->pmxops = &rockchip_pmx_ops;
3620 ctrldesc->confops = &rockchip_pinconf_ops;
3621
3622 pindesc = devm_kcalloc(dev, n: info->ctrl->nr_pins, size: sizeof(*pindesc), GFP_KERNEL);
3623 if (!pindesc)
3624 return -ENOMEM;
3625
3626 ctrldesc->pins = pindesc;
3627 ctrldesc->npins = info->ctrl->nr_pins;
3628
3629 pdesc = pindesc;
3630 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3631 pin_bank = &info->ctrl->pin_banks[bank];
3632
3633 pin_names = devm_kasprintf_strarray(dev, prefix: pin_bank->name, n: pin_bank->nr_pins);
3634 if (IS_ERR(ptr: pin_names))
3635 return PTR_ERR(ptr: pin_names);
3636
3637 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3638 pdesc->number = k;
3639 pdesc->name = pin_names[pin];
3640 pdesc++;
3641 }
3642
3643 INIT_LIST_HEAD(list: &pin_bank->deferred_pins);
3644 mutex_init(&pin_bank->deferred_lock);
3645 }
3646
3647 ret = rockchip_pinctrl_parse_dt(pdev, info);
3648 if (ret)
3649 return ret;
3650
3651 info->pctl_dev = devm_pinctrl_register(dev, pctldesc: ctrldesc, driver_data: info);
3652 if (IS_ERR(ptr: info->pctl_dev))
3653 return dev_err_probe(dev, err: PTR_ERR(ptr: info->pctl_dev), fmt: "could not register pinctrl driver\n");
3654
3655 return 0;
3656}
3657
3658static const struct of_device_id rockchip_pinctrl_dt_match[];
3659
3660/* retrieve the soc specific data */
3661static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3662 struct rockchip_pinctrl *d,
3663 struct platform_device *pdev)
3664{
3665 struct device *dev = &pdev->dev;
3666 struct device_node *node = dev->of_node;
3667 const struct of_device_id *match;
3668 struct rockchip_pin_ctrl *ctrl;
3669 struct rockchip_pin_bank *bank;
3670 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3671
3672 match = of_match_node(matches: rockchip_pinctrl_dt_match, node);
3673 ctrl = (struct rockchip_pin_ctrl *)match->data;
3674
3675 grf_offs = ctrl->grf_mux_offset;
3676 pmu_offs = ctrl->pmu_mux_offset;
3677 drv_pmu_offs = ctrl->pmu_drv_offset;
3678 drv_grf_offs = ctrl->grf_drv_offset;
3679 bank = ctrl->pin_banks;
3680 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3681 int bank_pins = 0;
3682
3683 raw_spin_lock_init(&bank->slock);
3684 bank->drvdata = d;
3685 bank->pin_base = ctrl->nr_pins;
3686 ctrl->nr_pins += bank->nr_pins;
3687
3688 /* calculate iomux and drv offsets */
3689 for (j = 0; j < 4; j++) {
3690 struct rockchip_iomux *iom = &bank->iomux[j];
3691 struct rockchip_drv *drv = &bank->drv[j];
3692 int inc;
3693
3694 if (bank_pins >= bank->nr_pins)
3695 break;
3696
3697 /* preset iomux offset value, set new start value */
3698 if (iom->offset >= 0) {
3699 if ((iom->type & IOMUX_SOURCE_PMU) ||
3700 (iom->type & IOMUX_L_SOURCE_PMU))
3701 pmu_offs = iom->offset;
3702 else
3703 grf_offs = iom->offset;
3704 } else { /* set current iomux offset */
3705 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3706 (iom->type & IOMUX_L_SOURCE_PMU)) ?
3707 pmu_offs : grf_offs;
3708 }
3709
3710 /* preset drv offset value, set new start value */
3711 if (drv->offset >= 0) {
3712 if (iom->type & IOMUX_SOURCE_PMU)
3713 drv_pmu_offs = drv->offset;
3714 else
3715 drv_grf_offs = drv->offset;
3716 } else { /* set current drv offset */
3717 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3718 drv_pmu_offs : drv_grf_offs;
3719 }
3720
3721 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3722 i, j, iom->offset, drv->offset);
3723
3724 /*
3725 * Increase offset according to iomux width.
3726 * 4bit iomux'es are spread over two registers.
3727 */
3728 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3729 IOMUX_WIDTH_3BIT |
3730 IOMUX_WIDTH_2BIT)) ? 8 : 4;
3731 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3732 pmu_offs += inc;
3733 else
3734 grf_offs += inc;
3735
3736 /*
3737 * Increase offset according to drv width.
3738 * 3bit drive-strenth'es are spread over two registers.
3739 */
3740 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3741 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3742 inc = 8;
3743 else
3744 inc = 4;
3745
3746 if (iom->type & IOMUX_SOURCE_PMU)
3747 drv_pmu_offs += inc;
3748 else
3749 drv_grf_offs += inc;
3750
3751 bank_pins += 8;
3752 }
3753
3754 /* calculate the per-bank recalced_mask */
3755 for (j = 0; j < ctrl->niomux_recalced; j++) {
3756 int pin = 0;
3757
3758 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3759 pin = ctrl->iomux_recalced[j].pin;
3760 bank->recalced_mask |= BIT(pin);
3761 }
3762 }
3763
3764 /* calculate the per-bank route_mask */
3765 for (j = 0; j < ctrl->niomux_routes; j++) {
3766 int pin = 0;
3767
3768 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3769 pin = ctrl->iomux_routes[j].pin;
3770 bank->route_mask |= BIT(pin);
3771 }
3772 }
3773 }
3774
3775 return ctrl;
3776}
3777
3778#define RK3288_GRF_GPIO6C_IOMUX 0x64
3779#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3780
3781static u32 rk3288_grf_gpio6c_iomux;
3782
3783static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3784{
3785 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3786 int ret = pinctrl_force_sleep(pctldev: info->pctl_dev);
3787
3788 if (ret)
3789 return ret;
3790
3791 /*
3792 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3793 * the setting here, and restore it at resume.
3794 */
3795 if (info->ctrl->type == RK3288) {
3796 ret = regmap_read(map: info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3797 val: &rk3288_grf_gpio6c_iomux);
3798 if (ret) {
3799 pinctrl_force_default(pctldev: info->pctl_dev);
3800 return ret;
3801 }
3802 }
3803
3804 return 0;
3805}
3806
3807static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3808{
3809 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3810 int ret;
3811
3812 if (info->ctrl->type == RK3288) {
3813 ret = regmap_write(map: info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3814 val: rk3288_grf_gpio6c_iomux |
3815 GPIO6C6_SEL_WRITE_ENABLE);
3816 if (ret)
3817 return ret;
3818 }
3819
3820 return pinctrl_force_default(pctldev: info->pctl_dev);
3821}
3822
3823static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3824 rockchip_pinctrl_resume);
3825
3826static int rockchip_pinctrl_probe(struct platform_device *pdev)
3827{
3828 struct rockchip_pinctrl *info;
3829 struct device *dev = &pdev->dev;
3830 struct device_node *np = dev->of_node, *node;
3831 struct rockchip_pin_ctrl *ctrl;
3832 struct resource *res;
3833 void __iomem *base;
3834 int ret;
3835
3836 if (!dev->of_node)
3837 return dev_err_probe(dev, err: -ENODEV, fmt: "device tree node not found\n");
3838
3839 info = devm_kzalloc(dev, size: sizeof(*info), GFP_KERNEL);
3840 if (!info)
3841 return -ENOMEM;
3842
3843 info->dev = dev;
3844
3845 ctrl = rockchip_pinctrl_get_soc_data(d: info, pdev);
3846 if (!ctrl)
3847 return dev_err_probe(dev, err: -EINVAL, fmt: "driver data not available\n");
3848 info->ctrl = ctrl;
3849
3850 node = of_parse_phandle(np, phandle_name: "rockchip,grf", index: 0);
3851 if (node) {
3852 info->regmap_base = syscon_node_to_regmap(np: node);
3853 of_node_put(node);
3854 if (IS_ERR(ptr: info->regmap_base))
3855 return PTR_ERR(ptr: info->regmap_base);
3856 } else {
3857 base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res);
3858 if (IS_ERR(ptr: base))
3859 return PTR_ERR(ptr: base);
3860
3861 rockchip_regmap_config.max_register = resource_size(res) - 4;
3862 rockchip_regmap_config.name = "rockchip,pinctrl";
3863 info->regmap_base =
3864 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3865
3866 /* to check for the old dt-bindings */
3867 info->reg_size = resource_size(res);
3868
3869 /* Honor the old binding, with pull registers as 2nd resource */
3870 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3871 base = devm_platform_get_and_ioremap_resource(pdev, index: 1, res: &res);
3872 if (IS_ERR(ptr: base))
3873 return PTR_ERR(ptr: base);
3874
3875 rockchip_regmap_config.max_register = resource_size(res) - 4;
3876 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3877 info->regmap_pull =
3878 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3879 }
3880 }
3881
3882 /* try to find the optional reference to the pmu syscon */
3883 node = of_parse_phandle(np, phandle_name: "rockchip,pmu", index: 0);
3884 if (node) {
3885 info->regmap_pmu = syscon_node_to_regmap(np: node);
3886 of_node_put(node);
3887 if (IS_ERR(ptr: info->regmap_pmu))
3888 return PTR_ERR(ptr: info->regmap_pmu);
3889 }
3890
3891 ret = rockchip_pinctrl_register(pdev, info);
3892 if (ret)
3893 return ret;
3894
3895 platform_set_drvdata(pdev, data: info);
3896
3897 ret = of_platform_populate(root: np, NULL, NULL, parent: &pdev->dev);
3898 if (ret)
3899 return dev_err_probe(dev, err: ret, fmt: "failed to register gpio device\n");
3900
3901 return 0;
3902}
3903
3904static void rockchip_pinctrl_remove(struct platform_device *pdev)
3905{
3906 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
3907 struct rockchip_pin_bank *bank;
3908 struct rockchip_pin_deferred *cfg;
3909 int i;
3910
3911 of_platform_depopulate(parent: &pdev->dev);
3912
3913 for (i = 0; i < info->ctrl->nr_banks; i++) {
3914 bank = &info->ctrl->pin_banks[i];
3915
3916 mutex_lock(&bank->deferred_lock);
3917 while (!list_empty(head: &bank->deferred_pins)) {
3918 cfg = list_first_entry(&bank->deferred_pins,
3919 struct rockchip_pin_deferred, head);
3920 list_del(entry: &cfg->head);
3921 kfree(objp: cfg);
3922 }
3923 mutex_unlock(lock: &bank->deferred_lock);
3924 }
3925}
3926
3927static struct rockchip_pin_bank px30_pin_banks[] = {
3928 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3929 IOMUX_SOURCE_PMU,
3930 IOMUX_SOURCE_PMU,
3931 IOMUX_SOURCE_PMU
3932 ),
3933 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3934 IOMUX_WIDTH_4BIT,
3935 IOMUX_WIDTH_4BIT,
3936 IOMUX_WIDTH_4BIT
3937 ),
3938 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3939 IOMUX_WIDTH_4BIT,
3940 IOMUX_WIDTH_4BIT,
3941 IOMUX_WIDTH_4BIT
3942 ),
3943 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3944 IOMUX_WIDTH_4BIT,
3945 IOMUX_WIDTH_4BIT,
3946 IOMUX_WIDTH_4BIT
3947 ),
3948};
3949
3950static struct rockchip_pin_ctrl px30_pin_ctrl = {
3951 .pin_banks = px30_pin_banks,
3952 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3953 .label = "PX30-GPIO",
3954 .type = PX30,
3955 .grf_mux_offset = 0x0,
3956 .pmu_mux_offset = 0x0,
3957 .iomux_routes = px30_mux_route_data,
3958 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3959 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3960 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3961 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3962};
3963
3964static struct rockchip_pin_bank rv1108_pin_banks[] = {
3965 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3966 IOMUX_SOURCE_PMU,
3967 IOMUX_SOURCE_PMU,
3968 IOMUX_SOURCE_PMU),
3969 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3970 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3971 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3972};
3973
3974static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3975 .pin_banks = rv1108_pin_banks,
3976 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3977 .label = "RV1108-GPIO",
3978 .type = RV1108,
3979 .grf_mux_offset = 0x10,
3980 .pmu_mux_offset = 0x0,
3981 .iomux_recalced = rv1108_mux_recalced_data,
3982 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3983 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3984 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3985 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3986};
3987
3988static struct rockchip_pin_bank rv1126_pin_banks[] = {
3989 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3990 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3991 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3992 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
3993 IOMUX_WIDTH_4BIT),
3994 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
3995 IOMUX_WIDTH_4BIT,
3996 IOMUX_WIDTH_4BIT,
3997 IOMUX_WIDTH_4BIT,
3998 IOMUX_WIDTH_4BIT,
3999 0x10010, 0x10018, 0x10020, 0x10028),
4000 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
4001 IOMUX_WIDTH_4BIT,
4002 IOMUX_WIDTH_4BIT,
4003 IOMUX_WIDTH_4BIT,
4004 IOMUX_WIDTH_4BIT),
4005 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4006 IOMUX_WIDTH_4BIT,
4007 IOMUX_WIDTH_4BIT,
4008 IOMUX_WIDTH_4BIT,
4009 IOMUX_WIDTH_4BIT),
4010 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
4011 IOMUX_WIDTH_4BIT, 0, 0, 0),
4012};
4013
4014static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
4015 .pin_banks = rv1126_pin_banks,
4016 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
4017 .label = "RV1126-GPIO",
4018 .type = RV1126,
4019 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
4020 .pmu_mux_offset = 0x0,
4021 .iomux_routes = rv1126_mux_route_data,
4022 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
4023 .iomux_recalced = rv1126_mux_recalced_data,
4024 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
4025 .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
4026 .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
4027 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
4028};
4029
4030static struct rockchip_pin_bank rk2928_pin_banks[] = {
4031 PIN_BANK(0, 32, "gpio0"),
4032 PIN_BANK(1, 32, "gpio1"),
4033 PIN_BANK(2, 32, "gpio2"),
4034 PIN_BANK(3, 32, "gpio3"),
4035};
4036
4037static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
4038 .pin_banks = rk2928_pin_banks,
4039 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
4040 .label = "RK2928-GPIO",
4041 .type = RK2928,
4042 .grf_mux_offset = 0xa8,
4043 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4044};
4045
4046static struct rockchip_pin_bank rk3036_pin_banks[] = {
4047 PIN_BANK(0, 32, "gpio0"),
4048 PIN_BANK(1, 32, "gpio1"),
4049 PIN_BANK(2, 32, "gpio2"),
4050};
4051
4052static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
4053 .pin_banks = rk3036_pin_banks,
4054 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
4055 .label = "RK3036-GPIO",
4056 .type = RK2928,
4057 .grf_mux_offset = 0xa8,
4058 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4059};
4060
4061static struct rockchip_pin_bank rk3066a_pin_banks[] = {
4062 PIN_BANK(0, 32, "gpio0"),
4063 PIN_BANK(1, 32, "gpio1"),
4064 PIN_BANK(2, 32, "gpio2"),
4065 PIN_BANK(3, 32, "gpio3"),
4066 PIN_BANK(4, 32, "gpio4"),
4067 PIN_BANK(6, 16, "gpio6"),
4068};
4069
4070static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
4071 .pin_banks = rk3066a_pin_banks,
4072 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
4073 .label = "RK3066a-GPIO",
4074 .type = RK2928,
4075 .grf_mux_offset = 0xa8,
4076 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4077};
4078
4079static struct rockchip_pin_bank rk3066b_pin_banks[] = {
4080 PIN_BANK(0, 32, "gpio0"),
4081 PIN_BANK(1, 32, "gpio1"),
4082 PIN_BANK(2, 32, "gpio2"),
4083 PIN_BANK(3, 32, "gpio3"),
4084};
4085
4086static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
4087 .pin_banks = rk3066b_pin_banks,
4088 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
4089 .label = "RK3066b-GPIO",
4090 .type = RK3066B,
4091 .grf_mux_offset = 0x60,
4092};
4093
4094static struct rockchip_pin_bank rk3128_pin_banks[] = {
4095 PIN_BANK(0, 32, "gpio0"),
4096 PIN_BANK(1, 32, "gpio1"),
4097 PIN_BANK(2, 32, "gpio2"),
4098 PIN_BANK(3, 32, "gpio3"),
4099};
4100
4101static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
4102 .pin_banks = rk3128_pin_banks,
4103 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
4104 .label = "RK3128-GPIO",
4105 .type = RK3128,
4106 .grf_mux_offset = 0xa8,
4107 .iomux_recalced = rk3128_mux_recalced_data,
4108 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
4109 .iomux_routes = rk3128_mux_route_data,
4110 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
4111 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
4112};
4113
4114static struct rockchip_pin_bank rk3188_pin_banks[] = {
4115 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
4116 PIN_BANK(1, 32, "gpio1"),
4117 PIN_BANK(2, 32, "gpio2"),
4118 PIN_BANK(3, 32, "gpio3"),
4119};
4120
4121static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
4122 .pin_banks = rk3188_pin_banks,
4123 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
4124 .label = "RK3188-GPIO",
4125 .type = RK3188,
4126 .grf_mux_offset = 0x60,
4127 .iomux_routes = rk3188_mux_route_data,
4128 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
4129 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
4130};
4131
4132static struct rockchip_pin_bank rk3228_pin_banks[] = {
4133 PIN_BANK(0, 32, "gpio0"),
4134 PIN_BANK(1, 32, "gpio1"),
4135 PIN_BANK(2, 32, "gpio2"),
4136 PIN_BANK(3, 32, "gpio3"),
4137};
4138
4139static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4140 .pin_banks = rk3228_pin_banks,
4141 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
4142 .label = "RK3228-GPIO",
4143 .type = RK3288,
4144 .grf_mux_offset = 0x0,
4145 .iomux_routes = rk3228_mux_route_data,
4146 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
4147 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4148 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4149};
4150
4151static struct rockchip_pin_bank rk3288_pin_banks[] = {
4152 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4153 IOMUX_SOURCE_PMU,
4154 IOMUX_SOURCE_PMU,
4155 IOMUX_UNROUTED
4156 ),
4157 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4158 IOMUX_UNROUTED,
4159 IOMUX_UNROUTED,
4160 0
4161 ),
4162 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4163 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4164 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4165 IOMUX_WIDTH_4BIT,
4166 0,
4167 0
4168 ),
4169 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4170 0,
4171 0,
4172 IOMUX_UNROUTED
4173 ),
4174 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4175 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4176 0,
4177 IOMUX_WIDTH_4BIT,
4178 IOMUX_UNROUTED
4179 ),
4180 PIN_BANK(8, 16, "gpio8"),
4181};
4182
4183static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4184 .pin_banks = rk3288_pin_banks,
4185 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
4186 .label = "RK3288-GPIO",
4187 .type = RK3288,
4188 .grf_mux_offset = 0x0,
4189 .pmu_mux_offset = 0x84,
4190 .iomux_routes = rk3288_mux_route_data,
4191 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
4192 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
4193 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4194};
4195
4196static struct rockchip_pin_bank rk3308_pin_banks[] = {
4197 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4198 IOMUX_WIDTH_2BIT,
4199 IOMUX_WIDTH_2BIT,
4200 IOMUX_WIDTH_2BIT),
4201 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4202 IOMUX_WIDTH_2BIT,
4203 IOMUX_WIDTH_2BIT,
4204 IOMUX_WIDTH_2BIT),
4205 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4206 IOMUX_WIDTH_2BIT,
4207 IOMUX_WIDTH_2BIT,
4208 IOMUX_WIDTH_2BIT),
4209 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4210 IOMUX_WIDTH_2BIT,
4211 IOMUX_WIDTH_2BIT,
4212 IOMUX_WIDTH_2BIT),
4213 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4214 IOMUX_WIDTH_2BIT,
4215 IOMUX_WIDTH_2BIT,
4216 IOMUX_WIDTH_2BIT),
4217};
4218
4219static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4220 .pin_banks = rk3308_pin_banks,
4221 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
4222 .label = "RK3308-GPIO",
4223 .type = RK3308,
4224 .grf_mux_offset = 0x0,
4225 .iomux_recalced = rk3308_mux_recalced_data,
4226 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4227 .iomux_routes = rk3308_mux_route_data,
4228 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4229 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4230 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4231 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
4232};
4233
4234static struct rockchip_pin_bank rk3328_pin_banks[] = {
4235 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4236 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4237 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4238 IOMUX_WIDTH_2BIT,
4239 IOMUX_WIDTH_3BIT,
4240 0),
4241 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4242 IOMUX_WIDTH_3BIT,
4243 IOMUX_WIDTH_3BIT,
4244 0,
4245 0),
4246};
4247
4248static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4249 .pin_banks = rk3328_pin_banks,
4250 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
4251 .label = "RK3328-GPIO",
4252 .type = RK3328,
4253 .grf_mux_offset = 0x0,
4254 .iomux_recalced = rk3328_mux_recalced_data,
4255 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
4256 .iomux_routes = rk3328_mux_route_data,
4257 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
4258 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4259 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4260 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
4261};
4262
4263static struct rockchip_pin_bank rk3368_pin_banks[] = {
4264 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4265 IOMUX_SOURCE_PMU,
4266 IOMUX_SOURCE_PMU,
4267 IOMUX_SOURCE_PMU
4268 ),
4269 PIN_BANK(1, 32, "gpio1"),
4270 PIN_BANK(2, 32, "gpio2"),
4271 PIN_BANK(3, 32, "gpio3"),
4272};
4273
4274static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4275 .pin_banks = rk3368_pin_banks,
4276 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
4277 .label = "RK3368-GPIO",
4278 .type = RK3368,
4279 .grf_mux_offset = 0x0,
4280 .pmu_mux_offset = 0x0,
4281 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
4282 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
4283};
4284
4285static struct rockchip_pin_bank rk3399_pin_banks[] = {
4286 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4287 IOMUX_SOURCE_PMU,
4288 IOMUX_SOURCE_PMU,
4289 IOMUX_SOURCE_PMU,
4290 IOMUX_SOURCE_PMU,
4291 DRV_TYPE_IO_1V8_ONLY,
4292 DRV_TYPE_IO_1V8_ONLY,
4293 DRV_TYPE_IO_DEFAULT,
4294 DRV_TYPE_IO_DEFAULT,
4295 0x80,
4296 0x88,
4297 -1,
4298 -1,
4299 PULL_TYPE_IO_1V8_ONLY,
4300 PULL_TYPE_IO_1V8_ONLY,
4301 PULL_TYPE_IO_DEFAULT,
4302 PULL_TYPE_IO_DEFAULT
4303 ),
4304 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4305 IOMUX_SOURCE_PMU,
4306 IOMUX_SOURCE_PMU,
4307 IOMUX_SOURCE_PMU,
4308 DRV_TYPE_IO_1V8_OR_3V0,
4309 DRV_TYPE_IO_1V8_OR_3V0,
4310 DRV_TYPE_IO_1V8_OR_3V0,
4311 DRV_TYPE_IO_1V8_OR_3V0,
4312 0xa0,
4313 0xa8,
4314 0xb0,
4315 0xb8
4316 ),
4317 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4318 DRV_TYPE_IO_1V8_OR_3V0,
4319 DRV_TYPE_IO_1V8_ONLY,
4320 DRV_TYPE_IO_1V8_ONLY,
4321 PULL_TYPE_IO_DEFAULT,
4322 PULL_TYPE_IO_DEFAULT,
4323 PULL_TYPE_IO_1V8_ONLY,
4324 PULL_TYPE_IO_1V8_ONLY
4325 ),
4326 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4327 DRV_TYPE_IO_3V3_ONLY,
4328 DRV_TYPE_IO_3V3_ONLY,
4329 DRV_TYPE_IO_1V8_OR_3V0
4330 ),
4331 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4332 DRV_TYPE_IO_1V8_3V0_AUTO,
4333 DRV_TYPE_IO_1V8_OR_3V0,
4334 DRV_TYPE_IO_1V8_OR_3V0
4335 ),
4336};
4337
4338static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4339 .pin_banks = rk3399_pin_banks,
4340 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
4341 .label = "RK3399-GPIO",
4342 .type = RK3399,
4343 .grf_mux_offset = 0xe000,
4344 .pmu_mux_offset = 0x0,
4345 .grf_drv_offset = 0xe100,
4346 .pmu_drv_offset = 0x80,
4347 .iomux_routes = rk3399_mux_route_data,
4348 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
4349 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
4350 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4351};
4352
4353static struct rockchip_pin_bank rk3528_pin_banks[] = {
4354 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
4355 IOMUX_WIDTH_4BIT,
4356 IOMUX_WIDTH_4BIT,
4357 IOMUX_WIDTH_4BIT,
4358 IOMUX_WIDTH_4BIT,
4359 0, 0, 0, 0),
4360 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4361 IOMUX_WIDTH_4BIT,
4362 IOMUX_WIDTH_4BIT,
4363 IOMUX_WIDTH_4BIT,
4364 IOMUX_WIDTH_4BIT,
4365 0x20020, 0x20028, 0x20030, 0x20038),
4366 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4367 IOMUX_WIDTH_4BIT,
4368 IOMUX_WIDTH_4BIT,
4369 IOMUX_WIDTH_4BIT,
4370 IOMUX_WIDTH_4BIT,
4371 0x30040, 0, 0, 0),
4372 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4373 IOMUX_WIDTH_4BIT,
4374 IOMUX_WIDTH_4BIT,
4375 IOMUX_WIDTH_4BIT,
4376 IOMUX_WIDTH_4BIT,
4377 0x20060, 0x20068, 0x20070, 0),
4378 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
4379 IOMUX_WIDTH_4BIT,
4380 IOMUX_WIDTH_4BIT,
4381 IOMUX_WIDTH_4BIT,
4382 IOMUX_WIDTH_4BIT,
4383 0x10080, 0x10088, 0x10090, 0x10098),
4384};
4385
4386static struct rockchip_pin_ctrl rk3528_pin_ctrl = {
4387 .pin_banks = rk3528_pin_banks,
4388 .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
4389 .label = "RK3528-GPIO",
4390 .type = RK3528,
4391 .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
4392 .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
4393 .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
4394};
4395
4396static struct rockchip_pin_bank rk3562_pin_banks[] = {
4397 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
4398 IOMUX_WIDTH_4BIT,
4399 IOMUX_WIDTH_4BIT,
4400 IOMUX_WIDTH_4BIT,
4401 IOMUX_WIDTH_4BIT,
4402 0x20000, 0x20008, 0x20010, 0x20018),
4403 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4404 IOMUX_WIDTH_4BIT,
4405 IOMUX_WIDTH_4BIT,
4406 IOMUX_WIDTH_4BIT,
4407 IOMUX_WIDTH_4BIT,
4408 0, 0x08, 0x10, 0x18),
4409 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4410 IOMUX_WIDTH_4BIT,
4411 IOMUX_WIDTH_4BIT,
4412 IOMUX_WIDTH_4BIT,
4413 IOMUX_WIDTH_4BIT,
4414 0x20, 0, 0, 0),
4415 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4416 IOMUX_WIDTH_4BIT,
4417 IOMUX_WIDTH_4BIT,
4418 IOMUX_WIDTH_4BIT,
4419 IOMUX_WIDTH_4BIT,
4420 0x10040, 0x10048, 0x10050, 0x10058),
4421 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
4422 IOMUX_WIDTH_4BIT,
4423 IOMUX_WIDTH_4BIT,
4424 0,
4425 0,
4426 0x10060, 0x10068, 0, 0),
4427};
4428
4429static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
4430 .pin_banks = rk3562_pin_banks,
4431 .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
4432 .label = "RK3562-GPIO",
4433 .type = RK3562,
4434 .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
4435 .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
4436 .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
4437};
4438
4439static struct rockchip_pin_bank rk3568_pin_banks[] = {
4440 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4441 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4442 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4443 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4444 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4445 IOMUX_WIDTH_4BIT,
4446 IOMUX_WIDTH_4BIT,
4447 IOMUX_WIDTH_4BIT),
4448 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4449 IOMUX_WIDTH_4BIT,
4450 IOMUX_WIDTH_4BIT,
4451 IOMUX_WIDTH_4BIT),
4452 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4453 IOMUX_WIDTH_4BIT,
4454 IOMUX_WIDTH_4BIT,
4455 IOMUX_WIDTH_4BIT),
4456 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4457 IOMUX_WIDTH_4BIT,
4458 IOMUX_WIDTH_4BIT,
4459 IOMUX_WIDTH_4BIT),
4460};
4461
4462static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
4463 .pin_banks = rk3568_pin_banks,
4464 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
4465 .label = "RK3568-GPIO",
4466 .type = RK3568,
4467 .grf_mux_offset = 0x0,
4468 .pmu_mux_offset = 0x0,
4469 .grf_drv_offset = 0x0200,
4470 .pmu_drv_offset = 0x0070,
4471 .iomux_routes = rk3568_mux_route_data,
4472 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
4473 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
4474 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
4475 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4476};
4477
4478#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
4479 PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
4480 IOMUX_WIDTH_4BIT, \
4481 IOMUX_WIDTH_4BIT, \
4482 IOMUX_WIDTH_4BIT, \
4483 IOMUX_WIDTH_4BIT, \
4484 OFFSET0, OFFSET1, \
4485 OFFSET2, OFFSET3, \
4486 PULL_TYPE_IO_1V8_ONLY, \
4487 PULL_TYPE_IO_1V8_ONLY, \
4488 PULL_TYPE_IO_1V8_ONLY, \
4489 PULL_TYPE_IO_1V8_ONLY)
4490
4491static struct rockchip_pin_bank rk3576_pin_banks[] = {
4492 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
4493 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
4494 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
4495 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
4496 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
4497};
4498
4499static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
4500 .pin_banks = rk3576_pin_banks,
4501 .nr_banks = ARRAY_SIZE(rk3576_pin_banks),
4502 .label = "RK3576-GPIO",
4503 .type = RK3576,
4504 .pull_calc_reg = rk3576_calc_pull_reg_and_bit,
4505 .drv_calc_reg = rk3576_calc_drv_reg_and_bit,
4506 .schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
4507};
4508
4509static struct rockchip_pin_bank rk3588_pin_banks[] = {
4510 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
4511 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4512 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
4513 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4514 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
4515 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4516 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
4517 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4518 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
4519 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4520};
4521
4522static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
4523 .pin_banks = rk3588_pin_banks,
4524 .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
4525 .label = "RK3588-GPIO",
4526 .type = RK3588,
4527 .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
4528 .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
4529 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
4530};
4531
4532static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4533 { .compatible = "rockchip,px30-pinctrl",
4534 .data = &px30_pin_ctrl },
4535 { .compatible = "rockchip,rv1108-pinctrl",
4536 .data = &rv1108_pin_ctrl },
4537 { .compatible = "rockchip,rv1126-pinctrl",
4538 .data = &rv1126_pin_ctrl },
4539 { .compatible = "rockchip,rk2928-pinctrl",
4540 .data = &rk2928_pin_ctrl },
4541 { .compatible = "rockchip,rk3036-pinctrl",
4542 .data = &rk3036_pin_ctrl },
4543 { .compatible = "rockchip,rk3066a-pinctrl",
4544 .data = &rk3066a_pin_ctrl },
4545 { .compatible = "rockchip,rk3066b-pinctrl",
4546 .data = &rk3066b_pin_ctrl },
4547 { .compatible = "rockchip,rk3128-pinctrl",
4548 .data = (void *)&rk3128_pin_ctrl },
4549 { .compatible = "rockchip,rk3188-pinctrl",
4550 .data = &rk3188_pin_ctrl },
4551 { .compatible = "rockchip,rk3228-pinctrl",
4552 .data = &rk3228_pin_ctrl },
4553 { .compatible = "rockchip,rk3288-pinctrl",
4554 .data = &rk3288_pin_ctrl },
4555 { .compatible = "rockchip,rk3308-pinctrl",
4556 .data = &rk3308_pin_ctrl },
4557 { .compatible = "rockchip,rk3328-pinctrl",
4558 .data = &rk3328_pin_ctrl },
4559 { .compatible = "rockchip,rk3368-pinctrl",
4560 .data = &rk3368_pin_ctrl },
4561 { .compatible = "rockchip,rk3399-pinctrl",
4562 .data = &rk3399_pin_ctrl },
4563 { .compatible = "rockchip,rk3528-pinctrl",
4564 .data = &rk3528_pin_ctrl },
4565 { .compatible = "rockchip,rk3562-pinctrl",
4566 .data = &rk3562_pin_ctrl },
4567 { .compatible = "rockchip,rk3568-pinctrl",
4568 .data = &rk3568_pin_ctrl },
4569 { .compatible = "rockchip,rk3576-pinctrl",
4570 .data = &rk3576_pin_ctrl },
4571 { .compatible = "rockchip,rk3588-pinctrl",
4572 .data = &rk3588_pin_ctrl },
4573 {},
4574};
4575
4576static struct platform_driver rockchip_pinctrl_driver = {
4577 .probe = rockchip_pinctrl_probe,
4578 .remove = rockchip_pinctrl_remove,
4579 .driver = {
4580 .name = "rockchip-pinctrl",
4581 .pm = &rockchip_pinctrl_dev_pm_ops,
4582 .of_match_table = rockchip_pinctrl_dt_match,
4583 },
4584};
4585
4586static int __init rockchip_pinctrl_drv_register(void)
4587{
4588 return platform_driver_register(&rockchip_pinctrl_driver);
4589}
4590postcore_initcall(rockchip_pinctrl_drv_register);
4591
4592static void __exit rockchip_pinctrl_drv_unregister(void)
4593{
4594 platform_driver_unregister(&rockchip_pinctrl_driver);
4595}
4596module_exit(rockchip_pinctrl_drv_unregister);
4597
4598MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4599MODULE_LICENSE("GPL");
4600MODULE_ALIAS("platform:pinctrl-rockchip");
4601MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
4602

source code of linux/drivers/pinctrl/pinctrl-rockchip.c