1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/acpi.h>
14#include <linux/array_size.h>
15#include <linux/bitfield.h>
16#include <linux/bits.h>
17#include <linux/debugfs.h>
18#include <linux/delay.h>
19#include <linux/io.h>
20#include <linux/iopoll.h>
21#include <linux/limits.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/platform_device.h>
25#include <linux/rtc.h>
26#include <linux/serio.h>
27#include <linux/suspend.h>
28#include <linux/seq_file.h>
29#include <linux/uaccess.h>
30
31#include <asm/amd/node.h>
32
33#include "pmc.h"
34
35static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {
36 {"DISPLAY", BIT(0)},
37 {"CPU", BIT(1)},
38 {"GFX", BIT(2)},
39 {"VDD", BIT(3)},
40 {"VDD_CCX", BIT(4)},
41 {"ACP", BIT(5)},
42 {"VCN_0", BIT(6)},
43 {"VCN_1", BIT(7)},
44 {"ISP", BIT(8)},
45 {"NBIO", BIT(9)},
46 {"DF", BIT(10)},
47 {"USB3_0", BIT(11)},
48 {"USB3_1", BIT(12)},
49 {"LAPIC", BIT(13)},
50 {"USB3_2", BIT(14)},
51 {"USB4_RT0", BIT(15)},
52 {"USB4_RT1", BIT(16)},
53 {"USB4_0", BIT(17)},
54 {"USB4_1", BIT(18)},
55 {"MPM", BIT(19)},
56 {"JPEG_0", BIT(20)},
57 {"JPEG_1", BIT(21)},
58 {"IPU", BIT(22)},
59 {"UMSCH", BIT(23)},
60 {"VPE", BIT(24)},
61};
62
63static const struct amd_pmc_bit_map soc15_ip_blk[] = {
64 {"DISPLAY", BIT(0)},
65 {"CPU", BIT(1)},
66 {"GFX", BIT(2)},
67 {"VDD", BIT(3)},
68 {"ACP", BIT(4)},
69 {"VCN", BIT(5)},
70 {"ISP", BIT(6)},
71 {"NBIO", BIT(7)},
72 {"DF", BIT(8)},
73 {"USB3_0", BIT(9)},
74 {"USB3_1", BIT(10)},
75 {"LAPIC", BIT(11)},
76 {"USB3_2", BIT(12)},
77 {"USB3_3", BIT(13)},
78 {"USB3_4", BIT(14)},
79 {"USB4_0", BIT(15)},
80 {"USB4_1", BIT(16)},
81 {"MPM", BIT(17)},
82 {"JPEG", BIT(18)},
83 {"IPU", BIT(19)},
84 {"UMSCH", BIT(20)},
85 {"VPE", BIT(21)},
86};
87
88static bool disable_workarounds;
89module_param(disable_workarounds, bool, 0644);
90MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
91
92static struct amd_pmc_dev pmc;
93
94static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
95{
96 return ioread32(dev->regbase + reg_offset);
97}
98
99static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
100{
101 iowrite32(val, dev->regbase + reg_offset);
102}
103
104static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
105{
106 switch (dev->cpu_id) {
107 case AMD_CPU_ID_PCO:
108 case AMD_CPU_ID_RN:
109 case AMD_CPU_ID_YC:
110 case AMD_CPU_ID_CB:
111 dev->num_ips = 12;
112 dev->ips_ptr = soc15_ip_blk;
113 dev->smu_msg = 0x538;
114 break;
115 case AMD_CPU_ID_PS:
116 dev->num_ips = 21;
117 dev->ips_ptr = soc15_ip_blk;
118 dev->smu_msg = 0x538;
119 break;
120 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
121 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
122 if (boot_cpu_data.x86_model == 0x70) {
123 dev->num_ips = ARRAY_SIZE(soc15_ip_blk_v2);
124 dev->ips_ptr = soc15_ip_blk_v2;
125 } else {
126 dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
127 dev->ips_ptr = soc15_ip_blk;
128 }
129 dev->smu_msg = 0x938;
130 break;
131 }
132}
133
134static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
135{
136 if (dev->cpu_id == AMD_CPU_ID_PCO) {
137 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
138 return -EINVAL;
139 }
140
141 /* Get Active devices list from SMU */
142 if (!dev->active_ips)
143 amd_pmc_send_cmd(dev, arg: 0, data: &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, ret: true);
144
145 /* Get dram address */
146 if (!dev->smu_virt_addr) {
147 u32 phys_addr_low, phys_addr_hi;
148 u64 smu_phys_addr;
149
150 amd_pmc_send_cmd(dev, arg: 0, data: &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, ret: true);
151 amd_pmc_send_cmd(dev, arg: 0, data: &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, ret: true);
152 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
153
154 dev->smu_virt_addr = devm_ioremap(dev: dev->dev, offset: smu_phys_addr,
155 size: sizeof(struct smu_metrics));
156 if (!dev->smu_virt_addr)
157 return -ENOMEM;
158 }
159
160 /* Start the logging */
161 amd_pmc_send_cmd(dev, arg: 0, NULL, SMU_MSG_LOG_RESET, ret: false);
162 amd_pmc_send_cmd(dev, arg: 0, NULL, SMU_MSG_LOG_START, ret: false);
163
164 return 0;
165}
166
167static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
168{
169 int rc;
170
171 if (!pdev->smu_virt_addr) {
172 rc = amd_pmc_setup_smu_logging(dev: pdev);
173 if (rc)
174 return rc;
175 }
176
177 if (pdev->cpu_id == AMD_CPU_ID_PCO)
178 return -ENODEV;
179 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
180 return 0;
181}
182
183static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
184{
185 struct smu_metrics table;
186
187 if (get_metrics_table(pdev, table: &table))
188 return;
189
190 if (!table.s0i3_last_entry_status)
191 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
192 pm_report_hw_sleep_time(t: table.s0i3_last_entry_status ?
193 table.timein_s0i3_lastcapture : 0);
194}
195
196static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
197{
198 int rc;
199 u32 val;
200
201 if (dev->cpu_id == AMD_CPU_ID_PCO)
202 return -ENODEV;
203
204 rc = amd_pmc_send_cmd(dev, arg: 0, data: &val, SMU_MSG_GETSMUVERSION, ret: true);
205 if (rc)
206 return rc;
207
208 dev->smu_program = (val >> 24) & GENMASK(7, 0);
209 dev->major = (val >> 16) & GENMASK(7, 0);
210 dev->minor = (val >> 8) & GENMASK(7, 0);
211 dev->rev = (val >> 0) & GENMASK(7, 0);
212
213 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
214 dev->smu_program, dev->major, dev->minor, dev->rev);
215
216 return 0;
217}
218
219static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
220 char *buf)
221{
222 struct amd_pmc_dev *dev = dev_get_drvdata(dev: d);
223 int rc;
224
225 if (!dev->major) {
226 rc = amd_pmc_get_smu_version(dev);
227 if (rc)
228 return rc;
229 }
230 return sysfs_emit(buf, fmt: "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
231}
232
233static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
234 char *buf)
235{
236 struct amd_pmc_dev *dev = dev_get_drvdata(dev: d);
237 int rc;
238
239 if (!dev->major) {
240 rc = amd_pmc_get_smu_version(dev);
241 if (rc)
242 return rc;
243 }
244 return sysfs_emit(buf, fmt: "%u\n", dev->smu_program);
245}
246
247static DEVICE_ATTR_RO(smu_fw_version);
248static DEVICE_ATTR_RO(smu_program);
249
250static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
251{
252 struct device *dev = kobj_to_dev(kobj);
253 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
254
255 if (pdev->cpu_id == AMD_CPU_ID_PCO)
256 return 0;
257 return 0444;
258}
259
260static struct attribute *pmc_attrs[] = {
261 &dev_attr_smu_fw_version.attr,
262 &dev_attr_smu_program.attr,
263 NULL,
264};
265
266static struct attribute_group pmc_attr_group = {
267 .attrs = pmc_attrs,
268 .is_visible = pmc_attr_is_visible,
269};
270
271static const struct attribute_group *pmc_groups[] = {
272 &pmc_attr_group,
273 NULL,
274};
275
276static int smu_fw_info_show(struct seq_file *s, void *unused)
277{
278 struct amd_pmc_dev *dev = s->private;
279 struct smu_metrics table;
280 int idx;
281
282 if (get_metrics_table(pdev: dev, table: &table))
283 return -EINVAL;
284
285 seq_puts(m: s, s: "\n=== SMU Statistics ===\n");
286 seq_printf(m: s, fmt: "Table Version: %d\n", table.table_version);
287 seq_printf(m: s, fmt: "Hint Count: %d\n", table.hint_count);
288 seq_printf(m: s, fmt: "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
289 "Unknown/Fail");
290 seq_printf(m: s, fmt: "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
291 seq_printf(m: s, fmt: "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
292 seq_printf(m: s, fmt: "Time (in us) to resume from S0i3: %lld\n",
293 table.timeto_resume_to_os_lastcapture);
294
295 seq_puts(m: s, s: "\n=== Active time (in us) ===\n");
296 for (idx = 0 ; idx < dev->num_ips ; idx++) {
297 if (dev->ips_ptr[idx].bit_mask & dev->active_ips)
298 seq_printf(m: s, fmt: "%-8s : %lld\n", dev->ips_ptr[idx].name,
299 table.timecondition_notmet_lastcapture[idx]);
300 }
301
302 return 0;
303}
304DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
305
306static int s0ix_stats_show(struct seq_file *s, void *unused)
307{
308 struct amd_pmc_dev *dev = s->private;
309 u64 entry_time, exit_time, residency;
310
311 /* Use FCH registers to get the S0ix stats */
312 if (!dev->fch_virt_addr) {
313 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
314 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
315 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
316
317 dev->fch_virt_addr = devm_ioremap(dev: dev->dev, offset: fch_phys_addr, FCH_SSC_MAPPING_SIZE);
318 if (!dev->fch_virt_addr)
319 return -ENOMEM;
320 }
321
322 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
323 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
324
325 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
326 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
327
328 /* It's in 48MHz. We need to convert it */
329 residency = exit_time - entry_time;
330 do_div(residency, 48);
331
332 seq_puts(m: s, s: "=== S0ix statistics ===\n");
333 seq_printf(m: s, fmt: "S0ix Entry Time: %lld\n", entry_time);
334 seq_printf(m: s, fmt: "S0ix Exit Time: %lld\n", exit_time);
335 seq_printf(m: s, fmt: "Residency Time: %lld\n", residency);
336
337 return 0;
338}
339DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
340
341static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
342 struct seq_file *s)
343{
344 u32 val;
345 int rc;
346
347 switch (pdev->cpu_id) {
348 case AMD_CPU_ID_CZN:
349 /* we haven't yet read SMU version */
350 if (!pdev->major) {
351 rc = amd_pmc_get_smu_version(dev: pdev);
352 if (rc)
353 return rc;
354 }
355 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
356 val = amd_pmc_reg_read(dev: pdev, AMD_PMC_SCRATCH_REG_CZN);
357 else
358 return -EINVAL;
359 break;
360 case AMD_CPU_ID_YC:
361 case AMD_CPU_ID_CB:
362 case AMD_CPU_ID_PS:
363 val = amd_pmc_reg_read(dev: pdev, AMD_PMC_SCRATCH_REG_YC);
364 break;
365 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
366 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
367 val = amd_pmc_reg_read(dev: pdev, AMD_PMC_SCRATCH_REG_1AH);
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 if (dev)
374 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
375
376 if (s)
377 seq_printf(m: s, fmt: "SMU idlemask : 0x%x\n", val);
378
379 return 0;
380}
381
382static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
383{
384 return amd_pmc_idlemask_read(pdev: s->private, NULL, s);
385}
386DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
387
388static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
389{
390 debugfs_remove_recursive(dentry: dev->dbgfs_dir);
391}
392
393static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
394{
395 dev->dbgfs_dir = debugfs_create_dir(name: "amd_pmc", NULL);
396 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
397 &smu_fw_info_fops);
398 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
399 &s0ix_stats_fops);
400 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
401 &amd_pmc_idlemask_fops);
402}
403
404static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev)
405{
406 switch (dev->msg_port) {
407 case MSG_PORT_PMC:
408 return "PMC";
409 case MSG_PORT_S2D:
410 return "S2D";
411 default:
412 return "Invalid message port";
413 }
414}
415
416static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
417{
418 u32 value, message, argument, response;
419
420 if (dev->msg_port == MSG_PORT_S2D) {
421 message = dev->stb_arg.msg;
422 argument = dev->stb_arg.arg;
423 response = dev->stb_arg.resp;
424 } else {
425 message = dev->smu_msg;
426 argument = AMD_PMC_REGISTER_ARGUMENT;
427 response = AMD_PMC_REGISTER_RESPONSE;
428 }
429
430 value = amd_pmc_reg_read(dev, reg_offset: response);
431 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value);
432
433 value = amd_pmc_reg_read(dev, reg_offset: argument);
434 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value);
435
436 value = amd_pmc_reg_read(dev, reg_offset: message);
437 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value);
438}
439
440int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
441{
442 int rc;
443 u32 val, message, argument, response;
444
445 guard(mutex)(T: &dev->lock);
446
447 if (dev->msg_port == MSG_PORT_S2D) {
448 message = dev->stb_arg.msg;
449 argument = dev->stb_arg.arg;
450 response = dev->stb_arg.resp;
451 } else {
452 message = dev->smu_msg;
453 argument = AMD_PMC_REGISTER_ARGUMENT;
454 response = AMD_PMC_REGISTER_RESPONSE;
455 }
456
457 /* Wait until we get a valid response */
458 rc = readx_poll_timeout(ioread32, dev->regbase + response,
459 val, val != 0, PMC_MSG_DELAY_MIN_US,
460 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
461 if (rc) {
462 dev_err(dev->dev, "failed to talk to SMU\n");
463 return rc;
464 }
465
466 /* Write zero to response register */
467 amd_pmc_reg_write(dev, reg_offset: response, val: 0);
468
469 /* Write argument into response register */
470 amd_pmc_reg_write(dev, reg_offset: argument, val: arg);
471
472 /* Write message ID to message ID register */
473 amd_pmc_reg_write(dev, reg_offset: message, val: msg);
474
475 /* Wait until we get a valid response */
476 rc = readx_poll_timeout(ioread32, dev->regbase + response,
477 val, val != 0, PMC_MSG_DELAY_MIN_US,
478 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
479 if (rc) {
480 dev_err(dev->dev, "SMU response timed out\n");
481 return rc;
482 }
483
484 switch (val) {
485 case AMD_PMC_RESULT_OK:
486 if (ret) {
487 /* PMFW may take longer time to return back the data */
488 usleep_range(DELAY_MIN_US, max: 10 * DELAY_MAX_US);
489 *data = amd_pmc_reg_read(dev, reg_offset: argument);
490 }
491 break;
492 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
493 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
494 rc = -EBUSY;
495 break;
496 case AMD_PMC_RESULT_CMD_UNKNOWN:
497 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
498 rc = -EINVAL;
499 break;
500 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
501 case AMD_PMC_RESULT_FAILED:
502 default:
503 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
504 rc = -EIO;
505 break;
506 }
507
508 amd_pmc_dump_registers(dev);
509 return rc;
510}
511
512static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
513{
514 switch (dev->cpu_id) {
515 case AMD_CPU_ID_PCO:
516 return MSG_OS_HINT_PCO;
517 case AMD_CPU_ID_RN:
518 case AMD_CPU_ID_YC:
519 case AMD_CPU_ID_CB:
520 case AMD_CPU_ID_PS:
521 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
522 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
523 return MSG_OS_HINT_RN;
524 }
525 return -EINVAL;
526}
527
528static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
529{
530 struct device *d;
531 int rc;
532
533 /* cezanne platform firmware has a fix in 64.66.0 */
534 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
535 if (!pdev->major) {
536 rc = amd_pmc_get_smu_version(dev: pdev);
537 if (rc)
538 return rc;
539 }
540
541 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
542 return 0;
543 }
544
545 d = bus_find_device_by_name(bus: &serio_bus, NULL, name: "serio0");
546 if (!d)
547 return 0;
548 if (device_may_wakeup(dev: d)) {
549 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
550 disable_irq_wake(irq: 1);
551 device_set_wakeup_enable(dev: d, enable: false);
552 }
553 put_device(dev: d);
554
555 return 0;
556}
557
558static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
559{
560 struct rtc_device *rtc_device;
561 time64_t then, now, duration;
562 struct rtc_wkalrm alarm;
563 struct rtc_time tm;
564 int rc;
565
566 /* we haven't yet read SMU version */
567 if (!pdev->major) {
568 rc = amd_pmc_get_smu_version(dev: pdev);
569 if (rc)
570 return rc;
571 }
572
573 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
574 return 0;
575
576 rtc_device = rtc_class_open(name: "rtc0");
577 if (!rtc_device)
578 return 0;
579 rc = rtc_read_alarm(rtc: rtc_device, alrm: &alarm);
580 if (rc)
581 return rc;
582 if (!alarm.enabled) {
583 dev_dbg(pdev->dev, "alarm not enabled\n");
584 return 0;
585 }
586 rc = rtc_read_time(rtc: rtc_device, tm: &tm);
587 if (rc)
588 return rc;
589 then = rtc_tm_to_time64(tm: &alarm.time);
590 now = rtc_tm_to_time64(tm: &tm);
591 duration = then-now;
592
593 /* in the past */
594 if (then < now)
595 return 0;
596
597 /* will be stored in upper 16 bits of s0i3 hint argument,
598 * so timer wakeup from s0i3 is limited to ~18 hours or less
599 */
600 if (duration <= 4 || duration > U16_MAX)
601 return -EINVAL;
602
603 *arg |= (duration << 16);
604 rc = rtc_alarm_irq_enable(rtc: rtc_device, enabled: 0);
605 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
606
607 return rc;
608}
609
610static void amd_pmc_s2idle_prepare(void)
611{
612 struct amd_pmc_dev *pdev = &pmc;
613 int rc;
614 u8 msg;
615 u32 arg = 1;
616
617 /* Reset and Start SMU logging - to monitor the s0i3 stats */
618 amd_pmc_setup_smu_logging(dev: pdev);
619
620 /* Activate CZN specific platform bug workarounds */
621 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
622 rc = amd_pmc_verify_czn_rtc(pdev, arg: &arg);
623 if (rc) {
624 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
625 return;
626 }
627 }
628
629 msg = amd_pmc_get_os_hint(dev: pdev);
630 rc = amd_pmc_send_cmd(dev: pdev, arg, NULL, msg, ret: false);
631 if (rc) {
632 dev_err(pdev->dev, "suspend failed: %d\n", rc);
633 return;
634 }
635
636 rc = amd_stb_write(dev: pdev, AMD_PMC_STB_S2IDLE_PREPARE);
637 if (rc)
638 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
639}
640
641static void amd_pmc_s2idle_check(void)
642{
643 struct amd_pmc_dev *pdev = &pmc;
644 struct smu_metrics table;
645 int rc;
646
647 /* Avoid triggering OVP */
648 if (!get_metrics_table(pdev, table: &table) && table.s0i3_last_entry_status)
649 msleep(msecs: 2500);
650
651 /* Dump the IdleMask before we add to the STB */
652 amd_pmc_idlemask_read(pdev, dev: pdev->dev, NULL);
653
654 rc = amd_stb_write(dev: pdev, AMD_PMC_STB_S2IDLE_CHECK);
655 if (rc)
656 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
657}
658
659static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
660{
661 if (pdev->cpu_id == AMD_CPU_ID_PCO)
662 return -ENODEV;
663
664 return amd_pmc_send_cmd(dev: pdev, arg: 0, NULL, SMU_MSG_LOG_DUMP_DATA, ret: false);
665}
666
667static void amd_pmc_s2idle_restore(void)
668{
669 struct amd_pmc_dev *pdev = &pmc;
670 int rc;
671 u8 msg;
672
673 msg = amd_pmc_get_os_hint(dev: pdev);
674 rc = amd_pmc_send_cmd(dev: pdev, arg: 0, NULL, msg, ret: false);
675 if (rc)
676 dev_err(pdev->dev, "resume failed: %d\n", rc);
677
678 /* Let SMU know that we are looking for stats */
679 amd_pmc_dump_data(pdev);
680
681 rc = amd_stb_write(dev: pdev, AMD_PMC_STB_S2IDLE_RESTORE);
682 if (rc)
683 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
684
685 /* Notify on failed entry */
686 amd_pmc_validate_deepest(pdev);
687
688 amd_pmc_process_restore_quirks(dev: pdev);
689}
690
691static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
692 .prepare = amd_pmc_s2idle_prepare,
693 .check = amd_pmc_s2idle_check,
694 .restore = amd_pmc_s2idle_restore,
695};
696
697static int amd_pmc_suspend_handler(struct device *dev)
698{
699 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
700 int rc;
701
702 /*
703 * Must be called only from the same set of dev_pm_ops handlers
704 * as i8042_pm_suspend() is called: currently just from .suspend.
705 */
706 if (pdev->disable_8042_wakeup && !disable_workarounds) {
707 rc = amd_pmc_wa_irq1(pdev);
708 if (rc) {
709 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
710 return rc;
711 }
712 }
713
714 return 0;
715}
716
717static const struct dev_pm_ops amd_pmc_pm = {
718 .suspend = amd_pmc_suspend_handler,
719};
720
721static const struct pci_device_id pmc_pci_ids[] = {
722 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
723 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
724 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
725 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
726 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
727 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
728 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
729 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
730 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
731 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
732 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
733 { }
734};
735
736static int amd_pmc_probe(struct platform_device *pdev)
737{
738 struct amd_pmc_dev *dev = &pmc;
739 struct pci_dev *rdev;
740 u32 base_addr_lo, base_addr_hi;
741 u64 base_addr;
742 int err;
743 u32 val;
744
745 dev->dev = &pdev->dev;
746 rdev = pci_get_domain_bus_and_slot(domain: 0, bus: 0, PCI_DEVFN(0, 0));
747 if (!rdev || !pci_match_id(ids: pmc_pci_ids, dev: rdev)) {
748 err = -ENODEV;
749 goto err_pci_dev_put;
750 }
751
752 dev->cpu_id = rdev->device;
753 if (dev->cpu_id == AMD_CPU_ID_SP || dev->cpu_id == AMD_CPU_ID_SHP) {
754 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
755 err = -ENODEV;
756 goto err_pci_dev_put;
757 }
758
759 dev->rdev = rdev;
760 err = amd_smn_read(node: 0, AMD_PMC_BASE_ADDR_LO, value: &val);
761 if (err) {
762 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
763 err = pcibios_err_to_errno(err);
764 goto err_pci_dev_put;
765 }
766
767 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
768 err = amd_smn_read(node: 0, AMD_PMC_BASE_ADDR_HI, value: &val);
769 if (err) {
770 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
771 err = pcibios_err_to_errno(err);
772 goto err_pci_dev_put;
773 }
774
775 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
776 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
777
778 dev->regbase = devm_ioremap(dev: dev->dev, offset: base_addr + AMD_PMC_BASE_ADDR_OFFSET,
779 AMD_PMC_MAPPING_SIZE);
780 if (!dev->regbase) {
781 err = -ENOMEM;
782 goto err_pci_dev_put;
783 }
784
785 err = devm_mutex_init(dev->dev, &dev->lock);
786 if (err)
787 goto err_pci_dev_put;
788
789 /* Get num of IP blocks within the SoC */
790 amd_pmc_get_ip_info(dev);
791
792 platform_set_drvdata(pdev, data: dev);
793 if (IS_ENABLED(CONFIG_SUSPEND)) {
794 err = acpi_register_lps0_dev(arg: &amd_pmc_s2idle_dev_ops);
795 if (err)
796 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
797 if (!disable_workarounds)
798 amd_pmc_quirks_init(dev);
799 }
800
801 amd_pmc_dbgfs_register(dev);
802 err = amd_stb_s2d_init(dev);
803 if (err)
804 goto err_pci_dev_put;
805
806 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
807 amd_mp2_stb_init(dev);
808 pm_report_max_hw_sleep(U64_MAX);
809 return 0;
810
811err_pci_dev_put:
812 pci_dev_put(dev: rdev);
813 return err;
814}
815
816static void amd_pmc_remove(struct platform_device *pdev)
817{
818 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
819
820 if (IS_ENABLED(CONFIG_SUSPEND))
821 acpi_unregister_lps0_dev(arg: &amd_pmc_s2idle_dev_ops);
822 amd_pmc_dbgfs_unregister(dev);
823 pci_dev_put(dev: dev->rdev);
824 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
825 amd_mp2_stb_deinit(dev);
826}
827
828static const struct acpi_device_id amd_pmc_acpi_ids[] = {
829 {"AMDI0005", 0},
830 {"AMDI0006", 0},
831 {"AMDI0007", 0},
832 {"AMDI0008", 0},
833 {"AMDI0009", 0},
834 {"AMDI000A", 0},
835 {"AMDI000B", 0},
836 {"AMD0004", 0},
837 {"AMD0005", 0},
838 { }
839};
840MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
841
842static struct platform_driver amd_pmc_driver = {
843 .driver = {
844 .name = "amd_pmc",
845 .acpi_match_table = amd_pmc_acpi_ids,
846 .dev_groups = pmc_groups,
847 .pm = pm_sleep_ptr(&amd_pmc_pm),
848 },
849 .probe = amd_pmc_probe,
850 .remove = amd_pmc_remove,
851};
852module_platform_driver(amd_pmc_driver);
853
854MODULE_LICENSE("GPL v2");
855MODULE_DESCRIPTION("AMD PMC Driver");
856

source code of linux/drivers/platform/x86/amd/pmc/pmc.c