1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Driver for the Apple SoC PWM controller
4 *
5 * Copyright The Asahi Linux Contributors
6 *
7 * Limitations:
8 * - The writes to cycle registers are shadowed until a write to
9 * the control register.
10 * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output
11 * is a constant off signal.
12 * - When APPLE_PWM_CTRL is set to 0, the output is constant low
13 */
14
15#include <linux/mod_devicetable.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/math64.h>
22
23#define APPLE_PWM_CTRL 0x00
24#define APPLE_PWM_ON_CYCLES 0x1c
25#define APPLE_PWM_OFF_CYCLES 0x18
26
27#define APPLE_PWM_CTRL_ENABLE BIT(0)
28#define APPLE_PWM_CTRL_MODE BIT(2)
29#define APPLE_PWM_CTRL_UPDATE BIT(5)
30#define APPLE_PWM_CTRL_TRIGGER BIT(9)
31#define APPLE_PWM_CTRL_INVERT BIT(10)
32#define APPLE_PWM_CTRL_OUTPUT_ENABLE BIT(14)
33
34struct apple_pwm {
35 void __iomem *base;
36 u64 clkrate;
37};
38
39static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip)
40{
41 return pwmchip_get_drvdata(chip);
42}
43
44static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
45 const struct pwm_state *state)
46{
47 struct apple_pwm *fpwm;
48
49 if (state->polarity == PWM_POLARITY_INVERSED)
50 return -EINVAL;
51
52 fpwm = to_apple_pwm(chip);
53 if (state->enabled) {
54 u64 on_cycles, off_cycles;
55
56 on_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
57 state->duty_cycle, NSEC_PER_SEC);
58 if (on_cycles > 0xFFFFFFFF)
59 on_cycles = 0xFFFFFFFF;
60
61 off_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
62 state->period, NSEC_PER_SEC) - on_cycles;
63 if (off_cycles > 0xFFFFFFFF)
64 off_cycles = 0xFFFFFFFF;
65
66 writel(val: on_cycles, addr: fpwm->base + APPLE_PWM_ON_CYCLES);
67 writel(val: off_cycles, addr: fpwm->base + APPLE_PWM_OFF_CYCLES);
68 writel(APPLE_PWM_CTRL_ENABLE | APPLE_PWM_CTRL_OUTPUT_ENABLE | APPLE_PWM_CTRL_UPDATE,
69 addr: fpwm->base + APPLE_PWM_CTRL);
70 } else {
71 writel(val: 0, addr: fpwm->base + APPLE_PWM_CTRL);
72 }
73 return 0;
74}
75
76static int apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
77 struct pwm_state *state)
78{
79 struct apple_pwm *fpwm;
80 u32 on_cycles, off_cycles, ctrl;
81
82 fpwm = to_apple_pwm(chip);
83
84 ctrl = readl(addr: fpwm->base + APPLE_PWM_CTRL);
85 on_cycles = readl(addr: fpwm->base + APPLE_PWM_ON_CYCLES);
86 off_cycles = readl(addr: fpwm->base + APPLE_PWM_OFF_CYCLES);
87
88 state->enabled = (ctrl & APPLE_PWM_CTRL_ENABLE) && (ctrl & APPLE_PWM_CTRL_OUTPUT_ENABLE);
89 state->polarity = PWM_POLARITY_NORMAL;
90 // on_cycles + off_cycles is 33 bits, NSEC_PER_SEC is 30, there is no overflow
91 state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);
92 state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) *
93 NSEC_PER_SEC, fpwm->clkrate);
94
95 return 0;
96}
97
98static const struct pwm_ops apple_pwm_ops = {
99 .apply = apple_pwm_apply,
100 .get_state = apple_pwm_get_state,
101};
102
103static int apple_pwm_probe(struct platform_device *pdev)
104{
105 struct pwm_chip *chip;
106 struct apple_pwm *fpwm;
107 struct clk *clk;
108 int ret;
109
110 chip = devm_pwmchip_alloc(parent: &pdev->dev, npwm: 1, sizeof_priv: sizeof(*fpwm));
111 if (IS_ERR(ptr: chip))
112 return PTR_ERR(ptr: chip);
113
114 fpwm = to_apple_pwm(chip);
115
116 fpwm->base = devm_platform_ioremap_resource(pdev, index: 0);
117 if (IS_ERR(ptr: fpwm->base))
118 return PTR_ERR(ptr: fpwm->base);
119
120 clk = devm_clk_get_enabled(dev: &pdev->dev, NULL);
121 if (IS_ERR(ptr: clk))
122 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: clk), fmt: "unable to get the clock");
123
124 /*
125 * Uses the 24MHz system clock on all existing devices, can only
126 * happen if the device tree is broken
127 *
128 * This check is done to prevent an overflow in .apply
129 */
130 fpwm->clkrate = clk_get_rate(clk);
131 if (fpwm->clkrate > NSEC_PER_SEC)
132 return dev_err_probe(dev: &pdev->dev, err: -EINVAL, fmt: "pwm clock out of range");
133
134 chip->ops = &apple_pwm_ops;
135
136 ret = devm_pwmchip_add(&pdev->dev, chip);
137 if (ret < 0)
138 return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "unable to add pwm chip");
139
140 return 0;
141}
142
143static const struct of_device_id apple_pwm_of_match[] = {
144 { .compatible = "apple,s5l-fpwm" },
145 {}
146};
147MODULE_DEVICE_TABLE(of, apple_pwm_of_match);
148
149static struct platform_driver apple_pwm_driver = {
150 .probe = apple_pwm_probe,
151 .driver = {
152 .name = "apple-pwm",
153 .of_match_table = apple_pwm_of_match,
154 },
155};
156module_platform_driver(apple_pwm_driver);
157
158MODULE_DESCRIPTION("Apple SoC PWM driver");
159MODULE_LICENSE("Dual MIT/GPL");
160

source code of linux/drivers/pwm/pwm-apple.c