1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * PWM controller driver for Amlogic Meson SoCs.
4 *
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
16 *
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
18 * controller starting on page 543:
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
21 * datasheet contains the description for this IP block revision starting at
22 * page 1084:
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
24 *
25 * Copyright (c) 2016 BayLibre, SAS.
26 * Author: Neil Armstrong <narmstrong@baylibre.com>
27 * Copyright (C) 2014 Amlogic, Inc.
28 */
29
30#include <linux/bitfield.h>
31#include <linux/bits.h>
32#include <linux/clk.h>
33#include <linux/clk-provider.h>
34#include <linux/err.h>
35#include <linux/io.h>
36#include <linux/kernel.h>
37#include <linux/math64.h>
38#include <linux/module.h>
39#include <linux/of.h>
40#include <linux/platform_device.h>
41#include <linux/pwm.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
44
45#define REG_PWM_A 0x0
46#define REG_PWM_B 0x4
47#define PWM_LOW_MASK GENMASK(15, 0)
48#define PWM_HIGH_MASK GENMASK(31, 16)
49
50#define REG_MISC_AB 0x8
51#define MISC_B_CLK_EN_SHIFT 23
52#define MISC_A_CLK_EN_SHIFT 15
53#define MISC_CLK_DIV_WIDTH 7
54#define MISC_B_CLK_DIV_SHIFT 16
55#define MISC_A_CLK_DIV_SHIFT 8
56#define MISC_B_CLK_SEL_SHIFT 6
57#define MISC_A_CLK_SEL_SHIFT 4
58#define MISC_CLK_SEL_MASK 0x3
59#define MISC_B_EN BIT(1)
60#define MISC_A_EN BIT(0)
61
62#define MESON_NUM_PWMS 2
63#define MESON_NUM_MUX_PARENTS 4
64
65static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u8 clk_en_shift;
70 u32 pwm_en_mask;
71} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_shift = MISC_A_CLK_EN_SHIFT,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_shift = MISC_B_CLK_EN_SHIFT,
84 .pwm_en_mask = MISC_B_EN,
85 }
86};
87
88struct meson_pwm_channel {
89 unsigned long rate;
90 unsigned int hi;
91 unsigned int lo;
92
93 struct clk_mux mux;
94 struct clk_divider div;
95 struct clk_gate gate;
96 struct clk *clk;
97};
98
99struct meson_pwm_data {
100 const char *const parent_names[MESON_NUM_MUX_PARENTS];
101};
102
103struct meson_pwm {
104 const struct meson_pwm_data *data;
105 struct meson_pwm_channel channels[MESON_NUM_PWMS];
106 void __iomem *base;
107 /*
108 * Protects register (write) access to the REG_MISC_AB register
109 * that is shared between the two PWMs.
110 */
111 spinlock_t lock;
112};
113
114static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
115{
116 return pwmchip_get_drvdata(chip);
117}
118
119static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
120{
121 struct meson_pwm *meson = to_meson_pwm(chip);
122 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
123 struct device *dev = pwmchip_parent(chip);
124 int err;
125
126 err = clk_prepare_enable(clk: channel->clk);
127 if (err < 0) {
128 dev_err(dev, "failed to enable clock %s: %d\n",
129 __clk_get_name(channel->clk), err);
130 return err;
131 }
132
133 return 0;
134}
135
136static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
137{
138 struct meson_pwm *meson = to_meson_pwm(chip);
139 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
140
141 clk_disable_unprepare(clk: channel->clk);
142}
143
144static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm,
145 const struct pwm_state *state)
146{
147 struct meson_pwm *meson = to_meson_pwm(chip);
148 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
149 unsigned int cnt, duty_cnt;
150 unsigned long fin_freq;
151 u64 duty, period, freq;
152
153 duty = state->duty_cycle;
154 period = state->period;
155
156 /*
157 * Note this is wrong. The result is an output wave that isn't really
158 * inverted and so is wrongly identified by .get_state as normal.
159 * Fixing this needs some care however as some machines might rely on
160 * this.
161 */
162 if (state->polarity == PWM_POLARITY_INVERSED)
163 duty = period - duty;
164
165 freq = div64_u64(NSEC_PER_SEC * 0xffffULL, divisor: period);
166 if (freq > ULONG_MAX)
167 freq = ULONG_MAX;
168
169 fin_freq = clk_round_rate(clk: channel->clk, rate: freq);
170 if (fin_freq == 0) {
171 dev_err(pwmchip_parent(chip), "invalid source clock frequency\n");
172 return -EINVAL;
173 }
174
175 dev_dbg(pwmchip_parent(chip), "fin_freq: %lu Hz\n", fin_freq);
176
177 cnt = div_u64(dividend: fin_freq * period, NSEC_PER_SEC);
178 if (cnt > 0xffff) {
179 dev_err(pwmchip_parent(chip), "unable to get period cnt\n");
180 return -EINVAL;
181 }
182
183 dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt);
184
185 if (duty == period) {
186 channel->hi = cnt;
187 channel->lo = 0;
188 } else if (duty == 0) {
189 channel->hi = 0;
190 channel->lo = cnt;
191 } else {
192 duty_cnt = div_u64(dividend: fin_freq * duty, NSEC_PER_SEC);
193
194 dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
195
196 channel->hi = duty_cnt;
197 channel->lo = cnt - duty_cnt;
198 }
199
200 channel->rate = fin_freq;
201
202 return 0;
203}
204
205static void meson_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
206{
207 struct meson_pwm *meson = to_meson_pwm(chip);
208 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
209 struct meson_pwm_channel_data *channel_data;
210 unsigned long flags;
211 u32 value;
212 int err;
213
214 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
215
216 err = clk_set_rate(clk: channel->clk, rate: channel->rate);
217 if (err)
218 dev_err(pwmchip_parent(chip), "setting clock rate failed\n");
219
220 spin_lock_irqsave(&meson->lock, flags);
221
222 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
223 FIELD_PREP(PWM_LOW_MASK, channel->lo);
224 writel(val: value, addr: meson->base + channel_data->reg_offset);
225
226 value = readl(addr: meson->base + REG_MISC_AB);
227 value |= channel_data->pwm_en_mask;
228 writel(val: value, addr: meson->base + REG_MISC_AB);
229
230 spin_unlock_irqrestore(lock: &meson->lock, flags);
231}
232
233static void meson_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
234{
235 struct meson_pwm *meson = to_meson_pwm(chip);
236 unsigned long flags;
237 u32 value;
238
239 spin_lock_irqsave(&meson->lock, flags);
240
241 value = readl(addr: meson->base + REG_MISC_AB);
242 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
243 writel(val: value, addr: meson->base + REG_MISC_AB);
244
245 spin_unlock_irqrestore(lock: &meson->lock, flags);
246}
247
248static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
249 const struct pwm_state *state)
250{
251 struct meson_pwm *meson = to_meson_pwm(chip);
252 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
253 int err = 0;
254
255 if (!state->enabled) {
256 if (state->polarity == PWM_POLARITY_INVERSED) {
257 /*
258 * This IP block revision doesn't have an "always high"
259 * setting which we can use for "inverted disabled".
260 * Instead we achieve this by setting mux parent with
261 * highest rate and minimum divider value, resulting
262 * in the shortest possible duration for one "count"
263 * and "period == duty_cycle". This results in a signal
264 * which is LOW for one "count", while being HIGH for
265 * the rest of the (so the signal is HIGH for slightly
266 * less than 100% of the period, but this is the best
267 * we can achieve).
268 */
269 channel->rate = ULONG_MAX;
270 channel->hi = ~0;
271 channel->lo = 0;
272
273 meson_pwm_enable(chip, pwm);
274 } else {
275 meson_pwm_disable(chip, pwm);
276 }
277 } else {
278 err = meson_pwm_calc(chip, pwm, state);
279 if (err < 0)
280 return err;
281
282 meson_pwm_enable(chip, pwm);
283 }
284
285 return 0;
286}
287
288static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm,
289 u32 cnt)
290{
291 struct meson_pwm *meson = to_meson_pwm(chip);
292 struct meson_pwm_channel *channel;
293 unsigned long fin_freq;
294
295 /* to_meson_pwm() can only be used after .get_state() is called */
296 channel = &meson->channels[pwm->hwpwm];
297
298 fin_freq = clk_get_rate(clk: channel->clk);
299 if (fin_freq == 0)
300 return 0;
301
302 return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq);
303}
304
305static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
306 struct pwm_state *state)
307{
308 struct meson_pwm *meson = to_meson_pwm(chip);
309 struct meson_pwm_channel_data *channel_data;
310 struct meson_pwm_channel *channel;
311 u32 value;
312
313 if (!state)
314 return 0;
315
316 channel = &meson->channels[pwm->hwpwm];
317 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
318
319 value = readl(addr: meson->base + REG_MISC_AB);
320 state->enabled = value & channel_data->pwm_en_mask;
321
322 value = readl(addr: meson->base + channel_data->reg_offset);
323 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
324 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
325
326 state->period = meson_pwm_cnt_to_ns(chip, pwm, cnt: channel->lo + channel->hi);
327 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, cnt: channel->hi);
328
329 state->polarity = PWM_POLARITY_NORMAL;
330
331 return 0;
332}
333
334static const struct pwm_ops meson_pwm_ops = {
335 .request = meson_pwm_request,
336 .free = meson_pwm_free,
337 .apply = meson_pwm_apply,
338 .get_state = meson_pwm_get_state,
339};
340
341static const struct meson_pwm_data pwm_meson8b_data = {
342 .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" },
343};
344
345/*
346 * Only the 2 first inputs of the GXBB AO PWMs are valid
347 * The last 2 are grounded
348 */
349static const struct meson_pwm_data pwm_gxbb_ao_data = {
350 .parent_names = { "xtal", "clk81", NULL, NULL },
351};
352
353static const struct meson_pwm_data pwm_axg_ee_data = {
354 .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" },
355};
356
357static const struct meson_pwm_data pwm_axg_ao_data = {
358 .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" },
359};
360
361static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
362 .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" },
363};
364
365static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
366 .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL },
367};
368
369static const struct of_device_id meson_pwm_matches[] = {
370 {
371 .compatible = "amlogic,meson8b-pwm",
372 .data = &pwm_meson8b_data
373 },
374 {
375 .compatible = "amlogic,meson-gxbb-pwm",
376 .data = &pwm_meson8b_data
377 },
378 {
379 .compatible = "amlogic,meson-gxbb-ao-pwm",
380 .data = &pwm_gxbb_ao_data
381 },
382 {
383 .compatible = "amlogic,meson-axg-ee-pwm",
384 .data = &pwm_axg_ee_data
385 },
386 {
387 .compatible = "amlogic,meson-axg-ao-pwm",
388 .data = &pwm_axg_ao_data
389 },
390 {
391 .compatible = "amlogic,meson-g12a-ee-pwm",
392 .data = &pwm_meson8b_data
393 },
394 {
395 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
396 .data = &pwm_g12a_ao_ab_data
397 },
398 {
399 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
400 .data = &pwm_g12a_ao_cd_data
401 },
402 {},
403};
404MODULE_DEVICE_TABLE(of, meson_pwm_matches);
405
406static int meson_pwm_init_channels(struct pwm_chip *chip)
407{
408 struct meson_pwm *meson = to_meson_pwm(chip);
409 struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {};
410 struct device *dev = pwmchip_parent(chip);
411 unsigned int i;
412 char name[255];
413 int err;
414
415 for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) {
416 mux_parent_data[i].index = -1;
417 mux_parent_data[i].name = meson->data->parent_names[i];
418 }
419
420 for (i = 0; i < chip->npwm; i++) {
421 struct meson_pwm_channel *channel = &meson->channels[i];
422 struct clk_parent_data div_parent = {}, gate_parent = {};
423 struct clk_init_data init = {};
424
425 snprintf(buf: name, size: sizeof(name), fmt: "%s#mux%u", dev_name(dev), i);
426
427 init.name = name;
428 init.ops = &clk_mux_ops;
429 init.flags = 0;
430 init.parent_data = mux_parent_data;
431 init.num_parents = MESON_NUM_MUX_PARENTS;
432
433 channel->mux.reg = meson->base + REG_MISC_AB;
434 channel->mux.shift =
435 meson_pwm_per_channel_data[i].clk_sel_shift;
436 channel->mux.mask = MISC_CLK_SEL_MASK;
437 channel->mux.flags = 0;
438 channel->mux.lock = &meson->lock;
439 channel->mux.table = NULL;
440 channel->mux.hw.init = &init;
441
442 err = devm_clk_hw_register(dev, hw: &channel->mux.hw);
443 if (err)
444 return dev_err_probe(dev, err,
445 fmt: "failed to register %s\n", name);
446
447 snprintf(buf: name, size: sizeof(name), fmt: "%s#div%u", dev_name(dev), i);
448
449 init.name = name;
450 init.ops = &clk_divider_ops;
451 init.flags = CLK_SET_RATE_PARENT;
452 div_parent.index = -1;
453 div_parent.hw = &channel->mux.hw;
454 init.parent_data = &div_parent;
455 init.num_parents = 1;
456
457 channel->div.reg = meson->base + REG_MISC_AB;
458 channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift;
459 channel->div.width = MISC_CLK_DIV_WIDTH;
460 channel->div.hw.init = &init;
461 channel->div.flags = 0;
462 channel->div.lock = &meson->lock;
463
464 err = devm_clk_hw_register(dev, hw: &channel->div.hw);
465 if (err)
466 return dev_err_probe(dev, err,
467 fmt: "failed to register %s\n", name);
468
469 snprintf(buf: name, size: sizeof(name), fmt: "%s#gate%u", dev_name(dev), i);
470
471 init.name = name;
472 init.ops = &clk_gate_ops;
473 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
474 gate_parent.index = -1;
475 gate_parent.hw = &channel->div.hw;
476 init.parent_data = &gate_parent;
477 init.num_parents = 1;
478
479 channel->gate.reg = meson->base + REG_MISC_AB;
480 channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift;
481 channel->gate.hw.init = &init;
482 channel->gate.flags = 0;
483 channel->gate.lock = &meson->lock;
484
485 err = devm_clk_hw_register(dev, hw: &channel->gate.hw);
486 if (err)
487 return dev_err_probe(dev, err, fmt: "failed to register %s\n", name);
488
489 channel->clk = devm_clk_hw_get_clk(dev, hw: &channel->gate.hw, NULL);
490 if (IS_ERR(ptr: channel->clk))
491 return dev_err_probe(dev, err: PTR_ERR(ptr: channel->clk),
492 fmt: "failed to register %s\n", name);
493 }
494
495 return 0;
496}
497
498static int meson_pwm_probe(struct platform_device *pdev)
499{
500 struct pwm_chip *chip;
501 struct meson_pwm *meson;
502 int err;
503
504 chip = devm_pwmchip_alloc(parent: &pdev->dev, MESON_NUM_PWMS, sizeof_priv: sizeof(*meson));
505 if (IS_ERR(ptr: chip))
506 return PTR_ERR(ptr: chip);
507 meson = to_meson_pwm(chip);
508
509 meson->base = devm_platform_ioremap_resource(pdev, index: 0);
510 if (IS_ERR(ptr: meson->base))
511 return PTR_ERR(ptr: meson->base);
512
513 spin_lock_init(&meson->lock);
514 chip->ops = &meson_pwm_ops;
515
516 meson->data = of_device_get_match_data(dev: &pdev->dev);
517
518 err = meson_pwm_init_channels(chip);
519 if (err < 0)
520 return err;
521
522 err = devm_pwmchip_add(&pdev->dev, chip);
523 if (err < 0)
524 return dev_err_probe(dev: &pdev->dev, err,
525 fmt: "failed to register PWM chip\n");
526
527 return 0;
528}
529
530static struct platform_driver meson_pwm_driver = {
531 .driver = {
532 .name = "meson-pwm",
533 .of_match_table = meson_pwm_matches,
534 },
535 .probe = meson_pwm_probe,
536};
537module_platform_driver(meson_pwm_driver);
538
539MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
540MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
541MODULE_LICENSE("Dual BSD/GPL");
542

source code of linux/drivers/pwm/pwm-meson.c