1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Toshiba Visconti pulse-width-modulation controller driver |
4 | * |
5 | * Copyright (c) 2020 - 2021 TOSHIBA CORPORATION |
6 | * Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation |
7 | * |
8 | * Authors: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> |
9 | * |
10 | * Limitations: |
11 | * - The fixed input clock is running at 1 MHz and is divided by either 1, |
12 | * 2, 4 or 8. |
13 | * - When the settings of the PWM are modified, the new values are shadowed |
14 | * in hardware until the PIPGM_PCSR register is written and the currently |
15 | * running period is completed. This way the hardware switches atomically |
16 | * from the old setting to the new. |
17 | * - Disabling the hardware completes the currently running period and keeps |
18 | * the output at low level at all times. |
19 | */ |
20 | |
21 | #include <linux/err.h> |
22 | #include <linux/io.h> |
23 | #include <linux/module.h> |
24 | #include <linux/of.h> |
25 | #include <linux/platform_device.h> |
26 | #include <linux/pwm.h> |
27 | |
28 | #define PIPGM_PCSR(ch) (0x400 + 4 * (ch)) |
29 | #define PIPGM_PDUT(ch) (0x420 + 4 * (ch)) |
30 | #define PIPGM_PWMC(ch) (0x440 + 4 * (ch)) |
31 | |
32 | #define PIPGM_PWMC_PWMACT BIT(5) |
33 | #define PIPGM_PWMC_CLK_MASK GENMASK(1, 0) |
34 | #define PIPGM_PWMC_POLARITY_MASK GENMASK(5, 5) |
35 | |
36 | struct visconti_pwm_chip { |
37 | void __iomem *base; |
38 | }; |
39 | |
40 | static inline struct visconti_pwm_chip *visconti_pwm_from_chip(struct pwm_chip *chip) |
41 | { |
42 | return pwmchip_get_drvdata(chip); |
43 | } |
44 | |
45 | static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
46 | const struct pwm_state *state) |
47 | { |
48 | struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip); |
49 | u32 period, duty_cycle, pwmc0; |
50 | |
51 | if (!state->enabled) { |
52 | writel(val: 0, addr: priv->base + PIPGM_PCSR(pwm->hwpwm)); |
53 | return 0; |
54 | } |
55 | |
56 | /* |
57 | * The biggest period the hardware can provide is |
58 | * (0xffff << 3) * 1000 ns |
59 | * This value fits easily in an u32, so simplify the maths by |
60 | * capping the values to 32 bit integers. |
61 | */ |
62 | if (state->period > (0xffff << 3) * 1000) |
63 | period = (0xffff << 3) * 1000; |
64 | else |
65 | period = state->period; |
66 | |
67 | if (state->duty_cycle > period) |
68 | duty_cycle = period; |
69 | else |
70 | duty_cycle = state->duty_cycle; |
71 | |
72 | /* |
73 | * The input clock runs fixed at 1 MHz, so we have only |
74 | * microsecond resolution and so can divide by |
75 | * NSEC_PER_SEC / CLKFREQ = 1000 without losing precision. |
76 | */ |
77 | period /= 1000; |
78 | duty_cycle /= 1000; |
79 | |
80 | if (!period) |
81 | return -ERANGE; |
82 | |
83 | /* |
84 | * PWMC controls a divider that divides the input clk by a power of two |
85 | * between 1 and 8. As a smaller divider yields higher precision, pick |
86 | * the smallest possible one. As period is at most 0xffff << 3, pwmc0 is |
87 | * in the intended range [0..3]. |
88 | */ |
89 | pwmc0 = fls(x: period >> 16); |
90 | if (WARN_ON(pwmc0 > 3)) |
91 | return -EINVAL; |
92 | |
93 | period >>= pwmc0; |
94 | duty_cycle >>= pwmc0; |
95 | |
96 | if (state->polarity == PWM_POLARITY_INVERSED) |
97 | pwmc0 |= PIPGM_PWMC_PWMACT; |
98 | writel(val: pwmc0, addr: priv->base + PIPGM_PWMC(pwm->hwpwm)); |
99 | writel(val: duty_cycle, addr: priv->base + PIPGM_PDUT(pwm->hwpwm)); |
100 | writel(val: period, addr: priv->base + PIPGM_PCSR(pwm->hwpwm)); |
101 | |
102 | return 0; |
103 | } |
104 | |
105 | static int visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
106 | struct pwm_state *state) |
107 | { |
108 | struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip); |
109 | u32 period, duty, pwmc0, pwmc0_clk; |
110 | |
111 | period = readl(addr: priv->base + PIPGM_PCSR(pwm->hwpwm)); |
112 | duty = readl(addr: priv->base + PIPGM_PDUT(pwm->hwpwm)); |
113 | pwmc0 = readl(addr: priv->base + PIPGM_PWMC(pwm->hwpwm)); |
114 | pwmc0_clk = pwmc0 & PIPGM_PWMC_CLK_MASK; |
115 | |
116 | state->period = (period << pwmc0_clk) * NSEC_PER_USEC; |
117 | state->duty_cycle = (duty << pwmc0_clk) * NSEC_PER_USEC; |
118 | if (pwmc0 & PIPGM_PWMC_POLARITY_MASK) |
119 | state->polarity = PWM_POLARITY_INVERSED; |
120 | else |
121 | state->polarity = PWM_POLARITY_NORMAL; |
122 | |
123 | state->enabled = true; |
124 | |
125 | return 0; |
126 | } |
127 | |
128 | static const struct pwm_ops visconti_pwm_ops = { |
129 | .apply = visconti_pwm_apply, |
130 | .get_state = visconti_pwm_get_state, |
131 | }; |
132 | |
133 | static int visconti_pwm_probe(struct platform_device *pdev) |
134 | { |
135 | struct device *dev = &pdev->dev; |
136 | struct pwm_chip *chip; |
137 | struct visconti_pwm_chip *priv; |
138 | int ret; |
139 | |
140 | chip = devm_pwmchip_alloc(parent: dev, npwm: 4, sizeof_priv: sizeof(*priv)); |
141 | if (IS_ERR(ptr: chip)) |
142 | return PTR_ERR(ptr: chip); |
143 | priv = visconti_pwm_from_chip(chip); |
144 | |
145 | priv->base = devm_platform_ioremap_resource(pdev, index: 0); |
146 | if (IS_ERR(ptr: priv->base)) |
147 | return PTR_ERR(ptr: priv->base); |
148 | |
149 | chip->ops = &visconti_pwm_ops; |
150 | |
151 | ret = devm_pwmchip_add(&pdev->dev, chip); |
152 | if (ret < 0) |
153 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Cannot register visconti PWM\n" ); |
154 | |
155 | return 0; |
156 | } |
157 | |
158 | static const struct of_device_id visconti_pwm_of_match[] = { |
159 | { .compatible = "toshiba,visconti-pwm" , }, |
160 | { } |
161 | }; |
162 | MODULE_DEVICE_TABLE(of, visconti_pwm_of_match); |
163 | |
164 | static struct platform_driver visconti_pwm_driver = { |
165 | .driver = { |
166 | .name = "pwm-visconti" , |
167 | .of_match_table = visconti_pwm_of_match, |
168 | }, |
169 | .probe = visconti_pwm_probe, |
170 | }; |
171 | module_platform_driver(visconti_pwm_driver); |
172 | |
173 | MODULE_LICENSE("GPL v2" ); |
174 | MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>" ); |
175 | MODULE_ALIAS("platform:pwm-visconti" ); |
176 | |