1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. |
4 | */ |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/iopoll.h> |
8 | #include <linux/module.h> |
9 | #include <linux/of.h> |
10 | #include <linux/platform_device.h> |
11 | #include <linux/regmap.h> |
12 | #include <linux/soc/mediatek/mtk-mmsys.h> |
13 | #include <linux/soc/mediatek/mtk-mutex.h> |
14 | #include <linux/soc/mediatek/mtk-cmdq.h> |
15 | |
16 | #define MTK_MUTEX_MAX_HANDLES 10 |
17 | |
18 | #define MT2701_MUTEX0_MOD0 0x2c |
19 | #define MT2701_MUTEX0_SOF0 0x30 |
20 | #define MT8183_MUTEX0_MOD0 0x30 |
21 | #define MT8183_MUTEX0_SOF0 0x2c |
22 | |
23 | #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) |
24 | #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) |
25 | #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) |
26 | #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) |
27 | #define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4) |
28 | #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) |
29 | #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) |
30 | |
31 | #define INT_MUTEX BIT(1) |
32 | |
33 | #define MT8186_MUTEX_MOD_DISP_OVL0 0 |
34 | #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 |
35 | #define MT8186_MUTEX_MOD_DISP_RDMA0 2 |
36 | #define MT8186_MUTEX_MOD_DISP_COLOR0 4 |
37 | #define MT8186_MUTEX_MOD_DISP_CCORR0 5 |
38 | #define MT8186_MUTEX_MOD_DISP_AAL0 7 |
39 | #define MT8186_MUTEX_MOD_DISP_GAMMA0 8 |
40 | #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 |
41 | #define MT8186_MUTEX_MOD_DISP_DITHER0 10 |
42 | #define MT8186_MUTEX_MOD_DISP_RDMA1 17 |
43 | |
44 | #define MT8186_MUTEX_SOF_SINGLE_MODE 0 |
45 | #define MT8186_MUTEX_SOF_DSI0 1 |
46 | #define MT8186_MUTEX_SOF_DPI0 2 |
47 | #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) |
48 | #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) |
49 | |
50 | #define MT8167_MUTEX_MOD_DISP_PWM 1 |
51 | #define MT8167_MUTEX_MOD_DISP_OVL0 6 |
52 | #define MT8167_MUTEX_MOD_DISP_OVL1 7 |
53 | #define MT8167_MUTEX_MOD_DISP_RDMA0 8 |
54 | #define MT8167_MUTEX_MOD_DISP_RDMA1 9 |
55 | #define MT8167_MUTEX_MOD_DISP_WDMA0 10 |
56 | #define MT8167_MUTEX_MOD_DISP_CCORR 11 |
57 | #define MT8167_MUTEX_MOD_DISP_COLOR 12 |
58 | #define MT8167_MUTEX_MOD_DISP_AAL 13 |
59 | #define MT8167_MUTEX_MOD_DISP_GAMMA 14 |
60 | #define MT8167_MUTEX_MOD_DISP_DITHER 15 |
61 | #define MT8167_MUTEX_MOD_DISP_UFOE 16 |
62 | |
63 | #define MT8192_MUTEX_MOD_DISP_OVL0 0 |
64 | #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 |
65 | #define MT8192_MUTEX_MOD_DISP_RDMA0 2 |
66 | #define MT8192_MUTEX_MOD_DISP_COLOR0 4 |
67 | #define MT8192_MUTEX_MOD_DISP_CCORR0 5 |
68 | #define MT8192_MUTEX_MOD_DISP_AAL0 6 |
69 | #define MT8192_MUTEX_MOD_DISP_GAMMA0 7 |
70 | #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 |
71 | #define MT8192_MUTEX_MOD_DISP_DITHER0 9 |
72 | #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 |
73 | #define MT8192_MUTEX_MOD_DISP_RDMA4 17 |
74 | |
75 | #define MT8183_MUTEX_MOD_DISP_RDMA0 0 |
76 | #define MT8183_MUTEX_MOD_DISP_RDMA1 1 |
77 | #define MT8183_MUTEX_MOD_DISP_OVL0 9 |
78 | #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 |
79 | #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 |
80 | #define MT8183_MUTEX_MOD_DISP_WDMA0 12 |
81 | #define MT8183_MUTEX_MOD_DISP_COLOR0 13 |
82 | #define MT8183_MUTEX_MOD_DISP_CCORR0 14 |
83 | #define MT8183_MUTEX_MOD_DISP_AAL0 15 |
84 | #define MT8183_MUTEX_MOD_DISP_GAMMA0 16 |
85 | #define MT8183_MUTEX_MOD_DISP_DITHER0 17 |
86 | |
87 | #define MT8183_MUTEX_MOD_MDP_RDMA0 2 |
88 | #define MT8183_MUTEX_MOD_MDP_RSZ0 4 |
89 | #define MT8183_MUTEX_MOD_MDP_RSZ1 5 |
90 | #define MT8183_MUTEX_MOD_MDP_TDSHP0 6 |
91 | #define MT8183_MUTEX_MOD_MDP_WROT0 7 |
92 | #define MT8183_MUTEX_MOD_MDP_WDMA 8 |
93 | #define MT8183_MUTEX_MOD_MDP_AAL0 23 |
94 | #define MT8183_MUTEX_MOD_MDP_CCORR0 24 |
95 | |
96 | #define MT8186_MUTEX_MOD_MDP_RDMA0 0 |
97 | #define MT8186_MUTEX_MOD_MDP_AAL0 2 |
98 | #define MT8186_MUTEX_MOD_MDP_HDR0 4 |
99 | #define MT8186_MUTEX_MOD_MDP_RSZ0 5 |
100 | #define MT8186_MUTEX_MOD_MDP_RSZ1 6 |
101 | #define MT8186_MUTEX_MOD_MDP_WROT0 7 |
102 | #define MT8186_MUTEX_MOD_MDP_TDSHP0 9 |
103 | #define MT8186_MUTEX_MOD_MDP_COLOR0 14 |
104 | |
105 | #define MT8173_MUTEX_MOD_DISP_OVL0 11 |
106 | #define MT8173_MUTEX_MOD_DISP_OVL1 12 |
107 | #define MT8173_MUTEX_MOD_DISP_RDMA0 13 |
108 | #define MT8173_MUTEX_MOD_DISP_RDMA1 14 |
109 | #define MT8173_MUTEX_MOD_DISP_RDMA2 15 |
110 | #define MT8173_MUTEX_MOD_DISP_WDMA0 16 |
111 | #define MT8173_MUTEX_MOD_DISP_WDMA1 17 |
112 | #define MT8173_MUTEX_MOD_DISP_COLOR0 18 |
113 | #define MT8173_MUTEX_MOD_DISP_COLOR1 19 |
114 | #define MT8173_MUTEX_MOD_DISP_AAL 20 |
115 | #define MT8173_MUTEX_MOD_DISP_GAMMA 21 |
116 | #define MT8173_MUTEX_MOD_DISP_UFOE 22 |
117 | #define MT8173_MUTEX_MOD_DISP_PWM0 23 |
118 | #define MT8173_MUTEX_MOD_DISP_PWM1 24 |
119 | #define MT8173_MUTEX_MOD_DISP_OD 25 |
120 | |
121 | #define MT8188_MUTEX_MOD_DISP_OVL0 0 |
122 | #define MT8188_MUTEX_MOD_DISP_WDMA0 1 |
123 | #define MT8188_MUTEX_MOD_DISP_RDMA0 2 |
124 | #define MT8188_MUTEX_MOD_DISP_COLOR0 3 |
125 | #define MT8188_MUTEX_MOD_DISP_CCORR0 4 |
126 | #define MT8188_MUTEX_MOD_DISP_AAL0 5 |
127 | #define MT8188_MUTEX_MOD_DISP_GAMMA0 6 |
128 | #define MT8188_MUTEX_MOD_DISP_DITHER0 7 |
129 | #define MT8188_MUTEX_MOD_DISP_DSI0 8 |
130 | #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 |
131 | #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20 |
132 | #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21 |
133 | #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 |
134 | #define MT8188_MUTEX_MOD2_DISP_PWM0 33 |
135 | |
136 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 |
137 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 |
138 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 |
139 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 |
140 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 |
141 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 |
142 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 |
143 | #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 |
144 | #define MT8188_MUTEX_MOD_DISP1_PADDING0 8 |
145 | #define MT8188_MUTEX_MOD_DISP1_PADDING1 9 |
146 | #define MT8188_MUTEX_MOD_DISP1_PADDING2 10 |
147 | #define MT8188_MUTEX_MOD_DISP1_PADDING3 11 |
148 | #define MT8188_MUTEX_MOD_DISP1_PADDING4 12 |
149 | #define MT8188_MUTEX_MOD_DISP1_PADDING5 13 |
150 | #define MT8188_MUTEX_MOD_DISP1_PADDING6 14 |
151 | #define MT8188_MUTEX_MOD_DISP1_PADDING7 15 |
152 | #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 |
153 | #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 |
154 | #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 |
155 | #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 |
156 | #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 |
157 | #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 |
158 | #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 |
159 | |
160 | #define MT8195_MUTEX_MOD_DISP_OVL0 0 |
161 | #define MT8195_MUTEX_MOD_DISP_WDMA0 1 |
162 | #define MT8195_MUTEX_MOD_DISP_RDMA0 2 |
163 | #define MT8195_MUTEX_MOD_DISP_COLOR0 3 |
164 | #define MT8195_MUTEX_MOD_DISP_CCORR0 4 |
165 | #define MT8195_MUTEX_MOD_DISP_AAL0 5 |
166 | #define MT8195_MUTEX_MOD_DISP_GAMMA0 6 |
167 | #define MT8195_MUTEX_MOD_DISP_DITHER0 7 |
168 | #define MT8195_MUTEX_MOD_DISP_DSI0 8 |
169 | #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 |
170 | #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 |
171 | #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 |
172 | #define MT8195_MUTEX_MOD_DISP_PWM0 27 |
173 | |
174 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 |
175 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 |
176 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 |
177 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 |
178 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 |
179 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 |
180 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 |
181 | #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 |
182 | #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 |
183 | #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 |
184 | #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 |
185 | #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 |
186 | #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 |
187 | #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 |
188 | #define MT8195_MUTEX_MOD_DISP1_DPI0 25 |
189 | #define MT8195_MUTEX_MOD_DISP1_DPI1 26 |
190 | #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 |
191 | |
192 | /* VPPSYS0 */ |
193 | #define MT8195_MUTEX_MOD_MDP_RDMA0 0 |
194 | #define MT8195_MUTEX_MOD_MDP_FG0 1 |
195 | #define MT8195_MUTEX_MOD_MDP_STITCH0 2 |
196 | #define MT8195_MUTEX_MOD_MDP_HDR0 3 |
197 | #define MT8195_MUTEX_MOD_MDP_AAL0 4 |
198 | #define MT8195_MUTEX_MOD_MDP_RSZ0 5 |
199 | #define MT8195_MUTEX_MOD_MDP_TDSHP0 6 |
200 | #define MT8195_MUTEX_MOD_MDP_COLOR0 7 |
201 | #define MT8195_MUTEX_MOD_MDP_OVL0 8 |
202 | #define MT8195_MUTEX_MOD_MDP_PAD0 9 |
203 | #define MT8195_MUTEX_MOD_MDP_TCC0 10 |
204 | #define MT8195_MUTEX_MOD_MDP_WROT0 11 |
205 | |
206 | /* VPPSYS1 */ |
207 | #define MT8195_MUTEX_MOD_MDP_TCC1 3 |
208 | #define MT8195_MUTEX_MOD_MDP_RDMA1 4 |
209 | #define MT8195_MUTEX_MOD_MDP_RDMA2 5 |
210 | #define MT8195_MUTEX_MOD_MDP_RDMA3 6 |
211 | #define MT8195_MUTEX_MOD_MDP_FG1 7 |
212 | #define MT8195_MUTEX_MOD_MDP_FG2 8 |
213 | #define MT8195_MUTEX_MOD_MDP_FG3 9 |
214 | #define MT8195_MUTEX_MOD_MDP_HDR1 10 |
215 | #define MT8195_MUTEX_MOD_MDP_HDR2 11 |
216 | #define MT8195_MUTEX_MOD_MDP_HDR3 12 |
217 | #define MT8195_MUTEX_MOD_MDP_AAL1 13 |
218 | #define MT8195_MUTEX_MOD_MDP_AAL2 14 |
219 | #define MT8195_MUTEX_MOD_MDP_AAL3 15 |
220 | #define MT8195_MUTEX_MOD_MDP_RSZ1 16 |
221 | #define MT8195_MUTEX_MOD_MDP_RSZ2 17 |
222 | #define MT8195_MUTEX_MOD_MDP_RSZ3 18 |
223 | #define MT8195_MUTEX_MOD_MDP_TDSHP1 19 |
224 | #define MT8195_MUTEX_MOD_MDP_TDSHP2 20 |
225 | #define MT8195_MUTEX_MOD_MDP_TDSHP3 21 |
226 | #define MT8195_MUTEX_MOD_MDP_MERGE2 22 |
227 | #define MT8195_MUTEX_MOD_MDP_MERGE3 23 |
228 | #define MT8195_MUTEX_MOD_MDP_COLOR1 24 |
229 | #define MT8195_MUTEX_MOD_MDP_COLOR2 25 |
230 | #define MT8195_MUTEX_MOD_MDP_COLOR3 26 |
231 | #define MT8195_MUTEX_MOD_MDP_OVL1 27 |
232 | #define MT8195_MUTEX_MOD_MDP_PAD1 28 |
233 | #define MT8195_MUTEX_MOD_MDP_PAD2 29 |
234 | #define MT8195_MUTEX_MOD_MDP_PAD3 30 |
235 | #define MT8195_MUTEX_MOD_MDP_WROT1 31 |
236 | #define MT8195_MUTEX_MOD_MDP_WROT2 32 |
237 | #define MT8195_MUTEX_MOD_MDP_WROT3 33 |
238 | |
239 | #define MT8365_MUTEX_MOD_DISP_OVL0 7 |
240 | #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 |
241 | #define MT8365_MUTEX_MOD_DISP_RDMA0 9 |
242 | #define MT8365_MUTEX_MOD_DISP_RDMA1 10 |
243 | #define MT8365_MUTEX_MOD_DISP_WDMA0 11 |
244 | #define MT8365_MUTEX_MOD_DISP_COLOR0 12 |
245 | #define MT8365_MUTEX_MOD_DISP_CCORR 13 |
246 | #define MT8365_MUTEX_MOD_DISP_AAL 14 |
247 | #define MT8365_MUTEX_MOD_DISP_GAMMA 15 |
248 | #define MT8365_MUTEX_MOD_DISP_DITHER 16 |
249 | #define MT8365_MUTEX_MOD_DISP_DSI0 17 |
250 | #define MT8365_MUTEX_MOD_DISP_PWM0 20 |
251 | #define MT8365_MUTEX_MOD_DISP_DPI0 22 |
252 | |
253 | #define MT2712_MUTEX_MOD_DISP_PWM2 10 |
254 | #define MT2712_MUTEX_MOD_DISP_OVL0 11 |
255 | #define MT2712_MUTEX_MOD_DISP_OVL1 12 |
256 | #define MT2712_MUTEX_MOD_DISP_RDMA0 13 |
257 | #define MT2712_MUTEX_MOD_DISP_RDMA1 14 |
258 | #define MT2712_MUTEX_MOD_DISP_RDMA2 15 |
259 | #define MT2712_MUTEX_MOD_DISP_WDMA0 16 |
260 | #define MT2712_MUTEX_MOD_DISP_WDMA1 17 |
261 | #define MT2712_MUTEX_MOD_DISP_COLOR0 18 |
262 | #define MT2712_MUTEX_MOD_DISP_COLOR1 19 |
263 | #define MT2712_MUTEX_MOD_DISP_AAL0 20 |
264 | #define MT2712_MUTEX_MOD_DISP_UFOE 22 |
265 | #define MT2712_MUTEX_MOD_DISP_PWM0 23 |
266 | #define MT2712_MUTEX_MOD_DISP_PWM1 24 |
267 | #define MT2712_MUTEX_MOD_DISP_OD0 25 |
268 | #define MT2712_MUTEX_MOD2_DISP_AAL1 33 |
269 | #define MT2712_MUTEX_MOD2_DISP_OD1 34 |
270 | |
271 | #define MT2701_MUTEX_MOD_DISP_OVL 3 |
272 | #define MT2701_MUTEX_MOD_DISP_WDMA 6 |
273 | #define MT2701_MUTEX_MOD_DISP_COLOR 7 |
274 | #define MT2701_MUTEX_MOD_DISP_BLS 9 |
275 | #define MT2701_MUTEX_MOD_DISP_RDMA0 10 |
276 | #define MT2701_MUTEX_MOD_DISP_RDMA1 12 |
277 | |
278 | #define MT2712_MUTEX_SOF_SINGLE_MODE 0 |
279 | #define MT2712_MUTEX_SOF_DSI0 1 |
280 | #define MT2712_MUTEX_SOF_DSI1 2 |
281 | #define MT2712_MUTEX_SOF_DPI0 3 |
282 | #define MT2712_MUTEX_SOF_DPI1 4 |
283 | #define MT2712_MUTEX_SOF_DSI2 5 |
284 | #define MT2712_MUTEX_SOF_DSI3 6 |
285 | #define MT8167_MUTEX_SOF_DPI0 2 |
286 | #define MT8167_MUTEX_SOF_DPI1 3 |
287 | #define MT8183_MUTEX_SOF_DSI0 1 |
288 | #define MT8183_MUTEX_SOF_DPI0 2 |
289 | #define MT8188_MUTEX_SOF_DSI0 1 |
290 | #define MT8188_MUTEX_SOF_DP_INTF0 3 |
291 | #define MT8188_MUTEX_SOF_DP_INTF1 4 |
292 | #define MT8195_MUTEX_SOF_DSI0 1 |
293 | #define MT8195_MUTEX_SOF_DSI1 2 |
294 | #define MT8195_MUTEX_SOF_DP_INTF0 3 |
295 | #define MT8195_MUTEX_SOF_DP_INTF1 4 |
296 | #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ |
297 | #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ |
298 | |
299 | #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) |
300 | #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) |
301 | #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) |
302 | #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) |
303 | #define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) |
304 | #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) |
305 | #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) |
306 | #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) |
307 | #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) |
308 | #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) |
309 | #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) |
310 | |
311 | struct mtk_mutex { |
312 | u8 id; |
313 | bool claimed; |
314 | }; |
315 | |
316 | enum mtk_mutex_sof_id { |
317 | MUTEX_SOF_SINGLE_MODE, |
318 | MUTEX_SOF_DSI0, |
319 | MUTEX_SOF_DSI1, |
320 | MUTEX_SOF_DPI0, |
321 | MUTEX_SOF_DPI1, |
322 | MUTEX_SOF_DSI2, |
323 | MUTEX_SOF_DSI3, |
324 | MUTEX_SOF_DP_INTF0, |
325 | MUTEX_SOF_DP_INTF1, |
326 | DDP_MUTEX_SOF_MAX, |
327 | }; |
328 | |
329 | struct mtk_mutex_data { |
330 | const unsigned int *mutex_mod; |
331 | const unsigned int *mutex_sof; |
332 | const unsigned int mutex_mod_reg; |
333 | const unsigned int mutex_sof_reg; |
334 | const unsigned int *mutex_table_mod; |
335 | const bool no_clk; |
336 | }; |
337 | |
338 | struct mtk_mutex_ctx { |
339 | struct device *dev; |
340 | struct clk *clk; |
341 | void __iomem *regs; |
342 | struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES]; |
343 | const struct mtk_mutex_data *data; |
344 | phys_addr_t addr; |
345 | struct cmdq_client_reg cmdq_reg; |
346 | }; |
347 | |
348 | static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
349 | [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, |
350 | [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, |
351 | [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, |
352 | [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, |
353 | [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, |
354 | [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, |
355 | }; |
356 | |
357 | static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
358 | [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, |
359 | [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, |
360 | [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, |
361 | [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, |
362 | [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, |
363 | [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, |
364 | [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, |
365 | [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, |
366 | [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, |
367 | [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, |
368 | [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, |
369 | [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, |
370 | [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, |
371 | [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, |
372 | [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, |
373 | [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, |
374 | [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, |
375 | }; |
376 | |
377 | static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
378 | [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, |
379 | [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, |
380 | [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, |
381 | [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER, |
382 | [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, |
383 | [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, |
384 | [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, |
385 | [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, |
386 | [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, |
387 | [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, |
388 | [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, |
389 | [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, |
390 | }; |
391 | |
392 | static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
393 | [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, |
394 | [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, |
395 | [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, |
396 | [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, |
397 | [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, |
398 | [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, |
399 | [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, |
400 | [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, |
401 | [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, |
402 | [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, |
403 | [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, |
404 | [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, |
405 | [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, |
406 | [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, |
407 | [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, |
408 | }; |
409 | |
410 | static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
411 | [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, |
412 | [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, |
413 | [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, |
414 | [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0, |
415 | [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, |
416 | [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, |
417 | [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, |
418 | [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, |
419 | [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, |
420 | [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, |
421 | [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, |
422 | }; |
423 | |
424 | static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { |
425 | [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0, |
426 | [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0, |
427 | [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1, |
428 | [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0, |
429 | [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0, |
430 | [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA, |
431 | [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0, |
432 | [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0, |
433 | }; |
434 | |
435 | static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
436 | [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, |
437 | [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, |
438 | [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, |
439 | [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0, |
440 | [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, |
441 | [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, |
442 | [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, |
443 | [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0, |
444 | [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0, |
445 | [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1, |
446 | }; |
447 | |
448 | static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { |
449 | [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0, |
450 | [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0, |
451 | [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1, |
452 | [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0, |
453 | [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0, |
454 | [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0, |
455 | [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0, |
456 | [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0, |
457 | }; |
458 | |
459 | static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
460 | [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0, |
461 | [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0, |
462 | [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0, |
463 | [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0, |
464 | [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0, |
465 | [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0, |
466 | [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0, |
467 | [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0, |
468 | [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0, |
469 | [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE, |
470 | [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, |
471 | [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, |
472 | [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, |
473 | [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, |
474 | [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, |
475 | [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, |
476 | [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, |
477 | [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, |
478 | [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, |
479 | [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, |
480 | [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, |
481 | [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, |
482 | [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, |
483 | [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, |
484 | [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0, |
485 | [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1, |
486 | [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2, |
487 | [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3, |
488 | [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4, |
489 | [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5, |
490 | [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6, |
491 | [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7, |
492 | [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, |
493 | [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, |
494 | [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, |
495 | [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, |
496 | [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, |
497 | }; |
498 | |
499 | static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
500 | [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, |
501 | [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, |
502 | [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, |
503 | [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0, |
504 | [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, |
505 | [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, |
506 | [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, |
507 | [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, |
508 | [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, |
509 | [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, |
510 | [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, |
511 | }; |
512 | |
513 | static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
514 | [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, |
515 | [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, |
516 | [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, |
517 | [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, |
518 | [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, |
519 | [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, |
520 | [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, |
521 | [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0, |
522 | [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, |
523 | [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, |
524 | [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, |
525 | [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, |
526 | [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, |
527 | [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0, |
528 | [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1, |
529 | [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2, |
530 | [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3, |
531 | [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4, |
532 | [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5, |
533 | [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6, |
534 | [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7, |
535 | [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0, |
536 | [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1, |
537 | [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2, |
538 | [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3, |
539 | [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER, |
540 | [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, |
541 | [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, |
542 | }; |
543 | |
544 | static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { |
545 | [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, |
546 | [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1, |
547 | [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, |
548 | [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, |
549 | [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0, |
550 | [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, |
551 | [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1, |
552 | [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, |
553 | [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, |
554 | [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, |
555 | [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1, |
556 | [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, |
557 | [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, |
558 | [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, |
559 | [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1, |
560 | [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, |
561 | [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, |
562 | [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, |
563 | [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1, |
564 | [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, |
565 | [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, |
566 | [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, |
567 | [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, |
568 | [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, |
569 | [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1, |
570 | [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, |
571 | [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, |
572 | [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, |
573 | [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1, |
574 | [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, |
575 | [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, |
576 | [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, |
577 | [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1, |
578 | [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, |
579 | [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1, |
580 | [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, |
581 | [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, |
582 | [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0, |
583 | [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1, |
584 | [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, |
585 | [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1, |
586 | [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, |
587 | [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, |
588 | }; |
589 | |
590 | static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { |
591 | [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, |
592 | [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, |
593 | [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0, |
594 | [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER, |
595 | [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0, |
596 | [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0, |
597 | [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA, |
598 | [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0, |
599 | [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L, |
600 | [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0, |
601 | [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0, |
602 | [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1, |
603 | [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0, |
604 | }; |
605 | |
606 | static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { |
607 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
608 | [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, |
609 | [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, |
610 | [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, |
611 | [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, |
612 | [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, |
613 | [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, |
614 | }; |
615 | |
616 | static const unsigned int mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = { |
617 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
618 | [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, |
619 | [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, |
620 | [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, |
621 | }; |
622 | |
623 | static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { |
624 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
625 | [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, |
626 | [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, |
627 | [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, |
628 | }; |
629 | |
630 | /* Add EOF setting so overlay hardware can receive frame done irq */ |
631 | static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { |
632 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
633 | [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, |
634 | [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, |
635 | }; |
636 | |
637 | static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { |
638 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
639 | [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0, |
640 | [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, |
641 | }; |
642 | |
643 | /* |
644 | * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should |
645 | * select the EOF source and configure the EOF plus timing from the |
646 | * module that provides the timing signal. |
647 | * So that MUTEX can not only send a STREAM_DONE event to GCE |
648 | * but also detect the error at end of frame(EAEOF) when EOF signal |
649 | * arrives. |
650 | */ |
651 | static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { |
652 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
653 | [MUTEX_SOF_DSI0] = |
654 | MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, |
655 | [MUTEX_SOF_DP_INTF0] = |
656 | MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, |
657 | [MUTEX_SOF_DP_INTF1] = |
658 | MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, |
659 | }; |
660 | |
661 | static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { |
662 | [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, |
663 | [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, |
664 | [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, |
665 | [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, |
666 | [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, |
667 | [MUTEX_SOF_DP_INTF0] = |
668 | MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, |
669 | [MUTEX_SOF_DP_INTF1] = |
670 | MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, |
671 | }; |
672 | |
673 | static const struct mtk_mutex_data mt2701_mutex_driver_data = { |
674 | .mutex_mod = mt2701_mutex_mod, |
675 | .mutex_sof = mt2712_mutex_sof, |
676 | .mutex_mod_reg = MT2701_MUTEX0_MOD0, |
677 | .mutex_sof_reg = MT2701_MUTEX0_SOF0, |
678 | }; |
679 | |
680 | static const struct mtk_mutex_data mt2712_mutex_driver_data = { |
681 | .mutex_mod = mt2712_mutex_mod, |
682 | .mutex_sof = mt2712_mutex_sof, |
683 | .mutex_mod_reg = MT2701_MUTEX0_MOD0, |
684 | .mutex_sof_reg = MT2701_MUTEX0_SOF0, |
685 | }; |
686 | |
687 | static const struct mtk_mutex_data mt6795_mutex_driver_data = { |
688 | .mutex_mod = mt8173_mutex_mod, |
689 | .mutex_sof = mt6795_mutex_sof, |
690 | .mutex_mod_reg = MT2701_MUTEX0_MOD0, |
691 | .mutex_sof_reg = MT2701_MUTEX0_SOF0, |
692 | }; |
693 | |
694 | static const struct mtk_mutex_data mt8167_mutex_driver_data = { |
695 | .mutex_mod = mt8167_mutex_mod, |
696 | .mutex_sof = mt8167_mutex_sof, |
697 | .mutex_mod_reg = MT2701_MUTEX0_MOD0, |
698 | .mutex_sof_reg = MT2701_MUTEX0_SOF0, |
699 | .no_clk = true, |
700 | }; |
701 | |
702 | static const struct mtk_mutex_data mt8173_mutex_driver_data = { |
703 | .mutex_mod = mt8173_mutex_mod, |
704 | .mutex_sof = mt2712_mutex_sof, |
705 | .mutex_mod_reg = MT2701_MUTEX0_MOD0, |
706 | .mutex_sof_reg = MT2701_MUTEX0_SOF0, |
707 | }; |
708 | |
709 | static const struct mtk_mutex_data mt8183_mutex_driver_data = { |
710 | .mutex_mod = mt8183_mutex_mod, |
711 | .mutex_sof = mt8183_mutex_sof, |
712 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
713 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
714 | .mutex_table_mod = mt8183_mutex_table_mod, |
715 | .no_clk = true, |
716 | }; |
717 | |
718 | static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = { |
719 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
720 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
721 | .mutex_table_mod = mt8186_mdp_mutex_table_mod, |
722 | }; |
723 | |
724 | static const struct mtk_mutex_data mt8186_mutex_driver_data = { |
725 | .mutex_mod = mt8186_mutex_mod, |
726 | .mutex_sof = mt8186_mutex_sof, |
727 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
728 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
729 | }; |
730 | |
731 | static const struct mtk_mutex_data mt8188_mutex_driver_data = { |
732 | .mutex_mod = mt8188_mutex_mod, |
733 | .mutex_sof = mt8188_mutex_sof, |
734 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
735 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
736 | }; |
737 | |
738 | static const struct mtk_mutex_data mt8192_mutex_driver_data = { |
739 | .mutex_mod = mt8192_mutex_mod, |
740 | .mutex_sof = mt8183_mutex_sof, |
741 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
742 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
743 | }; |
744 | |
745 | static const struct mtk_mutex_data mt8195_mutex_driver_data = { |
746 | .mutex_mod = mt8195_mutex_mod, |
747 | .mutex_sof = mt8195_mutex_sof, |
748 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
749 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
750 | }; |
751 | |
752 | static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = { |
753 | .mutex_sof = mt8195_mutex_sof, |
754 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
755 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
756 | .mutex_table_mod = mt8195_mutex_table_mod, |
757 | }; |
758 | |
759 | static const struct mtk_mutex_data mt8365_mutex_driver_data = { |
760 | .mutex_mod = mt8365_mutex_mod, |
761 | .mutex_sof = mt8183_mutex_sof, |
762 | .mutex_mod_reg = MT8183_MUTEX0_MOD0, |
763 | .mutex_sof_reg = MT8183_MUTEX0_SOF0, |
764 | .no_clk = true, |
765 | }; |
766 | |
767 | struct mtk_mutex *mtk_mutex_get(struct device *dev) |
768 | { |
769 | struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); |
770 | int i; |
771 | |
772 | for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) |
773 | if (!mtx->mutex[i].claimed) { |
774 | mtx->mutex[i].claimed = true; |
775 | return &mtx->mutex[i]; |
776 | } |
777 | |
778 | return ERR_PTR(error: -EBUSY); |
779 | } |
780 | EXPORT_SYMBOL_GPL(mtk_mutex_get); |
781 | |
782 | void mtk_mutex_put(struct mtk_mutex *mutex) |
783 | { |
784 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
785 | mutex[mutex->id]); |
786 | |
787 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
788 | |
789 | mutex->claimed = false; |
790 | } |
791 | EXPORT_SYMBOL_GPL(mtk_mutex_put); |
792 | |
793 | int mtk_mutex_prepare(struct mtk_mutex *mutex) |
794 | { |
795 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
796 | mutex[mutex->id]); |
797 | return clk_prepare_enable(clk: mtx->clk); |
798 | } |
799 | EXPORT_SYMBOL_GPL(mtk_mutex_prepare); |
800 | |
801 | void mtk_mutex_unprepare(struct mtk_mutex *mutex) |
802 | { |
803 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
804 | mutex[mutex->id]); |
805 | clk_disable_unprepare(clk: mtx->clk); |
806 | } |
807 | EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); |
808 | |
809 | void mtk_mutex_add_comp(struct mtk_mutex *mutex, |
810 | enum mtk_ddp_comp_id id) |
811 | { |
812 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
813 | mutex[mutex->id]); |
814 | unsigned int reg; |
815 | unsigned int sof_id; |
816 | unsigned int offset; |
817 | |
818 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
819 | |
820 | switch (id) { |
821 | case DDP_COMPONENT_DSI0: |
822 | sof_id = MUTEX_SOF_DSI0; |
823 | break; |
824 | case DDP_COMPONENT_DSI1: |
825 | sof_id = MUTEX_SOF_DSI0; |
826 | break; |
827 | case DDP_COMPONENT_DSI2: |
828 | sof_id = MUTEX_SOF_DSI2; |
829 | break; |
830 | case DDP_COMPONENT_DSI3: |
831 | sof_id = MUTEX_SOF_DSI3; |
832 | break; |
833 | case DDP_COMPONENT_DPI0: |
834 | sof_id = MUTEX_SOF_DPI0; |
835 | break; |
836 | case DDP_COMPONENT_DPI1: |
837 | sof_id = MUTEX_SOF_DPI1; |
838 | break; |
839 | case DDP_COMPONENT_DP_INTF0: |
840 | sof_id = MUTEX_SOF_DP_INTF0; |
841 | break; |
842 | case DDP_COMPONENT_DP_INTF1: |
843 | sof_id = MUTEX_SOF_DP_INTF1; |
844 | break; |
845 | default: |
846 | if (mtx->data->mutex_mod[id] < 32) { |
847 | offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, |
848 | mutex->id); |
849 | reg = readl_relaxed(mtx->regs + offset); |
850 | reg |= 1 << mtx->data->mutex_mod[id]; |
851 | writel_relaxed(reg, mtx->regs + offset); |
852 | } else { |
853 | offset = DISP_REG_MUTEX_MOD2(mutex->id); |
854 | reg = readl_relaxed(mtx->regs + offset); |
855 | reg |= 1 << (mtx->data->mutex_mod[id] - 32); |
856 | writel_relaxed(reg, mtx->regs + offset); |
857 | } |
858 | return; |
859 | } |
860 | |
861 | writel_relaxed(mtx->data->mutex_sof[sof_id], |
862 | mtx->regs + |
863 | DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); |
864 | } |
865 | EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); |
866 | |
867 | void mtk_mutex_remove_comp(struct mtk_mutex *mutex, |
868 | enum mtk_ddp_comp_id id) |
869 | { |
870 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
871 | mutex[mutex->id]); |
872 | unsigned int reg; |
873 | unsigned int offset; |
874 | |
875 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
876 | |
877 | switch (id) { |
878 | case DDP_COMPONENT_DSI0: |
879 | case DDP_COMPONENT_DSI1: |
880 | case DDP_COMPONENT_DSI2: |
881 | case DDP_COMPONENT_DSI3: |
882 | case DDP_COMPONENT_DPI0: |
883 | case DDP_COMPONENT_DPI1: |
884 | case DDP_COMPONENT_DP_INTF0: |
885 | case DDP_COMPONENT_DP_INTF1: |
886 | writel_relaxed(MUTEX_SOF_SINGLE_MODE, |
887 | mtx->regs + |
888 | DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, |
889 | mutex->id)); |
890 | break; |
891 | default: |
892 | if (mtx->data->mutex_mod[id] < 32) { |
893 | offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, |
894 | mutex->id); |
895 | reg = readl_relaxed(mtx->regs + offset); |
896 | reg &= ~(1 << mtx->data->mutex_mod[id]); |
897 | writel_relaxed(reg, mtx->regs + offset); |
898 | } else { |
899 | offset = DISP_REG_MUTEX_MOD2(mutex->id); |
900 | reg = readl_relaxed(mtx->regs + offset); |
901 | reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); |
902 | writel_relaxed(reg, mtx->regs + offset); |
903 | } |
904 | break; |
905 | } |
906 | } |
907 | EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); |
908 | |
909 | void mtk_mutex_enable(struct mtk_mutex *mutex) |
910 | { |
911 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
912 | mutex[mutex->id]); |
913 | |
914 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
915 | |
916 | writel(val: 1, addr: mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); |
917 | } |
918 | EXPORT_SYMBOL_GPL(mtk_mutex_enable); |
919 | |
920 | int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt) |
921 | { |
922 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
923 | mutex[mutex->id]); |
924 | struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt; |
925 | |
926 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
927 | |
928 | if (!mtx->cmdq_reg.size) { |
929 | dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set" ); |
930 | return -ENODEV; |
931 | } |
932 | |
933 | cmdq_pkt_write(pkt: cmdq_pkt, subsys: mtx->cmdq_reg.subsys, |
934 | offset: mtx->addr + DISP_REG_MUTEX_EN(mutex->id), value: 1); |
935 | return 0; |
936 | } |
937 | EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq); |
938 | |
939 | void mtk_mutex_disable(struct mtk_mutex *mutex) |
940 | { |
941 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
942 | mutex[mutex->id]); |
943 | |
944 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
945 | |
946 | writel(val: 0, addr: mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); |
947 | } |
948 | EXPORT_SYMBOL_GPL(mtk_mutex_disable); |
949 | |
950 | void mtk_mutex_acquire(struct mtk_mutex *mutex) |
951 | { |
952 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
953 | mutex[mutex->id]); |
954 | u32 tmp; |
955 | |
956 | writel(val: 1, addr: mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); |
957 | writel(val: 1, addr: mtx->regs + DISP_REG_MUTEX(mutex->id)); |
958 | if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), |
959 | tmp, tmp & INT_MUTEX, 1, 10000)) |
960 | pr_err("could not acquire mutex %d\n" , mutex->id); |
961 | } |
962 | EXPORT_SYMBOL_GPL(mtk_mutex_acquire); |
963 | |
964 | void mtk_mutex_release(struct mtk_mutex *mutex) |
965 | { |
966 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
967 | mutex[mutex->id]); |
968 | |
969 | writel(val: 0, addr: mtx->regs + DISP_REG_MUTEX(mutex->id)); |
970 | } |
971 | EXPORT_SYMBOL_GPL(mtk_mutex_release); |
972 | |
973 | int mtk_mutex_write_mod(struct mtk_mutex *mutex, |
974 | enum mtk_mutex_mod_index idx, bool clear) |
975 | { |
976 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
977 | mutex[mutex->id]); |
978 | unsigned int reg; |
979 | u32 reg_offset, id_offset = 0; |
980 | |
981 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
982 | |
983 | if (idx < MUTEX_MOD_IDX_MDP_RDMA0 || |
984 | idx >= MUTEX_MOD_IDX_MAX) { |
985 | dev_err(mtx->dev, "Not supported MOD table index : %d" , idx); |
986 | return -EINVAL; |
987 | } |
988 | |
989 | /* |
990 | * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods |
991 | * are present, hence requiring multiple 32-bits registers. |
992 | * |
993 | * The mutex_table_mod fully represents that by defining the number of |
994 | * the mod sequentially, later used as a bit number, which can be more |
995 | * than 0..31. |
996 | * |
997 | * In order to retain compatibility with older SoCs, we perform R/W on |
998 | * the single 32 bits registers, but this requires us to translate the |
999 | * mutex ID bit accordingly. |
1000 | */ |
1001 | if (mtx->data->mutex_table_mod[idx] < 32) { |
1002 | reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, |
1003 | mutex->id); |
1004 | } else { |
1005 | reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, |
1006 | mutex->id); |
1007 | id_offset = 32; |
1008 | } |
1009 | |
1010 | reg = readl_relaxed(mtx->regs + reg_offset); |
1011 | if (clear) |
1012 | reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset); |
1013 | else |
1014 | reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset); |
1015 | |
1016 | writel_relaxed(reg, mtx->regs + reg_offset); |
1017 | |
1018 | return 0; |
1019 | } |
1020 | EXPORT_SYMBOL_GPL(mtk_mutex_write_mod); |
1021 | |
1022 | int mtk_mutex_write_sof(struct mtk_mutex *mutex, |
1023 | enum mtk_mutex_sof_index idx) |
1024 | { |
1025 | struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, |
1026 | mutex[mutex->id]); |
1027 | |
1028 | WARN_ON(&mtx->mutex[mutex->id] != mutex); |
1029 | |
1030 | if (idx < MUTEX_SOF_IDX_SINGLE_MODE || |
1031 | idx >= MUTEX_SOF_IDX_MAX) { |
1032 | dev_err(mtx->dev, "Not supported SOF index : %d" , idx); |
1033 | return -EINVAL; |
1034 | } |
1035 | |
1036 | writel_relaxed(idx, mtx->regs + |
1037 | DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); |
1038 | |
1039 | return 0; |
1040 | } |
1041 | EXPORT_SYMBOL_GPL(mtk_mutex_write_sof); |
1042 | |
1043 | static int mtk_mutex_probe(struct platform_device *pdev) |
1044 | { |
1045 | struct device *dev = &pdev->dev; |
1046 | struct mtk_mutex_ctx *mtx; |
1047 | struct resource *regs; |
1048 | int i, ret; |
1049 | |
1050 | mtx = devm_kzalloc(dev, size: sizeof(*mtx), GFP_KERNEL); |
1051 | if (!mtx) |
1052 | return -ENOMEM; |
1053 | |
1054 | for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) |
1055 | mtx->mutex[i].id = i; |
1056 | |
1057 | mtx->data = of_device_get_match_data(dev); |
1058 | |
1059 | if (!mtx->data->no_clk) { |
1060 | mtx->clk = devm_clk_get(dev, NULL); |
1061 | if (IS_ERR(ptr: mtx->clk)) |
1062 | return dev_err_probe(dev, err: PTR_ERR(ptr: mtx->clk), fmt: "Failed to get clock\n" ); |
1063 | } |
1064 | |
1065 | mtx->regs = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: ®s); |
1066 | if (IS_ERR(ptr: mtx->regs)) { |
1067 | dev_err(dev, "Failed to map mutex registers\n" ); |
1068 | return PTR_ERR(ptr: mtx->regs); |
1069 | } |
1070 | mtx->addr = regs->start; |
1071 | |
1072 | /* CMDQ is optional */ |
1073 | ret = cmdq_dev_get_client_reg(dev, client_reg: &mtx->cmdq_reg, idx: 0); |
1074 | if (ret) |
1075 | dev_dbg(dev, "No mediatek,gce-client-reg!\n" ); |
1076 | |
1077 | platform_set_drvdata(pdev, data: mtx); |
1078 | |
1079 | return 0; |
1080 | } |
1081 | |
1082 | static const struct of_device_id mutex_driver_dt_match[] = { |
1083 | { .compatible = "mediatek,mt2701-disp-mutex" , .data = &mt2701_mutex_driver_data }, |
1084 | { .compatible = "mediatek,mt2712-disp-mutex" , .data = &mt2712_mutex_driver_data }, |
1085 | { .compatible = "mediatek,mt6795-disp-mutex" , .data = &mt6795_mutex_driver_data }, |
1086 | { .compatible = "mediatek,mt8167-disp-mutex" , .data = &mt8167_mutex_driver_data }, |
1087 | { .compatible = "mediatek,mt8173-disp-mutex" , .data = &mt8173_mutex_driver_data }, |
1088 | { .compatible = "mediatek,mt8183-disp-mutex" , .data = &mt8183_mutex_driver_data }, |
1089 | { .compatible = "mediatek,mt8186-disp-mutex" , .data = &mt8186_mutex_driver_data }, |
1090 | { .compatible = "mediatek,mt8186-mdp3-mutex" , .data = &mt8186_mdp_mutex_driver_data }, |
1091 | { .compatible = "mediatek,mt8188-disp-mutex" , .data = &mt8188_mutex_driver_data }, |
1092 | { .compatible = "mediatek,mt8192-disp-mutex" , .data = &mt8192_mutex_driver_data }, |
1093 | { .compatible = "mediatek,mt8195-disp-mutex" , .data = &mt8195_mutex_driver_data }, |
1094 | { .compatible = "mediatek,mt8195-vpp-mutex" , .data = &mt8195_vpp_mutex_driver_data }, |
1095 | { .compatible = "mediatek,mt8365-disp-mutex" , .data = &mt8365_mutex_driver_data }, |
1096 | { /* sentinel */ }, |
1097 | }; |
1098 | MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); |
1099 | |
1100 | static struct platform_driver mtk_mutex_driver = { |
1101 | .probe = mtk_mutex_probe, |
1102 | .driver = { |
1103 | .name = "mediatek-mutex" , |
1104 | .of_match_table = mutex_driver_dt_match, |
1105 | }, |
1106 | }; |
1107 | module_platform_driver(mtk_mutex_driver); |
1108 | |
1109 | MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>" ); |
1110 | MODULE_DESCRIPTION("MediaTek SoC MUTEX driver" ); |
1111 | MODULE_LICENSE("GPL" ); |
1112 | |