1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (C) 2022 MediaTek Inc.
4	* Copyright (C) 2022 Collabora Ltd.
5	* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6	*/
7
8	#include <linux/bitfield.h>
9	#include <linux/bits.h>
10	#include <linux/clk.h>
11	#include <linux/completion.h>
12	#include <linux/cpu.h>
13	#include <linux/cpuidle.h>
14	#include <linux/debugfs.h>
15	#include <linux/device.h>
16	#include <linux/init.h>
17	#include <linux/interrupt.h>
18	#include <linux/kernel.h>
19	#include <linux/kthread.h>
20	#include <linux/module.h>
21	#include <linux/mutex.h>
22	#include <linux/nvmem-consumer.h>
23	#include <linux/of_address.h>
24	#include <linux/of_irq.h>
25	#include <linux/of_platform.h>
26	#include <linux/platform_device.h>
27	#include <linux/pm_domain.h>
28	#include <linux/pm_opp.h>
29	#include <linux/pm_runtime.h>
30	#include <linux/regulator/consumer.h>
31	#include <linux/reset.h>
32	#include <linux/seq_file.h>
33	#include <linux/slab.h>
34	#include <linux/spinlock.h>
35	#include <linux/thermal.h>
36
37	/* svs bank mode support */
38	#define SVSB_MODE_ALL_DISABLE 0
39	#define SVSB_MODE_INIT01 BIT(1)
40	#define SVSB_MODE_INIT02 BIT(2)
41	#define SVSB_MODE_MON BIT(3)
42
43	/* svs bank volt flags */
44	#define SVSB_INIT01_PD_REQ BIT(0)
45	#define SVSB_INIT01_VOLT_IGNORE BIT(1)
46	#define SVSB_INIT01_VOLT_INC_ONLY BIT(2)
47	#define SVSB_MON_VOLT_IGNORE BIT(16)
48	#define SVSB_REMOVE_DVTFIXED_VOLT BIT(24)
49
50	/* svs bank register fields and common configuration */
51	#define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0)
52	#define SVSB_DET_MAX FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff)
53	#define SVSB_DET_WINDOW 0xa28
54
55	/* DESCHAR */
56	#define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0)
57	#define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8)
58
59	/* TEMPCHAR */
60	#define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0)
61	#define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8)
62	#define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16)
63
64	/* DETCHAR */
65	#define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0)
66	#define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8)
67
68	/* SVSEN (PTPEN) */
69	#define SVSB_PTPEN_INIT01 BIT(0)
70	#define SVSB_PTPEN_MON BIT(1)
71	#define SVSB_PTPEN_INIT02 (SVSB_PTPEN_INIT01 | BIT(2))
72	#define SVSB_PTPEN_OFF 0x0
73
74	/* FREQPCTS */
75	#define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0)
76	#define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8)
77	#define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16)
78	#define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24)
79
80	/* INTSTS */
81	#define SVSB_INTSTS_VAL_CLEAN 0x00ffffff
82	#define SVSB_INTSTS_F0_COMPLETE BIT(0)
83	#define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16)
84	#define SVSB_RUNCONFIG_DEFAULT 0x80000000
85
86	/* LIMITVALS */
87	#define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0)
88	#define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8)
89	#define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16)
90	#define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24)
91	#define SVSB_VAL_DTHI 0x1
92	#define SVSB_VAL_DTLO 0xfe
93
94	/* INTEN */
95	#define SVSB_INTEN_F0EN BIT(0)
96	#define SVSB_INTEN_DACK0UPEN BIT(8)
97	#define SVSB_INTEN_DC0EN BIT(9)
98	#define SVSB_INTEN_DC1EN BIT(10)
99	#define SVSB_INTEN_DACK0LOEN BIT(11)
100	#define SVSB_INTEN_INITPROD_OVF_EN BIT(12)
101	#define SVSB_INTEN_INITSUM_OVF_EN BIT(14)
102	#define SVSB_INTEN_MONVOPEN GENMASK(23, 16)
103	#define SVSB_INTEN_INIT0x (SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN | \
104	SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN | \
105	SVSB_INTEN_DACK0LOEN | \
106	SVSB_INTEN_INITPROD_OVF_EN | \
107	SVSB_INTEN_INITSUM_OVF_EN)
108
109	/* TSCALCS */
110	#define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0)
111	#define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12)
112
113	/* INIT2VALS */
114	#define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0)
115	#define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16)
116
117	/* VOPS */
118	#define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0)
119	#define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8)
120	#define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16)
121	#define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24)
122
123	/* SVS Thermal Coefficients */
124	#define SVSB_TS_COEFF_MT8195 250460
125	#define SVSB_TS_COEFF_MT8186 204650
126
127	/* Algo helpers */
128	#define FUSE_DATA_NOT_VALID U32_MAX
129
130	/* svs bank related setting */
131	#define BITS8 8
132	#define MAX_OPP_ENTRIES 16
133	#define REG_BYTES 4
134	#define SVSB_DC_SIGNED_BIT BIT(15)
135	#define SVSB_DET_CLK_EN BIT(31)
136	#define SVSB_TEMP_LOWER_BOUND 0xb2
137	#define SVSB_TEMP_UPPER_BOUND 0x64
138
139	static DEFINE_SPINLOCK(svs_lock);
140
141	#ifdef CONFIG_DEBUG_FS
142	#define debug_fops_ro(name) \
143	static int svs_##name##_debug_open(struct inode *inode, \
144	struct file *filp) \
145	{ \
146	return single_open(filp, svs_##name##_debug_show, \
147	inode->i_private); \
148	} \
149	static const struct file_operations svs_##name##_debug_fops = { \
150	.owner = THIS_MODULE, \
151	.open = svs_##name##_debug_open, \
152	.read = seq_read, \
153	.llseek = seq_lseek, \
154	.release = single_release, \
155	}
156
157	#define debug_fops_rw(name) \
158	static int svs_##name##_debug_open(struct inode *inode, \
159	struct file *filp) \
160	{ \
161	return single_open(filp, svs_##name##_debug_show, \
162	inode->i_private); \
163	} \
164	static const struct file_operations svs_##name##_debug_fops = { \
165	.owner = THIS_MODULE, \
166	.open = svs_##name##_debug_open, \
167	.read = seq_read, \
168	.write = svs_##name##_debug_write, \
169	.llseek = seq_lseek, \
170	.release = single_release, \
171	}
172
173	#define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops}
174	#endif
175
176	/**
177	* enum svsb_sw_id - SVS Bank Software ID
178	* @SVSB_SWID_CPU_LITTLE: CPU little cluster Bank
179	* @SVSB_SWID_CPU_BIG: CPU big cluster Bank
180	* @SVSB_SWID_CCI: Cache Coherent Interconnect Bank
181	* @SVSB_SWID_GPU: GPU Bank
182	* @SVSB_SWID_MAX: Total number of Banks
183	*/
184	enum svsb_sw_id {
185	SVSB_SWID_CPU_LITTLE,
186	SVSB_SWID_CPU_BIG,
187	SVSB_SWID_CCI,
188	SVSB_SWID_GPU,
189	SVSB_SWID_MAX
190	};
191
192	/**
193	* enum svsb_type - SVS Bank 2-line: Type and Role
194	* @SVSB_TYPE_NONE: One-line type Bank - Global role
195	* @SVSB_TYPE_LOW: Two-line type Bank - Low bank role
196	* @SVSB_TYPE_HIGH: Two-line type Bank - High bank role
197	* @SVSB_TYPE_MAX: Total number of bank types
198	*/
199	enum svsb_type {
200	SVSB_TYPE_NONE,
201	SVSB_TYPE_LOW,
202	SVSB_TYPE_HIGH,
203	SVSB_TYPE_MAX
204	};
205
206	/**
207	* enum svsb_phase - svs bank phase enumeration
208	* @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
209	* @SVSB_PHASE_INIT01: svs bank basic init for data calibration
210	* @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
211	* @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
212	* @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
213	*
214	* Each svs bank has its own independent phase and we enable each svs bank by
215	* running their phase orderly. However, when svs bank encounters unexpected
216	* condition, it will fire an irq (PHASE_ERROR) to inform svs software.
217	*
218	* svs bank general phase-enabled order:
219	* SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
220	*/
221	enum svsb_phase {
222	SVSB_PHASE_ERROR = 0,
223	SVSB_PHASE_INIT01,
224	SVSB_PHASE_INIT02,
225	SVSB_PHASE_MON,
226	SVSB_PHASE_MAX,
227	};
228
229	enum svs_reg_index {
230	DESCHAR = 0,
231	TEMPCHAR,
232	DETCHAR,
233	AGECHAR,
234	DCCONFIG,
235	AGECONFIG,
236	FREQPCT30,
237	FREQPCT74,
238	LIMITVALS,
239	VBOOT,
240	DETWINDOW,
241	CONFIG,
242	TSCALCS,
243	RUNCONFIG,
244	SVSEN,
245	INIT2VALS,
246	DCVALUES,
247	AGEVALUES,
248	VOP30,
249	VOP74,
250	TEMP,
251	INTSTS,
252	INTSTSRAW,
253	INTEN,
254	CHKINT,
255	CHKSHIFT,
256	STATUS,
257	VDESIGN30,
258	VDESIGN74,
259	DVT30,
260	DVT74,
261	AGECOUNT,
262	SMSTATE0,
263	SMSTATE1,
264	CTL0,
265	DESDETSEC,
266	TEMPAGESEC,
267	CTRLSPARE0,
268	CTRLSPARE1,
269	CTRLSPARE2,
270	CTRLSPARE3,
271	CORESEL,
272	THERMINTST,
273	INTST,
274	THSTAGE0ST,
275	THSTAGE1ST,
276	THSTAGE2ST,
277	THAHBST0,
278	THAHBST1,
279	SPARE0,
280	SPARE1,
281	SPARE2,
282	SPARE3,
283	THSLPEVEB,
284	SVS_REG_MAX,
285	};
286
287	static const u32 svs_regs_v2[] = {
288	[DESCHAR] = 0x00,
289	[TEMPCHAR] = 0x04,
290	[DETCHAR] = 0x08,
291	[AGECHAR] = 0x0c,
292	[DCCONFIG] = 0x10,
293	[AGECONFIG] = 0x14,
294	[FREQPCT30] = 0x18,
295	[FREQPCT74] = 0x1c,
296	[LIMITVALS] = 0x20,
297	[VBOOT] = 0x24,
298	[DETWINDOW] = 0x28,
299	[CONFIG] = 0x2c,
300	[TSCALCS] = 0x30,
301	[RUNCONFIG] = 0x34,
302	[SVSEN] = 0x38,
303	[INIT2VALS] = 0x3c,
304	[DCVALUES] = 0x40,
305	[AGEVALUES] = 0x44,
306	[VOP30] = 0x48,
307	[VOP74] = 0x4c,
308	[TEMP] = 0x50,
309	[INTSTS] = 0x54,
310	[INTSTSRAW] = 0x58,
311	[INTEN] = 0x5c,
312	[CHKINT] = 0x60,
313	[CHKSHIFT] = 0x64,
314	[STATUS] = 0x68,
315	[VDESIGN30] = 0x6c,
316	[VDESIGN74] = 0x70,
317	[DVT30] = 0x74,
318	[DVT74] = 0x78,
319	[AGECOUNT] = 0x7c,
320	[SMSTATE0] = 0x80,
321	[SMSTATE1] = 0x84,
322	[CTL0] = 0x88,
323	[DESDETSEC] = 0xe0,
324	[TEMPAGESEC] = 0xe4,
325	[CTRLSPARE0] = 0xf0,
326	[CTRLSPARE1] = 0xf4,
327	[CTRLSPARE2] = 0xf8,
328	[CTRLSPARE3] = 0xfc,
329	[CORESEL] = 0x300,
330	[THERMINTST] = 0x304,
331	[INTST] = 0x308,
332	[THSTAGE0ST] = 0x30c,
333	[THSTAGE1ST] = 0x310,
334	[THSTAGE2ST] = 0x314,
335	[THAHBST0] = 0x318,
336	[THAHBST1] = 0x31c,
337	[SPARE0] = 0x320,
338	[SPARE1] = 0x324,
339	[SPARE2] = 0x328,
340	[SPARE3] = 0x32c,
341	[THSLPEVEB] = 0x330,
342	};
343
344	static const char * const svs_swid_names[SVSB_SWID_MAX] = {
345	"SVSB_CPU_LITTLE", "SVSB_CPU_BIG", "SVSB_CCI", "SVSB_GPU"
346	};
347
348	static const char * const svs_type_names[SVSB_TYPE_MAX] = {
349	"", "_LOW", "_HIGH"
350	};
351
352	enum svs_fusemap_dev {
353	BDEV_BDES,
354	BDEV_MDES,
355	BDEV_MTDES,
356	BDEV_DCBDET,
357	BDEV_DCMDET,
358	BDEV_MAX
359	};
360
361	enum svs_fusemap_glb {
362	GLB_FT_PGM,
363	GLB_VMIN,
364	GLB_MAX
365	};
366
367	struct svs_fusemap {
368	s8 index;
369	u8 ofst;
370	};
371
372	/**
373	* struct svs_platform - svs platform control
374	* @base: svs platform register base
375	* @dev: svs platform device
376	* @main_clk: main clock for svs bank
377	* @banks: svs banks that svs platform supports
378	* @rst: svs platform reset control
379	* @efuse_max: total number of svs efuse
380	* @tefuse_max: total number of thermal efuse
381	* @regs: svs platform registers map
382	* @efuse: svs efuse data received from NVMEM framework
383	* @tefuse: thermal efuse data received from NVMEM framework
384	* @ts_coeff: thermal sensors coefficient
385	* @bank_max: total number of svs banks
386	*/
387	struct svs_platform {
388	void __iomem *base;
389	struct device *dev;
390	struct clk *main_clk;
391	struct svs_bank *banks;
392	struct reset_control *rst;
393	size_t efuse_max;
394	size_t tefuse_max;
395	const u32 *regs;
396	u32 *efuse;
397	u32 *tefuse;
398	u32 ts_coeff;
399	u16 bank_max;
400	};
401
402	struct svs_platform_data {
403	char *name;
404	struct svs_bank *banks;
405	bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata);
406	int (*probe)(struct svs_platform *svsp);
407	const struct svs_fusemap *glb_fuse_map;
408	const u32 *regs;
409	u32 ts_coeff;
410	u16 bank_max;
411	};
412
413	/**
414	* struct svs_bank_pdata - SVS Bank immutable config parameters
415	* @dev_fuse_map: Bank fuse map data
416	* @buck_name: Regulator name
417	* @tzone_name: Thermal zone name
418	* @age_config: Bank age configuration
419	* @ctl0: TS-x selection
420	* @dc_config: Bank dc configuration
421	* @int_st: Bank interrupt identification
422	* @turn_freq_base: Reference frequency for 2-line turn point
423	* @tzone_htemp: Thermal zone high temperature threshold
424	* @tzone_ltemp: Thermal zone low temperature threshold
425	* @volt_step: Bank voltage step
426	* @volt_base: Bank voltage base
427	* @tzone_htemp_voffset: Thermal zone high temperature voltage offset
428	* @tzone_ltemp_voffset: Thermal zone low temperature voltage offset
429	* @chk_shift: Bank chicken shift
430	* @cpu_id: CPU core ID for SVS CPU bank use only
431	* @opp_count: Bank opp count
432	* @vboot: Voltage request for bank init01 only
433	* @vco: Bank VCO value
434	* @sw_id: Bank software identification
435	* @type: SVS Bank Type (1 or 2-line) and Role (high/low)
436	* @set_freq_pct: function pointer to set bank frequency percent table
437	* @get_volts: function pointer to get bank voltages
438	*/
439	struct svs_bank_pdata {
440	const struct svs_fusemap *dev_fuse_map;
441	char *buck_name;
442	char *tzone_name;
443	u32 age_config;
444	u32 ctl0;
445	u32 dc_config;
446	u32 int_st;
447	u32 turn_freq_base;
448	u32 tzone_htemp;
449	u32 tzone_ltemp;
450	u32 volt_step;
451	u32 volt_base;
452	u16 tzone_htemp_voffset;
453	u16 tzone_ltemp_voffset;
454	u8 chk_shift;
455	u8 cpu_id;
456	u8 opp_count;
457	u8 vboot;
458	u8 vco;
459	u8 sw_id;
460	u8 type;
461
462	/* Callbacks */
463	void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb);
464	void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb);
465	};
466
467	/**
468	* struct svs_bank - svs bank representation
469	* @pdata: SVS Bank immutable config parameters
470	* @dev: bank device
471	* @opp_dev: device for opp table/buck control
472	* @init_completion: the timeout completion for bank init
473	* @buck: regulator used by opp_dev
474	* @tzd: thermal zone device for getting temperature
475	* @lock: mutex lock to protect voltage update process
476	* @name: bank name
477	* @phase: bank current phase
478	* @volt_od: bank voltage overdrive
479	* @reg_data: bank register data in different phase for debug purpose
480	* @pm_runtime_enabled_count: bank pm runtime enabled count
481	* @mode_support: bank mode support
482	* @freq_base: reference frequency for bank init
483	* @opp_dfreq: default opp frequency table
484	* @opp_dvolt: default opp voltage table
485	* @freq_pct: frequency percent table for bank init
486	* @volt: bank voltage table
487	* @volt_flags: bank voltage flags
488	* @vmax: bank voltage maximum
489	* @vmin: bank voltage minimum
490	* @age_voffset_in: bank age voltage offset
491	* @dc_voffset_in: bank dc voltage offset
492	* @dvt_fixed: bank dvt fixed value
493	* @core_sel: bank selection
494	* @temp: bank temperature
495	* @bts: svs efuse data
496	* @mts: svs efuse data
497	* @bdes: svs efuse data
498	* @mdes: svs efuse data
499	* @mtdes: svs efuse data
500	* @dcbdet: svs efuse data
501	* @dcmdet: svs efuse data
502	* @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
503	* @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden
504	*
505	* Svs bank will generate suitable voltages by below general math equation
506	* and provide these voltages to opp voltage table.
507	*
508	* opp_volt[i] = (volt[i] * volt_step) + volt_base;
509	*/
510	struct svs_bank {
511	const struct svs_bank_pdata pdata;
512	struct device *dev;
513	struct device *opp_dev;
514	struct completion init_completion;
515	struct regulator *buck;
516	struct thermal_zone_device *tzd;
517	struct mutex lock;
518	int pm_runtime_enabled_count;
519	short int volt_od;
520	char *name;
521	enum svsb_phase phase;
522	u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX];
523	u8 mode_support;
524	u32 opp_dfreq[MAX_OPP_ENTRIES];
525	u32 opp_dvolt[MAX_OPP_ENTRIES];
526	u32 freq_pct[MAX_OPP_ENTRIES];
527	u32 volt[MAX_OPP_ENTRIES];
528	u32 volt_flags;
529	u32 freq_base;
530	u32 turn_pt;
531	u32 vbin_turn_pt;
532	u32 core_sel;
533	u32 temp;
534	u16 age_voffset_in;
535	u16 dc_voffset_in;
536	u8 dvt_fixed;
537	u8 vmax;
538	u8 vmin;
539	u16 bts;
540	u16 mts;
541	u16 bdes;
542	u16 mdes;
543	u8 mtdes;
544	u8 dcbdet;
545	u8 dcmdet;
546	};
547
548	static u32 percent(u32 numerator, u32 denominator)
549	{
550	/* If not divide 1000, "numerator * 100" will have data overflow. */
551	numerator /= 1000;
552	denominator /= 1000;
553
554	return DIV_ROUND_UP(numerator * 100, denominator);
555	}
556
557	static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i)
558	{
559	return readl_relaxed(svsp->base + svsp->regs[rg_i]);
560	}
561
562	static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,
563	enum svs_reg_index rg_i)
564	{
565	writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
566	}
567
568	static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb)
569	{
570	svs_writel_relaxed(svsp, val: svsb->core_sel, rg_i: CORESEL);
571	}
572
573	static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
574	u32 svsb_volt_base)
575	{
576	return (svsb_volt * svsb_volt_step) + svsb_volt_base;
577	}
578
579	static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step,
580	u32 svsb_volt_base)
581	{
582	return (opp_u_volt - svsb_volt_base) / svsb_volt_step;
583	}
584
585	static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb)
586	{
587	const struct svs_bank_pdata *bdata = &svsb->pdata;
588	struct dev_pm_opp *opp;
589	u32 i, opp_u_volt;
590
591	for (i = 0; i < bdata->opp_count; i++) {
592	opp = dev_pm_opp_find_freq_exact(dev: svsb->opp_dev,
593	freq: svsb->opp_dfreq[i],
594	available: true);
595	if (IS_ERR(ptr: opp)) {
596	dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
597	svsb->opp_dfreq[i], PTR_ERR(opp));
598	return PTR_ERR(ptr: opp);
599	}
600
601	opp_u_volt = dev_pm_opp_get_voltage(opp);
602	svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
603	svsb_volt_step: bdata->volt_step,
604	svsb_volt_base: bdata->volt_base);
605	dev_pm_opp_put(opp);
606	}
607
608	return 0;
609	}
610
611	static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
612	{
613	int ret = -EPERM, tzone_temp = 0;
614	const struct svs_bank_pdata *bdata = &svsb->pdata;
615	u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop;
616
617	mutex_lock(&svsb->lock);
618
619	/*
620	* 2-line bank updates its corresponding opp volts.
621	* 1-line bank updates all opp volts.
622	*/
623	if (bdata->type == SVSB_TYPE_HIGH) {
624	opp_start = 0;
625	opp_stop = svsb->turn_pt;
626	} else if (bdata->type == SVSB_TYPE_LOW) {
627	opp_start = svsb->turn_pt;
628	opp_stop = bdata->opp_count;
629	} else {
630	opp_start = 0;
631	opp_stop = bdata->opp_count;
632	}
633
634	/* Get thermal effect */
635	if (!IS_ERR_OR_NULL(ptr: svsb->tzd)) {
636	ret = thermal_zone_get_temp(tz: svsb->tzd, temp: &tzone_temp);
637	if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
638	svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
639	dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
640	bdata->tzone_name, ret, svsb->temp);
641	svsb->phase = SVSB_PHASE_ERROR;
642	}
643
644	if (tzone_temp >= bdata->tzone_htemp)
645	temp_voffset += bdata->tzone_htemp_voffset;
646	else if (tzone_temp <= bdata->tzone_ltemp)
647	temp_voffset += bdata->tzone_ltemp_voffset;
648
649	/* 2-line bank update all opp volts when running mon mode */
650	if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH ||
651	bdata->type == SVSB_TYPE_LOW)) {
652	opp_start = 0;
653	opp_stop = bdata->opp_count;
654	}
655	}
656
657	/* vmin <= svsb_volt (opp_volt) <= default opp voltage */
658	for (i = opp_start; i < opp_stop; i++) {
659	switch (svsb->phase) {
660	case SVSB_PHASE_ERROR:
661	opp_volt = svsb->opp_dvolt[i];
662	break;
663	case SVSB_PHASE_INIT01:
664	/* do nothing */
665	goto unlock_mutex;
666	case SVSB_PHASE_INIT02:
667	case SVSB_PHASE_MON:
668	svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
669	opp_volt = svs_bank_volt_to_opp_volt(svsb_volt,
670	svsb_volt_step: bdata->volt_step,
671	svsb_volt_base: bdata->volt_base);
672	break;
673	default:
674	dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
675	ret = -EINVAL;
676	goto unlock_mutex;
677	}
678
679	opp_volt = min(opp_volt, svsb->opp_dvolt[i]);
680	ret = dev_pm_opp_adjust_voltage(dev: svsb->opp_dev,
681	freq: svsb->opp_dfreq[i],
682	u_volt: opp_volt, u_volt_min: opp_volt,
683	u_volt_max: svsb->opp_dvolt[i]);
684	if (ret) {
685	dev_err(svsb->dev, "set %uuV fail: %d\n",
686	opp_volt, ret);
687	goto unlock_mutex;
688	}
689	}
690
691	unlock_mutex:
692	mutex_unlock(lock: &svsb->lock);
693
694	return ret;
695	}
696
697	static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp,
698	struct svs_bank *svsb)
699	{
700	unsigned long flags;
701
702	if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
703	return;
704
705	spin_lock_irqsave(&svs_lock, flags);
706	svs_switch_bank(svsp, svsb);
707	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, rg_i: SVSEN);
708	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, rg_i: INTSTS);
709	spin_unlock_irqrestore(lock: &svs_lock, flags);
710
711	svsb->phase = SVSB_PHASE_ERROR;
712	svs_adjust_pm_opp_volts(svsb);
713	}
714
715	#ifdef CONFIG_DEBUG_FS
716	static int svs_dump_debug_show(struct seq_file *m, void *p)
717	{
718	struct svs_platform *svsp = (struct svs_platform *)m->private;
719	struct svs_bank *svsb;
720	unsigned long svs_reg_addr;
721	u32 idx, i, j, bank_id;
722
723	for (i = 0; i < svsp->efuse_max; i++)
724	if (svsp->efuse && svsp->efuse[i])
725	seq_printf(m, fmt: "M_HW_RES%d = 0x%08x\n",
726	i, svsp->efuse[i]);
727
728	for (i = 0; i < svsp->tefuse_max; i++)
729	if (svsp->tefuse)
730	seq_printf(m, fmt: "THERMAL_EFUSE%d = 0x%08x\n",
731	i, svsp->tefuse[i]);
732
733	for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
734	svsb = &svsp->banks[idx];
735
736	for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) {
737	seq_printf(m, fmt: "Bank_number = %u\n", bank_id);
738
739	if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02)
740	seq_printf(m, fmt: "mode = init%d\n", i);
741	else if (i == SVSB_PHASE_MON)
742	seq_puts(m, s: "mode = mon\n");
743	else
744	seq_puts(m, s: "mode = error\n");
745
746	for (j = DESCHAR; j < SVS_REG_MAX; j++) {
747	svs_reg_addr = (unsigned long)(svsp->base +
748	svsp->regs[j]);
749	seq_printf(m, fmt: "0x%08lx = 0x%08x\n",
750	svs_reg_addr, svsb->reg_data[i][j]);
751	}
752	}
753	}
754
755	return 0;
756	}
757
758	debug_fops_ro(dump);
759
760	static int svs_enable_debug_show(struct seq_file *m, void *v)
761	{
762	struct svs_bank *svsb = (struct svs_bank *)m->private;
763
764	switch (svsb->phase) {
765	case SVSB_PHASE_ERROR:
766	seq_puts(m, s: "disabled\n");
767	break;
768	case SVSB_PHASE_INIT01:
769	seq_puts(m, s: "init1\n");
770	break;
771	case SVSB_PHASE_INIT02:
772	seq_puts(m, s: "init2\n");
773	break;
774	case SVSB_PHASE_MON:
775	seq_puts(m, s: "mon mode\n");
776	break;
777	default:
778	seq_puts(m, s: "unknown\n");
779	break;
780	}
781
782	return 0;
783	}
784
785	static ssize_t svs_enable_debug_write(struct file *filp,
786	const char __user *buffer,
787	size_t count, loff_t *pos)
788	{
789	struct svs_bank *svsb = file_inode(f: filp)->i_private;
790	struct svs_platform *svsp = dev_get_drvdata(dev: svsb->dev);
791	int enabled, ret;
792	char *buf = NULL;
793
794	if (count >= PAGE_SIZE)
795	return -EINVAL;
796
797	buf = (char *)memdup_user_nul(buffer, count);
798	if (IS_ERR(ptr: buf))
799	return PTR_ERR(ptr: buf);
800
801	ret = kstrtoint(s: buf, base: 10, res: &enabled);
802	if (ret)
803	return ret;
804
805	if (!enabled) {
806	svs_bank_disable_and_restore_default_volts(svsp, svsb);
807	svsb->mode_support = SVSB_MODE_ALL_DISABLE;
808	}
809
810	kfree(objp: buf);
811
812	return count;
813	}
814
815	debug_fops_rw(enable);
816
817	static int svs_status_debug_show(struct seq_file *m, void *v)
818	{
819	struct svs_bank *svsb = (struct svs_bank *)m->private;
820	struct dev_pm_opp *opp;
821	int tzone_temp = 0, ret;
822	u32 i;
823
824	ret = thermal_zone_get_temp(tz: svsb->tzd, temp: &tzone_temp);
825	if (ret)
826	seq_printf(m, fmt: "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n",
827	svsb->name, svsb->vbin_turn_pt, svsb->turn_pt);
828	else
829	seq_printf(m, fmt: "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n",
830	svsb->name, tzone_temp, svsb->vbin_turn_pt,
831	svsb->turn_pt);
832
833	for (i = 0; i < svsb->pdata.opp_count; i++) {
834	opp = dev_pm_opp_find_freq_exact(dev: svsb->opp_dev,
835	freq: svsb->opp_dfreq[i], available: true);
836	if (IS_ERR(ptr: opp)) {
837	seq_printf(m, fmt: "%s: cannot find freq = %u (%ld)\n",
838	svsb->name, svsb->opp_dfreq[i],
839	PTR_ERR(ptr: opp));
840	return PTR_ERR(ptr: opp);
841	}
842
843	seq_printf(m, fmt: "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ",
844	i, svsb->opp_dfreq[i], i,
845	dev_pm_opp_get_voltage(opp));
846	seq_printf(m, fmt: "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n",
847	i, svsb->volt[i], i, svsb->freq_pct[i]);
848	dev_pm_opp_put(opp);
849	}
850
851	return 0;
852	}
853
854	debug_fops_ro(status);
855
856	static int svs_create_debug_cmds(struct svs_platform *svsp)
857	{
858	struct svs_bank *svsb;
859	struct dentry *svs_dir, *svsb_dir, *file_entry;
860	const char *d = "/sys/kernel/debug/svs";
861	u32 i, idx;
862
863	struct svs_dentry {
864	const char *name;
865	const struct file_operations *fops;
866	};
867
868	struct svs_dentry svs_entries[] = {
869	svs_dentry_data(dump),
870	};
871
872	struct svs_dentry svsb_entries[] = {
873	svs_dentry_data(enable),
874	svs_dentry_data(status),
875	};
876
877	svs_dir = debugfs_create_dir(name: "svs", NULL);
878	if (IS_ERR(ptr: svs_dir)) {
879	dev_err(svsp->dev, "cannot create %s: %ld\n",
880	d, PTR_ERR(svs_dir));
881	return PTR_ERR(ptr: svs_dir);
882	}
883
884	for (i = 0; i < ARRAY_SIZE(svs_entries); i++) {
885	file_entry = debugfs_create_file(name: svs_entries[i].name, mode: 0664,
886	parent: svs_dir, data: svsp,
887	fops: svs_entries[i].fops);
888	if (IS_ERR(ptr: file_entry)) {
889	dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
890	d, svs_entries[i].name, PTR_ERR(file_entry));
891	return PTR_ERR(ptr: file_entry);
892	}
893	}
894
895	for (idx = 0; idx < svsp->bank_max; idx++) {
896	svsb = &svsp->banks[idx];
897
898	if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
899	continue;
900
901	svsb_dir = debugfs_create_dir(name: svsb->name, parent: svs_dir);
902	if (IS_ERR(ptr: svsb_dir)) {
903	dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
904	d, svsb->name, PTR_ERR(svsb_dir));
905	return PTR_ERR(ptr: svsb_dir);
906	}
907
908	for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) {
909	file_entry = debugfs_create_file(name: svsb_entries[i].name,
910	mode: 0664, parent: svsb_dir, data: svsb,
911	fops: svsb_entries[i].fops);
912	if (IS_ERR(ptr: file_entry)) {
913	dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
914	d, svsb->name, svsb_entries[i].name,
915	PTR_ERR(file_entry));
916	return PTR_ERR(ptr: file_entry);
917	}
918	}
919	}
920
921	return 0;
922	}
923	#endif /* CONFIG_DEBUG_FS */
924
925	static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)
926	{
927	u32 vx;
928
929	if (v0 == v1 || f0 == f1)
930	return v0;
931
932	/* *100 to have decimal fraction factor */
933	vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx));
934
935	return DIV_ROUND_UP(vx, 100);
936	}
937
938	static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb)
939	{
940	const struct svs_bank_pdata *bdata = &svsb->pdata;
941	u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
942	u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0;
943	u32 middle_index = (bdata->opp_count / 2);
944
945	if (svsb->phase == SVSB_PHASE_MON &&
946	svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
947	return;
948
949	vop74 = svs_readl_relaxed(svsp, rg_i: VOP74);
950	vop30 = svs_readl_relaxed(svsp, rg_i: VOP30);
951
952	/* Target is to set svsb->volt[] by algorithm */
953	if (turn_pt < middle_index) {
954	if (bdata->type == SVSB_TYPE_HIGH) {
955	/* volt[0] ~ volt[turn_pt - 1] */
956	for (i = 0; i < turn_pt; i++) {
957	b_sft = BITS8 * (shift_byte % REG_BYTES);
958	vop = (shift_byte < REG_BYTES) ? &vop30 :
959	&vop74;
960	svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
961	shift_byte++;
962	}
963	} else if (bdata->type == SVSB_TYPE_LOW) {
964	/* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
965	j = bdata->opp_count - 7;
966	svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
967	shift_byte++;
968	for (i = j; i < bdata->opp_count; i++) {
969	b_sft = BITS8 * (shift_byte % REG_BYTES);
970	vop = (shift_byte < REG_BYTES) ? &vop30 :
971	&vop74;
972	svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
973	shift_byte++;
974	}
975
976	/* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */
977	for (i = turn_pt + 1; i < j; i++)
978	svsb->volt[i] = interpolate(f0: svsb->freq_pct[turn_pt],
979	f1: svsb->freq_pct[j],
980	v0: svsb->volt[turn_pt],
981	v1: svsb->volt[j],
982	fx: svsb->freq_pct[i]);
983	}
984	} else {
985	if (bdata->type == SVSB_TYPE_HIGH) {
986	/* volt[0] + volt[j] ~ volt[turn_pt - 1] */
987	j = turn_pt - 7;
988	svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
989	shift_byte++;
990	for (i = j; i < turn_pt; i++) {
991	b_sft = BITS8 * (shift_byte % REG_BYTES);
992	vop = (shift_byte < REG_BYTES) ? &vop30 :
993	&vop74;
994	svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
995	shift_byte++;
996	}
997
998	/* volt[1] ~ volt[j - 1] by interpolate */
999	for (i = 1; i < j; i++)
1000	svsb->volt[i] = interpolate(f0: svsb->freq_pct[0],
1001	f1: svsb->freq_pct[j],
1002	v0: svsb->volt[0],
1003	v1: svsb->volt[j],
1004	fx: svsb->freq_pct[i]);
1005	} else if (bdata->type == SVSB_TYPE_LOW) {
1006	/* volt[turn_pt] ~ volt[opp_count - 1] */
1007	for (i = turn_pt; i < bdata->opp_count; i++) {
1008	b_sft = BITS8 * (shift_byte % REG_BYTES);
1009	vop = (shift_byte < REG_BYTES) ? &vop30 :
1010	&vop74;
1011	svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
1012	shift_byte++;
1013	}
1014	}
1015	}
1016
1017	if (bdata->type == SVSB_TYPE_HIGH) {
1018	opp_start = 0;
1019	opp_stop = svsb->turn_pt;
1020	} else if (bdata->type == SVSB_TYPE_LOW) {
1021	opp_start = svsb->turn_pt;
1022	opp_stop = bdata->opp_count;
1023	}
1024
1025	for (i = opp_start; i < opp_stop; i++)
1026	if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
1027	svsb->volt[i] -= svsb->dvt_fixed;
1028
1029	/* For voltage bin support */
1030	if (svsb->opp_dfreq[0] > svsb->freq_base) {
1031	svsb->volt[0] = svs_opp_volt_to_bank_volt(opp_u_volt: svsb->opp_dvolt[0],
1032	svsb_volt_step: bdata->volt_step,
1033	svsb_volt_base: bdata->volt_base);
1034
1035	/* Find voltage bin turn point */
1036	for (i = 0; i < bdata->opp_count; i++) {
1037	if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1038	svsb->vbin_turn_pt = i;
1039	break;
1040	}
1041	}
1042
1043	/* Override svs bank voltages */
1044	for (i = 1; i < svsb->vbin_turn_pt; i++)
1045	svsb->volt[i] = interpolate(f0: svsb->freq_pct[0],
1046	f1: svsb->freq_pct[svsb->vbin_turn_pt],
1047	v0: svsb->volt[0],
1048	v1: svsb->volt[svsb->vbin_turn_pt],
1049	fx: svsb->freq_pct[i]);
1050	}
1051	}
1052
1053	static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb)
1054	{
1055	const struct svs_bank_pdata *bdata = &svsb->pdata;
1056	u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0;
1057	u32 b_sft, shift_byte = 0, turn_pt;
1058	u32 middle_index = (bdata->opp_count / 2);
1059
1060	for (i = 0; i < bdata->opp_count; i++) {
1061	if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) {
1062	svsb->turn_pt = i;
1063	break;
1064	}
1065	}
1066
1067	turn_pt = svsb->turn_pt;
1068
1069	/* Target is to fill out freq_pct74 / freq_pct30 by algorithm */
1070	if (turn_pt < middle_index) {
1071	if (bdata->type == SVSB_TYPE_HIGH) {
1072	/*
1073	* If we don't handle this situation,
1074	* SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0"
1075	* and this leads SVSB_TYPE_LOW to work abnormally.
1076	*/
1077	if (turn_pt == 0)
1078	freq_pct30 = svsb->freq_pct[0];
1079
1080	/* freq_pct[0] ~ freq_pct[turn_pt - 1] */
1081	for (i = 0; i < turn_pt; i++) {
1082	b_sft = BITS8 * (shift_byte % REG_BYTES);
1083	freq_pct = (shift_byte < REG_BYTES) ?
1084	&freq_pct30 : &freq_pct74;
1085	*freq_pct |= (svsb->freq_pct[i] << b_sft);
1086	shift_byte++;
1087	}
1088	} else if (bdata->type == SVSB_TYPE_LOW) {
1089	/*
1090	* freq_pct[turn_pt] +
1091	* freq_pct[opp_count - 7] ~ freq_pct[opp_count -1]
1092	*/
1093	freq_pct30 = svsb->freq_pct[turn_pt];
1094	shift_byte++;
1095	j = bdata->opp_count - 7;
1096	for (i = j; i < bdata->opp_count; i++) {
1097	b_sft = BITS8 * (shift_byte % REG_BYTES);
1098	freq_pct = (shift_byte < REG_BYTES) ?
1099	&freq_pct30 : &freq_pct74;
1100	*freq_pct |= (svsb->freq_pct[i] << b_sft);
1101	shift_byte++;
1102	}
1103	}
1104	} else {
1105	if (bdata->type == SVSB_TYPE_HIGH) {
1106	/*
1107	* freq_pct[0] +
1108	* freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1]
1109	*/
1110	freq_pct30 = svsb->freq_pct[0];
1111	shift_byte++;
1112	j = turn_pt - 7;
1113	for (i = j; i < turn_pt; i++) {
1114	b_sft = BITS8 * (shift_byte % REG_BYTES);
1115	freq_pct = (shift_byte < REG_BYTES) ?
1116	&freq_pct30 : &freq_pct74;
1117	*freq_pct |= (svsb->freq_pct[i] << b_sft);
1118	shift_byte++;
1119	}
1120	} else if (bdata->type == SVSB_TYPE_LOW) {
1121	/* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */
1122	for (i = turn_pt; i < bdata->opp_count; i++) {
1123	b_sft = BITS8 * (shift_byte % REG_BYTES);
1124	freq_pct = (shift_byte < REG_BYTES) ?
1125	&freq_pct30 : &freq_pct74;
1126	*freq_pct |= (svsb->freq_pct[i] << b_sft);
1127	shift_byte++;
1128	}
1129	}
1130	}
1131
1132	svs_writel_relaxed(svsp, val: freq_pct74, rg_i: FREQPCT74);
1133	svs_writel_relaxed(svsp, val: freq_pct30, rg_i: FREQPCT30);
1134	}
1135
1136	static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1137	{
1138	const struct svs_bank_pdata *bdata = &svsb->pdata;
1139	u32 temp, i;
1140
1141	temp = svs_readl_relaxed(svsp, rg_i: VOP74);
1142	svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1143	svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1144	svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1145	svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1146
1147	temp = svs_readl_relaxed(svsp, rg_i: VOP30);
1148	svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1149	svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1150	svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1151	svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1152
1153	for (i = 0; i <= 12; i += 2)
1154	svsb->volt[i + 1] = interpolate(f0: svsb->freq_pct[i],
1155	f1: svsb->freq_pct[i + 2],
1156	v0: svsb->volt[i],
1157	v1: svsb->volt[i + 2],
1158	fx: svsb->freq_pct[i + 1]);
1159
1160	svsb->volt[15] = interpolate(f0: svsb->freq_pct[12],
1161	f1: svsb->freq_pct[14],
1162	v0: svsb->volt[12],
1163	v1: svsb->volt[14],
1164	fx: svsb->freq_pct[15]);
1165
1166	for (i = 0; i < bdata->opp_count; i++)
1167	svsb->volt[i] += svsb->volt_od;
1168
1169	/* For voltage bin support */
1170	if (svsb->opp_dfreq[0] > svsb->freq_base) {
1171	svsb->volt[0] = svs_opp_volt_to_bank_volt(opp_u_volt: svsb->opp_dvolt[0],
1172	svsb_volt_step: bdata->volt_step,
1173	svsb_volt_base: bdata->volt_base);
1174
1175	/* Find voltage bin turn point */
1176	for (i = 0; i < bdata->opp_count; i++) {
1177	if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1178	svsb->vbin_turn_pt = i;
1179	break;
1180	}
1181	}
1182
1183	/* Override svs bank voltages */
1184	for (i = 1; i < svsb->vbin_turn_pt; i++)
1185	svsb->volt[i] = interpolate(f0: svsb->freq_pct[0],
1186	f1: svsb->freq_pct[svsb->vbin_turn_pt],
1187	v0: svsb->volt[0],
1188	v1: svsb->volt[svsb->vbin_turn_pt],
1189	fx: svsb->freq_pct[i]);
1190	}
1191	}
1192
1193	static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1194	{
1195	u32 freqpct74_val, freqpct30_val;
1196
1197	freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
1198	FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
1199	FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
1200	FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
1201
1202	freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
1203	FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
1204	FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
1205	FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
1206
1207	svs_writel_relaxed(svsp, val: freqpct74_val, rg_i: FREQPCT74);
1208	svs_writel_relaxed(svsp, val: freqpct30_val, rg_i: FREQPCT30);
1209	}
1210
1211	static void svs_set_bank_phase(struct svs_platform *svsp,
1212	unsigned int bank_idx,
1213	enum svsb_phase target_phase)
1214	{
1215	struct svs_bank *svsb = &svsp->banks[bank_idx];
1216	const struct svs_bank_pdata *bdata = &svsb->pdata;
1217	u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs;
1218
1219	svs_switch_bank(svsp, svsb);
1220
1221	des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
1222	FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
1223	svs_writel_relaxed(svsp, val: des_char, rg_i: DESCHAR);
1224
1225	temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) |
1226	FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
1227	FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
1228	svs_writel_relaxed(svsp, val: temp_char, rg_i: TEMPCHAR);
1229
1230	det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
1231	FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
1232	svs_writel_relaxed(svsp, val: det_char, rg_i: DETCHAR);
1233
1234	svs_writel_relaxed(svsp, val: bdata->dc_config, rg_i: DCCONFIG);
1235	svs_writel_relaxed(svsp, val: bdata->age_config, rg_i: AGECONFIG);
1236	svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, rg_i: RUNCONFIG);
1237
1238	bdata->set_freq_pct(svsp, svsb);
1239
1240	limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) |
1241	FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) |
1242	FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
1243	FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
1244	svs_writel_relaxed(svsp, val: limit_vals, rg_i: LIMITVALS);
1245
1246	svs_writel_relaxed(svsp, SVSB_DET_WINDOW, rg_i: DETWINDOW);
1247	svs_writel_relaxed(svsp, SVSB_DET_MAX, rg_i: CONFIG);
1248	svs_writel_relaxed(svsp, val: bdata->chk_shift, rg_i: CHKSHIFT);
1249	svs_writel_relaxed(svsp, val: bdata->ctl0, rg_i: CTL0);
1250	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, rg_i: INTSTS);
1251
1252	switch (target_phase) {
1253	case SVSB_PHASE_INIT01:
1254	svs_writel_relaxed(svsp, val: bdata->vboot, rg_i: VBOOT);
1255	svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, rg_i: INTEN);
1256	svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, rg_i: SVSEN);
1257	break;
1258	case SVSB_PHASE_INIT02:
1259	init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
1260	FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
1261	svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, rg_i: INTEN);
1262	svs_writel_relaxed(svsp, val: init2vals, rg_i: INIT2VALS);
1263	svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, rg_i: SVSEN);
1264	break;
1265	case SVSB_PHASE_MON:
1266	ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
1267	FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
1268	svs_writel_relaxed(svsp, val: ts_calcs, rg_i: TSCALCS);
1269	svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, rg_i: INTEN);
1270	svs_writel_relaxed(svsp, SVSB_PTPEN_MON, rg_i: SVSEN);
1271	break;
1272	default:
1273	dev_err(svsb->dev, "requested unknown target phase: %u\n",
1274	target_phase);
1275	break;
1276	}
1277	}
1278
1279	static inline void svs_save_bank_register_data(struct svs_platform *svsp,
1280	unsigned short bank_idx,
1281	enum svsb_phase phase)
1282	{
1283	struct svs_bank *svsb = &svsp->banks[bank_idx];
1284	enum svs_reg_index rg_i;
1285
1286	for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++)
1287	svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1288	}
1289
1290	static inline void svs_error_isr_handler(struct svs_platform *svsp,
1291	unsigned short bank_idx)
1292	{
1293	struct svs_bank *svsb = &svsp->banks[bank_idx];
1294
1295	dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n",
1296	__func__, svs_readl_relaxed(svsp, CORESEL));
1297	dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n",
1298	svs_readl_relaxed(svsp, SVSEN),
1299	svs_readl_relaxed(svsp, INTSTS));
1300	dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
1301	svs_readl_relaxed(svsp, SMSTATE0),
1302	svs_readl_relaxed(svsp, SMSTATE1));
1303	dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1304
1305	svs_save_bank_register_data(svsp, bank_idx, phase: SVSB_PHASE_ERROR);
1306
1307	svsb->phase = SVSB_PHASE_ERROR;
1308	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, rg_i: SVSEN);
1309	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, rg_i: INTSTS);
1310	}
1311
1312	static inline void svs_init01_isr_handler(struct svs_platform *svsp,
1313	unsigned short bank_idx)
1314	{
1315	struct svs_bank *svsb = &svsp->banks[bank_idx];
1316	u32 val;
1317
1318	dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n",
1319	__func__, svs_readl_relaxed(svsp, VDESIGN74),
1320	svs_readl_relaxed(svsp, VDESIGN30),
1321	svs_readl_relaxed(svsp, DCVALUES));
1322
1323	svs_save_bank_register_data(svsp, bank_idx, phase: SVSB_PHASE_INIT01);
1324
1325	svsb->phase = SVSB_PHASE_INIT01;
1326	val = ~(svs_readl_relaxed(svsp, rg_i: DCVALUES) & GENMASK(15, 0)) + 1;
1327	svsb->dc_voffset_in = val & GENMASK(15, 0);
1328	if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE ||
1329	(svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT &&
1330	svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY))
1331	svsb->dc_voffset_in = 0;
1332
1333	svsb->age_voffset_in = svs_readl_relaxed(svsp, rg_i: AGEVALUES) &
1334	GENMASK(15, 0);
1335
1336	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, rg_i: SVSEN);
1337	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, rg_i: INTSTS);
1338	svsb->core_sel &= ~SVSB_DET_CLK_EN;
1339	}
1340
1341	static inline void svs_init02_isr_handler(struct svs_platform *svsp,
1342	unsigned short bank_idx)
1343	{
1344	struct svs_bank *svsb = &svsp->banks[bank_idx];
1345	const struct svs_bank_pdata *bdata = &svsb->pdata;
1346
1347	dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n",
1348	__func__, svs_readl_relaxed(svsp, VOP74),
1349	svs_readl_relaxed(svsp, VOP30),
1350	svs_readl_relaxed(svsp, DCVALUES));
1351
1352	svs_save_bank_register_data(svsp, bank_idx, phase: SVSB_PHASE_INIT02);
1353
1354	svsb->phase = SVSB_PHASE_INIT02;
1355	bdata->get_volts(svsp, svsb);
1356
1357	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, rg_i: SVSEN);
1358	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, rg_i: INTSTS);
1359	}
1360
1361	static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp,
1362	unsigned short bank_idx)
1363	{
1364	struct svs_bank *svsb = &svsp->banks[bank_idx];
1365	const struct svs_bank_pdata *bdata = &svsb->pdata;
1366
1367	svs_save_bank_register_data(svsp, bank_idx, phase: SVSB_PHASE_MON);
1368
1369	svsb->phase = SVSB_PHASE_MON;
1370	bdata->get_volts(svsp, svsb);
1371
1372	svsb->temp = svs_readl_relaxed(svsp, rg_i: TEMP) & GENMASK(7, 0);
1373	svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, rg_i: INTSTS);
1374	}
1375
1376	static irqreturn_t svs_isr(int irq, void *data)
1377	{
1378	struct svs_platform *svsp = data;
1379	const struct svs_bank_pdata *bdata;
1380	struct svs_bank *svsb = NULL;
1381	unsigned long flags;
1382	u32 idx, int_sts, svs_en;
1383
1384	for (idx = 0; idx < svsp->bank_max; idx++) {
1385	svsb = &svsp->banks[idx];
1386	bdata = &svsb->pdata;
1387	WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name);
1388
1389	spin_lock_irqsave(&svs_lock, flags);
1390
1391	/* Find out which svs bank fires interrupt */
1392	if (bdata->int_st & svs_readl_relaxed(svsp, rg_i: INTST)) {
1393	spin_unlock_irqrestore(lock: &svs_lock, flags);
1394	continue;
1395	}
1396
1397	svs_switch_bank(svsp, svsb);
1398	int_sts = svs_readl_relaxed(svsp, rg_i: INTSTS);
1399	svs_en = svs_readl_relaxed(svsp, rg_i: SVSEN);
1400
1401	if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1402	svs_en == SVSB_PTPEN_INIT01)
1403	svs_init01_isr_handler(svsp, bank_idx: idx);
1404	else if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1405	svs_en == SVSB_PTPEN_INIT02)
1406	svs_init02_isr_handler(svsp, bank_idx: idx);
1407	else if (int_sts & SVSB_INTSTS_FLD_MONVOP)
1408	svs_mon_mode_isr_handler(svsp, bank_idx: idx);
1409	else
1410	svs_error_isr_handler(svsp, bank_idx: idx);
1411
1412	spin_unlock_irqrestore(lock: &svs_lock, flags);
1413	break;
1414	}
1415
1416	svs_adjust_pm_opp_volts(svsb);
1417
1418	if (svsb->phase == SVSB_PHASE_INIT01 ||
1419	svsb->phase == SVSB_PHASE_INIT02)
1420	complete(&svsb->init_completion);
1421
1422	return IRQ_HANDLED;
1423	}
1424
1425	static bool svs_mode_available(struct svs_platform *svsp, u8 mode)
1426	{
1427	int i;
1428
1429	for (i = 0; i < svsp->bank_max; i++)
1430	if (svsp->banks[i].mode_support & mode)
1431	return true;
1432	return false;
1433	}
1434
1435	static int svs_init01(struct svs_platform *svsp)
1436	{
1437	const struct svs_bank_pdata *bdata;
1438	struct svs_bank *svsb;
1439	unsigned long flags, time_left;
1440	bool search_done;
1441	int ret = 0, r;
1442	u32 opp_freq, opp_vboot, buck_volt, idx, i;
1443
1444	if (!svs_mode_available(svsp, SVSB_MODE_INIT01))
1445	return 0;
1446
1447	/* Keep CPUs' core power on for svs_init01 initialization */
1448	cpuidle_pause_and_lock();
1449
1450	/* Svs bank init01 preparation - power enable */
1451	for (idx = 0; idx < svsp->bank_max; idx++) {
1452	svsb = &svsp->banks[idx];
1453	bdata = &svsb->pdata;
1454
1455	if (!(svsb->mode_support & SVSB_MODE_INIT01))
1456	continue;
1457
1458	ret = regulator_enable(regulator: svsb->buck);
1459	if (ret) {
1460	dev_err(svsb->dev, "%s enable fail: %d\n",
1461	bdata->buck_name, ret);
1462	goto svs_init01_resume_cpuidle;
1463	}
1464
1465	/* Some buck doesn't support mode change. Show fail msg only */
1466	ret = regulator_set_mode(regulator: svsb->buck, REGULATOR_MODE_FAST);
1467	if (ret)
1468	dev_notice(svsb->dev, "set fast mode fail: %d\n", ret);
1469
1470	if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1471	if (!pm_runtime_enabled(dev: svsb->opp_dev)) {
1472	pm_runtime_enable(dev: svsb->opp_dev);
1473	svsb->pm_runtime_enabled_count++;
1474	}
1475
1476	ret = pm_runtime_resume_and_get(dev: svsb->opp_dev);
1477	if (ret < 0) {
1478	dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
1479	goto svs_init01_resume_cpuidle;
1480	}
1481	}
1482	}
1483
1484	/*
1485	* Svs bank init01 preparation - vboot voltage adjustment
1486	* Sometimes two svs banks use the same buck. Therefore,
1487	* we have to set each svs bank to target voltage(vboot) first.
1488	*/
1489	for (idx = 0; idx < svsp->bank_max; idx++) {
1490	svsb = &svsp->banks[idx];
1491	bdata = &svsb->pdata;
1492
1493	if (!(svsb->mode_support & SVSB_MODE_INIT01))
1494	continue;
1495
1496	/*
1497	* Find the fastest freq that can be run at vboot and
1498	* fix to that freq until svs_init01 is done.
1499	*/
1500	search_done = false;
1501	opp_vboot = svs_bank_volt_to_opp_volt(svsb_volt: bdata->vboot,
1502	svsb_volt_step: bdata->volt_step,
1503	svsb_volt_base: bdata->volt_base);
1504
1505	for (i = 0; i < bdata->opp_count; i++) {
1506	opp_freq = svsb->opp_dfreq[i];
1507	if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) {
1508	ret = dev_pm_opp_adjust_voltage(dev: svsb->opp_dev,
1509	freq: opp_freq,
1510	u_volt: opp_vboot,
1511	u_volt_min: opp_vboot,
1512	u_volt_max: opp_vboot);
1513	if (ret) {
1514	dev_err(svsb->dev,
1515	"set opp %uuV vboot fail: %d\n",
1516	opp_vboot, ret);
1517	goto svs_init01_finish;
1518	}
1519
1520	search_done = true;
1521	} else {
1522	ret = dev_pm_opp_disable(dev: svsb->opp_dev,
1523	freq: svsb->opp_dfreq[i]);
1524	if (ret) {
1525	dev_err(svsb->dev,
1526	"opp %uHz disable fail: %d\n",
1527	svsb->opp_dfreq[i], ret);
1528	goto svs_init01_finish;
1529	}
1530	}
1531	}
1532	}
1533
1534	/* Svs bank init01 begins */
1535	for (idx = 0; idx < svsp->bank_max; idx++) {
1536	svsb = &svsp->banks[idx];
1537	bdata = &svsb->pdata;
1538
1539	if (!(svsb->mode_support & SVSB_MODE_INIT01))
1540	continue;
1541
1542	opp_vboot = svs_bank_volt_to_opp_volt(svsb_volt: bdata->vboot,
1543	svsb_volt_step: bdata->volt_step,
1544	svsb_volt_base: bdata->volt_base);
1545
1546	buck_volt = regulator_get_voltage(regulator: svsb->buck);
1547	if (buck_volt != opp_vboot) {
1548	dev_err(svsb->dev,
1549	"buck voltage: %uuV, expected vboot: %uuV\n",
1550	buck_volt, opp_vboot);
1551	ret = -EPERM;
1552	goto svs_init01_finish;
1553	}
1554
1555	spin_lock_irqsave(&svs_lock, flags);
1556	svs_set_bank_phase(svsp, bank_idx: idx, target_phase: SVSB_PHASE_INIT01);
1557	spin_unlock_irqrestore(lock: &svs_lock, flags);
1558
1559	time_left = wait_for_completion_timeout(x: &svsb->init_completion,
1560	timeout: msecs_to_jiffies(m: 5000));
1561	if (!time_left) {
1562	dev_err(svsb->dev, "init01 completion timeout\n");
1563	ret = -EBUSY;
1564	goto svs_init01_finish;
1565	}
1566	}
1567
1568	svs_init01_finish:
1569	for (idx = 0; idx < svsp->bank_max; idx++) {
1570	svsb = &svsp->banks[idx];
1571	bdata = &svsb->pdata;
1572
1573	if (!(svsb->mode_support & SVSB_MODE_INIT01))
1574	continue;
1575
1576	for (i = 0; i < bdata->opp_count; i++) {
1577	r = dev_pm_opp_enable(dev: svsb->opp_dev,
1578	freq: svsb->opp_dfreq[i]);
1579	if (r)
1580	dev_err(svsb->dev, "opp %uHz enable fail: %d\n",
1581	svsb->opp_dfreq[i], r);
1582	}
1583
1584	if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1585	r = pm_runtime_put_sync(dev: svsb->opp_dev);
1586	if (r)
1587	dev_err(svsb->dev, "mtcmos off fail: %d\n", r);
1588
1589	if (svsb->pm_runtime_enabled_count > 0) {
1590	pm_runtime_disable(dev: svsb->opp_dev);
1591	svsb->pm_runtime_enabled_count--;
1592	}
1593	}
1594
1595	r = regulator_set_mode(regulator: svsb->buck, REGULATOR_MODE_NORMAL);
1596	if (r)
1597	dev_notice(svsb->dev, "set normal mode fail: %d\n", r);
1598
1599	r = regulator_disable(regulator: svsb->buck);
1600	if (r)
1601	dev_err(svsb->dev, "%s disable fail: %d\n",
1602	bdata->buck_name, r);
1603	}
1604
1605	svs_init01_resume_cpuidle:
1606	cpuidle_resume_and_unlock();
1607
1608	return ret;
1609	}
1610
1611	static int svs_init02(struct svs_platform *svsp)
1612	{
1613	const struct svs_bank_pdata *bdata;
1614	struct svs_bank *svsb;
1615	unsigned long flags, time_left;
1616	int ret;
1617	u32 idx;
1618
1619	if (!svs_mode_available(svsp, SVSB_MODE_INIT02))
1620	return 0;
1621
1622	for (idx = 0; idx < svsp->bank_max; idx++) {
1623	svsb = &svsp->banks[idx];
1624
1625	if (!(svsb->mode_support & SVSB_MODE_INIT02))
1626	continue;
1627
1628	reinit_completion(x: &svsb->init_completion);
1629	spin_lock_irqsave(&svs_lock, flags);
1630	svs_set_bank_phase(svsp, bank_idx: idx, target_phase: SVSB_PHASE_INIT02);
1631	spin_unlock_irqrestore(lock: &svs_lock, flags);
1632
1633	time_left = wait_for_completion_timeout(x: &svsb->init_completion,
1634	timeout: msecs_to_jiffies(m: 5000));
1635	if (!time_left) {
1636	dev_err(svsb->dev, "init02 completion timeout\n");
1637	ret = -EBUSY;
1638	goto out_of_init02;
1639	}
1640	}
1641
1642	/*
1643	* 2-line high/low bank update its corresponding opp voltages only.
1644	* Therefore, we sync voltages from opp for high/low bank voltages
1645	* consistency.
1646	*/
1647	for (idx = 0; idx < svsp->bank_max; idx++) {
1648	svsb = &svsp->banks[idx];
1649	bdata = &svsb->pdata;
1650
1651	if (!(svsb->mode_support & SVSB_MODE_INIT02))
1652	continue;
1653
1654	if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) {
1655	if (svs_sync_bank_volts_from_opp(svsb)) {
1656	dev_err(svsb->dev, "sync volt fail\n");
1657	ret = -EPERM;
1658	goto out_of_init02;
1659	}
1660	}
1661	}
1662
1663	return 0;
1664
1665	out_of_init02:
1666	for (idx = 0; idx < svsp->bank_max; idx++) {
1667	svsb = &svsp->banks[idx];
1668	svs_bank_disable_and_restore_default_volts(svsp, svsb);
1669	}
1670
1671	return ret;
1672	}
1673
1674	static void svs_mon_mode(struct svs_platform *svsp)
1675	{
1676	struct svs_bank *svsb;
1677	unsigned long flags;
1678	u32 idx;
1679
1680	for (idx = 0; idx < svsp->bank_max; idx++) {
1681	svsb = &svsp->banks[idx];
1682
1683	if (!(svsb->mode_support & SVSB_MODE_MON))
1684	continue;
1685
1686	spin_lock_irqsave(&svs_lock, flags);
1687	svs_set_bank_phase(svsp, bank_idx: idx, target_phase: SVSB_PHASE_MON);
1688	spin_unlock_irqrestore(lock: &svs_lock, flags);
1689	}
1690	}
1691
1692	static int svs_start(struct svs_platform *svsp)
1693	{
1694	int ret;
1695
1696	ret = svs_init01(svsp);
1697	if (ret)
1698	return ret;
1699
1700	ret = svs_init02(svsp);
1701	if (ret)
1702	return ret;
1703
1704	svs_mon_mode(svsp);
1705
1706	return 0;
1707	}
1708
1709	static int svs_suspend(struct device *dev)
1710	{
1711	struct svs_platform *svsp = dev_get_drvdata(dev);
1712	int ret;
1713	u32 idx;
1714
1715	for (idx = 0; idx < svsp->bank_max; idx++) {
1716	struct svs_bank *svsb = &svsp->banks[idx];
1717
1718	svs_bank_disable_and_restore_default_volts(svsp, svsb);
1719	}
1720
1721	ret = reset_control_assert(rstc: svsp->rst);
1722	if (ret) {
1723	dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1724	return ret;
1725	}
1726
1727	clk_disable_unprepare(clk: svsp->main_clk);
1728
1729	return 0;
1730	}
1731
1732	static int svs_resume(struct device *dev)
1733	{
1734	struct svs_platform *svsp = dev_get_drvdata(dev);
1735	int ret;
1736
1737	ret = clk_prepare_enable(clk: svsp->main_clk);
1738	if (ret) {
1739	dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1740	return ret;
1741	}
1742
1743	ret = reset_control_deassert(rstc: svsp->rst);
1744	if (ret) {
1745	dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1746	goto out_of_resume;
1747	}
1748
1749	ret = svs_init02(svsp);
1750	if (ret)
1751	goto svs_resume_reset_assert;
1752
1753	svs_mon_mode(svsp);
1754
1755	return 0;
1756
1757	svs_resume_reset_assert:
1758	dev_err(svsp->dev, "assert reset: %d\n",
1759	reset_control_assert(svsp->rst));
1760
1761	out_of_resume:
1762	clk_disable_unprepare(clk: svsp->main_clk);
1763	return ret;
1764	}
1765
1766	static int svs_bank_resource_setup(struct svs_platform *svsp)
1767	{
1768	const struct svs_bank_pdata *bdata;
1769	struct svs_bank *svsb;
1770	struct dev_pm_opp *opp;
1771	unsigned long freq;
1772	int count, ret;
1773	u32 idx, i;
1774
1775	dev_set_drvdata(dev: svsp->dev, data: svsp);
1776
1777	for (idx = 0; idx < svsp->bank_max; idx++) {
1778	svsb = &svsp->banks[idx];
1779	bdata = &svsb->pdata;
1780
1781	if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) {
1782	dev_err(svsb->dev, "unknown bank sw_id or type\n");
1783	return -EINVAL;
1784	}
1785
1786	svsb->dev = devm_kzalloc(dev: svsp->dev, size: sizeof(*svsb->dev), GFP_KERNEL);
1787	if (!svsb->dev)
1788	return -ENOMEM;
1789
1790	svsb->name = devm_kasprintf(dev: svsp->dev, GFP_KERNEL, fmt: "%s%s",
1791	svs_swid_names[bdata->sw_id],
1792	svs_type_names[bdata->type]);
1793	if (!svsb->name)
1794	return -ENOMEM;
1795
1796	ret = dev_set_name(dev: svsb->dev, name: "%s", svsb->name);
1797	if (ret)
1798	return ret;
1799
1800	dev_set_drvdata(dev: svsb->dev, data: svsp);
1801
1802	ret = devm_pm_opp_of_add_table(dev: svsb->opp_dev);
1803	if (ret) {
1804	dev_err(svsb->dev, "add opp table fail: %d\n", ret);
1805	return ret;
1806	}
1807
1808	mutex_init(&svsb->lock);
1809	init_completion(x: &svsb->init_completion);
1810
1811	if (svsb->mode_support & SVSB_MODE_INIT01) {
1812	svsb->buck = devm_regulator_get_optional(dev: svsb->opp_dev,
1813	id: bdata->buck_name);
1814	if (IS_ERR(ptr: svsb->buck)) {
1815	dev_err(svsb->dev, "cannot get \"%s-supply\"\n",
1816	bdata->buck_name);
1817	return PTR_ERR(ptr: svsb->buck);
1818	}
1819	}
1820
1821	if (!IS_ERR_OR_NULL(ptr: bdata->tzone_name)) {
1822	svsb->tzd = thermal_zone_get_zone_by_name(name: bdata->tzone_name);
1823	if (IS_ERR(ptr: svsb->tzd)) {
1824	dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1825	bdata->tzone_name);
1826	return PTR_ERR(ptr: svsb->tzd);
1827	}
1828	}
1829
1830	count = dev_pm_opp_get_opp_count(dev: svsb->opp_dev);
1831	if (bdata->opp_count != count) {
1832	dev_err(svsb->dev,
1833	"opp_count not \"%u\" but get \"%d\"?\n",
1834	bdata->opp_count, count);
1835	return count;
1836	}
1837
1838	for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) {
1839	opp = dev_pm_opp_find_freq_floor(dev: svsb->opp_dev, freq: &freq);
1840	if (IS_ERR(ptr: opp)) {
1841	dev_err(svsb->dev, "cannot find freq = %ld\n",
1842	PTR_ERR(opp));
1843	return PTR_ERR(ptr: opp);
1844	}
1845
1846	svsb->opp_dfreq[i] = freq;
1847	svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp);
1848	svsb->freq_pct[i] = percent(numerator: svsb->opp_dfreq[i],
1849	denominator: svsb->freq_base);
1850	dev_pm_opp_put(opp);
1851	}
1852	}
1853
1854	return 0;
1855	}
1856
1857	static int svs_get_efuse_data(struct svs_platform *svsp,
1858	const char *nvmem_cell_name,
1859	u32 **svsp_efuse, size_t *svsp_efuse_max)
1860	{
1861	struct nvmem_cell *cell;
1862
1863	cell = nvmem_cell_get(dev: svsp->dev, id: nvmem_cell_name);
1864	if (IS_ERR(ptr: cell)) {
1865	dev_err(svsp->dev, "no \"%s\"? %ld\n",
1866	nvmem_cell_name, PTR_ERR(cell));
1867	return PTR_ERR(ptr: cell);
1868	}
1869
1870	*svsp_efuse = nvmem_cell_read(cell, len: svsp_efuse_max);
1871	if (IS_ERR(ptr: *svsp_efuse)) {
1872	nvmem_cell_put(cell);
1873	return PTR_ERR(ptr: *svsp_efuse);
1874	}
1875
1876	*svsp_efuse_max /= sizeof(u32);
1877	nvmem_cell_put(cell);
1878
1879	return 0;
1880	}
1881
1882	static u32 svs_get_fuse_val(u32 *fuse_array, const struct svs_fusemap *fmap, u8 nbits)
1883	{
1884	u32 val;
1885
1886	if (fmap->index < 0)
1887	return FUSE_DATA_NOT_VALID;
1888
1889	val = fuse_array[fmap->index] >> fmap->ofst;
1890	val &= GENMASK(nbits - 1, 0);
1891
1892	return val;
1893	}
1894
1895	static bool svs_is_available(struct svs_platform *svsp)
1896	{
1897	int i, num_populated = 0;
1898
1899	/* If at least two fuse arrays are populated, SVS is calibrated */
1900	for (i = 0; i < svsp->efuse_max; i++) {
1901	if (svsp->efuse[i])
1902	num_populated++;
1903
1904	if (num_populated > 1)
1905	return true;
1906	}
1907
1908	return false;
1909	}
1910
1911	static bool svs_common_parse_efuse(struct svs_platform *svsp,
1912	const struct svs_platform_data *pdata)
1913	{
1914	const struct svs_fusemap *gfmap = pdata->glb_fuse_map;
1915	struct svs_fusemap tfm = { 0, 24 };
1916	u32 golden_temp, val;
1917	u8 ft_pgm, vmin;
1918	int i;
1919
1920	if (!svs_is_available(svsp))
1921	return false;
1922
1923	/* Get golden temperature from SVS-Thermal calibration */
1924	val = svs_get_fuse_val(fuse_array: svsp->tefuse, fmap: &tfm, nbits: 8);
1925
1926	/* If golden temp is not programmed, use the default of 50 */
1927	golden_temp = val ? val : 50;
1928
1929	/* Parse fused SVS calibration */
1930	ft_pgm = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &gfmap[GLB_FT_PGM], nbits: 8);
1931	vmin = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &gfmap[GLB_VMIN], nbits: 2);
1932
1933	for (i = 0; i < svsp->bank_max; i++) {
1934	struct svs_bank *svsb = &svsp->banks[i];
1935	const struct svs_bank_pdata *bdata = &svsb->pdata;
1936	const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1937
1938	if (vmin == 1)
1939	svsb->vmin = 0x1e;
1940
1941	if (ft_pgm == 0)
1942	svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1943
1944	svsb->mtdes = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_MTDES], nbits: 8);
1945	svsb->bdes = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_BDES], nbits: 8);
1946	svsb->mdes = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_MDES], nbits: 8);
1947	svsb->dcbdet = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_DCBDET], nbits: 8);
1948	svsb->dcmdet = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_DCMDET], nbits: 8);
1949	svsb->vmax += svsb->dvt_fixed;
1950
1951	svsb->mts = (svsp->ts_coeff * 2) / 1000;
1952	svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4;
1953	}
1954
1955	return true;
1956	}
1957
1958	static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp,
1959	const struct svs_platform_data *pdata)
1960	{
1961	struct svs_bank *svsb;
1962	const struct svs_bank_pdata *bdata;
1963	int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0;
1964	int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t;
1965	int o_slope, o_slope_sign, ts_id;
1966	u32 idx, i, ft_pgm, mts, temp0, temp1, temp2;
1967
1968	for (i = 0; i < svsp->efuse_max; i++)
1969	if (svsp->efuse[i])
1970	dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1971	i, svsp->efuse[i]);
1972
1973	if (!svsp->efuse[2]) {
1974	dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1975	return false;
1976	}
1977
1978	/* Svs efuse parsing */
1979	ft_pgm = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &pdata->glb_fuse_map[GLB_FT_PGM], nbits: 4);
1980
1981	for (idx = 0; idx < svsp->bank_max; idx++) {
1982	svsb = &svsp->banks[idx];
1983	bdata = &svsb->pdata;
1984	const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1985
1986	if (ft_pgm <= 1)
1987	svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1988
1989	svsb->mtdes = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_MTDES], nbits: 8);
1990	svsb->bdes = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_BDES], nbits: 8);
1991	svsb->mdes = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_MDES], nbits: 8);
1992	svsb->dcbdet = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_DCBDET], nbits: 8);
1993	svsb->dcmdet = svs_get_fuse_val(fuse_array: svsp->efuse, fmap: &dfmap[BDEV_DCMDET], nbits: 8);
1994
1995	switch (bdata->sw_id) {
1996	case SVSB_SWID_CPU_LITTLE:
1997	case SVSB_SWID_CCI:
1998	if (ft_pgm <= 3)
1999	svsb->volt_od += 10;
2000	else
2001	svsb->volt_od += 2;
2002	break;
2003	case SVSB_SWID_CPU_BIG:
2004	if (ft_pgm <= 3)
2005	svsb->volt_od += 15;
2006	else
2007	svsb->volt_od += 12;
2008	break;
2009	case SVSB_SWID_GPU:
2010	if (ft_pgm != FUSE_DATA_NOT_VALID && ft_pgm >= 2) {
2011	svsb->freq_base = 800000000; /* 800MHz */
2012	svsb->dvt_fixed = 2;
2013	}
2014	break;
2015	default:
2016	dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2017	return false;
2018	}
2019	}
2020
2021	/* Thermal efuse parsing */
2022	adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
2023	adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
2024
2025	o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
2026	o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
2027	o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
2028	o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
2029	o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
2030	o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
2031
2032	degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
2033	adc_cali_en_t = svsp->tefuse[0] & BIT(0);
2034	o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
2035
2036	ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
2037	if (!ts_id) {
2038	o_slope = 1534;
2039	} else {
2040	o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
2041	if (!o_slope_sign)
2042	o_slope = 1534 + o_slope * 10;
2043	else
2044	o_slope = 1534 - o_slope * 10;
2045	}
2046
2047	if (adc_cali_en_t == 0 ||
2048	adc_ge_t < 265 || adc_ge_t > 758 ||
2049	adc_oe_t < 265 || adc_oe_t > 758 ||
2050	o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
2051	o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
2052	o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
2053	o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
2054	o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
2055	o_vtsabb < -8 || o_vtsabb > 484 ||
2056	degc_cali < 1 || degc_cali > 63) {
2057	dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
2058	goto remove_mt8183_svsb_mon_mode;
2059	}
2060
2061	ge = ((adc_ge_t - 512) * 10000) / 4096;
2062	oe = (adc_oe_t - 512);
2063	gain = (10000 + ge);
2064
2065	format[0] = (o_vtsmcu[0] + 3350 - oe);
2066	format[1] = (o_vtsmcu[1] + 3350 - oe);
2067	format[2] = (o_vtsmcu[2] + 3350 - oe);
2068	format[3] = (o_vtsmcu[3] + 3350 - oe);
2069	format[4] = (o_vtsmcu[4] + 3350 - oe);
2070	format[5] = (o_vtsabb + 3350 - oe);
2071
2072	for (i = 0; i < 6; i++)
2073	x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain;
2074
2075	temp0 = (10000 * 100000 / gain) * 15 / 18;
2076	mts = (temp0 * 10) / o_slope;
2077
2078	for (idx = 0; idx < svsp->bank_max; idx++) {
2079	svsb = &svsp->banks[idx];
2080	bdata = &svsb->pdata;
2081	svsb->mts = mts;
2082
2083	switch (bdata->sw_id) {
2084	case SVSB_SWID_CPU_LITTLE:
2085	tb_roomt = x_roomt[3];
2086	break;
2087	case SVSB_SWID_CPU_BIG:
2088	tb_roomt = x_roomt[4];
2089	break;
2090	case SVSB_SWID_CCI:
2091	tb_roomt = x_roomt[3];
2092	break;
2093	case SVSB_SWID_GPU:
2094	tb_roomt = x_roomt[1];
2095	break;
2096	default:
2097	dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2098	goto remove_mt8183_svsb_mon_mode;
2099	}
2100
2101	temp0 = (degc_cali * 10 / 2);
2102	temp1 = ((10000 * 100000 / 4096 / gain) *
2103	oe + tb_roomt * 10) * 15 / 18;
2104	temp2 = temp1 * 100 / o_slope;
2105
2106	svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
2107	}
2108
2109	return true;
2110
2111	remove_mt8183_svsb_mon_mode:
2112	for (idx = 0; idx < svsp->bank_max; idx++) {
2113	svsb = &svsp->banks[idx];
2114	svsb->mode_support &= ~SVSB_MODE_MON;
2115	}
2116
2117	return true;
2118	}
2119
2120	static struct device *svs_get_subsys_device(struct svs_platform *svsp,
2121	const char *node_name)
2122	{
2123	struct platform_device *pdev;
2124	struct device_node *np;
2125
2126	np = of_find_node_by_name(NULL, name: node_name);
2127	if (!np) {
2128	dev_err(svsp->dev, "cannot find %s node\n", node_name);
2129	return ERR_PTR(error: -ENODEV);
2130	}
2131
2132	pdev = of_find_device_by_node(np);
2133	if (!pdev) {
2134	of_node_put(node: np);
2135	dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2136	return ERR_PTR(error: -ENXIO);
2137	}
2138
2139	of_node_put(node: np);
2140
2141	return &pdev->dev;
2142	}
2143
2144	static struct device *svs_add_device_link(struct svs_platform *svsp,
2145	const char *node_name)
2146	{
2147	struct device *dev;
2148	struct device_link *sup_link;
2149
2150	dev = svs_get_subsys_device(svsp, node_name);
2151	if (IS_ERR(ptr: dev))
2152	return dev;
2153
2154	sup_link = device_link_add(consumer: svsp->dev, supplier: dev,
2155	DL_FLAG_AUTOREMOVE_CONSUMER);
2156	if (!sup_link) {
2157	dev_err(svsp->dev, "sup_link is NULL\n");
2158	return ERR_PTR(error: -EINVAL);
2159	}
2160
2161	if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
2162	return ERR_PTR(error: -EPROBE_DEFER);
2163
2164	return dev;
2165	}
2166
2167	static int svs_mt8192_platform_probe(struct svs_platform *svsp)
2168	{
2169	struct device *dev;
2170	u32 idx;
2171
2172	svsp->rst = devm_reset_control_get_optional(dev: svsp->dev, id: "svs_rst");
2173	if (IS_ERR(ptr: svsp->rst))
2174	return dev_err_probe(dev: svsp->dev, err: PTR_ERR(ptr: svsp->rst),
2175	fmt: "cannot get svs reset control\n");
2176
2177	dev = svs_add_device_link(svsp, node_name: "thermal-sensor");
2178	if (IS_ERR(ptr: dev))
2179	return dev_err_probe(dev: svsp->dev, err: PTR_ERR(ptr: dev),
2180	fmt: "failed to get lvts device\n");
2181
2182	for (idx = 0; idx < svsp->bank_max; idx++) {
2183	struct svs_bank *svsb = &svsp->banks[idx];
2184	const struct svs_bank_pdata *bdata = &svsb->pdata;
2185
2186	switch (bdata->sw_id) {
2187	case SVSB_SWID_CPU_LITTLE:
2188	case SVSB_SWID_CPU_BIG:
2189	svsb->opp_dev = get_cpu_device(cpu: bdata->cpu_id);
2190	break;
2191	case SVSB_SWID_CCI:
2192	svsb->opp_dev = svs_add_device_link(svsp, node_name: "cci");
2193	break;
2194	case SVSB_SWID_GPU:
2195	if (bdata->type == SVSB_TYPE_LOW)
2196	svsb->opp_dev = svs_get_subsys_device(svsp, node_name: "gpu");
2197	else
2198	svsb->opp_dev = svs_add_device_link(svsp, node_name: "gpu");
2199	break;
2200	default:
2201	dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2202	return -EINVAL;
2203	}
2204
2205	if (IS_ERR(ptr: svsb->opp_dev))
2206	return dev_err_probe(dev: svsp->dev, err: PTR_ERR(ptr: svsb->opp_dev),
2207	fmt: "failed to get OPP device for bank %d\n",
2208	idx);
2209	}
2210
2211	return 0;
2212	}
2213
2214	static int svs_mt8183_platform_probe(struct svs_platform *svsp)
2215	{
2216	struct device *dev;
2217	u32 idx;
2218
2219	dev = svs_add_device_link(svsp, node_name: "thermal-sensor");
2220	if (IS_ERR(ptr: dev))
2221	return dev_err_probe(dev: svsp->dev, err: PTR_ERR(ptr: dev),
2222	fmt: "failed to get thermal device\n");
2223
2224	for (idx = 0; idx < svsp->bank_max; idx++) {
2225	struct svs_bank *svsb = &svsp->banks[idx];
2226	const struct svs_bank_pdata *bdata = &svsb->pdata;
2227
2228	switch (bdata->sw_id) {
2229	case SVSB_SWID_CPU_LITTLE:
2230	case SVSB_SWID_CPU_BIG:
2231	svsb->opp_dev = get_cpu_device(cpu: bdata->cpu_id);
2232	break;
2233	case SVSB_SWID_CCI:
2234	svsb->opp_dev = svs_add_device_link(svsp, node_name: "cci");
2235	break;
2236	case SVSB_SWID_GPU:
2237	svsb->opp_dev = svs_add_device_link(svsp, node_name: "gpu");
2238	break;
2239	default:
2240	dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2241	return -EINVAL;
2242	}
2243
2244	if (IS_ERR(ptr: svsb->opp_dev))
2245	return dev_err_probe(dev: svsp->dev, err: PTR_ERR(ptr: svsb->opp_dev),
2246	fmt: "failed to get OPP device for bank %d\n",
2247	idx);
2248	}
2249
2250	return 0;
2251	}
2252
2253	static struct svs_bank svs_mt8195_banks[] = {
2254	{
2255	.pdata = (const struct svs_bank_pdata) {
2256	.sw_id = SVSB_SWID_GPU,
2257	.type = SVSB_TYPE_LOW,
2258	.set_freq_pct = svs_set_bank_freq_pct_v3,
2259	.get_volts = svs_get_bank_volts_v3,
2260	.opp_count = MAX_OPP_ENTRIES,
2261	.turn_freq_base = 640000000,
2262	.volt_step = 6250,
2263	.volt_base = 400000,
2264	.age_config = 0x555555,
2265	.dc_config = 0x1,
2266	.vco = 0x18,
2267	.chk_shift = 0x87,
2268	.int_st = BIT(0),
2269	.ctl0 = 0x00540003,
2270	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2271	{ 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 }
2272	}
2273	},
2274	.mode_support = SVSB_MODE_INIT02,
2275	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
2276	.freq_base = 640000000,
2277	.core_sel = 0x0fff0100,
2278	.dvt_fixed = 0x1,
2279	.vmax = 0x38,
2280	.vmin = 0x14,
2281	},
2282	{
2283	.pdata = (const struct svs_bank_pdata) {
2284	.sw_id = SVSB_SWID_GPU,
2285	.type = SVSB_TYPE_HIGH,
2286	.set_freq_pct = svs_set_bank_freq_pct_v3,
2287	.get_volts = svs_get_bank_volts_v3,
2288	.tzone_name = "gpu",
2289	.opp_count = MAX_OPP_ENTRIES,
2290	.turn_freq_base = 640000000,
2291	.volt_step = 6250,
2292	.volt_base = 400000,
2293	.age_config = 0x555555,
2294	.dc_config = 0x1,
2295	.vco = 0x18,
2296	.chk_shift = 0x87,
2297	.int_st = BIT(1),
2298	.ctl0 = 0x00540003,
2299	.tzone_htemp = 85000,
2300	.tzone_htemp_voffset = 0,
2301	.tzone_ltemp = 25000,
2302	.tzone_ltemp_voffset = 7,
2303	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2304	{ 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 }
2305	},
2306	},
2307	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2308	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2309	.freq_base = 880000000,
2310	.core_sel = 0x0fff0101,
2311	.dvt_fixed = 0x6,
2312	.vmax = 0x38,
2313	.vmin = 0x14,
2314	},
2315	};
2316
2317	static struct svs_bank svs_mt8192_banks[] = {
2318	{
2319	.pdata = (const struct svs_bank_pdata) {
2320	.sw_id = SVSB_SWID_GPU,
2321	.type = SVSB_TYPE_LOW,
2322	.set_freq_pct = svs_set_bank_freq_pct_v3,
2323	.get_volts = svs_get_bank_volts_v3,
2324	.tzone_name = "gpu",
2325	.opp_count = MAX_OPP_ENTRIES,
2326	.turn_freq_base = 688000000,
2327	.volt_step = 6250,
2328	.volt_base = 400000,
2329	.age_config = 0x555555,
2330	.dc_config = 0x1,
2331	.vco = 0x18,
2332	.chk_shift = 0x87,
2333	.int_st = BIT(0),
2334	.ctl0 = 0x00540003,
2335	.tzone_htemp = 85000,
2336	.tzone_htemp_voffset = 0,
2337	.tzone_ltemp = 25000,
2338	.tzone_ltemp_voffset = 7,
2339	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2340	{ 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 }
2341	}
2342	},
2343	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
2344	.mode_support = SVSB_MODE_INIT02,
2345	.freq_base = 688000000,
2346	.core_sel = 0x0fff0100,
2347	.dvt_fixed = 0x1,
2348	.vmax = 0x60,
2349	.vmin = 0x1a,
2350	},
2351	{
2352	.pdata = (const struct svs_bank_pdata) {
2353	.sw_id = SVSB_SWID_GPU,
2354	.type = SVSB_TYPE_HIGH,
2355	.set_freq_pct = svs_set_bank_freq_pct_v3,
2356	.get_volts = svs_get_bank_volts_v3,
2357	.tzone_name = "gpu",
2358	.opp_count = MAX_OPP_ENTRIES,
2359	.turn_freq_base = 688000000,
2360	.volt_step = 6250,
2361	.volt_base = 400000,
2362	.age_config = 0x555555,
2363	.dc_config = 0x1,
2364	.vco = 0x18,
2365	.chk_shift = 0x87,
2366	.int_st = BIT(1),
2367	.ctl0 = 0x00540003,
2368	.tzone_htemp = 85000,
2369	.tzone_htemp_voffset = 0,
2370	.tzone_ltemp = 25000,
2371	.tzone_ltemp_voffset = 7,
2372	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2373	{ 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 }
2374	}
2375	},
2376	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2377	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2378	.freq_base = 902000000,
2379	.core_sel = 0x0fff0101,
2380	.dvt_fixed = 0x6,
2381	.vmax = 0x60,
2382	.vmin = 0x1a,
2383	},
2384	};
2385
2386	static struct svs_bank svs_mt8188_banks[] = {
2387	{
2388	.pdata = (const struct svs_bank_pdata) {
2389	.sw_id = SVSB_SWID_GPU,
2390	.type = SVSB_TYPE_LOW,
2391	.set_freq_pct = svs_set_bank_freq_pct_v3,
2392	.get_volts = svs_get_bank_volts_v3,
2393	.opp_count = MAX_OPP_ENTRIES,
2394	.turn_freq_base = 640000000,
2395	.volt_step = 6250,
2396	.volt_base = 400000,
2397	.age_config = 0x555555,
2398	.dc_config = 0x555555,
2399	.vco = 0x10,
2400	.chk_shift = 0x87,
2401	.int_st = BIT(0),
2402	.ctl0 = 0x00100003,
2403	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2404	{ 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 }
2405	}
2406	},
2407	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
2408	.mode_support = SVSB_MODE_INIT02,
2409	.freq_base = 640000000,
2410	.core_sel = 0x0fff0000,
2411	.dvt_fixed = 0x1,
2412	.vmax = 0x38,
2413	.vmin = 0x1c,
2414	},
2415	{
2416	.pdata = (const struct svs_bank_pdata) {
2417	.sw_id = SVSB_SWID_GPU,
2418	.type = SVSB_TYPE_HIGH,
2419	.set_freq_pct = svs_set_bank_freq_pct_v3,
2420	.get_volts = svs_get_bank_volts_v3,
2421	.tzone_name = "gpu",
2422	.opp_count = MAX_OPP_ENTRIES,
2423	.turn_freq_base = 640000000,
2424	.volt_step = 6250,
2425	.volt_base = 400000,
2426	.age_config = 0x555555,
2427	.dc_config = 0x555555,
2428	.vco = 0x10,
2429	.chk_shift = 0x87,
2430	.int_st = BIT(1),
2431	.ctl0 = 0x00100003,
2432	.tzone_htemp = 85000,
2433	.tzone_htemp_voffset = 0,
2434	.tzone_ltemp = 25000,
2435	.tzone_ltemp_voffset = 7,
2436	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2437	{ 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 }
2438	}
2439	},
2440	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2441	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2442	.freq_base = 880000000,
2443	.core_sel = 0x0fff0001,
2444	.dvt_fixed = 0x4,
2445	.vmax = 0x38,
2446	.vmin = 0x1c,
2447	},
2448	};
2449
2450	static struct svs_bank svs_mt8186_banks[] = {
2451	{
2452	.pdata = (const struct svs_bank_pdata) {
2453	.sw_id = SVSB_SWID_CPU_BIG,
2454	.type = SVSB_TYPE_LOW,
2455	.set_freq_pct = svs_set_bank_freq_pct_v3,
2456	.get_volts = svs_get_bank_volts_v3,
2457	.cpu_id = 6,
2458	.opp_count = MAX_OPP_ENTRIES,
2459	.turn_freq_base = 1670000000,
2460	.volt_step = 6250,
2461	.volt_base = 400000,
2462	.age_config = 0x1,
2463	.dc_config = 0x1,
2464	.vco = 0x10,
2465	.chk_shift = 0x87,
2466	.int_st = BIT(0),
2467	.ctl0 = 0x00540003,
2468	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2469	{ 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 }
2470	}
2471	},
2472	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
2473	.volt_od = 4,
2474	.mode_support = SVSB_MODE_INIT02,
2475	.freq_base = 1670000000,
2476	.core_sel = 0x0fff0100,
2477	.dvt_fixed = 0x3,
2478	.vmax = 0x59,
2479	.vmin = 0x20,
2480	},
2481	{
2482	.pdata = (const struct svs_bank_pdata) {
2483	.sw_id = SVSB_SWID_CPU_BIG,
2484	.type = SVSB_TYPE_HIGH,
2485	.set_freq_pct = svs_set_bank_freq_pct_v3,
2486	.get_volts = svs_get_bank_volts_v3,
2487	.cpu_id = 6,
2488	.tzone_name = "cpu-big",
2489	.opp_count = MAX_OPP_ENTRIES,
2490	.turn_freq_base = 1670000000,
2491	.volt_step = 6250,
2492	.volt_base = 400000,
2493	.age_config = 0x1,
2494	.dc_config = 0x1,
2495	.vco = 0x10,
2496	.chk_shift = 0x87,
2497	.int_st = BIT(1),
2498	.ctl0 = 0x00540003,
2499	.tzone_htemp = 85000,
2500	.tzone_htemp_voffset = 8,
2501	.tzone_ltemp = 25000,
2502	.tzone_ltemp_voffset = 8,
2503	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2504	{ 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 }
2505	}
2506	},
2507	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2508	.volt_od = 4,
2509	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2510	.freq_base = 2050000000,
2511	.core_sel = 0x0fff0101,
2512	.dvt_fixed = 0x6,
2513	.vmax = 0x73,
2514	.vmin = 0x20,
2515	},
2516	{
2517	.pdata = (const struct svs_bank_pdata) {
2518	.sw_id = SVSB_SWID_CPU_LITTLE,
2519	.set_freq_pct = svs_set_bank_freq_pct_v2,
2520	.get_volts = svs_get_bank_volts_v2,
2521	.cpu_id = 0,
2522	.tzone_name = "cpu-little",
2523	.opp_count = MAX_OPP_ENTRIES,
2524	.volt_step = 6250,
2525	.volt_base = 400000,
2526	.age_config = 0x1,
2527	.dc_config = 0x1,
2528	.vco = 0x10,
2529	.chk_shift = 0x87,
2530	.int_st = BIT(2),
2531	.ctl0 = 0x3210000f,
2532	.tzone_htemp = 85000,
2533	.tzone_htemp_voffset = 8,
2534	.tzone_ltemp = 25000,
2535	.tzone_ltemp_voffset = 8,
2536	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2537	{ 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 }
2538	}
2539	},
2540	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2541	.volt_od = 3,
2542	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2543	.freq_base = 2000000000,
2544	.core_sel = 0x0fff0102,
2545	.dvt_fixed = 0x6,
2546	.vmax = 0x65,
2547	.vmin = 0x20,
2548	},
2549	{
2550	.pdata = (const struct svs_bank_pdata) {
2551	.sw_id = SVSB_SWID_CCI,
2552	.set_freq_pct = svs_set_bank_freq_pct_v2,
2553	.get_volts = svs_get_bank_volts_v2,
2554	.tzone_name = "cci",
2555	.opp_count = MAX_OPP_ENTRIES,
2556	.volt_step = 6250,
2557	.volt_base = 400000,
2558	.age_config = 0x1,
2559	.dc_config = 0x1,
2560	.vco = 0x10,
2561	.chk_shift = 0x87,
2562	.int_st = BIT(3),
2563	.ctl0 = 0x3210000f,
2564	.tzone_htemp = 85000,
2565	.tzone_htemp_voffset = 8,
2566	.tzone_ltemp = 25000,
2567	.tzone_ltemp_voffset = 8,
2568	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2569	{ 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 }
2570	}
2571	},
2572	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2573	.volt_od = 3,
2574	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2575	.freq_base = 1400000000,
2576	.core_sel = 0x0fff0103,
2577	.dvt_fixed = 0x6,
2578	.vmax = 0x65,
2579	.vmin = 0x20,
2580	},
2581	{
2582	.pdata = (const struct svs_bank_pdata) {
2583	.sw_id = SVSB_SWID_GPU,
2584	.set_freq_pct = svs_set_bank_freq_pct_v2,
2585	.get_volts = svs_get_bank_volts_v2,
2586	.tzone_name = "gpu",
2587	.opp_count = MAX_OPP_ENTRIES,
2588	.volt_step = 6250,
2589	.volt_base = 400000,
2590	.age_config = 0x555555,
2591	.dc_config = 0x1,
2592	.vco = 0x10,
2593	.chk_shift = 0x87,
2594	.int_st = BIT(4),
2595	.ctl0 = 0x00100003,
2596	.tzone_htemp = 85000,
2597	.tzone_htemp_voffset = 8,
2598	.tzone_ltemp = 25000,
2599	.tzone_ltemp_voffset = 7,
2600	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2601	{ 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 }
2602	}
2603	},
2604	.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2605	.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2606	.freq_base = 850000000,
2607	.core_sel = 0x0fff0104,
2608	.dvt_fixed = 0x4,
2609	.vmax = 0x58,
2610	.vmin = 0x20,
2611	},
2612	};
2613
2614	static struct svs_bank svs_mt8183_banks[] = {
2615	{
2616	.pdata = (const struct svs_bank_pdata) {
2617	.sw_id = SVSB_SWID_CPU_LITTLE,
2618	.set_freq_pct = svs_set_bank_freq_pct_v2,
2619	.get_volts = svs_get_bank_volts_v2,
2620	.cpu_id = 0,
2621	.buck_name = "proc",
2622	.opp_count = MAX_OPP_ENTRIES,
2623	.vboot = 0x30,
2624	.volt_step = 6250,
2625	.volt_base = 500000,
2626	.age_config = 0x555555,
2627	.dc_config = 0x555555,
2628	.vco = 0x10,
2629	.chk_shift = 0x77,
2630	.int_st = BIT(0),
2631	.ctl0 = 0x00010001,
2632	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2633	{ 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 }
2634	}
2635	},
2636	.volt_flags = SVSB_INIT01_VOLT_INC_ONLY,
2637	.mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2638	.freq_base = 1989000000,
2639	.core_sel = 0x8fff0000,
2640	.dvt_fixed = 0x7,
2641	.vmax = 0x64,
2642	.vmin = 0x18,
2643
2644	},
2645	{
2646	.pdata = (const struct svs_bank_pdata) {
2647	.sw_id = SVSB_SWID_CPU_BIG,
2648	.set_freq_pct = svs_set_bank_freq_pct_v2,
2649	.get_volts = svs_get_bank_volts_v2,
2650	.cpu_id = 4,
2651	.buck_name = "proc",
2652	.opp_count = MAX_OPP_ENTRIES,
2653	.vboot = 0x30,
2654	.volt_step = 6250,
2655	.volt_base = 500000,
2656	.age_config = 0x555555,
2657	.dc_config = 0x555555,
2658	.vco = 0x10,
2659	.chk_shift = 0x77,
2660	.int_st = BIT(1),
2661	.ctl0 = 0x00000001,
2662	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2663	{ 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 }
2664	}
2665	},
2666	.volt_flags = SVSB_INIT01_VOLT_INC_ONLY,
2667	.mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2668	.freq_base = 1989000000,
2669	.core_sel = 0x8fff0001,
2670	.dvt_fixed = 0x7,
2671	.vmax = 0x58,
2672	.vmin = 0x10,
2673
2674	},
2675	{
2676	.pdata = (const struct svs_bank_pdata) {
2677	.sw_id = SVSB_SWID_CCI,
2678	.set_freq_pct = svs_set_bank_freq_pct_v2,
2679	.get_volts = svs_get_bank_volts_v2,
2680	.buck_name = "proc",
2681	.opp_count = MAX_OPP_ENTRIES,
2682	.vboot = 0x30,
2683	.volt_step = 6250,
2684	.volt_base = 500000,
2685	.age_config = 0x555555,
2686	.dc_config = 0x555555,
2687	.vco = 0x10,
2688	.chk_shift = 0x77,
2689	.int_st = BIT(2),
2690	.ctl0 = 0x00100003,
2691	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2692	{ 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 }
2693	}
2694	},
2695	.volt_flags = SVSB_INIT01_VOLT_INC_ONLY,
2696	.mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2697	.freq_base = 1196000000,
2698	.core_sel = 0x8fff0002,
2699	.dvt_fixed = 0x7,
2700	.vmax = 0x64,
2701	.vmin = 0x18,
2702	},
2703	{
2704	.pdata = (const struct svs_bank_pdata) {
2705	.sw_id = SVSB_SWID_GPU,
2706	.set_freq_pct = svs_set_bank_freq_pct_v2,
2707	.get_volts = svs_get_bank_volts_v2,
2708	.buck_name = "mali",
2709	.tzone_name = "gpu",
2710	.opp_count = MAX_OPP_ENTRIES,
2711	.vboot = 0x30,
2712	.volt_step = 6250,
2713	.volt_base = 500000,
2714	.age_config = 0x555555,
2715	.dc_config = 0x555555,
2716	.vco = 0x10,
2717	.chk_shift = 0x77,
2718	.int_st = BIT(3),
2719	.ctl0 = 0x00050001,
2720	.tzone_htemp = 85000,
2721	.tzone_htemp_voffset = 0,
2722	.tzone_ltemp = 25000,
2723	.tzone_ltemp_voffset = 3,
2724	.dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) {
2725	{ 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 }
2726	}
2727	},
2728	.volt_flags = SVSB_INIT01_PD_REQ | SVSB_INIT01_VOLT_INC_ONLY,
2729	.mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | SVSB_MODE_MON,
2730	.freq_base = 900000000,
2731	.core_sel = 0x8fff0003,
2732	.dvt_fixed = 0x3,
2733	.vmax = 0x40,
2734	.vmin = 0x14,
2735	},
2736	};
2737
2738	static const struct svs_platform_data svs_mt8195_platform_data = {
2739	.name = "mt8195-svs",
2740	.banks = svs_mt8195_banks,
2741	.efuse_parsing = svs_common_parse_efuse,
2742	.probe = svs_mt8192_platform_probe,
2743	.regs = svs_regs_v2,
2744	.bank_max = ARRAY_SIZE(svs_mt8195_banks),
2745	.ts_coeff = SVSB_TS_COEFF_MT8195,
2746	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2747	{ 0, 0 }, { 19, 4 }
2748	}
2749	};
2750
2751	static const struct svs_platform_data svs_mt8192_platform_data = {
2752	.name = "mt8192-svs",
2753	.banks = svs_mt8192_banks,
2754	.efuse_parsing = svs_common_parse_efuse,
2755	.probe = svs_mt8192_platform_probe,
2756	.regs = svs_regs_v2,
2757	.bank_max = ARRAY_SIZE(svs_mt8192_banks),
2758	.ts_coeff = SVSB_TS_COEFF_MT8195,
2759	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2760	/* FT_PGM not present */
2761	{ -1, 0 }, { 19, 4 }
2762	}
2763	};
2764
2765	static const struct svs_platform_data svs_mt8188_platform_data = {
2766	.name = "mt8188-svs",
2767	.banks = svs_mt8188_banks,
2768	.efuse_parsing = svs_common_parse_efuse,
2769	.probe = svs_mt8192_platform_probe,
2770	.regs = svs_regs_v2,
2771	.bank_max = ARRAY_SIZE(svs_mt8188_banks),
2772	.ts_coeff = SVSB_TS_COEFF_MT8195,
2773	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2774	/* FT_PGM and VMIN not present */
2775	{ -1, 0 }, { -1, 0 }
2776	}
2777	};
2778
2779	static const struct svs_platform_data svs_mt8186_platform_data = {
2780	.name = "mt8186-svs",
2781	.banks = svs_mt8186_banks,
2782	.efuse_parsing = svs_common_parse_efuse,
2783	.probe = svs_mt8192_platform_probe,
2784	.regs = svs_regs_v2,
2785	.bank_max = ARRAY_SIZE(svs_mt8186_banks),
2786	.ts_coeff = SVSB_TS_COEFF_MT8186,
2787	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2788	/* FT_PGM and VMIN not present */
2789	{ -1, 0 }, { -1, 0 }
2790	}
2791	};
2792
2793	static const struct svs_platform_data svs_mt8183_platform_data = {
2794	.name = "mt8183-svs",
2795	.banks = svs_mt8183_banks,
2796	.efuse_parsing = svs_mt8183_efuse_parsing,
2797	.probe = svs_mt8183_platform_probe,
2798	.regs = svs_regs_v2,
2799	.bank_max = ARRAY_SIZE(svs_mt8183_banks),
2800	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2801	/* VMIN not present */
2802	{ 0, 4 }, { -1, 0 }
2803	}
2804	};
2805
2806	static const struct of_device_id svs_of_match[] = {
2807	{ .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data },
2808	{ .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data },
2809	{ .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data },
2810	{ .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data },
2811	{ .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data },
2812	{ /* sentinel */ }
2813	};
2814	MODULE_DEVICE_TABLE(of, svs_of_match);
2815
2816	static int svs_probe(struct platform_device *pdev)
2817	{
2818	struct svs_platform *svsp;
2819	const struct svs_platform_data *svsp_data;
2820	int ret, svsp_irq;
2821
2822	svsp_data = of_device_get_match_data(dev: &pdev->dev);
2823
2824	svsp = devm_kzalloc(dev: &pdev->dev, size: sizeof(*svsp), GFP_KERNEL);
2825	if (!svsp)
2826	return -ENOMEM;
2827
2828	svsp->dev = &pdev->dev;
2829	svsp->banks = svsp_data->banks;
2830	svsp->regs = svsp_data->regs;
2831	svsp->bank_max = svsp_data->bank_max;
2832	svsp->ts_coeff = svsp_data->ts_coeff;
2833
2834	ret = svsp_data->probe(svsp);
2835	if (ret)
2836	return ret;
2837
2838	ret = svs_get_efuse_data(svsp, nvmem_cell_name: "svs-calibration-data",
2839	svsp_efuse: &svsp->efuse, svsp_efuse_max: &svsp->efuse_max);
2840	if (ret)
2841	return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Cannot read SVS calibration\n");
2842
2843	ret = svs_get_efuse_data(svsp, nvmem_cell_name: "t-calibration-data",
2844	svsp_efuse: &svsp->tefuse, svsp_efuse_max: &svsp->tefuse_max);
2845	if (ret) {
2846	dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Cannot read SVS-Thermal calibration\n");
2847	goto svs_probe_free_efuse;
2848	}
2849
2850	if (!svsp_data->efuse_parsing(svsp, svsp_data)) {
2851	ret = dev_err_probe(dev: svsp->dev, err: -EINVAL, fmt: "efuse data parsing failed\n");
2852	goto svs_probe_free_tefuse;
2853	}
2854
2855	ret = svs_bank_resource_setup(svsp);
2856	if (ret) {
2857	dev_err_probe(dev: svsp->dev, err: ret, fmt: "svs bank resource setup fail\n");
2858	goto svs_probe_free_tefuse;
2859	}
2860
2861	svsp_irq = platform_get_irq(pdev, 0);
2862	if (svsp_irq < 0) {
2863	ret = svsp_irq;
2864	goto svs_probe_free_tefuse;
2865	}
2866
2867	svsp->main_clk = devm_clk_get(dev: svsp->dev, id: "main");
2868	if (IS_ERR(ptr: svsp->main_clk)) {
2869	ret = dev_err_probe(dev: svsp->dev, err: PTR_ERR(ptr: svsp->main_clk),
2870	fmt: "failed to get clock\n");
2871	goto svs_probe_free_tefuse;
2872	}
2873
2874	ret = clk_prepare_enable(clk: svsp->main_clk);
2875	if (ret) {
2876	dev_err_probe(dev: svsp->dev, err: ret, fmt: "cannot enable main clk\n");
2877	goto svs_probe_free_tefuse;
2878	}
2879
2880	svsp->base = of_iomap(node: svsp->dev->of_node, index: 0);
2881	if (IS_ERR_OR_NULL(ptr: svsp->base)) {
2882	ret = dev_err_probe(dev: svsp->dev, err: -EINVAL, fmt: "cannot find svs register base\n");
2883	goto svs_probe_clk_disable;
2884	}
2885
2886	ret = devm_request_threaded_irq(dev: svsp->dev, irq: svsp_irq, NULL, thread_fn: svs_isr,
2887	IRQF_ONESHOT, devname: svsp_data->name, dev_id: svsp);
2888	if (ret) {
2889	dev_err_probe(dev: svsp->dev, err: ret, fmt: "register irq(%d) failed\n", svsp_irq);
2890	goto svs_probe_iounmap;
2891	}
2892
2893	ret = svs_start(svsp);
2894	if (ret) {
2895	dev_err_probe(dev: svsp->dev, err: ret, fmt: "svs start fail\n");
2896	goto svs_probe_iounmap;
2897	}
2898
2899	#ifdef CONFIG_DEBUG_FS
2900	ret = svs_create_debug_cmds(svsp);
2901	if (ret) {
2902	dev_err_probe(dev: svsp->dev, err: ret, fmt: "svs create debug cmds fail\n");
2903	goto svs_probe_iounmap;
2904	}
2905	#endif
2906
2907	return 0;
2908
2909	svs_probe_iounmap:
2910	iounmap(addr: svsp->base);
2911	svs_probe_clk_disable:
2912	clk_disable_unprepare(clk: svsp->main_clk);
2913	svs_probe_free_tefuse:
2914	kfree(objp: svsp->tefuse);
2915	svs_probe_free_efuse:
2916	kfree(objp: svsp->efuse);
2917	return ret;
2918	}
2919
2920	static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume);
2921
2922	static struct platform_driver svs_driver = {
2923	.probe = svs_probe,
2924	.driver = {
2925	.name = "mtk-svs",
2926	.pm = &svs_pm_ops,
2927	.of_match_table = svs_of_match,
2928	},
2929	};
2930
2931	module_platform_driver(svs_driver);
2932
2933	MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>");
2934	MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
2935	MODULE_DESCRIPTION("MediaTek SVS driver");
2936	MODULE_LICENSE("GPL");
2937