1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/bitfield.h>
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/device.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/mutex.h>
15#include <linux/nvmem-consumer.h>
16#include <linux/of.h>
17#include <linux/regmap.h>
18#include <linux/sizes.h>
19#include <linux/slab.h>
20#include <linux/soc/qcom/llcc-qcom.h>
21
22#define ACTIVATE BIT(0)
23#define DEACTIVATE BIT(1)
24#define ACT_CLEAR BIT(0)
25#define ACT_COMPLETE BIT(4)
26#define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
27#define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
28#define ACT_CTRL_ACT_TRIG BIT(0)
29#define ACT_CTRL_OPCODE_SHIFT 0x01
30#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
31#define ATTR1_FIXED_SIZE_SHIFT 0x03
32#define ATTR1_PRIORITY_SHIFT 0x04
33#define ATTR1_MAX_CAP_SHIFT 0x10
34#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
35#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
36#define ATTR0_BONUS_WAYS_SHIFT 0x10
37#define LLCC_STATUS_READ_DELAY 100
38
39#define CACHE_LINE_SIZE_SHIFT 6
40
41#define LLCC_LB_CNT_MASK GENMASK(31, 28)
42#define LLCC_LB_CNT_SHIFT 28
43
44#define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
45#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
46#define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K)
47#define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
48#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
49#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
50#define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n)
51
52#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
53#define LLCC_TRP_PCB_ACT 0x21f04
54#define LLCC_TRP_ALGO_CFG1 0x21f0c
55#define LLCC_TRP_ALGO_CFG2 0x21f10
56#define LLCC_TRP_ALGO_CFG3 0x21f14
57#define LLCC_TRP_ALGO_CFG4 0x21f18
58#define LLCC_TRP_ALGO_CFG5 0x21f1c
59#define LLCC_TRP_WRSC_EN 0x21f20
60#define LLCC_TRP_ALGO_CFG6 0x21f24
61#define LLCC_TRP_ALGO_CFG7 0x21f28
62#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
63#define LLCC_TRP_ALGO_CFG8 0x21f30
64
65#define LLCC_VERSION_2_0_0_0 0x02000000
66#define LLCC_VERSION_2_1_0_0 0x02010000
67#define LLCC_VERSION_4_1_0_0 0x04010000
68
69/**
70 * struct llcc_slice_config - Data associated with the llcc slice
71 * @usecase_id: Unique id for the client's use case
72 * @slice_id: llcc slice id for each client
73 * @max_cap: The maximum capacity of the cache slice provided in KB
74 * @priority: Priority of the client used to select victim line for replacement
75 * @fixed_size: Boolean indicating if the slice has a fixed capacity
76 * @bonus_ways: Bonus ways are additional ways to be used for any slice,
77 * if client ends up using more than reserved cache ways. Bonus
78 * ways are allocated only if they are not reserved for some
79 * other client.
80 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
81 * be used by any other client than the one its assigned to.
82 * @cache_mode: Each slice operates as a cache, this controls the mode of the
83 * slice: normal or TCM(Tightly Coupled Memory)
84 * @probe_target_ways: Determines what ways to probe for access hit. When
85 * configured to 1 only bonus and reserved ways are probed.
86 * When configured to 0 all ways in llcc are probed.
87 * @dis_cap_alloc: Disable capacity based allocation for a client
88 * @retain_on_pc: If this bit is set and client has maintained active vote
89 * then the ways assigned to this client are not flushed on power
90 * collapse.
91 * @activate_on_init: Activate the slice immediately after it is programmed
92 * @write_scid_en: Bit enables write cache support for a given scid.
93 * @write_scid_cacheable_en: Enables write cache cacheable support for a
94 * given scid (not supported on v2 or older hardware).
95 * @stale_en: Bit enables stale.
96 * @stale_cap_en: Bit enables stale only if current scid is over-cap.
97 * @mru_uncap_en: Roll-over on reserved cache ways if current scid is
98 * under-cap.
99 * @mru_rollover: Roll-over on reserved cache ways.
100 * @alloc_oneway_en: Allways allocate one way on over-cap even if there's no
101 * same-scid lines for replacement.
102 * @ovcap_en: Once current scid is over-capacity, allocate other over-cap SCID.
103 * @ovcap_prio: Once current scid is over-capacity, allocate other low priority
104 * over-cap scid. Depends on corresponding bit being set in
105 * ovcap_en.
106 * @vict_prio: When current scid is under-capacity, allocate over other
107 * lower-than victim priority-line threshold scid.
108 */
109struct llcc_slice_config {
110 u32 usecase_id;
111 u32 slice_id;
112 u32 max_cap;
113 u32 priority;
114 bool fixed_size;
115 u32 bonus_ways;
116 u32 res_ways;
117 u32 cache_mode;
118 u32 probe_target_ways;
119 bool dis_cap_alloc;
120 bool retain_on_pc;
121 bool activate_on_init;
122 bool write_scid_en;
123 bool write_scid_cacheable_en;
124 bool stale_en;
125 bool stale_cap_en;
126 bool mru_uncap_en;
127 bool mru_rollover;
128 bool alloc_oneway_en;
129 bool ovcap_en;
130 bool ovcap_prio;
131 bool vict_prio;
132};
133
134struct qcom_llcc_config {
135 const struct llcc_slice_config *sct_data;
136 const u32 *reg_offset;
137 const struct llcc_edac_reg_offset *edac_reg_offset;
138 int size;
139 bool need_llcc_cfg;
140 bool no_edac;
141};
142
143struct qcom_sct_config {
144 const struct qcom_llcc_config *llcc_config;
145 int num_config;
146};
147
148enum llcc_reg_offset {
149 LLCC_COMMON_HW_INFO,
150 LLCC_COMMON_STATUS0,
151};
152
153static const struct llcc_slice_config sc7180_data[] = {
154 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
155 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
156 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
157 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
158};
159
160static const struct llcc_slice_config sc7280_data[] = {
161 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
162 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
163 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
164 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
165 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
166 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0},
167 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
168 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
169 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
170};
171
172static const struct llcc_slice_config sc8180x_data[] = {
173 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 },
174 { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
175 { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
176 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
177 { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 },
178 { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
179 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
180 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
181 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
182 { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
183 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 },
184 { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
185 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
186 { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
187 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
188 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 },
189 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
190 { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
191 { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
192 { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 },
193 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
194 { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 },
195};
196
197static const struct llcc_slice_config sc8280xp_data[] = {
198 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
199 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
200 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
201 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
202 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
203 { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
204 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
205 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
206 { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
207 { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
208 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
209 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
210 { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
211 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
212 { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
213 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
214};
215
216static const struct llcc_slice_config sdm845_data[] = {
217 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
218 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
219 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
220 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
221 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
222 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
223 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
224 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
225 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
226 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
227 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
228 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
229 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
230 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
231 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
232 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
233 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
234 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
235};
236
237static const struct llcc_slice_config sm6350_data[] = {
238 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 },
239 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
240 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
241 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
242 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
243 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
244 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
245};
246
247static const struct llcc_slice_config sm7150_data[] = {
248 { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 },
249 { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
250 { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
251 { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
252 { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
253};
254
255static const struct llcc_slice_config sm8150_data[] = {
256 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 },
257 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
258 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
259 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
260 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 },
261 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
262 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
263 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
264 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
265 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
266 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 },
267 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
268 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
269 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
270 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
271 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
272 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
273 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
274 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
275 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
276 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 },
277};
278
279static const struct llcc_slice_config sm8250_data[] = {
280 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
281 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
282 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
283 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
284 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
285 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
286 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
287 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
288 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
289 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
290 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
291 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
292 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
293 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
294 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 },
295 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
296};
297
298static const struct llcc_slice_config sm8350_data[] = {
299 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 },
300 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
301 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
302 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
303 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
304 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
305 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
306 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
307 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
308 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
309 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 },
310 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
311 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
312 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 },
313 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 },
314 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
315 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
316 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
317 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
318};
319
320static const struct llcc_slice_config sm8450_data[] = {
321 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
322 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
323 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
324 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
325 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
326 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
327 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
328 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 },
329 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
330 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
331 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
332 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
333 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
334 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
335 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 },
336 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
337 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
338 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
339 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
340 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
341 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
342 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
343 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
344};
345
346static const struct llcc_slice_config sm8550_data[] = {
347 {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
348 {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
349 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
350 {LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
351 {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
352 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
353 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
354 {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, },
355 {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
356 {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
357 {LLCC_MDMPNG, 27, 1024, 0, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
358 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
359 {LLCC_CVP, 8, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
360 {LLCC_MODPE, 29, 64, 1, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
361 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
362 {LLCC_CAMEXP0, 4, 256, 4, 1, 0xF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
363 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
364 {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
365 {LLCC_CMPTHCP, 17, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
366 {LLCC_LCPDARE, 30, 128, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
367 {LLCC_AENPU, 3, 3072, 1, 1, 0xFE01FF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
368 {LLCC_ISLAND1, 12, 1792, 7, 1, 0xFE00, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
369 {LLCC_ISLAND4, 15, 256, 7, 1, 0x10000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
370 {LLCC_CAMEXP2, 19, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
371 {LLCC_CAMEXP3, 20, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
372 {LLCC_CAMEXP4, 21, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
373 {LLCC_DISP_WB, 23, 1024, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
374 {LLCC_DISP_1, 24, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
375 {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
376};
377
378static const struct llcc_slice_config sm8650_data[] = {
379 {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0},
380 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
381 {LLCC_AUDIO, 6, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
382 {LLCC_MDMHPGRW, 25, 1024, 3, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
383 {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
384 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
385 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
386 {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
387 {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
388 {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
389 {LLCC_MDMHPFX, 24, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
390 {LLCC_MDMPNG, 27, 1024, 0, 1, 0x000000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
391 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
392 {LLCC_CVP, 8, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
393 {LLCC_MODPE, 29, 128, 1, 1, 0xF00000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0},
394 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
395 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
396 {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
397 {LLCC_CMPTHCP, 17, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
398 {LLCC_LCPDARE, 30, 128, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0},
399 {LLCC_AENPU, 3, 3072, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
400 {LLCC_ISLAND1, 12, 5888, 7, 1, 0x0, 0x7FFFFF, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
401 {LLCC_DISP_WB, 23, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
402 {LLCC_VIDVSP, 28, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
403};
404
405static const struct llcc_slice_config qdu1000_data_2ch[] = {
406 { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
407 { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
408 { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
409 { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
410 { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
411 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
412 { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
413};
414
415static const struct llcc_slice_config qdu1000_data_4ch[] = {
416 { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
417 { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
418 { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
419 { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
420 { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
421 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
422 { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
423};
424
425static const struct llcc_slice_config qdu1000_data_8ch[] = {
426 { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
427 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
428 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
429 { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
430 { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
431 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
432 { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
433};
434
435static const struct llcc_slice_config x1e80100_data[] = {
436 {LLCC_CPUSS, 1, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
437 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
438 {LLCC_AUDIO, 6, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
439 {LLCC_CMPT, 10, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
440 {LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
441 {LLCC_GPU, 9, 4096, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
442 {LLCC_MMUHWT, 18, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
443 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
444 {LLCC_CVP, 8, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
445 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
446 {LLCC_CAMEXP1, 7, 3072, 2, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
447 {LLCC_LCPDARE, 30, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
448 {LLCC_AENPU, 3, 3072, 1, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
449 {LLCC_ISLAND1, 12, 512, 7, 1, 0x1, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
450 {LLCC_ISLAND2, 13, 512, 7, 1, 0x2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
451 {LLCC_ISLAND3, 14, 512, 7, 1, 0x3, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
452 {LLCC_ISLAND4, 15, 512, 7, 1, 0x4, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
453 {LLCC_CAMEXP2, 19, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
454 {LLCC_CAMEXP3, 20, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
455 {LLCC_CAMEXP4, 21, 3072, 3, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
456};
457
458static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
459 .trp_ecc_error_status0 = 0x20344,
460 .trp_ecc_error_status1 = 0x20348,
461 .trp_ecc_sb_err_syn0 = 0x2304c,
462 .trp_ecc_db_err_syn0 = 0x20370,
463 .trp_ecc_error_cntr_clear = 0x20440,
464 .trp_interrupt_0_status = 0x20480,
465 .trp_interrupt_0_clear = 0x20484,
466 .trp_interrupt_0_enable = 0x20488,
467
468 /* LLCC Common registers */
469 .cmn_status0 = 0x3000c,
470 .cmn_interrupt_0_enable = 0x3001c,
471 .cmn_interrupt_2_enable = 0x3003c,
472
473 /* LLCC DRP registers */
474 .drp_ecc_error_cfg = 0x40000,
475 .drp_ecc_error_cntr_clear = 0x40004,
476 .drp_interrupt_status = 0x41000,
477 .drp_interrupt_clear = 0x41008,
478 .drp_interrupt_enable = 0x4100c,
479 .drp_ecc_error_status0 = 0x42044,
480 .drp_ecc_error_status1 = 0x42048,
481 .drp_ecc_sb_err_syn0 = 0x4204c,
482 .drp_ecc_db_err_syn0 = 0x42070,
483};
484
485static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
486 .trp_ecc_error_status0 = 0x20344,
487 .trp_ecc_error_status1 = 0x20348,
488 .trp_ecc_sb_err_syn0 = 0x2034c,
489 .trp_ecc_db_err_syn0 = 0x20370,
490 .trp_ecc_error_cntr_clear = 0x20440,
491 .trp_interrupt_0_status = 0x20480,
492 .trp_interrupt_0_clear = 0x20484,
493 .trp_interrupt_0_enable = 0x20488,
494
495 /* LLCC Common registers */
496 .cmn_status0 = 0x3400c,
497 .cmn_interrupt_0_enable = 0x3401c,
498 .cmn_interrupt_2_enable = 0x3403c,
499
500 /* LLCC DRP registers */
501 .drp_ecc_error_cfg = 0x50000,
502 .drp_ecc_error_cntr_clear = 0x50004,
503 .drp_interrupt_status = 0x50020,
504 .drp_interrupt_clear = 0x50028,
505 .drp_interrupt_enable = 0x5002c,
506 .drp_ecc_error_status0 = 0x520f4,
507 .drp_ecc_error_status1 = 0x520f8,
508 .drp_ecc_sb_err_syn0 = 0x520fc,
509 .drp_ecc_db_err_syn0 = 0x52120,
510};
511
512/* LLCC register offset starting from v1.0.0 */
513static const u32 llcc_v1_reg_offset[] = {
514 [LLCC_COMMON_HW_INFO] = 0x00030000,
515 [LLCC_COMMON_STATUS0] = 0x0003000c,
516};
517
518/* LLCC register offset starting from v2.0.1 */
519static const u32 llcc_v2_1_reg_offset[] = {
520 [LLCC_COMMON_HW_INFO] = 0x00034000,
521 [LLCC_COMMON_STATUS0] = 0x0003400c,
522};
523
524static const struct qcom_llcc_config qdu1000_cfg[] = {
525 {
526 .sct_data = qdu1000_data_8ch,
527 .size = ARRAY_SIZE(qdu1000_data_8ch),
528 .need_llcc_cfg = true,
529 .reg_offset = llcc_v2_1_reg_offset,
530 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
531 },
532 {
533 .sct_data = qdu1000_data_4ch,
534 .size = ARRAY_SIZE(qdu1000_data_4ch),
535 .need_llcc_cfg = true,
536 .reg_offset = llcc_v2_1_reg_offset,
537 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
538 },
539 {
540 .sct_data = qdu1000_data_4ch,
541 .size = ARRAY_SIZE(qdu1000_data_4ch),
542 .need_llcc_cfg = true,
543 .reg_offset = llcc_v2_1_reg_offset,
544 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
545 },
546 {
547 .sct_data = qdu1000_data_2ch,
548 .size = ARRAY_SIZE(qdu1000_data_2ch),
549 .need_llcc_cfg = true,
550 .reg_offset = llcc_v2_1_reg_offset,
551 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
552 },
553};
554
555static const struct qcom_llcc_config sc7180_cfg[] = {
556 {
557 .sct_data = sc7180_data,
558 .size = ARRAY_SIZE(sc7180_data),
559 .need_llcc_cfg = true,
560 .reg_offset = llcc_v1_reg_offset,
561 .edac_reg_offset = &llcc_v1_edac_reg_offset,
562 },
563};
564
565static const struct qcom_llcc_config sc7280_cfg[] = {
566 {
567 .sct_data = sc7280_data,
568 .size = ARRAY_SIZE(sc7280_data),
569 .need_llcc_cfg = true,
570 .reg_offset = llcc_v1_reg_offset,
571 .edac_reg_offset = &llcc_v1_edac_reg_offset,
572 },
573};
574
575static const struct qcom_llcc_config sc8180x_cfg[] = {
576 {
577 .sct_data = sc8180x_data,
578 .size = ARRAY_SIZE(sc8180x_data),
579 .need_llcc_cfg = true,
580 .reg_offset = llcc_v1_reg_offset,
581 .edac_reg_offset = &llcc_v1_edac_reg_offset,
582 },
583};
584
585static const struct qcom_llcc_config sc8280xp_cfg[] = {
586 {
587 .sct_data = sc8280xp_data,
588 .size = ARRAY_SIZE(sc8280xp_data),
589 .need_llcc_cfg = true,
590 .reg_offset = llcc_v1_reg_offset,
591 .edac_reg_offset = &llcc_v1_edac_reg_offset,
592 },
593};
594
595static const struct qcom_llcc_config sdm845_cfg[] = {
596 {
597 .sct_data = sdm845_data,
598 .size = ARRAY_SIZE(sdm845_data),
599 .need_llcc_cfg = false,
600 .reg_offset = llcc_v1_reg_offset,
601 .edac_reg_offset = &llcc_v1_edac_reg_offset,
602 .no_edac = true,
603 },
604};
605
606static const struct qcom_llcc_config sm6350_cfg[] = {
607 {
608 .sct_data = sm6350_data,
609 .size = ARRAY_SIZE(sm6350_data),
610 .need_llcc_cfg = true,
611 .reg_offset = llcc_v1_reg_offset,
612 .edac_reg_offset = &llcc_v1_edac_reg_offset,
613 },
614};
615
616static const struct qcom_llcc_config sm7150_cfg[] = {
617 {
618 .sct_data = sm7150_data,
619 .size = ARRAY_SIZE(sm7150_data),
620 .need_llcc_cfg = true,
621 .reg_offset = llcc_v1_reg_offset,
622 .edac_reg_offset = &llcc_v1_edac_reg_offset,
623 },
624};
625
626static const struct qcom_llcc_config sm8150_cfg[] = {
627 {
628 .sct_data = sm8150_data,
629 .size = ARRAY_SIZE(sm8150_data),
630 .need_llcc_cfg = true,
631 .reg_offset = llcc_v1_reg_offset,
632 .edac_reg_offset = &llcc_v1_edac_reg_offset,
633 },
634};
635
636static const struct qcom_llcc_config sm8250_cfg[] = {
637 {
638 .sct_data = sm8250_data,
639 .size = ARRAY_SIZE(sm8250_data),
640 .need_llcc_cfg = true,
641 .reg_offset = llcc_v1_reg_offset,
642 .edac_reg_offset = &llcc_v1_edac_reg_offset,
643 },
644};
645
646static const struct qcom_llcc_config sm8350_cfg[] = {
647 {
648 .sct_data = sm8350_data,
649 .size = ARRAY_SIZE(sm8350_data),
650 .need_llcc_cfg = true,
651 .reg_offset = llcc_v1_reg_offset,
652 .edac_reg_offset = &llcc_v1_edac_reg_offset,
653 },
654};
655
656static const struct qcom_llcc_config sm8450_cfg[] = {
657 {
658 .sct_data = sm8450_data,
659 .size = ARRAY_SIZE(sm8450_data),
660 .need_llcc_cfg = true,
661 .reg_offset = llcc_v2_1_reg_offset,
662 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
663 },
664};
665
666static const struct qcom_llcc_config sm8550_cfg[] = {
667 {
668 .sct_data = sm8550_data,
669 .size = ARRAY_SIZE(sm8550_data),
670 .need_llcc_cfg = true,
671 .reg_offset = llcc_v2_1_reg_offset,
672 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
673 },
674};
675
676static const struct qcom_llcc_config sm8650_cfg[] = {
677 {
678 .sct_data = sm8650_data,
679 .size = ARRAY_SIZE(sm8650_data),
680 .need_llcc_cfg = true,
681 .reg_offset = llcc_v2_1_reg_offset,
682 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
683 },
684};
685
686static const struct qcom_llcc_config x1e80100_cfg[] = {
687 {
688 .sct_data = x1e80100_data,
689 .size = ARRAY_SIZE(x1e80100_data),
690 .need_llcc_cfg = true,
691 .reg_offset = llcc_v2_1_reg_offset,
692 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
693 },
694};
695
696static const struct qcom_sct_config qdu1000_cfgs = {
697 .llcc_config = qdu1000_cfg,
698 .num_config = ARRAY_SIZE(qdu1000_cfg),
699};
700
701static const struct qcom_sct_config sc7180_cfgs = {
702 .llcc_config = sc7180_cfg,
703 .num_config = ARRAY_SIZE(sc7180_cfg),
704};
705
706static const struct qcom_sct_config sc7280_cfgs = {
707 .llcc_config = sc7280_cfg,
708 .num_config = ARRAY_SIZE(sc7280_cfg),
709};
710
711static const struct qcom_sct_config sc8180x_cfgs = {
712 .llcc_config = sc8180x_cfg,
713 .num_config = ARRAY_SIZE(sc8180x_cfg),
714};
715
716static const struct qcom_sct_config sc8280xp_cfgs = {
717 .llcc_config = sc8280xp_cfg,
718 .num_config = ARRAY_SIZE(sc8280xp_cfg),
719};
720
721static const struct qcom_sct_config sdm845_cfgs = {
722 .llcc_config = sdm845_cfg,
723 .num_config = ARRAY_SIZE(sdm845_cfg),
724};
725
726static const struct qcom_sct_config sm6350_cfgs = {
727 .llcc_config = sm6350_cfg,
728 .num_config = ARRAY_SIZE(sm6350_cfg),
729};
730
731static const struct qcom_sct_config sm7150_cfgs = {
732 .llcc_config = sm7150_cfg,
733 .num_config = ARRAY_SIZE(sm7150_cfg),
734};
735
736static const struct qcom_sct_config sm8150_cfgs = {
737 .llcc_config = sm8150_cfg,
738 .num_config = ARRAY_SIZE(sm8150_cfg),
739};
740
741static const struct qcom_sct_config sm8250_cfgs = {
742 .llcc_config = sm8250_cfg,
743 .num_config = ARRAY_SIZE(sm8250_cfg),
744};
745
746static const struct qcom_sct_config sm8350_cfgs = {
747 .llcc_config = sm8350_cfg,
748 .num_config = ARRAY_SIZE(sm8350_cfg),
749};
750
751static const struct qcom_sct_config sm8450_cfgs = {
752 .llcc_config = sm8450_cfg,
753 .num_config = ARRAY_SIZE(sm8450_cfg),
754};
755
756static const struct qcom_sct_config sm8550_cfgs = {
757 .llcc_config = sm8550_cfg,
758 .num_config = ARRAY_SIZE(sm8550_cfg),
759};
760
761static const struct qcom_sct_config sm8650_cfgs = {
762 .llcc_config = sm8650_cfg,
763 .num_config = ARRAY_SIZE(sm8650_cfg),
764};
765
766static const struct qcom_sct_config x1e80100_cfgs = {
767 .llcc_config = x1e80100_cfg,
768 .num_config = ARRAY_SIZE(x1e80100_cfg),
769};
770
771static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
772
773/**
774 * llcc_slice_getd - get llcc slice descriptor
775 * @uid: usecase_id for the client
776 *
777 * A pointer to llcc slice descriptor will be returned on success
778 * and error pointer is returned on failure
779 */
780struct llcc_slice_desc *llcc_slice_getd(u32 uid)
781{
782 const struct llcc_slice_config *cfg;
783 struct llcc_slice_desc *desc;
784 u32 sz, count;
785
786 if (IS_ERR(ptr: drv_data))
787 return ERR_CAST(ptr: drv_data);
788
789 cfg = drv_data->cfg;
790 sz = drv_data->cfg_size;
791
792 for (count = 0; cfg && count < sz; count++, cfg++)
793 if (cfg->usecase_id == uid)
794 break;
795
796 if (count == sz || !cfg)
797 return ERR_PTR(error: -ENODEV);
798
799 desc = kzalloc(size: sizeof(*desc), GFP_KERNEL);
800 if (!desc)
801 return ERR_PTR(error: -ENOMEM);
802
803 desc->slice_id = cfg->slice_id;
804 desc->slice_size = cfg->max_cap;
805
806 return desc;
807}
808EXPORT_SYMBOL_GPL(llcc_slice_getd);
809
810/**
811 * llcc_slice_putd - llcc slice descriptor
812 * @desc: Pointer to llcc slice descriptor
813 */
814void llcc_slice_putd(struct llcc_slice_desc *desc)
815{
816 if (!IS_ERR_OR_NULL(ptr: desc))
817 kfree(objp: desc);
818}
819EXPORT_SYMBOL_GPL(llcc_slice_putd);
820
821static int llcc_update_act_ctrl(u32 sid,
822 u32 act_ctrl_reg_val, u32 status)
823{
824 u32 act_ctrl_reg;
825 u32 act_clear_reg;
826 u32 status_reg;
827 u32 slice_status;
828 int ret;
829
830 if (IS_ERR(ptr: drv_data))
831 return PTR_ERR(ptr: drv_data);
832
833 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
834 act_clear_reg = LLCC_TRP_ACT_CLEARn(sid);
835 status_reg = LLCC_TRP_STATUSn(sid);
836
837 /* Set the ACTIVE trigger */
838 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
839 ret = regmap_write(map: drv_data->bcast_regmap, reg: act_ctrl_reg,
840 val: act_ctrl_reg_val);
841 if (ret)
842 return ret;
843
844 /* Clear the ACTIVE trigger */
845 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
846 ret = regmap_write(map: drv_data->bcast_regmap, reg: act_ctrl_reg,
847 val: act_ctrl_reg_val);
848 if (ret)
849 return ret;
850
851 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
852 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
853 slice_status, (slice_status & ACT_COMPLETE),
854 0, LLCC_STATUS_READ_DELAY);
855 if (ret)
856 return ret;
857 }
858
859 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
860 slice_status, !(slice_status & status),
861 0, LLCC_STATUS_READ_DELAY);
862 if (ret)
863 return ret;
864
865 if (drv_data->version >= LLCC_VERSION_4_1_0_0)
866 ret = regmap_write(map: drv_data->bcast_regmap, reg: act_clear_reg,
867 ACT_CLEAR);
868
869 return ret;
870}
871
872/**
873 * llcc_slice_activate - Activate the llcc slice
874 * @desc: Pointer to llcc slice descriptor
875 *
876 * A value of zero will be returned on success and a negative errno will
877 * be returned in error cases
878 */
879int llcc_slice_activate(struct llcc_slice_desc *desc)
880{
881 int ret;
882 u32 act_ctrl_val;
883
884 if (IS_ERR(ptr: drv_data))
885 return PTR_ERR(ptr: drv_data);
886
887 if (IS_ERR_OR_NULL(ptr: desc))
888 return -EINVAL;
889
890 mutex_lock(&drv_data->lock);
891 if (test_bit(desc->slice_id, drv_data->bitmap)) {
892 mutex_unlock(lock: &drv_data->lock);
893 return 0;
894 }
895
896 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
897
898 ret = llcc_update_act_ctrl(sid: desc->slice_id, act_ctrl_reg_val: act_ctrl_val,
899 DEACTIVATE);
900 if (ret) {
901 mutex_unlock(lock: &drv_data->lock);
902 return ret;
903 }
904
905 __set_bit(desc->slice_id, drv_data->bitmap);
906 mutex_unlock(lock: &drv_data->lock);
907
908 return ret;
909}
910EXPORT_SYMBOL_GPL(llcc_slice_activate);
911
912/**
913 * llcc_slice_deactivate - Deactivate the llcc slice
914 * @desc: Pointer to llcc slice descriptor
915 *
916 * A value of zero will be returned on success and a negative errno will
917 * be returned in error cases
918 */
919int llcc_slice_deactivate(struct llcc_slice_desc *desc)
920{
921 u32 act_ctrl_val;
922 int ret;
923
924 if (IS_ERR(ptr: drv_data))
925 return PTR_ERR(ptr: drv_data);
926
927 if (IS_ERR_OR_NULL(ptr: desc))
928 return -EINVAL;
929
930 mutex_lock(&drv_data->lock);
931 if (!test_bit(desc->slice_id, drv_data->bitmap)) {
932 mutex_unlock(lock: &drv_data->lock);
933 return 0;
934 }
935 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
936
937 ret = llcc_update_act_ctrl(sid: desc->slice_id, act_ctrl_reg_val: act_ctrl_val,
938 ACTIVATE);
939 if (ret) {
940 mutex_unlock(lock: &drv_data->lock);
941 return ret;
942 }
943
944 __clear_bit(desc->slice_id, drv_data->bitmap);
945 mutex_unlock(lock: &drv_data->lock);
946
947 return ret;
948}
949EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
950
951/**
952 * llcc_get_slice_id - return the slice id
953 * @desc: Pointer to llcc slice descriptor
954 */
955int llcc_get_slice_id(struct llcc_slice_desc *desc)
956{
957 if (IS_ERR_OR_NULL(ptr: desc))
958 return -EINVAL;
959
960 return desc->slice_id;
961}
962EXPORT_SYMBOL_GPL(llcc_get_slice_id);
963
964/**
965 * llcc_get_slice_size - return the slice id
966 * @desc: Pointer to llcc slice descriptor
967 */
968size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
969{
970 if (IS_ERR_OR_NULL(ptr: desc))
971 return 0;
972
973 return desc->slice_size;
974}
975EXPORT_SYMBOL_GPL(llcc_get_slice_size);
976
977static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
978 const struct qcom_llcc_config *cfg)
979{
980 int ret;
981 u32 attr2_cfg;
982 u32 attr1_cfg;
983 u32 attr0_cfg;
984 u32 attr2_val;
985 u32 attr1_val;
986 u32 attr0_val;
987 u32 max_cap_cacheline;
988 struct llcc_slice_desc desc;
989
990 attr1_val = config->cache_mode;
991 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
992 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
993 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
994
995 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
996
997 /*
998 * LLCC instances can vary for each target.
999 * The SW writes to broadcast register which gets propagated
1000 * to each llcc instance (llcc0,.. llccN).
1001 * Since the size of the memory is divided equally amongst the
1002 * llcc instances, we need to configure the max cap accordingly.
1003 */
1004 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
1005 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
1006 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
1007
1008 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
1009
1010 ret = regmap_write(map: drv_data->bcast_regmap, reg: attr1_cfg, val: attr1_val);
1011 if (ret)
1012 return ret;
1013
1014 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
1015 attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id);
1016 attr0_val = config->res_ways;
1017 attr2_val = config->bonus_ways;
1018 } else {
1019 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
1020 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
1021 }
1022
1023 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
1024
1025 ret = regmap_write(map: drv_data->bcast_regmap, reg: attr0_cfg, val: attr0_val);
1026 if (ret)
1027 return ret;
1028
1029 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
1030 ret = regmap_write(map: drv_data->bcast_regmap, reg: attr2_cfg, val: attr2_val);
1031 if (ret)
1032 return ret;
1033 }
1034
1035 if (cfg->need_llcc_cfg) {
1036 u32 disable_cap_alloc, retain_pc;
1037
1038 disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
1039 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC,
1040 BIT(config->slice_id), val: disable_cap_alloc);
1041 if (ret)
1042 return ret;
1043
1044 if (drv_data->version < LLCC_VERSION_4_1_0_0) {
1045 retain_pc = config->retain_on_pc << config->slice_id;
1046 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_PCB_ACT,
1047 BIT(config->slice_id), val: retain_pc);
1048 if (ret)
1049 return ret;
1050 }
1051 }
1052
1053 if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
1054 u32 wren;
1055
1056 wren = config->write_scid_en << config->slice_id;
1057 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
1058 BIT(config->slice_id), val: wren);
1059 if (ret)
1060 return ret;
1061 }
1062
1063 if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
1064 u32 wr_cache_en;
1065
1066 wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
1067 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
1068 BIT(config->slice_id), val: wr_cache_en);
1069 if (ret)
1070 return ret;
1071 }
1072
1073 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
1074 u32 stale_en;
1075 u32 stale_cap_en;
1076 u32 mru_uncap_en;
1077 u32 mru_rollover;
1078 u32 alloc_oneway_en;
1079 u32 ovcap_en;
1080 u32 ovcap_prio;
1081 u32 vict_prio;
1082
1083 stale_en = config->stale_en << config->slice_id;
1084 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1,
1085 BIT(config->slice_id), val: stale_en);
1086 if (ret)
1087 return ret;
1088
1089 stale_cap_en = config->stale_cap_en << config->slice_id;
1090 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2,
1091 BIT(config->slice_id), val: stale_cap_en);
1092 if (ret)
1093 return ret;
1094
1095 mru_uncap_en = config->mru_uncap_en << config->slice_id;
1096 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3,
1097 BIT(config->slice_id), val: mru_uncap_en);
1098 if (ret)
1099 return ret;
1100
1101 mru_rollover = config->mru_rollover << config->slice_id;
1102 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4,
1103 BIT(config->slice_id), val: mru_rollover);
1104 if (ret)
1105 return ret;
1106
1107 alloc_oneway_en = config->alloc_oneway_en << config->slice_id;
1108 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5,
1109 BIT(config->slice_id), val: alloc_oneway_en);
1110 if (ret)
1111 return ret;
1112
1113 ovcap_en = config->ovcap_en << config->slice_id;
1114 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6,
1115 BIT(config->slice_id), val: ovcap_en);
1116 if (ret)
1117 return ret;
1118
1119 ovcap_prio = config->ovcap_prio << config->slice_id;
1120 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7,
1121 BIT(config->slice_id), val: ovcap_prio);
1122 if (ret)
1123 return ret;
1124
1125 vict_prio = config->vict_prio << config->slice_id;
1126 ret = regmap_update_bits(map: drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8,
1127 BIT(config->slice_id), val: vict_prio);
1128 if (ret)
1129 return ret;
1130 }
1131
1132 if (config->activate_on_init) {
1133 desc.slice_id = config->slice_id;
1134 ret = llcc_slice_activate(&desc);
1135 }
1136
1137 return ret;
1138}
1139
1140static int qcom_llcc_cfg_program(struct platform_device *pdev,
1141 const struct qcom_llcc_config *cfg)
1142{
1143 int i;
1144 u32 sz;
1145 int ret = 0;
1146 const struct llcc_slice_config *llcc_table;
1147
1148 sz = drv_data->cfg_size;
1149 llcc_table = drv_data->cfg;
1150
1151 for (i = 0; i < sz; i++) {
1152 ret = _qcom_llcc_cfg_program(config: &llcc_table[i], cfg);
1153 if (ret)
1154 return ret;
1155 }
1156
1157 return ret;
1158}
1159
1160static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config)
1161{
1162 int ret;
1163
1164 ret = nvmem_cell_read_u8(dev: &pdev->dev, cell_id: "multi-chan-ddr", val: cfg_index);
1165 if (ret == -ENOENT || ret == -EOPNOTSUPP) {
1166 if (num_config > 1)
1167 return -EINVAL;
1168 *cfg_index = 0;
1169 return 0;
1170 }
1171
1172 if (!ret && *cfg_index >= num_config)
1173 ret = -EINVAL;
1174
1175 return ret;
1176}
1177
1178static void qcom_llcc_remove(struct platform_device *pdev)
1179{
1180 /* Set the global pointer to a error code to avoid referencing it */
1181 drv_data = ERR_PTR(error: -ENODEV);
1182}
1183
1184static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index,
1185 const char *name)
1186{
1187 void __iomem *base;
1188 struct regmap_config llcc_regmap_config = {
1189 .reg_bits = 32,
1190 .reg_stride = 4,
1191 .val_bits = 32,
1192 .fast_io = true,
1193 };
1194
1195 base = devm_platform_ioremap_resource(pdev, index);
1196 if (IS_ERR(ptr: base))
1197 return ERR_CAST(ptr: base);
1198
1199 llcc_regmap_config.name = name;
1200 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
1201}
1202
1203static int qcom_llcc_probe(struct platform_device *pdev)
1204{
1205 u32 num_banks;
1206 struct device *dev = &pdev->dev;
1207 int ret, i;
1208 struct platform_device *llcc_edac;
1209 const struct qcom_sct_config *cfgs;
1210 const struct qcom_llcc_config *cfg;
1211 const struct llcc_slice_config *llcc_cfg;
1212 u32 sz;
1213 u8 cfg_index;
1214 u32 version;
1215 struct regmap *regmap;
1216
1217 if (!IS_ERR(ptr: drv_data))
1218 return -EBUSY;
1219
1220 drv_data = devm_kzalloc(dev, size: sizeof(*drv_data), GFP_KERNEL);
1221 if (!drv_data) {
1222 ret = -ENOMEM;
1223 goto err;
1224 }
1225
1226 /* Initialize the first LLCC bank regmap */
1227 regmap = qcom_llcc_init_mmio(pdev, index: 0, name: "llcc0_base");
1228 if (IS_ERR(ptr: regmap)) {
1229 ret = PTR_ERR(ptr: regmap);
1230 goto err;
1231 }
1232
1233 cfgs = of_device_get_match_data(dev: &pdev->dev);
1234 if (!cfgs) {
1235 ret = -EINVAL;
1236 goto err;
1237 }
1238 ret = qcom_llcc_get_cfg_index(pdev, cfg_index: &cfg_index, num_config: cfgs->num_config);
1239 if (ret)
1240 goto err;
1241 cfg = &cfgs->llcc_config[cfg_index];
1242
1243 ret = regmap_read(map: regmap, reg: cfg->reg_offset[LLCC_COMMON_STATUS0], val: &num_banks);
1244 if (ret)
1245 goto err;
1246
1247 num_banks &= LLCC_LB_CNT_MASK;
1248 num_banks >>= LLCC_LB_CNT_SHIFT;
1249 drv_data->num_banks = num_banks;
1250
1251 drv_data->regmaps = devm_kcalloc(dev, n: num_banks, size: sizeof(*drv_data->regmaps), GFP_KERNEL);
1252 if (!drv_data->regmaps) {
1253 ret = -ENOMEM;
1254 goto err;
1255 }
1256
1257 drv_data->regmaps[0] = regmap;
1258
1259 /* Initialize rest of LLCC bank regmaps */
1260 for (i = 1; i < num_banks; i++) {
1261 char *base = kasprintf(GFP_KERNEL, fmt: "llcc%d_base", i);
1262
1263 drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, index: i, name: base);
1264 if (IS_ERR(ptr: drv_data->regmaps[i])) {
1265 ret = PTR_ERR(ptr: drv_data->regmaps[i]);
1266 kfree(objp: base);
1267 goto err;
1268 }
1269
1270 kfree(objp: base);
1271 }
1272
1273 drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, index: i, name: "llcc_broadcast_base");
1274 if (IS_ERR(ptr: drv_data->bcast_regmap)) {
1275 ret = PTR_ERR(ptr: drv_data->bcast_regmap);
1276 goto err;
1277 }
1278
1279 /* Extract version of the IP */
1280 ret = regmap_read(map: drv_data->bcast_regmap, reg: cfg->reg_offset[LLCC_COMMON_HW_INFO],
1281 val: &version);
1282 if (ret)
1283 goto err;
1284
1285 drv_data->version = version;
1286
1287 llcc_cfg = cfg->sct_data;
1288 sz = cfg->size;
1289
1290 for (i = 0; i < sz; i++)
1291 if (llcc_cfg[i].slice_id > drv_data->max_slices)
1292 drv_data->max_slices = llcc_cfg[i].slice_id;
1293
1294 drv_data->bitmap = devm_bitmap_zalloc(dev, nbits: drv_data->max_slices,
1295 GFP_KERNEL);
1296 if (!drv_data->bitmap) {
1297 ret = -ENOMEM;
1298 goto err;
1299 }
1300
1301 drv_data->cfg = llcc_cfg;
1302 drv_data->cfg_size = sz;
1303 drv_data->edac_reg_offset = cfg->edac_reg_offset;
1304 mutex_init(&drv_data->lock);
1305 platform_set_drvdata(pdev, data: drv_data);
1306
1307 ret = qcom_llcc_cfg_program(pdev, cfg);
1308 if (ret)
1309 goto err;
1310
1311 drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
1312
1313 /*
1314 * On some platforms, the access to EDAC registers will be locked by
1315 * the bootloader. So probing the EDAC driver will result in a crash.
1316 * Hence, disable the creation of EDAC platform device for the
1317 * problematic platforms.
1318 */
1319 if (!cfg->no_edac) {
1320 llcc_edac = platform_device_register_data(parent: &pdev->dev,
1321 name: "qcom_llcc_edac", id: -1, data: drv_data,
1322 size: sizeof(*drv_data));
1323 if (IS_ERR(ptr: llcc_edac))
1324 dev_err(dev, "Failed to register llcc edac driver\n");
1325 }
1326
1327 return 0;
1328err:
1329 drv_data = ERR_PTR(error: -ENODEV);
1330 return ret;
1331}
1332
1333static const struct of_device_id qcom_llcc_of_match[] = {
1334 { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
1335 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
1336 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
1337 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
1338 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
1339 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
1340 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
1341 { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
1342 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
1343 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
1344 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
1345 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
1346 { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
1347 { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs },
1348 { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs },
1349 { }
1350};
1351MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
1352
1353static struct platform_driver qcom_llcc_driver = {
1354 .driver = {
1355 .name = "qcom-llcc",
1356 .of_match_table = qcom_llcc_of_match,
1357 },
1358 .probe = qcom_llcc_probe,
1359 .remove_new = qcom_llcc_remove,
1360};
1361module_platform_driver(qcom_llcc_driver);
1362
1363MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
1364MODULE_LICENSE("GPL v2");
1365

source code of linux/drivers/soc/qcom/llcc-qcom.c