1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Xilinx SPI controller driver (host mode only) |
4 | * |
5 | * Author: MontaVista Software, Inc. |
6 | * source@mvista.com |
7 | * |
8 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
9 | * Copyright (c) 2009 Intel Corporation |
10 | * 2002-2007 (c) MontaVista Software, Inc. |
11 | |
12 | */ |
13 | |
14 | #include <linux/module.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/of.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/spi/spi.h> |
19 | #include <linux/spi/spi_bitbang.h> |
20 | #include <linux/spi/xilinx_spi.h> |
21 | #include <linux/io.h> |
22 | |
23 | #define XILINX_SPI_MAX_CS 32 |
24 | |
25 | #define XILINX_SPI_NAME "xilinx_spi" |
26 | |
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) |
28 | * Product Specification", DS464 |
29 | */ |
30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
31 | |
32 | #define XSPI_CR_LOOP 0x01 |
33 | #define XSPI_CR_ENABLE 0x02 |
34 | #define XSPI_CR_MASTER_MODE 0x04 |
35 | #define XSPI_CR_CPOL 0x08 |
36 | #define XSPI_CR_CPHA 0x10 |
37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
38 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) |
39 | #define XSPI_CR_TXFIFO_RESET 0x20 |
40 | #define XSPI_CR_RXFIFO_RESET 0x40 |
41 | #define XSPI_CR_MANUAL_SSELECT 0x80 |
42 | #define XSPI_CR_TRANS_INHIBIT 0x100 |
43 | #define XSPI_CR_LSB_FIRST 0x200 |
44 | |
45 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
46 | |
47 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ |
48 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ |
49 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ |
50 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ |
51 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ |
52 | |
53 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
54 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ |
55 | |
56 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ |
57 | |
58 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 |
59 | * IPIF registers are 32 bit |
60 | */ |
61 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ |
62 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 |
63 | |
64 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ |
65 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ |
66 | |
67 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ |
68 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while |
69 | * disabled */ |
70 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ |
71 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ |
72 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ |
73 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ |
74 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
75 | |
76 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ |
77 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ |
78 | |
79 | struct xilinx_spi { |
80 | /* bitbang has to be first */ |
81 | struct spi_bitbang bitbang; |
82 | struct completion done; |
83 | void __iomem *regs; /* virt. address of the control registers */ |
84 | |
85 | int irq; |
86 | bool force_irq; /* force irq to setup host inhibit */ |
87 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
88 | const u8 *tx_ptr; /* pointer in the Rx buffer */ |
89 | u8 bytes_per_word; |
90 | int buffer_size; /* buffer size in words */ |
91 | u32 cs_inactive; /* Level of the CS pins when inactive*/ |
92 | unsigned int (*read_fn)(void __iomem *); |
93 | void (*write_fn)(u32, void __iomem *); |
94 | }; |
95 | |
96 | static void xspi_write32(u32 val, void __iomem *addr) |
97 | { |
98 | iowrite32(val, addr); |
99 | } |
100 | |
101 | static unsigned int xspi_read32(void __iomem *addr) |
102 | { |
103 | return ioread32(addr); |
104 | } |
105 | |
106 | static void xspi_write32_be(u32 val, void __iomem *addr) |
107 | { |
108 | iowrite32be(val, addr); |
109 | } |
110 | |
111 | static unsigned int xspi_read32_be(void __iomem *addr) |
112 | { |
113 | return ioread32be(addr); |
114 | } |
115 | |
116 | static void xilinx_spi_tx(struct xilinx_spi *xspi) |
117 | { |
118 | u32 data = 0; |
119 | |
120 | if (!xspi->tx_ptr) { |
121 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); |
122 | return; |
123 | } |
124 | |
125 | switch (xspi->bytes_per_word) { |
126 | case 1: |
127 | data = *(u8 *)(xspi->tx_ptr); |
128 | break; |
129 | case 2: |
130 | data = *(u16 *)(xspi->tx_ptr); |
131 | break; |
132 | case 4: |
133 | data = *(u32 *)(xspi->tx_ptr); |
134 | break; |
135 | } |
136 | |
137 | xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); |
138 | xspi->tx_ptr += xspi->bytes_per_word; |
139 | } |
140 | |
141 | static void xilinx_spi_rx(struct xilinx_spi *xspi) |
142 | { |
143 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); |
144 | |
145 | if (!xspi->rx_ptr) |
146 | return; |
147 | |
148 | switch (xspi->bytes_per_word) { |
149 | case 1: |
150 | *(u8 *)(xspi->rx_ptr) = data; |
151 | break; |
152 | case 2: |
153 | *(u16 *)(xspi->rx_ptr) = data; |
154 | break; |
155 | case 4: |
156 | *(u32 *)(xspi->rx_ptr) = data; |
157 | break; |
158 | } |
159 | |
160 | xspi->rx_ptr += xspi->bytes_per_word; |
161 | } |
162 | |
163 | static void xspi_init_hw(struct xilinx_spi *xspi) |
164 | { |
165 | void __iomem *regs_base = xspi->regs; |
166 | |
167 | /* Reset the SPI device */ |
168 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
169 | regs_base + XIPIF_V123B_RESETR_OFFSET); |
170 | /* Enable the transmit empty interrupt, which we use to determine |
171 | * progress on the transmission. |
172 | */ |
173 | xspi->write_fn(XSPI_INTR_TX_EMPTY, |
174 | regs_base + XIPIF_V123B_IIER_OFFSET); |
175 | /* Disable the global IPIF interrupt */ |
176 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); |
177 | /* Deselect the Target on the SPI bus */ |
178 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
179 | /* Disable the transmitter, enable Manual Target Select Assertion, |
180 | * put SPI controller into host mode, and enable it */ |
181 | xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | |
182 | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, |
183 | regs_base + XSPI_CR_OFFSET); |
184 | } |
185 | |
186 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) |
187 | { |
188 | struct xilinx_spi *xspi = spi_controller_get_devdata(ctlr: spi->controller); |
189 | u16 cr; |
190 | u32 cs; |
191 | |
192 | if (is_on == BITBANG_CS_INACTIVE) { |
193 | /* Deselect the target on the SPI bus */ |
194 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
195 | return; |
196 | } |
197 | |
198 | /* Set the SPI clock phase and polarity */ |
199 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; |
200 | if (spi->mode & SPI_CPHA) |
201 | cr |= XSPI_CR_CPHA; |
202 | if (spi->mode & SPI_CPOL) |
203 | cr |= XSPI_CR_CPOL; |
204 | if (spi->mode & SPI_LSB_FIRST) |
205 | cr |= XSPI_CR_LSB_FIRST; |
206 | if (spi->mode & SPI_LOOP) |
207 | cr |= XSPI_CR_LOOP; |
208 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
209 | |
210 | /* We do not check spi->max_speed_hz here as the SPI clock |
211 | * frequency is not software programmable (the IP block design |
212 | * parameter) |
213 | */ |
214 | |
215 | cs = xspi->cs_inactive; |
216 | cs ^= BIT(spi_get_chipselect(spi, 0)); |
217 | |
218 | /* Activate the chip select */ |
219 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); |
220 | } |
221 | |
222 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a |
223 | * custom txrx_bufs(). |
224 | */ |
225 | static int xilinx_spi_setup_transfer(struct spi_device *spi, |
226 | struct spi_transfer *t) |
227 | { |
228 | struct xilinx_spi *xspi = spi_controller_get_devdata(ctlr: spi->controller); |
229 | |
230 | if (spi->mode & SPI_CS_HIGH) |
231 | xspi->cs_inactive &= ~BIT(spi_get_chipselect(spi, 0)); |
232 | else |
233 | xspi->cs_inactive |= BIT(spi_get_chipselect(spi, 0)); |
234 | |
235 | return 0; |
236 | } |
237 | |
238 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
239 | { |
240 | struct xilinx_spi *xspi = spi_controller_get_devdata(ctlr: spi->controller); |
241 | int remaining_words; /* the number of words left to transfer */ |
242 | bool use_irq = false; |
243 | u16 cr = 0; |
244 | |
245 | /* We get here with transmitter inhibited */ |
246 | |
247 | xspi->tx_ptr = t->tx_buf; |
248 | xspi->rx_ptr = t->rx_buf; |
249 | remaining_words = t->len / xspi->bytes_per_word; |
250 | |
251 | if (xspi->irq >= 0 && |
252 | (xspi->force_irq || remaining_words > xspi->buffer_size)) { |
253 | u32 isr; |
254 | use_irq = true; |
255 | /* Inhibit irq to avoid spurious irqs on tx_empty*/ |
256 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); |
257 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
258 | xspi->regs + XSPI_CR_OFFSET); |
259 | /* ACK old irqs (if any) */ |
260 | isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
261 | if (isr) |
262 | xspi->write_fn(isr, |
263 | xspi->regs + XIPIF_V123B_IISR_OFFSET); |
264 | /* Enable the global IPIF interrupt */ |
265 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, |
266 | xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
267 | reinit_completion(x: &xspi->done); |
268 | } |
269 | |
270 | while (remaining_words) { |
271 | int n_words, tx_words, rx_words; |
272 | u32 sr; |
273 | int stalled; |
274 | |
275 | n_words = min(remaining_words, xspi->buffer_size); |
276 | |
277 | tx_words = n_words; |
278 | while (tx_words--) |
279 | xilinx_spi_tx(xspi); |
280 | |
281 | /* Start the transfer by not inhibiting the transmitter any |
282 | * longer |
283 | */ |
284 | |
285 | if (use_irq) { |
286 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
287 | wait_for_completion(&xspi->done); |
288 | /* A transmit has just completed. Process received data |
289 | * and check for more data to transmit. Always inhibit |
290 | * the transmitter while the Isr refills the transmit |
291 | * register/FIFO, or make sure it is stopped if we're |
292 | * done. |
293 | */ |
294 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
295 | xspi->regs + XSPI_CR_OFFSET); |
296 | sr = XSPI_SR_TX_EMPTY_MASK; |
297 | } else |
298 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
299 | |
300 | /* Read out all the data from the Rx FIFO */ |
301 | rx_words = n_words; |
302 | stalled = 10; |
303 | while (rx_words) { |
304 | if (rx_words == n_words && !(stalled--) && |
305 | !(sr & XSPI_SR_TX_EMPTY_MASK) && |
306 | (sr & XSPI_SR_RX_EMPTY_MASK)) { |
307 | dev_err(&spi->dev, |
308 | "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n" ); |
309 | xspi_init_hw(xspi); |
310 | return -EIO; |
311 | } |
312 | |
313 | if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) { |
314 | xilinx_spi_rx(xspi); |
315 | rx_words--; |
316 | continue; |
317 | } |
318 | |
319 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
320 | if (!(sr & XSPI_SR_RX_EMPTY_MASK)) { |
321 | xilinx_spi_rx(xspi); |
322 | rx_words--; |
323 | } |
324 | } |
325 | |
326 | remaining_words -= n_words; |
327 | } |
328 | |
329 | if (use_irq) { |
330 | xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
331 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
332 | } |
333 | |
334 | return t->len; |
335 | } |
336 | |
337 | |
338 | /* This driver supports single host mode only. Hence Tx FIFO Empty |
339 | * is the only interrupt we care about. |
340 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Target Mode |
341 | * Fault are not to happen. |
342 | */ |
343 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) |
344 | { |
345 | struct xilinx_spi *xspi = dev_id; |
346 | u32 ipif_isr; |
347 | |
348 | /* Get the IPIF interrupts, and clear them immediately */ |
349 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
350 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); |
351 | |
352 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ |
353 | complete(&xspi->done); |
354 | return IRQ_HANDLED; |
355 | } |
356 | |
357 | return IRQ_NONE; |
358 | } |
359 | |
360 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) |
361 | { |
362 | u8 sr; |
363 | int n_words = 0; |
364 | |
365 | /* |
366 | * Before the buffer_size detection we reset the core |
367 | * to make sure we start with a clean state. |
368 | */ |
369 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
370 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); |
371 | |
372 | /* Fill the Tx FIFO with as many words as possible */ |
373 | do { |
374 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); |
375 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
376 | n_words++; |
377 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); |
378 | |
379 | return n_words; |
380 | } |
381 | |
382 | static const struct of_device_id xilinx_spi_of_match[] = { |
383 | { .compatible = "xlnx,axi-quad-spi-1.00.a" , }, |
384 | { .compatible = "xlnx,xps-spi-2.00.a" , }, |
385 | { .compatible = "xlnx,xps-spi-2.00.b" , }, |
386 | {} |
387 | }; |
388 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); |
389 | |
390 | static int xilinx_spi_probe(struct platform_device *pdev) |
391 | { |
392 | struct xilinx_spi *xspi; |
393 | struct xspi_platform_data *pdata; |
394 | struct resource *res; |
395 | int ret, num_cs = 0, bits_per_word; |
396 | struct spi_controller *host; |
397 | bool force_irq = false; |
398 | u32 tmp; |
399 | u8 i; |
400 | |
401 | pdata = dev_get_platdata(dev: &pdev->dev); |
402 | if (pdata) { |
403 | num_cs = pdata->num_chipselect; |
404 | bits_per_word = pdata->bits_per_word; |
405 | force_irq = pdata->force_irq; |
406 | } else { |
407 | of_property_read_u32(np: pdev->dev.of_node, propname: "xlnx,num-ss-bits" , |
408 | out_value: &num_cs); |
409 | ret = of_property_read_u32(np: pdev->dev.of_node, |
410 | propname: "xlnx,num-transfer-bits" , |
411 | out_value: &bits_per_word); |
412 | if (ret) |
413 | bits_per_word = 8; |
414 | } |
415 | |
416 | if (!num_cs) { |
417 | dev_err(&pdev->dev, |
418 | "Missing target select configuration data\n" ); |
419 | return -EINVAL; |
420 | } |
421 | |
422 | if (num_cs > XILINX_SPI_MAX_CS) { |
423 | dev_err(&pdev->dev, "Invalid number of spi targets\n" ); |
424 | return -EINVAL; |
425 | } |
426 | |
427 | host = devm_spi_alloc_host(dev: &pdev->dev, size: sizeof(struct xilinx_spi)); |
428 | if (!host) |
429 | return -ENODEV; |
430 | |
431 | /* the spi->mode bits understood by this driver: */ |
432 | host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
433 | SPI_CS_HIGH; |
434 | |
435 | xspi = spi_controller_get_devdata(ctlr: host); |
436 | xspi->cs_inactive = 0xffffffff; |
437 | xspi->bitbang.ctlr = host; |
438 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
439 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; |
440 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; |
441 | init_completion(x: &xspi->done); |
442 | |
443 | xspi->regs = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res); |
444 | if (IS_ERR(ptr: xspi->regs)) |
445 | return PTR_ERR(ptr: xspi->regs); |
446 | |
447 | host->bus_num = pdev->id; |
448 | host->num_chipselect = num_cs; |
449 | host->dev.of_node = pdev->dev.of_node; |
450 | |
451 | /* |
452 | * Detect endianess on the IP via loop bit in CR. Detection |
453 | * must be done before reset is sent because incorrect reset |
454 | * value generates error interrupt. |
455 | * Setup little endian helper functions first and try to use them |
456 | * and check if bit was correctly setup or not. |
457 | */ |
458 | xspi->read_fn = xspi_read32; |
459 | xspi->write_fn = xspi_write32; |
460 | |
461 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); |
462 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); |
463 | tmp &= XSPI_CR_LOOP; |
464 | if (tmp != XSPI_CR_LOOP) { |
465 | xspi->read_fn = xspi_read32_be; |
466 | xspi->write_fn = xspi_write32_be; |
467 | } |
468 | |
469 | host->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
470 | xspi->bytes_per_word = bits_per_word / 8; |
471 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
472 | |
473 | xspi->irq = platform_get_irq(pdev, 0); |
474 | if (xspi->irq < 0 && xspi->irq != -ENXIO) { |
475 | return xspi->irq; |
476 | } else if (xspi->irq >= 0) { |
477 | /* Register for SPI Interrupt */ |
478 | ret = devm_request_irq(dev: &pdev->dev, irq: xspi->irq, handler: xilinx_spi_irq, irqflags: 0, |
479 | devname: dev_name(dev: &pdev->dev), dev_id: xspi); |
480 | if (ret) |
481 | return ret; |
482 | |
483 | xspi->force_irq = force_irq; |
484 | } |
485 | |
486 | /* SPI controller initializations */ |
487 | xspi_init_hw(xspi); |
488 | |
489 | ret = spi_bitbang_start(spi: &xspi->bitbang); |
490 | if (ret) { |
491 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n" ); |
492 | return ret; |
493 | } |
494 | |
495 | dev_info(&pdev->dev, "at %pR, irq=%d\n" , res, xspi->irq); |
496 | |
497 | if (pdata) { |
498 | for (i = 0; i < pdata->num_devices; i++) |
499 | spi_new_device(host, pdata->devices + i); |
500 | } |
501 | |
502 | platform_set_drvdata(pdev, data: host); |
503 | return 0; |
504 | } |
505 | |
506 | static void xilinx_spi_remove(struct platform_device *pdev) |
507 | { |
508 | struct spi_controller *host = platform_get_drvdata(pdev); |
509 | struct xilinx_spi *xspi = spi_controller_get_devdata(ctlr: host); |
510 | void __iomem *regs_base = xspi->regs; |
511 | |
512 | spi_bitbang_stop(spi: &xspi->bitbang); |
513 | |
514 | /* Disable all the interrupts just in case */ |
515 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); |
516 | /* Disable the global IPIF interrupt */ |
517 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); |
518 | |
519 | spi_controller_put(ctlr: xspi->bitbang.ctlr); |
520 | } |
521 | |
522 | /* work with hotplug and coldplug */ |
523 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); |
524 | |
525 | static struct platform_driver xilinx_spi_driver = { |
526 | .probe = xilinx_spi_probe, |
527 | .remove_new = xilinx_spi_remove, |
528 | .driver = { |
529 | .name = XILINX_SPI_NAME, |
530 | .of_match_table = xilinx_spi_of_match, |
531 | }, |
532 | }; |
533 | module_platform_driver(xilinx_spi_driver); |
534 | |
535 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>" ); |
536 | MODULE_DESCRIPTION("Xilinx SPI driver" ); |
537 | MODULE_LICENSE("GPL" ); |
538 | |