1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Universal Flash Storage Host controller driver Core
4	* Copyright (C) 2011-2013 Samsung India Software Operations
5	* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6	*
7	* Authors:
8	* Santosh Yaraganavi <santosh.sy@samsung.com>
9	* Vinayak Holikatti <h.vinayak@samsung.com>
10	*/
11
12	#include <linux/async.h>
13	#include <linux/devfreq.h>
14	#include <linux/nls.h>
15	#include <linux/of.h>
16	#include <linux/bitfield.h>
17	#include <linux/blk-pm.h>
18	#include <linux/blkdev.h>
19	#include <linux/clk.h>
20	#include <linux/delay.h>
21	#include <linux/interrupt.h>
22	#include <linux/module.h>
23	#include <linux/pm_opp.h>
24	#include <linux/regulator/consumer.h>
25	#include <linux/sched/clock.h>
26	#include <linux/iopoll.h>
27	#include <scsi/scsi_cmnd.h>
28	#include <scsi/scsi_dbg.h>
29	#include <scsi/scsi_driver.h>
30	#include <scsi/scsi_eh.h>
31	#include <scsi/scsi_tcq.h>
32	#include "ufshcd-priv.h"
33	#include <ufs/ufs_quirks.h>
34	#include <ufs/unipro.h>
35	#include "ufs-sysfs.h"
36	#include "ufs-debugfs.h"
37	#include "ufs-fault-injection.h"
38	#include "ufs_bsg.h"
39	#include "ufshcd-crypto.h"
40	#include <linux/unaligned.h>
41
42	#define CREATE_TRACE_POINTS
43	#include "ufs_trace.h"
44
45	#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
46	UTP_TASK_REQ_COMPL |\
47	UFSHCD_ERROR_MASK)
48
49	/* UIC command timeout, unit: ms */
50	enum {
51	UIC_CMD_TIMEOUT_DEFAULT = 500,
52	UIC_CMD_TIMEOUT_MAX = 5000,
53	};
54	/* NOP OUT retries waiting for NOP IN response */
55	#define NOP_OUT_RETRIES 10
56	/* Timeout after 50 msecs if NOP OUT hangs without response */
57	#define NOP_OUT_TIMEOUT 50 /* msecs */
58
59	/* Query request retries */
60	#define QUERY_REQ_RETRIES 3
61	/* Query request timeout */
62	enum {
63	QUERY_REQ_TIMEOUT_MIN = 1,
64	QUERY_REQ_TIMEOUT_DEFAULT = 1500,
65	QUERY_REQ_TIMEOUT_MAX = 30000
66	};
67
68	/* Advanced RPMB request timeout */
69	#define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */
70
71	/* Task management command timeout */
72	#define TM_CMD_TIMEOUT 100 /* msecs */
73
74	/* maximum number of retries for a general UIC command */
75	#define UFS_UIC_COMMAND_RETRIES 3
76
77	/* maximum number of link-startup retries */
78	#define DME_LINKSTARTUP_RETRIES 3
79
80	/* maximum number of reset retries before giving up */
81	#define MAX_HOST_RESET_RETRIES 5
82
83	/* Maximum number of error handler retries before giving up */
84	#define MAX_ERR_HANDLER_RETRIES 5
85
86	/* Expose the flag value from utp_upiu_query.value */
87	#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
88
89	/* Interrupt aggregation default timeout, unit: 40us */
90	#define INT_AGGR_DEF_TO 0x02
91
92	/* default delay of autosuspend: 2000 ms */
93	#define RPM_AUTOSUSPEND_DELAY_MS 2000
94
95	/* Default delay of RPM device flush delayed work */
96	#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
97
98	/* Default value of wait time before gating device ref clock */
99	#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
100
101	/* Polling time to wait for fDeviceInit */
102	#define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
103
104	/* Default RTC update every 10 seconds */
105	#define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC)
106
107	/* bMaxNumOfRTT is equal to two after device manufacturing */
108	#define DEFAULT_MAX_NUM_RTT 2
109
110	/* UFSHC 4.0 compliant HC support this mode. */
111	static bool use_mcq_mode = true;
112
113	static bool is_mcq_supported(struct ufs_hba *hba)
114	{
115	return hba->mcq_sup && use_mcq_mode;
116	}
117
118	module_param(use_mcq_mode, bool, 0644);
119	MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default");
120
121	static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT;
122
123	static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp)
124	{
125	return param_set_uint_minmax(val, kp, min: UIC_CMD_TIMEOUT_DEFAULT,
126	max: UIC_CMD_TIMEOUT_MAX);
127	}
128
129	static const struct kernel_param_ops uic_cmd_timeout_ops = {
130	.set = uic_cmd_timeout_set,
131	.get = param_get_uint,
132	};
133
134	module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644);
135	MODULE_PARM_DESC(uic_cmd_timeout,
136	"UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 5 seconds inclusively");
137
138	static unsigned int dev_cmd_timeout = QUERY_REQ_TIMEOUT_DEFAULT;
139
140	static int dev_cmd_timeout_set(const char *val, const struct kernel_param *kp)
141	{
142	return param_set_uint_minmax(val, kp, min: QUERY_REQ_TIMEOUT_MIN,
143	max: QUERY_REQ_TIMEOUT_MAX);
144	}
145
146	static const struct kernel_param_ops dev_cmd_timeout_ops = {
147	.set = dev_cmd_timeout_set,
148	.get = param_get_uint,
149	};
150
151	module_param_cb(dev_cmd_timeout, &dev_cmd_timeout_ops, &dev_cmd_timeout, 0644);
152	MODULE_PARM_DESC(dev_cmd_timeout,
153	"UFS Device command timeout in milliseconds. Defaults to 1.5s. Supported values range from 1ms to 30 seconds inclusively");
154
155	#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
156	({ \
157	int _ret; \
158	if (_on) \
159	_ret = ufshcd_enable_vreg(_dev, _vreg); \
160	else \
161	_ret = ufshcd_disable_vreg(_dev, _vreg); \
162	_ret; \
163	})
164
165	#define ufshcd_hex_dump(prefix_str, buf, len) do { \
166	size_t __len = (len); \
167	print_hex_dump(KERN_ERR, prefix_str, \
168	__len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
169	16, 4, buf, __len, false); \
170	} while (0)
171
172	int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
173	const char *prefix)
174	{
175	u32 *regs;
176	size_t pos;
177
178	if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
179	return -EINVAL;
180
181	regs = kzalloc(len, GFP_ATOMIC);
182	if (!regs)
183	return -ENOMEM;
184
185	for (pos = 0; pos < len; pos += 4) {
186	if (offset == 0 &&
187	pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
188	pos <= REG_UIC_ERROR_CODE_DME)
189	continue;
190	regs[pos / 4] = ufshcd_readl(hba, offset + pos);
191	}
192
193	ufshcd_hex_dump(prefix, regs, len);
194	kfree(objp: regs);
195
196	return 0;
197	}
198	EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
199
200	enum {
201	UFSHCD_MAX_CHANNEL = 0,
202	UFSHCD_MAX_ID = 1,
203	};
204
205	static const char *const ufshcd_state_name[] = {
206	[UFSHCD_STATE_RESET] = "reset",
207	[UFSHCD_STATE_OPERATIONAL] = "operational",
208	[UFSHCD_STATE_ERROR] = "error",
209	[UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
210	[UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
211	};
212
213	/* UFSHCD error handling flags */
214	enum {
215	UFSHCD_EH_IN_PROGRESS = (1 << 0),
216	};
217
218	/* UFSHCD UIC layer error flags */
219	enum {
220	UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
221	UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
222	UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
223	UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
224	UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
225	UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
226	UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
227	};
228
229	#define ufshcd_set_eh_in_progress(h) \
230	((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
231	#define ufshcd_eh_in_progress(h) \
232	((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
233	#define ufshcd_clear_eh_in_progress(h) \
234	((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
235
236	const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
237	[UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
238	[UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
239	[UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
240	[UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
241	[UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
242	[UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
243	/*
244	* For DeepSleep, the link is first put in hibern8 and then off.
245	* Leaving the link in hibern8 is not supported.
246	*/
247	[UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
248	};
249
250	static inline enum ufs_dev_pwr_mode
251	ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
252	{
253	return ufs_pm_lvl_states[lvl].dev_state;
254	}
255
256	static inline enum uic_link_state
257	ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
258	{
259	return ufs_pm_lvl_states[lvl].link_state;
260	}
261
262	static inline enum ufs_pm_level
263	ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
264	enum uic_link_state link_state)
265	{
266	enum ufs_pm_level lvl;
267
268	for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
269	if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
270	(ufs_pm_lvl_states[lvl].link_state == link_state))
271	return lvl;
272	}
273
274	/* if no match found, return the level 0 */
275	return UFS_PM_LVL_0;
276	}
277
278	static bool ufshcd_has_pending_tasks(struct ufs_hba *hba)
279	{
280	return hba->outstanding_tasks || hba->active_uic_cmd ||
281	hba->uic_async_done;
282	}
283
284	static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba)
285	{
286	return scsi_host_busy(shost: hba->host) || ufshcd_has_pending_tasks(hba);
287	}
288
289	static const struct ufs_dev_quirk ufs_fixups[] = {
290	/* UFS cards deviations table */
291	{ .wmanufacturerid = UFS_VENDOR_MICRON,
292	.model = UFS_ANY_MODEL,
293	.quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
294	{ .wmanufacturerid = UFS_VENDOR_SAMSUNG,
295	.model = UFS_ANY_MODEL,
296	.quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
297	UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
298	UFS_DEVICE_QUIRK_PA_HIBER8TIME |
299	UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
300	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
301	.model = UFS_ANY_MODEL,
302	.quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
303	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
304	.model = "hB8aL1" /*H28U62301AMR*/,
305	.quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
306	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
307	.model = UFS_ANY_MODEL,
308	.quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
309	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
310	.model = "THGLF2G9C8KBADG",
311	.quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
312	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
313	.model = "THGLF2G9D8KBADG",
314	.quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
315	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
316	.model = "THGJFJT1E45BATP",
317	.quirk = UFS_DEVICE_QUIRK_NO_TIMESTAMP_SUPPORT },
318	{}
319	};
320
321	static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
322	static void ufshcd_async_scan(void *data, async_cookie_t cookie);
323	static int ufshcd_reset_and_restore(struct ufs_hba *hba);
324	static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
325	static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
326	static void ufshcd_hba_exit(struct ufs_hba *hba);
327	static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params);
328	static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
329	static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
330	static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
331	static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
332	static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
333	static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
334	static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
335	bool scale_up);
336	static irqreturn_t ufshcd_intr(int irq, void *__hba);
337	static int ufshcd_change_power_mode(struct ufs_hba *hba,
338	struct ufs_pa_layer_attr *pwr_mode);
339	static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
340	static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
341	static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
342	struct ufs_vreg *vreg);
343	static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
344	bool enable);
345	static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
346	static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
347
348	void ufshcd_enable_irq(struct ufs_hba *hba)
349	{
350	if (!hba->is_irq_enabled) {
351	enable_irq(irq: hba->irq);
352	hba->is_irq_enabled = true;
353	}
354	}
355	EXPORT_SYMBOL_GPL(ufshcd_enable_irq);
356
357	void ufshcd_disable_irq(struct ufs_hba *hba)
358	{
359	if (hba->is_irq_enabled) {
360	disable_irq(irq: hba->irq);
361	hba->is_irq_enabled = false;
362	}
363	}
364	EXPORT_SYMBOL_GPL(ufshcd_disable_irq);
365
366	/**
367	* ufshcd_enable_intr - enable interrupts
368	* @hba: per adapter instance
369	* @intrs: interrupt bits
370	*/
371	void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
372	{
373	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
374	u32 new_val = old_val | intrs;
375
376	if (new_val != old_val)
377	ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
378	}
379
380	/**
381	* ufshcd_disable_intr - disable interrupts
382	* @hba: per adapter instance
383	* @intrs: interrupt bits
384	*/
385	static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
386	{
387	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
388	u32 new_val = old_val & ~intrs;
389
390	if (new_val != old_val)
391	ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
392	}
393
394	static void ufshcd_configure_wb(struct ufs_hba *hba)
395	{
396	if (!ufshcd_is_wb_allowed(hba))
397	return;
398
399	ufshcd_wb_toggle(hba, enable: true);
400
401	ufshcd_wb_toggle_buf_flush_during_h8(hba, enable: true);
402
403	if (ufshcd_is_wb_buf_flush_allowed(hba))
404	ufshcd_wb_toggle_buf_flush(hba, enable: true);
405	}
406
407	static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba,
408	struct ufshcd_lrb *lrb,
409	enum ufs_trace_str_t str_t)
410	{
411	struct utp_upiu_req *rq = lrb->ucd_req_ptr;
412	struct utp_upiu_header *header;
413
414	if (!trace_ufshcd_upiu_enabled())
415	return;
416
417	if (str_t == UFS_CMD_SEND)
418	header = &rq->header;
419	else
420	header = &lrb->ucd_rsp_ptr->header;
421
422	trace_ufshcd_upiu(hba, str_t, hdr: header, tsf: &rq->sc.cdb,
423	tsf_t: UFS_TSF_CDB);
424	}
425
426	static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
427	enum ufs_trace_str_t str_t,
428	struct utp_upiu_req *rq_rsp)
429	{
430	if (!trace_ufshcd_upiu_enabled())
431	return;
432
433	trace_ufshcd_upiu(hba, str_t, hdr: &rq_rsp->header,
434	tsf: &rq_rsp->qr, tsf_t: UFS_TSF_OSF);
435	}
436
437	static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
438	enum ufs_trace_str_t str_t)
439	{
440	struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
441
442	if (!trace_ufshcd_upiu_enabled())
443	return;
444
445	if (str_t == UFS_TM_SEND)
446	trace_ufshcd_upiu(hba, str_t,
447	hdr: &descp->upiu_req.req_header,
448	tsf: &descp->upiu_req.input_param1,
449	tsf_t: UFS_TSF_TM_INPUT);
450	else
451	trace_ufshcd_upiu(hba, str_t,
452	hdr: &descp->upiu_rsp.rsp_header,
453	tsf: &descp->upiu_rsp.output_param1,
454	tsf_t: UFS_TSF_TM_OUTPUT);
455	}
456
457	static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
458	const struct uic_command *ucmd,
459	enum ufs_trace_str_t str_t)
460	{
461	u32 cmd;
462
463	if (!trace_ufshcd_uic_command_enabled())
464	return;
465
466	if (str_t == UFS_CMD_SEND)
467	cmd = ucmd->command;
468	else
469	cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
470
471	trace_ufshcd_uic_command(hba, str_t, cmd,
472	ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
473	ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
474	ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
475	}
476
477	static void ufshcd_add_command_trace(struct ufs_hba *hba, struct scsi_cmnd *cmd,
478	enum ufs_trace_str_t str_t)
479	{
480	u64 lba = 0;
481	u8 opcode = 0, group_id = 0;
482	u32 doorbell = 0;
483	u32 intr;
484	u32 hwq_id = 0;
485	struct request *rq = scsi_cmd_to_rq(scmd: cmd);
486	unsigned int tag = rq->tag;
487	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
488	int transfer_len = -1;
489
490	/* trace UPIU also */
491	ufshcd_add_cmd_upiu_trace(hba, lrb: lrbp, str_t);
492	if (!trace_ufshcd_command_enabled())
493	return;
494
495	opcode = cmd->cmnd[0];
496
497	if (opcode == READ_10 || opcode == WRITE_10) {
498	/*
499	* Currently we only fully trace read(10) and write(10) commands
500	*/
501	transfer_len =
502	be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
503	lba = scsi_get_lba(scmd: cmd);
504	if (opcode == WRITE_10)
505	group_id = cmd->cmnd[6];
506	} else if (opcode == UNMAP) {
507	/*
508	* The number of Bytes to be unmapped beginning with the lba.
509	*/
510	transfer_len = blk_rq_bytes(rq);
511	lba = scsi_get_lba(scmd: cmd);
512	}
513
514	intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
515
516	if (hba->mcq_enabled) {
517	struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, req: rq);
518
519	hwq_id = hwq->id;
520	} else {
521	doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
522	}
523	trace_ufshcd_command(sdev: cmd->device, hba, str_t, tag, doorbell, hwq_id,
524	transfer_len, intr, lba, opcode, group_id);
525	}
526
527	static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
528	{
529	struct ufs_clk_info *clki;
530	struct list_head *head = &hba->clk_list_head;
531
532	if (list_empty(head))
533	return;
534
535	list_for_each_entry(clki, head, list) {
536	if (!IS_ERR_OR_NULL(ptr: clki->clk) && clki->min_freq &&
537	clki->max_freq)
538	dev_err(hba->dev, "clk: %s, rate: %u\n",
539	clki->name, clki->curr_freq);
540	}
541	}
542
543	static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
544	const char *err_name)
545	{
546	int i;
547	bool found = false;
548	const struct ufs_event_hist *e;
549
550	if (id >= UFS_EVT_CNT)
551	return;
552
553	e = &hba->ufs_stats.event[id];
554
555	for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
556	int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
557
558	if (e->tstamp[p] == 0)
559	continue;
560	dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
561	e->val[p], div_u64(e->tstamp[p], 1000));
562	found = true;
563	}
564
565	if (!found)
566	dev_err(hba->dev, "No record of %s\n", err_name);
567	else
568	dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
569	}
570
571	static void ufshcd_print_evt_hist(struct ufs_hba *hba)
572	{
573	ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
574
575	ufshcd_print_evt(hba, id: UFS_EVT_PA_ERR, err_name: "pa_err");
576	ufshcd_print_evt(hba, id: UFS_EVT_DL_ERR, err_name: "dl_err");
577	ufshcd_print_evt(hba, id: UFS_EVT_NL_ERR, err_name: "nl_err");
578	ufshcd_print_evt(hba, id: UFS_EVT_TL_ERR, err_name: "tl_err");
579	ufshcd_print_evt(hba, id: UFS_EVT_DME_ERR, err_name: "dme_err");
580	ufshcd_print_evt(hba, id: UFS_EVT_AUTO_HIBERN8_ERR,
581	err_name: "auto_hibern8_err");
582	ufshcd_print_evt(hba, id: UFS_EVT_FATAL_ERR, err_name: "fatal_err");
583	ufshcd_print_evt(hba, id: UFS_EVT_LINK_STARTUP_FAIL,
584	err_name: "link_startup_fail");
585	ufshcd_print_evt(hba, id: UFS_EVT_RESUME_ERR, err_name: "resume_fail");
586	ufshcd_print_evt(hba, id: UFS_EVT_SUSPEND_ERR,
587	err_name: "suspend_fail");
588	ufshcd_print_evt(hba, id: UFS_EVT_WL_RES_ERR, err_name: "wlun resume_fail");
589	ufshcd_print_evt(hba, id: UFS_EVT_WL_SUSP_ERR,
590	err_name: "wlun suspend_fail");
591	ufshcd_print_evt(hba, id: UFS_EVT_DEV_RESET, err_name: "dev_reset");
592	ufshcd_print_evt(hba, id: UFS_EVT_HOST_RESET, err_name: "host_reset");
593	ufshcd_print_evt(hba, id: UFS_EVT_ABORT, err_name: "task_abort");
594
595	ufshcd_vops_dbg_register_dump(hba);
596	}
597
598	static void ufshcd_print_tr(struct ufs_hba *hba, struct scsi_cmnd *cmd,
599	bool pr_prdt)
600	{
601	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
602	const int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
603	int prdt_length;
604
605	if (hba->monitor.enabled) {
606	dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", tag,
607	div_u64(lrbp->issue_time_stamp_local_clock, 1000));
608	dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", tag,
609	div_u64(lrbp->compl_time_stamp_local_clock, 1000));
610	}
611	dev_err(hba->dev,
612	"UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
613	tag, (u64)lrbp->utrd_dma_addr);
614
615	ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
616	sizeof(struct utp_transfer_req_desc));
617	dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
618	(u64)lrbp->ucd_req_dma_addr);
619	ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
620	sizeof(struct utp_upiu_req));
621	dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
622	(u64)lrbp->ucd_rsp_dma_addr);
623	ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
624	sizeof(struct utp_upiu_rsp));
625
626	prdt_length = le16_to_cpu(
627	lrbp->utr_descriptor_ptr->prd_table_length);
628	if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
629	prdt_length /= ufshcd_sg_entry_size(hba);
630
631	dev_err(hba->dev,
632	"UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
633	tag, prdt_length,
634	(u64)lrbp->ucd_prdt_dma_addr);
635
636	if (pr_prdt)
637	ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
638	ufshcd_sg_entry_size(hba) * prdt_length);
639	}
640
641	static bool ufshcd_print_tr_iter(struct request *req, void *priv)
642	{
643	struct scsi_device *sdev = req->q->queuedata;
644	struct Scsi_Host *shost = sdev->host;
645	struct ufs_hba *hba = shost_priv(shost);
646
647	if (!blk_mq_is_reserved_rq(rq: req))
648	ufshcd_print_tr(hba, cmd: blk_mq_rq_to_pdu(rq: req), pr_prdt: *(bool *)priv);
649
650	return true;
651	}
652
653	/**
654	* ufshcd_print_trs_all - print trs for all started requests.
655	* @hba: per-adapter instance.
656	* @pr_prdt: need to print prdt or not.
657	*/
658	static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt)
659	{
660	blk_mq_tagset_busy_iter(tagset: &hba->host->tag_set, fn: ufshcd_print_tr_iter, priv: &pr_prdt);
661	}
662
663	static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
664	{
665	int tag;
666
667	for_each_set_bit(tag, &bitmap, hba->nutmrs) {
668	struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
669
670	dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
671	ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
672	}
673	}
674
675	static void ufshcd_print_host_state(struct ufs_hba *hba)
676	{
677	const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
678
679	dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
680	dev_err(hba->dev, "%d outstanding reqs, tasks=0x%lx\n",
681	scsi_host_busy(hba->host), hba->outstanding_tasks);
682	dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
683	hba->saved_err, hba->saved_uic_err);
684	dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
685	hba->curr_dev_pwr_mode, hba->uic_link_state);
686	dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
687	hba->pm_op_in_progress, hba->is_sys_suspended);
688	dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
689	hba->auto_bkops_enabled, hba->host->host_self_blocked);
690	dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
691	dev_err(hba->dev,
692	"last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
693	div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
694	hba->ufs_stats.hibern8_exit_cnt);
695	dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
696	hba->eh_flags, hba->req_abort_count);
697	dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
698	hba->ufs_version, hba->capabilities, hba->caps);
699	dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
700	hba->dev_quirks);
701	if (sdev_ufs)
702	dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
703	sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
704
705	ufshcd_print_clk_freqs(hba);
706	}
707
708	/**
709	* ufshcd_print_pwr_info - print power params as saved in hba
710	* power info
711	* @hba: per-adapter instance
712	*/
713	static void ufshcd_print_pwr_info(struct ufs_hba *hba)
714	{
715	static const char * const names[] = {
716	"INVALID MODE",
717	"FAST MODE",
718	"SLOW_MODE",
719	"INVALID MODE",
720	"FASTAUTO_MODE",
721	"SLOWAUTO_MODE",
722	"INVALID MODE",
723	};
724
725	/*
726	* Using dev_dbg to avoid messages during runtime PM to avoid
727	* never-ending cycles of messages written back to storage by user space
728	* causing runtime resume, causing more messages and so on.
729	*/
730	dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
731	__func__,
732	hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
733	hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
734	names[hba->pwr_info.pwr_rx],
735	names[hba->pwr_info.pwr_tx],
736	hba->pwr_info.hs_rate);
737	}
738
739	static void ufshcd_device_reset(struct ufs_hba *hba)
740	{
741	int err;
742
743	err = ufshcd_vops_device_reset(hba);
744
745	if (!err) {
746	ufshcd_set_ufs_dev_active(hba);
747	if (ufshcd_is_wb_allowed(hba)) {
748	hba->dev_info.wb_enabled = false;
749	hba->dev_info.wb_buf_flush_enabled = false;
750	}
751	if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE)
752	hba->dev_info.rtc_time_baseline = 0;
753	}
754	if (err != -EOPNOTSUPP)
755	ufshcd_update_evt_hist(hba, id: UFS_EVT_DEV_RESET, val: err);
756	}
757
758	void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
759	{
760	if (!us)
761	return;
762
763	if (us < 10)
764	udelay(usec: us);
765	else
766	usleep_range(min: us, max: us + tolerance);
767	}
768	EXPORT_SYMBOL_GPL(ufshcd_delay_us);
769
770	/**
771	* ufshcd_wait_for_register - wait for register value to change
772	* @hba: per-adapter interface
773	* @reg: mmio register offset
774	* @mask: mask to apply to the read register value
775	* @val: value to wait for
776	* @interval_us: polling interval in microseconds
777	* @timeout_ms: timeout in milliseconds
778	*
779	* Return: -ETIMEDOUT on error, zero on success.
780	*/
781	static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
782	u32 val, unsigned long interval_us,
783	unsigned long timeout_ms)
784	{
785	u32 v;
786
787	val &= mask; /* ignore bits that we don't intend to wait on */
788
789	return read_poll_timeout(ufshcd_readl, v, (v & mask) == val,
790	interval_us, timeout_ms * 1000, false, hba, reg);
791	}
792
793	/**
794	* ufshcd_get_intr_mask - Get the interrupt bit mask
795	* @hba: Pointer to adapter instance
796	*
797	* Return: interrupt bit mask per version
798	*/
799	static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
800	{
801	if (hba->ufs_version <= ufshci_version(major: 2, minor: 0))
802	return INTERRUPT_MASK_ALL_VER_11;
803
804	return INTERRUPT_MASK_ALL_VER_21;
805	}
806
807	/**
808	* ufshcd_get_ufs_version - Get the UFS version supported by the HBA
809	* @hba: Pointer to adapter instance
810	*
811	* Return: UFSHCI version supported by the controller
812	*/
813	static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
814	{
815	u32 ufshci_ver;
816
817	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
818	ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
819	else
820	ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
821
822	/*
823	* UFSHCI v1.x uses a different version scheme, in order
824	* to allow the use of comparisons with the ufshci_version
825	* function, we convert it to the same scheme as ufs 2.0+.
826	*/
827	if (ufshci_ver & 0x00010000)
828	return ufshci_version(major: 1, minor: ufshci_ver & 0x00000100);
829
830	return ufshci_ver;
831	}
832
833	/**
834	* ufshcd_is_device_present - Check if any device connected to
835	* the host controller
836	* @hba: pointer to adapter instance
837	*
838	* Return: true if device present, false if no device detected
839	*/
840	static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
841	{
842	return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
843	}
844
845	/**
846	* ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
847	* @lrbp: pointer to local command reference block
848	* @cqe: pointer to the completion queue entry
849	*
850	* This function is used to get the OCS field from UTRD
851	*
852	* Return: the OCS field in the UTRD.
853	*/
854	static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp,
855	struct cq_entry *cqe)
856	{
857	if (cqe)
858	return cqe->overall_status & MASK_OCS;
859
860	return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS;
861	}
862
863	/**
864	* ufshcd_utrl_clear() - Clear requests from the controller request list.
865	* @hba: per adapter instance
866	* @mask: mask with one bit set for each request to be cleared
867	*/
868	static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
869	{
870	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
871	mask = ~mask;
872	/*
873	* From the UFSHCI specification: "UTP Transfer Request List CLear
874	* Register (UTRLCLR): This field is bit significant. Each bit
875	* corresponds to a slot in the UTP Transfer Request List, where bit 0
876	* corresponds to request slot 0. A bit in this field is set to ‘0’
877	* by host software to indicate to the host controller that a transfer
878	* request slot is cleared. The host controller
879	* shall free up any resources associated to the request slot
880	* immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
881	* host software indicates no change to request slots by setting the
882	* associated bits in this field to ‘1’. Bits in this field shall only
883	* be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
884	*/
885	ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
886	}
887
888	/**
889	* ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
890	* @hba: per adapter instance
891	* @pos: position of the bit to be cleared
892	*/
893	static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
894	{
895	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
896	ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
897	else
898	ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
899	}
900
901	/**
902	* ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
903	* @reg: Register value of host controller status
904	*
905	* Return: 0 on success; a positive value if failed.
906	*/
907	static inline int ufshcd_get_lists_status(u32 reg)
908	{
909	return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
910	}
911
912	/**
913	* ufshcd_get_uic_cmd_result - Get the UIC command result
914	* @hba: Pointer to adapter instance
915	*
916	* This function gets the result of UIC command completion
917	*
918	* Return: 0 on success; non-zero value on error.
919	*/
920	static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
921	{
922	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
923	MASK_UIC_COMMAND_RESULT;
924	}
925
926	/**
927	* ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
928	* @hba: Pointer to adapter instance
929	*
930	* This function gets UIC command argument3
931	*
932	* Return: 0 on success; non-zero value on error.
933	*/
934	static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
935	{
936	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
937	}
938
939	/**
940	* ufshcd_get_req_rsp - returns the TR response transaction type
941	* @ucd_rsp_ptr: pointer to response UPIU
942	*
943	* Return: UPIU type.
944	*/
945	static inline enum upiu_response_transaction
946	ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
947	{
948	return ucd_rsp_ptr->header.transaction_code;
949	}
950
951	/**
952	* ufshcd_is_exception_event - Check if the device raised an exception event
953	* @ucd_rsp_ptr: pointer to response UPIU
954	*
955	* The function checks if the device raised an exception event indicated in
956	* the Device Information field of response UPIU.
957	*
958	* Return: true if exception is raised, false otherwise.
959	*/
960	static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
961	{
962	return ucd_rsp_ptr->header.device_information & 1;
963	}
964
965	/**
966	* ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
967	* @hba: per adapter instance
968	*/
969	static inline void
970	ufshcd_reset_intr_aggr(struct ufs_hba *hba)
971	{
972	ufshcd_writel(hba, INT_AGGR_ENABLE |
973	INT_AGGR_COUNTER_AND_TIMER_RESET,
974	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
975	}
976
977	/**
978	* ufshcd_config_intr_aggr - Configure interrupt aggregation values.
979	* @hba: per adapter instance
980	* @cnt: Interrupt aggregation counter threshold
981	* @tmout: Interrupt aggregation timeout value
982	*/
983	static inline void
984	ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
985	{
986	ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
987	INT_AGGR_COUNTER_THLD_VAL(cnt) |
988	INT_AGGR_TIMEOUT_VAL(tmout),
989	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
990	}
991
992	/**
993	* ufshcd_disable_intr_aggr - Disables interrupt aggregation.
994	* @hba: per adapter instance
995	*/
996	static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
997	{
998	ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
999	}
1000
1001	/**
1002	* ufshcd_enable_run_stop_reg - Enable run-stop registers,
1003	* When run-stop registers are set to 1, it indicates the
1004	* host controller that it can process the requests
1005	* @hba: per adapter instance
1006	*/
1007	static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
1008	{
1009	ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
1010	REG_UTP_TASK_REQ_LIST_RUN_STOP);
1011	ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
1012	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
1013	}
1014
1015	/**
1016	* ufshcd_hba_start - Start controller initialization sequence
1017	* @hba: per adapter instance
1018	*/
1019	static inline void ufshcd_hba_start(struct ufs_hba *hba)
1020	{
1021	u32 val = CONTROLLER_ENABLE;
1022
1023	if (ufshcd_crypto_enable(hba))
1024	val |= CRYPTO_GENERAL_ENABLE;
1025
1026	ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
1027	}
1028
1029	/**
1030	* ufshcd_is_hba_active - Get controller state
1031	* @hba: per adapter instance
1032	*
1033	* Return: true if and only if the controller is active.
1034	*/
1035	bool ufshcd_is_hba_active(struct ufs_hba *hba)
1036	{
1037	return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
1038	}
1039	EXPORT_SYMBOL_GPL(ufshcd_is_hba_active);
1040
1041	/**
1042	* ufshcd_pm_qos_init - initialize PM QoS request
1043	* @hba: per adapter instance
1044	*/
1045	void ufshcd_pm_qos_init(struct ufs_hba *hba)
1046	{
1047	guard(mutex)(T: &hba->pm_qos_mutex);
1048
1049	if (hba->pm_qos_enabled)
1050	return;
1051
1052	cpu_latency_qos_add_request(req: &hba->pm_qos_req, PM_QOS_DEFAULT_VALUE);
1053
1054	if (cpu_latency_qos_request_active(req: &hba->pm_qos_req))
1055	hba->pm_qos_enabled = true;
1056	}
1057
1058	/**
1059	* ufshcd_pm_qos_exit - remove request from PM QoS
1060	* @hba: per adapter instance
1061	*/
1062	void ufshcd_pm_qos_exit(struct ufs_hba *hba)
1063	{
1064	guard(mutex)(T: &hba->pm_qos_mutex);
1065
1066	if (!hba->pm_qos_enabled)
1067	return;
1068
1069	cpu_latency_qos_remove_request(req: &hba->pm_qos_req);
1070	hba->pm_qos_enabled = false;
1071	}
1072
1073	/**
1074	* ufshcd_pm_qos_update - update PM QoS request
1075	* @hba: per adapter instance
1076	* @on: If True, vote for perf PM QoS mode otherwise power save mode
1077	*/
1078	void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on)
1079	{
1080	guard(mutex)(T: &hba->pm_qos_mutex);
1081
1082	if (!hba->pm_qos_enabled)
1083	return;
1084
1085	cpu_latency_qos_update_request(req: &hba->pm_qos_req, new_value: on ? 0 : PM_QOS_DEFAULT_VALUE);
1086	}
1087	EXPORT_SYMBOL_GPL(ufshcd_pm_qos_update);
1088
1089	/**
1090	* ufshcd_set_clk_freq - set UFS controller clock frequencies
1091	* @hba: per adapter instance
1092	* @scale_up: If True, set max possible frequency othewise set low frequency
1093	*
1094	* Return: 0 if successful; < 0 upon failure.
1095	*/
1096	static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
1097	{
1098	int ret = 0;
1099	struct ufs_clk_info *clki;
1100	struct list_head *head = &hba->clk_list_head;
1101
1102	if (list_empty(head))
1103	goto out;
1104
1105	list_for_each_entry(clki, head, list) {
1106	if (!IS_ERR_OR_NULL(ptr: clki->clk)) {
1107	if (scale_up && clki->max_freq) {
1108	if (clki->curr_freq == clki->max_freq)
1109	continue;
1110
1111	ret = clk_set_rate(clk: clki->clk, rate: clki->max_freq);
1112	if (ret) {
1113	dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1114	__func__, clki->name,
1115	clki->max_freq, ret);
1116	break;
1117	}
1118	trace_ufshcd_clk_scaling(hba,
1119	state: "scaled up", clk: clki->name,
1120	prev_state: clki->curr_freq,
1121	curr_state: clki->max_freq);
1122
1123	clki->curr_freq = clki->max_freq;
1124
1125	} else if (!scale_up && clki->min_freq) {
1126	if (clki->curr_freq == clki->min_freq)
1127	continue;
1128
1129	ret = clk_set_rate(clk: clki->clk, rate: clki->min_freq);
1130	if (ret) {
1131	dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1132	__func__, clki->name,
1133	clki->min_freq, ret);
1134	break;
1135	}
1136	trace_ufshcd_clk_scaling(hba,
1137	state: "scaled down", clk: clki->name,
1138	prev_state: clki->curr_freq,
1139	curr_state: clki->min_freq);
1140	clki->curr_freq = clki->min_freq;
1141	}
1142	}
1143	dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1144	clki->name, clk_get_rate(clki->clk));
1145	}
1146
1147	out:
1148	return ret;
1149	}
1150
1151	int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1152	struct dev_pm_opp *opp, void *data,
1153	bool scaling_down)
1154	{
1155	struct ufs_hba *hba = dev_get_drvdata(dev);
1156	struct list_head *head = &hba->clk_list_head;
1157	struct ufs_clk_info *clki;
1158	unsigned long freq;
1159	u8 idx = 0;
1160	int ret;
1161
1162	list_for_each_entry(clki, head, list) {
1163	if (!IS_ERR_OR_NULL(ptr: clki->clk)) {
1164	freq = dev_pm_opp_get_freq_indexed(opp, index: idx++);
1165
1166	/* Do not set rate for clocks having frequency as 0 */
1167	if (!freq)
1168	continue;
1169
1170	ret = clk_set_rate(clk: clki->clk, rate: freq);
1171	if (ret) {
1172	dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n",
1173	__func__, clki->name, freq, ret);
1174	return ret;
1175	}
1176
1177	trace_ufshcd_clk_scaling(hba,
1178	state: (scaling_down ? "scaled down" : "scaled up"),
1179	clk: clki->name, prev_state: hba->clk_scaling.target_freq, curr_state: freq);
1180	}
1181	}
1182
1183	return 0;
1184	}
1185	EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks);
1186
1187	static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq)
1188	{
1189	struct dev_pm_opp *opp;
1190	int ret;
1191
1192	opp = dev_pm_opp_find_freq_floor_indexed(dev: hba->dev,
1193	freq: &freq, index: 0);
1194	if (IS_ERR(ptr: opp))
1195	return PTR_ERR(ptr: opp);
1196
1197	ret = dev_pm_opp_set_opp(dev: hba->dev, opp);
1198	dev_pm_opp_put(opp);
1199
1200	return ret;
1201	}
1202
1203	/**
1204	* ufshcd_scale_clks - scale up or scale down UFS controller clocks
1205	* @hba: per adapter instance
1206	* @freq: frequency to scale
1207	* @scale_up: True if scaling up and false if scaling down
1208	*
1209	* Return: 0 if successful; < 0 upon failure.
1210	*/
1211	static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
1212	bool scale_up)
1213	{
1214	int ret = 0;
1215	ktime_t start = ktime_get();
1216
1217	ret = ufshcd_vops_clk_scale_notify(hba, up: scale_up, target_freq: freq, status: PRE_CHANGE);
1218	if (ret)
1219	goto out;
1220
1221	if (hba->use_pm_opp)
1222	ret = ufshcd_opp_set_rate(hba, freq);
1223	else
1224	ret = ufshcd_set_clk_freq(hba, scale_up);
1225	if (ret)
1226	goto out;
1227
1228	ret = ufshcd_vops_clk_scale_notify(hba, up: scale_up, target_freq: freq, status: POST_CHANGE);
1229	if (ret) {
1230	if (hba->use_pm_opp)
1231	ufshcd_opp_set_rate(hba,
1232	freq: hba->devfreq->previous_freq);
1233	else
1234	ufshcd_set_clk_freq(hba, scale_up: !scale_up);
1235	goto out;
1236	}
1237
1238	ufshcd_pm_qos_update(hba, scale_up);
1239
1240	out:
1241	trace_ufshcd_profile_clk_scaling(hba,
1242	profile_info: (scale_up ? "up" : "down"),
1243	time_us: ktime_to_us(ktime_sub(ktime_get(), start)), err: ret);
1244	return ret;
1245	}
1246
1247	/**
1248	* ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1249	* @hba: per adapter instance
1250	* @freq: frequency to scale
1251	* @scale_up: True if scaling up and false if scaling down
1252	*
1253	* Return: true if scaling is required, false otherwise.
1254	*/
1255	static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1256	unsigned long freq, bool scale_up)
1257	{
1258	struct ufs_clk_info *clki;
1259	struct list_head *head = &hba->clk_list_head;
1260
1261	if (list_empty(head))
1262	return false;
1263
1264	if (hba->use_pm_opp)
1265	return freq != hba->clk_scaling.target_freq;
1266
1267	list_for_each_entry(clki, head, list) {
1268	if (!IS_ERR_OR_NULL(ptr: clki->clk)) {
1269	if (scale_up && clki->max_freq) {
1270	if (clki->curr_freq == clki->max_freq)
1271	continue;
1272	return true;
1273	} else if (!scale_up && clki->min_freq) {
1274	if (clki->curr_freq == clki->min_freq)
1275	continue;
1276	return true;
1277	}
1278	}
1279	}
1280
1281	return false;
1282	}
1283
1284	/*
1285	* Determine the number of pending commands by counting the bits in the SCSI
1286	* device budget maps. This approach has been selected because a bit is set in
1287	* the budget map before scsi_host_queue_ready() checks the host_self_blocked
1288	* flag. The host_self_blocked flag can be modified by calling
1289	* scsi_block_requests() or scsi_unblock_requests().
1290	*/
1291	static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1292	{
1293	struct scsi_device *sdev;
1294	unsigned long flags;
1295	u32 pending = 0;
1296
1297	spin_lock_irqsave(hba->host->host_lock, flags);
1298	__shost_for_each_device(sdev, hba->host)
1299	pending += scsi_device_busy(sdev);
1300	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
1301
1302	return pending;
1303	}
1304
1305	/*
1306	* Wait until all pending SCSI commands and TMFs have finished or the timeout
1307	* has expired.
1308	*
1309	* Return: 0 upon success; -EBUSY upon timeout.
1310	*/
1311	static int ufshcd_wait_for_pending_cmds(struct ufs_hba *hba,
1312	u64 wait_timeout_us)
1313	{
1314	int ret = 0;
1315	u32 tm_doorbell;
1316	u32 tr_pending;
1317	bool timeout = false, do_last_check = false;
1318	ktime_t start;
1319
1320	ufshcd_hold(hba);
1321	/*
1322	* Wait for all the outstanding tasks/transfer requests.
1323	* Verify by checking the doorbell registers are clear.
1324	*/
1325	start = ktime_get();
1326	do {
1327	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1328	ret = -EBUSY;
1329	goto out;
1330	}
1331
1332	tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1333	tr_pending = ufshcd_pending_cmds(hba);
1334	if (!tm_doorbell && !tr_pending) {
1335	timeout = false;
1336	break;
1337	} else if (do_last_check) {
1338	break;
1339	}
1340
1341	io_schedule_timeout(timeout: msecs_to_jiffies(m: 20));
1342	if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1343	wait_timeout_us) {
1344	timeout = true;
1345	/*
1346	* We might have scheduled out for long time so make
1347	* sure to check if doorbells are cleared by this time
1348	* or not.
1349	*/
1350	do_last_check = true;
1351	}
1352	} while (tm_doorbell || tr_pending);
1353
1354	if (timeout) {
1355	dev_err(hba->dev,
1356	"%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1357	__func__, tm_doorbell, tr_pending);
1358	ret = -EBUSY;
1359	}
1360	out:
1361	ufshcd_release(hba);
1362	return ret;
1363	}
1364
1365	/**
1366	* ufshcd_scale_gear - scale up/down UFS gear
1367	* @hba: per adapter instance
1368	* @target_gear: target gear to scale to
1369	* @scale_up: True for scaling up gear and false for scaling down
1370	*
1371	* Return: 0 for success; -EBUSY if scaling can't happen at this time;
1372	* non-zero for any other errors.
1373	*/
1374	static int ufshcd_scale_gear(struct ufs_hba *hba, u32 target_gear, bool scale_up)
1375	{
1376	int ret = 0;
1377	struct ufs_pa_layer_attr new_pwr_info;
1378
1379	if (target_gear) {
1380	new_pwr_info = hba->pwr_info;
1381	new_pwr_info.gear_tx = target_gear;
1382	new_pwr_info.gear_rx = target_gear;
1383
1384	goto config_pwr_mode;
1385	}
1386
1387	/* Legacy gear scaling, in case vops_freq_to_gear_speed() is not implemented */
1388	if (scale_up) {
1389	memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info,
1390	sizeof(struct ufs_pa_layer_attr));
1391	} else {
1392	memcpy(&new_pwr_info, &hba->pwr_info,
1393	sizeof(struct ufs_pa_layer_attr));
1394
1395	if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1396	hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1397	/* save the current power mode */
1398	memcpy(&hba->clk_scaling.saved_pwr_info,
1399	&hba->pwr_info,
1400	sizeof(struct ufs_pa_layer_attr));
1401
1402	/* scale down gear */
1403	new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1404	new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1405	}
1406	}
1407
1408	config_pwr_mode:
1409	/* check if the power mode needs to be changed or not? */
1410	ret = ufshcd_config_pwr_mode(hba, desired_pwr_mode: &new_pwr_info);
1411	if (ret)
1412	dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1413	__func__, ret,
1414	hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1415	new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1416
1417	return ret;
1418	}
1419
1420	/*
1421	* Wait until all pending SCSI commands and TMFs have finished or the timeout
1422	* has expired.
1423	*
1424	* Return: 0 upon success; -EBUSY upon timeout.
1425	*/
1426	static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
1427	{
1428	int ret = 0;
1429	/*
1430	* make sure that there are no outstanding requests when
1431	* clock scaling is in progress
1432	*/
1433	mutex_lock(&hba->host->scan_mutex);
1434	blk_mq_quiesce_tagset(set: &hba->host->tag_set);
1435	mutex_lock(&hba->wb_mutex);
1436	down_write(sem: &hba->clk_scaling_lock);
1437
1438	if (!hba->clk_scaling.is_allowed ||
1439	ufshcd_wait_for_pending_cmds(hba, wait_timeout_us: timeout_us)) {
1440	ret = -EBUSY;
1441	up_write(sem: &hba->clk_scaling_lock);
1442	mutex_unlock(lock: &hba->wb_mutex);
1443	blk_mq_unquiesce_tagset(set: &hba->host->tag_set);
1444	mutex_unlock(lock: &hba->host->scan_mutex);
1445	goto out;
1446	}
1447
1448	/* let's not get into low power until clock scaling is completed */
1449	ufshcd_hold(hba);
1450
1451	out:
1452	return ret;
1453	}
1454
1455	static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err)
1456	{
1457	up_write(sem: &hba->clk_scaling_lock);
1458	mutex_unlock(lock: &hba->wb_mutex);
1459	blk_mq_unquiesce_tagset(set: &hba->host->tag_set);
1460	mutex_unlock(lock: &hba->host->scan_mutex);
1461
1462	/* Enable Write Booster if current gear requires it else disable it */
1463	if (ufshcd_enable_wb_if_scaling_up(hba) && !err)
1464	ufshcd_wb_toggle(hba, enable: hba->pwr_info.gear_rx >= hba->clk_scaling.wb_gear);
1465
1466	ufshcd_release(hba);
1467	}
1468
1469	/**
1470	* ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1471	* @hba: per adapter instance
1472	* @freq: frequency to scale
1473	* @scale_up: True for scaling up and false for scalin down
1474	*
1475	* Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero
1476	* for any other errors.
1477	*/
1478	static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq,
1479	bool scale_up)
1480	{
1481	u32 old_gear = hba->pwr_info.gear_rx;
1482	u32 new_gear = 0;
1483	int ret = 0;
1484
1485	new_gear = ufshcd_vops_freq_to_gear_speed(hba, freq);
1486
1487	ret = ufshcd_clock_scaling_prepare(hba, timeout_us: 1 * USEC_PER_SEC);
1488	if (ret)
1489	return ret;
1490
1491	/* scale down the gear before scaling down clocks */
1492	if (!scale_up) {
1493	ret = ufshcd_scale_gear(hba, target_gear: new_gear, scale_up: false);
1494	if (ret)
1495	goto out_unprepare;
1496	}
1497
1498	ret = ufshcd_scale_clks(hba, freq, scale_up);
1499	if (ret) {
1500	if (!scale_up)
1501	ufshcd_scale_gear(hba, target_gear: old_gear, scale_up: true);
1502	goto out_unprepare;
1503	}
1504
1505	/* scale up the gear after scaling up clocks */
1506	if (scale_up) {
1507	ret = ufshcd_scale_gear(hba, target_gear: new_gear, scale_up: true);
1508	if (ret) {
1509	ufshcd_scale_clks(hba, freq: hba->devfreq->previous_freq,
1510	scale_up: false);
1511	goto out_unprepare;
1512	}
1513	}
1514
1515	out_unprepare:
1516	ufshcd_clock_scaling_unprepare(hba, err: ret);
1517	return ret;
1518	}
1519
1520	static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1521	{
1522	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1523	clk_scaling.suspend_work);
1524
1525	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1526	{
1527	if (hba->clk_scaling.active_reqs ||
1528	hba->clk_scaling.is_suspended)
1529	return;
1530
1531	hba->clk_scaling.is_suspended = true;
1532	hba->clk_scaling.window_start_t = 0;
1533	}
1534
1535	devfreq_suspend_device(devfreq: hba->devfreq);
1536	}
1537
1538	static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1539	{
1540	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1541	clk_scaling.resume_work);
1542
1543	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1544	{
1545	if (!hba->clk_scaling.is_suspended)
1546	return;
1547	hba->clk_scaling.is_suspended = false;
1548	}
1549
1550	devfreq_resume_device(devfreq: hba->devfreq);
1551	}
1552
1553	static int ufshcd_devfreq_target(struct device *dev,
1554	unsigned long *freq, u32 flags)
1555	{
1556	int ret = 0;
1557	struct ufs_hba *hba = dev_get_drvdata(dev);
1558	ktime_t start;
1559	bool scale_up = false, sched_clk_scaling_suspend_work = false;
1560	struct list_head *clk_list = &hba->clk_list_head;
1561	struct ufs_clk_info *clki;
1562
1563	if (!ufshcd_is_clkscaling_supported(hba))
1564	return -EINVAL;
1565
1566	if (hba->use_pm_opp) {
1567	struct dev_pm_opp *opp;
1568
1569	/* Get the recommended frequency from OPP framework */
1570	opp = devfreq_recommended_opp(dev, freq, flags);
1571	if (IS_ERR(ptr: opp))
1572	return PTR_ERR(ptr: opp);
1573
1574	dev_pm_opp_put(opp);
1575	} else {
1576	/* Override with the closest supported frequency */
1577	clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info,
1578	list);
1579	*freq = (unsigned long) clk_round_rate(clk: clki->clk, rate: *freq);
1580	}
1581
1582	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1583	{
1584	if (ufshcd_eh_in_progress(hba))
1585	return 0;
1586
1587	/* Skip scaling clock when clock scaling is suspended */
1588	if (hba->clk_scaling.is_suspended) {
1589	dev_warn(hba->dev, "clock scaling is suspended, skip");
1590	return 0;
1591	}
1592
1593	if (!hba->clk_scaling.active_reqs)
1594	sched_clk_scaling_suspend_work = true;
1595
1596	if (list_empty(head: clk_list))
1597	goto out;
1598
1599	/* Decide based on the target or rounded-off frequency and update */
1600	if (hba->use_pm_opp)
1601	scale_up = *freq > hba->clk_scaling.target_freq;
1602	else
1603	scale_up = *freq == clki->max_freq;
1604
1605	if (!hba->use_pm_opp && !scale_up)
1606	*freq = clki->min_freq;
1607
1608	/* Update the frequency */
1609	if (!ufshcd_is_devfreq_scaling_required(hba, freq: *freq, scale_up)) {
1610	ret = 0;
1611	goto out; /* no state change required */
1612	}
1613	}
1614
1615	start = ktime_get();
1616	ret = ufshcd_devfreq_scale(hba, freq: *freq, scale_up);
1617	if (!ret)
1618	hba->clk_scaling.target_freq = *freq;
1619
1620	trace_ufshcd_profile_clk_scaling(hba,
1621	profile_info: (scale_up ? "up" : "down"),
1622	time_us: ktime_to_us(ktime_sub(ktime_get(), start)), err: ret);
1623
1624	out:
1625	if (sched_clk_scaling_suspend_work &&
1626	(!scale_up || hba->clk_scaling.suspend_on_no_request))
1627	queue_work(wq: hba->clk_scaling.workq,
1628	work: &hba->clk_scaling.suspend_work);
1629
1630	return ret;
1631	}
1632
1633	static int ufshcd_devfreq_get_dev_status(struct device *dev,
1634	struct devfreq_dev_status *stat)
1635	{
1636	struct ufs_hba *hba = dev_get_drvdata(dev);
1637	struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1638	ktime_t curr_t;
1639
1640	if (!ufshcd_is_clkscaling_supported(hba))
1641	return -EINVAL;
1642
1643	memset(stat, 0, sizeof(*stat));
1644
1645	guard(spinlock_irqsave)(l: &hba->clk_scaling.lock);
1646
1647	curr_t = ktime_get();
1648	if (!scaling->window_start_t)
1649	goto start_window;
1650
1651	/*
1652	* If current frequency is 0, then the ondemand governor considers
1653	* there's no initial frequency set. And it always requests to set
1654	* to max. frequency.
1655	*/
1656	if (hba->use_pm_opp) {
1657	stat->current_frequency = hba->clk_scaling.target_freq;
1658	} else {
1659	struct list_head *clk_list = &hba->clk_list_head;
1660	struct ufs_clk_info *clki;
1661
1662	clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1663	stat->current_frequency = clki->curr_freq;
1664	}
1665
1666	if (scaling->is_busy_started)
1667	scaling->tot_busy_t += ktime_us_delta(later: curr_t,
1668	earlier: scaling->busy_start_t);
1669	stat->total_time = ktime_us_delta(later: curr_t, earlier: scaling->window_start_t);
1670	stat->busy_time = scaling->tot_busy_t;
1671	start_window:
1672	scaling->window_start_t = curr_t;
1673	scaling->tot_busy_t = 0;
1674
1675	if (scaling->active_reqs) {
1676	scaling->busy_start_t = curr_t;
1677	scaling->is_busy_started = true;
1678	} else {
1679	scaling->busy_start_t = 0;
1680	scaling->is_busy_started = false;
1681	}
1682
1683	return 0;
1684	}
1685
1686	static int ufshcd_devfreq_init(struct ufs_hba *hba)
1687	{
1688	struct list_head *clk_list = &hba->clk_list_head;
1689	struct ufs_clk_info *clki;
1690	struct devfreq *devfreq;
1691	int ret;
1692
1693	/* Skip devfreq if we don't have any clocks in the list */
1694	if (list_empty(head: clk_list))
1695	return 0;
1696
1697	if (!hba->use_pm_opp) {
1698	clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1699	dev_pm_opp_add(dev: hba->dev, freq: clki->min_freq, u_volt: 0);
1700	dev_pm_opp_add(dev: hba->dev, freq: clki->max_freq, u_volt: 0);
1701	}
1702
1703	ufshcd_vops_config_scaling_param(hba, p: &hba->vps->devfreq_profile,
1704	data: &hba->vps->ondemand_data);
1705	devfreq = devfreq_add_device(dev: hba->dev,
1706	profile: &hba->vps->devfreq_profile,
1707	DEVFREQ_GOV_SIMPLE_ONDEMAND,
1708	data: &hba->vps->ondemand_data);
1709	if (IS_ERR(ptr: devfreq)) {
1710	ret = PTR_ERR(ptr: devfreq);
1711	dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1712
1713	if (!hba->use_pm_opp) {
1714	dev_pm_opp_remove(dev: hba->dev, freq: clki->min_freq);
1715	dev_pm_opp_remove(dev: hba->dev, freq: clki->max_freq);
1716	}
1717	return ret;
1718	}
1719
1720	hba->devfreq = devfreq;
1721
1722	return 0;
1723	}
1724
1725	static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1726	{
1727	struct list_head *clk_list = &hba->clk_list_head;
1728
1729	if (!hba->devfreq)
1730	return;
1731
1732	devfreq_remove_device(devfreq: hba->devfreq);
1733	hba->devfreq = NULL;
1734
1735	if (!hba->use_pm_opp) {
1736	struct ufs_clk_info *clki;
1737
1738	clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1739	dev_pm_opp_remove(dev: hba->dev, freq: clki->min_freq);
1740	dev_pm_opp_remove(dev: hba->dev, freq: clki->max_freq);
1741	}
1742	}
1743
1744	static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1745	{
1746	bool suspend = false;
1747
1748	cancel_work_sync(work: &hba->clk_scaling.suspend_work);
1749	cancel_work_sync(work: &hba->clk_scaling.resume_work);
1750
1751	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1752	{
1753	if (!hba->clk_scaling.is_suspended) {
1754	suspend = true;
1755	hba->clk_scaling.is_suspended = true;
1756	hba->clk_scaling.window_start_t = 0;
1757	}
1758	}
1759
1760	if (suspend)
1761	devfreq_suspend_device(devfreq: hba->devfreq);
1762	}
1763
1764	static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1765	{
1766	bool resume = false;
1767
1768	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1769	{
1770	if (hba->clk_scaling.is_suspended) {
1771	resume = true;
1772	hba->clk_scaling.is_suspended = false;
1773	}
1774	}
1775
1776	if (resume)
1777	devfreq_resume_device(devfreq: hba->devfreq);
1778	}
1779
1780	static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1781	struct device_attribute *attr, char *buf)
1782	{
1783	struct ufs_hba *hba = dev_get_drvdata(dev);
1784
1785	return sysfs_emit(buf, fmt: "%d\n", hba->clk_scaling.is_enabled);
1786	}
1787
1788	static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1789	struct device_attribute *attr, const char *buf, size_t count)
1790	{
1791	struct ufs_hba *hba = dev_get_drvdata(dev);
1792	struct ufs_clk_info *clki;
1793	unsigned long freq;
1794	u32 value;
1795	int err = 0;
1796
1797	if (kstrtou32(s: buf, base: 0, res: &value))
1798	return -EINVAL;
1799
1800	down(sem: &hba->host_sem);
1801	if (!ufshcd_is_user_access_allowed(hba)) {
1802	err = -EBUSY;
1803	goto out;
1804	}
1805
1806	value = !!value;
1807	if (value == hba->clk_scaling.is_enabled)
1808	goto out;
1809
1810	ufshcd_rpm_get_sync(hba);
1811	ufshcd_hold(hba);
1812
1813	hba->clk_scaling.is_enabled = value;
1814
1815	if (value) {
1816	ufshcd_resume_clkscaling(hba);
1817	goto out_rel;
1818	}
1819
1820	clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1821	freq = clki->max_freq;
1822
1823	ufshcd_suspend_clkscaling(hba);
1824
1825	if (!ufshcd_is_devfreq_scaling_required(hba, freq, scale_up: true))
1826	goto out_rel;
1827
1828	err = ufshcd_devfreq_scale(hba, freq, scale_up: true);
1829	if (err)
1830	dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1831	__func__, err);
1832	else
1833	hba->clk_scaling.target_freq = freq;
1834
1835	out_rel:
1836	ufshcd_release(hba);
1837	ufshcd_rpm_put_sync(hba);
1838	out:
1839	up(sem: &hba->host_sem);
1840	return err ? err : count;
1841	}
1842
1843	static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1844	{
1845	hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1846	hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1847	sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1848	hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1849	hba->clk_scaling.enable_attr.attr.mode = 0644;
1850	if (device_create_file(device: hba->dev, entry: &hba->clk_scaling.enable_attr))
1851	dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1852	}
1853
1854	static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1855	{
1856	if (hba->clk_scaling.enable_attr.attr.name)
1857	device_remove_file(dev: hba->dev, attr: &hba->clk_scaling.enable_attr);
1858	}
1859
1860	static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1861	{
1862	if (!ufshcd_is_clkscaling_supported(hba))
1863	return;
1864
1865	if (!hba->clk_scaling.min_gear)
1866	hba->clk_scaling.min_gear = UFS_HS_G1;
1867
1868	if (!hba->clk_scaling.wb_gear)
1869	/* Use intermediate gear speed HS_G3 as the default wb_gear */
1870	hba->clk_scaling.wb_gear = UFS_HS_G3;
1871
1872	INIT_WORK(&hba->clk_scaling.suspend_work,
1873	ufshcd_clk_scaling_suspend_work);
1874	INIT_WORK(&hba->clk_scaling.resume_work,
1875	ufshcd_clk_scaling_resume_work);
1876
1877	spin_lock_init(&hba->clk_scaling.lock);
1878
1879	hba->clk_scaling.workq = alloc_ordered_workqueue(
1880	"ufs_clkscaling_%d", WQ_MEM_RECLAIM, hba->host->host_no);
1881
1882	hba->clk_scaling.is_initialized = true;
1883	}
1884
1885	static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1886	{
1887	if (!hba->clk_scaling.is_initialized)
1888	return;
1889
1890	ufshcd_remove_clk_scaling_sysfs(hba);
1891	destroy_workqueue(wq: hba->clk_scaling.workq);
1892	ufshcd_devfreq_remove(hba);
1893	hba->clk_scaling.is_initialized = false;
1894	}
1895
1896	static void ufshcd_ungate_work(struct work_struct *work)
1897	{
1898	int ret;
1899	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1900	clk_gating.ungate_work);
1901
1902	cancel_delayed_work_sync(dwork: &hba->clk_gating.gate_work);
1903
1904	scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) {
1905	if (hba->clk_gating.state == CLKS_ON)
1906	return;
1907	}
1908
1909	ufshcd_hba_vreg_set_hpm(hba);
1910	ufshcd_setup_clocks(hba, on: true);
1911
1912	ufshcd_enable_irq(hba);
1913
1914	/* Exit from hibern8 */
1915	if (ufshcd_can_hibern8_during_gating(hba)) {
1916	/* Prevent gating in this path */
1917	hba->clk_gating.is_suspended = true;
1918	if (ufshcd_is_link_hibern8(hba)) {
1919	ret = ufshcd_uic_hibern8_exit(hba);
1920	if (ret)
1921	dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1922	__func__, ret);
1923	else
1924	ufshcd_set_link_active(hba);
1925	}
1926	hba->clk_gating.is_suspended = false;
1927	}
1928	}
1929
1930	/**
1931	* ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1932	* Also, exit from hibern8 mode and set the link as active.
1933	* @hba: per adapter instance
1934	*/
1935	void ufshcd_hold(struct ufs_hba *hba)
1936	{
1937	bool flush_result;
1938	unsigned long flags;
1939
1940	if (!ufshcd_is_clkgating_allowed(hba) ||
1941	!hba->clk_gating.is_initialized)
1942	return;
1943	spin_lock_irqsave(&hba->clk_gating.lock, flags);
1944	hba->clk_gating.active_reqs++;
1945
1946	start:
1947	switch (hba->clk_gating.state) {
1948	case CLKS_ON:
1949	/*
1950	* Wait for the ungate work to complete if in progress.
1951	* Though the clocks may be in ON state, the link could
1952	* still be in hibner8 state if hibern8 is allowed
1953	* during clock gating.
1954	* Make sure we exit hibern8 state also in addition to
1955	* clocks being ON.
1956	*/
1957	if (ufshcd_can_hibern8_during_gating(hba) &&
1958	ufshcd_is_link_hibern8(hba)) {
1959	spin_unlock_irqrestore(lock: &hba->clk_gating.lock, flags);
1960	flush_result = flush_work(work: &hba->clk_gating.ungate_work);
1961	if (hba->clk_gating.is_suspended && !flush_result)
1962	return;
1963	spin_lock_irqsave(&hba->clk_gating.lock, flags);
1964	goto start;
1965	}
1966	break;
1967	case REQ_CLKS_OFF:
1968	if (cancel_delayed_work(dwork: &hba->clk_gating.gate_work)) {
1969	hba->clk_gating.state = CLKS_ON;
1970	trace_ufshcd_clk_gating(hba,
1971	state: hba->clk_gating.state);
1972	break;
1973	}
1974	/*
1975	* If we are here, it means gating work is either done or
1976	* currently running. Hence, fall through to cancel gating
1977	* work and to enable clocks.
1978	*/
1979	fallthrough;
1980	case CLKS_OFF:
1981	hba->clk_gating.state = REQ_CLKS_ON;
1982	trace_ufshcd_clk_gating(hba,
1983	state: hba->clk_gating.state);
1984	queue_work(wq: hba->clk_gating.clk_gating_workq,
1985	work: &hba->clk_gating.ungate_work);
1986	/*
1987	* fall through to check if we should wait for this
1988	* work to be done or not.
1989	*/
1990	fallthrough;
1991	case REQ_CLKS_ON:
1992	spin_unlock_irqrestore(lock: &hba->clk_gating.lock, flags);
1993	flush_work(work: &hba->clk_gating.ungate_work);
1994	/* Make sure state is CLKS_ON before returning */
1995	spin_lock_irqsave(&hba->clk_gating.lock, flags);
1996	goto start;
1997	default:
1998	dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1999	__func__, hba->clk_gating.state);
2000	break;
2001	}
2002	spin_unlock_irqrestore(lock: &hba->clk_gating.lock, flags);
2003	}
2004	EXPORT_SYMBOL_GPL(ufshcd_hold);
2005
2006	static void ufshcd_gate_work(struct work_struct *work)
2007	{
2008	struct ufs_hba *hba = container_of(work, struct ufs_hba,
2009	clk_gating.gate_work.work);
2010	int ret;
2011
2012	scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) {
2013	/*
2014	* In case you are here to cancel this work the gating state
2015	* would be marked as REQ_CLKS_ON. In this case save time by
2016	* skipping the gating work and exit after changing the clock
2017	* state to CLKS_ON.
2018	*/
2019	if (hba->clk_gating.is_suspended ||
2020	hba->clk_gating.state != REQ_CLKS_OFF) {
2021	hba->clk_gating.state = CLKS_ON;
2022	trace_ufshcd_clk_gating(hba,
2023	state: hba->clk_gating.state);
2024	return;
2025	}
2026
2027	if (hba->clk_gating.active_reqs)
2028	return;
2029	}
2030
2031	scoped_guard(spinlock_irqsave, hba->host->host_lock) {
2032	if (ufshcd_is_ufs_dev_busy(hba) ||
2033	hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
2034	return;
2035	}
2036
2037	/* put the link into hibern8 mode before turning off clocks */
2038	if (ufshcd_can_hibern8_during_gating(hba)) {
2039	ret = ufshcd_uic_hibern8_enter(hba);
2040	if (ret) {
2041	hba->clk_gating.state = CLKS_ON;
2042	dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
2043	__func__, ret);
2044	trace_ufshcd_clk_gating(hba,
2045	state: hba->clk_gating.state);
2046	return;
2047	}
2048	ufshcd_set_link_hibern8(hba);
2049	}
2050
2051	ufshcd_disable_irq(hba);
2052
2053	ufshcd_setup_clocks(hba, on: false);
2054
2055	/* Put the host controller in low power mode if possible */
2056	ufshcd_hba_vreg_set_lpm(hba);
2057	/*
2058	* In case you are here to cancel this work the gating state
2059	* would be marked as REQ_CLKS_ON. In this case keep the state
2060	* as REQ_CLKS_ON which would anyway imply that clocks are off
2061	* and a request to turn them on is pending. By doing this way,
2062	* we keep the state machine in tact and this would ultimately
2063	* prevent from doing cancel work multiple times when there are
2064	* new requests arriving before the current cancel work is done.
2065	*/
2066	guard(spinlock_irqsave)(l: &hba->clk_gating.lock);
2067	if (hba->clk_gating.state == REQ_CLKS_OFF) {
2068	hba->clk_gating.state = CLKS_OFF;
2069	trace_ufshcd_clk_gating(hba,
2070	state: hba->clk_gating.state);
2071	}
2072	}
2073
2074	static void __ufshcd_release(struct ufs_hba *hba)
2075	{
2076	lockdep_assert_held(&hba->clk_gating.lock);
2077
2078	if (!ufshcd_is_clkgating_allowed(hba))
2079	return;
2080
2081	hba->clk_gating.active_reqs--;
2082
2083	if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
2084	!hba->clk_gating.is_initialized ||
2085	hba->clk_gating.state == CLKS_OFF)
2086	return;
2087
2088	scoped_guard(spinlock_irqsave, hba->host->host_lock) {
2089	if (ufshcd_has_pending_tasks(hba) ||
2090	hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
2091	return;
2092	}
2093
2094	hba->clk_gating.state = REQ_CLKS_OFF;
2095	trace_ufshcd_clk_gating(hba, state: hba->clk_gating.state);
2096	queue_delayed_work(wq: hba->clk_gating.clk_gating_workq,
2097	dwork: &hba->clk_gating.gate_work,
2098	delay: msecs_to_jiffies(m: hba->clk_gating.delay_ms));
2099	}
2100
2101	void ufshcd_release(struct ufs_hba *hba)
2102	{
2103	guard(spinlock_irqsave)(l: &hba->clk_gating.lock);
2104	__ufshcd_release(hba);
2105	}
2106	EXPORT_SYMBOL_GPL(ufshcd_release);
2107
2108	static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
2109	struct device_attribute *attr, char *buf)
2110	{
2111	struct ufs_hba *hba = dev_get_drvdata(dev);
2112
2113	return sysfs_emit(buf, fmt: "%lu\n", hba->clk_gating.delay_ms);
2114	}
2115
2116	void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
2117	{
2118	struct ufs_hba *hba = dev_get_drvdata(dev);
2119
2120	guard(spinlock_irqsave)(l: &hba->clk_gating.lock);
2121	hba->clk_gating.delay_ms = value;
2122	}
2123	EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
2124
2125	static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
2126	struct device_attribute *attr, const char *buf, size_t count)
2127	{
2128	unsigned long value;
2129
2130	if (kstrtoul(s: buf, base: 0, res: &value))
2131	return -EINVAL;
2132
2133	ufshcd_clkgate_delay_set(dev, value);
2134	return count;
2135	}
2136
2137	static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
2138	struct device_attribute *attr, char *buf)
2139	{
2140	struct ufs_hba *hba = dev_get_drvdata(dev);
2141
2142	return sysfs_emit(buf, fmt: "%d\n", hba->clk_gating.is_enabled);
2143	}
2144
2145	static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
2146	struct device_attribute *attr, const char *buf, size_t count)
2147	{
2148	struct ufs_hba *hba = dev_get_drvdata(dev);
2149	u32 value;
2150
2151	if (kstrtou32(s: buf, base: 0, res: &value))
2152	return -EINVAL;
2153
2154	value = !!value;
2155
2156	guard(spinlock_irqsave)(l: &hba->clk_gating.lock);
2157
2158	if (value == hba->clk_gating.is_enabled)
2159	return count;
2160
2161	if (value)
2162	__ufshcd_release(hba);
2163	else
2164	hba->clk_gating.active_reqs++;
2165
2166	hba->clk_gating.is_enabled = value;
2167
2168	return count;
2169	}
2170
2171	static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
2172	{
2173	hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
2174	hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
2175	sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
2176	hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
2177	hba->clk_gating.delay_attr.attr.mode = 0644;
2178	if (device_create_file(device: hba->dev, entry: &hba->clk_gating.delay_attr))
2179	dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
2180
2181	hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
2182	hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
2183	sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
2184	hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
2185	hba->clk_gating.enable_attr.attr.mode = 0644;
2186	if (device_create_file(device: hba->dev, entry: &hba->clk_gating.enable_attr))
2187	dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
2188	}
2189
2190	static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
2191	{
2192	if (hba->clk_gating.delay_attr.attr.name)
2193	device_remove_file(dev: hba->dev, attr: &hba->clk_gating.delay_attr);
2194	if (hba->clk_gating.enable_attr.attr.name)
2195	device_remove_file(dev: hba->dev, attr: &hba->clk_gating.enable_attr);
2196	}
2197
2198	static void ufshcd_init_clk_gating(struct ufs_hba *hba)
2199	{
2200	if (!ufshcd_is_clkgating_allowed(hba))
2201	return;
2202
2203	hba->clk_gating.state = CLKS_ON;
2204
2205	hba->clk_gating.delay_ms = 150;
2206	INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2207	INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2208
2209	hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(
2210	"ufs_clk_gating_%d", WQ_MEM_RECLAIM | WQ_HIGHPRI,
2211	hba->host->host_no);
2212
2213	ufshcd_init_clk_gating_sysfs(hba);
2214
2215	hba->clk_gating.is_enabled = true;
2216	hba->clk_gating.is_initialized = true;
2217	}
2218
2219	static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2220	{
2221	if (!hba->clk_gating.is_initialized)
2222	return;
2223
2224	ufshcd_remove_clk_gating_sysfs(hba);
2225
2226	/* Ungate the clock if necessary. */
2227	ufshcd_hold(hba);
2228	hba->clk_gating.is_initialized = false;
2229	ufshcd_release(hba);
2230
2231	destroy_workqueue(wq: hba->clk_gating.clk_gating_workq);
2232	}
2233
2234	static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2235	{
2236	bool queue_resume_work = false;
2237	ktime_t curr_t;
2238
2239	if (!ufshcd_is_clkscaling_supported(hba))
2240	return;
2241
2242	curr_t = ktime_get();
2243
2244	guard(spinlock_irqsave)(l: &hba->clk_scaling.lock);
2245
2246	if (!hba->clk_scaling.active_reqs++)
2247	queue_resume_work = true;
2248
2249	if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress)
2250	return;
2251
2252	if (queue_resume_work)
2253	queue_work(wq: hba->clk_scaling.workq,
2254	work: &hba->clk_scaling.resume_work);
2255
2256	if (!hba->clk_scaling.window_start_t) {
2257	hba->clk_scaling.window_start_t = curr_t;
2258	hba->clk_scaling.tot_busy_t = 0;
2259	hba->clk_scaling.is_busy_started = false;
2260	}
2261
2262	if (!hba->clk_scaling.is_busy_started) {
2263	hba->clk_scaling.busy_start_t = curr_t;
2264	hba->clk_scaling.is_busy_started = true;
2265	}
2266	}
2267
2268	static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2269	{
2270	struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2271
2272	if (!ufshcd_is_clkscaling_supported(hba))
2273	return;
2274
2275	guard(spinlock_irqsave)(l: &hba->clk_scaling.lock);
2276
2277	hba->clk_scaling.active_reqs--;
2278	if (!scaling->active_reqs && scaling->is_busy_started) {
2279	scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2280	scaling->busy_start_t));
2281	scaling->busy_start_t = 0;
2282	scaling->is_busy_started = false;
2283	}
2284	}
2285
2286	static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2287	{
2288	if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2289	return READ;
2290	else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2291	return WRITE;
2292	else
2293	return -EINVAL;
2294	}
2295
2296	/* Must only be called for SCSI commands. */
2297	static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2298	struct scsi_cmnd *cmd)
2299	{
2300	const struct ufs_hba_monitor *m = &hba->monitor;
2301	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2302
2303	return m->enabled &&
2304	(!m->chunk_size || m->chunk_size == cmd->sdb.length) &&
2305	ktime_before(cmp1: hba->monitor.enabled_ts, cmp2: lrbp->issue_time_stamp);
2306	}
2307
2308	static void ufshcd_start_monitor(struct ufs_hba *hba, struct scsi_cmnd *cmd)
2309	{
2310	int dir = ufshcd_monitor_opcode2dir(opcode: cmd->cmnd[0]);
2311	unsigned long flags;
2312
2313	spin_lock_irqsave(hba->host->host_lock, flags);
2314	if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2315	hba->monitor.busy_start_ts[dir] = ktime_get();
2316	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
2317	}
2318
2319	static void ufshcd_update_monitor(struct ufs_hba *hba, struct scsi_cmnd *cmd)
2320	{
2321	struct request *req = scsi_cmd_to_rq(scmd: cmd);
2322	const struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2323	int dir = ufshcd_monitor_opcode2dir(opcode: cmd->cmnd[0]);
2324	unsigned long flags;
2325
2326	spin_lock_irqsave(hba->host->host_lock, flags);
2327	if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2328	struct ufs_hba_monitor *m = &hba->monitor;
2329	ktime_t now, inc, lat;
2330
2331	now = lrbp->compl_time_stamp;
2332	inc = ktime_sub(now, m->busy_start_ts[dir]);
2333	m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2334	m->nr_sec_rw[dir] += blk_rq_sectors(rq: req);
2335
2336	/* Update latencies */
2337	m->nr_req[dir]++;
2338	lat = ktime_sub(now, lrbp->issue_time_stamp);
2339	m->lat_sum[dir] += lat;
2340	if (m->lat_max[dir] < lat || !m->lat_max[dir])
2341	m->lat_max[dir] = lat;
2342	if (m->lat_min[dir] > lat || !m->lat_min[dir])
2343	m->lat_min[dir] = lat;
2344
2345	m->nr_queued[dir]--;
2346	/* Push forward the busy start of monitor */
2347	m->busy_start_ts[dir] = now;
2348	}
2349	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
2350	}
2351
2352	/* Returns %true for SCSI commands and %false for device management commands. */
2353	static bool ufshcd_is_scsi_cmd(struct scsi_cmnd *cmd)
2354	{
2355	return !blk_mq_is_reserved_rq(rq: scsi_cmd_to_rq(scmd: cmd));
2356	}
2357
2358	/**
2359	* ufshcd_send_command - Send SCSI or device management commands
2360	* @hba: per adapter instance
2361	* @cmd: SCSI command or device management command pointer
2362	* @hwq: pointer to hardware queue instance
2363	*/
2364	static inline void ufshcd_send_command(struct ufs_hba *hba,
2365	struct scsi_cmnd *cmd,
2366	struct ufs_hw_queue *hwq)
2367	{
2368	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2369	const int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
2370	unsigned long flags;
2371
2372	if (hba->monitor.enabled) {
2373	lrbp->issue_time_stamp = ktime_get();
2374	lrbp->issue_time_stamp_local_clock = local_clock();
2375	lrbp->compl_time_stamp = ktime_set(secs: 0, nsecs: 0);
2376	lrbp->compl_time_stamp_local_clock = 0;
2377	}
2378	if (ufshcd_is_scsi_cmd(cmd)) {
2379	ufshcd_add_command_trace(hba, cmd, str_t: UFS_CMD_SEND);
2380	ufshcd_clk_scaling_start_busy(hba);
2381	if (unlikely(ufshcd_should_inform_monitor(hba, cmd)))
2382	ufshcd_start_monitor(hba, cmd);
2383	}
2384
2385	if (hba->mcq_enabled) {
2386	int utrd_size = sizeof(struct utp_transfer_req_desc);
2387	struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr;
2388	struct utp_transfer_req_desc *dest;
2389
2390	spin_lock(lock: &hwq->sq_lock);
2391	dest = hwq->sqe_base_addr + hwq->sq_tail_slot;
2392	memcpy(dest, src, utrd_size);
2393	ufshcd_inc_sq_tail(q: hwq);
2394	spin_unlock(lock: &hwq->sq_lock);
2395	} else {
2396	spin_lock_irqsave(&hba->outstanding_lock, flags);
2397	if (hba->vops && hba->vops->setup_xfer_req)
2398	hba->vops->setup_xfer_req(hba, tag,
2399	ufshcd_is_scsi_cmd(cmd));
2400	__set_bit(tag, &hba->outstanding_reqs);
2401	ufshcd_writel(hba, 1 << tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2402	spin_unlock_irqrestore(lock: &hba->outstanding_lock, flags);
2403	}
2404	}
2405
2406	/**
2407	* ufshcd_copy_sense_data - Copy sense data in case of check condition
2408	* @cmd: SCSI command
2409	*/
2410	static inline void ufshcd_copy_sense_data(struct scsi_cmnd *cmd)
2411	{
2412	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2413	u8 *const sense_buffer = cmd->sense_buffer;
2414	u16 resp_len;
2415	int len;
2416
2417	resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length);
2418	if (sense_buffer && resp_len) {
2419	int len_to_copy;
2420
2421	len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2422	len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2423
2424	memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2425	len_to_copy);
2426	}
2427	}
2428
2429	/**
2430	* ufshcd_copy_query_response() - Copy the Query Response and the data
2431	* descriptor
2432	* @hba: per adapter instance
2433	* @lrbp: pointer to local reference block
2434	*
2435	* Return: 0 upon success; < 0 upon failure.
2436	*/
2437	static
2438	int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2439	{
2440	struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2441
2442	memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2443
2444	/* Get the descriptor */
2445	if (hba->dev_cmd.query.descriptor &&
2446	lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2447	u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2448	GENERAL_UPIU_REQUEST_SIZE;
2449	u16 resp_len;
2450	u16 buf_len;
2451
2452	/* data segment length */
2453	resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
2454	.data_segment_length);
2455	buf_len = be16_to_cpu(
2456	hba->dev_cmd.query.request.upiu_req.length);
2457	if (likely(buf_len >= resp_len)) {
2458	memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2459	} else {
2460	dev_warn(hba->dev,
2461	"%s: rsp size %d is bigger than buffer size %d",
2462	__func__, resp_len, buf_len);
2463	return -EINVAL;
2464	}
2465	}
2466
2467	return 0;
2468	}
2469
2470	/**
2471	* ufshcd_hba_capabilities - Read controller capabilities
2472	* @hba: per adapter instance
2473	*
2474	* Return: 0 on success, negative on error.
2475	*/
2476	static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2477	{
2478	int err;
2479
2480	hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2481
2482	/* nutrs and nutmrs are 0 based values */
2483	hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1;
2484	hba->nutmrs =
2485	((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2486
2487	hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1;
2488
2489	/* Read crypto capabilities */
2490	err = ufshcd_hba_init_crypto_capabilities(hba);
2491	if (err) {
2492	dev_err(hba->dev, "crypto setup failed\n");
2493	return err;
2494	}
2495
2496	/*
2497	* The UFSHCI 3.0 specification does not define MCQ_SUPPORT and
2498	* LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which
2499	* means we can simply read values regardless of version.
2500	*/
2501	hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities);
2502	/*
2503	* 0h: legacy single doorbell support is available
2504	* 1h: indicate that legacy single doorbell support has been removed
2505	*/
2506	if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_LSDBS_CAP))
2507	hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities);
2508	else
2509	hba->lsdb_sup = true;
2510
2511	hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2512
2513	return 0;
2514	}
2515
2516	/**
2517	* ufshcd_ready_for_uic_cmd - Check if controller is ready
2518	* to accept UIC commands
2519	* @hba: per adapter instance
2520	*
2521	* Return: true on success, else false.
2522	*/
2523	static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2524	{
2525	u32 val;
2526	int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
2527	500, uic_cmd_timeout * 1000, false, hba,
2528	REG_CONTROLLER_STATUS);
2529	return ret == 0;
2530	}
2531
2532	/**
2533	* ufshcd_get_upmcrs - Get the power mode change request status
2534	* @hba: Pointer to adapter instance
2535	*
2536	* This function gets the UPMCRS field of HCS register
2537	*
2538	* Return: value of UPMCRS field.
2539	*/
2540	static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2541	{
2542	return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2543	}
2544
2545	/**
2546	* ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2547	* @hba: per adapter instance
2548	* @uic_cmd: UIC command
2549	*/
2550	static inline void
2551	ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2552	{
2553	lockdep_assert_held(&hba->uic_cmd_mutex);
2554
2555	WARN_ON(hba->active_uic_cmd);
2556
2557	hba->active_uic_cmd = uic_cmd;
2558
2559	/* Write Args */
2560	ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2561	ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2562	ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2563
2564	ufshcd_add_uic_command_trace(hba, ucmd: uic_cmd, str_t: UFS_CMD_SEND);
2565
2566	/* Write UIC Cmd */
2567	ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2568	REG_UIC_COMMAND);
2569	}
2570
2571	/**
2572	* ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2573	* @hba: per adapter instance
2574	* @uic_cmd: UIC command
2575	*
2576	* Return: 0 only if success.
2577	*/
2578	static int
2579	ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2580	{
2581	int ret;
2582	unsigned long flags;
2583
2584	lockdep_assert_held(&hba->uic_cmd_mutex);
2585
2586	if (wait_for_completion_timeout(x: &uic_cmd->done,
2587	timeout: msecs_to_jiffies(m: uic_cmd_timeout))) {
2588	ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2589	} else {
2590	ret = -ETIMEDOUT;
2591	dev_err(hba->dev,
2592	"uic cmd 0x%x with arg3 0x%x completion timeout\n",
2593	uic_cmd->command, uic_cmd->argument3);
2594
2595	if (!uic_cmd->cmd_active) {
2596	dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2597	__func__);
2598	ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2599	}
2600	}
2601
2602	spin_lock_irqsave(hba->host->host_lock, flags);
2603	hba->active_uic_cmd = NULL;
2604	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
2605
2606	return ret;
2607	}
2608
2609	/**
2610	* __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2611	* @hba: per adapter instance
2612	* @uic_cmd: UIC command
2613	*
2614	* Return: 0 if successful; < 0 upon failure.
2615	*/
2616	static int
2617	__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2618	{
2619	lockdep_assert_held(&hba->uic_cmd_mutex);
2620
2621	if (!ufshcd_ready_for_uic_cmd(hba)) {
2622	dev_err(hba->dev,
2623	"Controller not ready to accept UIC commands\n");
2624	return -EIO;
2625	}
2626
2627	init_completion(x: &uic_cmd->done);
2628
2629	uic_cmd->cmd_active = true;
2630	ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2631
2632	return 0;
2633	}
2634
2635	/**
2636	* ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2637	* @hba: per adapter instance
2638	* @uic_cmd: UIC command
2639	*
2640	* Return: 0 only if success.
2641	*/
2642	int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2643	{
2644	unsigned long flags;
2645	int ret;
2646
2647	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2648	return 0;
2649
2650	ufshcd_hold(hba);
2651	mutex_lock(&hba->uic_cmd_mutex);
2652	ufshcd_add_delay_before_dme_cmd(hba);
2653
2654	spin_lock_irqsave(hba->host->host_lock, flags);
2655	ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
2656	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
2657
2658	ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
2659	if (!ret)
2660	ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2661
2662	mutex_unlock(lock: &hba->uic_cmd_mutex);
2663
2664	ufshcd_release(hba);
2665	return ret;
2666	}
2667
2668	/**
2669	* ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2670	* @hba: per-adapter instance
2671	* @lrbp: pointer to local reference block
2672	* @sg_entries: The number of sg lists actually used
2673	* @sg_list: Pointer to SG list
2674	*/
2675	static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2676	struct scatterlist *sg_list)
2677	{
2678	struct ufshcd_sg_entry *prd;
2679	struct scatterlist *sg;
2680	int i;
2681
2682	if (sg_entries) {
2683
2684	if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2685	lrbp->utr_descriptor_ptr->prd_table_length =
2686	cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
2687	else
2688	lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
2689
2690	prd = lrbp->ucd_prdt_ptr;
2691
2692	for_each_sg(sg_list, sg, sg_entries, i) {
2693	const unsigned int len = sg_dma_len(sg);
2694
2695	/*
2696	* From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2697	* based value that indicates the length, in bytes, of
2698	* the data block. A maximum of length of 256KB may
2699	* exist for any entry. Bits 1:0 of this field shall be
2700	* 11b to indicate Dword granularity. A value of '3'
2701	* indicates 4 bytes, '7' indicates 8 bytes, etc."
2702	*/
2703	WARN_ONCE(len > SZ_256K, "len = %#x\n", len);
2704	prd->size = cpu_to_le32(len - 1);
2705	prd->addr = cpu_to_le64(sg->dma_address);
2706	prd->reserved = 0;
2707	prd = (void *)prd + ufshcd_sg_entry_size(hba);
2708	}
2709	} else {
2710	lrbp->utr_descriptor_ptr->prd_table_length = 0;
2711	}
2712	}
2713
2714	/**
2715	* ufshcd_map_sg - Map scatter-gather list to prdt
2716	* @hba: per adapter instance
2717	* @cmd: SCSI command
2718	*
2719	* Return: 0 in case of success, non-zero value in case of failure.
2720	*/
2721	static int ufshcd_map_sg(struct ufs_hba *hba, struct scsi_cmnd *cmd)
2722	{
2723	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2724	int sg_segments = scsi_dma_map(cmd);
2725
2726	if (sg_segments < 0)
2727	return sg_segments;
2728
2729	ufshcd_sgl_to_prdt(hba, lrbp, sg_entries: sg_segments, sg_list: scsi_sglist(cmd));
2730
2731	return ufshcd_crypto_fill_prdt(hba, cmd);
2732	}
2733
2734	/**
2735	* ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
2736	* descriptor according to request
2737	* @hba: per adapter instance
2738	* @lrbp: pointer to local reference block
2739	* @upiu_flags: flags required in the header
2740	* @cmd_dir: requests data direction
2741	* @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
2742	*/
2743	static void
2744	ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
2745	u8 *upiu_flags, enum dma_data_direction cmd_dir,
2746	int ehs_length)
2747	{
2748	struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2749	struct request_desc_header *h = &req_desc->header;
2750	enum utp_data_direction data_direction;
2751
2752	lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2753
2754	*h = (typeof(*h)){ };
2755
2756	if (cmd_dir == DMA_FROM_DEVICE) {
2757	data_direction = UTP_DEVICE_TO_HOST;
2758	*upiu_flags = UPIU_CMD_FLAGS_READ;
2759	} else if (cmd_dir == DMA_TO_DEVICE) {
2760	data_direction = UTP_HOST_TO_DEVICE;
2761	*upiu_flags = UPIU_CMD_FLAGS_WRITE;
2762	} else {
2763	data_direction = UTP_NO_DATA_TRANSFER;
2764	*upiu_flags = UPIU_CMD_FLAGS_NONE;
2765	}
2766
2767	h->command_type = lrbp->command_type;
2768	h->data_direction = data_direction;
2769	h->ehs_length = ehs_length;
2770
2771	if (lrbp->intr_cmd)
2772	h->interrupt = 1;
2773
2774	/* Prepare crypto related dwords */
2775	ufshcd_prepare_req_desc_hdr_crypto(lrbp, h);
2776
2777	/*
2778	* assigning invalid value for command status. Controller
2779	* updates OCS on command completion, with the command
2780	* status
2781	*/
2782	h->ocs = OCS_INVALID_COMMAND_STATUS;
2783
2784	req_desc->prd_table_length = 0;
2785	}
2786
2787	/**
2788	* ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2789	* for scsi commands
2790	* @cmd: SCSI command
2791	* @upiu_flags: flags
2792	*/
2793	static void ufshcd_prepare_utp_scsi_cmd_upiu(struct scsi_cmnd *cmd,
2794	u8 upiu_flags)
2795	{
2796	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2797	const int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
2798	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2799	unsigned short cdb_len;
2800
2801	ucd_req_ptr->header = (struct utp_upiu_header){
2802	.transaction_code = UPIU_TRANSACTION_COMMAND,
2803	.flags = upiu_flags,
2804	.lun = lrbp->lun,
2805	.task_tag = tag,
2806	.command_set_type = UPIU_COMMAND_SET_TYPE_SCSI,
2807	};
2808
2809	WARN_ON_ONCE(ucd_req_ptr->header.task_tag != tag);
2810
2811	ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2812
2813	cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2814	memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2815
2816	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2817	}
2818
2819	/**
2820	* ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
2821	* @hba: UFS hba
2822	* @cmd: SCSI command pointer
2823	* @upiu_flags: flags
2824	*/
2825	static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2826	struct scsi_cmnd *cmd, u8 upiu_flags)
2827	{
2828	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2829	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2830	const int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
2831	struct ufs_query *query = &hba->dev_cmd.query;
2832	u16 len = be16_to_cpu(query->request.upiu_req.length);
2833
2834	/* Query request header */
2835	ucd_req_ptr->header = (struct utp_upiu_header){
2836	.transaction_code = UPIU_TRANSACTION_QUERY_REQ,
2837	.flags = upiu_flags,
2838	.lun = lrbp->lun,
2839	.task_tag = tag,
2840	.query_function = query->request.query_func,
2841	/* Data segment length only need for WRITE_DESC */
2842	.data_segment_length =
2843	query->request.upiu_req.opcode ==
2844	UPIU_QUERY_OPCODE_WRITE_DESC ?
2845	cpu_to_be16(len) :
2846	0,
2847	};
2848
2849	/* Copy the Query Request buffer as is */
2850	memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2851	QUERY_OSF_SIZE);
2852
2853	/* Copy the Descriptor */
2854	if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2855	memcpy(ucd_req_ptr + 1, query->descriptor, len);
2856	}
2857
2858	static inline void ufshcd_prepare_utp_nop_upiu(struct scsi_cmnd *cmd)
2859	{
2860	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2861	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2862	const int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
2863
2864	memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2865
2866	ucd_req_ptr->header = (struct utp_upiu_header){
2867	.transaction_code = UPIU_TRANSACTION_NOP_OUT,
2868	.task_tag = tag,
2869	};
2870	}
2871
2872	/**
2873	* ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2874	* for Device Management Purposes
2875	* @hba: per adapter instance
2876	* @cmd: SCSI command pointer
2877	*
2878	* Return: 0 upon success; < 0 upon failure.
2879	*/
2880	static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2881	struct scsi_cmnd *cmd)
2882	{
2883	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2884	u8 upiu_flags;
2885	int ret = 0;
2886
2887	ufshcd_prepare_req_desc_hdr(hba, lrbp, upiu_flags: &upiu_flags, cmd_dir: DMA_NONE, ehs_length: 0);
2888
2889	if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2890	ufshcd_prepare_utp_query_req_upiu(hba, cmd, upiu_flags);
2891	else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2892	ufshcd_prepare_utp_nop_upiu(cmd);
2893	else
2894	ret = -EINVAL;
2895
2896	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2897
2898	return ret;
2899	}
2900
2901	/**
2902	* ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2903	* for SCSI Purposes
2904	* @hba: per adapter instance
2905	* @cmd: SCSI command
2906	*/
2907	static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct scsi_cmnd *cmd)
2908	{
2909	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2910	struct request *rq = scsi_cmd_to_rq(scmd: cmd);
2911	unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq));
2912	u8 upiu_flags;
2913
2914	ufshcd_prepare_req_desc_hdr(hba, lrbp, upiu_flags: &upiu_flags,
2915	cmd_dir: cmd->sc_data_direction, ehs_length: 0);
2916	if (ioprio_class == IOPRIO_CLASS_RT)
2917	upiu_flags |= UPIU_CMD_FLAGS_CP;
2918	ufshcd_prepare_utp_scsi_cmd_upiu(cmd, upiu_flags);
2919	}
2920
2921	static void ufshcd_init_lrb(struct ufs_hba *hba, struct scsi_cmnd *cmd)
2922	{
2923	const int i = scsi_cmd_to_rq(scmd: cmd)->tag;
2924	struct utp_transfer_cmd_desc *cmd_descp =
2925	(void *)hba->ucdl_base_addr + i * ufshcd_get_ucd_size(hba);
2926	struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2927	dma_addr_t cmd_desc_element_addr =
2928	hba->ucdl_dma_addr + i * ufshcd_get_ucd_size(hba);
2929	u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset);
2930	u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset);
2931	struct ufshcd_lrb *lrb = scsi_cmd_priv(cmd);
2932
2933	lrb->utr_descriptor_ptr = utrdlp + i;
2934	lrb->utrd_dma_addr =
2935	hba->utrdl_dma_addr + i * sizeof(struct utp_transfer_req_desc);
2936	lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
2937	lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2938	lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
2939	lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2940	lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
2941	lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2942	}
2943
2944	static void __ufshcd_setup_cmd(struct ufs_hba *hba, struct scsi_cmnd *cmd,
2945	u8 lun, int tag)
2946	{
2947	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2948
2949	ufshcd_init_lrb(hba, cmd);
2950
2951	memset(lrbp->ucd_req_ptr, 0, sizeof(*lrbp->ucd_req_ptr));
2952
2953	lrbp->lun = lun;
2954	ufshcd_prepare_lrbp_crypto(rq: ufshcd_is_scsi_cmd(cmd) ?
2955	scsi_cmd_to_rq(scmd: cmd) : NULL, lrbp);
2956	}
2957
2958	static void ufshcd_setup_scsi_cmd(struct ufs_hba *hba, struct scsi_cmnd *cmd,
2959	u8 lun, int tag)
2960	{
2961	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
2962
2963	__ufshcd_setup_cmd(hba, cmd, lun, tag);
2964	lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
2965	lrbp->req_abort_skip = false;
2966
2967	ufshcd_comp_scsi_upiu(hba, cmd);
2968	}
2969
2970	/**
2971	* ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2972	* @upiu_wlun_id: UPIU W-LUN id
2973	*
2974	* Return: SCSI W-LUN id.
2975	*/
2976	static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2977	{
2978	return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2979	}
2980
2981	static inline bool is_device_wlun(struct scsi_device *sdev)
2982	{
2983	return sdev->lun ==
2984	ufshcd_upiu_wlun_to_scsi_wlun(upiu_wlun_id: UFS_UPIU_UFS_DEVICE_WLUN);
2985	}
2986
2987	/*
2988	* Associate the UFS controller queue with the default and poll HCTX types.
2989	* Initialize the mq_map[] arrays.
2990	*/
2991	static void ufshcd_map_queues(struct Scsi_Host *shost)
2992	{
2993	struct ufs_hba *hba = shost_priv(shost);
2994	int i, queue_offset = 0;
2995
2996	if (!is_mcq_supported(hba)) {
2997	hba->nr_queues[HCTX_TYPE_DEFAULT] = 1;
2998	hba->nr_queues[HCTX_TYPE_READ] = 0;
2999	hba->nr_queues[HCTX_TYPE_POLL] = 1;
3000	hba->nr_hw_queues = 1;
3001	}
3002
3003	for (i = 0; i < shost->nr_maps; i++) {
3004	struct blk_mq_queue_map *map = &shost->tag_set.map[i];
3005
3006	map->nr_queues = hba->nr_queues[i];
3007	if (!map->nr_queues)
3008	continue;
3009	map->queue_offset = queue_offset;
3010	if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba))
3011	map->queue_offset = 0;
3012
3013	blk_mq_map_queues(qmap: map);
3014	queue_offset += map->nr_queues;
3015	}
3016	}
3017
3018	/*
3019	* The only purpose of this function is to make the SCSI core skip the memset()
3020	* call for the private command data.
3021	*/
3022	static int ufshcd_init_cmd_priv(struct Scsi_Host *host, struct scsi_cmnd *cmd)
3023	{
3024	return 0;
3025	}
3026
3027	/**
3028	* ufshcd_queuecommand - main entry point for SCSI requests
3029	* @host: SCSI host pointer
3030	* @cmd: command from SCSI Midlayer
3031	*
3032	* Return: 0 for success, non-zero in case of failure.
3033	*/
3034	static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
3035	{
3036	struct ufs_hba *hba = shost_priv(shost: host);
3037	int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
3038	int err = 0;
3039	struct ufs_hw_queue *hwq = NULL;
3040
3041	switch (hba->ufshcd_state) {
3042	case UFSHCD_STATE_OPERATIONAL:
3043	break;
3044	case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
3045	/*
3046	* SCSI error handler can call ->queuecommand() while UFS error
3047	* handler is in progress. Error interrupts could change the
3048	* state from UFSHCD_STATE_RESET to
3049	* UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
3050	* being issued in that case.
3051	*/
3052	if (ufshcd_eh_in_progress(hba)) {
3053	err = SCSI_MLQUEUE_HOST_BUSY;
3054	goto out;
3055	}
3056	break;
3057	case UFSHCD_STATE_EH_SCHEDULED_FATAL:
3058	/*
3059	* pm_runtime_get_sync() is used at error handling preparation
3060	* stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
3061	* PM ops, it can never be finished if we let SCSI layer keep
3062	* retrying it, which gets err handler stuck forever. Neither
3063	* can we let the scsi cmd pass through, because UFS is in bad
3064	* state, the scsi cmd may eventually time out, which will get
3065	* err handler blocked for too long. So, just fail the scsi cmd
3066	* sent from PM ops, err handler can recover PM error anyways.
3067	*/
3068	if (hba->pm_op_in_progress) {
3069	hba->force_reset = true;
3070	set_host_byte(cmd, status: DID_BAD_TARGET);
3071	scsi_done(cmd);
3072	goto out;
3073	}
3074	fallthrough;
3075	case UFSHCD_STATE_RESET:
3076	err = SCSI_MLQUEUE_HOST_BUSY;
3077	goto out;
3078	case UFSHCD_STATE_ERROR:
3079	set_host_byte(cmd, status: DID_ERROR);
3080	scsi_done(cmd);
3081	goto out;
3082	}
3083
3084	hba->req_abort_count = 0;
3085
3086	ufshcd_hold(hba);
3087
3088	ufshcd_setup_scsi_cmd(hba, cmd,
3089	lun: ufshcd_scsi_to_upiu_lun(scsi_lun: cmd->device->lun), tag);
3090
3091	err = ufshcd_map_sg(hba, cmd);
3092	if (err) {
3093	ufshcd_release(hba);
3094	goto out;
3095	}
3096
3097	if (hba->mcq_enabled)
3098	hwq = ufshcd_mcq_req_to_hwq(hba, req: scsi_cmd_to_rq(scmd: cmd));
3099
3100	ufshcd_send_command(hba, cmd, hwq);
3101
3102	out:
3103	if (ufs_trigger_eh(hba)) {
3104	unsigned long flags;
3105
3106	spin_lock_irqsave(hba->host->host_lock, flags);
3107	ufshcd_schedule_eh_work(hba);
3108	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
3109	}
3110
3111	return err;
3112	}
3113
3114	static int ufshcd_queue_reserved_command(struct Scsi_Host *host,
3115	struct scsi_cmnd *cmd)
3116	{
3117	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
3118	struct request *rq = scsi_cmd_to_rq(scmd: cmd);
3119	struct ufs_hba *hba = shost_priv(shost: host);
3120	struct ufs_hw_queue *hwq =
3121	hba->mcq_enabled ? ufshcd_mcq_req_to_hwq(hba, req: rq) : NULL;
3122
3123	ufshcd_add_query_upiu_trace(hba, str_t: UFS_QUERY_SEND, rq_rsp: lrbp->ucd_req_ptr);
3124	ufshcd_send_command(hba, cmd, hwq);
3125	return 0;
3126	}
3127
3128	static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct scsi_cmnd *cmd,
3129	enum dev_cmd_type cmd_type, u8 lun, int tag)
3130	{
3131	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
3132
3133	__ufshcd_setup_cmd(hba, cmd, lun, tag);
3134	lrbp->intr_cmd = true; /* No interrupt aggregation */
3135	hba->dev_cmd.type = cmd_type;
3136	}
3137
3138	/*
3139	* Return: 0 upon success; < 0 upon failure.
3140	*/
3141	static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, struct scsi_cmnd *cmd,
3142	enum dev_cmd_type cmd_type, int tag)
3143	{
3144	ufshcd_setup_dev_cmd(hba, cmd, cmd_type, lun: 0, tag);
3145
3146	return ufshcd_compose_devman_upiu(hba, cmd);
3147	}
3148
3149	/*
3150	* Check with the block layer if the command is inflight
3151	* @cmd: command to check.
3152	*
3153	* Return: true if command is inflight; false if not.
3154	*/
3155	bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd)
3156	{
3157	return cmd && blk_mq_rq_state(rq: scsi_cmd_to_rq(scmd: cmd)) == MQ_RQ_IN_FLIGHT;
3158	}
3159
3160	/*
3161	* Clear the pending command in the controller and wait until
3162	* the controller confirms that the command has been cleared.
3163	* @hba: per adapter instance
3164	* @task_tag: The tag number of the command to be cleared.
3165	*/
3166	static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag)
3167	{
3168	u32 mask;
3169	int err;
3170
3171	if (hba->mcq_enabled) {
3172	/*
3173	* MCQ mode. Clean up the MCQ resources similar to
3174	* what the ufshcd_utrl_clear() does for SDB mode.
3175	*/
3176	err = ufshcd_mcq_sq_cleanup(hba, task_tag);
3177	if (err) {
3178	dev_err(hba->dev, "%s: failed tag=%d. err=%d\n",
3179	__func__, task_tag, err);
3180	return err;
3181	}
3182	return 0;
3183	}
3184
3185	mask = 1U << task_tag;
3186
3187	/* clear outstanding transaction before retry */
3188	ufshcd_utrl_clear(hba, mask);
3189
3190	/*
3191	* wait for h/w to clear corresponding bit in door-bell.
3192	* max. wait is 1 sec.
3193	*/
3194	return ufshcd_wait_for_register(hba, reg: REG_UTP_TRANSFER_REQ_DOOR_BELL,
3195	mask, val: ~mask, interval_us: 1000, timeout_ms: 1000);
3196	}
3197
3198	/**
3199	* ufshcd_dev_cmd_completion() - handles device management command responses
3200	* @hba: per adapter instance
3201	* @lrbp: pointer to local reference block
3202	*
3203	* Return: 0 upon success; < 0 upon failure.
3204	*/
3205	static int
3206	ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3207	{
3208	enum upiu_response_transaction resp;
3209	int err = 0;
3210
3211	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(secs: 0, nsecs: 0);
3212	resp = ufshcd_get_req_rsp(ucd_rsp_ptr: lrbp->ucd_rsp_ptr);
3213
3214	switch (resp) {
3215	case UPIU_TRANSACTION_NOP_IN:
3216	if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
3217	err = -EINVAL;
3218	dev_err(hba->dev, "%s: unexpected response %x\n",
3219	__func__, resp);
3220	}
3221	break;
3222	case UPIU_TRANSACTION_QUERY_RSP: {
3223	u8 response = lrbp->ucd_rsp_ptr->header.response;
3224
3225	if (response == 0) {
3226	err = ufshcd_copy_query_response(hba, lrbp);
3227	} else {
3228	err = -EINVAL;
3229	dev_err(hba->dev, "%s: unexpected response in Query RSP: %x\n",
3230	__func__, response);
3231	}
3232	break;
3233	}
3234	case UPIU_TRANSACTION_REJECT_UPIU:
3235	/* TODO: handle Reject UPIU Response */
3236	err = -EPERM;
3237	dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
3238	__func__);
3239	break;
3240	case UPIU_TRANSACTION_RESPONSE:
3241	if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
3242	err = -EINVAL;
3243	dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
3244	}
3245	break;
3246	default:
3247	err = -EINVAL;
3248	dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
3249	__func__, resp);
3250	break;
3251	}
3252
3253	WARN_ONCE(err > 0, "Incorrect return value %d > 0\n", err);
3254	return err;
3255	}
3256
3257	static void ufshcd_dev_man_lock(struct ufs_hba *hba)
3258	{
3259	ufshcd_hold(hba);
3260	mutex_lock(&hba->dev_cmd.lock);
3261	down_read(sem: &hba->clk_scaling_lock);
3262	}
3263
3264	static void ufshcd_dev_man_unlock(struct ufs_hba *hba)
3265	{
3266	up_read(sem: &hba->clk_scaling_lock);
3267	mutex_unlock(lock: &hba->dev_cmd.lock);
3268	ufshcd_release(hba);
3269	}
3270
3271	static struct scsi_cmnd *ufshcd_get_dev_mgmt_cmd(struct ufs_hba *hba)
3272	{
3273	/*
3274	* The caller must hold this lock to guarantee that the NOWAIT
3275	* allocation will succeed.
3276	*/
3277	lockdep_assert_held(&hba->dev_cmd.lock);
3278
3279	return scsi_get_internal_cmd(
3280	sdev: hba->host->pseudo_sdev, data_direction: DMA_TO_DEVICE,
3281	flags: BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT);
3282	}
3283
3284	static void ufshcd_put_dev_mgmt_cmd(struct scsi_cmnd *cmd)
3285	{
3286	scsi_put_internal_cmd(scmd: cmd);
3287	}
3288
3289	/*
3290	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3291	* < 0 if another error occurred.
3292	*/
3293	static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct scsi_cmnd *cmd,
3294	const u32 tag, int timeout)
3295	{
3296	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
3297	struct request *rq = scsi_cmd_to_rq(scmd: cmd);
3298	blk_status_t sts;
3299
3300	rq->timeout = timeout;
3301	sts = blk_execute_rq(rq, at_head: true);
3302	if (sts != BLK_STS_OK)
3303	return blk_status_to_errno(status: sts);
3304	return lrbp->utr_descriptor_ptr->header.ocs;
3305	}
3306
3307	/**
3308	* ufshcd_exec_dev_cmd - API for sending device management requests
3309	* @hba: UFS hba
3310	* @cmd_type: specifies the type (NOP, Query...)
3311	* @timeout: timeout in milliseconds
3312	*
3313	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3314	* < 0 if another error occurred.
3315	*
3316	* NOTE: Since there is only one available tag for device management commands,
3317	* it is expected you hold the hba->dev_cmd.lock mutex.
3318	*/
3319	static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3320	enum dev_cmd_type cmd_type, int timeout)
3321	{
3322	struct scsi_cmnd *cmd = ufshcd_get_dev_mgmt_cmd(hba);
3323	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
3324	u32 tag;
3325	int err;
3326
3327	/* Protects use of hba->dev_cmd. */
3328	lockdep_assert_held(&hba->dev_cmd.lock);
3329
3330	if (WARN_ON_ONCE(!cmd))
3331	return -ENOMEM;
3332
3333	tag = scsi_cmd_to_rq(scmd: cmd)->tag;
3334
3335	err = ufshcd_compose_dev_cmd(hba, cmd, cmd_type, tag);
3336	if (unlikely(err))
3337	goto out;
3338
3339	err = ufshcd_issue_dev_cmd(hba, cmd, tag, timeout);
3340	if (err == 0)
3341	err = ufshcd_dev_cmd_completion(hba, lrbp);
3342
3343	out:
3344	ufshcd_put_dev_mgmt_cmd(cmd);
3345
3346	return err;
3347	}
3348
3349	/**
3350	* ufshcd_init_query() - init the query response and request parameters
3351	* @hba: per-adapter instance
3352	* @request: address of the request pointer to be initialized
3353	* @response: address of the response pointer to be initialized
3354	* @opcode: operation to perform
3355	* @idn: flag idn to access
3356	* @index: LU number to access
3357	* @selector: query/flag/descriptor further identification
3358	*/
3359	static inline void ufshcd_init_query(struct ufs_hba *hba,
3360	struct ufs_query_req **request, struct ufs_query_res **response,
3361	enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3362	{
3363	*request = &hba->dev_cmd.query.request;
3364	*response = &hba->dev_cmd.query.response;
3365	memset(*request, 0, sizeof(struct ufs_query_req));
3366	memset(*response, 0, sizeof(struct ufs_query_res));
3367	(*request)->upiu_req.opcode = opcode;
3368	(*request)->upiu_req.idn = idn;
3369	(*request)->upiu_req.index = index;
3370	(*request)->upiu_req.selector = selector;
3371	}
3372
3373	/*
3374	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3375	* < 0 if another error occurred.
3376	*/
3377	static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3378	enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3379	{
3380	int ret;
3381	int retries;
3382
3383	for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3384	ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3385	if (ret)
3386	dev_dbg(hba->dev,
3387	"%s: failed with error %d, retries %d\n",
3388	__func__, ret, retries);
3389	else
3390	break;
3391	}
3392
3393	if (ret)
3394	dev_err(hba->dev,
3395	"%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
3396	__func__, opcode, idn, ret, retries);
3397	return ret;
3398	}
3399
3400	/**
3401	* ufshcd_query_flag() - API function for sending flag query requests
3402	* @hba: per-adapter instance
3403	* @opcode: flag query to perform
3404	* @idn: flag idn to access
3405	* @index: flag index to access
3406	* @flag_res: the flag value after the query request completes
3407	*
3408	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3409	* < 0 if another error occurred.
3410	*/
3411	int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3412	enum flag_idn idn, u8 index, bool *flag_res)
3413	{
3414	struct ufs_query_req *request = NULL;
3415	struct ufs_query_res *response = NULL;
3416	int err, selector = 0;
3417	int timeout = dev_cmd_timeout;
3418
3419	BUG_ON(!hba);
3420
3421	ufshcd_dev_man_lock(hba);
3422
3423	ufshcd_init_query(hba, request: &request, response: &response, opcode, idn, index,
3424	selector);
3425
3426	switch (opcode) {
3427	case UPIU_QUERY_OPCODE_SET_FLAG:
3428	case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3429	case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3430	request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3431	break;
3432	case UPIU_QUERY_OPCODE_READ_FLAG:
3433	request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3434	if (!flag_res) {
3435	/* No dummy reads */
3436	dev_err(hba->dev, "%s: Invalid argument for read request\n",
3437	__func__);
3438	err = -EINVAL;
3439	goto out_unlock;
3440	}
3441	break;
3442	default:
3443	dev_err(hba->dev,
3444	"%s: Expected query flag opcode but got = %d\n",
3445	__func__, opcode);
3446	err = -EINVAL;
3447	goto out_unlock;
3448	}
3449
3450	err = ufshcd_exec_dev_cmd(hba, cmd_type: DEV_CMD_TYPE_QUERY, timeout);
3451
3452	if (err) {
3453	dev_err(hba->dev,
3454	"%s: Sending flag query for idn %d failed, err = %d\n",
3455	__func__, idn, err);
3456	goto out_unlock;
3457	}
3458
3459	if (flag_res)
3460	*flag_res = (be32_to_cpu(response->upiu_res.value) &
3461	MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3462
3463	out_unlock:
3464	ufshcd_dev_man_unlock(hba);
3465	return err;
3466	}
3467
3468	/**
3469	* ufshcd_query_attr - API function for sending attribute requests
3470	* @hba: per-adapter instance
3471	* @opcode: attribute opcode
3472	* @idn: attribute idn to access
3473	* @index: index field
3474	* @selector: selector field
3475	* @attr_val: the attribute value after the query request completes
3476	*
3477	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3478	* < 0 if another error occurred.
3479	*/
3480	int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3481	enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3482	{
3483	struct ufs_query_req *request = NULL;
3484	struct ufs_query_res *response = NULL;
3485	int err;
3486
3487	BUG_ON(!hba);
3488
3489	if (!attr_val) {
3490	dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3491	__func__, opcode);
3492	return -EINVAL;
3493	}
3494
3495	ufshcd_dev_man_lock(hba);
3496
3497	ufshcd_init_query(hba, request: &request, response: &response, opcode, idn, index,
3498	selector);
3499
3500	switch (opcode) {
3501	case UPIU_QUERY_OPCODE_WRITE_ATTR:
3502	request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3503	request->upiu_req.value = cpu_to_be32(*attr_val);
3504	break;
3505	case UPIU_QUERY_OPCODE_READ_ATTR:
3506	request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3507	break;
3508	default:
3509	dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3510	__func__, opcode);
3511	err = -EINVAL;
3512	goto out_unlock;
3513	}
3514
3515	err = ufshcd_exec_dev_cmd(hba, cmd_type: DEV_CMD_TYPE_QUERY, timeout: dev_cmd_timeout);
3516
3517	if (err) {
3518	dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3519	__func__, opcode, idn, index, err);
3520	goto out_unlock;
3521	}
3522
3523	*attr_val = be32_to_cpu(response->upiu_res.value);
3524
3525	out_unlock:
3526	ufshcd_dev_man_unlock(hba);
3527	return err;
3528	}
3529
3530	/**
3531	* ufshcd_query_attr_retry() - API function for sending query
3532	* attribute with retries
3533	* @hba: per-adapter instance
3534	* @opcode: attribute opcode
3535	* @idn: attribute idn to access
3536	* @index: index field
3537	* @selector: selector field
3538	* @attr_val: the attribute value after the query request
3539	* completes
3540	*
3541	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3542	* < 0 if another error occurred.
3543	*/
3544	int ufshcd_query_attr_retry(struct ufs_hba *hba,
3545	enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3546	u32 *attr_val)
3547	{
3548	int ret = 0;
3549	u32 retries;
3550
3551	for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3552	ret = ufshcd_query_attr(hba, opcode, idn, index,
3553	selector, attr_val);
3554	if (ret)
3555	dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3556	__func__, ret, retries);
3557	else
3558	break;
3559	}
3560
3561	if (ret)
3562	dev_err(hba->dev,
3563	"%s: query attribute, idn %d, failed with error %d after %d retries\n",
3564	__func__, idn, ret, QUERY_REQ_RETRIES);
3565	return ret;
3566	}
3567
3568	/*
3569	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3570	* < 0 if another error occurred.
3571	*/
3572	static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3573	enum query_opcode opcode, enum desc_idn idn, u8 index,
3574	u8 selector, u8 *desc_buf, int *buf_len)
3575	{
3576	struct ufs_query_req *request = NULL;
3577	struct ufs_query_res *response = NULL;
3578	int err;
3579
3580	BUG_ON(!hba);
3581
3582	if (!desc_buf) {
3583	dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3584	__func__, opcode);
3585	return -EINVAL;
3586	}
3587
3588	if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3589	dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3590	__func__, *buf_len);
3591	return -EINVAL;
3592	}
3593
3594	ufshcd_dev_man_lock(hba);
3595
3596	ufshcd_init_query(hba, request: &request, response: &response, opcode, idn, index,
3597	selector);
3598	hba->dev_cmd.query.descriptor = desc_buf;
3599	request->upiu_req.length = cpu_to_be16(*buf_len);
3600
3601	switch (opcode) {
3602	case UPIU_QUERY_OPCODE_WRITE_DESC:
3603	request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3604	break;
3605	case UPIU_QUERY_OPCODE_READ_DESC:
3606	request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3607	break;
3608	default:
3609	dev_err(hba->dev,
3610	"%s: Expected query descriptor opcode but got = 0x%.2x\n",
3611	__func__, opcode);
3612	err = -EINVAL;
3613	goto out_unlock;
3614	}
3615
3616	err = ufshcd_exec_dev_cmd(hba, cmd_type: DEV_CMD_TYPE_QUERY, timeout: dev_cmd_timeout);
3617
3618	if (err) {
3619	dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3620	__func__, opcode, idn, index, err);
3621	goto out_unlock;
3622	}
3623
3624	*buf_len = be16_to_cpu(response->upiu_res.length);
3625
3626	out_unlock:
3627	hba->dev_cmd.query.descriptor = NULL;
3628	ufshcd_dev_man_unlock(hba);
3629	return err;
3630	}
3631
3632	/**
3633	* ufshcd_query_descriptor_retry - API function for sending descriptor requests
3634	* @hba: per-adapter instance
3635	* @opcode: attribute opcode
3636	* @idn: attribute idn to access
3637	* @index: index field
3638	* @selector: selector field
3639	* @desc_buf: the buffer that contains the descriptor
3640	* @buf_len: length parameter passed to the device
3641	*
3642	* The buf_len parameter will contain, on return, the length parameter
3643	* received on the response.
3644	*
3645	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3646	* < 0 if another error occurred.
3647	*/
3648	int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3649	enum query_opcode opcode,
3650	enum desc_idn idn, u8 index,
3651	u8 selector,
3652	u8 *desc_buf, int *buf_len)
3653	{
3654	int err;
3655	int retries;
3656
3657	for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3658	err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3659	selector, desc_buf, buf_len);
3660	if (!err || err == -EINVAL)
3661	break;
3662	}
3663
3664	return err;
3665	}
3666
3667	/**
3668	* ufshcd_read_desc_param - read the specified descriptor parameter
3669	* @hba: Pointer to adapter instance
3670	* @desc_id: descriptor idn value
3671	* @desc_index: descriptor index
3672	* @param_offset: offset of the parameter to read
3673	* @param_read_buf: pointer to buffer where parameter would be read
3674	* @param_size: sizeof(param_read_buf)
3675	*
3676	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
3677	* < 0 if another error occurred.
3678	*/
3679	int ufshcd_read_desc_param(struct ufs_hba *hba,
3680	enum desc_idn desc_id,
3681	int desc_index,
3682	u8 param_offset,
3683	u8 *param_read_buf,
3684	u8 param_size)
3685	{
3686	int ret;
3687	u8 *desc_buf;
3688	int buff_len = QUERY_DESC_MAX_SIZE;
3689	bool is_kmalloc = true;
3690
3691	/* Safety check */
3692	if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3693	return -EINVAL;
3694
3695	/* Check whether we need temp memory */
3696	if (param_offset != 0 || param_size < buff_len) {
3697	desc_buf = kzalloc(buff_len, GFP_KERNEL);
3698	if (!desc_buf)
3699	return -ENOMEM;
3700	} else {
3701	desc_buf = param_read_buf;
3702	is_kmalloc = false;
3703	}
3704
3705	/* Request for full descriptor */
3706	ret = ufshcd_query_descriptor_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_DESC,
3707	idn: desc_id, index: desc_index, selector: 0,
3708	desc_buf, buf_len: &buff_len);
3709	if (ret) {
3710	dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3711	__func__, desc_id, desc_index, param_offset, ret);
3712	goto out;
3713	}
3714
3715	/* Update descriptor length */
3716	buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3717
3718	if (param_offset >= buff_len) {
3719	dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3720	__func__, param_offset, desc_id, buff_len);
3721	ret = -EINVAL;
3722	goto out;
3723	}
3724
3725	/* Sanity check */
3726	if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3727	dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3728	__func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3729	ret = -EINVAL;
3730	goto out;
3731	}
3732
3733	if (is_kmalloc) {
3734	/* Make sure we don't copy more data than available */
3735	if (param_offset >= buff_len)
3736	ret = -EINVAL;
3737	else
3738	memcpy(param_read_buf, &desc_buf[param_offset],
3739	min_t(u32, param_size, buff_len - param_offset));
3740	}
3741	out:
3742	if (is_kmalloc)
3743	kfree(objp: desc_buf);
3744	return ret;
3745	}
3746
3747	/**
3748	* struct uc_string_id - unicode string
3749	*
3750	* @len: size of this descriptor inclusive
3751	* @type: descriptor type
3752	* @uc: unicode string character
3753	*/
3754	struct uc_string_id {
3755	u8 len;
3756	u8 type;
3757	wchar_t uc[];
3758	} __packed;
3759
3760	/* replace non-printable or non-ASCII characters with spaces */
3761	static inline char ufshcd_remove_non_printable(u8 ch)
3762	{
3763	return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3764	}
3765
3766	/**
3767	* ufshcd_read_string_desc - read string descriptor
3768	* @hba: pointer to adapter instance
3769	* @desc_index: descriptor index
3770	* @buf: pointer to buffer where descriptor would be read,
3771	* the caller should free the memory.
3772	* @fmt: if %SD_ASCII_STD, convert from UTF-16 to ASCII
3773	*
3774	* Return:
3775	* * string size on success.
3776	* * -ENOMEM: on allocation failure
3777	* * -EINVAL: on a wrong parameter
3778	*/
3779	int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, u8 **buf, enum ufs_descr_fmt fmt)
3780	{
3781	struct uc_string_id *uc_str;
3782	u8 *str;
3783	int ret;
3784
3785	if (!buf)
3786	return -EINVAL;
3787
3788	uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3789	if (!uc_str)
3790	return -ENOMEM;
3791
3792	ret = ufshcd_read_desc_param(hba, desc_id: QUERY_DESC_IDN_STRING, desc_index, param_offset: 0,
3793	param_read_buf: (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3794	if (ret < 0) {
3795	dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3796	QUERY_REQ_RETRIES, ret);
3797	str = NULL;
3798	goto out;
3799	}
3800
3801	if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3802	dev_dbg(hba->dev, "String Desc is of zero length\n");
3803	str = NULL;
3804	ret = 0;
3805	goto out;
3806	}
3807
3808	if (fmt == SD_ASCII_STD) {
3809	ssize_t ascii_len;
3810	int i;
3811	/* remove header and divide by 2 to move from UTF16 to UTF8 */
3812	ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3813	str = kzalloc(ascii_len, GFP_KERNEL);
3814	if (!str) {
3815	ret = -ENOMEM;
3816	goto out;
3817	}
3818
3819	/*
3820	* the descriptor contains string in UTF16 format
3821	* we need to convert to utf-8 so it can be displayed
3822	*/
3823	ret = utf16s_to_utf8s(pwcs: uc_str->uc,
3824	len: uc_str->len - QUERY_DESC_HDR_SIZE,
3825	endian: UTF16_BIG_ENDIAN, s: str, maxlen: ascii_len - 1);
3826
3827	/* replace non-printable or non-ASCII characters with spaces */
3828	for (i = 0; i < ret; i++)
3829	str[i] = ufshcd_remove_non_printable(ch: str[i]);
3830
3831	str[ret++] = '\0';
3832
3833	} else {
3834	str = kmemdup(uc_str->uc, uc_str->len, GFP_KERNEL);
3835	if (!str) {
3836	ret = -ENOMEM;
3837	goto out;
3838	}
3839	ret = uc_str->len;
3840	}
3841	out:
3842	*buf = str;
3843	kfree(objp: uc_str);
3844	return ret;
3845	}
3846
3847	/**
3848	* ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3849	* @hba: Pointer to adapter instance
3850	* @lun: lun id
3851	* @param_offset: offset of the parameter to read
3852	* @param_read_buf: pointer to buffer where parameter would be read
3853	* @param_size: sizeof(param_read_buf)
3854	*
3855	* Return: 0 in case of success; < 0 upon failure.
3856	*/
3857	static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3858	int lun,
3859	enum unit_desc_param param_offset,
3860	u8 *param_read_buf,
3861	u32 param_size)
3862	{
3863	/*
3864	* Unit descriptors are only available for general purpose LUs (LUN id
3865	* from 0 to 7) and RPMB Well known LU.
3866	*/
3867	if (!ufs_is_valid_unit_desc_lun(dev_info: &hba->dev_info, lun))
3868	return -EOPNOTSUPP;
3869
3870	return ufshcd_read_desc_param(hba, desc_id: QUERY_DESC_IDN_UNIT, desc_index: lun,
3871	param_offset, param_read_buf, param_size);
3872	}
3873
3874	static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3875	{
3876	int err = 0;
3877	u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3878
3879	if (hba->dev_info.wspecversion >= 0x300) {
3880	err = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
3881	idn: QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, index: 0, selector: 0,
3882	attr_val: &gating_wait);
3883	if (err)
3884	dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3885	err, gating_wait);
3886
3887	if (gating_wait == 0) {
3888	gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3889	dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3890	gating_wait);
3891	}
3892
3893	hba->dev_info.clk_gating_wait_us = gating_wait;
3894	}
3895
3896	return err;
3897	}
3898
3899	/**
3900	* ufshcd_memory_alloc - allocate memory for host memory space data structures
3901	* @hba: per adapter instance
3902	*
3903	* 1. Allocate DMA memory for Command Descriptor array
3904	* Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3905	* 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3906	* 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3907	* (UTMRDL)
3908	* 4. Allocate memory for local reference block(lrb).
3909	*
3910	* Return: 0 for success, non-zero in case of failure.
3911	*/
3912	static int ufshcd_memory_alloc(struct ufs_hba *hba)
3913	{
3914	size_t utmrdl_size, utrdl_size, ucdl_size;
3915
3916	/* Allocate memory for UTP command descriptors */
3917	ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs;
3918	hba->ucdl_base_addr = dmam_alloc_coherent(dev: hba->dev,
3919	size: ucdl_size,
3920	dma_handle: &hba->ucdl_dma_addr,
3921	GFP_KERNEL);
3922
3923	/*
3924	* UFSHCI requires UTP command descriptor to be 128 byte aligned.
3925	*/
3926	if (!hba->ucdl_base_addr ||
3927	WARN_ON(hba->ucdl_dma_addr & (128 - 1))) {
3928	dev_err(hba->dev,
3929	"Command Descriptor Memory allocation failed\n");
3930	goto out;
3931	}
3932
3933	/*
3934	* Allocate memory for UTP Transfer descriptors
3935	* UFSHCI requires 1KB alignment of UTRD
3936	*/
3937	utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3938	hba->utrdl_base_addr = dmam_alloc_coherent(dev: hba->dev,
3939	size: utrdl_size,
3940	dma_handle: &hba->utrdl_dma_addr,
3941	GFP_KERNEL);
3942	if (!hba->utrdl_base_addr ||
3943	WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) {
3944	dev_err(hba->dev,
3945	"Transfer Descriptor Memory allocation failed\n");
3946	goto out;
3947	}
3948
3949	/*
3950	* Skip utmrdl allocation; it may have been
3951	* allocated during first pass and not released during
3952	* MCQ memory allocation.
3953	* See ufshcd_release_sdb_queue() and ufshcd_config_mcq()
3954	*/
3955	if (hba->utmrdl_base_addr)
3956	goto skip_utmrdl;
3957	/*
3958	* Allocate memory for UTP Task Management descriptors
3959	* UFSHCI requires 1KB alignment of UTMRD
3960	*/
3961	utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3962	hba->utmrdl_base_addr = dmam_alloc_coherent(dev: hba->dev,
3963	size: utmrdl_size,
3964	dma_handle: &hba->utmrdl_dma_addr,
3965	GFP_KERNEL);
3966	if (!hba->utmrdl_base_addr ||
3967	WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) {
3968	dev_err(hba->dev,
3969	"Task Management Descriptor Memory allocation failed\n");
3970	goto out;
3971	}
3972
3973	skip_utmrdl:
3974	return 0;
3975	out:
3976	return -ENOMEM;
3977	}
3978
3979	/**
3980	* ufshcd_host_memory_configure - configure local reference block with
3981	* memory offsets
3982	* @hba: per adapter instance
3983	*
3984	* Configure Host memory space
3985	* 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3986	* address.
3987	* 2. Update each UTRD with Response UPIU offset, Response UPIU length
3988	* and PRDT offset.
3989	* 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3990	* into local reference block.
3991	*/
3992	static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3993	{
3994	struct utp_transfer_req_desc *utrdlp;
3995	dma_addr_t cmd_desc_dma_addr;
3996	dma_addr_t cmd_desc_element_addr;
3997	u16 response_offset;
3998	u16 prdt_offset;
3999	int cmd_desc_size;
4000	int i;
4001
4002	utrdlp = hba->utrdl_base_addr;
4003
4004	response_offset =
4005	offsetof(struct utp_transfer_cmd_desc, response_upiu);
4006	prdt_offset =
4007	offsetof(struct utp_transfer_cmd_desc, prd_table);
4008
4009	cmd_desc_size = ufshcd_get_ucd_size(hba);
4010	cmd_desc_dma_addr = hba->ucdl_dma_addr;
4011
4012	for (i = 0; i < hba->nutrs; i++) {
4013	/* Configure UTRD with command descriptor base address */
4014	cmd_desc_element_addr =
4015	(cmd_desc_dma_addr + (cmd_desc_size * i));
4016	utrdlp[i].command_desc_base_addr =
4017	cpu_to_le64(cmd_desc_element_addr);
4018
4019	/* Response upiu and prdt offset should be in double words */
4020	if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
4021	utrdlp[i].response_upiu_offset =
4022	cpu_to_le16(response_offset);
4023	utrdlp[i].prd_table_offset =
4024	cpu_to_le16(prdt_offset);
4025	utrdlp[i].response_upiu_length =
4026	cpu_to_le16(ALIGNED_UPIU_SIZE);
4027	} else {
4028	utrdlp[i].response_upiu_offset =
4029	cpu_to_le16(response_offset >> 2);
4030	utrdlp[i].prd_table_offset =
4031	cpu_to_le16(prdt_offset >> 2);
4032	utrdlp[i].response_upiu_length =
4033	cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
4034	}
4035	}
4036	}
4037
4038	/**
4039	* ufshcd_dme_link_startup - Notify Unipro to perform link startup
4040	* @hba: per adapter instance
4041	*
4042	* UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
4043	* in order to initialize the Unipro link startup procedure.
4044	* Once the Unipro links are up, the device connected to the controller
4045	* is detected.
4046	*
4047	* Return: 0 on success, non-zero value on failure.
4048	*/
4049	static int ufshcd_dme_link_startup(struct ufs_hba *hba)
4050	{
4051	struct uic_command uic_cmd = {
4052	.command = UIC_CMD_DME_LINK_STARTUP,
4053	};
4054	int ret;
4055
4056	ret = ufshcd_send_uic_cmd(hba, uic_cmd: &uic_cmd);
4057	if (ret)
4058	dev_dbg(hba->dev,
4059	"dme-link-startup: error code %d\n", ret);
4060	return ret;
4061	}
4062	/**
4063	* ufshcd_dme_reset - UIC command for DME_RESET
4064	* @hba: per adapter instance
4065	*
4066	* DME_RESET command is issued in order to reset UniPro stack.
4067	* This function now deals with cold reset.
4068	*
4069	* Return: 0 on success, non-zero value on failure.
4070	*/
4071	int ufshcd_dme_reset(struct ufs_hba *hba)
4072	{
4073	struct uic_command uic_cmd = {
4074	.command = UIC_CMD_DME_RESET,
4075	};
4076	int ret;
4077
4078	ret = ufshcd_send_uic_cmd(hba, uic_cmd: &uic_cmd);
4079	if (ret)
4080	dev_err(hba->dev,
4081	"dme-reset: error code %d\n", ret);
4082
4083	return ret;
4084	}
4085	EXPORT_SYMBOL_GPL(ufshcd_dme_reset);
4086
4087	int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
4088	int agreed_gear,
4089	int adapt_val)
4090	{
4091	int ret;
4092
4093	if (agreed_gear < UFS_HS_G4)
4094	adapt_val = PA_NO_ADAPT;
4095
4096	ret = ufshcd_dme_set(hba,
4097	UIC_ARG_MIB(PA_TXHSADAPTTYPE),
4098	mib_val: adapt_val);
4099	return ret;
4100	}
4101	EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
4102
4103	/**
4104	* ufshcd_dme_enable - UIC command for DME_ENABLE
4105	* @hba: per adapter instance
4106	*
4107	* DME_ENABLE command is issued in order to enable UniPro stack.
4108	*
4109	* Return: 0 on success, non-zero value on failure.
4110	*/
4111	int ufshcd_dme_enable(struct ufs_hba *hba)
4112	{
4113	struct uic_command uic_cmd = {
4114	.command = UIC_CMD_DME_ENABLE,
4115	};
4116	int ret;
4117
4118	ret = ufshcd_send_uic_cmd(hba, uic_cmd: &uic_cmd);
4119	if (ret)
4120	dev_err(hba->dev,
4121	"dme-enable: error code %d\n", ret);
4122
4123	return ret;
4124	}
4125	EXPORT_SYMBOL_GPL(ufshcd_dme_enable);
4126
4127	static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
4128	{
4129	#define MIN_DELAY_BEFORE_DME_CMDS_US 1000
4130	unsigned long min_sleep_time_us;
4131
4132	if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
4133	return;
4134
4135	/*
4136	* last_dme_cmd_tstamp will be 0 only for 1st call to
4137	* this function
4138	*/
4139	if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
4140	min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
4141	} else {
4142	unsigned long delta =
4143	(unsigned long) ktime_to_us(
4144	ktime_sub(ktime_get(),
4145	hba->last_dme_cmd_tstamp));
4146
4147	if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
4148	min_sleep_time_us =
4149	MIN_DELAY_BEFORE_DME_CMDS_US - delta;
4150	else
4151	min_sleep_time_us = 0; /* no more delay required */
4152	}
4153
4154	if (min_sleep_time_us > 0) {
4155	/* allow sleep for extra 50us if needed */
4156	usleep_range(min: min_sleep_time_us, max: min_sleep_time_us + 50);
4157	}
4158
4159	/* update the last_dme_cmd_tstamp */
4160	hba->last_dme_cmd_tstamp = ktime_get();
4161	}
4162
4163	/**
4164	* ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
4165	* @hba: per adapter instance
4166	* @attr_sel: uic command argument1
4167	* @attr_set: attribute set type as uic command argument2
4168	* @mib_val: setting value as uic command argument3
4169	* @peer: indicate whether peer or local
4170	*
4171	* Return: 0 on success, non-zero value on failure.
4172	*/
4173	int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
4174	u8 attr_set, u32 mib_val, u8 peer)
4175	{
4176	struct uic_command uic_cmd = {
4177	.command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET,
4178	.argument1 = attr_sel,
4179	.argument2 = UIC_ARG_ATTR_TYPE(attr_set),
4180	.argument3 = mib_val,
4181	};
4182	static const char *const action[] = {
4183	"dme-set",
4184	"dme-peer-set"
4185	};
4186	const char *set = action[!!peer];
4187	int ret;
4188	int retries = UFS_UIC_COMMAND_RETRIES;
4189
4190	do {
4191	/* for peer attributes we retry upon failure */
4192	ret = ufshcd_send_uic_cmd(hba, uic_cmd: &uic_cmd);
4193	if (ret)
4194	dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
4195	set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
4196	} while (ret && peer && --retries);
4197
4198	if (ret)
4199	dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
4200	set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4201	UFS_UIC_COMMAND_RETRIES - retries);
4202
4203	return ret;
4204	}
4205	EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
4206
4207	/**
4208	* ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
4209	* @hba: per adapter instance
4210	* @attr_sel: uic command argument1
4211	* @mib_val: the value of the attribute as returned by the UIC command
4212	* @peer: indicate whether peer or local
4213	*
4214	* Return: 0 on success, non-zero value on failure.
4215	*/
4216	int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
4217	u32 *mib_val, u8 peer)
4218	{
4219	struct uic_command uic_cmd = {
4220	.command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET,
4221	.argument1 = attr_sel,
4222	};
4223	static const char *const action[] = {
4224	"dme-get",
4225	"dme-peer-get"
4226	};
4227	const char *get = action[!!peer];
4228	int ret;
4229	int retries = UFS_UIC_COMMAND_RETRIES;
4230	struct ufs_pa_layer_attr orig_pwr_info;
4231	struct ufs_pa_layer_attr temp_pwr_info;
4232	bool pwr_mode_change = false;
4233
4234	if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
4235	orig_pwr_info = hba->pwr_info;
4236	temp_pwr_info = orig_pwr_info;
4237
4238	if (orig_pwr_info.pwr_tx == FAST_MODE ||
4239	orig_pwr_info.pwr_rx == FAST_MODE) {
4240	temp_pwr_info.pwr_tx = FASTAUTO_MODE;
4241	temp_pwr_info.pwr_rx = FASTAUTO_MODE;
4242	pwr_mode_change = true;
4243	} else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
4244	orig_pwr_info.pwr_rx == SLOW_MODE) {
4245	temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
4246	temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
4247	pwr_mode_change = true;
4248	}
4249	if (pwr_mode_change) {
4250	ret = ufshcd_change_power_mode(hba, pwr_mode: &temp_pwr_info);
4251	if (ret)
4252	goto out;
4253	}
4254	}
4255
4256	do {
4257	/* for peer attributes we retry upon failure */
4258	ret = ufshcd_send_uic_cmd(hba, uic_cmd: &uic_cmd);
4259	if (ret)
4260	dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4261	get, UIC_GET_ATTR_ID(attr_sel), ret);
4262	} while (ret && peer && --retries);
4263
4264	if (ret)
4265	dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4266	get, UIC_GET_ATTR_ID(attr_sel),
4267	UFS_UIC_COMMAND_RETRIES - retries);
4268
4269	if (mib_val)
4270	*mib_val = ret == 0 ? uic_cmd.argument3 : 0;
4271
4272	if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4273	&& pwr_mode_change)
4274	ufshcd_change_power_mode(hba, pwr_mode: &orig_pwr_info);
4275	out:
4276	return ret;
4277	}
4278	EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4279
4280	/**
4281	* ufshcd_dme_rmw - get modify set a DME attribute
4282	* @hba: per adapter instance
4283	* @mask: indicates which bits to clear from the value that has been read
4284	* @val: actual value to write
4285	* @attr: dme attribute
4286	*/
4287	int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask,
4288	u32 val, u32 attr)
4289	{
4290	u32 cfg = 0;
4291	int err;
4292
4293	err = ufshcd_dme_get(hba, UIC_ARG_MIB(attr), mib_val: &cfg);
4294	if (err)
4295	return err;
4296
4297	cfg &= ~mask;
4298	cfg |= (val & mask);
4299
4300	return ufshcd_dme_set(hba, UIC_ARG_MIB(attr), mib_val: cfg);
4301	}
4302	EXPORT_SYMBOL_GPL(ufshcd_dme_rmw);
4303
4304	/**
4305	* ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4306	* state) and waits for it to take effect.
4307	*
4308	* @hba: per adapter instance
4309	* @cmd: UIC command to execute
4310	*
4311	* DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4312	* DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4313	* and device UniPro link and hence it's final completion would be indicated by
4314	* dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4315	* addition to normal UIC command completion Status (UCCS). This function only
4316	* returns after the relevant status bits indicate the completion.
4317	*
4318	* Return: 0 on success, non-zero value on failure.
4319	*/
4320	static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4321	{
4322	DECLARE_COMPLETION_ONSTACK(uic_async_done);
4323	unsigned long flags;
4324	u8 status;
4325	int ret;
4326
4327	mutex_lock(&hba->uic_cmd_mutex);
4328	ufshcd_add_delay_before_dme_cmd(hba);
4329
4330	spin_lock_irqsave(hba->host->host_lock, flags);
4331	if (ufshcd_is_link_broken(hba)) {
4332	ret = -ENOLINK;
4333	goto out_unlock;
4334	}
4335	hba->uic_async_done = &uic_async_done;
4336	ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4337	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
4338	ret = __ufshcd_send_uic_cmd(hba, uic_cmd: cmd);
4339	if (ret) {
4340	dev_err(hba->dev,
4341	"pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4342	cmd->command, cmd->argument3, ret);
4343	goto out;
4344	}
4345
4346	if (!wait_for_completion_timeout(x: hba->uic_async_done,
4347	timeout: msecs_to_jiffies(m: uic_cmd_timeout))) {
4348	dev_err(hba->dev,
4349	"pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4350	cmd->command, cmd->argument3);
4351
4352	if (!cmd->cmd_active) {
4353	dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4354	__func__);
4355	goto check_upmcrs;
4356	}
4357
4358	ret = -ETIMEDOUT;
4359	goto out;
4360	}
4361
4362	check_upmcrs:
4363	status = ufshcd_get_upmcrs(hba);
4364	if (status != PWR_LOCAL) {
4365	dev_err(hba->dev,
4366	"pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4367	cmd->command, status);
4368	ret = (status != PWR_OK) ? status : -1;
4369	}
4370	out:
4371	if (ret) {
4372	ufshcd_print_host_state(hba);
4373	ufshcd_print_pwr_info(hba);
4374	ufshcd_print_evt_hist(hba);
4375	}
4376
4377	spin_lock_irqsave(hba->host->host_lock, flags);
4378	hba->active_uic_cmd = NULL;
4379	hba->uic_async_done = NULL;
4380	if (ret && !hba->pm_op_in_progress) {
4381	ufshcd_set_link_broken(hba);
4382	ufshcd_schedule_eh_work(hba);
4383	}
4384	out_unlock:
4385	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
4386	mutex_unlock(lock: &hba->uic_cmd_mutex);
4387
4388	/*
4389	* If the h8 exit fails during the runtime resume process, it becomes
4390	* stuck and cannot be recovered through the error handler. To fix
4391	* this, use link recovery instead of the error handler.
4392	*/
4393	if (ret && hba->pm_op_in_progress)
4394	ret = ufshcd_link_recovery(hba);
4395
4396	return ret;
4397	}
4398
4399	/**
4400	* ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result
4401	* @hba: per adapter instance
4402	* @uic_cmd: UIC command
4403	*
4404	* Return: 0 only if success.
4405	*/
4406	int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
4407	{
4408	int ret;
4409
4410	if (uic_cmd->argument1 != UIC_ARG_MIB(PA_PWRMODE) ||
4411	uic_cmd->command != UIC_CMD_DME_SET)
4412	return ufshcd_send_uic_cmd(hba, uic_cmd);
4413
4414	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
4415	return 0;
4416
4417	ufshcd_hold(hba);
4418	ret = ufshcd_uic_pwr_ctrl(hba, cmd: uic_cmd);
4419	ufshcd_release(hba);
4420
4421	return ret;
4422	}
4423
4424	/**
4425	* ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4426	* using DME_SET primitives.
4427	* @hba: per adapter instance
4428	* @mode: powr mode value
4429	*
4430	* Return: 0 on success, non-zero value on failure.
4431	*/
4432	int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4433	{
4434	struct uic_command uic_cmd = {
4435	.command = UIC_CMD_DME_SET,
4436	.argument1 = UIC_ARG_MIB(PA_PWRMODE),
4437	.argument3 = mode,
4438	};
4439	int ret;
4440
4441	if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4442	ret = ufshcd_dme_set(hba,
4443	UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), mib_val: 1);
4444	if (ret) {
4445	dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4446	__func__, ret);
4447	goto out;
4448	}
4449	}
4450
4451	ufshcd_hold(hba);
4452	ret = ufshcd_uic_pwr_ctrl(hba, cmd: &uic_cmd);
4453	ufshcd_release(hba);
4454
4455	out:
4456	return ret;
4457	}
4458	EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
4459
4460	int ufshcd_link_recovery(struct ufs_hba *hba)
4461	{
4462	int ret;
4463	unsigned long flags;
4464
4465	spin_lock_irqsave(hba->host->host_lock, flags);
4466	hba->ufshcd_state = UFSHCD_STATE_RESET;
4467	ufshcd_set_eh_in_progress(hba);
4468	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
4469
4470	/* Reset the attached device */
4471	ufshcd_device_reset(hba);
4472
4473	ret = ufshcd_host_reset_and_restore(hba);
4474
4475	spin_lock_irqsave(hba->host->host_lock, flags);
4476	if (ret)
4477	hba->ufshcd_state = UFSHCD_STATE_ERROR;
4478	ufshcd_clear_eh_in_progress(hba);
4479	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
4480
4481	if (ret)
4482	dev_err(hba->dev, "%s: link recovery failed, err %d",
4483	__func__, ret);
4484
4485	return ret;
4486	}
4487	EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4488
4489	int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4490	{
4491	struct uic_command uic_cmd = {
4492	.command = UIC_CMD_DME_HIBER_ENTER,
4493	};
4494	ktime_t start = ktime_get();
4495	int ret;
4496
4497	ufshcd_vops_hibern8_notify(hba, cmd: UIC_CMD_DME_HIBER_ENTER, status: PRE_CHANGE);
4498
4499	ret = ufshcd_uic_pwr_ctrl(hba, cmd: &uic_cmd);
4500	trace_ufshcd_profile_hibern8(hba, profile_info: "enter",
4501	time_us: ktime_to_us(ktime_sub(ktime_get(), start)), err: ret);
4502
4503	if (ret)
4504	dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4505	__func__, ret);
4506	else
4507	ufshcd_vops_hibern8_notify(hba, cmd: UIC_CMD_DME_HIBER_ENTER,
4508	status: POST_CHANGE);
4509
4510	return ret;
4511	}
4512	EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4513
4514	int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4515	{
4516	struct uic_command uic_cmd = {
4517	.command = UIC_CMD_DME_HIBER_EXIT,
4518	};
4519	int ret;
4520	ktime_t start = ktime_get();
4521
4522	ufshcd_vops_hibern8_notify(hba, cmd: UIC_CMD_DME_HIBER_EXIT, status: PRE_CHANGE);
4523
4524	ret = ufshcd_uic_pwr_ctrl(hba, cmd: &uic_cmd);
4525	trace_ufshcd_profile_hibern8(hba, profile_info: "exit",
4526	time_us: ktime_to_us(ktime_sub(ktime_get(), start)), err: ret);
4527
4528	if (ret) {
4529	dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4530	__func__, ret);
4531	} else {
4532	ufshcd_vops_hibern8_notify(hba, cmd: UIC_CMD_DME_HIBER_EXIT,
4533	status: POST_CHANGE);
4534	hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
4535	hba->ufs_stats.hibern8_exit_cnt++;
4536	}
4537
4538	return ret;
4539	}
4540	EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4541
4542	static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba)
4543	{
4544	if (!ufshcd_is_auto_hibern8_supported(hba))
4545	return;
4546
4547	ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4548	}
4549
4550	void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4551	{
4552	const u32 cur_ahit = READ_ONCE(hba->ahit);
4553
4554	if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit)
4555	return;
4556
4557	WRITE_ONCE(hba->ahit, ahit);
4558	if (!pm_runtime_suspended(dev: &hba->ufs_device_wlun->sdev_gendev)) {
4559	ufshcd_rpm_get_sync(hba);
4560	ufshcd_hold(hba);
4561	ufshcd_configure_auto_hibern8(hba);
4562	ufshcd_release(hba);
4563	ufshcd_rpm_put_sync(hba);
4564	}
4565	}
4566	EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4567
4568	/**
4569	* ufshcd_init_pwr_info - setting the POR (power on reset)
4570	* values in hba power info
4571	* @hba: per-adapter instance
4572	*/
4573	static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4574	{
4575	hba->pwr_info.gear_rx = UFS_PWM_G1;
4576	hba->pwr_info.gear_tx = UFS_PWM_G1;
4577	hba->pwr_info.lane_rx = UFS_LANE_1;
4578	hba->pwr_info.lane_tx = UFS_LANE_1;
4579	hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4580	hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4581	hba->pwr_info.hs_rate = 0;
4582	}
4583
4584	/**
4585	* ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4586	* @hba: per-adapter instance
4587	*
4588	* Return: 0 upon success; < 0 upon failure.
4589	*/
4590	static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4591	{
4592	struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4593
4594	if (hba->max_pwr_info.is_valid)
4595	return 0;
4596
4597	if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4598	pwr_info->pwr_tx = FASTAUTO_MODE;
4599	pwr_info->pwr_rx = FASTAUTO_MODE;
4600	} else {
4601	pwr_info->pwr_tx = FAST_MODE;
4602	pwr_info->pwr_rx = FAST_MODE;
4603	}
4604	pwr_info->hs_rate = PA_HS_MODE_B;
4605
4606	/* Get the connected lane count */
4607	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4608	mib_val: &pwr_info->lane_rx);
4609	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4610	mib_val: &pwr_info->lane_tx);
4611
4612	if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4613	dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4614	__func__,
4615	pwr_info->lane_rx,
4616	pwr_info->lane_tx);
4617	return -EINVAL;
4618	}
4619
4620	if (pwr_info->lane_rx != pwr_info->lane_tx) {
4621	dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n",
4622	__func__,
4623	pwr_info->lane_rx,
4624	pwr_info->lane_tx);
4625	return -EINVAL;
4626	}
4627
4628	/*
4629	* First, get the maximum gears of HS speed.
4630	* If a zero value, it means there is no HSGEAR capability.
4631	* Then, get the maximum gears of PWM speed.
4632	*/
4633	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), mib_val: &pwr_info->gear_rx);
4634	if (!pwr_info->gear_rx) {
4635	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4636	mib_val: &pwr_info->gear_rx);
4637	if (!pwr_info->gear_rx) {
4638	dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4639	__func__, pwr_info->gear_rx);
4640	return -EINVAL;
4641	}
4642	pwr_info->pwr_rx = SLOW_MODE;
4643	}
4644
4645	ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4646	mib_val: &pwr_info->gear_tx);
4647	if (!pwr_info->gear_tx) {
4648	ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4649	mib_val: &pwr_info->gear_tx);
4650	if (!pwr_info->gear_tx) {
4651	dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4652	__func__, pwr_info->gear_tx);
4653	return -EINVAL;
4654	}
4655	pwr_info->pwr_tx = SLOW_MODE;
4656	}
4657
4658	hba->max_pwr_info.is_valid = true;
4659	return 0;
4660	}
4661
4662	static int ufshcd_change_power_mode(struct ufs_hba *hba,
4663	struct ufs_pa_layer_attr *pwr_mode)
4664	{
4665	int ret;
4666
4667	/* if already configured to the requested pwr_mode */
4668	if (!hba->force_pmc &&
4669	pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4670	pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4671	pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4672	pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4673	pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4674	pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4675	pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4676	dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4677	return 0;
4678	}
4679
4680	/*
4681	* Configure attributes for power mode change with below.
4682	* - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4683	* - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4684	* - PA_HSSERIES
4685	*/
4686	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), mib_val: pwr_mode->gear_rx);
4687	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4688	mib_val: pwr_mode->lane_rx);
4689	if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4690	pwr_mode->pwr_rx == FAST_MODE)
4691	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), mib_val: true);
4692	else
4693	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), mib_val: false);
4694
4695	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), mib_val: pwr_mode->gear_tx);
4696	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4697	mib_val: pwr_mode->lane_tx);
4698	if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4699	pwr_mode->pwr_tx == FAST_MODE)
4700	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), mib_val: true);
4701	else
4702	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), mib_val: false);
4703
4704	if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4705	pwr_mode->pwr_tx == FASTAUTO_MODE ||
4706	pwr_mode->pwr_rx == FAST_MODE ||
4707	pwr_mode->pwr_tx == FAST_MODE)
4708	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4709	mib_val: pwr_mode->hs_rate);
4710
4711	if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4712	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4713	DL_FC0ProtectionTimeOutVal_Default);
4714	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4715	DL_TC0ReplayTimeOutVal_Default);
4716	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4717	DL_AFC0ReqTimeOutVal_Default);
4718	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4719	DL_FC1ProtectionTimeOutVal_Default);
4720	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4721	DL_TC1ReplayTimeOutVal_Default);
4722	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4723	DL_AFC1ReqTimeOutVal_Default);
4724
4725	ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4726	DL_FC0ProtectionTimeOutVal_Default);
4727	ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4728	DL_TC0ReplayTimeOutVal_Default);
4729	ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4730	DL_AFC0ReqTimeOutVal_Default);
4731	}
4732
4733	ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4734	| pwr_mode->pwr_tx);
4735
4736	if (ret) {
4737	dev_err(hba->dev,
4738	"%s: power mode change failed %d\n", __func__, ret);
4739	} else {
4740	memcpy(&hba->pwr_info, pwr_mode,
4741	sizeof(struct ufs_pa_layer_attr));
4742	}
4743
4744	return ret;
4745	}
4746
4747	/**
4748	* ufshcd_config_pwr_mode - configure a new power mode
4749	* @hba: per-adapter instance
4750	* @desired_pwr_mode: desired power configuration
4751	*
4752	* Return: 0 upon success; < 0 upon failure.
4753	*/
4754	int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4755	struct ufs_pa_layer_attr *desired_pwr_mode)
4756	{
4757	struct ufs_pa_layer_attr final_params = { 0 };
4758	int ret;
4759
4760	ret = ufshcd_vops_pwr_change_notify(hba, status: PRE_CHANGE,
4761	dev_max_params: desired_pwr_mode, dev_req_params: &final_params);
4762
4763	if (ret)
4764	memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4765
4766	ret = ufshcd_change_power_mode(hba, pwr_mode: &final_params);
4767
4768	if (!ret)
4769	ufshcd_vops_pwr_change_notify(hba, status: POST_CHANGE, NULL,
4770	dev_req_params: &final_params);
4771
4772	return ret;
4773	}
4774	EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4775
4776	/**
4777	* ufshcd_complete_dev_init() - checks device readiness
4778	* @hba: per-adapter instance
4779	*
4780	* Set fDeviceInit flag and poll until device toggles it.
4781	*
4782	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
4783	* < 0 if another error occurred.
4784	*/
4785	static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4786	{
4787	int err;
4788	bool flag_res = true;
4789	ktime_t timeout;
4790
4791	err = ufshcd_query_flag_retry(hba, opcode: UPIU_QUERY_OPCODE_SET_FLAG,
4792	idn: QUERY_FLAG_IDN_FDEVICEINIT, index: 0, NULL);
4793	if (err) {
4794	dev_err(hba->dev,
4795	"%s: setting fDeviceInit flag failed with error %d\n",
4796	__func__, err);
4797	goto out;
4798	}
4799
4800	/* Poll fDeviceInit flag to be cleared */
4801	timeout = ktime_add_ms(kt: ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4802	do {
4803	err = ufshcd_query_flag(hba, opcode: UPIU_QUERY_OPCODE_READ_FLAG,
4804	idn: QUERY_FLAG_IDN_FDEVICEINIT, index: 0, flag_res: &flag_res);
4805	if (!flag_res)
4806	break;
4807	usleep_range(min: 500, max: 1000);
4808	} while (ktime_before(cmp1: ktime_get(), cmp2: timeout));
4809
4810	if (err) {
4811	dev_err(hba->dev,
4812	"%s: reading fDeviceInit flag failed with error %d\n",
4813	__func__, err);
4814	} else if (flag_res) {
4815	dev_err(hba->dev,
4816	"%s: fDeviceInit was not cleared by the device\n",
4817	__func__);
4818	err = -EBUSY;
4819	}
4820	out:
4821	return err;
4822	}
4823
4824	/**
4825	* ufshcd_make_hba_operational - Make UFS controller operational
4826	* @hba: per adapter instance
4827	*
4828	* To bring UFS host controller to operational state,
4829	* 1. Enable required interrupts
4830	* 2. Configure interrupt aggregation
4831	* 3. Program UTRL and UTMRL base address
4832	* 4. Configure run-stop-registers
4833	*
4834	* Return: 0 if successful; < 0 upon failure.
4835	*/
4836	int ufshcd_make_hba_operational(struct ufs_hba *hba)
4837	{
4838	int err = 0;
4839	u32 reg;
4840
4841	/* Enable required interrupts */
4842	ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4843
4844	/* Configure interrupt aggregation */
4845	if (ufshcd_is_intr_aggr_allowed(hba))
4846	ufshcd_config_intr_aggr(hba, cnt: hba->nutrs - 1, INT_AGGR_DEF_TO);
4847	else
4848	ufshcd_disable_intr_aggr(hba);
4849
4850	/* Configure UTRL and UTMRL base address registers */
4851	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4852	REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4853	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4854	REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4855	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4856	REG_UTP_TASK_REQ_LIST_BASE_L);
4857	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4858	REG_UTP_TASK_REQ_LIST_BASE_H);
4859
4860	/*
4861	* UCRDY, UTMRLDY and UTRLRDY bits must be 1
4862	*/
4863	reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4864	if (!(ufshcd_get_lists_status(reg))) {
4865	ufshcd_enable_run_stop_reg(hba);
4866	} else {
4867	dev_err(hba->dev,
4868	"Host controller not ready to process requests");
4869	err = -EIO;
4870	}
4871
4872	return err;
4873	}
4874	EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4875
4876	/**
4877	* ufshcd_hba_stop - Send controller to reset state
4878	* @hba: per adapter instance
4879	*/
4880	void ufshcd_hba_stop(struct ufs_hba *hba)
4881	{
4882	int err;
4883
4884	ufshcd_disable_irq(hba);
4885	ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4886	err = ufshcd_wait_for_register(hba, reg: REG_CONTROLLER_ENABLE,
4887	CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4888	interval_us: 10, timeout_ms: 1);
4889	ufshcd_enable_irq(hba);
4890	if (err)
4891	dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4892	}
4893	EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4894
4895	/**
4896	* ufshcd_hba_execute_hce - initialize the controller
4897	* @hba: per adapter instance
4898	*
4899	* The controller resets itself and controller firmware initialization
4900	* sequence kicks off. When controller is ready it will set
4901	* the Host Controller Enable bit to 1.
4902	*
4903	* Return: 0 on success, non-zero value on failure.
4904	*/
4905	static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4906	{
4907	int retry;
4908
4909	for (retry = 3; retry > 0; retry--) {
4910	if (ufshcd_is_hba_active(hba))
4911	/* change controller state to "reset state" */
4912	ufshcd_hba_stop(hba);
4913
4914	/* UniPro link is disabled at this point */
4915	ufshcd_set_link_off(hba);
4916
4917	ufshcd_vops_hce_enable_notify(hba, status: PRE_CHANGE);
4918
4919	/* start controller initialization sequence */
4920	ufshcd_hba_start(hba);
4921
4922	/*
4923	* To initialize a UFS host controller HCE bit must be set to 1.
4924	* During initialization the HCE bit value changes from 1->0->1.
4925	* When the host controller completes initialization sequence
4926	* it sets the value of HCE bit to 1. The same HCE bit is read back
4927	* to check if the controller has completed initialization sequence.
4928	* So without this delay the value HCE = 1, set in the previous
4929	* instruction might be read back.
4930	* This delay can be changed based on the controller.
4931	*/
4932	ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4933
4934	/* wait for the host controller to complete initialization */
4935	if (!ufshcd_wait_for_register(hba, reg: REG_CONTROLLER_ENABLE, CONTROLLER_ENABLE,
4936	CONTROLLER_ENABLE, interval_us: 1000, timeout_ms: 50))
4937	break;
4938
4939	dev_err(hba->dev, "Enabling the controller failed\n");
4940	}
4941
4942	if (!retry)
4943	return -EIO;
4944
4945	/* enable UIC related interrupts */
4946	ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4947
4948	ufshcd_vops_hce_enable_notify(hba, status: POST_CHANGE);
4949
4950	return 0;
4951	}
4952
4953	int ufshcd_hba_enable(struct ufs_hba *hba)
4954	{
4955	int ret;
4956
4957	if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4958	ufshcd_set_link_off(hba);
4959	ufshcd_vops_hce_enable_notify(hba, status: PRE_CHANGE);
4960
4961	/* enable UIC related interrupts */
4962	ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4963	ret = ufshcd_dme_reset(hba);
4964	if (ret) {
4965	dev_err(hba->dev, "DME_RESET failed\n");
4966	return ret;
4967	}
4968
4969	ret = ufshcd_dme_enable(hba);
4970	if (ret) {
4971	dev_err(hba->dev, "Enabling DME failed\n");
4972	return ret;
4973	}
4974
4975	ufshcd_vops_hce_enable_notify(hba, status: POST_CHANGE);
4976	} else {
4977	ret = ufshcd_hba_execute_hce(hba);
4978	}
4979
4980	return ret;
4981	}
4982	EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4983
4984	static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4985	{
4986	int tx_lanes, i, err = 0;
4987
4988	if (!peer)
4989	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4990	mib_val: &tx_lanes);
4991	else
4992	ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4993	mib_val: &tx_lanes);
4994	for (i = 0; i < tx_lanes; i++) {
4995	if (!peer)
4996	err = ufshcd_dme_set(hba,
4997	UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4998	UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4999	mib_val: 0);
5000	else
5001	err = ufshcd_dme_peer_set(hba,
5002	UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
5003	UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
5004	mib_val: 0);
5005	if (err) {
5006	dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
5007	__func__, peer, i, err);
5008	break;
5009	}
5010	}
5011
5012	return err;
5013	}
5014
5015	static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
5016	{
5017	return ufshcd_disable_tx_lcc(hba, peer: true);
5018	}
5019
5020	void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
5021	{
5022	struct ufs_event_hist *e;
5023
5024	if (id >= UFS_EVT_CNT)
5025	return;
5026
5027	e = &hba->ufs_stats.event[id];
5028	e->val[e->pos] = val;
5029	e->tstamp[e->pos] = local_clock();
5030	e->cnt += 1;
5031	e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
5032
5033	ufshcd_vops_event_notify(hba, evt: id, data: &val);
5034	}
5035	EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
5036
5037	/**
5038	* ufshcd_link_startup - Initialize unipro link startup
5039	* @hba: per adapter instance
5040	*
5041	* Return: 0 for success, non-zero in case of failure.
5042	*/
5043	static int ufshcd_link_startup(struct ufs_hba *hba)
5044	{
5045	int ret;
5046	int retries = DME_LINKSTARTUP_RETRIES;
5047	bool link_startup_again = false;
5048
5049	/*
5050	* If UFS device isn't active then we will have to issue link startup
5051	* 2 times to make sure the device state move to active.
5052	*/
5053	if (!(hba->quirks & UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE) &&
5054	!ufshcd_is_ufs_dev_active(hba))
5055	link_startup_again = true;
5056
5057	link_startup:
5058	do {
5059	ufshcd_vops_link_startup_notify(hba, status: PRE_CHANGE);
5060
5061	ret = ufshcd_dme_link_startup(hba);
5062
5063	/* check if device is detected by inter-connect layer */
5064	if (!ret && !ufshcd_is_device_present(hba)) {
5065	ufshcd_update_evt_hist(hba,
5066	UFS_EVT_LINK_STARTUP_FAIL,
5067	0);
5068	dev_err(hba->dev, "%s: Device not present\n", __func__);
5069	ret = -ENXIO;
5070	goto out;
5071	}
5072
5073	/*
5074	* DME link lost indication is only received when link is up,
5075	* but we can't be sure if the link is up until link startup
5076	* succeeds. So reset the local Uni-Pro and try again.
5077	*/
5078	if (ret && retries && ufshcd_hba_enable(hba)) {
5079	ufshcd_update_evt_hist(hba,
5080	UFS_EVT_LINK_STARTUP_FAIL,
5081	(u32)ret);
5082	goto out;
5083	}
5084	} while (ret && retries--);
5085
5086	if (ret) {
5087	/* failed to get the link up... retire */
5088	ufshcd_update_evt_hist(hba,
5089	UFS_EVT_LINK_STARTUP_FAIL,
5090	(u32)ret);
5091	goto out;
5092	}
5093
5094	if (link_startup_again) {
5095	link_startup_again = false;
5096	retries = DME_LINKSTARTUP_RETRIES;
5097	goto link_startup;
5098	}
5099
5100	/* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
5101	ufshcd_init_pwr_info(hba);
5102	ufshcd_print_pwr_info(hba);
5103
5104	if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
5105	ret = ufshcd_disable_device_tx_lcc(hba);
5106	if (ret)
5107	goto out;
5108	}
5109
5110	/* Include any host controller configuration via UIC commands */
5111	ret = ufshcd_vops_link_startup_notify(hba, status: POST_CHANGE);
5112	if (ret)
5113	goto out;
5114
5115	/* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
5116	ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5117	ret = ufshcd_make_hba_operational(hba);
5118	out:
5119	if (ret)
5120	dev_err(hba->dev, "link startup failed %d\n", ret);
5121	return ret;
5122	}
5123
5124	/**
5125	* ufshcd_verify_dev_init() - Verify device initialization
5126	* @hba: per-adapter instance
5127	*
5128	* Send NOP OUT UPIU and wait for NOP IN response to check whether the
5129	* device Transport Protocol (UTP) layer is ready after a reset.
5130	* If the UTP layer at the device side is not initialized, it may
5131	* not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
5132	* and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
5133	*
5134	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
5135	* < 0 if another error occurred.
5136	*/
5137	static int ufshcd_verify_dev_init(struct ufs_hba *hba)
5138	{
5139	int err = 0;
5140	int retries;
5141
5142	ufshcd_dev_man_lock(hba);
5143
5144	for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
5145	err = ufshcd_exec_dev_cmd(hba, cmd_type: DEV_CMD_TYPE_NOP,
5146	timeout: hba->nop_out_timeout);
5147
5148	if (!err || err == -ETIMEDOUT)
5149	break;
5150
5151	dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
5152	}
5153
5154	ufshcd_dev_man_unlock(hba);
5155
5156	if (err)
5157	dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
5158	return err;
5159	}
5160
5161	/**
5162	* ufshcd_setup_links - associate link b/w device wlun and other luns
5163	* @sdev: pointer to SCSI device
5164	* @hba: pointer to ufs hba
5165	*/
5166	static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
5167	{
5168	struct device_link *link;
5169
5170	/*
5171	* Device wlun is the supplier & rest of the luns are consumers.
5172	* This ensures that device wlun suspends after all other luns.
5173	*/
5174	if (hba->ufs_device_wlun) {
5175	link = device_link_add(consumer: &sdev->sdev_gendev,
5176	supplier: &hba->ufs_device_wlun->sdev_gendev,
5177	DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
5178	if (!link) {
5179	dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
5180	dev_name(&hba->ufs_device_wlun->sdev_gendev));
5181	return;
5182	}
5183	hba->luns_avail--;
5184	/* Ignore REPORT_LUN wlun probing */
5185	if (hba->luns_avail == 1) {
5186	ufshcd_rpm_put(hba);
5187	return;
5188	}
5189	} else {
5190	/*
5191	* Device wlun is probed. The assumption is that WLUNs are
5192	* scanned before other LUNs.
5193	*/
5194	hba->luns_avail--;
5195	}
5196	}
5197
5198	/**
5199	* ufshcd_lu_init - Initialize the relevant parameters of the LU
5200	* @hba: per-adapter instance
5201	* @sdev: pointer to SCSI device
5202	*/
5203	static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
5204	{
5205	int len = QUERY_DESC_MAX_SIZE;
5206	u8 lun = ufshcd_scsi_to_upiu_lun(scsi_lun: sdev->lun);
5207	u8 lun_qdepth = hba->nutrs;
5208	u8 *desc_buf;
5209	int ret;
5210
5211	desc_buf = kzalloc(len, GFP_KERNEL);
5212	if (!desc_buf)
5213	goto set_qdepth;
5214
5215	ret = ufshcd_read_unit_desc_param(hba, lun, param_offset: 0, param_read_buf: desc_buf, param_size: len);
5216	if (ret < 0) {
5217	if (ret == -EOPNOTSUPP)
5218	/* If LU doesn't support unit descriptor, its queue depth is set to 1 */
5219	lun_qdepth = 1;
5220	kfree(objp: desc_buf);
5221	goto set_qdepth;
5222	}
5223
5224	if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
5225	/*
5226	* In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
5227	* use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
5228	*/
5229	lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
5230	}
5231	/*
5232	* According to UFS device specification, the write protection mode is only supported by
5233	* normal LU, not supported by WLUN.
5234	*/
5235	if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
5236	!hba->dev_info.is_lu_power_on_wp &&
5237	desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
5238	hba->dev_info.is_lu_power_on_wp = true;
5239
5240	/* In case of RPMB LU, check if advanced RPMB mode is enabled, and get region size */
5241	if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN) {
5242	if (desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
5243	hba->dev_info.b_advanced_rpmb_en = true;
5244	hba->dev_info.rpmb_region_size[0] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION0_SIZE];
5245	hba->dev_info.rpmb_region_size[1] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION1_SIZE];
5246	hba->dev_info.rpmb_region_size[2] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION2_SIZE];
5247	hba->dev_info.rpmb_region_size[3] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION3_SIZE];
5248	}
5249
5250
5251	kfree(objp: desc_buf);
5252	set_qdepth:
5253	/*
5254	* For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
5255	* bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
5256	*/
5257	dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
5258	scsi_change_queue_depth(sdev, lun_qdepth);
5259	}
5260
5261	/**
5262	* ufshcd_sdev_init - handle initial SCSI device configurations
5263	* @sdev: pointer to SCSI device
5264	*
5265	* Return: success.
5266	*/
5267	static int ufshcd_sdev_init(struct scsi_device *sdev)
5268	{
5269	struct ufs_hba *hba;
5270
5271	hba = shost_priv(shost: sdev->host);
5272
5273	/* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
5274	sdev->use_10_for_ms = 1;
5275
5276	/* DBD field should be set to 1 in mode sense(10) */
5277	sdev->set_dbd_for_ms = 1;
5278
5279	/* allow SCSI layer to restart the device in case of errors */
5280	sdev->allow_restart = 1;
5281
5282	/* REPORT SUPPORTED OPERATION CODES is not supported */
5283	sdev->no_report_opcodes = 1;
5284
5285	/* WRITE_SAME command is not supported */
5286	sdev->no_write_same = 1;
5287
5288	ufshcd_lu_init(hba, sdev);
5289
5290	ufshcd_setup_links(hba, sdev);
5291
5292	return 0;
5293	}
5294
5295	/**
5296	* ufshcd_change_queue_depth - change queue depth
5297	* @sdev: pointer to SCSI device
5298	* @depth: required depth to set
5299	*
5300	* Change queue depth and make sure the max. limits are not crossed.
5301	*
5302	* Return: new queue depth.
5303	*/
5304	static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5305	{
5306	return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5307	}
5308
5309	/**
5310	* ufshcd_sdev_configure - adjust SCSI device configurations
5311	* @sdev: pointer to SCSI device
5312	* @lim: queue limits
5313	*
5314	* Return: 0 (success).
5315	*/
5316	static int ufshcd_sdev_configure(struct scsi_device *sdev,
5317	struct queue_limits *lim)
5318	{
5319	struct ufs_hba *hba = shost_priv(shost: sdev->host);
5320	struct request_queue *q = sdev->request_queue;
5321
5322	lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1;
5323
5324	/*
5325	* Block runtime-pm until all consumers are added.
5326	* Refer ufshcd_setup_links().
5327	*/
5328	if (is_device_wlun(sdev))
5329	pm_runtime_get_noresume(dev: &sdev->sdev_gendev);
5330	else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5331	sdev->rpm_autosuspend = 1;
5332	/*
5333	* Do not print messages during runtime PM to avoid never-ending cycles
5334	* of messages written back to storage by user space causing runtime
5335	* resume, causing more messages and so on.
5336	*/
5337	sdev->silence_suspend = 1;
5338
5339	if (hba->vops && hba->vops->config_scsi_dev)
5340	hba->vops->config_scsi_dev(sdev);
5341
5342	ufshcd_crypto_register(hba, q);
5343
5344	return 0;
5345	}
5346
5347	/**
5348	* ufshcd_sdev_destroy - remove SCSI device configurations
5349	* @sdev: pointer to SCSI device
5350	*/
5351	static void ufshcd_sdev_destroy(struct scsi_device *sdev)
5352	{
5353	struct ufs_hba *hba;
5354	unsigned long flags;
5355
5356	hba = shost_priv(shost: sdev->host);
5357
5358	/* Drop the reference as it won't be needed anymore */
5359	if (ufshcd_scsi_to_upiu_lun(scsi_lun: sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5360	spin_lock_irqsave(hba->host->host_lock, flags);
5361	hba->ufs_device_wlun = NULL;
5362	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
5363	} else if (hba->ufs_device_wlun) {
5364	struct device *supplier = NULL;
5365
5366	/* Ensure UFS Device WLUN exists and does not disappear */
5367	spin_lock_irqsave(hba->host->host_lock, flags);
5368	if (hba->ufs_device_wlun) {
5369	supplier = &hba->ufs_device_wlun->sdev_gendev;
5370	get_device(dev: supplier);
5371	}
5372	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
5373
5374	if (supplier) {
5375	/*
5376	* If a LUN fails to probe (e.g. absent BOOT WLUN), the
5377	* device will not have been registered but can still
5378	* have a device link holding a reference to the device.
5379	*/
5380	device_link_remove(consumer: &sdev->sdev_gendev, supplier);
5381	put_device(dev: supplier);
5382	}
5383	}
5384	}
5385
5386	/**
5387	* ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5388	* @cmd: SCSI command
5389	* @scsi_status: SCSI command status
5390	*
5391	* Return: value base on SCSI command status.
5392	*/
5393	static inline int ufshcd_scsi_cmd_status(struct scsi_cmnd *cmd, int scsi_status)
5394	{
5395	int result = 0;
5396
5397	switch (scsi_status) {
5398	case SAM_STAT_CHECK_CONDITION:
5399	ufshcd_copy_sense_data(cmd);
5400	fallthrough;
5401	case SAM_STAT_GOOD:
5402	result |= DID_OK << 16 | scsi_status;
5403	break;
5404	case SAM_STAT_TASK_SET_FULL:
5405	case SAM_STAT_BUSY:
5406	case SAM_STAT_TASK_ABORTED:
5407	ufshcd_copy_sense_data(cmd);
5408	result |= scsi_status;
5409	break;
5410	default:
5411	result |= DID_ERROR << 16;
5412	break;
5413	} /* end of switch */
5414
5415	return result;
5416	}
5417
5418	/**
5419	* ufshcd_transfer_rsp_status - Get overall status of the response
5420	* @hba: per adapter instance
5421	* @cmd: SCSI command
5422	* @cqe: pointer to the completion queue entry
5423	*
5424	* Return: result of the command to notify SCSI midlayer.
5425	*/
5426	static inline int ufshcd_transfer_rsp_status(struct ufs_hba *hba,
5427	struct scsi_cmnd *cmd,
5428	struct cq_entry *cqe)
5429	{
5430	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
5431	const int tag = scsi_cmd_to_rq(scmd: cmd)->tag;
5432	int result = 0;
5433	int scsi_status;
5434	enum utp_ocs ocs;
5435	u8 upiu_flags;
5436	u32 resid;
5437
5438	upiu_flags = lrbp->ucd_rsp_ptr->header.flags;
5439	resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count);
5440	/*
5441	* Test !overflow instead of underflow to support UFS devices that do
5442	* not set either flag.
5443	*/
5444	if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW))
5445	scsi_set_resid(cmd, resid);
5446
5447	/* overall command status of utrd */
5448	ocs = ufshcd_get_tr_ocs(lrbp, cqe);
5449
5450	if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5451	if (lrbp->ucd_rsp_ptr->header.response ||
5452	lrbp->ucd_rsp_ptr->header.status)
5453	ocs = OCS_SUCCESS;
5454	}
5455
5456	switch (ocs) {
5457	case OCS_SUCCESS:
5458	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(secs: 0, nsecs: 0);
5459	switch (ufshcd_get_req_rsp(ucd_rsp_ptr: lrbp->ucd_rsp_ptr)) {
5460	case UPIU_TRANSACTION_RESPONSE:
5461	/*
5462	* get the result based on SCSI status response
5463	* to notify the SCSI midlayer of the command status
5464	*/
5465	scsi_status = lrbp->ucd_rsp_ptr->header.status;
5466	result = ufshcd_scsi_cmd_status(cmd, scsi_status);
5467
5468	/*
5469	* Currently we are only supporting BKOPs exception
5470	* events hence we can ignore BKOPs exception event
5471	* during power management callbacks. BKOPs exception
5472	* event is not expected to be raised in runtime suspend
5473	* callback as it allows the urgent bkops.
5474	* During system suspend, we are anyway forcefully
5475	* disabling the bkops and if urgent bkops is needed
5476	* it will be enabled on system resume. Long term
5477	* solution could be to abort the system suspend if
5478	* UFS device needs urgent BKOPs.
5479	*/
5480	if (!hba->pm_op_in_progress &&
5481	!ufshcd_eh_in_progress(hba) &&
5482	ufshcd_is_exception_event(ucd_rsp_ptr: lrbp->ucd_rsp_ptr))
5483	/* Flushed in suspend */
5484	schedule_work(work: &hba->eeh_work);
5485	break;
5486	case UPIU_TRANSACTION_REJECT_UPIU:
5487	/* TODO: handle Reject UPIU Response */
5488	result = DID_ERROR << 16;
5489	dev_err(hba->dev,
5490	"Reject UPIU not fully implemented\n");
5491	break;
5492	default:
5493	dev_err(hba->dev,
5494	"Unexpected request response code = %x\n",
5495	result);
5496	result = DID_ERROR << 16;
5497	break;
5498	}
5499	break;
5500	case OCS_ABORTED:
5501	case OCS_INVALID_COMMAND_STATUS:
5502	result |= DID_REQUEUE << 16;
5503	dev_warn(hba->dev, "OCS %s from controller for tag %d\n",
5504	ocs == OCS_ABORTED ? "aborted" : "invalid", tag);
5505	break;
5506	case OCS_INVALID_CMD_TABLE_ATTR:
5507	case OCS_INVALID_PRDT_ATTR:
5508	case OCS_MISMATCH_DATA_BUF_SIZE:
5509	case OCS_MISMATCH_RESP_UPIU_SIZE:
5510	case OCS_PEER_COMM_FAILURE:
5511	case OCS_FATAL_ERROR:
5512	case OCS_DEVICE_FATAL_ERROR:
5513	case OCS_INVALID_CRYPTO_CONFIG:
5514	case OCS_GENERAL_CRYPTO_ERROR:
5515	default:
5516	result |= DID_ERROR << 16;
5517	dev_err(hba->dev, "OCS error from controller = %x for tag %d\n",
5518	ocs, tag);
5519	ufshcd_print_evt_hist(hba);
5520	ufshcd_print_host_state(hba);
5521	break;
5522	} /* end of switch */
5523
5524	if ((host_byte(result) != DID_OK) &&
5525	(host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) {
5526	if (cqe)
5527	ufshcd_hex_dump("UPIU CQE: ", cqe, sizeof(struct cq_entry));
5528	ufshcd_print_tr(hba, cmd, pr_prdt: true);
5529	}
5530	return result;
5531	}
5532
5533	static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5534	u32 intr_mask)
5535	{
5536	if (!ufshcd_is_auto_hibern8_supported(hba) ||
5537	!ufshcd_is_auto_hibern8_enabled(hba))
5538	return false;
5539
5540	if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5541	return false;
5542
5543	if (hba->active_uic_cmd &&
5544	(hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5545	hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5546	return false;
5547
5548	return true;
5549	}
5550
5551	/**
5552	* ufshcd_uic_cmd_compl - handle completion of uic command
5553	* @hba: per adapter instance
5554	* @intr_status: interrupt status generated by the controller
5555	*
5556	* Return:
5557	* IRQ_HANDLED - If interrupt is valid
5558	* IRQ_NONE - If invalid interrupt
5559	*/
5560	static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5561	{
5562	irqreturn_t retval = IRQ_NONE;
5563	struct uic_command *cmd;
5564
5565	guard(spinlock_irqsave)(l: hba->host->host_lock);
5566	cmd = hba->active_uic_cmd;
5567	if (!cmd)
5568	return retval;
5569
5570	if (ufshcd_is_auto_hibern8_error(hba, intr_mask: intr_status))
5571	hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5572
5573	if (intr_status & UIC_COMMAND_COMPL) {
5574	cmd->argument2 |= ufshcd_get_uic_cmd_result(hba);
5575	cmd->argument3 = ufshcd_get_dme_attr_val(hba);
5576	if (!hba->uic_async_done)
5577	cmd->cmd_active = false;
5578	complete(&cmd->done);
5579	retval = IRQ_HANDLED;
5580	}
5581
5582	if (intr_status & UFSHCD_UIC_PWR_MASK && hba->uic_async_done) {
5583	cmd->cmd_active = false;
5584	complete(hba->uic_async_done);
5585	retval = IRQ_HANDLED;
5586	}
5587
5588	if (retval == IRQ_HANDLED)
5589	ufshcd_add_uic_command_trace(hba, ucmd: cmd, str_t: UFS_CMD_COMP);
5590
5591	return retval;
5592	}
5593
5594	/* Release the resources allocated for processing a SCSI command. */
5595	void ufshcd_release_scsi_cmd(struct ufs_hba *hba, struct scsi_cmnd *cmd)
5596	{
5597	scsi_dma_unmap(cmd);
5598	ufshcd_crypto_clear_prdt(hba, cmd);
5599	ufshcd_release(hba);
5600	ufshcd_clk_scaling_update_busy(hba);
5601	}
5602
5603	/**
5604	* ufshcd_compl_one_cqe - handle a completion queue entry
5605	* @hba: per adapter instance
5606	* @task_tag: the task tag of the request to be completed
5607	* @cqe: pointer to the completion queue entry
5608	*/
5609	void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag,
5610	struct cq_entry *cqe)
5611	{
5612	struct scsi_cmnd *cmd = ufshcd_tag_to_cmd(hba, tag: task_tag);
5613	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
5614	enum utp_ocs ocs;
5615
5616	if (WARN_ONCE(!cmd, "cqe->command_desc_base_addr = %#llx\n",
5617	le64_to_cpu(cqe->command_desc_base_addr)))
5618	return;
5619
5620	if (hba->monitor.enabled) {
5621	lrbp->compl_time_stamp = ktime_get();
5622	lrbp->compl_time_stamp_local_clock = local_clock();
5623	}
5624	if (ufshcd_is_scsi_cmd(cmd)) {
5625	if (unlikely(ufshcd_should_inform_monitor(hba, cmd)))
5626	ufshcd_update_monitor(hba, cmd);
5627	ufshcd_add_command_trace(hba, cmd, str_t: UFS_CMD_COMP);
5628	cmd->result = ufshcd_transfer_rsp_status(hba, cmd, cqe);
5629	ufshcd_release_scsi_cmd(hba, cmd);
5630	} else {
5631	if (cqe) {
5632	ocs = cqe->overall_status & MASK_OCS;
5633	lrbp->utr_descriptor_ptr->header.ocs = ocs;
5634	} else {
5635	ocs = lrbp->utr_descriptor_ptr->header.ocs;
5636	}
5637	ufshcd_add_query_upiu_trace(
5638	hba,
5639	str_t: ocs == OCS_SUCCESS ? UFS_QUERY_COMP : UFS_QUERY_ERR,
5640	rq_rsp: (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
5641	cmd->result = 0;
5642	}
5643	/* Do not touch lrbp after scsi_done() has been called. */
5644	scsi_done(cmd);
5645	}
5646
5647	/**
5648	* __ufshcd_transfer_req_compl - handle SCSI and query command completion
5649	* @hba: per adapter instance
5650	* @completed_reqs: bitmask that indicates which requests to complete
5651	*/
5652	static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5653	unsigned long completed_reqs)
5654	{
5655	int tag;
5656
5657	for_each_set_bit(tag, &completed_reqs, hba->nutrs)
5658	ufshcd_compl_one_cqe(hba, task_tag: tag, NULL);
5659	}
5660
5661	/* Any value that is not an existing queue number is fine for this constant. */
5662	enum {
5663	UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5664	};
5665
5666	static void ufshcd_clear_polled(struct ufs_hba *hba,
5667	unsigned long *completed_reqs)
5668	{
5669	int tag;
5670
5671	for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5672	struct scsi_cmnd *cmd = scsi_host_find_tag(shost: hba->host, tag);
5673
5674	if (!cmd)
5675	continue;
5676	if (scsi_cmd_to_rq(scmd: cmd)->cmd_flags & REQ_POLLED)
5677	__clear_bit(tag, completed_reqs);
5678	}
5679	}
5680
5681	/*
5682	* Return: > 0 if one or more commands have been completed or 0 if no
5683	* requests have been completed.
5684	*/
5685	static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5686	{
5687	struct ufs_hba *hba = shost_priv(shost);
5688	unsigned long completed_reqs, flags;
5689	u32 tr_doorbell;
5690	struct ufs_hw_queue *hwq;
5691
5692	if (hba->mcq_enabled) {
5693	hwq = &hba->uhq[queue_num];
5694
5695	return ufshcd_mcq_poll_cqe_lock(hba, hwq);
5696	}
5697
5698	spin_lock_irqsave(&hba->outstanding_lock, flags);
5699	tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5700	completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5701	WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5702	"completed: %#lx; outstanding: %#lx\n", completed_reqs,
5703	hba->outstanding_reqs);
5704	if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5705	/* Do not complete polled requests from interrupt context. */
5706	ufshcd_clear_polled(hba, completed_reqs: &completed_reqs);
5707	}
5708	hba->outstanding_reqs &= ~completed_reqs;
5709	spin_unlock_irqrestore(lock: &hba->outstanding_lock, flags);
5710
5711	if (completed_reqs)
5712	__ufshcd_transfer_req_compl(hba, completed_reqs);
5713
5714	return completed_reqs != 0;
5715	}
5716
5717	static bool ufshcd_mcq_force_compl_one(struct request *rq, void *priv)
5718	{
5719	struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq);
5720	struct scsi_device *sdev = rq->q->queuedata;
5721	struct Scsi_Host *shost = sdev->host;
5722	struct ufs_hba *hba = shost_priv(shost);
5723	struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, req: rq);
5724
5725	if (blk_mq_is_reserved_rq(rq) || !hwq)
5726	return true;
5727
5728	ufshcd_mcq_compl_all_cqes_lock(hba, hwq);
5729
5730	/*
5731	* For those cmds of which the cqes are not present in the cq, complete
5732	* them explicitly.
5733	*/
5734	scoped_guard(spinlock_irqsave, &hwq->cq_lock) {
5735	if (!test_bit(SCMD_STATE_COMPLETE, &cmd->state)) {
5736	set_host_byte(cmd, status: DID_REQUEUE);
5737	ufshcd_release_scsi_cmd(hba, cmd);
5738	scsi_done(cmd);
5739	}
5740	}
5741
5742	return true;
5743	}
5744
5745	static bool ufshcd_mcq_compl_one(struct request *rq, void *priv)
5746	{
5747	struct scsi_device *sdev = rq->q->queuedata;
5748	struct Scsi_Host *shost = sdev->host;
5749	struct ufs_hba *hba = shost_priv(shost);
5750	struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, req: rq);
5751
5752	if (!blk_mq_is_reserved_rq(rq) && hwq)
5753	ufshcd_mcq_poll_cqe_lock(hba, hwq);
5754
5755	return true;
5756	}
5757
5758	/**
5759	* ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is
5760	* invoked from the error handler context or ufshcd_host_reset_and_restore()
5761	* to complete the pending transfers and free the resources associated with
5762	* the scsi command.
5763	*
5764	* @hba: per adapter instance
5765	* @force_compl: This flag is set to true when invoked
5766	* from ufshcd_host_reset_and_restore() in which case it requires special
5767	* handling because the host controller has been reset by ufshcd_hba_stop().
5768	*/
5769	static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba,
5770	bool force_compl)
5771	{
5772	blk_mq_tagset_busy_iter(tagset: &hba->host->tag_set,
5773	fn: force_compl ? ufshcd_mcq_force_compl_one :
5774	ufshcd_mcq_compl_one,
5775	NULL);
5776	}
5777
5778	/**
5779	* ufshcd_transfer_req_compl - handle SCSI and query command completion
5780	* @hba: per adapter instance
5781	*
5782	* Return:
5783	* IRQ_HANDLED - If interrupt is valid
5784	* IRQ_NONE - If invalid interrupt
5785	*/
5786	static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5787	{
5788	/* Resetting interrupt aggregation counters first and reading the
5789	* DOOR_BELL afterward allows us to handle all the completed requests.
5790	* In order to prevent other interrupts starvation the DB is read once
5791	* after reset. The down side of this solution is the possibility of
5792	* false interrupt if device completes another request after resetting
5793	* aggregation and before reading the DB.
5794	*/
5795	if (ufshcd_is_intr_aggr_allowed(hba) &&
5796	!(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5797	ufshcd_reset_intr_aggr(hba);
5798
5799	if (ufs_fail_completion(hba))
5800	return IRQ_HANDLED;
5801
5802	/*
5803	* Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5804	* do not want polling to trigger spurious interrupt complaints.
5805	*/
5806	ufshcd_poll(shost: hba->host, queue_num: UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
5807
5808	return IRQ_HANDLED;
5809	}
5810
5811	int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5812	{
5813	return ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_WRITE_ATTR,
5814	idn: QUERY_ATTR_IDN_EE_CONTROL, index: 0, selector: 0,
5815	attr_val: &ee_ctrl_mask);
5816	}
5817
5818	int ufshcd_write_ee_control(struct ufs_hba *hba)
5819	{
5820	int err;
5821
5822	mutex_lock(&hba->ee_ctrl_mutex);
5823	err = __ufshcd_write_ee_control(hba, ee_ctrl_mask: hba->ee_ctrl_mask);
5824	mutex_unlock(lock: &hba->ee_ctrl_mutex);
5825	if (err)
5826	dev_err(hba->dev, "%s: failed to write ee control %d\n",
5827	__func__, err);
5828	return err;
5829	}
5830
5831	int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5832	const u16 *other_mask, u16 set, u16 clr)
5833	{
5834	u16 new_mask, ee_ctrl_mask;
5835	int err = 0;
5836
5837	mutex_lock(&hba->ee_ctrl_mutex);
5838	new_mask = (*mask & ~clr) | set;
5839	ee_ctrl_mask = new_mask | *other_mask;
5840	if (ee_ctrl_mask != hba->ee_ctrl_mask)
5841	err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5842	/* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5843	if (!err) {
5844	hba->ee_ctrl_mask = ee_ctrl_mask;
5845	*mask = new_mask;
5846	}
5847	mutex_unlock(lock: &hba->ee_ctrl_mutex);
5848	return err;
5849	}
5850
5851	/**
5852	* ufshcd_disable_ee - disable exception event
5853	* @hba: per-adapter instance
5854	* @mask: exception event to disable
5855	*
5856	* Disables exception event in the device so that the EVENT_ALERT
5857	* bit is not set.
5858	*
5859	* Return: zero on success, non-zero error value on failure.
5860	*/
5861	static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5862	{
5863	return ufshcd_update_ee_drv_mask(hba, set: 0, clr: mask);
5864	}
5865
5866	/**
5867	* ufshcd_enable_ee - enable exception event
5868	* @hba: per-adapter instance
5869	* @mask: exception event to enable
5870	*
5871	* Enable corresponding exception event in the device to allow
5872	* device to alert host in critical scenarios.
5873	*
5874	* Return: zero on success, non-zero error value on failure.
5875	*/
5876	static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5877	{
5878	return ufshcd_update_ee_drv_mask(hba, set: mask, clr: 0);
5879	}
5880
5881	/**
5882	* ufshcd_enable_auto_bkops - Allow device managed BKOPS
5883	* @hba: per-adapter instance
5884	*
5885	* Allow device to manage background operations on its own. Enabling
5886	* this might lead to inconsistent latencies during normal data transfers
5887	* as the device is allowed to manage its own way of handling background
5888	* operations.
5889	*
5890	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
5891	* < 0 if another error occurred.
5892	*/
5893	static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5894	{
5895	int err = 0;
5896
5897	if (hba->auto_bkops_enabled)
5898	goto out;
5899
5900	err = ufshcd_query_flag_retry(hba, opcode: UPIU_QUERY_OPCODE_SET_FLAG,
5901	idn: QUERY_FLAG_IDN_BKOPS_EN, index: 0, NULL);
5902	if (err) {
5903	dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5904	__func__, err);
5905	goto out;
5906	}
5907
5908	hba->auto_bkops_enabled = true;
5909	trace_ufshcd_auto_bkops_state(hba, state: "Enabled");
5910
5911	/* No need of URGENT_BKOPS exception from the device */
5912	err = ufshcd_disable_ee(hba, mask: MASK_EE_URGENT_BKOPS);
5913	if (err)
5914	dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5915	__func__, err);
5916	out:
5917	return err;
5918	}
5919
5920	/**
5921	* ufshcd_disable_auto_bkops - block device in doing background operations
5922	* @hba: per-adapter instance
5923	*
5924	* Disabling background operations improves command response latency but
5925	* has drawback of device moving into critical state where the device is
5926	* not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5927	* host is idle so that BKOPS are managed effectively without any negative
5928	* impacts.
5929	*
5930	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
5931	* < 0 if another error occurred.
5932	*/
5933	static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5934	{
5935	int err = 0;
5936
5937	if (!hba->auto_bkops_enabled)
5938	goto out;
5939
5940	/*
5941	* If host assisted BKOPs is to be enabled, make sure
5942	* urgent bkops exception is allowed.
5943	*/
5944	err = ufshcd_enable_ee(hba, mask: MASK_EE_URGENT_BKOPS);
5945	if (err) {
5946	dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5947	__func__, err);
5948	goto out;
5949	}
5950
5951	err = ufshcd_query_flag_retry(hba, opcode: UPIU_QUERY_OPCODE_CLEAR_FLAG,
5952	idn: QUERY_FLAG_IDN_BKOPS_EN, index: 0, NULL);
5953	if (err) {
5954	dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5955	__func__, err);
5956	ufshcd_disable_ee(hba, mask: MASK_EE_URGENT_BKOPS);
5957	goto out;
5958	}
5959
5960	hba->auto_bkops_enabled = false;
5961	trace_ufshcd_auto_bkops_state(hba, state: "Disabled");
5962	hba->is_urgent_bkops_lvl_checked = false;
5963	out:
5964	return err;
5965	}
5966
5967	/**
5968	* ufshcd_force_reset_auto_bkops - force reset auto bkops state
5969	* @hba: per adapter instance
5970	*
5971	* After a device reset the device may toggle the BKOPS_EN flag
5972	* to default value. The s/w tracking variables should be updated
5973	* as well. This function would change the auto-bkops state based on
5974	* UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5975	*/
5976	static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5977	{
5978	if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5979	hba->auto_bkops_enabled = false;
5980	hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5981	ufshcd_enable_auto_bkops(hba);
5982	} else {
5983	hba->auto_bkops_enabled = true;
5984	hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5985	ufshcd_disable_auto_bkops(hba);
5986	}
5987	hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5988	hba->is_urgent_bkops_lvl_checked = false;
5989	}
5990
5991	static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5992	{
5993	return ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
5994	idn: QUERY_ATTR_IDN_BKOPS_STATUS, index: 0, selector: 0, attr_val: status);
5995	}
5996
5997	/**
5998	* ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5999	* @hba: per-adapter instance
6000	*
6001	* Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
6002	* flag in the device to permit background operations if the device
6003	* bkops_status is greater than or equal to the "hba->urgent_bkops_lvl",
6004	* disable otherwise.
6005	*
6006	* Return: 0 for success, non-zero in case of failure.
6007	*
6008	* NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
6009	* to know whether auto bkops is enabled or disabled after this function
6010	* returns control to it.
6011	*/
6012	static int ufshcd_bkops_ctrl(struct ufs_hba *hba)
6013	{
6014	enum bkops_status status = hba->urgent_bkops_lvl;
6015	u32 curr_status = 0;
6016	int err;
6017
6018	err = ufshcd_get_bkops_status(hba, status: &curr_status);
6019	if (err) {
6020	dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
6021	__func__, err);
6022	goto out;
6023	} else if (curr_status > BKOPS_STATUS_MAX) {
6024	dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
6025	__func__, curr_status);
6026	err = -EINVAL;
6027	goto out;
6028	}
6029
6030	if (curr_status >= status)
6031	err = ufshcd_enable_auto_bkops(hba);
6032	else
6033	err = ufshcd_disable_auto_bkops(hba);
6034	out:
6035	return err;
6036	}
6037
6038	static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
6039	{
6040	return ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
6041	idn: QUERY_ATTR_IDN_EE_STATUS, index: 0, selector: 0, attr_val: status);
6042	}
6043
6044	static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
6045	{
6046	int err;
6047	u32 curr_status = 0;
6048
6049	if (hba->is_urgent_bkops_lvl_checked)
6050	goto enable_auto_bkops;
6051
6052	err = ufshcd_get_bkops_status(hba, status: &curr_status);
6053	if (err) {
6054	dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
6055	__func__, err);
6056	goto out;
6057	}
6058
6059	/*
6060	* We are seeing that some devices are raising the urgent bkops
6061	* exception events even when BKOPS status doesn't indicate performace
6062	* impacted or critical. Handle these device by determining their urgent
6063	* bkops status at runtime.
6064	*/
6065	if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
6066	dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
6067	__func__, curr_status);
6068	/* update the current status as the urgent bkops level */
6069	hba->urgent_bkops_lvl = curr_status;
6070	hba->is_urgent_bkops_lvl_checked = true;
6071	}
6072
6073	enable_auto_bkops:
6074	err = ufshcd_enable_auto_bkops(hba);
6075	out:
6076	if (err < 0)
6077	dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
6078	__func__, err);
6079	}
6080
6081	/*
6082	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
6083	* < 0 if another error occurred.
6084	*/
6085	int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id)
6086	{
6087	struct utp_upiu_query_v4_0 *upiu_resp;
6088	struct ufs_query_req *request = NULL;
6089	struct ufs_query_res *response = NULL;
6090	int err;
6091
6092	if (hba->dev_info.wspecversion < 0x410)
6093	return -EOPNOTSUPP;
6094
6095	ufshcd_hold(hba);
6096	mutex_lock(&hba->dev_cmd.lock);
6097
6098	ufshcd_init_query(hba, request: &request, response: &response,
6099	opcode: UPIU_QUERY_OPCODE_READ_ATTR,
6100	idn: QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID, index: 0, selector: 0);
6101
6102	request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
6103
6104	err = ufshcd_exec_dev_cmd(hba, cmd_type: DEV_CMD_TYPE_QUERY, timeout: dev_cmd_timeout);
6105
6106	if (err) {
6107	dev_err(hba->dev, "%s: failed to read device level exception %d\n",
6108	__func__, err);
6109	goto out;
6110	}
6111
6112	upiu_resp = (struct utp_upiu_query_v4_0 *)response;
6113	*exception_id = get_unaligned_be64(p: &upiu_resp->osf3);
6114	out:
6115	mutex_unlock(lock: &hba->dev_cmd.lock);
6116	ufshcd_release(hba);
6117
6118	return err;
6119	}
6120
6121	static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
6122	{
6123	u8 index;
6124	enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
6125	UPIU_QUERY_OPCODE_CLEAR_FLAG;
6126
6127	index = ufshcd_wb_get_query_index(hba);
6128	return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
6129	}
6130
6131	int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
6132	{
6133	int ret;
6134
6135	if (!ufshcd_is_wb_allowed(hba) ||
6136	hba->dev_info.wb_enabled == enable)
6137	return 0;
6138
6139	ret = __ufshcd_wb_toggle(hba, set: enable, idn: QUERY_FLAG_IDN_WB_EN);
6140	if (ret) {
6141	dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
6142	__func__, enable ? "enabling" : "disabling", ret);
6143	return ret;
6144	}
6145
6146	hba->dev_info.wb_enabled = enable;
6147	dev_dbg(hba->dev, "%s: Write Booster %s\n",
6148	__func__, enable ? "enabled" : "disabled");
6149
6150	return ret;
6151	}
6152
6153	static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
6154	bool enable)
6155	{
6156	int ret;
6157
6158	ret = __ufshcd_wb_toggle(hba, set: enable,
6159	idn: QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
6160	if (ret) {
6161	dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
6162	__func__, enable ? "enabling" : "disabling", ret);
6163	return;
6164	}
6165	dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
6166	__func__, enable ? "enabled" : "disabled");
6167	}
6168
6169	int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
6170	{
6171	int ret;
6172
6173	if (!ufshcd_is_wb_allowed(hba) ||
6174	hba->dev_info.wb_buf_flush_enabled == enable)
6175	return 0;
6176
6177	ret = __ufshcd_wb_toggle(hba, set: enable, idn: QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
6178	if (ret) {
6179	dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
6180	__func__, enable ? "enabling" : "disabling", ret);
6181	return ret;
6182	}
6183
6184	hba->dev_info.wb_buf_flush_enabled = enable;
6185	dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
6186	__func__, enable ? "enabled" : "disabled");
6187
6188	return ret;
6189	}
6190
6191	int ufshcd_wb_set_resize_en(struct ufs_hba *hba, enum wb_resize_en en_mode)
6192	{
6193	int ret;
6194	u8 index;
6195
6196	index = ufshcd_wb_get_query_index(hba);
6197	ret = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_WRITE_ATTR,
6198	idn: QUERY_ATTR_IDN_WB_BUF_RESIZE_EN, index, selector: 0, attr_val: &en_mode);
6199	if (ret)
6200	dev_err(hba->dev, "%s: Enable WB buf resize operation failed %d\n",
6201	__func__, ret);
6202
6203	return ret;
6204	}
6205
6206	static bool ufshcd_wb_curr_buff_threshold_check(struct ufs_hba *hba,
6207	u32 avail_buf)
6208	{
6209	u32 cur_buf;
6210	int ret;
6211	u8 index;
6212
6213	index = ufshcd_wb_get_query_index(hba);
6214	ret = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
6215	idn: QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
6216	index, selector: 0, attr_val: &cur_buf);
6217	if (ret) {
6218	dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
6219	__func__, ret);
6220	return false;
6221	}
6222
6223	if (!cur_buf) {
6224	dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
6225	cur_buf);
6226	return false;
6227	}
6228	/* Let it continue to flush when available buffer exceeds threshold */
6229	return avail_buf < hba->vps->wb_flush_threshold;
6230	}
6231
6232	static void ufshcd_wb_force_disable(struct ufs_hba *hba)
6233	{
6234	if (ufshcd_is_wb_buf_flush_allowed(hba))
6235	ufshcd_wb_toggle_buf_flush(hba, enable: false);
6236
6237	ufshcd_wb_toggle_buf_flush_during_h8(hba, enable: false);
6238	ufshcd_wb_toggle(hba, enable: false);
6239	hba->caps &= ~UFSHCD_CAP_WB_EN;
6240
6241	dev_info(hba->dev, "%s: WB force disabled\n", __func__);
6242	}
6243
6244	static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
6245	{
6246	u32 lifetime;
6247	int ret;
6248	u8 index;
6249
6250	index = ufshcd_wb_get_query_index(hba);
6251	ret = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
6252	idn: QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
6253	index, selector: 0, attr_val: &lifetime);
6254	if (ret) {
6255	dev_err(hba->dev,
6256	"%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
6257	__func__, ret);
6258	return false;
6259	}
6260
6261	if (lifetime == UFS_WB_EXCEED_LIFETIME) {
6262	dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
6263	__func__, lifetime);
6264	return false;
6265	}
6266
6267	dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
6268	__func__, lifetime);
6269
6270	return true;
6271	}
6272
6273	static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
6274	{
6275	int ret;
6276	u32 avail_buf;
6277	u8 index;
6278
6279	if (!ufshcd_is_wb_allowed(hba))
6280	return false;
6281
6282	if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
6283	ufshcd_wb_force_disable(hba);
6284	return false;
6285	}
6286
6287	/*
6288	* With user-space reduction enabled, it's enough to enable flush
6289	* by checking only the available buffer. The threshold
6290	* defined here is > 90% full.
6291	* With user-space preserved enabled, the current-buffer
6292	* should be checked too because the wb buffer size can reduce
6293	* when disk tends to be full. This info is provided by current
6294	* buffer (dCurrentWriteBoosterBufferSize).
6295	*/
6296	index = ufshcd_wb_get_query_index(hba);
6297	ret = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
6298	idn: QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
6299	index, selector: 0, attr_val: &avail_buf);
6300	if (ret) {
6301	dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
6302	__func__, ret);
6303	return false;
6304	}
6305
6306	if (!hba->dev_info.b_presrv_uspc_en)
6307	return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
6308
6309	return ufshcd_wb_curr_buff_threshold_check(hba, avail_buf);
6310	}
6311
6312	static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
6313	{
6314	struct ufs_hba *hba = container_of(to_delayed_work(work),
6315	struct ufs_hba,
6316	rpm_dev_flush_recheck_work);
6317	/*
6318	* To prevent unnecessary VCC power drain after device finishes
6319	* WriteBooster buffer flush or Auto BKOPs, force runtime resume
6320	* after a certain delay to recheck the threshold by next runtime
6321	* suspend.
6322	*/
6323	ufshcd_rpm_get_sync(hba);
6324	ufshcd_rpm_put_sync(hba);
6325	}
6326
6327	/**
6328	* ufshcd_exception_event_handler - handle exceptions raised by device
6329	* @work: pointer to work data
6330	*
6331	* Read bExceptionEventStatus attribute from the device and handle the
6332	* exception event accordingly.
6333	*/
6334	static void ufshcd_exception_event_handler(struct work_struct *work)
6335	{
6336	struct ufs_hba *hba;
6337	int err;
6338	u32 status = 0;
6339	hba = container_of(work, struct ufs_hba, eeh_work);
6340
6341	err = ufshcd_get_ee_status(hba, status: &status);
6342	if (err) {
6343	dev_err(hba->dev, "%s: failed to get exception status %d\n",
6344	__func__, err);
6345	return;
6346	}
6347
6348	trace_ufshcd_exception_event(hba, status);
6349
6350	if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
6351	ufshcd_bkops_exception_event_handler(hba);
6352
6353	if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
6354	ufs_hwmon_notify_event(hba, ee_mask: status & MASK_EE_URGENT_TEMP);
6355
6356	if (status & hba->ee_drv_mask & MASK_EE_HEALTH_CRITICAL) {
6357	hba->critical_health_count++;
6358	sysfs_notify(kobj: &hba->dev->kobj, NULL, attr: "critical_health");
6359	}
6360
6361	if (status & hba->ee_drv_mask & MASK_EE_DEV_LVL_EXCEPTION) {
6362	atomic_inc(v: &hba->dev_lvl_exception_count);
6363	sysfs_notify(kobj: &hba->dev->kobj, NULL, attr: "device_lvl_exception_count");
6364	}
6365
6366	ufs_debugfs_exception_event(hba, status);
6367	}
6368
6369	/* Complete requests that have door-bell cleared */
6370	static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl)
6371	{
6372	if (hba->mcq_enabled)
6373	ufshcd_mcq_compl_pending_transfer(hba, force_compl);
6374	else
6375	ufshcd_transfer_req_compl(hba);
6376
6377	ufshcd_tmc_handler(hba);
6378	}
6379
6380	/**
6381	* ufshcd_quirk_dl_nac_errors - This function checks if error handling is
6382	* to recover from the DL NAC errors or not.
6383	* @hba: per-adapter instance
6384	*
6385	* Return: true if error handling is required, false otherwise.
6386	*/
6387	static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
6388	{
6389	unsigned long flags;
6390	bool err_handling = true;
6391
6392	spin_lock_irqsave(hba->host->host_lock, flags);
6393	/*
6394	* UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
6395	* device fatal error and/or DL NAC & REPLAY timeout errors.
6396	*/
6397	if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
6398	goto out;
6399
6400	if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
6401	((hba->saved_err & UIC_ERROR) &&
6402	(hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
6403	goto out;
6404
6405	if ((hba->saved_err & UIC_ERROR) &&
6406	(hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
6407	int err;
6408	/*
6409	* wait for 50ms to see if we can get any other errors or not.
6410	*/
6411	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6412	msleep(msecs: 50);
6413	spin_lock_irqsave(hba->host->host_lock, flags);
6414
6415	/*
6416	* now check if we have got any other severe errors other than
6417	* DL NAC error?
6418	*/
6419	if ((hba->saved_err & INT_FATAL_ERRORS) ||
6420	((hba->saved_err & UIC_ERROR) &&
6421	(hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6422	goto out;
6423
6424	/*
6425	* As DL NAC is the only error received so far, send out NOP
6426	* command to confirm if link is still active or not.
6427	* - If we don't get any response then do error recovery.
6428	* - If we get response then clear the DL NAC error bit.
6429	*/
6430
6431	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6432	err = ufshcd_verify_dev_init(hba);
6433	spin_lock_irqsave(hba->host->host_lock, flags);
6434
6435	if (err)
6436	goto out;
6437
6438	/* Link seems to be alive hence ignore the DL NAC errors */
6439	if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6440	hba->saved_err &= ~UIC_ERROR;
6441	/* clear NAC error */
6442	hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6443	if (!hba->saved_uic_err)
6444	err_handling = false;
6445	}
6446	out:
6447	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6448	return err_handling;
6449	}
6450
6451	/* host lock must be held before calling this func */
6452	static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6453	{
6454	return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6455	(hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6456	}
6457
6458	void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6459	{
6460	lockdep_assert_held(hba->host->host_lock);
6461
6462	/* handle fatal errors only when link is not in error state */
6463	if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6464	if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6465	ufshcd_is_saved_err_fatal(hba))
6466	hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6467	else
6468	hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6469	queue_work(wq: hba->eh_wq, work: &hba->eh_work);
6470	}
6471	}
6472
6473	void ufshcd_force_error_recovery(struct ufs_hba *hba)
6474	{
6475	spin_lock_irq(lock: hba->host->host_lock);
6476	hba->force_reset = true;
6477	ufshcd_schedule_eh_work(hba);
6478	spin_unlock_irq(lock: hba->host->host_lock);
6479	}
6480	EXPORT_SYMBOL_GPL(ufshcd_force_error_recovery);
6481
6482	static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6483	{
6484	mutex_lock(&hba->wb_mutex);
6485	down_write(sem: &hba->clk_scaling_lock);
6486	hba->clk_scaling.is_allowed = allow;
6487	up_write(sem: &hba->clk_scaling_lock);
6488	mutex_unlock(lock: &hba->wb_mutex);
6489	}
6490
6491	static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6492	{
6493	if (suspend) {
6494	if (hba->clk_scaling.is_enabled)
6495	ufshcd_suspend_clkscaling(hba);
6496	ufshcd_clk_scaling_allow(hba, allow: false);
6497	} else {
6498	ufshcd_clk_scaling_allow(hba, allow: true);
6499	if (hba->clk_scaling.is_enabled)
6500	ufshcd_resume_clkscaling(hba);
6501	}
6502	}
6503
6504	static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6505	{
6506	/*
6507	* A WLUN resume failure could potentially lead to the HBA being
6508	* runtime suspended, so take an extra reference on hba->dev.
6509	*/
6510	pm_runtime_get_sync(dev: hba->dev);
6511	ufshcd_rpm_get_sync(hba);
6512	if (pm_runtime_status_suspended(dev: &hba->ufs_device_wlun->sdev_gendev) ||
6513	hba->is_sys_suspended) {
6514	enum ufs_pm_op pm_op;
6515
6516	/*
6517	* Don't assume anything of resume, if
6518	* resume fails, irq and clocks can be OFF, and powers
6519	* can be OFF or in LPM.
6520	*/
6521	ufshcd_setup_hba_vreg(hba, on: true);
6522	ufshcd_enable_irq(hba);
6523	ufshcd_setup_vreg(hba, on: true);
6524	ufshcd_config_vreg_hpm(hba, vreg: hba->vreg_info.vccq);
6525	ufshcd_config_vreg_hpm(hba, vreg: hba->vreg_info.vccq2);
6526	ufshcd_hold(hba);
6527	if (!ufshcd_is_clkgating_allowed(hba))
6528	ufshcd_setup_clocks(hba, on: true);
6529	pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6530	ufshcd_vops_resume(hba, op: pm_op);
6531	} else {
6532	ufshcd_hold(hba);
6533	if (ufshcd_is_clkscaling_supported(hba) &&
6534	hba->clk_scaling.is_enabled)
6535	ufshcd_suspend_clkscaling(hba);
6536	ufshcd_clk_scaling_allow(hba, allow: false);
6537	}
6538	/* Wait for ongoing ufshcd_queuecommand() calls to finish. */
6539	blk_mq_quiesce_tagset(set: &hba->host->tag_set);
6540	cancel_work_sync(work: &hba->eeh_work);
6541	}
6542
6543	static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6544	{
6545	blk_mq_unquiesce_tagset(set: &hba->host->tag_set);
6546	ufshcd_release(hba);
6547	if (ufshcd_is_clkscaling_supported(hba))
6548	ufshcd_clk_scaling_suspend(hba, suspend: false);
6549	ufshcd_rpm_put(hba);
6550	pm_runtime_put(dev: hba->dev);
6551	}
6552
6553	static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6554	{
6555	return (!hba->is_powered || hba->shutting_down ||
6556	!hba->ufs_device_wlun ||
6557	hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6558	(!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6559	ufshcd_is_link_broken(hba))));
6560	}
6561
6562	#ifdef CONFIG_PM
6563	static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6564	{
6565	struct scsi_target *starget = hba->ufs_device_wlun->sdev_target;
6566	struct Scsi_Host *shost = hba->host;
6567	struct scsi_device *sdev;
6568	struct request_queue *q;
6569	bool resume_sdev_queues = false;
6570
6571	hba->is_sys_suspended = false;
6572
6573	/*
6574	* Ensure the parent's error status is cleared before proceeding
6575	* to the child, as the parent must be active to activate the child.
6576	*/
6577	if (hba->dev->power.runtime_error) {
6578	/* hba->dev has no functional parent thus simplily set RPM_ACTIVE */
6579	pm_runtime_set_active(dev: hba->dev);
6580	resume_sdev_queues = true;
6581	}
6582
6583	if (hba->ufs_device_wlun->sdev_gendev.power.runtime_error) {
6584	/*
6585	* starget, parent of wlun, might be suspended if wlun resume failed.
6586	* Make sure parent is resumed before set child (wlun) active.
6587	*/
6588	pm_runtime_get_sync(dev: &starget->dev);
6589	pm_runtime_set_active(dev: &hba->ufs_device_wlun->sdev_gendev);
6590	pm_runtime_put_sync(dev: &starget->dev);
6591	resume_sdev_queues = true;
6592	}
6593
6594	/*
6595	* If wlun device had runtime error, we also need to resume those
6596	* consumer scsi devices in case any of them has failed to be
6597	* resumed due to supplier runtime resume failure. This is to unblock
6598	* blk_queue_enter in case there are bios waiting inside it.
6599	*/
6600	if (resume_sdev_queues) {
6601	shost_for_each_device(sdev, shost) {
6602	q = sdev->request_queue;
6603	if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6604	q->rpm_status == RPM_SUSPENDING))
6605	pm_request_resume(dev: q->dev);
6606	}
6607	}
6608	}
6609	#else
6610	static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6611	{
6612	}
6613	#endif
6614
6615	static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6616	{
6617	struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6618	u32 mode;
6619
6620	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), mib_val: &mode);
6621
6622	if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6623	return true;
6624
6625	if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6626	return true;
6627
6628	return false;
6629	}
6630
6631	static bool ufshcd_abort_one(struct request *rq, void *priv)
6632	{
6633	int *ret = priv;
6634	u32 tag = rq->tag;
6635	struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq);
6636	struct scsi_device *sdev = cmd->device;
6637	struct Scsi_Host *shost = sdev->host;
6638	struct ufs_hba *hba = shost_priv(shost);
6639
6640	if (blk_mq_is_reserved_rq(rq))
6641	return true;
6642
6643	*ret = ufshcd_try_to_abort_task(hba, tag);
6644	dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6645	ufshcd_is_scsi_cmd(cmd) ? cmd->cmnd[0] : -1,
6646	*ret ? "failed" : "succeeded");
6647
6648	return *ret == 0;
6649	}
6650
6651	/**
6652	* ufshcd_abort_all - Abort all pending commands.
6653	* @hba: Host bus adapter pointer.
6654	*
6655	* Return: true if and only if the host controller needs to be reset.
6656	*/
6657	static bool ufshcd_abort_all(struct ufs_hba *hba)
6658	{
6659	int tag, ret = 0;
6660
6661	blk_mq_tagset_busy_iter(tagset: &hba->host->tag_set, fn: ufshcd_abort_one, priv: &ret);
6662	if (ret)
6663	goto out;
6664
6665	/* Clear pending task management requests */
6666	for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6667	ret = ufshcd_clear_tm_cmd(hba, tag);
6668	if (ret)
6669	goto out;
6670	}
6671
6672	out:
6673	/* Complete the requests that are cleared by s/w */
6674	ufshcd_complete_requests(hba, force_compl: false);
6675
6676	return ret != 0;
6677	}
6678
6679	/**
6680	* ufshcd_err_handler - handle UFS errors that require s/w attention
6681	* @work: pointer to work structure
6682	*/
6683	static void ufshcd_err_handler(struct work_struct *work)
6684	{
6685	int retries = MAX_ERR_HANDLER_RETRIES;
6686	struct ufs_hba *hba;
6687	unsigned long flags;
6688	bool needs_restore;
6689	bool needs_reset;
6690	int pmc_err;
6691
6692	hba = container_of(work, struct ufs_hba, eh_work);
6693
6694	dev_info(hba->dev,
6695	"%s started; HBA state %s; powered %d; shutting down %d; saved_err = 0x%x; saved_uic_err = 0x%x; force_reset = %d%s\n",
6696	__func__, ufshcd_state_name[hba->ufshcd_state],
6697	hba->is_powered, hba->shutting_down, hba->saved_err,
6698	hba->saved_uic_err, hba->force_reset,
6699	ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6700
6701	if (hba->ufs_device_wlun) {
6702	/*
6703	* Use ufshcd_rpm_get_noresume() here to safely perform link
6704	* recovery even if an error occurs during runtime suspend or
6705	* runtime resume. This avoids potential deadlocks that could
6706	* happen if we tried to resume the device while a PM operation
6707	* is already in progress.
6708	*/
6709	ufshcd_rpm_get_noresume(hba);
6710	if (hba->pm_op_in_progress) {
6711	ufshcd_link_recovery(hba);
6712	ufshcd_rpm_put(hba);
6713	return;
6714	}
6715	ufshcd_rpm_put(hba);
6716	}
6717
6718	down(sem: &hba->host_sem);
6719	spin_lock_irqsave(hba->host->host_lock, flags);
6720	if (ufshcd_err_handling_should_stop(hba)) {
6721	if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6722	hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6723	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6724	up(sem: &hba->host_sem);
6725	return;
6726	}
6727	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6728
6729	ufshcd_err_handling_prepare(hba);
6730
6731	spin_lock_irqsave(hba->host->host_lock, flags);
6732	ufshcd_set_eh_in_progress(hba);
6733	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6734
6735	/* Complete requests that have door-bell cleared by h/w */
6736	ufshcd_complete_requests(hba, force_compl: false);
6737	spin_lock_irqsave(hba->host->host_lock, flags);
6738	again:
6739	needs_restore = false;
6740	needs_reset = false;
6741
6742	if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6743	hba->ufshcd_state = UFSHCD_STATE_RESET;
6744	/*
6745	* A full reset and restore might have happened after preparation
6746	* is finished, double check whether we should stop.
6747	*/
6748	if (ufshcd_err_handling_should_stop(hba))
6749	goto skip_err_handling;
6750
6751	if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) &&
6752	!hba->force_reset) {
6753	bool ret;
6754
6755	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6756	/* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6757	ret = ufshcd_quirk_dl_nac_errors(hba);
6758	spin_lock_irqsave(hba->host->host_lock, flags);
6759	if (!ret && ufshcd_err_handling_should_stop(hba))
6760	goto skip_err_handling;
6761	}
6762
6763	if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6764	(hba->saved_uic_err &&
6765	(hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6766	bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6767
6768	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6769	ufshcd_print_host_state(hba);
6770	ufshcd_print_pwr_info(hba);
6771	ufshcd_print_evt_hist(hba);
6772	ufshcd_print_tmrs(hba, bitmap: hba->outstanding_tasks);
6773	ufshcd_print_trs_all(hba, pr_prdt);
6774	spin_lock_irqsave(hba->host->host_lock, flags);
6775	}
6776
6777	/*
6778	* if host reset is required then skip clearing the pending
6779	* transfers forcefully because they will get cleared during
6780	* host reset and restore
6781	*/
6782	if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6783	ufshcd_is_saved_err_fatal(hba) ||
6784	((hba->saved_err & UIC_ERROR) &&
6785	(hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6786	UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6787	needs_reset = true;
6788	goto do_reset;
6789	}
6790
6791	/*
6792	* If LINERESET was caught, UFS might have been put to PWM mode,
6793	* check if power mode restore is needed.
6794	*/
6795	if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6796	hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6797	if (!hba->saved_uic_err)
6798	hba->saved_err &= ~UIC_ERROR;
6799	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6800	if (ufshcd_is_pwr_mode_restore_needed(hba))
6801	needs_restore = true;
6802	spin_lock_irqsave(hba->host->host_lock, flags);
6803	if (!hba->saved_err && !needs_restore)
6804	goto skip_err_handling;
6805	}
6806
6807	hba->silence_err_logs = true;
6808	/* release lock as clear command might sleep */
6809	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6810
6811	needs_reset = ufshcd_abort_all(hba);
6812
6813	spin_lock_irqsave(hba->host->host_lock, flags);
6814	hba->silence_err_logs = false;
6815	if (needs_reset)
6816	goto do_reset;
6817
6818	/*
6819	* After all reqs and tasks are cleared from doorbell,
6820	* now it is safe to retore power mode.
6821	*/
6822	if (needs_restore) {
6823	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6824	/*
6825	* Hold the scaling lock just in case dev cmds
6826	* are sent via bsg and/or sysfs.
6827	*/
6828	down_write(sem: &hba->clk_scaling_lock);
6829	hba->force_pmc = true;
6830	pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6831	if (pmc_err) {
6832	needs_reset = true;
6833	dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6834	__func__, pmc_err);
6835	}
6836	hba->force_pmc = false;
6837	ufshcd_print_pwr_info(hba);
6838	up_write(sem: &hba->clk_scaling_lock);
6839	spin_lock_irqsave(hba->host->host_lock, flags);
6840	}
6841
6842	do_reset:
6843	/* Fatal errors need reset */
6844	if (needs_reset) {
6845	int err;
6846
6847	hba->force_reset = false;
6848	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6849	err = ufshcd_reset_and_restore(hba);
6850	if (err)
6851	dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6852	__func__, err);
6853	else
6854	ufshcd_recover_pm_error(hba);
6855	spin_lock_irqsave(hba->host->host_lock, flags);
6856	}
6857
6858	skip_err_handling:
6859	if (!needs_reset) {
6860	if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6861	hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6862	if (hba->saved_err || hba->saved_uic_err)
6863	dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6864	__func__, hba->saved_err, hba->saved_uic_err);
6865	}
6866	/* Exit in an operational state or dead */
6867	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6868	hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6869	if (--retries)
6870	goto again;
6871	hba->ufshcd_state = UFSHCD_STATE_ERROR;
6872	}
6873	ufshcd_clear_eh_in_progress(hba);
6874	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
6875	ufshcd_err_handling_unprepare(hba);
6876	up(sem: &hba->host_sem);
6877
6878	dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6879	ufshcd_state_name[hba->ufshcd_state]);
6880	}
6881
6882	/**
6883	* ufshcd_update_uic_error - check and set fatal UIC error flags.
6884	* @hba: per-adapter instance
6885	*
6886	* Return:
6887	* IRQ_HANDLED - If interrupt is valid
6888	* IRQ_NONE - If invalid interrupt
6889	*/
6890	static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6891	{
6892	u32 reg;
6893	irqreturn_t retval = IRQ_NONE;
6894
6895	/* PHY layer error */
6896	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6897	if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6898	(reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6899	ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6900	/*
6901	* To know whether this error is fatal or not, DB timeout
6902	* must be checked but this error is handled separately.
6903	*/
6904	if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6905	dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6906	__func__);
6907
6908	/* Got a LINERESET indication. */
6909	if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6910	struct uic_command *cmd = NULL;
6911
6912	hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6913	if (hba->uic_async_done && hba->active_uic_cmd)
6914	cmd = hba->active_uic_cmd;
6915	/*
6916	* Ignore the LINERESET during power mode change
6917	* operation via DME_SET command.
6918	*/
6919	if (cmd && (cmd->command == UIC_CMD_DME_SET))
6920	hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6921	}
6922	retval |= IRQ_HANDLED;
6923	}
6924
6925	/* PA_INIT_ERROR is fatal and needs UIC reset */
6926	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6927	if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6928	(reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6929	ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6930
6931	if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6932	hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6933	else if (hba->dev_quirks &
6934	UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6935	if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6936	hba->uic_error |=
6937	UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6938	else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6939	hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6940	}
6941	retval |= IRQ_HANDLED;
6942	}
6943
6944	/* UIC NL/TL/DME errors needs software retry */
6945	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6946	if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6947	(reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6948	ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6949	hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6950	retval |= IRQ_HANDLED;
6951	}
6952
6953	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6954	if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6955	(reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6956	ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6957	hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6958	retval |= IRQ_HANDLED;
6959	}
6960
6961	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6962	if ((reg & UIC_DME_ERROR) &&
6963	(reg & UIC_DME_ERROR_CODE_MASK)) {
6964	ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6965	hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6966	retval |= IRQ_HANDLED;
6967	}
6968
6969	dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6970	__func__, hba->uic_error);
6971	return retval;
6972	}
6973
6974	/**
6975	* ufshcd_check_errors - Check for errors that need s/w attention
6976	* @hba: per-adapter instance
6977	* @intr_status: interrupt status generated by the controller
6978	*
6979	* Return:
6980	* IRQ_HANDLED - If interrupt is valid
6981	* IRQ_NONE - If invalid interrupt
6982	*/
6983	static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6984	{
6985	bool queue_eh_work = false;
6986	irqreturn_t retval = IRQ_NONE;
6987
6988	guard(spinlock_irqsave)(l: hba->host->host_lock);
6989	hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6990
6991	if (hba->errors & INT_FATAL_ERRORS) {
6992	ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6993	hba->errors);
6994	queue_eh_work = true;
6995	}
6996
6997	if (hba->errors & UIC_ERROR) {
6998	hba->uic_error = 0;
6999	retval = ufshcd_update_uic_error(hba);
7000	if (hba->uic_error)
7001	queue_eh_work = true;
7002	}
7003
7004	if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
7005	dev_err(hba->dev,
7006	"%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
7007	__func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
7008	"Enter" : "Exit",
7009	hba->errors, ufshcd_get_upmcrs(hba));
7010	ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
7011	hba->errors);
7012	ufshcd_set_link_broken(hba);
7013	queue_eh_work = true;
7014	}
7015
7016	if (queue_eh_work) {
7017	/*
7018	* update the transfer error masks to sticky bits, let's do this
7019	* irrespective of current ufshcd_state.
7020	*/
7021	hba->saved_err |= hba->errors;
7022	hba->saved_uic_err |= hba->uic_error;
7023
7024	/* dump controller state before resetting */
7025	if ((hba->saved_err &
7026	(INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
7027	(hba->saved_uic_err &&
7028	(hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
7029	dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
7030	__func__, hba->saved_err,
7031	hba->saved_uic_err);
7032	ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
7033	"host_regs: ");
7034	ufshcd_print_pwr_info(hba);
7035	}
7036	ufshcd_schedule_eh_work(hba);
7037	retval |= IRQ_HANDLED;
7038	}
7039	/*
7040	* if (!queue_eh_work) -
7041	* Other errors are either non-fatal where host recovers
7042	* itself without s/w intervention or errors that will be
7043	* handled by the SCSI core layer.
7044	*/
7045	hba->errors = 0;
7046	hba->uic_error = 0;
7047
7048	return retval;
7049	}
7050
7051	/**
7052	* ufshcd_tmc_handler - handle task management function completion
7053	* @hba: per adapter instance
7054	*
7055	* Return:
7056	* IRQ_HANDLED - If interrupt is valid
7057	* IRQ_NONE - If invalid interrupt
7058	*/
7059	static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7060	{
7061	unsigned long flags, pending, issued;
7062	irqreturn_t ret = IRQ_NONE;
7063	int tag;
7064
7065	spin_lock_irqsave(hba->host->host_lock, flags);
7066	pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7067	issued = hba->outstanding_tasks & ~pending;
7068	for_each_set_bit(tag, &issued, hba->nutmrs) {
7069	struct request *req = hba->tmf_rqs[tag];
7070	struct completion *c = req->end_io_data;
7071
7072	complete(c);
7073	ret = IRQ_HANDLED;
7074	}
7075	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
7076
7077	return ret;
7078	}
7079
7080	/**
7081	* ufshcd_handle_mcq_cq_events - handle MCQ completion queue events
7082	* @hba: per adapter instance
7083	*
7084	* Return: IRQ_HANDLED if interrupt is handled.
7085	*/
7086	static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba)
7087	{
7088	struct ufs_hw_queue *hwq;
7089	unsigned long outstanding_cqs;
7090	unsigned int nr_queues;
7091	int i, ret;
7092	u32 events;
7093
7094	ret = ufshcd_vops_get_outstanding_cqs(hba, ocqs: &outstanding_cqs);
7095	if (ret)
7096	outstanding_cqs = (1U << hba->nr_hw_queues) - 1;
7097
7098	/* Exclude the poll queues */
7099	nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
7100	for_each_set_bit(i, &outstanding_cqs, nr_queues) {
7101	hwq = &hba->uhq[i];
7102
7103	events = ufshcd_mcq_read_cqis(hba, i);
7104	if (events)
7105	ufshcd_mcq_write_cqis(hba, val: events, i);
7106
7107	if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
7108	ufshcd_mcq_poll_cqe_lock(hba, hwq);
7109	}
7110
7111	return IRQ_HANDLED;
7112	}
7113
7114	/**
7115	* ufshcd_sl_intr - Interrupt service routine
7116	* @hba: per adapter instance
7117	* @intr_status: contains interrupts generated by the controller
7118	*
7119	* Return:
7120	* IRQ_HANDLED - If interrupt is valid
7121	* IRQ_NONE - If invalid interrupt
7122	*/
7123	static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7124	{
7125	irqreturn_t retval = IRQ_NONE;
7126
7127	if (intr_status & UFSHCD_UIC_MASK)
7128	retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7129
7130	if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
7131	retval |= ufshcd_check_errors(hba, intr_status);
7132
7133	if (intr_status & UTP_TASK_REQ_COMPL)
7134	retval |= ufshcd_tmc_handler(hba);
7135
7136	if (intr_status & UTP_TRANSFER_REQ_COMPL)
7137	retval |= ufshcd_transfer_req_compl(hba);
7138
7139	if (intr_status & MCQ_CQ_EVENT_STATUS)
7140	retval |= ufshcd_handle_mcq_cq_events(hba);
7141
7142	return retval;
7143	}
7144
7145	/**
7146	* ufshcd_threaded_intr - Threaded interrupt service routine
7147	* @irq: irq number
7148	* @__hba: pointer to adapter instance
7149	*
7150	* Return:
7151	* IRQ_HANDLED - If interrupt is valid
7152	* IRQ_NONE - If invalid interrupt
7153	*/
7154	static irqreturn_t ufshcd_threaded_intr(int irq, void *__hba)
7155	{
7156	u32 last_intr_status, intr_status, enabled_intr_status = 0;
7157	irqreturn_t retval = IRQ_NONE;
7158	struct ufs_hba *hba = __hba;
7159	int retries = hba->nutrs;
7160
7161	last_intr_status = intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7162
7163	/*
7164	* There could be max of hba->nutrs reqs in flight and in worst case
7165	* if the reqs get finished 1 by 1 after the interrupt status is
7166	* read, make sure we handle them by checking the interrupt status
7167	* again in a loop until we process all of the reqs before returning.
7168	*/
7169	while (intr_status && retries--) {
7170	enabled_intr_status =
7171	intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7172	ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7173	if (enabled_intr_status)
7174	retval |= ufshcd_sl_intr(hba, intr_status: enabled_intr_status);
7175
7176	intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7177	}
7178
7179	if (enabled_intr_status && retval == IRQ_NONE &&
7180	(!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
7181	hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
7182	dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
7183	__func__,
7184	intr_status,
7185	last_intr_status,
7186	enabled_intr_status);
7187	ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
7188	}
7189
7190	return retval;
7191	}
7192
7193	/**
7194	* ufshcd_intr - Main interrupt service routine
7195	* @irq: irq number
7196	* @__hba: pointer to adapter instance
7197	*
7198	* Return:
7199	* IRQ_HANDLED - If interrupt is valid
7200	* IRQ_WAKE_THREAD - If handling is moved to threaded handled
7201	* IRQ_NONE - If invalid interrupt
7202	*/
7203	static irqreturn_t ufshcd_intr(int irq, void *__hba)
7204	{
7205	struct ufs_hba *hba = __hba;
7206	u32 intr_status, enabled_intr_status;
7207
7208	/* Move interrupt handling to thread when MCQ & ESI are not enabled */
7209	if (!hba->mcq_enabled || !hba->mcq_esi_enabled)
7210	return IRQ_WAKE_THREAD;
7211
7212	intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7213	enabled_intr_status = intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7214
7215	ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7216
7217	/* Directly handle interrupts since MCQ ESI handlers does the hard job */
7218	return ufshcd_sl_intr(hba, intr_status: enabled_intr_status);
7219	}
7220
7221	static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
7222	{
7223	int err = 0;
7224	u32 mask = 1 << tag;
7225
7226	if (!test_bit(tag, &hba->outstanding_tasks))
7227	goto out;
7228
7229	ufshcd_utmrl_clear(hba, pos: tag);
7230
7231	/* poll for max. 1 sec to clear door bell register by h/w */
7232	err = ufshcd_wait_for_register(hba,
7233	reg: REG_UTP_TASK_REQ_DOOR_BELL,
7234	mask, val: 0, interval_us: 1000, timeout_ms: 1000);
7235
7236	dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
7237	tag, err < 0 ? "failed" : "succeeded");
7238
7239	out:
7240	return err;
7241	}
7242
7243	static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
7244	struct utp_task_req_desc *treq, u8 tm_function)
7245	{
7246	struct request_queue *q = hba->tmf_queue;
7247	struct Scsi_Host *host = hba->host;
7248	DECLARE_COMPLETION_ONSTACK(wait);
7249	struct request *req;
7250	unsigned long flags;
7251	int task_tag, err;
7252
7253	/*
7254	* blk_mq_alloc_request() is used here only to get a free tag.
7255	*/
7256	req = blk_mq_alloc_request(q, opf: REQ_OP_DRV_OUT, flags: 0);
7257	if (IS_ERR(ptr: req))
7258	return PTR_ERR(ptr: req);
7259
7260	req->end_io_data = &wait;
7261	ufshcd_hold(hba);
7262
7263	spin_lock_irqsave(host->host_lock, flags);
7264
7265	task_tag = req->tag;
7266	hba->tmf_rqs[req->tag] = req;
7267	treq->upiu_req.req_header.task_tag = task_tag;
7268
7269	memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
7270	ufshcd_vops_setup_task_mgmt(hba, tag: task_tag, tm_function);
7271
7272	__set_bit(task_tag, &hba->outstanding_tasks);
7273
7274	spin_unlock_irqrestore(lock: host->host_lock, flags);
7275
7276	/* send command to the controller */
7277	ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
7278
7279	ufshcd_add_tm_upiu_trace(hba, tag: task_tag, str_t: UFS_TM_SEND);
7280
7281	/* wait until the task management command is completed */
7282	err = wait_for_completion_io_timeout(x: &wait,
7283	timeout: msecs_to_jiffies(TM_CMD_TIMEOUT));
7284	if (!err) {
7285	ufshcd_add_tm_upiu_trace(hba, tag: task_tag, str_t: UFS_TM_ERR);
7286	dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
7287	__func__, tm_function);
7288	if (ufshcd_clear_tm_cmd(hba, tag: task_tag))
7289	dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
7290	__func__, task_tag);
7291	err = -ETIMEDOUT;
7292	} else {
7293	err = 0;
7294	memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
7295
7296	ufshcd_add_tm_upiu_trace(hba, tag: task_tag, str_t: UFS_TM_COMP);
7297	}
7298
7299	spin_lock_irqsave(hba->host->host_lock, flags);
7300	hba->tmf_rqs[req->tag] = NULL;
7301	__clear_bit(task_tag, &hba->outstanding_tasks);
7302	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
7303
7304	ufshcd_release(hba);
7305	blk_mq_free_request(rq: req);
7306
7307	return err;
7308	}
7309
7310	/**
7311	* ufshcd_issue_tm_cmd - issues task management commands to controller
7312	* @hba: per adapter instance
7313	* @lun_id: LUN ID to which TM command is sent
7314	* @task_id: task ID to which the TM command is applicable
7315	* @tm_function: task management function opcode
7316	* @tm_response: task management service response return value
7317	*
7318	* Return: non-zero value on error, zero on success.
7319	*/
7320	static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
7321	u8 tm_function, u8 *tm_response)
7322	{
7323	struct utp_task_req_desc treq = { };
7324	enum utp_ocs ocs_value;
7325	int err;
7326
7327	/* Configure task request descriptor */
7328	treq.header.interrupt = 1;
7329	treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7330
7331	/* Configure task request UPIU */
7332	treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ;
7333	treq.upiu_req.req_header.lun = lun_id;
7334	treq.upiu_req.req_header.tm_function = tm_function;
7335
7336	/*
7337	* The host shall provide the same value for LUN field in the basic
7338	* header and for Input Parameter.
7339	*/
7340	treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
7341	treq.upiu_req.input_param2 = cpu_to_be32(task_id);
7342
7343	err = __ufshcd_issue_tm_cmd(hba, treq: &treq, tm_function);
7344	if (err == -ETIMEDOUT)
7345	return err;
7346
7347	ocs_value = treq.header.ocs & MASK_OCS;
7348	if (ocs_value != OCS_SUCCESS)
7349	dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
7350	__func__, ocs_value);
7351	else if (tm_response)
7352	*tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
7353	MASK_TM_SERVICE_RESP;
7354	return err;
7355	}
7356
7357	/**
7358	* ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
7359	* @hba: per-adapter instance
7360	* @req_upiu: upiu request
7361	* @rsp_upiu: upiu reply
7362	* @desc_buff: pointer to descriptor buffer, NULL if NA
7363	* @buff_len: descriptor size, 0 if NA
7364	* @cmd_type: specifies the type (NOP, Query...)
7365	* @desc_op: descriptor operation
7366	*
7367	* Those type of requests uses UTP Transfer Request Descriptor - utrd.
7368	* Therefore, it "rides" the device management infrastructure: uses its tag and
7369	* tasks work queues.
7370	*
7371	* Since there is only one available tag for device management commands,
7372	* the caller is expected to hold the hba->dev_cmd.lock mutex.
7373	*
7374	* Return: 0 upon success; < 0 upon failure.
7375	*/
7376	static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
7377	struct utp_upiu_req *req_upiu,
7378	struct utp_upiu_req *rsp_upiu,
7379	u8 *desc_buff, int *buff_len,
7380	enum dev_cmd_type cmd_type,
7381	enum query_opcode desc_op)
7382	{
7383	struct scsi_cmnd *cmd = ufshcd_get_dev_mgmt_cmd(hba);
7384	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
7385	u32 tag;
7386	int err = 0;
7387	u8 upiu_flags;
7388
7389	/* Protects use of hba->dev_cmd. */
7390	lockdep_assert_held(&hba->dev_cmd.lock);
7391
7392	if (WARN_ON_ONCE(!cmd))
7393	return -ENOMEM;
7394
7395	tag = scsi_cmd_to_rq(scmd: cmd)->tag;
7396
7397	ufshcd_setup_dev_cmd(hba, cmd, cmd_type, lun: 0, tag);
7398
7399	ufshcd_prepare_req_desc_hdr(hba, lrbp, upiu_flags: &upiu_flags, cmd_dir: DMA_NONE, ehs_length: 0);
7400
7401	/* update the task tag in the request upiu */
7402	req_upiu->header.task_tag = tag;
7403
7404	/* just copy the upiu request as it is */
7405	memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7406	if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
7407	/* The Data Segment Area is optional depending upon the query
7408	* function value. for WRITE DESCRIPTOR, the data segment
7409	* follows right after the tsf.
7410	*/
7411	memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
7412	*buff_len = 0;
7413	}
7414
7415	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7416
7417	err = ufshcd_issue_dev_cmd(hba, cmd, tag, timeout: dev_cmd_timeout);
7418	if (err)
7419	goto put_dev_mgmt_cmd;
7420
7421	/* just copy the upiu response as it is */
7422	memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7423	if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
7424	u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
7425	u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
7426	.data_segment_length);
7427
7428	if (*buff_len >= resp_len) {
7429	memcpy(desc_buff, descp, resp_len);
7430	*buff_len = resp_len;
7431	} else {
7432	dev_warn(hba->dev,
7433	"%s: rsp size %d is bigger than buffer size %d",
7434	__func__, resp_len, *buff_len);
7435	*buff_len = 0;
7436	err = -EINVAL;
7437	}
7438	}
7439
7440	put_dev_mgmt_cmd:
7441	ufshcd_put_dev_mgmt_cmd(cmd);
7442
7443	return err;
7444	}
7445
7446	/**
7447	* ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
7448	* @hba: per-adapter instance
7449	* @req_upiu: upiu request
7450	* @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
7451	* @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
7452	* @desc_buff: pointer to descriptor buffer, NULL if NA
7453	* @buff_len: descriptor size, 0 if NA
7454	* @desc_op: descriptor operation
7455	*
7456	* Supports UTP Transfer requests (nop and query), and UTP Task
7457	* Management requests.
7458	* It is up to the caller to fill the upiu conent properly, as it will
7459	* be copied without any further input validations.
7460	*
7461	* Return: 0 upon success; < 0 upon failure.
7462	*/
7463	int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
7464	struct utp_upiu_req *req_upiu,
7465	struct utp_upiu_req *rsp_upiu,
7466	enum upiu_request_transaction msgcode,
7467	u8 *desc_buff, int *buff_len,
7468	enum query_opcode desc_op)
7469	{
7470	int err;
7471	enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
7472	struct utp_task_req_desc treq = { };
7473	enum utp_ocs ocs_value;
7474	u8 tm_f = req_upiu->header.tm_function;
7475
7476	switch (msgcode) {
7477	case UPIU_TRANSACTION_NOP_OUT:
7478	cmd_type = DEV_CMD_TYPE_NOP;
7479	fallthrough;
7480	case UPIU_TRANSACTION_QUERY_REQ:
7481	ufshcd_dev_man_lock(hba);
7482	err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
7483	desc_buff, buff_len,
7484	cmd_type, desc_op);
7485	ufshcd_dev_man_unlock(hba);
7486
7487	break;
7488	case UPIU_TRANSACTION_TASK_REQ:
7489	treq.header.interrupt = 1;
7490	treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7491
7492	memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
7493
7494	err = __ufshcd_issue_tm_cmd(hba, treq: &treq, tm_function: tm_f);
7495	if (err == -ETIMEDOUT)
7496	break;
7497
7498	ocs_value = treq.header.ocs & MASK_OCS;
7499	if (ocs_value != OCS_SUCCESS) {
7500	dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
7501	ocs_value);
7502	break;
7503	}
7504
7505	memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
7506
7507	break;
7508	default:
7509	err = -EINVAL;
7510
7511	break;
7512	}
7513
7514	return err;
7515	}
7516
7517	/**
7518	* ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
7519	* @hba: per adapter instance
7520	* @req_upiu: upiu request
7521	* @rsp_upiu: upiu reply
7522	* @req_ehs: EHS field which contains Advanced RPMB Request Message
7523	* @rsp_ehs: EHS field which returns Advanced RPMB Response Message
7524	* @sg_cnt: The number of sg lists actually used
7525	* @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7526	* @dir: DMA direction
7527	*
7528	* Return: 0 upon success; > 0 in case the UFS device reported an OCS error;
7529	* < 0 if another error occurred.
7530	*/
7531	int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7532	struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7533	struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7534	enum dma_data_direction dir)
7535	{
7536	struct scsi_cmnd *cmd;
7537	struct ufshcd_lrb *lrbp;
7538	u32 tag;
7539	int err = 0;
7540	int result;
7541	u8 upiu_flags;
7542	u8 *ehs_data;
7543	u16 ehs_len;
7544	int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0;
7545
7546	ufshcd_dev_man_lock(hba);
7547
7548	cmd = ufshcd_get_dev_mgmt_cmd(hba);
7549
7550	if (WARN_ON_ONCE(!cmd)) {
7551	err = -ENOMEM;
7552	goto unlock;
7553	}
7554
7555	lrbp = scsi_cmd_priv(cmd);
7556	tag = scsi_cmd_to_rq(scmd: cmd)->tag;
7557
7558	ufshcd_setup_dev_cmd(hba, cmd, cmd_type: DEV_CMD_TYPE_RPMB, lun: UFS_UPIU_RPMB_WLUN,
7559	tag);
7560
7561	ufshcd_prepare_req_desc_hdr(hba, lrbp, upiu_flags: &upiu_flags, cmd_dir: DMA_NONE, ehs_length: ehs);
7562
7563	/* update the task tag */
7564	req_upiu->header.task_tag = tag;
7565
7566	/* copy the UPIU(contains CDB) request as it is */
7567	memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7568	/* Copy EHS, starting with byte32, immediately after the CDB package */
7569	memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7570
7571	if (dir != DMA_NONE && sg_list)
7572	ufshcd_sgl_to_prdt(hba, lrbp, sg_entries: sg_cnt, sg_list);
7573
7574	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7575
7576	err = ufshcd_issue_dev_cmd(hba, cmd, tag, ADVANCED_RPMB_REQ_TIMEOUT);
7577	if (err)
7578	goto put_dev_mgmt_cmd;
7579
7580	err = ufshcd_dev_cmd_completion(hba, lrbp);
7581	if (!err) {
7582	/* Just copy the upiu response as it is */
7583	memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7584	/* Get the response UPIU result */
7585	result = (lrbp->ucd_rsp_ptr->header.response << 8) |
7586	lrbp->ucd_rsp_ptr->header.status;
7587
7588	ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length;
7589	/*
7590	* Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7591	* in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7592	* Message is 02h
7593	*/
7594	if (ehs_len == 2 && rsp_ehs) {
7595	/*
7596	* ucd_rsp_ptr points to a buffer with a length of 512 bytes
7597	* (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7598	*/
7599	ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7600	memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7601	}
7602	}
7603
7604	put_dev_mgmt_cmd:
7605	ufshcd_put_dev_mgmt_cmd(cmd);
7606
7607	unlock:
7608	ufshcd_dev_man_unlock(hba);
7609
7610	return err ? : result;
7611	}
7612
7613	static bool ufshcd_clear_lu_cmds(struct request *req, void *priv)
7614	{
7615	struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq: req);
7616	struct scsi_device *sdev = cmd->device;
7617	struct Scsi_Host *shost = sdev->host;
7618	struct ufs_hba *hba = shost_priv(shost);
7619	const u64 lun = *(u64 *)priv;
7620	const u32 tag = req->tag;
7621
7622	if (blk_mq_is_reserved_rq(rq: req) || sdev->lun != lun)
7623	return true;
7624
7625	if (ufshcd_clear_cmd(hba, task_tag: tag) < 0) {
7626	dev_err(hba->dev, "%s: failed to clear request %d\n", __func__,
7627	tag);
7628	return true;
7629	}
7630
7631	if (hba->mcq_enabled) {
7632	struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, req);
7633
7634	if (hwq)
7635	ufshcd_mcq_poll_cqe_lock(hba, hwq);
7636	return true;
7637	}
7638
7639	ufshcd_compl_one_cqe(hba, task_tag: tag, NULL);
7640	return true;
7641	}
7642
7643	/**
7644	* ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7645	* @cmd: SCSI command pointer
7646	*
7647	* Return: SUCCESS or FAILED.
7648	*/
7649	static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7650	{
7651	struct Scsi_Host *host;
7652	struct ufs_hba *hba;
7653	int err;
7654	u8 resp = 0xF, lun;
7655
7656	host = cmd->device->host;
7657	hba = shost_priv(shost: host);
7658
7659	lun = ufshcd_scsi_to_upiu_lun(scsi_lun: cmd->device->lun);
7660	err = ufshcd_issue_tm_cmd(hba, lun_id: lun, task_id: 0, tm_function: UFS_LOGICAL_RESET, tm_response: &resp);
7661	if (err) {
7662	} else if (resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7663	err = resp;
7664	} else {
7665	/* clear the commands that were pending for corresponding LUN */
7666	blk_mq_tagset_busy_iter(tagset: &hba->host->tag_set,
7667	fn: ufshcd_clear_lu_cmds,
7668	priv: &cmd->device->lun);
7669	}
7670
7671	hba->req_abort_count = 0;
7672	ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7673	if (!err) {
7674	err = SUCCESS;
7675	} else {
7676	dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7677	err = FAILED;
7678	}
7679	return err;
7680	}
7681
7682	static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7683	{
7684	int tag;
7685
7686	for_each_set_bit(tag, &bitmap, hba->nutrs) {
7687	struct scsi_cmnd *cmd = ufshcd_tag_to_cmd(hba, tag);
7688	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
7689
7690	lrbp->req_abort_skip = true;
7691	}
7692	}
7693
7694	/**
7695	* ufshcd_try_to_abort_task - abort a specific task
7696	* @hba: Pointer to adapter instance
7697	* @tag: Tag of the task to be aborted
7698	*
7699	* Abort the pending command in device by sending UFS_ABORT_TASK task management
7700	* command, and in host controller by clearing the door-bell register. There can
7701	* be race between controller sending the command to the device while abort is
7702	* issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7703	* really issued and then try to abort it.
7704	*
7705	* Return: zero on success, non-zero on failure.
7706	*/
7707	int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7708	{
7709	struct scsi_cmnd *cmd = ufshcd_tag_to_cmd(hba, tag);
7710	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
7711	int err;
7712	int poll_cnt;
7713	u8 resp = 0xF;
7714
7715	for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7716	err = ufshcd_issue_tm_cmd(hba, lun_id: lrbp->lun, task_id: tag, tm_function: UFS_QUERY_TASK,
7717	tm_response: &resp);
7718	if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7719	/* cmd pending in the device */
7720	dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7721	__func__, tag);
7722	break;
7723	} else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7724	/*
7725	* cmd not pending in the device, check if it is
7726	* in transition.
7727	*/
7728	dev_info(
7729	hba->dev,
7730	"%s: cmd with tag %d not pending in the device.\n",
7731	__func__, tag);
7732	if (!ufshcd_cmd_inflight(cmd)) {
7733	dev_info(hba->dev,
7734	"%s: cmd with tag=%d completed.\n",
7735	__func__, tag);
7736	return 0;
7737	}
7738	usleep_range(min: 100, max: 200);
7739	} else {
7740	dev_err(hba->dev,
7741	"%s: no response from device. tag = %d, err %d\n",
7742	__func__, tag, err);
7743	return err ? : resp;
7744	}
7745	}
7746
7747	if (!poll_cnt)
7748	return -EBUSY;
7749
7750	err = ufshcd_issue_tm_cmd(hba, lun_id: lrbp->lun, task_id: tag, tm_function: UFS_ABORT_TASK, tm_response: &resp);
7751	if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7752	if (!err) {
7753	err = resp; /* service response error */
7754	dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7755	__func__, tag, err);
7756	}
7757	return err;
7758	}
7759
7760	err = ufshcd_clear_cmd(hba, task_tag: tag);
7761	if (err)
7762	dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7763	__func__, tag, err);
7764
7765	return err;
7766	}
7767
7768	/**
7769	* ufshcd_abort - scsi host template eh_abort_handler callback
7770	* @cmd: SCSI command pointer
7771	*
7772	* Return: SUCCESS or FAILED.
7773	*/
7774	static int ufshcd_abort(struct scsi_cmnd *cmd)
7775	{
7776	struct Scsi_Host *host = cmd->device->host;
7777	struct ufs_hba *hba = shost_priv(shost: host);
7778	struct request *rq = scsi_cmd_to_rq(scmd: cmd);
7779	int tag = rq->tag;
7780	struct ufshcd_lrb *lrbp = scsi_cmd_priv(cmd);
7781	unsigned long flags;
7782	int err = FAILED;
7783	bool outstanding;
7784	u32 reg;
7785
7786	ufshcd_hold(hba);
7787
7788	if (!hba->mcq_enabled) {
7789	reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7790	if (!test_bit(tag, &hba->outstanding_reqs)) {
7791	/* If command is already aborted/completed, return FAILED. */
7792	dev_err(hba->dev,
7793	"%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7794	__func__, tag, hba->outstanding_reqs, reg);
7795	goto release;
7796	}
7797	}
7798
7799	/* Print Transfer Request of aborted task */
7800	dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7801
7802	/*
7803	* Print detailed info about aborted request.
7804	* As more than one request might get aborted at the same time,
7805	* print full information only for the first aborted request in order
7806	* to reduce repeated printouts. For other aborted requests only print
7807	* basic details.
7808	*/
7809	if (ufshcd_is_scsi_cmd(cmd))
7810	scsi_print_command(cmd);
7811	if (!hba->req_abort_count) {
7812	ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7813	ufshcd_print_evt_hist(hba);
7814	ufshcd_print_host_state(hba);
7815	ufshcd_print_pwr_info(hba);
7816	ufshcd_print_tr(hba, cmd, pr_prdt: true);
7817	} else {
7818	ufshcd_print_tr(hba, cmd, pr_prdt: false);
7819	}
7820	hba->req_abort_count++;
7821
7822	if (!hba->mcq_enabled && !(reg & (1 << tag))) {
7823	/* only execute this code in single doorbell mode */
7824	dev_err(hba->dev,
7825	"%s: cmd was completed, but without a notifying intr, tag = %d",
7826	__func__, tag);
7827	__ufshcd_transfer_req_compl(hba, completed_reqs: 1UL << tag);
7828	goto release;
7829	}
7830
7831	/*
7832	* Task abort to the device W-LUN is illegal. When this command
7833	* will fail, due to spec violation, scsi err handling next step
7834	* will be to send LU reset which, again, is a spec violation.
7835	* To avoid these unnecessary/illegal steps, first we clean up
7836	* the lrb taken by this cmd and re-set it in outstanding_reqs,
7837	* then queue the eh_work and bail.
7838	*/
7839	if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7840	ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7841
7842	spin_lock_irqsave(host->host_lock, flags);
7843	hba->force_reset = true;
7844	ufshcd_schedule_eh_work(hba);
7845	spin_unlock_irqrestore(lock: host->host_lock, flags);
7846	goto release;
7847	}
7848
7849	if (hba->mcq_enabled) {
7850	/* MCQ mode. Branch off to handle abort for mcq mode */
7851	err = ufshcd_mcq_abort(cmd);
7852	goto release;
7853	}
7854
7855	/* Skip task abort in case previous aborts failed and report failure */
7856	if (lrbp->req_abort_skip) {
7857	dev_err(hba->dev, "%s: skipping abort\n", __func__);
7858	ufshcd_set_req_abort_skip(hba, bitmap: hba->outstanding_reqs);
7859	goto release;
7860	}
7861
7862	if (blk_mq_is_reserved_rq(rq))
7863	err = ufshcd_clear_cmd(hba, task_tag: tag);
7864	else
7865	err = ufshcd_try_to_abort_task(hba, tag);
7866	if (err) {
7867	dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7868	ufshcd_set_req_abort_skip(hba, bitmap: hba->outstanding_reqs);
7869	err = FAILED;
7870	goto release;
7871	}
7872
7873	/*
7874	* Clear the corresponding bit from outstanding_reqs since the command
7875	* has been aborted successfully.
7876	*/
7877	spin_lock_irqsave(&hba->outstanding_lock, flags);
7878	outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7879	spin_unlock_irqrestore(lock: &hba->outstanding_lock, flags);
7880
7881	if (outstanding)
7882	ufshcd_release_scsi_cmd(hba, cmd);
7883
7884	err = SUCCESS;
7885
7886	release:
7887	/* Matches the ufshcd_hold() call at the start of this function. */
7888	ufshcd_release(hba);
7889	return err;
7890	}
7891
7892	/**
7893	* ufshcd_process_probe_result - Process the ufshcd_probe_hba() result.
7894	* @hba: UFS host controller instance.
7895	* @probe_start: time when the ufshcd_probe_hba() call started.
7896	* @ret: ufshcd_probe_hba() return value.
7897	*/
7898	static void ufshcd_process_probe_result(struct ufs_hba *hba,
7899	ktime_t probe_start, int ret)
7900	{
7901	unsigned long flags;
7902
7903	spin_lock_irqsave(hba->host->host_lock, flags);
7904	if (ret)
7905	hba->ufshcd_state = UFSHCD_STATE_ERROR;
7906	else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
7907	hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
7908	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
7909
7910	trace_ufshcd_init(hba, err: ret,
7911	usecs: ktime_to_us(ktime_sub(ktime_get(), probe_start)),
7912	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
7913	}
7914
7915	/**
7916	* ufshcd_host_reset_and_restore - reset and restore host controller
7917	* @hba: per-adapter instance
7918	*
7919	* Note that host controller reset may issue DME_RESET to
7920	* local and remote (device) Uni-Pro stack and the attributes
7921	* are reset to default state.
7922	*
7923	* Return: zero on success, non-zero on failure.
7924	*/
7925	static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7926	{
7927	int err;
7928
7929	/*
7930	* Stop the host controller and complete the requests
7931	* cleared by h/w
7932	*/
7933	ufshcd_hba_stop(hba);
7934	hba->silence_err_logs = true;
7935	ufshcd_complete_requests(hba, force_compl: true);
7936	hba->silence_err_logs = false;
7937
7938	/* scale up clocks to max frequency before full reinitialization */
7939	if (ufshcd_is_clkscaling_supported(hba))
7940	ufshcd_scale_clks(hba, ULONG_MAX, scale_up: true);
7941
7942	err = ufshcd_hba_enable(hba);
7943
7944	/* Establish the link again and restore the device */
7945	if (!err) {
7946	ktime_t probe_start = ktime_get();
7947
7948	err = ufshcd_device_init(hba, /*init_dev_params=*/false);
7949	if (!err)
7950	err = ufshcd_probe_hba(hba, init_dev_params: false);
7951	ufshcd_process_probe_result(hba, probe_start, ret: err);
7952	}
7953
7954	if (err)
7955	dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7956	ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7957	return err;
7958	}
7959
7960	/**
7961	* ufshcd_reset_and_restore - reset and re-initialize host/device
7962	* @hba: per-adapter instance
7963	*
7964	* Reset and recover device, host and re-establish link. This
7965	* is helpful to recover the communication in fatal error conditions.
7966	*
7967	* Return: zero on success, non-zero on failure.
7968	*/
7969	static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7970	{
7971	u32 saved_err = 0;
7972	u32 saved_uic_err = 0;
7973	int err = 0;
7974	unsigned long flags;
7975	int retries = MAX_HOST_RESET_RETRIES;
7976
7977	spin_lock_irqsave(hba->host->host_lock, flags);
7978	do {
7979	/*
7980	* This is a fresh start, cache and clear saved error first,
7981	* in case new error generated during reset and restore.
7982	*/
7983	saved_err |= hba->saved_err;
7984	saved_uic_err |= hba->saved_uic_err;
7985	hba->saved_err = 0;
7986	hba->saved_uic_err = 0;
7987	hba->force_reset = false;
7988	hba->ufshcd_state = UFSHCD_STATE_RESET;
7989	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
7990
7991	/* Reset the attached device */
7992	ufshcd_device_reset(hba);
7993
7994	err = ufshcd_host_reset_and_restore(hba);
7995
7996	spin_lock_irqsave(hba->host->host_lock, flags);
7997	if (err)
7998	continue;
7999	/* Do not exit unless operational or dead */
8000	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
8001	hba->ufshcd_state != UFSHCD_STATE_ERROR &&
8002	hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
8003	err = -EAGAIN;
8004	} while (err && --retries);
8005
8006	/*
8007	* Inform scsi mid-layer that we did reset and allow to handle
8008	* Unit Attention properly.
8009	*/
8010	scsi_report_bus_reset(hba->host, 0);
8011	if (err) {
8012	hba->ufshcd_state = UFSHCD_STATE_ERROR;
8013	hba->saved_err |= saved_err;
8014	hba->saved_uic_err |= saved_uic_err;
8015	}
8016	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
8017
8018	return err;
8019	}
8020
8021	/**
8022	* ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8023	* @cmd: SCSI command pointer
8024	*
8025	* Return: SUCCESS or FAILED.
8026	*/
8027	static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
8028	{
8029	int err = SUCCESS;
8030	unsigned long flags;
8031	struct ufs_hba *hba;
8032
8033	hba = shost_priv(shost: cmd->device->host);
8034
8035	/*
8036	* If runtime PM sent SSU and got a timeout, scsi_error_handler is
8037	* stuck in this function waiting for flush_work(&hba->eh_work). And
8038	* ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do
8039	* ufshcd_link_recovery instead of eh_work to prevent deadlock.
8040	*/
8041	if (hba->pm_op_in_progress) {
8042	if (ufshcd_link_recovery(hba))
8043	err = FAILED;
8044
8045	return err;
8046	}
8047
8048	spin_lock_irqsave(hba->host->host_lock, flags);
8049	hba->force_reset = true;
8050	ufshcd_schedule_eh_work(hba);
8051	dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
8052	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
8053
8054	flush_work(work: &hba->eh_work);
8055
8056	spin_lock_irqsave(hba->host->host_lock, flags);
8057	if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
8058	err = FAILED;
8059	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
8060
8061	return err;
8062	}
8063
8064	/**
8065	* ufshcd_get_max_icc_level - calculate the ICC level
8066	* @sup_curr_uA: max. current supported by the regulator
8067	* @start_scan: row at the desc table to start scan from
8068	* @buff: power descriptor buffer
8069	*
8070	* Return: calculated max ICC level for specific regulator.
8071	*/
8072	static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
8073	const char *buff)
8074	{
8075	int i;
8076	int curr_uA;
8077	u16 data;
8078	u16 unit;
8079
8080	for (i = start_scan; i >= 0; i--) {
8081	data = get_unaligned_be16(p: &buff[2 * i]);
8082	unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
8083	ATTR_ICC_LVL_UNIT_OFFSET;
8084	curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
8085	switch (unit) {
8086	case UFSHCD_NANO_AMP:
8087	curr_uA = curr_uA / 1000;
8088	break;
8089	case UFSHCD_MILI_AMP:
8090	curr_uA = curr_uA * 1000;
8091	break;
8092	case UFSHCD_AMP:
8093	curr_uA = curr_uA * 1000 * 1000;
8094	break;
8095	case UFSHCD_MICRO_AMP:
8096	default:
8097	break;
8098	}
8099	if (sup_curr_uA >= curr_uA)
8100	break;
8101	}
8102	if (i < 0) {
8103	i = 0;
8104	pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
8105	}
8106
8107	return (u32)i;
8108	}
8109
8110	/**
8111	* ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
8112	* In case regulators are not initialized we'll return 0
8113	* @hba: per-adapter instance
8114	* @desc_buf: power descriptor buffer to extract ICC levels from.
8115	*
8116	* Return: calculated ICC level.
8117	*/
8118	static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
8119	const u8 *desc_buf)
8120	{
8121	u32 icc_level = 0;
8122
8123	if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
8124	!hba->vreg_info.vccq2) {
8125	/*
8126	* Using dev_dbg to avoid messages during runtime PM to avoid
8127	* never-ending cycles of messages written back to storage by
8128	* user space causing runtime resume, causing more messages and
8129	* so on.
8130	*/
8131	dev_dbg(hba->dev,
8132	"%s: Regulator capability was not set, actvIccLevel=%d",
8133	__func__, icc_level);
8134	goto out;
8135	}
8136
8137	if (hba->vreg_info.vcc->max_uA)
8138	icc_level = ufshcd_get_max_icc_level(
8139	sup_curr_uA: hba->vreg_info.vcc->max_uA,
8140	POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
8141	buff: &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
8142
8143	if (hba->vreg_info.vccq->max_uA)
8144	icc_level = ufshcd_get_max_icc_level(
8145	sup_curr_uA: hba->vreg_info.vccq->max_uA,
8146	start_scan: icc_level,
8147	buff: &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
8148
8149	if (hba->vreg_info.vccq2->max_uA)
8150	icc_level = ufshcd_get_max_icc_level(
8151	sup_curr_uA: hba->vreg_info.vccq2->max_uA,
8152	start_scan: icc_level,
8153	buff: &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
8154	out:
8155	return icc_level;
8156	}
8157
8158	static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
8159	{
8160	int ret;
8161	u8 *desc_buf;
8162	u32 icc_level;
8163
8164	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8165	if (!desc_buf)
8166	return;
8167
8168	ret = ufshcd_read_desc_param(hba, desc_id: QUERY_DESC_IDN_POWER, desc_index: 0, param_offset: 0,
8169	param_read_buf: desc_buf, QUERY_DESC_MAX_SIZE);
8170	if (ret) {
8171	dev_err(hba->dev,
8172	"%s: Failed reading power descriptor ret = %d",
8173	__func__, ret);
8174	goto out;
8175	}
8176
8177	icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
8178	dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
8179
8180	ret = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_WRITE_ATTR,
8181	idn: QUERY_ATTR_IDN_ACTIVE_ICC_LVL, index: 0, selector: 0, attr_val: &icc_level);
8182
8183	if (ret)
8184	dev_err(hba->dev,
8185	"%s: Failed configuring bActiveICCLevel = %d ret = %d",
8186	__func__, icc_level, ret);
8187
8188	out:
8189	kfree(objp: desc_buf);
8190	}
8191
8192	static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
8193	{
8194	struct Scsi_Host *shost = sdev->host;
8195
8196	scsi_autopm_get_device(sdev);
8197	blk_pm_runtime_init(q: sdev->request_queue, dev: &sdev->sdev_gendev);
8198	if (sdev->rpm_autosuspend)
8199	pm_runtime_set_autosuspend_delay(dev: &sdev->sdev_gendev,
8200	delay: shost->rpm_autosuspend_delay);
8201	scsi_autopm_put_device(sdev);
8202	}
8203
8204	/**
8205	* ufshcd_scsi_add_wlus - Adds required W-LUs
8206	* @hba: per-adapter instance
8207	*
8208	* UFS device specification requires the UFS devices to support 4 well known
8209	* logical units:
8210	* "REPORT_LUNS" (address: 01h)
8211	* "UFS Device" (address: 50h)
8212	* "RPMB" (address: 44h)
8213	* "BOOT" (address: 30h)
8214	* UFS device's power management needs to be controlled by "POWER CONDITION"
8215	* field of SSU (START STOP UNIT) command. But this "power condition" field
8216	* will take effect only when its sent to "UFS device" well known logical unit
8217	* hence we require the scsi_device instance to represent this logical unit in
8218	* order for the UFS host driver to send the SSU command for power management.
8219	*
8220	* We also require the scsi_device instance for "RPMB" (Replay Protected Memory
8221	* Block) LU so user space process can control this LU. User space may also
8222	* want to have access to BOOT LU.
8223	*
8224	* This function adds scsi device instances for each of all well known LUs
8225	* (except "REPORT LUNS" LU).
8226	*
8227	* Return: zero on success (all required W-LUs are added successfully),
8228	* non-zero error value on failure (if failed to add any of the required W-LU).
8229	*/
8230	static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
8231	{
8232	int ret = 0;
8233	struct scsi_device *sdev_boot, *sdev_rpmb;
8234
8235	hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
8236	ufshcd_upiu_wlun_to_scsi_wlun(upiu_wlun_id: UFS_UPIU_UFS_DEVICE_WLUN), NULL);
8237	if (IS_ERR(ptr: hba->ufs_device_wlun)) {
8238	ret = PTR_ERR(ptr: hba->ufs_device_wlun);
8239	hba->ufs_device_wlun = NULL;
8240	goto out;
8241	}
8242	scsi_device_put(hba->ufs_device_wlun);
8243
8244	sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
8245	ufshcd_upiu_wlun_to_scsi_wlun(upiu_wlun_id: UFS_UPIU_RPMB_WLUN), NULL);
8246	if (IS_ERR(ptr: sdev_rpmb)) {
8247	ret = PTR_ERR(ptr: sdev_rpmb);
8248	hba->ufs_rpmb_wlun = NULL;
8249	dev_err(hba->dev, "%s: RPMB WLUN not found\n", __func__);
8250	goto remove_ufs_device_wlun;
8251	}
8252	hba->ufs_rpmb_wlun = sdev_rpmb;
8253	ufshcd_blk_pm_runtime_init(sdev: sdev_rpmb);
8254	scsi_device_put(sdev_rpmb);
8255
8256	sdev_boot = __scsi_add_device(hba->host, 0, 0,
8257	ufshcd_upiu_wlun_to_scsi_wlun(upiu_wlun_id: UFS_UPIU_BOOT_WLUN), NULL);
8258	if (IS_ERR(ptr: sdev_boot)) {
8259	dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
8260	} else {
8261	ufshcd_blk_pm_runtime_init(sdev: sdev_boot);
8262	scsi_device_put(sdev_boot);
8263	}
8264	goto out;
8265
8266	remove_ufs_device_wlun:
8267	scsi_remove_device(hba->ufs_device_wlun);
8268	out:
8269	return ret;
8270	}
8271
8272	static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
8273	{
8274	struct ufs_dev_info *dev_info = &hba->dev_info;
8275	u8 lun;
8276	u32 d_lu_wb_buf_alloc;
8277	u32 ext_ufs_feature;
8278
8279	if (!ufshcd_is_wb_allowed(hba))
8280	return;
8281
8282	/*
8283	* Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
8284	* UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
8285	* enabled
8286	*/
8287	if (!(dev_info->wspecversion >= 0x310 ||
8288	dev_info->wspecversion == 0x220 ||
8289	(hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
8290	goto wb_disabled;
8291
8292	ext_ufs_feature = get_unaligned_be32(p: desc_buf +
8293	DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8294
8295	if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
8296	goto wb_disabled;
8297
8298	/*
8299	* WB may be supported but not configured while provisioning. The spec
8300	* says, in dedicated wb buffer mode, a max of 1 lun would have wb
8301	* buffer configured.
8302	*/
8303	dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
8304
8305	dev_info->ext_wb_sup = get_unaligned_be16(p: desc_buf +
8306	DEVICE_DESC_PARAM_EXT_WB_SUP);
8307
8308	dev_info->b_presrv_uspc_en =
8309	desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
8310
8311	if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
8312	if (!get_unaligned_be32(p: desc_buf +
8313	DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
8314	goto wb_disabled;
8315	} else {
8316	for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
8317	d_lu_wb_buf_alloc = 0;
8318	ufshcd_read_unit_desc_param(hba,
8319	lun,
8320	param_offset: UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
8321	param_read_buf: (u8 *)&d_lu_wb_buf_alloc,
8322	param_size: sizeof(d_lu_wb_buf_alloc));
8323	if (d_lu_wb_buf_alloc) {
8324	dev_info->wb_dedicated_lu = lun;
8325	break;
8326	}
8327	}
8328
8329	if (!d_lu_wb_buf_alloc)
8330	goto wb_disabled;
8331	}
8332
8333	if (!ufshcd_is_wb_buf_lifetime_available(hba))
8334	goto wb_disabled;
8335
8336	return;
8337
8338	wb_disabled:
8339	hba->caps &= ~UFSHCD_CAP_WB_EN;
8340	}
8341
8342	static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
8343	{
8344	struct ufs_dev_info *dev_info = &hba->dev_info;
8345	u32 ext_ufs_feature;
8346	u8 mask = 0;
8347
8348	if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
8349	return;
8350
8351	ext_ufs_feature = get_unaligned_be32(p: desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8352
8353	if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
8354	mask |= MASK_EE_TOO_LOW_TEMP;
8355
8356	if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
8357	mask |= MASK_EE_TOO_HIGH_TEMP;
8358
8359	if (mask) {
8360	ufshcd_enable_ee(hba, mask);
8361	ufs_hwmon_probe(hba, mask);
8362	}
8363	}
8364
8365	static void ufshcd_device_lvl_exception_probe(struct ufs_hba *hba, u8 *desc_buf)
8366	{
8367	u32 ext_ufs_feature;
8368
8369	if (hba->dev_info.wspecversion < 0x410)
8370	return;
8371
8372	ext_ufs_feature = get_unaligned_be32(p: desc_buf +
8373	DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8374	if (!(ext_ufs_feature & UFS_DEV_LVL_EXCEPTION_SUP))
8375	return;
8376
8377	atomic_set(v: &hba->dev_lvl_exception_count, i: 0);
8378	ufshcd_enable_ee(hba, mask: MASK_EE_DEV_LVL_EXCEPTION);
8379	}
8380
8381	static void ufshcd_set_rtt(struct ufs_hba *hba)
8382	{
8383	struct ufs_dev_info *dev_info = &hba->dev_info;
8384	u32 rtt = 0;
8385	u32 dev_rtt = 0;
8386	int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ?
8387	hba->vops->max_num_rtt : hba->nortt;
8388
8389	/* RTT override makes sense only for UFS-4.0 and above */
8390	if (dev_info->wspecversion < 0x400)
8391	return;
8392
8393	if (ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
8394	idn: QUERY_ATTR_IDN_MAX_NUM_OF_RTT, index: 0, selector: 0, attr_val: &dev_rtt)) {
8395	dev_err(hba->dev, "failed reading bMaxNumOfRTT\n");
8396	return;
8397	}
8398
8399	/* do not override if it was already written */
8400	if (dev_rtt != DEFAULT_MAX_NUM_RTT)
8401	return;
8402
8403	rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap);
8404
8405	if (rtt == dev_rtt)
8406	return;
8407
8408	if (ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_WRITE_ATTR,
8409	idn: QUERY_ATTR_IDN_MAX_NUM_OF_RTT, index: 0, selector: 0, attr_val: &rtt))
8410	dev_err(hba->dev, "failed writing bMaxNumOfRTT\n");
8411	}
8412
8413	void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
8414	const struct ufs_dev_quirk *fixups)
8415	{
8416	const struct ufs_dev_quirk *f;
8417	struct ufs_dev_info *dev_info = &hba->dev_info;
8418
8419	if (!fixups)
8420	return;
8421
8422	for (f = fixups; f->quirk; f++) {
8423	if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
8424	f->wmanufacturerid == UFS_ANY_VENDOR) &&
8425	((dev_info->model &&
8426	STR_PRFX_EQUAL(f->model, dev_info->model)) ||
8427	!strcmp(f->model, UFS_ANY_MODEL)))
8428	hba->dev_quirks |= f->quirk;
8429	}
8430	}
8431	EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
8432
8433	static void ufs_fixup_device_setup(struct ufs_hba *hba)
8434	{
8435	/* fix by general quirk table */
8436	ufshcd_fixup_dev_quirks(hba, ufs_fixups);
8437
8438	/* allow vendors to fix quirks */
8439	ufshcd_vops_fixup_dev_quirks(hba);
8440	}
8441
8442	static void ufshcd_update_rtc(struct ufs_hba *hba)
8443	{
8444	struct timespec64 ts64;
8445	int err;
8446	u32 val;
8447
8448	ktime_get_real_ts64(tv: &ts64);
8449
8450	if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) {
8451	dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__);
8452	return;
8453	}
8454
8455	/*
8456	* The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond
8457	* 2146 is required, it is recommended to choose the relative RTC mode.
8458	*/
8459	val = ts64.tv_sec - hba->dev_info.rtc_time_baseline;
8460
8461	/* Skip update RTC if RPM state is not RPM_ACTIVE */
8462	if (ufshcd_rpm_get_if_active(hba) <= 0)
8463	return;
8464
8465	err = ufshcd_query_attr(hba, opcode: UPIU_QUERY_OPCODE_WRITE_ATTR, idn: QUERY_ATTR_IDN_SECONDS_PASSED,
8466	index: 0, selector: 0, attr_val: &val);
8467	ufshcd_rpm_put(hba);
8468
8469	if (err)
8470	dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err);
8471	else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE)
8472	hba->dev_info.rtc_time_baseline = ts64.tv_sec;
8473	}
8474
8475	static void ufshcd_rtc_work(struct work_struct *work)
8476	{
8477	struct ufs_hba *hba;
8478
8479	hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work);
8480
8481	/* Update RTC only when there are no requests in progress and UFSHCI is operational */
8482	if (!ufshcd_is_ufs_dev_busy(hba) &&
8483	hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL &&
8484	!hba->clk_gating.active_reqs)
8485	ufshcd_update_rtc(hba);
8486
8487	if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period)
8488	schedule_delayed_work(dwork: &hba->ufs_rtc_update_work,
8489	delay: msecs_to_jiffies(m: hba->dev_info.rtc_update_period));
8490	}
8491
8492	static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf)
8493	{
8494	u16 periodic_rtc_update = get_unaligned_be16(p: &desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]);
8495	struct ufs_dev_info *dev_info = &hba->dev_info;
8496
8497	if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) {
8498	dev_info->rtc_type = UFS_RTC_ABSOLUTE;
8499
8500	/*
8501	* The concept of measuring time in Linux as the number of seconds elapsed since
8502	* 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st
8503	* 2010 00:00, here we need to adjust ABS baseline.
8504	*/
8505	dev_info->rtc_time_baseline = mktime64(year: 2010, mon: 1, day: 1, hour: 0, min: 0, sec: 0) -
8506	mktime64(year: 1970, mon: 1, day: 1, hour: 0, min: 0, sec: 0);
8507	} else {
8508	dev_info->rtc_type = UFS_RTC_RELATIVE;
8509	dev_info->rtc_time_baseline = 0;
8510	}
8511
8512	/*
8513	* We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state
8514	* how to calculate the specific update period for each time unit. And we disable periodic
8515	* RTC update work, let user configure by sysfs node according to specific circumstance.
8516	*/
8517	dev_info->rtc_update_period = 0;
8518	}
8519
8520	/**
8521	* ufshcd_create_device_id - Generate unique device identifier string
8522	* @hba: per-adapter instance
8523	* @desc_buf: device descriptor buffer
8524	*
8525	* Creates a unique device ID string combining manufacturer ID, spec version,
8526	* model name, serial number (as hex), device version, and manufacture date.
8527	*
8528	* Returns: Allocated device ID string on success, NULL on failure
8529	*/
8530	static char *ufshcd_create_device_id(struct ufs_hba *hba, u8 *desc_buf)
8531	{
8532	struct ufs_dev_info *dev_info = &hba->dev_info;
8533	u16 manufacture_date;
8534	u16 device_version;
8535	u8 *serial_number;
8536	char *serial_hex;
8537	char *device_id;
8538	u8 serial_index;
8539	int serial_len;
8540	int ret;
8541
8542	serial_index = desc_buf[DEVICE_DESC_PARAM_SN];
8543
8544	ret = ufshcd_read_string_desc(hba, desc_index: serial_index, buf: &serial_number, fmt: SD_RAW);
8545	if (ret < 0) {
8546	dev_err(hba->dev, "Failed reading Serial Number. err = %d\n", ret);
8547	return NULL;
8548	}
8549
8550	device_version = get_unaligned_be16(p: &desc_buf[DEVICE_DESC_PARAM_DEV_VER]);
8551	manufacture_date = get_unaligned_be16(p: &desc_buf[DEVICE_DESC_PARAM_MANF_DATE]);
8552
8553	serial_len = ret;
8554	/* Allocate buffer for hex string: 2 chars per byte + null terminator */
8555	serial_hex = kzalloc(serial_len * 2 + 1, GFP_KERNEL);
8556	if (!serial_hex) {
8557	kfree(objp: serial_number);
8558	return NULL;
8559	}
8560
8561	bin2hex(dst: serial_hex, src: serial_number, count: serial_len);
8562
8563	/*
8564	* Device ID format is ABI with secure world - do not change without firmware
8565	* coordination.
8566	*/
8567	device_id = kasprintf(GFP_KERNEL, fmt: "%04X-%04X-%s-%s-%04X-%04X",
8568	dev_info->wmanufacturerid, dev_info->wspecversion,
8569	dev_info->model, serial_hex, device_version,
8570	manufacture_date);
8571
8572	kfree(objp: serial_hex);
8573	kfree(objp: serial_number);
8574
8575	if (!device_id)
8576	dev_warn(hba->dev, "Failed to allocate unique device ID\n");
8577
8578	return device_id;
8579	}
8580
8581	static int ufs_get_device_desc(struct ufs_hba *hba)
8582	{
8583	struct ufs_dev_info *dev_info = &hba->dev_info;
8584	struct Scsi_Host *shost = hba->host;
8585	int err;
8586	u8 model_index;
8587	u8 *desc_buf;
8588
8589	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8590	if (!desc_buf) {
8591	err = -ENOMEM;
8592	goto out;
8593	}
8594
8595	err = ufshcd_read_desc_param(hba, desc_id: QUERY_DESC_IDN_DEVICE, desc_index: 0, param_offset: 0, param_read_buf: desc_buf,
8596	QUERY_DESC_MAX_SIZE);
8597	if (err) {
8598	dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
8599	__func__, err);
8600	goto out;
8601	}
8602
8603	/*
8604	* getting vendor (manufacturerID) and Bank Index in big endian
8605	* format
8606	*/
8607	dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
8608	desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
8609
8610	/* getting Specification Version in big endian format */
8611	dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
8612	desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
8613	dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
8614
8615	/*
8616	* According to the UFS standard, the UFS device queue depth
8617	* (bQueueDepth) must be in the range 1..255 if the shared queueing
8618	* architecture is supported. bQueueDepth is zero if the shared queueing
8619	* architecture is not supported.
8620	*/
8621	if (dev_info->bqueuedepth)
8622	shost->cmd_per_lun = min(hba->nutrs, dev_info->bqueuedepth) -
8623	UFSHCD_NUM_RESERVED;
8624	else
8625	shost->cmd_per_lun = shost->can_queue;
8626
8627	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
8628
8629	dev_info->hid_sup = get_unaligned_be32(p: desc_buf +
8630	DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP) &
8631	UFS_DEV_HID_SUPPORT;
8632
8633	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
8634
8635	err = ufshcd_read_string_desc(hba, desc_index: model_index,
8636	buf: &dev_info->model, fmt: SD_ASCII_STD);
8637	if (err < 0) {
8638	dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
8639	__func__, err);
8640	goto out;
8641	}
8642
8643	/* Generate unique device ID */
8644	dev_info->device_id = ufshcd_create_device_id(hba, desc_buf);
8645
8646	hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
8647	desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
8648
8649	ufs_fixup_device_setup(hba);
8650
8651	ufshcd_wb_probe(hba, desc_buf);
8652
8653	ufshcd_temp_notif_probe(hba, desc_buf);
8654
8655	if (dev_info->wspecversion >= 0x410) {
8656	hba->critical_health_count = 0;
8657	ufshcd_enable_ee(hba, mask: MASK_EE_HEALTH_CRITICAL);
8658	}
8659
8660	ufs_init_rtc(hba, desc_buf);
8661
8662	ufshcd_device_lvl_exception_probe(hba, desc_buf);
8663
8664	/*
8665	* ufshcd_read_string_desc returns size of the string
8666	* reset the error value
8667	*/
8668	err = 0;
8669
8670	out:
8671	kfree(objp: desc_buf);
8672	return err;
8673	}
8674
8675	static void ufs_put_device_desc(struct ufs_hba *hba)
8676	{
8677	struct ufs_dev_info *dev_info = &hba->dev_info;
8678
8679	kfree(objp: dev_info->model);
8680	dev_info->model = NULL;
8681	kfree(objp: dev_info->device_id);
8682	dev_info->device_id = NULL;
8683	}
8684
8685	/**
8686	* ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
8687	* less than device PA_TACTIVATE time.
8688	* @hba: per-adapter instance
8689	*
8690	* Some UFS devices require host PA_TACTIVATE to be lower than device
8691	* PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8692	* for such devices.
8693	*
8694	* Return: zero on success, non-zero error value on failure.
8695	*/
8696	static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8697	{
8698	int ret = 0;
8699	u32 granularity, peer_granularity;
8700	u32 pa_tactivate, peer_pa_tactivate;
8701	u32 pa_tactivate_us, peer_pa_tactivate_us;
8702	static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
8703
8704	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8705	mib_val: &granularity);
8706	if (ret)
8707	goto out;
8708
8709	ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8710	mib_val: &peer_granularity);
8711	if (ret)
8712	goto out;
8713
8714	if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8715	(granularity > PA_GRANULARITY_MAX_VAL)) {
8716	dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8717	__func__, granularity);
8718	return -EINVAL;
8719	}
8720
8721	if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8722	(peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8723	dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8724	__func__, peer_granularity);
8725	return -EINVAL;
8726	}
8727
8728	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), mib_val: &pa_tactivate);
8729	if (ret)
8730	goto out;
8731
8732	ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8733	mib_val: &peer_pa_tactivate);
8734	if (ret)
8735	goto out;
8736
8737	pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8738	peer_pa_tactivate_us = peer_pa_tactivate *
8739	gran_to_us_table[peer_granularity - 1];
8740
8741	if (pa_tactivate_us >= peer_pa_tactivate_us) {
8742	u32 new_peer_pa_tactivate;
8743
8744	new_peer_pa_tactivate = pa_tactivate_us /
8745	gran_to_us_table[peer_granularity - 1];
8746	new_peer_pa_tactivate++;
8747	ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8748	mib_val: new_peer_pa_tactivate);
8749	}
8750
8751	out:
8752	return ret;
8753	}
8754
8755	/**
8756	* ufshcd_quirk_override_pa_h8time - Ensures proper adjustment of PA_HIBERN8TIME.
8757	* @hba: per-adapter instance
8758	*
8759	* Some UFS devices require specific adjustments to the PA_HIBERN8TIME parameter
8760	* to ensure proper hibernation timing. This function retrieves the current
8761	* PA_HIBERN8TIME value and increments it by 100us.
8762	*/
8763	static void ufshcd_quirk_override_pa_h8time(struct ufs_hba *hba)
8764	{
8765	u32 pa_h8time;
8766	int ret;
8767
8768	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), mib_val: &pa_h8time);
8769	if (ret) {
8770	dev_err(hba->dev, "Failed to get PA_HIBERN8TIME: %d\n", ret);
8771	return;
8772	}
8773
8774	/* Increment by 1 to increase hibernation time by 100 µs */
8775	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), mib_val: pa_h8time + 1);
8776	if (ret)
8777	dev_err(hba->dev, "Failed updating PA_HIBERN8TIME: %d\n", ret);
8778	}
8779
8780	static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
8781	{
8782	ufshcd_vops_apply_dev_quirks(hba);
8783
8784	if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8785	/* set 1ms timeout for PA_TACTIVATE */
8786	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), mib_val: 10);
8787
8788	if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8789	ufshcd_quirk_tune_host_pa_tactivate(hba);
8790
8791	if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_HIBER8TIME)
8792	ufshcd_quirk_override_pa_h8time(hba);
8793	}
8794
8795	static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8796	{
8797	hba->ufs_stats.hibern8_exit_cnt = 0;
8798	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(secs: 0, nsecs: 0);
8799	hba->req_abort_count = 0;
8800	}
8801
8802	static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8803	{
8804	int err;
8805	u8 *desc_buf;
8806
8807	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8808	if (!desc_buf) {
8809	err = -ENOMEM;
8810	goto out;
8811	}
8812
8813	err = ufshcd_read_desc_param(hba, desc_id: QUERY_DESC_IDN_GEOMETRY, desc_index: 0, param_offset: 0,
8814	param_read_buf: desc_buf, QUERY_DESC_MAX_SIZE);
8815	if (err) {
8816	dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8817	__func__, err);
8818	goto out;
8819	}
8820
8821	if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8822	hba->dev_info.max_lu_supported = 32;
8823	else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8824	hba->dev_info.max_lu_supported = 8;
8825
8826	hba->dev_info.rpmb_io_size = desc_buf[GEOMETRY_DESC_PARAM_RPMB_RW_SIZE];
8827
8828	out:
8829	kfree(objp: desc_buf);
8830	return err;
8831	}
8832
8833	struct ufs_ref_clk {
8834	unsigned long freq_hz;
8835	enum ufs_ref_clk_freq val;
8836	};
8837
8838	static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8839	{19200000, REF_CLK_FREQ_19_2_MHZ},
8840	{26000000, REF_CLK_FREQ_26_MHZ},
8841	{38400000, REF_CLK_FREQ_38_4_MHZ},
8842	{52000000, REF_CLK_FREQ_52_MHZ},
8843	{0, REF_CLK_FREQ_INVAL},
8844	};
8845
8846	static enum ufs_ref_clk_freq
8847	ufs_get_bref_clk_from_hz(unsigned long freq)
8848	{
8849	int i;
8850
8851	for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8852	if (ufs_ref_clk_freqs[i].freq_hz == freq)
8853	return ufs_ref_clk_freqs[i].val;
8854
8855	return REF_CLK_FREQ_INVAL;
8856	}
8857
8858	void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8859	{
8860	unsigned long freq;
8861
8862	freq = clk_get_rate(clk: refclk);
8863
8864	hba->dev_ref_clk_freq =
8865	ufs_get_bref_clk_from_hz(freq);
8866
8867	if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8868	dev_err(hba->dev,
8869	"invalid ref_clk setting = %ld\n", freq);
8870	}
8871
8872	static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8873	{
8874	int err;
8875	u32 ref_clk;
8876	u32 freq = hba->dev_ref_clk_freq;
8877
8878	err = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_ATTR,
8879	idn: QUERY_ATTR_IDN_REF_CLK_FREQ, index: 0, selector: 0, attr_val: &ref_clk);
8880
8881	if (err) {
8882	dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8883	err);
8884	goto out;
8885	}
8886
8887	if (ref_clk == freq)
8888	goto out; /* nothing to update */
8889
8890	err = ufshcd_query_attr_retry(hba, opcode: UPIU_QUERY_OPCODE_WRITE_ATTR,
8891	idn: QUERY_ATTR_IDN_REF_CLK_FREQ, index: 0, selector: 0, attr_val: &freq);
8892
8893	if (err) {
8894	dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8895	ufs_ref_clk_freqs[freq].freq_hz);
8896	goto out;
8897	}
8898
8899	dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8900	ufs_ref_clk_freqs[freq].freq_hz);
8901
8902	out:
8903	return err;
8904	}
8905
8906	static int ufshcd_device_params_init(struct ufs_hba *hba)
8907	{
8908	bool flag;
8909	int ret;
8910
8911	/* Init UFS geometry descriptor related parameters */
8912	ret = ufshcd_device_geo_params_init(hba);
8913	if (ret)
8914	goto out;
8915
8916	/* Check and apply UFS device quirks */
8917	ret = ufs_get_device_desc(hba);
8918	if (ret) {
8919	dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8920	__func__, ret);
8921	goto out;
8922	}
8923
8924	ufshcd_set_rtt(hba);
8925
8926	ufshcd_get_ref_clk_gating_wait(hba);
8927
8928	if (!ufshcd_query_flag_retry(hba, opcode: UPIU_QUERY_OPCODE_READ_FLAG,
8929	idn: QUERY_FLAG_IDN_PWR_ON_WPE, index: 0, flag_res: &flag))
8930	hba->dev_info.f_power_on_wp_en = flag;
8931
8932	/* Probe maximum power mode co-supported by both UFS host and device */
8933	if (ufshcd_get_max_pwr_mode(hba))
8934	dev_err(hba->dev,
8935	"%s: Failed getting max supported power mode\n",
8936	__func__);
8937	out:
8938	return ret;
8939	}
8940
8941	static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
8942	{
8943	int err;
8944	struct ufs_query_req *request = NULL;
8945	struct ufs_query_res *response = NULL;
8946	struct ufs_dev_info *dev_info = &hba->dev_info;
8947	struct utp_upiu_query_v4_0 *upiu_data;
8948
8949	if (dev_info->wspecversion < 0x400 ||
8950	hba->dev_quirks & UFS_DEVICE_QUIRK_NO_TIMESTAMP_SUPPORT)
8951	return;
8952
8953	ufshcd_dev_man_lock(hba);
8954
8955	ufshcd_init_query(hba, request: &request, response: &response,
8956	opcode: UPIU_QUERY_OPCODE_WRITE_ATTR,
8957	idn: QUERY_ATTR_IDN_TIMESTAMP, index: 0, selector: 0);
8958
8959	request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
8960
8961	upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req;
8962
8963	put_unaligned_be64(val: ktime_get_real_ns(), p: &upiu_data->osf3);
8964
8965	err = ufshcd_exec_dev_cmd(hba, cmd_type: DEV_CMD_TYPE_QUERY, timeout: dev_cmd_timeout);
8966
8967	if (err)
8968	dev_err(hba->dev, "%s: failed to set timestamp %d\n",
8969	__func__, err);
8970
8971	ufshcd_dev_man_unlock(hba);
8972	}
8973
8974	/**
8975	* ufshcd_add_lus - probe and add UFS logical units
8976	* @hba: per-adapter instance
8977	*
8978	* Return: 0 upon success; < 0 upon failure.
8979	*/
8980	static int ufshcd_add_lus(struct ufs_hba *hba)
8981	{
8982	int ret;
8983
8984	/* Add required well known logical units to scsi mid layer */
8985	ret = ufshcd_scsi_add_wlus(hba);
8986	if (ret)
8987	goto out;
8988
8989	/* Initialize devfreq after UFS device is detected */
8990	if (ufshcd_is_clkscaling_supported(hba)) {
8991	memcpy(&hba->clk_scaling.saved_pwr_info,
8992	&hba->pwr_info,
8993	sizeof(struct ufs_pa_layer_attr));
8994	hba->clk_scaling.is_allowed = true;
8995
8996	ret = ufshcd_devfreq_init(hba);
8997	if (ret)
8998	goto out;
8999
9000	hba->clk_scaling.is_enabled = true;
9001	ufshcd_init_clk_scaling_sysfs(hba);
9002	}
9003
9004	/*
9005	* The RTC update code accesses the hba->ufs_device_wlun->sdev_gendev
9006	* pointer and hence must only be started after the WLUN pointer has
9007	* been initialized by ufshcd_scsi_add_wlus().
9008	*/
9009	schedule_delayed_work(dwork: &hba->ufs_rtc_update_work,
9010	delay: msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS));
9011
9012	ufs_bsg_probe(hba);
9013	scsi_scan_host(hba->host);
9014	ufs_rpmb_probe(hba);
9015
9016	out:
9017	return ret;
9018	}
9019
9020	/* SDB - Single Doorbell */
9021	static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs)
9022	{
9023	size_t ucdl_size, utrdl_size;
9024
9025	ucdl_size = ufshcd_get_ucd_size(hba) * nutrs;
9026	dmam_free_coherent(dev: hba->dev, size: ucdl_size, vaddr: hba->ucdl_base_addr,
9027	dma_handle: hba->ucdl_dma_addr);
9028
9029	utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs;
9030	dmam_free_coherent(dev: hba->dev, size: utrdl_size, vaddr: hba->utrdl_base_addr,
9031	dma_handle: hba->utrdl_dma_addr);
9032	}
9033
9034	static int ufshcd_alloc_mcq(struct ufs_hba *hba)
9035	{
9036	int ret;
9037	int old_nutrs = hba->nutrs;
9038
9039	ret = ufshcd_get_hba_mac(hba);
9040	if (ret < 0)
9041	return ret;
9042
9043	hba->nutrs = ret;
9044	ret = ufshcd_mcq_init(hba);
9045	if (ret)
9046	goto err;
9047
9048	/*
9049	* Previously allocated memory for nutrs may not be enough in MCQ mode.
9050	* Number of supported tags in MCQ mode may be larger than SDB mode.
9051	*/
9052	if (hba->nutrs != old_nutrs) {
9053	ufshcd_release_sdb_queue(hba, nutrs: old_nutrs);
9054	ret = ufshcd_memory_alloc(hba);
9055	if (ret)
9056	goto err;
9057	ufshcd_host_memory_configure(hba);
9058	}
9059
9060	ret = ufshcd_mcq_memory_alloc(hba);
9061	if (ret)
9062	goto err;
9063
9064	hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
9065
9066	return 0;
9067	err:
9068	hba->nutrs = old_nutrs;
9069	return ret;
9070	}
9071
9072	static void ufshcd_config_mcq(struct ufs_hba *hba)
9073	{
9074	int ret;
9075
9076	ret = ufshcd_mcq_vops_config_esi(hba);
9077	hba->mcq_esi_enabled = !ret;
9078	dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
9079
9080	ufshcd_mcq_make_queues_operational(hba);
9081	ufshcd_mcq_config_mac(hba, max_active_cmds: hba->nutrs);
9082
9083	dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
9084	hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT],
9085	hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL],
9086	hba->nutrs);
9087	}
9088
9089	static int ufshcd_post_device_init(struct ufs_hba *hba)
9090	{
9091	int ret;
9092
9093	ufshcd_tune_unipro_params(hba);
9094
9095	/* UFS device is also active now */
9096	ufshcd_set_ufs_dev_active(hba);
9097	ufshcd_force_reset_auto_bkops(hba);
9098
9099	ufshcd_set_timestamp_attr(hba);
9100
9101	if (!hba->max_pwr_info.is_valid)
9102	return 0;
9103
9104	/*
9105	* Set the right value to bRefClkFreq before attempting to
9106	* switch to HS gears.
9107	*/
9108	if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
9109	ufshcd_set_dev_ref_clk(hba);
9110	/* Gear up to HS gear. */
9111	ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
9112	if (ret) {
9113	dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
9114	__func__, ret);
9115	return ret;
9116	}
9117
9118	return 0;
9119	}
9120
9121	static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
9122	{
9123	int ret;
9124
9125	WARN_ON_ONCE(!hba->scsi_host_added);
9126
9127	hba->ufshcd_state = UFSHCD_STATE_RESET;
9128
9129	ret = ufshcd_link_startup(hba);
9130	if (ret)
9131	return ret;
9132
9133	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
9134	return ret;
9135
9136	/* Debug counters initialization */
9137	ufshcd_clear_dbg_ufs_stats(hba);
9138
9139	/* UniPro link is active now */
9140	ufshcd_set_link_active(hba);
9141
9142	/* Reconfigure MCQ upon reset */
9143	if (hba->mcq_enabled && !init_dev_params) {
9144	ufshcd_config_mcq(hba);
9145	ufshcd_mcq_enable(hba);
9146	}
9147
9148	/* Verify device initialization by sending NOP OUT UPIU */
9149	ret = ufshcd_verify_dev_init(hba);
9150	if (ret)
9151	return ret;
9152
9153	/* Initiate UFS initialization, and waiting until completion */
9154	ret = ufshcd_complete_dev_init(hba);
9155	if (ret)
9156	return ret;
9157
9158	/*
9159	* Initialize UFS device parameters used by driver, these
9160	* parameters are associated with UFS descriptors.
9161	*/
9162	if (init_dev_params) {
9163	ret = ufshcd_device_params_init(hba);
9164	if (ret)
9165	return ret;
9166	if (is_mcq_supported(hba) &&
9167	hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) {
9168	ufshcd_config_mcq(hba);
9169	ufshcd_mcq_enable(hba);
9170	}
9171	}
9172
9173	return ufshcd_post_device_init(hba);
9174	}
9175
9176	/**
9177	* ufshcd_probe_hba - probe hba to detect device and initialize it
9178	* @hba: per-adapter instance
9179	* @init_dev_params: whether or not to call ufshcd_device_params_init().
9180	*
9181	* Execute link-startup and verify device initialization
9182	*
9183	* Return: 0 upon success; < 0 upon failure.
9184	*/
9185	static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
9186	{
9187	int ret;
9188
9189	if (!hba->pm_op_in_progress &&
9190	(hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) {
9191	/* Reset the device and controller before doing reinit */
9192	ufshcd_device_reset(hba);
9193	ufs_put_device_desc(hba);
9194	ufshcd_hba_stop(hba);
9195	ret = ufshcd_hba_enable(hba);
9196	if (ret) {
9197	dev_err(hba->dev, "Host controller enable failed\n");
9198	ufshcd_print_evt_hist(hba);
9199	ufshcd_print_host_state(hba);
9200	return ret;
9201	}
9202
9203	/* Reinit the device */
9204	ret = ufshcd_device_init(hba, init_dev_params);
9205	if (ret)
9206	return ret;
9207	}
9208
9209	ufshcd_print_pwr_info(hba);
9210
9211	/*
9212	* bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
9213	* and for removable UFS card as well, hence always set the parameter.
9214	* Note: Error handler may issue the device reset hence resetting
9215	* bActiveICCLevel as well so it is always safe to set this here.
9216	*/
9217	ufshcd_set_active_icc_lvl(hba);
9218
9219	/* Enable UFS Write Booster if supported */
9220	ufshcd_configure_wb(hba);
9221
9222	if (hba->ee_usr_mask)
9223	ufshcd_write_ee_control(hba);
9224	ufshcd_configure_auto_hibern8(hba);
9225
9226	return 0;
9227	}
9228
9229	/**
9230	* ufshcd_async_scan - asynchronous execution for probing hba
9231	* @data: data pointer to pass to this function
9232	* @cookie: cookie data
9233	*/
9234	static void ufshcd_async_scan(void *data, async_cookie_t cookie)
9235	{
9236	struct ufs_hba *hba = (struct ufs_hba *)data;
9237	ktime_t probe_start;
9238	int ret;
9239
9240	down(sem: &hba->host_sem);
9241	/* Initialize hba, detect and initialize UFS device */
9242	probe_start = ktime_get();
9243	ret = ufshcd_probe_hba(hba, init_dev_params: true);
9244	ufshcd_process_probe_result(hba, probe_start, ret);
9245	up(sem: &hba->host_sem);
9246	if (ret)
9247	goto out;
9248
9249	/* Probe and add UFS logical units */
9250	ret = ufshcd_add_lus(hba);
9251
9252	out:
9253	pm_runtime_put_sync(dev: hba->dev);
9254
9255	if (ret)
9256	dev_err(hba->dev, "%s failed: %d\n", __func__, ret);
9257	}
9258
9259	static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
9260	{
9261	struct ufs_hba *hba = shost_priv(shost: scmd->device->host);
9262
9263	if (!hba->system_suspending) {
9264	/* Activate the error handler in the SCSI core. */
9265	return SCSI_EH_NOT_HANDLED;
9266	}
9267
9268	/*
9269	* If we get here we know that no TMFs are outstanding and also that
9270	* the only pending command is a START STOP UNIT command. Handle the
9271	* timeout of that command directly to prevent a deadlock between
9272	* ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
9273	*/
9274	ufshcd_link_recovery(hba);
9275	dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
9276	__func__, hba->outstanding_tasks);
9277
9278	return scsi_host_busy(shost: hba->host) ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
9279	}
9280
9281	static const struct attribute_group *ufshcd_driver_groups[] = {
9282	&ufs_sysfs_unit_descriptor_group,
9283	&ufs_sysfs_lun_attributes_group,
9284	NULL,
9285	};
9286
9287	static struct ufs_hba_variant_params ufs_hba_vps = {
9288	.hba_enable_delay_us = 1000,
9289	.wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
9290	.devfreq_profile.polling_ms = 100,
9291	.devfreq_profile.target = ufshcd_devfreq_target,
9292	.devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
9293	.ondemand_data.upthreshold = 70,
9294	.ondemand_data.downdifferential = 5,
9295	};
9296
9297	static const struct scsi_host_template ufshcd_driver_template = {
9298	.module = THIS_MODULE,
9299	.name = UFSHCD,
9300	.proc_name = UFSHCD,
9301	.map_queues = ufshcd_map_queues,
9302	.cmd_size = sizeof(struct ufshcd_lrb),
9303	.init_cmd_priv = ufshcd_init_cmd_priv,
9304	.queuecommand = ufshcd_queuecommand,
9305	.queue_reserved_command = ufshcd_queue_reserved_command,
9306	.nr_reserved_cmds = UFSHCD_NUM_RESERVED,
9307	.mq_poll = ufshcd_poll,
9308	.sdev_init = ufshcd_sdev_init,
9309	.sdev_configure = ufshcd_sdev_configure,
9310	.sdev_destroy = ufshcd_sdev_destroy,
9311	.change_queue_depth = ufshcd_change_queue_depth,
9312	.eh_abort_handler = ufshcd_abort,
9313	.eh_device_reset_handler = ufshcd_eh_device_reset_handler,
9314	.eh_host_reset_handler = ufshcd_eh_host_reset_handler,
9315	.eh_timed_out = ufshcd_eh_timed_out,
9316	.this_id = -1,
9317	.sg_tablesize = SG_ALL,
9318	.max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
9319	.max_sectors = SZ_1M / SECTOR_SIZE,
9320	.max_host_blocked = 1,
9321	.track_queue_depth = 1,
9322	.skip_settle_delay = 1,
9323	.sdev_groups = ufshcd_driver_groups,
9324	};
9325
9326	static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
9327	int ua)
9328	{
9329	int ret;
9330
9331	if (!vreg)
9332	return 0;
9333
9334	/*
9335	* "set_load" operation shall be required on those regulators
9336	* which specifically configured current limitation. Otherwise
9337	* zero max_uA may cause unexpected behavior when regulator is
9338	* enabled or set as high power mode.
9339	*/
9340	if (!vreg->max_uA)
9341	return 0;
9342
9343	ret = regulator_set_load(regulator: vreg->reg, load_uA: ua);
9344	if (ret < 0) {
9345	dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
9346	__func__, vreg->name, ua, ret);
9347	}
9348
9349	return ret;
9350	}
9351
9352	static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
9353	struct ufs_vreg *vreg)
9354	{
9355	return ufshcd_config_vreg_load(dev: hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
9356	}
9357
9358	static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
9359	struct ufs_vreg *vreg)
9360	{
9361	if (!vreg)
9362	return 0;
9363
9364	return ufshcd_config_vreg_load(dev: hba->dev, vreg, ua: vreg->max_uA);
9365	}
9366
9367	static int ufshcd_config_vreg(struct device *dev,
9368	struct ufs_vreg *vreg, bool on)
9369	{
9370	if (regulator_count_voltages(regulator: vreg->reg) <= 0)
9371	return 0;
9372
9373	return ufshcd_config_vreg_load(dev, vreg, ua: on ? vreg->max_uA : 0);
9374	}
9375
9376	static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
9377	{
9378	int ret = 0;
9379
9380	if (!vreg || vreg->enabled)
9381	goto out;
9382
9383	ret = ufshcd_config_vreg(dev, vreg, on: true);
9384	if (!ret)
9385	ret = regulator_enable(regulator: vreg->reg);
9386
9387	if (!ret)
9388	vreg->enabled = true;
9389	else
9390	dev_err(dev, "%s: %s enable failed, err=%d\n",
9391	__func__, vreg->name, ret);
9392	out:
9393	return ret;
9394	}
9395
9396	static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
9397	{
9398	int ret = 0;
9399
9400	if (!vreg || !vreg->enabled || vreg->always_on)
9401	goto out;
9402
9403	ret = regulator_disable(regulator: vreg->reg);
9404
9405	if (!ret) {
9406	/* ignore errors on applying disable config */
9407	ufshcd_config_vreg(dev, vreg, on: false);
9408	vreg->enabled = false;
9409	} else {
9410	dev_err(dev, "%s: %s disable failed, err=%d\n",
9411	__func__, vreg->name, ret);
9412	}
9413	out:
9414	return ret;
9415	}
9416
9417	static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
9418	{
9419	int ret = 0;
9420	struct device *dev = hba->dev;
9421	struct ufs_vreg_info *info = &hba->vreg_info;
9422
9423	ret = ufshcd_toggle_vreg(dev, info->vcc, on);
9424	if (ret)
9425	goto out;
9426
9427	ret = ufshcd_toggle_vreg(dev, info->vccq, on);
9428	if (ret)
9429	goto out;
9430
9431	ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
9432
9433	out:
9434	if (ret) {
9435	ufshcd_toggle_vreg(dev, info->vccq2, false);
9436	ufshcd_toggle_vreg(dev, info->vccq, false);
9437	ufshcd_toggle_vreg(dev, info->vcc, false);
9438	}
9439	return ret;
9440	}
9441
9442	static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
9443	{
9444	struct ufs_vreg_info *info = &hba->vreg_info;
9445
9446	return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
9447	}
9448
9449	int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
9450	{
9451	int ret = 0;
9452
9453	if (!vreg)
9454	goto out;
9455
9456	vreg->reg = devm_regulator_get(dev, id: vreg->name);
9457	if (IS_ERR(ptr: vreg->reg)) {
9458	ret = PTR_ERR(ptr: vreg->reg);
9459	dev_err(dev, "%s: %s get failed, err=%d\n",
9460	__func__, vreg->name, ret);
9461	}
9462	out:
9463	return ret;
9464	}
9465	EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
9466
9467	static int ufshcd_init_vreg(struct ufs_hba *hba)
9468	{
9469	int ret = 0;
9470	struct device *dev = hba->dev;
9471	struct ufs_vreg_info *info = &hba->vreg_info;
9472
9473	ret = ufshcd_get_vreg(dev, info->vcc);
9474	if (ret)
9475	goto out;
9476
9477	ret = ufshcd_get_vreg(dev, info->vccq);
9478	if (!ret)
9479	ret = ufshcd_get_vreg(dev, info->vccq2);
9480	out:
9481	return ret;
9482	}
9483
9484	static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
9485	{
9486	struct ufs_vreg_info *info = &hba->vreg_info;
9487
9488	return ufshcd_get_vreg(hba->dev, info->vdd_hba);
9489	}
9490
9491	static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
9492	{
9493	int ret = 0;
9494	struct ufs_clk_info *clki;
9495	struct list_head *head = &hba->clk_list_head;
9496	ktime_t start = ktime_get();
9497	bool clk_state_changed = false;
9498
9499	if (list_empty(head))
9500	goto out;
9501
9502	ret = ufshcd_vops_setup_clocks(hba, on, status: PRE_CHANGE);
9503	if (ret)
9504	return ret;
9505
9506	list_for_each_entry(clki, head, list) {
9507	if (!IS_ERR_OR_NULL(ptr: clki->clk)) {
9508	/*
9509	* Don't disable clocks which are needed
9510	* to keep the link active.
9511	*/
9512	if (ufshcd_is_link_active(hba) &&
9513	clki->keep_link_active)
9514	continue;
9515
9516	clk_state_changed = on ^ clki->enabled;
9517	if (on && !clki->enabled) {
9518	ret = clk_prepare_enable(clk: clki->clk);
9519	if (ret) {
9520	dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
9521	__func__, clki->name, ret);
9522	goto out;
9523	}
9524	} else if (!on && clki->enabled) {
9525	clk_disable_unprepare(clk: clki->clk);
9526	}
9527	clki->enabled = on;
9528	dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
9529	clki->name, on ? "en" : "dis");
9530	}
9531	}
9532
9533	ret = ufshcd_vops_setup_clocks(hba, on, status: POST_CHANGE);
9534	if (ret)
9535	return ret;
9536
9537	if (!ufshcd_is_clkscaling_supported(hba))
9538	ufshcd_pm_qos_update(hba, on);
9539	out:
9540	if (ret) {
9541	list_for_each_entry(clki, head, list) {
9542	if (!IS_ERR_OR_NULL(ptr: clki->clk) && clki->enabled)
9543	clk_disable_unprepare(clk: clki->clk);
9544	}
9545	} else if (!ret && on && hba->clk_gating.is_initialized) {
9546	scoped_guard(spinlock_irqsave, &hba->clk_gating.lock)
9547	hba->clk_gating.state = CLKS_ON;
9548	trace_ufshcd_clk_gating(hba,
9549	state: hba->clk_gating.state);
9550	}
9551
9552	if (clk_state_changed)
9553	trace_ufshcd_profile_clk_gating(hba,
9554	profile_info: (on ? "on" : "off"),
9555	time_us: ktime_to_us(ktime_sub(ktime_get(), start)), err: ret);
9556	return ret;
9557	}
9558
9559	static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
9560	{
9561	u32 freq;
9562	int ret = device_property_read_u32(dev: hba->dev, propname: "ref-clk-freq", val: &freq);
9563
9564	if (ret) {
9565	dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
9566	return REF_CLK_FREQ_INVAL;
9567	}
9568
9569	return ufs_get_bref_clk_from_hz(freq);
9570	}
9571
9572	static int ufshcd_init_clocks(struct ufs_hba *hba)
9573	{
9574	int ret = 0;
9575	struct ufs_clk_info *clki;
9576	struct device *dev = hba->dev;
9577	struct list_head *head = &hba->clk_list_head;
9578
9579	if (list_empty(head))
9580	goto out;
9581
9582	list_for_each_entry(clki, head, list) {
9583	if (!clki->name)
9584	continue;
9585
9586	clki->clk = devm_clk_get(dev, id: clki->name);
9587	if (IS_ERR(ptr: clki->clk)) {
9588	ret = PTR_ERR(ptr: clki->clk);
9589	dev_err(dev, "%s: %s clk get failed, %d\n",
9590	__func__, clki->name, ret);
9591	goto out;
9592	}
9593
9594	/*
9595	* Parse device ref clk freq as per device tree "ref_clk".
9596	* Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
9597	* in ufshcd_alloc_host().
9598	*/
9599	if (!strcmp(clki->name, "ref_clk"))
9600	ufshcd_parse_dev_ref_clk_freq(hba, refclk: clki->clk);
9601
9602	if (clki->max_freq) {
9603	ret = clk_set_rate(clk: clki->clk, rate: clki->max_freq);
9604	if (ret) {
9605	dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
9606	__func__, clki->name,
9607	clki->max_freq, ret);
9608	goto out;
9609	}
9610	clki->curr_freq = clki->max_freq;
9611	}
9612	dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
9613	clki->name, clk_get_rate(clki->clk));
9614	}
9615
9616	/* Set Max. frequency for all clocks */
9617	if (hba->use_pm_opp) {
9618	ret = ufshcd_opp_set_rate(hba, ULONG_MAX);
9619	if (ret) {
9620	dev_err(hba->dev, "%s: failed to set OPP: %d", __func__,
9621	ret);
9622	goto out;
9623	}
9624	}
9625
9626	out:
9627	return ret;
9628	}
9629
9630	static int ufshcd_variant_hba_init(struct ufs_hba *hba)
9631	{
9632	int err = 0;
9633
9634	if (!hba->vops)
9635	goto out;
9636
9637	err = ufshcd_vops_init(hba);
9638	if (err)
9639	dev_err_probe(dev: hba->dev, err,
9640	fmt: "%s: variant %s init failed with err %d\n",
9641	__func__, ufshcd_get_var_name(hba), err);
9642	out:
9643	return err;
9644	}
9645
9646	static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
9647	{
9648	if (!hba->vops)
9649	return;
9650
9651	ufshcd_vops_exit(hba);
9652	}
9653
9654	static int ufshcd_hba_init(struct ufs_hba *hba)
9655	{
9656	int err;
9657
9658	/*
9659	* Handle host controller power separately from the UFS device power
9660	* rails as it will help controlling the UFS host controller power
9661	* collapse easily which is different than UFS device power collapse.
9662	* Also, enable the host controller power before we go ahead with rest
9663	* of the initialization here.
9664	*/
9665	err = ufshcd_init_hba_vreg(hba);
9666	if (err)
9667	goto out;
9668
9669	err = ufshcd_setup_hba_vreg(hba, on: true);
9670	if (err)
9671	goto out;
9672
9673	err = ufshcd_init_clocks(hba);
9674	if (err)
9675	goto out_disable_hba_vreg;
9676
9677	if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
9678	hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
9679
9680	err = ufshcd_setup_clocks(hba, on: true);
9681	if (err)
9682	goto out_disable_hba_vreg;
9683
9684	err = ufshcd_init_vreg(hba);
9685	if (err)
9686	goto out_disable_clks;
9687
9688	err = ufshcd_setup_vreg(hba, on: true);
9689	if (err)
9690	goto out_disable_clks;
9691
9692	err = ufshcd_variant_hba_init(hba);
9693	if (err)
9694	goto out_disable_vreg;
9695
9696	ufs_debugfs_hba_init(hba);
9697	ufs_fault_inject_hba_init(hba);
9698
9699	hba->is_powered = true;
9700	goto out;
9701
9702	out_disable_vreg:
9703	ufshcd_setup_vreg(hba, on: false);
9704	out_disable_clks:
9705	ufshcd_setup_clocks(hba, on: false);
9706	out_disable_hba_vreg:
9707	ufshcd_setup_hba_vreg(hba, on: false);
9708	out:
9709	return err;
9710	}
9711
9712	static void ufshcd_hba_exit(struct ufs_hba *hba)
9713	{
9714	if (hba->is_powered) {
9715	ufshcd_pm_qos_exit(hba);
9716	ufshcd_exit_clk_scaling(hba);
9717	ufshcd_exit_clk_gating(hba);
9718	if (hba->eh_wq)
9719	destroy_workqueue(wq: hba->eh_wq);
9720	ufs_debugfs_hba_exit(hba);
9721	ufshcd_variant_hba_exit(hba);
9722	ufshcd_setup_vreg(hba, on: false);
9723	ufshcd_setup_clocks(hba, on: false);
9724	ufshcd_setup_hba_vreg(hba, on: false);
9725	hba->is_powered = false;
9726	ufs_put_device_desc(hba);
9727	}
9728	}
9729
9730	static int ufshcd_execute_start_stop(struct scsi_device *sdev,
9731	enum ufs_dev_pwr_mode pwr_mode,
9732	struct scsi_sense_hdr *sshdr)
9733	{
9734	const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
9735	struct scsi_failure failure_defs[] = {
9736	{
9737	.allowed = 2,
9738	.result = SCMD_FAILURE_RESULT_ANY,
9739	},
9740	};
9741	struct scsi_failures failures = {
9742	.failure_definitions = failure_defs,
9743	};
9744	const struct scsi_exec_args args = {
9745	.failures = &failures,
9746	.sshdr = sshdr,
9747	.req_flags = BLK_MQ_REQ_PM,
9748	.scmd_flags = SCMD_FAIL_IF_RECOVERING,
9749	};
9750
9751	return scsi_execute_cmd(sdev, cmd: cdb, opf: REQ_OP_DRV_IN, /*buffer=*/NULL,
9752	/*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0,
9753	args: &args);
9754	}
9755
9756	/**
9757	* ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
9758	* power mode
9759	* @hba: per adapter instance
9760	* @pwr_mode: device power mode to set
9761	*
9762	* Return: 0 if requested power mode is set successfully;
9763	* < 0 if failed to set the requested power mode.
9764	*/
9765	static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
9766	enum ufs_dev_pwr_mode pwr_mode)
9767	{
9768	struct scsi_sense_hdr sshdr;
9769	struct scsi_device *sdp;
9770	unsigned long flags;
9771	int ret;
9772
9773	spin_lock_irqsave(hba->host->host_lock, flags);
9774	sdp = hba->ufs_device_wlun;
9775	if (sdp && scsi_device_online(sdev: sdp))
9776	ret = scsi_device_get(sdp);
9777	else
9778	ret = -ENODEV;
9779	spin_unlock_irqrestore(lock: hba->host->host_lock, flags);
9780
9781	if (ret)
9782	return ret;
9783
9784	/*
9785	* If scsi commands fail, the scsi mid-layer schedules scsi error-
9786	* handling, which would wait for host to be resumed. Since we know
9787	* we are functional while we are here, skip host resume in error
9788	* handling context.
9789	*/
9790	hba->host->eh_noresume = 1;
9791
9792	/*
9793	* Current function would be generally called from the power management
9794	* callbacks hence set the RQF_PM flag so that it doesn't resume the
9795	* already suspended childs.
9796	*/
9797	ret = ufshcd_execute_start_stop(sdev: sdp, pwr_mode, sshdr: &sshdr);
9798	if (ret) {
9799	sdev_printk(KERN_WARNING, sdp,
9800	"START_STOP failed for power mode: %d, result %x\n",
9801	pwr_mode, ret);
9802	if (ret > 0) {
9803	if (scsi_sense_valid(sshdr: &sshdr))
9804	scsi_print_sense_hdr(sdp, NULL, &sshdr);
9805	ret = -EIO;
9806	}
9807	} else {
9808	hba->curr_dev_pwr_mode = pwr_mode;
9809	}
9810
9811	scsi_device_put(sdp);
9812	hba->host->eh_noresume = 0;
9813	return ret;
9814	}
9815
9816	static int ufshcd_link_state_transition(struct ufs_hba *hba,
9817	enum uic_link_state req_link_state,
9818	bool check_for_bkops)
9819	{
9820	int ret = 0;
9821
9822	if (req_link_state == hba->uic_link_state)
9823	return 0;
9824
9825	if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9826	ret = ufshcd_uic_hibern8_enter(hba);
9827	if (!ret) {
9828	ufshcd_set_link_hibern8(hba);
9829	} else {
9830	dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9831	__func__, ret);
9832	goto out;
9833	}
9834	}
9835	/*
9836	* If autobkops is enabled, link can't be turned off because
9837	* turning off the link would also turn off the device, except in the
9838	* case of DeepSleep where the device is expected to remain powered.
9839	*/
9840	else if ((req_link_state == UIC_LINK_OFF_STATE) &&
9841	(!check_for_bkops || !hba->auto_bkops_enabled)) {
9842	/*
9843	* Let's make sure that link is in low power mode, we are doing
9844	* this currently by putting the link in Hibern8. Otherway to
9845	* put the link in low power mode is to send the DME end point
9846	* to device and then send the DME reset command to local
9847	* unipro. But putting the link in hibern8 is much faster.
9848	*
9849	* Note also that putting the link in Hibern8 is a requirement
9850	* for entering DeepSleep.
9851	*/
9852	ret = ufshcd_uic_hibern8_enter(hba);
9853	if (ret) {
9854	dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9855	__func__, ret);
9856	goto out;
9857	}
9858	/*
9859	* Change controller state to "reset state" which
9860	* should also put the link in off/reset state
9861	*/
9862	ufshcd_hba_stop(hba);
9863	/*
9864	* TODO: Check if we need any delay to make sure that
9865	* controller is reset
9866	*/
9867	ufshcd_set_link_off(hba);
9868	}
9869
9870	out:
9871	return ret;
9872	}
9873
9874	static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9875	{
9876	bool vcc_off = false;
9877
9878	/*
9879	* It seems some UFS devices may keep drawing more than sleep current
9880	* (atleast for 500us) from UFS rails (especially from VCCQ rail).
9881	* To avoid this situation, add 2ms delay before putting these UFS
9882	* rails in LPM mode.
9883	*/
9884	if (!ufshcd_is_link_active(hba) &&
9885	hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9886	usleep_range(min: 2000, max: 2100);
9887
9888	/*
9889	* If UFS device is either in UFS_Sleep turn off VCC rail to save some
9890	* power.
9891	*
9892	* If UFS device and link is in OFF state, all power supplies (VCC,
9893	* VCCQ, VCCQ2) can be turned off if power on write protect is not
9894	* required. If UFS link is inactive (Hibern8 or OFF state) and device
9895	* is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9896	*
9897	* Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9898	* in low power state which would save some power.
9899	*
9900	* If Write Booster is enabled and the device needs to flush the WB
9901	* buffer OR if bkops status is urgent for WB, keep Vcc on.
9902	*/
9903	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9904	!hba->dev_info.is_lu_power_on_wp) {
9905	ufshcd_setup_vreg(hba, on: false);
9906	vcc_off = true;
9907	} else if (!ufshcd_is_ufs_dev_active(hba)) {
9908	ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9909	vcc_off = true;
9910	if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
9911	ufshcd_config_vreg_lpm(hba, vreg: hba->vreg_info.vccq);
9912	ufshcd_config_vreg_lpm(hba, vreg: hba->vreg_info.vccq2);
9913	}
9914	}
9915
9916	/*
9917	* All UFS devices require delay after VCC power rail is turned-off.
9918	*/
9919	if (vcc_off && hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
9920	usleep_range(min: hba->vcc_off_delay_us,
9921	max: hba->vcc_off_delay_us + 100);
9922	}
9923
9924	#ifdef CONFIG_PM
9925	static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9926	{
9927	int ret = 0;
9928
9929	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9930	!hba->dev_info.is_lu_power_on_wp) {
9931	ret = ufshcd_setup_vreg(hba, on: true);
9932	} else if (!ufshcd_is_ufs_dev_active(hba)) {
9933	if (!ufshcd_is_link_active(hba)) {
9934	ret = ufshcd_config_vreg_hpm(hba, vreg: hba->vreg_info.vccq);
9935	if (ret)
9936	goto vcc_disable;
9937	ret = ufshcd_config_vreg_hpm(hba, vreg: hba->vreg_info.vccq2);
9938	if (ret)
9939	goto vccq_lpm;
9940	}
9941	ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
9942	}
9943	goto out;
9944
9945	vccq_lpm:
9946	ufshcd_config_vreg_lpm(hba, vreg: hba->vreg_info.vccq);
9947	vcc_disable:
9948	ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9949	out:
9950	return ret;
9951	}
9952	#endif /* CONFIG_PM */
9953
9954	static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9955	{
9956	if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9957	ufshcd_setup_hba_vreg(hba, on: false);
9958	}
9959
9960	static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9961	{
9962	if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9963	ufshcd_setup_hba_vreg(hba, on: true);
9964	}
9965
9966	static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9967	{
9968	int ret = 0;
9969	bool check_for_bkops;
9970	enum ufs_pm_level pm_lvl;
9971	enum ufs_dev_pwr_mode req_dev_pwr_mode;
9972	enum uic_link_state req_link_state;
9973
9974	hba->pm_op_in_progress = true;
9975	if (pm_op != UFS_SHUTDOWN_PM) {
9976	pm_lvl = pm_op == UFS_RUNTIME_PM ?
9977	hba->rpm_lvl : hba->spm_lvl;
9978	req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(lvl: pm_lvl);
9979	req_link_state = ufs_get_pm_lvl_to_link_pwr_state(lvl: pm_lvl);
9980	} else {
9981	req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9982	req_link_state = UIC_LINK_OFF_STATE;
9983	}
9984
9985	/*
9986	* If we can't transition into any of the low power modes
9987	* just gate the clocks.
9988	*/
9989	ufshcd_hold(hba);
9990	hba->clk_gating.is_suspended = true;
9991
9992	if (ufshcd_is_clkscaling_supported(hba))
9993	ufshcd_clk_scaling_suspend(hba, suspend: true);
9994
9995	if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9996	req_link_state == UIC_LINK_ACTIVE_STATE) {
9997	goto vops_suspend;
9998	}
9999
10000	if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
10001	(req_link_state == hba->uic_link_state))
10002	goto enable_scaling;
10003
10004	/* UFS device & link must be active before we enter in this function */
10005	if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
10006	/* Wait err handler finish or trigger err recovery */
10007	if (!ufshcd_eh_in_progress(hba))
10008	ufshcd_force_error_recovery(hba);
10009	ret = -EBUSY;
10010	goto enable_scaling;
10011	}
10012
10013	if (pm_op == UFS_RUNTIME_PM) {
10014	if (ufshcd_can_autobkops_during_suspend(hba)) {
10015	/*
10016	* The device is idle with no requests in the queue,
10017	* allow background operations if bkops status shows
10018	* that performance might be impacted.
10019	*/
10020	ret = ufshcd_bkops_ctrl(hba);
10021	if (ret) {
10022	/*
10023	* If return err in suspend flow, IO will hang.
10024	* Trigger error handler and break suspend for
10025	* error recovery.
10026	*/
10027	ufshcd_force_error_recovery(hba);
10028	ret = -EBUSY;
10029	goto enable_scaling;
10030	}
10031	} else {
10032	/* make sure that auto bkops is disabled */
10033	ufshcd_disable_auto_bkops(hba);
10034	}
10035	/*
10036	* If device needs to do BKOP or WB buffer flush during
10037	* Hibern8, keep device power mode as "active power mode"
10038	* and VCC supply.
10039	*/
10040	hba->dev_info.b_rpm_dev_flush_capable =
10041	hba->auto_bkops_enabled ||
10042	(((req_link_state == UIC_LINK_HIBERN8_STATE) ||
10043	((req_link_state == UIC_LINK_ACTIVE_STATE) &&
10044	ufshcd_is_auto_hibern8_enabled(hba))) &&
10045	ufshcd_wb_need_flush(hba));
10046	}
10047
10048	flush_work(work: &hba->eeh_work);
10049
10050	ret = ufshcd_vops_suspend(hba, op: pm_op, status: PRE_CHANGE);
10051	if (ret)
10052	goto enable_scaling;
10053
10054	if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
10055	if (pm_op != UFS_RUNTIME_PM)
10056	/* ensure that bkops is disabled */
10057	ufshcd_disable_auto_bkops(hba);
10058
10059	if (!hba->dev_info.b_rpm_dev_flush_capable) {
10060	ret = ufshcd_set_dev_pwr_mode(hba, pwr_mode: req_dev_pwr_mode);
10061	if (ret && pm_op != UFS_SHUTDOWN_PM) {
10062	/*
10063	* If return err in suspend flow, IO will hang.
10064	* Trigger error handler and break suspend for
10065	* error recovery.
10066	*/
10067	ufshcd_force_error_recovery(hba);
10068	ret = -EBUSY;
10069	}
10070	if (ret)
10071	goto enable_scaling;
10072	}
10073	}
10074
10075	/*
10076	* In the case of DeepSleep, the device is expected to remain powered
10077	* with the link off, so do not check for bkops.
10078	*/
10079	check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
10080	ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
10081	if (ret && pm_op != UFS_SHUTDOWN_PM) {
10082	/*
10083	* If return err in suspend flow, IO will hang.
10084	* Trigger error handler and break suspend for
10085	* error recovery.
10086	*/
10087	ufshcd_force_error_recovery(hba);
10088	ret = -EBUSY;
10089	}
10090	if (ret)
10091	goto set_dev_active;
10092
10093	vops_suspend:
10094	/*
10095	* Call vendor specific suspend callback. As these callbacks may access
10096	* vendor specific host controller register space call them before the
10097	* host clocks are ON.
10098	*/
10099	ret = ufshcd_vops_suspend(hba, op: pm_op, status: POST_CHANGE);
10100	if (ret)
10101	goto set_link_active;
10102
10103	cancel_delayed_work_sync(dwork: &hba->ufs_rtc_update_work);
10104	goto out;
10105
10106	set_link_active:
10107	/*
10108	* Device hardware reset is required to exit DeepSleep. Also, for
10109	* DeepSleep, the link is off so host reset and restore will be done
10110	* further below.
10111	*/
10112	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
10113	ufshcd_device_reset(hba);
10114	WARN_ON(!ufshcd_is_link_off(hba));
10115	}
10116	if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
10117	ufshcd_set_link_active(hba);
10118	else if (ufshcd_is_link_off(hba))
10119	ufshcd_host_reset_and_restore(hba);
10120	set_dev_active:
10121	/* Can also get here needing to exit DeepSleep */
10122	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
10123	ufshcd_device_reset(hba);
10124	ufshcd_host_reset_and_restore(hba);
10125	}
10126	if (!ufshcd_set_dev_pwr_mode(hba, pwr_mode: UFS_ACTIVE_PWR_MODE))
10127	ufshcd_disable_auto_bkops(hba);
10128	enable_scaling:
10129	if (ufshcd_is_clkscaling_supported(hba))
10130	ufshcd_clk_scaling_suspend(hba, suspend: false);
10131
10132	hba->dev_info.b_rpm_dev_flush_capable = false;
10133	out:
10134	if (hba->dev_info.b_rpm_dev_flush_capable) {
10135	schedule_delayed_work(dwork: &hba->rpm_dev_flush_recheck_work,
10136	delay: msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
10137	}
10138
10139	if (ret) {
10140	ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
10141	hba->clk_gating.is_suspended = false;
10142	ufshcd_release(hba);
10143	}
10144	hba->pm_op_in_progress = false;
10145	return ret;
10146	}
10147
10148	#ifdef CONFIG_PM
10149	static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
10150	{
10151	int ret;
10152	enum uic_link_state old_link_state = hba->uic_link_state;
10153
10154	hba->pm_op_in_progress = true;
10155
10156	/*
10157	* Call vendor specific resume callback. As these callbacks may access
10158	* vendor specific host controller register space call them when the
10159	* host clocks are ON.
10160	*/
10161	ret = ufshcd_vops_resume(hba, op: pm_op);
10162	if (ret)
10163	goto out;
10164
10165	/* For DeepSleep, the only supported option is to have the link off */
10166	WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
10167
10168	if (ufshcd_is_link_hibern8(hba)) {
10169	ret = ufshcd_uic_hibern8_exit(hba);
10170	if (!ret) {
10171	ufshcd_set_link_active(hba);
10172	} else {
10173	dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
10174	__func__, ret);
10175	goto vendor_suspend;
10176	}
10177	} else if (ufshcd_is_link_off(hba)) {
10178	/*
10179	* A full initialization of the host and the device is
10180	* required since the link was put to off during suspend.
10181	* Note, in the case of DeepSleep, the device will exit
10182	* DeepSleep due to device reset.
10183	*/
10184	ret = ufshcd_reset_and_restore(hba);
10185	/*
10186	* ufshcd_reset_and_restore() should have already
10187	* set the link state as active
10188	*/
10189	if (ret || !ufshcd_is_link_active(hba))
10190	goto vendor_suspend;
10191	}
10192
10193	if (!ufshcd_is_ufs_dev_active(hba)) {
10194	ret = ufshcd_set_dev_pwr_mode(hba, pwr_mode: UFS_ACTIVE_PWR_MODE);
10195	if (ret)
10196	goto set_old_link_state;
10197	ufshcd_set_timestamp_attr(hba);
10198	schedule_delayed_work(dwork: &hba->ufs_rtc_update_work,
10199	delay: msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS));
10200	}
10201
10202	if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
10203	ufshcd_enable_auto_bkops(hba);
10204	else
10205	/*
10206	* If BKOPs operations are urgently needed at this moment then
10207	* keep auto-bkops enabled or else disable it.
10208	*/
10209	ufshcd_bkops_ctrl(hba);
10210
10211	if (hba->ee_usr_mask)
10212	ufshcd_write_ee_control(hba);
10213
10214	if (ufshcd_is_clkscaling_supported(hba))
10215	ufshcd_clk_scaling_suspend(hba, suspend: false);
10216
10217	if (hba->dev_info.b_rpm_dev_flush_capable) {
10218	hba->dev_info.b_rpm_dev_flush_capable = false;
10219	cancel_delayed_work(dwork: &hba->rpm_dev_flush_recheck_work);
10220	}
10221
10222	ufshcd_configure_auto_hibern8(hba);
10223
10224	goto out;
10225
10226	set_old_link_state:
10227	ufshcd_link_state_transition(hba, req_link_state: old_link_state, check_for_bkops: 0);
10228	vendor_suspend:
10229	ufshcd_vops_suspend(hba, op: pm_op, status: PRE_CHANGE);
10230	ufshcd_vops_suspend(hba, op: pm_op, status: POST_CHANGE);
10231	out:
10232	if (ret)
10233	ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
10234	hba->clk_gating.is_suspended = false;
10235	ufshcd_release(hba);
10236	hba->pm_op_in_progress = false;
10237	return ret;
10238	}
10239
10240	static int ufshcd_wl_runtime_suspend(struct device *dev)
10241	{
10242	struct scsi_device *sdev = to_scsi_device(dev);
10243	struct ufs_hba *hba;
10244	int ret;
10245	ktime_t start = ktime_get();
10246
10247	hba = shost_priv(shost: sdev->host);
10248
10249	ret = __ufshcd_wl_suspend(hba, pm_op: UFS_RUNTIME_PM);
10250	if (ret)
10251	dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10252
10253	trace_ufshcd_wl_runtime_suspend(hba, err: ret,
10254	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10255	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10256
10257	return ret;
10258	}
10259
10260	static int ufshcd_wl_runtime_resume(struct device *dev)
10261	{
10262	struct scsi_device *sdev = to_scsi_device(dev);
10263	struct ufs_hba *hba;
10264	int ret = 0;
10265	ktime_t start = ktime_get();
10266
10267	hba = shost_priv(shost: sdev->host);
10268
10269	ret = __ufshcd_wl_resume(hba, pm_op: UFS_RUNTIME_PM);
10270	if (ret)
10271	dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10272
10273	trace_ufshcd_wl_runtime_resume(hba, err: ret,
10274	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10275	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10276
10277	return ret;
10278	}
10279	#endif
10280
10281	#ifdef CONFIG_PM_SLEEP
10282	static int ufshcd_wl_suspend(struct device *dev)
10283	{
10284	struct scsi_device *sdev = to_scsi_device(dev);
10285	struct ufs_hba *hba;
10286	int ret = 0;
10287	ktime_t start = ktime_get();
10288
10289	hba = shost_priv(shost: sdev->host);
10290	down(sem: &hba->host_sem);
10291	hba->system_suspending = true;
10292
10293	if (pm_runtime_suspended(dev))
10294	goto out;
10295
10296	ret = __ufshcd_wl_suspend(hba, pm_op: UFS_SYSTEM_PM);
10297	if (ret) {
10298	dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10299	up(sem: &hba->host_sem);
10300	}
10301
10302	out:
10303	if (!ret)
10304	hba->is_sys_suspended = true;
10305	trace_ufshcd_wl_suspend(hba, err: ret,
10306	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10307	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10308
10309	return ret;
10310	}
10311
10312	static int ufshcd_wl_resume(struct device *dev)
10313	{
10314	struct scsi_device *sdev = to_scsi_device(dev);
10315	struct ufs_hba *hba;
10316	int ret = 0;
10317	ktime_t start = ktime_get();
10318
10319	hba = shost_priv(shost: sdev->host);
10320
10321	if (pm_runtime_suspended(dev))
10322	goto out;
10323
10324	ret = __ufshcd_wl_resume(hba, pm_op: UFS_SYSTEM_PM);
10325	if (ret)
10326	dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10327	out:
10328	trace_ufshcd_wl_resume(hba, err: ret,
10329	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10330	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10331	if (!ret)
10332	hba->is_sys_suspended = false;
10333	hba->system_suspending = false;
10334	up(sem: &hba->host_sem);
10335	return ret;
10336	}
10337	#endif
10338
10339	/**
10340	* ufshcd_suspend - helper function for suspend operations
10341	* @hba: per adapter instance
10342	*
10343	* This function will put disable irqs, turn off clocks
10344	* and set vreg and hba-vreg in lpm mode.
10345	*
10346	* Return: 0 upon success; < 0 upon failure.
10347	*/
10348	static int ufshcd_suspend(struct ufs_hba *hba)
10349	{
10350	int ret;
10351
10352	if (!hba->is_powered)
10353	return 0;
10354	/*
10355	* Disable the host irq as host controller as there won't be any
10356	* host controller transaction expected till resume.
10357	*/
10358	ufshcd_disable_irq(hba);
10359	ret = ufshcd_setup_clocks(hba, on: false);
10360	if (ret) {
10361	ufshcd_enable_irq(hba);
10362	goto out;
10363	}
10364	if (ufshcd_is_clkgating_allowed(hba)) {
10365	hba->clk_gating.state = CLKS_OFF;
10366	trace_ufshcd_clk_gating(hba,
10367	state: hba->clk_gating.state);
10368	}
10369
10370	ufshcd_vreg_set_lpm(hba);
10371	/* Put the host controller in low power mode if possible */
10372	ufshcd_hba_vreg_set_lpm(hba);
10373	ufshcd_pm_qos_update(hba, false);
10374	out:
10375	if (ret)
10376	ufshcd_update_evt_hist(hba, UFS_EVT_SUSPEND_ERR, (u32)ret);
10377	return ret;
10378	}
10379
10380	#ifdef CONFIG_PM
10381	/**
10382	* ufshcd_resume - helper function for resume operations
10383	* @hba: per adapter instance
10384	*
10385	* This function basically turns on the regulators, clocks and
10386	* irqs of the hba.
10387	*
10388	* Return: 0 for success and non-zero for failure.
10389	*/
10390	static int ufshcd_resume(struct ufs_hba *hba)
10391	{
10392	int ret;
10393
10394	if (!hba->is_powered)
10395	return 0;
10396
10397	ufshcd_hba_vreg_set_hpm(hba);
10398	ret = ufshcd_vreg_set_hpm(hba);
10399	if (ret)
10400	goto out;
10401
10402	/* Make sure clocks are enabled before accessing controller */
10403	ret = ufshcd_setup_clocks(hba, on: true);
10404	if (ret)
10405	goto disable_vreg;
10406
10407	/* enable the host irq as host controller would be active soon */
10408	ufshcd_enable_irq(hba);
10409
10410	goto out;
10411
10412	disable_vreg:
10413	ufshcd_vreg_set_lpm(hba);
10414	out:
10415	if (ret)
10416	ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
10417	return ret;
10418	}
10419	#endif /* CONFIG_PM */
10420
10421	#ifdef CONFIG_PM_SLEEP
10422	/**
10423	* ufshcd_system_suspend - system suspend callback
10424	* @dev: Device associated with the UFS controller.
10425	*
10426	* Executed before putting the system into a sleep state in which the contents
10427	* of main memory are preserved.
10428	*
10429	* Return: 0 for success and non-zero for failure.
10430	*/
10431	int ufshcd_system_suspend(struct device *dev)
10432	{
10433	struct ufs_hba *hba = dev_get_drvdata(dev);
10434	int ret = 0;
10435	ktime_t start = ktime_get();
10436
10437	if (pm_runtime_suspended(dev: hba->dev))
10438	goto out;
10439
10440	ret = ufshcd_suspend(hba);
10441	out:
10442	trace_ufshcd_system_suspend(hba, err: ret,
10443	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10444	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10445	return ret;
10446	}
10447	EXPORT_SYMBOL(ufshcd_system_suspend);
10448
10449	/**
10450	* ufshcd_system_resume - system resume callback
10451	* @dev: Device associated with the UFS controller.
10452	*
10453	* Executed after waking the system up from a sleep state in which the contents
10454	* of main memory were preserved.
10455	*
10456	* Return: 0 for success and non-zero for failure.
10457	*/
10458	int ufshcd_system_resume(struct device *dev)
10459	{
10460	struct ufs_hba *hba = dev_get_drvdata(dev);
10461	ktime_t start = ktime_get();
10462	int ret = 0;
10463
10464	if (pm_runtime_suspended(dev: hba->dev))
10465	goto out;
10466
10467	ret = ufshcd_resume(hba);
10468
10469	out:
10470	trace_ufshcd_system_resume(hba, err: ret,
10471	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10472	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10473
10474	return ret;
10475	}
10476	EXPORT_SYMBOL(ufshcd_system_resume);
10477	#endif /* CONFIG_PM_SLEEP */
10478
10479	#ifdef CONFIG_PM
10480	/**
10481	* ufshcd_runtime_suspend - runtime suspend callback
10482	* @dev: Device associated with the UFS controller.
10483	*
10484	* Check the description of ufshcd_suspend() function for more details.
10485	*
10486	* Return: 0 for success and non-zero for failure.
10487	*/
10488	int ufshcd_runtime_suspend(struct device *dev)
10489	{
10490	struct ufs_hba *hba = dev_get_drvdata(dev);
10491	int ret;
10492	ktime_t start = ktime_get();
10493
10494	ret = ufshcd_suspend(hba);
10495
10496	trace_ufshcd_runtime_suspend(hba, err: ret,
10497	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10498	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10499	return ret;
10500	}
10501	EXPORT_SYMBOL(ufshcd_runtime_suspend);
10502
10503	/**
10504	* ufshcd_runtime_resume - runtime resume routine
10505	* @dev: Device associated with the UFS controller.
10506	*
10507	* This function basically brings controller
10508	* to active state. Following operations are done in this function:
10509	*
10510	* 1. Turn on all the controller related clocks
10511	* 2. Turn ON VCC rail
10512	*
10513	* Return: 0 upon success; < 0 upon failure.
10514	*/
10515	int ufshcd_runtime_resume(struct device *dev)
10516	{
10517	struct ufs_hba *hba = dev_get_drvdata(dev);
10518	int ret;
10519	ktime_t start = ktime_get();
10520
10521	ret = ufshcd_resume(hba);
10522
10523	trace_ufshcd_runtime_resume(hba, err: ret,
10524	usecs: ktime_to_us(ktime_sub(ktime_get(), start)),
10525	dev_state: hba->curr_dev_pwr_mode, link_state: hba->uic_link_state);
10526	return ret;
10527	}
10528	EXPORT_SYMBOL(ufshcd_runtime_resume);
10529	#endif /* CONFIG_PM */
10530
10531	static void ufshcd_wl_shutdown(struct device *dev)
10532	{
10533	struct scsi_device *sdev = to_scsi_device(dev);
10534	struct ufs_hba *hba = shost_priv(shost: sdev->host);
10535
10536	down(sem: &hba->host_sem);
10537	hba->shutting_down = true;
10538	up(sem: &hba->host_sem);
10539
10540	/* Turn on everything while shutting down */
10541	ufshcd_rpm_get_sync(hba);
10542	scsi_device_quiesce(sdev);
10543	shost_for_each_device(sdev, hba->host) {
10544	if (sdev == hba->ufs_device_wlun)
10545	continue;
10546	mutex_lock(&sdev->state_mutex);
10547	scsi_device_set_state(sdev, state: SDEV_OFFLINE);
10548	mutex_unlock(lock: &sdev->state_mutex);
10549	}
10550	__ufshcd_wl_suspend(hba, pm_op: UFS_SHUTDOWN_PM);
10551
10552	/*
10553	* Next, turn off the UFS controller and the UFS regulators. Disable
10554	* clocks.
10555	*/
10556	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
10557	ufshcd_suspend(hba);
10558
10559	hba->is_powered = false;
10560	}
10561
10562	/**
10563	* ufshcd_remove - de-allocate SCSI host and host memory space
10564	* data structure memory
10565	* @hba: per adapter instance
10566	*/
10567	void ufshcd_remove(struct ufs_hba *hba)
10568	{
10569	if (hba->ufs_device_wlun)
10570	ufshcd_rpm_get_sync(hba);
10571	ufs_hwmon_remove(hba);
10572	ufs_bsg_remove(hba);
10573	ufs_rpmb_remove(hba);
10574	ufs_sysfs_remove_nodes(dev: hba->dev);
10575	cancel_delayed_work_sync(dwork: &hba->ufs_rtc_update_work);
10576	blk_mq_destroy_queue(hba->tmf_queue);
10577	blk_put_queue(hba->tmf_queue);
10578	blk_mq_free_tag_set(set: &hba->tmf_tag_set);
10579	if (hba->scsi_host_added)
10580	scsi_remove_host(hba->host);
10581	/* disable interrupts */
10582	ufshcd_disable_intr(hba, intrs: hba->intr_mask);
10583	ufshcd_hba_stop(hba);
10584	ufshcd_hba_exit(hba);
10585	}
10586	EXPORT_SYMBOL_GPL(ufshcd_remove);
10587
10588	#ifdef CONFIG_PM_SLEEP
10589	int ufshcd_system_freeze(struct device *dev)
10590	{
10591
10592	return ufshcd_system_suspend(dev);
10593
10594	}
10595	EXPORT_SYMBOL_GPL(ufshcd_system_freeze);
10596
10597	int ufshcd_system_restore(struct device *dev)
10598	{
10599
10600	struct ufs_hba *hba = dev_get_drvdata(dev);
10601	int ret;
10602
10603	ret = ufshcd_system_resume(dev);
10604	if (ret)
10605	return ret;
10606
10607	/* Configure UTRL and UTMRL base address registers */
10608	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
10609	REG_UTP_TRANSFER_REQ_LIST_BASE_L);
10610	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
10611	REG_UTP_TRANSFER_REQ_LIST_BASE_H);
10612	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
10613	REG_UTP_TASK_REQ_LIST_BASE_L);
10614	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
10615	REG_UTP_TASK_REQ_LIST_BASE_H);
10616	/*
10617	* Make sure that UTRL and UTMRL base address registers
10618	* are updated with the latest queue addresses. Only after
10619	* updating these addresses, we can queue the new commands.
10620	*/
10621	ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H);
10622
10623	return 0;
10624
10625	}
10626	EXPORT_SYMBOL_GPL(ufshcd_system_restore);
10627
10628	int ufshcd_system_thaw(struct device *dev)
10629	{
10630	return ufshcd_system_resume(dev);
10631	}
10632	EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
10633	#endif /* CONFIG_PM_SLEEP */
10634
10635	/**
10636	* ufshcd_set_dma_mask - Set dma mask based on the controller
10637	* addressing capability
10638	* @hba: per adapter instance
10639	*
10640	* Return: 0 for success, non-zero for failure.
10641	*/
10642	static int ufshcd_set_dma_mask(struct ufs_hba *hba)
10643	{
10644	if (hba->vops && hba->vops->set_dma_mask)
10645	return hba->vops->set_dma_mask(hba);
10646	if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
10647	if (!dma_set_mask_and_coherent(dev: hba->dev, DMA_BIT_MASK(64)))
10648	return 0;
10649	}
10650	return dma_set_mask_and_coherent(dev: hba->dev, DMA_BIT_MASK(32));
10651	}
10652
10653	/**
10654	* ufshcd_devres_release - devres cleanup handler, invoked during release of
10655	* hba->dev
10656	* @host: pointer to SCSI host
10657	*/
10658	static void ufshcd_devres_release(void *host)
10659	{
10660	scsi_host_put(t: host);
10661	}
10662
10663	/**
10664	* ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
10665	* @dev: pointer to device handle
10666	* @hba_handle: driver private handle
10667	*
10668	* Return: 0 on success, non-zero value on failure.
10669	*
10670	* NOTE: There is no corresponding ufshcd_dealloc_host() because this function
10671	* keeps track of its allocations using devres and deallocates everything on
10672	* device removal automatically.
10673	*/
10674	int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
10675	{
10676	struct Scsi_Host *host;
10677	struct ufs_hba *hba;
10678	int err = 0;
10679
10680	if (!dev) {
10681	dev_err(dev,
10682	"Invalid memory reference for dev is NULL\n");
10683	err = -ENODEV;
10684	goto out_error;
10685	}
10686
10687	host = scsi_host_alloc(&ufshcd_driver_template,
10688	sizeof(struct ufs_hba));
10689	if (!host) {
10690	dev_err(dev, "scsi_host_alloc failed\n");
10691	err = -ENOMEM;
10692	goto out_error;
10693	}
10694
10695	err = devm_add_action_or_reset(dev, ufshcd_devres_release,
10696	host);
10697	if (err)
10698	return err;
10699
10700	host->nr_maps = HCTX_TYPE_POLL + 1;
10701	hba = shost_priv(shost: host);
10702	hba->host = host;
10703	hba->dev = dev;
10704	hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
10705	hba->nop_out_timeout = NOP_OUT_TIMEOUT;
10706	ufshcd_set_sg_entry_size(hba, sg_entry_size: sizeof(struct ufshcd_sg_entry));
10707	INIT_LIST_HEAD(list: &hba->clk_list_head);
10708	spin_lock_init(&hba->outstanding_lock);
10709
10710	*hba_handle = hba;
10711
10712	out_error:
10713	return err;
10714	}
10715	EXPORT_SYMBOL(ufshcd_alloc_host);
10716
10717	/* This function exists because blk_mq_alloc_tag_set() requires this. */
10718	static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
10719	const struct blk_mq_queue_data *qd)
10720	{
10721	WARN_ON_ONCE(true);
10722	return BLK_STS_NOTSUPP;
10723	}
10724
10725	static const struct blk_mq_ops ufshcd_tmf_ops = {
10726	.queue_rq = ufshcd_queue_tmf,
10727	};
10728
10729	static int ufshcd_add_scsi_host(struct ufs_hba *hba)
10730	{
10731	int err;
10732
10733	WARN_ON_ONCE(!hba->host->can_queue);
10734	WARN_ON_ONCE(!hba->host->cmd_per_lun);
10735
10736	if (is_mcq_supported(hba)) {
10737	ufshcd_mcq_enable(hba);
10738	err = ufshcd_alloc_mcq(hba);
10739	if (err) {
10740	/* Continue with SDB mode */
10741	ufshcd_mcq_disable(hba);
10742	use_mcq_mode = false;
10743	dev_err(hba->dev, "MCQ mode is disabled, err=%d\n",
10744	err);
10745	}
10746	}
10747	if (!is_mcq_supported(hba) && !hba->lsdb_sup) {
10748	dev_err(hba->dev,
10749	"%s: failed to initialize (legacy doorbell mode not supported)\n",
10750	__func__);
10751	return -EINVAL;
10752	}
10753
10754	err = scsi_add_host(host: hba->host, dev: hba->dev);
10755	if (err) {
10756	dev_err(hba->dev, "scsi_add_host failed\n");
10757	return err;
10758	}
10759	hba->scsi_host_added = true;
10760
10761	hba->tmf_tag_set = (struct blk_mq_tag_set) {
10762	.nr_hw_queues = 1,
10763	.queue_depth = hba->nutmrs,
10764	.ops = &ufshcd_tmf_ops,
10765	};
10766	err = blk_mq_alloc_tag_set(set: &hba->tmf_tag_set);
10767	if (err < 0)
10768	goto remove_scsi_host;
10769	hba->tmf_queue = blk_mq_alloc_queue(set: &hba->tmf_tag_set, NULL, NULL);
10770	if (IS_ERR(ptr: hba->tmf_queue)) {
10771	err = PTR_ERR(ptr: hba->tmf_queue);
10772	goto free_tmf_tag_set;
10773	}
10774	hba->tmf_rqs = devm_kcalloc(dev: hba->dev, n: hba->nutmrs,
10775	size: sizeof(*hba->tmf_rqs), GFP_KERNEL);
10776	if (!hba->tmf_rqs) {
10777	err = -ENOMEM;
10778	goto free_tmf_queue;
10779	}
10780
10781	return 0;
10782
10783	free_tmf_queue:
10784	blk_mq_destroy_queue(hba->tmf_queue);
10785	blk_put_queue(hba->tmf_queue);
10786
10787	free_tmf_tag_set:
10788	blk_mq_free_tag_set(set: &hba->tmf_tag_set);
10789
10790	remove_scsi_host:
10791	if (hba->scsi_host_added)
10792	scsi_remove_host(hba->host);
10793
10794	return err;
10795	}
10796
10797	/**
10798	* ufshcd_init - Driver initialization routine
10799	* @hba: per-adapter instance
10800	* @mmio_base: base register address
10801	* @irq: Interrupt line of device
10802	*
10803	* Return: 0 on success; < 0 on failure.
10804	*/
10805	int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
10806	{
10807	int err;
10808	struct Scsi_Host *host = hba->host;
10809	struct device *dev = hba->dev;
10810
10811	/*
10812	* dev_set_drvdata() must be called before any callbacks are registered
10813	* that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
10814	* sysfs).
10815	*/
10816	dev_set_drvdata(dev, data: hba);
10817
10818	if (!mmio_base) {
10819	dev_err(hba->dev,
10820	"Invalid memory reference for mmio_base is NULL\n");
10821	err = -ENODEV;
10822	goto out_error;
10823	}
10824
10825	hba->mmio_base = mmio_base;
10826	hba->irq = irq;
10827	hba->vps = &ufs_hba_vps;
10828
10829	/*
10830	* Initialize clk_gating.lock early since it is being used in
10831	* ufshcd_setup_clocks()
10832	*/
10833	spin_lock_init(&hba->clk_gating.lock);
10834
10835	/* Initialize mutex for PM QoS request synchronization */
10836	mutex_init(&hba->pm_qos_mutex);
10837
10838	/*
10839	* Set the default power management level for runtime and system PM.
10840	* Host controller drivers can override them in their
10841	* 'ufs_hba_variant_ops::init' callback.
10842	*
10843	* Default power saving mode is to keep UFS link in Hibern8 state
10844	* and UFS device in sleep state.
10845	*/
10846	hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10847	dev_state: UFS_SLEEP_PWR_MODE,
10848	link_state: UIC_LINK_HIBERN8_STATE);
10849	hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10850	dev_state: UFS_SLEEP_PWR_MODE,
10851	link_state: UIC_LINK_HIBERN8_STATE);
10852
10853	/*
10854	* Most ufs devices require 1ms delay after vcc is powered off before
10855	* it can be powered on again. Set the default to 2ms. The platform
10856	* drivers can override this setting as needed.
10857	*/
10858	hba->vcc_off_delay_us = 2000;
10859
10860	err = ufshcd_hba_init(hba);
10861	if (err)
10862	goto out_error;
10863
10864	/* Read capabilities registers */
10865	err = ufshcd_hba_capabilities(hba);
10866	if (err)
10867	goto out_disable;
10868
10869	/* Get UFS version supported by the controller */
10870	hba->ufs_version = ufshcd_get_ufs_version(hba);
10871
10872	/* Get Interrupt bit mask per version */
10873	hba->intr_mask = ufshcd_get_intr_mask(hba);
10874
10875	err = ufshcd_set_dma_mask(hba);
10876	if (err) {
10877	dev_err(hba->dev, "set dma mask failed\n");
10878	goto out_disable;
10879	}
10880
10881	/* Allocate memory for host memory space */
10882	err = ufshcd_memory_alloc(hba);
10883	if (err) {
10884	dev_err(hba->dev, "Memory allocation failed\n");
10885	goto out_disable;
10886	}
10887
10888	/* Configure LRB */
10889	ufshcd_host_memory_configure(hba);
10890
10891	host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
10892	/*
10893	* Set the queue depth for WLUNs. ufs_get_device_desc() will increase
10894	* host->cmd_per_lun to a larger value.
10895	*/
10896	host->cmd_per_lun = 1;
10897	host->max_id = UFSHCD_MAX_ID;
10898	host->max_lun = UFS_MAX_LUNS;
10899	host->max_channel = UFSHCD_MAX_CHANNEL;
10900	host->unique_id = host->host_no;
10901	host->max_cmd_len = UFS_CDB_SIZE;
10902	host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING);
10903
10904	/* Use default RPM delay if host not set */
10905	if (host->rpm_autosuspend_delay == 0)
10906	host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS;
10907
10908	hba->max_pwr_info.is_valid = false;
10909
10910	/* Initialize work queues */
10911	hba->eh_wq = alloc_ordered_workqueue("ufs_eh_wq_%d", WQ_MEM_RECLAIM,
10912	hba->host->host_no);
10913	if (!hba->eh_wq) {
10914	dev_err(hba->dev, "%s: failed to create eh workqueue\n",
10915	__func__);
10916	err = -ENOMEM;
10917	goto out_disable;
10918	}
10919	INIT_WORK(&hba->eh_work, ufshcd_err_handler);
10920	INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
10921
10922	sema_init(sem: &hba->host_sem, val: 1);
10923
10924	/* Initialize UIC command mutex */
10925	mutex_init(&hba->uic_cmd_mutex);
10926
10927	/* Initialize mutex for device management commands */
10928	mutex_init(&hba->dev_cmd.lock);
10929
10930	/* Initialize mutex for exception event control */
10931	mutex_init(&hba->ee_ctrl_mutex);
10932
10933	mutex_init(&hba->wb_mutex);
10934
10935	init_rwsem(&hba->clk_scaling_lock);
10936
10937	ufshcd_init_clk_gating(hba);
10938
10939	ufshcd_init_clk_scaling(hba);
10940
10941	/*
10942	* In order to avoid any spurious interrupt immediately after
10943	* registering UFS controller interrupt handler, clear any pending UFS
10944	* interrupt status and disable all the UFS interrupts.
10945	*/
10946	ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
10947	REG_INTERRUPT_STATUS);
10948	ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
10949	/*
10950	* Make sure that UFS interrupts are disabled and any pending interrupt
10951	* status is cleared before registering UFS interrupt handler.
10952	*/
10953	ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
10954
10955	/* IRQ registration */
10956	err = devm_request_threaded_irq(dev, irq, handler: ufshcd_intr, thread_fn: ufshcd_threaded_intr,
10957	IRQF_ONESHOT | IRQF_SHARED, UFSHCD, dev_id: hba);
10958	if (err) {
10959	dev_err(hba->dev, "request irq failed\n");
10960	goto out_disable;
10961	} else {
10962	hba->is_irq_enabled = true;
10963	}
10964
10965	/* Reset the attached device */
10966	ufshcd_device_reset(hba);
10967
10968	ufshcd_init_crypto(hba);
10969
10970	/* Host controller enable */
10971	err = ufshcd_hba_enable(hba);
10972	if (err) {
10973	dev_err(hba->dev, "Host controller enable failed\n");
10974	ufshcd_print_evt_hist(hba);
10975	ufshcd_print_host_state(hba);
10976	goto out_disable;
10977	}
10978
10979	INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work);
10980	INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work);
10981
10982	/* Set the default auto-hiberate idle timer value to 150 ms */
10983	if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
10984	hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10985	FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10986	}
10987
10988	err = ufshcd_add_scsi_host(hba);
10989	if (err)
10990	goto out_disable;
10991
10992	/* Hold auto suspend until async scan completes */
10993	pm_runtime_get_sync(dev);
10994
10995	/*
10996	* We are assuming that device wasn't put in sleep/power-down
10997	* state exclusively during the boot stage before kernel.
10998	* This assumption helps avoid doing link startup twice during
10999	* ufshcd_probe_hba().
11000	*/
11001	ufshcd_set_ufs_dev_active(hba);
11002
11003	/* Initialize hba, detect and initialize UFS device */
11004	ktime_t probe_start = ktime_get();
11005
11006	hba->ufshcd_state = UFSHCD_STATE_RESET;
11007
11008	err = ufshcd_link_startup(hba);
11009	if (err)
11010	goto out_disable;
11011
11012	if (hba->mcq_enabled)
11013	ufshcd_config_mcq(hba);
11014
11015	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
11016	goto initialized;
11017
11018	/* Debug counters initialization */
11019	ufshcd_clear_dbg_ufs_stats(hba);
11020
11021	/* UniPro link is active now */
11022	ufshcd_set_link_active(hba);
11023
11024	/* Verify device initialization by sending NOP OUT UPIU */
11025	err = ufshcd_verify_dev_init(hba);
11026	if (err)
11027	goto out_disable;
11028
11029	/* Initiate UFS initialization, and waiting until completion */
11030	err = ufshcd_complete_dev_init(hba);
11031	if (err)
11032	goto out_disable;
11033
11034	err = ufshcd_device_params_init(hba);
11035	if (err)
11036	goto out_disable;
11037
11038	err = ufshcd_post_device_init(hba);
11039
11040	initialized:
11041	ufshcd_process_probe_result(hba, probe_start, ret: err);
11042	if (err)
11043	goto out_disable;
11044
11045	ufs_sysfs_add_nodes(dev: hba->dev);
11046	async_schedule(func: ufshcd_async_scan, data: hba);
11047
11048	device_enable_async_suspend(dev);
11049	ufshcd_pm_qos_init(hba);
11050	return 0;
11051
11052	out_disable:
11053	hba->is_irq_enabled = false;
11054	ufshcd_hba_exit(hba);
11055	out_error:
11056	return err > 0 ? -EIO : err;
11057	}
11058	EXPORT_SYMBOL_GPL(ufshcd_init);
11059
11060	void ufshcd_resume_complete(struct device *dev)
11061	{
11062	struct ufs_hba *hba = dev_get_drvdata(dev);
11063
11064	if (hba->complete_put) {
11065	ufshcd_rpm_put(hba);
11066	hba->complete_put = false;
11067	}
11068	}
11069	EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
11070
11071	static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
11072	{
11073	struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
11074	enum ufs_dev_pwr_mode dev_pwr_mode;
11075	enum uic_link_state link_state;
11076	unsigned long flags;
11077	bool res;
11078
11079	spin_lock_irqsave(&dev->power.lock, flags);
11080	dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(lvl: hba->spm_lvl);
11081	link_state = ufs_get_pm_lvl_to_link_pwr_state(lvl: hba->spm_lvl);
11082	res = pm_runtime_suspended(dev) &&
11083	hba->curr_dev_pwr_mode == dev_pwr_mode &&
11084	hba->uic_link_state == link_state &&
11085	!hba->dev_info.b_rpm_dev_flush_capable;
11086	spin_unlock_irqrestore(lock: &dev->power.lock, flags);
11087
11088	return res;
11089	}
11090
11091	int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
11092	{
11093	struct ufs_hba *hba = dev_get_drvdata(dev);
11094	int ret;
11095
11096	/*
11097	* SCSI assumes that runtime-pm and system-pm for scsi drivers
11098	* are same. And it doesn't wake up the device for system-suspend
11099	* if it's runtime suspended. But ufs doesn't follow that.
11100	* Refer ufshcd_resume_complete()
11101	*/
11102	if (hba->ufs_device_wlun) {
11103	/* Prevent runtime suspend */
11104	ufshcd_rpm_get_noresume(hba);
11105	/*
11106	* Check if already runtime suspended in same state as system
11107	* suspend would be.
11108	*/
11109	if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
11110	/* RPM state is not ok for SPM, so runtime resume */
11111	ret = ufshcd_rpm_resume(hba);
11112	if (ret < 0 && ret != -EACCES) {
11113	ufshcd_rpm_put(hba);
11114	return ret;
11115	}
11116	}
11117	hba->complete_put = true;
11118	}
11119	return 0;
11120	}
11121	EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
11122
11123	int ufshcd_suspend_prepare(struct device *dev)
11124	{
11125	return __ufshcd_suspend_prepare(dev, true);
11126	}
11127	EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
11128
11129	#ifdef CONFIG_PM_SLEEP
11130	static int ufshcd_wl_poweroff(struct device *dev)
11131	{
11132	struct scsi_device *sdev = to_scsi_device(dev);
11133	struct ufs_hba *hba = shost_priv(shost: sdev->host);
11134
11135	__ufshcd_wl_suspend(hba, pm_op: UFS_SHUTDOWN_PM);
11136	return 0;
11137	}
11138	#endif
11139
11140	static int ufshcd_wl_probe(struct device *dev)
11141	{
11142	struct scsi_device *sdev = to_scsi_device(dev);
11143
11144	if (!is_device_wlun(sdev))
11145	return -ENODEV;
11146
11147	blk_pm_runtime_init(q: sdev->request_queue, dev);
11148	pm_runtime_set_autosuspend_delay(dev, delay: 0);
11149	pm_runtime_allow(dev);
11150
11151	return 0;
11152	}
11153
11154	static int ufshcd_wl_remove(struct device *dev)
11155	{
11156	pm_runtime_forbid(dev);
11157	return 0;
11158	}
11159
11160	static const struct dev_pm_ops ufshcd_wl_pm_ops = {
11161	#ifdef CONFIG_PM_SLEEP
11162	.suspend = ufshcd_wl_suspend,
11163	.resume = ufshcd_wl_resume,
11164	.freeze = ufshcd_wl_suspend,
11165	.thaw = ufshcd_wl_resume,
11166	.poweroff = ufshcd_wl_poweroff,
11167	.restore = ufshcd_wl_resume,
11168	#endif
11169	SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
11170	};
11171
11172	static void ufshcd_check_header_layout(void)
11173	{
11174	/*
11175	* gcc compilers before version 10 cannot do constant-folding for
11176	* sub-byte bitfields. Hence skip the layout checks for gcc 9 and
11177	* before.
11178	*/
11179	if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000)
11180	return;
11181
11182	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
11183	.cci = 3})[0] != 3);
11184
11185	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
11186	.ehs_length = 2})[1] != 2);
11187
11188	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
11189	.enable_crypto = 1})[2]
11190	!= 0x80);
11191
11192	BUILD_BUG_ON((((u8 *)&(struct request_desc_header){
11193	.command_type = 5,
11194	.data_direction = 3,
11195	.interrupt = 1,
11196	})[3]) != ((5 << 4) | (3 << 1) | 1));
11197
11198	BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
11199	.dunl = cpu_to_le32(0xdeadbeef)})[1] !=
11200	cpu_to_le32(0xdeadbeef));
11201
11202	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
11203	.ocs = 4})[8] != 4);
11204
11205	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
11206	.cds = 5})[9] != 5);
11207
11208	BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
11209	.dunu = cpu_to_le32(0xbadcafe)})[3] !=
11210	cpu_to_le32(0xbadcafe));
11211
11212	BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
11213	.iid = 0xf })[4] != 0xf0);
11214
11215	BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
11216	.command_set_type = 0xf })[4] != 0xf);
11217	}
11218
11219	/*
11220	* ufs_dev_wlun_template - describes ufs device wlun
11221	* ufs-device wlun - used to send pm commands
11222	* All luns are consumers of ufs-device wlun.
11223	*
11224	* Currently, no sd driver is present for wluns.
11225	* Hence the no specific pm operations are performed.
11226	* With ufs design, SSU should be sent to ufs-device wlun.
11227	* Hence register a scsi driver for ufs wluns only.
11228	*/
11229	static struct scsi_driver ufs_dev_wlun_template = {
11230	.gendrv = {
11231	.name = "ufs_device_wlun",
11232	.probe = ufshcd_wl_probe,
11233	.remove = ufshcd_wl_remove,
11234	.pm = &ufshcd_wl_pm_ops,
11235	.shutdown = ufshcd_wl_shutdown,
11236	},
11237	};
11238
11239	static int __init ufshcd_core_init(void)
11240	{
11241	int ret;
11242
11243	ufshcd_check_header_layout();
11244
11245	ufs_debugfs_init();
11246
11247	ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
11248	if (ret)
11249	ufs_debugfs_exit();
11250	return ret;
11251	}
11252
11253	static void __exit ufshcd_core_exit(void)
11254	{
11255	ufs_debugfs_exit();
11256	scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
11257	}
11258
11259	module_init(ufshcd_core_init);
11260	module_exit(ufshcd_core_exit);
11261
11262	MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
11263	MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
11264	MODULE_DESCRIPTION("Generic UFS host controller driver Core");
11265	MODULE_SOFTDEP("pre: governor_simpleondemand");
11266	MODULE_LICENSE("GPL");
11267