1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* xHCI host controller driver
4	*
5	* Copyright (C) 2008 Intel Corp.
6	*
7	* Author: Sarah Sharp
8	* Some code borrowed from the Linux EHCI driver.
9	*/
10
11	#include <linux/usb.h>
12	#include <linux/overflow.h>
13	#include <linux/pci.h>
14	#include <linux/slab.h>
15	#include <linux/dmapool.h>
16	#include <linux/dma-mapping.h>
17
18	#include "xhci.h"
19	#include "xhci-trace.h"
20	#include "xhci-debugfs.h"
21
22	/*
23	* Allocates a generic ring segment from the ring pool, sets the dma address,
24	* initializes the segment to zero, and sets the private next pointer to NULL.
25	*
26	* Section 4.11.1.1:
27	* "All components of all Command and Transfer TRBs shall be initialized to '0'"
28	*/
29	static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
30	unsigned int max_packet,
31	unsigned int num,
32	gfp_t flags)
33	{
34	struct xhci_segment *seg;
35	dma_addr_t dma;
36	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
37
38	seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
39	if (!seg)
40	return NULL;
41
42	seg->trbs = dma_pool_zalloc(pool: xhci->segment_pool, mem_flags: flags, handle: &dma);
43	if (!seg->trbs) {
44	kfree(objp: seg);
45	return NULL;
46	}
47
48	if (max_packet) {
49	seg->bounce_buf = kzalloc_node(max_packet, flags,
50	dev_to_node(dev));
51	if (!seg->bounce_buf) {
52	dma_pool_free(pool: xhci->segment_pool, vaddr: seg->trbs, addr: dma);
53	kfree(objp: seg);
54	return NULL;
55	}
56	}
57	seg->num = num;
58	seg->dma = dma;
59	seg->next = NULL;
60
61	return seg;
62	}
63
64	static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
65	{
66	if (seg->trbs) {
67	dma_pool_free(pool: xhci->segment_pool, vaddr: seg->trbs, addr: seg->dma);
68	seg->trbs = NULL;
69	}
70	kfree(objp: seg->bounce_buf);
71	kfree(objp: seg);
72	}
73
74	static void xhci_ring_segments_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
75	{
76	struct xhci_segment *seg, *next;
77
78	ring->last_seg->next = NULL;
79	seg = ring->first_seg;
80
81	while (seg) {
82	next = seg->next;
83	xhci_segment_free(xhci, seg);
84	seg = next;
85	}
86	}
87
88	/*
89	* Only for transfer and command rings where driver is the producer, not for
90	* event rings.
91	*
92	* Change the last TRB in the segment to be a Link TRB which points to the
93	* DMA address of the next segment. The caller needs to set any Link TRB
94	* related flags, such as End TRB, Toggle Cycle, and no snoop.
95	*/
96	static void xhci_set_link_trb(struct xhci_segment *seg, bool chain_links)
97	{
98	union xhci_trb *trb;
99	u32 val;
100
101	if (!seg || !seg->next)
102	return;
103
104	trb = &seg->trbs[TRBS_PER_SEGMENT - 1];
105
106	/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
107	val = le32_to_cpu(trb->link.control);
108	val &= ~TRB_TYPE_BITMASK;
109	val |= TRB_TYPE(TRB_LINK);
110	if (chain_links)
111	val |= TRB_CHAIN;
112	trb->link.control = cpu_to_le32(val);
113	trb->link.segment_ptr = cpu_to_le64(seg->next->dma);
114	}
115
116	static void xhci_initialize_ring_segments(struct xhci_hcd *xhci, struct xhci_ring *ring)
117	{
118	struct xhci_segment *seg;
119	bool chain_links;
120
121	if (ring->type == TYPE_EVENT)
122	return;
123
124	chain_links = xhci_link_chain_quirk(xhci, type: ring->type);
125	xhci_for_each_ring_seg(ring->first_seg, seg)
126	xhci_set_link_trb(seg, chain_links);
127
128	/* See section 4.9.2.1 and 6.4.4.1 */
129	ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= cpu_to_le32(LINK_TOGGLE);
130	}
131
132	/*
133	* Link the src ring segments to the dst ring.
134	* Set Toggle Cycle for the new ring if needed.
135	*/
136	static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *src, struct xhci_ring *dst)
137	{
138	struct xhci_segment *seg;
139	bool chain_links;
140
141	if (!src || !dst)
142	return;
143
144	/* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
145	if (dst->cycle_state == 0) {
146	xhci_for_each_ring_seg(src->first_seg, seg) {
147	for (int i = 0; i < TRBS_PER_SEGMENT; i++)
148	seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
149	}
150	}
151
152	src->last_seg->next = dst->enq_seg->next;
153	dst->enq_seg->next = src->first_seg;
154	if (dst->type != TYPE_EVENT) {
155	chain_links = xhci_link_chain_quirk(xhci, type: dst->type);
156	xhci_set_link_trb(seg: dst->enq_seg, chain_links);
157	xhci_set_link_trb(seg: src->last_seg, chain_links);
158	}
159	dst->num_segs += src->num_segs;
160
161	if (dst->enq_seg == dst->last_seg) {
162	if (dst->type != TYPE_EVENT)
163	dst->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
164	&= ~cpu_to_le32(LINK_TOGGLE);
165
166	dst->last_seg = src->last_seg;
167	} else if (dst->type != TYPE_EVENT) {
168	src->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control &= ~cpu_to_le32(LINK_TOGGLE);
169	}
170
171	for (seg = dst->enq_seg; seg != dst->last_seg; seg = seg->next)
172	seg->next->num = seg->num + 1;
173	}
174
175	/*
176	* We need a radix tree for mapping physical addresses of TRBs to which stream
177	* ID they belong to. We need to do this because the host controller won't tell
178	* us which stream ring the TRB came from. We could store the stream ID in an
179	* event data TRB, but that doesn't help us for the cancellation case, since the
180	* endpoint may stop before it reaches that event data TRB.
181	*
182	* The radix tree maps the upper portion of the TRB DMA address to a ring
183	* segment that has the same upper portion of DMA addresses. For example, say I
184	* have segments of size 1KB, that are always 1KB aligned. A segment may
185	* start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
186	* key to the stream ID is 0x43244. I can use the DMA address of the TRB to
187	* pass the radix tree a key to get the right stream ID:
188	*
189	* 0x10c90fff >> 10 = 0x43243
190	* 0x10c912c0 >> 10 = 0x43244
191	* 0x10c91400 >> 10 = 0x43245
192	*
193	* Obviously, only those TRBs with DMA addresses that are within the segment
194	* will make the radix tree return the stream ID for that ring.
195	*
196	* Caveats for the radix tree:
197	*
198	* The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
199	* unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
200	* 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
201	* key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
202	* PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
203	* extended systems (where the DMA address can be bigger than 32-bits),
204	* if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
205	*/
206	static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
207	struct xhci_ring *ring,
208	struct xhci_segment *seg,
209	gfp_t mem_flags)
210	{
211	unsigned long key;
212	int ret;
213
214	key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
215	/* Skip any segments that were already added. */
216	if (radix_tree_lookup(trb_address_map, key))
217	return 0;
218
219	ret = radix_tree_maybe_preload(gfp_mask: mem_flags);
220	if (ret)
221	return ret;
222	ret = radix_tree_insert(trb_address_map,
223	index: key, ring);
224	radix_tree_preload_end();
225	return ret;
226	}
227
228	static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
229	struct xhci_segment *seg)
230	{
231	unsigned long key;
232
233	key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
234	if (radix_tree_lookup(trb_address_map, key))
235	radix_tree_delete(trb_address_map, key);
236	}
237
238	static int xhci_update_stream_segment_mapping(
239	struct radix_tree_root *trb_address_map,
240	struct xhci_ring *ring,
241	struct xhci_segment *first_seg,
242	gfp_t mem_flags)
243	{
244	struct xhci_segment *seg;
245	struct xhci_segment *failed_seg;
246	int ret;
247
248	if (WARN_ON_ONCE(trb_address_map == NULL))
249	return 0;
250
251	xhci_for_each_ring_seg(first_seg, seg) {
252	ret = xhci_insert_segment_mapping(trb_address_map,
253	ring, seg, mem_flags);
254	if (ret)
255	goto remove_streams;
256	}
257
258	return 0;
259
260	remove_streams:
261	failed_seg = seg;
262	xhci_for_each_ring_seg(first_seg, seg) {
263	xhci_remove_segment_mapping(trb_address_map, seg);
264	if (seg == failed_seg)
265	return ret;
266	}
267
268	return ret;
269	}
270
271	static void xhci_remove_stream_mapping(struct xhci_ring *ring)
272	{
273	struct xhci_segment *seg;
274
275	if (WARN_ON_ONCE(ring->trb_address_map == NULL))
276	return;
277
278	xhci_for_each_ring_seg(ring->first_seg, seg)
279	xhci_remove_segment_mapping(trb_address_map: ring->trb_address_map, seg);
280	}
281
282	static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
283	{
284	return xhci_update_stream_segment_mapping(trb_address_map: ring->trb_address_map, ring,
285	first_seg: ring->first_seg, mem_flags);
286	}
287
288	/* XXX: Do we need the hcd structure in all these functions? */
289	void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
290	{
291	if (!ring)
292	return;
293
294	trace_xhci_ring_free(ring);
295
296	if (ring->first_seg) {
297	if (ring->type == TYPE_STREAM)
298	xhci_remove_stream_mapping(ring);
299	xhci_ring_segments_free(xhci, ring);
300	}
301
302	kfree(objp: ring);
303	}
304
305	void xhci_initialize_ring_info(struct xhci_ring *ring)
306	{
307	/* The ring is empty, so the enqueue pointer == dequeue pointer */
308	ring->enqueue = ring->first_seg->trbs;
309	ring->enq_seg = ring->first_seg;
310	ring->dequeue = ring->enqueue;
311	ring->deq_seg = ring->first_seg;
312	/* The ring is initialized to 0. The producer must write 1 to the cycle
313	* bit to handover ownership of the TRB, so PCS = 1. The consumer must
314	* compare CCS to the cycle bit to check ownership, so CCS = 1.
315	*
316	* New rings are initialized with cycle state equal to 1; if we are
317	* handling ring expansion, set the cycle state equal to the old ring.
318	*/
319	ring->cycle_state = 1;
320
321	/*
322	* Each segment has a link TRB, and leave an extra TRB for SW
323	* accounting purpose
324	*/
325	ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
326	}
327	EXPORT_SYMBOL_GPL(xhci_initialize_ring_info);
328
329	/* Allocate segments and link them for a ring */
330	static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, gfp_t flags)
331	{
332	struct xhci_segment *prev;
333	unsigned int num = 0;
334
335	prev = xhci_segment_alloc(xhci, max_packet: ring->bounce_buf_len, num, flags);
336	if (!prev)
337	return -ENOMEM;
338	num++;
339
340	ring->first_seg = prev;
341	while (num < ring->num_segs) {
342	struct xhci_segment *next;
343
344	next = xhci_segment_alloc(xhci, max_packet: ring->bounce_buf_len, num, flags);
345	if (!next)
346	goto free_segments;
347
348	prev->next = next;
349	prev = next;
350	num++;
351	}
352	ring->last_seg = prev;
353
354	ring->last_seg->next = ring->first_seg;
355	return 0;
356
357	free_segments:
358	ring->last_seg = prev;
359	xhci_ring_segments_free(xhci, ring);
360	return -ENOMEM;
361	}
362
363	/*
364	* Create a new ring with zero or more segments.
365	*
366	* Link each segment together into a ring.
367	* Set the end flag and the cycle toggle bit on the last segment.
368	* See section 4.9.1 and figures 15 and 16.
369	*/
370	struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs,
371	enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
372	{
373	struct xhci_ring *ring;
374	int ret;
375	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
376
377	ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
378	if (!ring)
379	return NULL;
380
381	ring->num_segs = num_segs;
382	ring->bounce_buf_len = max_packet;
383	INIT_LIST_HEAD(list: &ring->td_list);
384	ring->type = type;
385	if (num_segs == 0)
386	return ring;
387
388	ret = xhci_alloc_segments_for_ring(xhci, ring, flags);
389	if (ret)
390	goto fail;
391
392	xhci_initialize_ring_segments(xhci, ring);
393	xhci_initialize_ring_info(ring);
394	trace_xhci_ring_alloc(ring);
395	return ring;
396
397	fail:
398	kfree(objp: ring);
399	return NULL;
400	}
401
402	void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
403	struct xhci_virt_device *virt_dev,
404	unsigned int ep_index)
405	{
406	xhci_ring_free(xhci, ring: virt_dev->eps[ep_index].ring);
407	virt_dev->eps[ep_index].ring = NULL;
408	}
409
410	/*
411	* Expand an existing ring.
412	* Allocate a new ring which has same segment numbers and link the two rings.
413	*/
414	int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
415	unsigned int num_new_segs, gfp_t flags)
416	{
417	struct xhci_ring new_ring;
418	int ret;
419
420	if (num_new_segs == 0)
421	return 0;
422
423	new_ring.num_segs = num_new_segs;
424	new_ring.bounce_buf_len = ring->bounce_buf_len;
425	new_ring.type = ring->type;
426	ret = xhci_alloc_segments_for_ring(xhci, ring: &new_ring, flags);
427	if (ret)
428	return -ENOMEM;
429
430	xhci_initialize_ring_segments(xhci, ring: &new_ring);
431
432	if (ring->type == TYPE_STREAM) {
433	ret = xhci_update_stream_segment_mapping(trb_address_map: ring->trb_address_map, ring,
434	first_seg: new_ring.first_seg, mem_flags: flags);
435	if (ret)
436	goto free_segments;
437	}
438
439	xhci_link_rings(xhci, src: &new_ring, dst: ring);
440	trace_xhci_ring_expansion(ring);
441	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_ring_expansion,
442	fmt: "ring expansion succeed, now has %d segments",
443	ring->num_segs);
444
445	return 0;
446
447	free_segments:
448	xhci_ring_segments_free(xhci, ring: &new_ring);
449	return ret;
450	}
451
452	struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
453	int type, gfp_t flags)
454	{
455	struct xhci_container_ctx *ctx;
456	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
457
458	if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
459	return NULL;
460
461	ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
462	if (!ctx)
463	return NULL;
464
465	ctx->type = type;
466	ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
467	if (type == XHCI_CTX_TYPE_INPUT)
468	ctx->size += CTX_SIZE(xhci->hcc_params);
469
470	ctx->bytes = dma_pool_zalloc(pool: xhci->device_pool, mem_flags: flags, handle: &ctx->dma);
471	if (!ctx->bytes) {
472	kfree(objp: ctx);
473	return NULL;
474	}
475	return ctx;
476	}
477
478	void xhci_free_container_ctx(struct xhci_hcd *xhci,
479	struct xhci_container_ctx *ctx)
480	{
481	if (!ctx)
482	return;
483	dma_pool_free(pool: xhci->device_pool, vaddr: ctx->bytes, addr: ctx->dma);
484	kfree(objp: ctx);
485	}
486
487	struct xhci_container_ctx *xhci_alloc_port_bw_ctx(struct xhci_hcd *xhci,
488	gfp_t flags)
489	{
490	struct xhci_container_ctx *ctx;
491	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
492
493	ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
494	if (!ctx)
495	return NULL;
496
497	ctx->size = GET_PORT_BW_ARRAY_SIZE;
498
499	ctx->bytes = dma_pool_zalloc(pool: xhci->port_bw_pool, mem_flags: flags, handle: &ctx->dma);
500	if (!ctx->bytes) {
501	kfree(objp: ctx);
502	return NULL;
503	}
504	return ctx;
505	}
506
507	void xhci_free_port_bw_ctx(struct xhci_hcd *xhci,
508	struct xhci_container_ctx *ctx)
509	{
510	if (!ctx)
511	return;
512	dma_pool_free(pool: xhci->port_bw_pool, vaddr: ctx->bytes, addr: ctx->dma);
513	kfree(objp: ctx);
514	}
515
516	struct xhci_input_control_ctx *xhci_get_input_control_ctx(
517	struct xhci_container_ctx *ctx)
518	{
519	if (ctx->type != XHCI_CTX_TYPE_INPUT)
520	return NULL;
521
522	return (struct xhci_input_control_ctx *)ctx->bytes;
523	}
524
525	struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
526	struct xhci_container_ctx *ctx)
527	{
528	if (ctx->type == XHCI_CTX_TYPE_DEVICE)
529	return (struct xhci_slot_ctx *)ctx->bytes;
530
531	return (struct xhci_slot_ctx *)
532	(ctx->bytes + CTX_SIZE(xhci->hcc_params));
533	}
534
535	struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
536	struct xhci_container_ctx *ctx,
537	unsigned int ep_index)
538	{
539	/* increment ep index by offset of start of ep ctx array */
540	ep_index++;
541	if (ctx->type == XHCI_CTX_TYPE_INPUT)
542	ep_index++;
543
544	return (struct xhci_ep_ctx *)
545	(ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
546	}
547	EXPORT_SYMBOL_GPL(xhci_get_ep_ctx);
548
549	/***************** Streams structures manipulation *************************/
550
551	static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
552	unsigned int num_stream_ctxs,
553	struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
554	{
555	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
556	size_t size = array_size(sizeof(struct xhci_stream_ctx), num_stream_ctxs);
557
558	if (size > MEDIUM_STREAM_ARRAY_SIZE)
559	dma_free_coherent(dev, size, cpu_addr: stream_ctx, dma_handle: dma);
560	else if (size > SMALL_STREAM_ARRAY_SIZE)
561	dma_pool_free(pool: xhci->medium_streams_pool, vaddr: stream_ctx, addr: dma);
562	else
563	dma_pool_free(pool: xhci->small_streams_pool, vaddr: stream_ctx, addr: dma);
564	}
565
566	/*
567	* The stream context array for each endpoint with bulk streams enabled can
568	* vary in size, based on:
569	* - how many streams the endpoint supports,
570	* - the maximum primary stream array size the host controller supports,
571	* - and how many streams the device driver asks for.
572	*
573	* The stream context array must be a power of 2, and can be as small as
574	* 64 bytes or as large as 1MB.
575	*/
576	static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
577	unsigned int num_stream_ctxs, dma_addr_t *dma,
578	gfp_t mem_flags)
579	{
580	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
581	size_t size = array_size(sizeof(struct xhci_stream_ctx), num_stream_ctxs);
582
583	if (size > MEDIUM_STREAM_ARRAY_SIZE)
584	return dma_alloc_coherent(dev, size, dma_handle: dma, gfp: mem_flags);
585	if (size > SMALL_STREAM_ARRAY_SIZE)
586	return dma_pool_zalloc(pool: xhci->medium_streams_pool, mem_flags, handle: dma);
587	else
588	return dma_pool_zalloc(pool: xhci->small_streams_pool, mem_flags, handle: dma);
589	}
590
591	struct xhci_ring *xhci_dma_to_transfer_ring(
592	struct xhci_virt_ep *ep,
593	u64 address)
594	{
595	if (ep->ep_state & EP_HAS_STREAMS)
596	return radix_tree_lookup(&ep->stream_info->trb_address_map,
597	address >> TRB_SEGMENT_SHIFT);
598	return ep->ring;
599	}
600
601	/*
602	* Change an endpoint's internal structure so it supports stream IDs. The
603	* number of requested streams includes stream 0, which cannot be used by device
604	* drivers.
605	*
606	* The number of stream contexts in the stream context array may be bigger than
607	* the number of streams the driver wants to use. This is because the number of
608	* stream context array entries must be a power of two.
609	*/
610	struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
611	unsigned int num_stream_ctxs,
612	unsigned int num_streams,
613	unsigned int max_packet, gfp_t mem_flags)
614	{
615	struct xhci_stream_info *stream_info;
616	u32 cur_stream;
617	struct xhci_ring *cur_ring;
618	u64 addr;
619	int ret;
620	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
621
622	xhci_dbg(xhci, "Allocating %u streams and %u stream context array entries.\n",
623	num_streams, num_stream_ctxs);
624	if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
625	xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
626	return NULL;
627	}
628	xhci->cmd_ring_reserved_trbs++;
629
630	stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
631	dev_to_node(dev));
632	if (!stream_info)
633	goto cleanup_trbs;
634
635	stream_info->num_streams = num_streams;
636	stream_info->num_stream_ctxs = num_stream_ctxs;
637
638	/* Initialize the array of virtual pointers to stream rings. */
639	stream_info->stream_rings = kcalloc_node(
640	num_streams, sizeof(struct xhci_ring *), mem_flags,
641	dev_to_node(dev));
642	if (!stream_info->stream_rings)
643	goto cleanup_info;
644
645	/* Initialize the array of DMA addresses for stream rings for the HW. */
646	stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
647	num_stream_ctxs, dma: &stream_info->ctx_array_dma,
648	mem_flags);
649	if (!stream_info->stream_ctx_array)
650	goto cleanup_ring_array;
651
652	/* Allocate everything needed to free the stream rings later */
653	stream_info->free_streams_command =
654	xhci_alloc_command_with_ctx(xhci, allocate_completion: true, mem_flags);
655	if (!stream_info->free_streams_command)
656	goto cleanup_ctx;
657
658	INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
659
660	/* Allocate rings for all the streams that the driver will use,
661	* and add their segment DMA addresses to the radix tree.
662	* Stream 0 is reserved.
663	*/
664
665	for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
666	stream_info->stream_rings[cur_stream] =
667	xhci_ring_alloc(xhci, num_segs: 2, type: TYPE_STREAM, max_packet, flags: mem_flags);
668	cur_ring = stream_info->stream_rings[cur_stream];
669	if (!cur_ring)
670	goto cleanup_rings;
671	cur_ring->stream_id = cur_stream;
672	cur_ring->trb_address_map = &stream_info->trb_address_map;
673	/* Set deq ptr, cycle bit, and stream context type */
674	addr = cur_ring->first_seg->dma |
675	SCT_FOR_CTX(SCT_PRI_TR) |
676	cur_ring->cycle_state;
677	stream_info->stream_ctx_array[cur_stream].stream_ring =
678	cpu_to_le64(addr);
679	xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", cur_stream, addr);
680
681	ret = xhci_update_stream_mapping(ring: cur_ring, mem_flags);
682
683	trace_xhci_alloc_stream_info_ctx(info: stream_info, stream_id: cur_stream);
684	if (ret) {
685	xhci_ring_free(xhci, ring: cur_ring);
686	stream_info->stream_rings[cur_stream] = NULL;
687	goto cleanup_rings;
688	}
689	}
690	/* Leave the other unused stream ring pointers in the stream context
691	* array initialized to zero. This will cause the xHC to give us an
692	* error if the device asks for a stream ID we don't have setup (if it
693	* was any other way, the host controller would assume the ring is
694	* "empty" and wait forever for data to be queued to that stream ID).
695	*/
696
697	return stream_info;
698
699	cleanup_rings:
700	for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
701	cur_ring = stream_info->stream_rings[cur_stream];
702	if (cur_ring) {
703	xhci_ring_free(xhci, ring: cur_ring);
704	stream_info->stream_rings[cur_stream] = NULL;
705	}
706	}
707	xhci_free_command(xhci, command: stream_info->free_streams_command);
708	cleanup_ctx:
709	xhci_free_stream_ctx(xhci,
710	num_stream_ctxs: stream_info->num_stream_ctxs,
711	stream_ctx: stream_info->stream_ctx_array,
712	dma: stream_info->ctx_array_dma);
713	cleanup_ring_array:
714	kfree(objp: stream_info->stream_rings);
715	cleanup_info:
716	kfree(objp: stream_info);
717	cleanup_trbs:
718	xhci->cmd_ring_reserved_trbs--;
719	return NULL;
720	}
721	/*
722	* Sets the MaxPStreams field and the Linear Stream Array field.
723	* Sets the dequeue pointer to the stream context array.
724	*/
725	void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
726	struct xhci_ep_ctx *ep_ctx,
727	struct xhci_stream_info *stream_info)
728	{
729	u32 max_primary_streams;
730	/* MaxPStreams is the number of stream context array entries, not the
731	* number we're actually using. Must be in 2^(MaxPstreams + 1) format.
732	* fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
733	*/
734	max_primary_streams = fls(x: stream_info->num_stream_ctxs) - 2;
735	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_context_change,
736	fmt: "Setting number of stream ctx array entries to %u",
737	1 << (max_primary_streams + 1));
738	ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
739	ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
740	| EP_HAS_LSA);
741	ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
742	}
743
744	/*
745	* Sets the MaxPStreams field and the Linear Stream Array field to 0.
746	* Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
747	* not at the beginning of the ring).
748	*/
749	void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
750	struct xhci_virt_ep *ep)
751	{
752	dma_addr_t addr;
753	ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
754	addr = xhci_trb_virt_to_dma(seg: ep->ring->deq_seg, trb: ep->ring->dequeue);
755	ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
756	}
757
758	/* Frees all stream contexts associated with the endpoint,
759	*
760	* Caller should fix the endpoint context streams fields.
761	*/
762	void xhci_free_stream_info(struct xhci_hcd *xhci,
763	struct xhci_stream_info *stream_info)
764	{
765	int cur_stream;
766	struct xhci_ring *cur_ring;
767
768	if (!stream_info)
769	return;
770
771	for (cur_stream = 1; cur_stream < stream_info->num_streams;
772	cur_stream++) {
773	cur_ring = stream_info->stream_rings[cur_stream];
774	if (cur_ring) {
775	xhci_ring_free(xhci, ring: cur_ring);
776	stream_info->stream_rings[cur_stream] = NULL;
777	}
778	}
779	xhci_free_command(xhci, command: stream_info->free_streams_command);
780	xhci->cmd_ring_reserved_trbs--;
781	if (stream_info->stream_ctx_array)
782	xhci_free_stream_ctx(xhci,
783	num_stream_ctxs: stream_info->num_stream_ctxs,
784	stream_ctx: stream_info->stream_ctx_array,
785	dma: stream_info->ctx_array_dma);
786
787	kfree(objp: stream_info->stream_rings);
788	kfree(objp: stream_info);
789	}
790
791
792	/***************** Device context manipulation *************************/
793
794	static void xhci_free_tt_info(struct xhci_hcd *xhci,
795	struct xhci_virt_device *virt_dev,
796	int slot_id)
797	{
798	struct list_head *tt_list_head;
799	struct xhci_tt_bw_info *tt_info, *next;
800	bool slot_found = false;
801
802	/* If the device never made it past the Set Address stage,
803	* it may not have the root hub port pointer set correctly.
804	*/
805	if (!virt_dev->rhub_port) {
806	xhci_dbg(xhci, "Bad rhub port.\n");
807	return;
808	}
809
810	tt_list_head = &(xhci->rh_bw[virt_dev->rhub_port->hw_portnum].tts);
811	list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
812	/* Multi-TT hubs will have more than one entry */
813	if (tt_info->slot_id == slot_id) {
814	slot_found = true;
815	list_del(entry: &tt_info->tt_list);
816	kfree(objp: tt_info);
817	} else if (slot_found) {
818	break;
819	}
820	}
821	}
822
823	int xhci_alloc_tt_info(struct xhci_hcd *xhci,
824	struct xhci_virt_device *virt_dev,
825	struct usb_device *hdev,
826	struct usb_tt *tt, gfp_t mem_flags)
827	{
828	struct xhci_tt_bw_info *tt_info;
829	unsigned int num_ports;
830	int i, j;
831	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
832
833	if (!tt->multi)
834	num_ports = 1;
835	else
836	num_ports = hdev->maxchild;
837
838	for (i = 0; i < num_ports; i++, tt_info++) {
839	struct xhci_interval_bw_table *bw_table;
840
841	tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
842	dev_to_node(dev));
843	if (!tt_info)
844	goto free_tts;
845	INIT_LIST_HEAD(list: &tt_info->tt_list);
846	list_add(new: &tt_info->tt_list,
847	head: &xhci->rh_bw[virt_dev->rhub_port->hw_portnum].tts);
848	tt_info->slot_id = virt_dev->udev->slot_id;
849	if (tt->multi)
850	tt_info->ttport = i+1;
851	bw_table = &tt_info->bw_table;
852	for (j = 0; j < XHCI_MAX_INTERVAL; j++)
853	INIT_LIST_HEAD(list: &bw_table->interval_bw[j].endpoints);
854	}
855	return 0;
856
857	free_tts:
858	xhci_free_tt_info(xhci, virt_dev, slot_id: virt_dev->udev->slot_id);
859	return -ENOMEM;
860	}
861
862
863	/* All the xhci_tds in the ring's TD list should be freed at this point.
864	* Should be called with xhci->lock held if there is any chance the TT lists
865	* will be manipulated by the configure endpoint, allocate device, or update
866	* hub functions while this function is removing the TT entries from the list.
867	*/
868	void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
869	{
870	struct xhci_virt_device *dev;
871	int i;
872	int old_active_eps = 0;
873
874	/* Slot ID 0 is reserved */
875	if (slot_id == 0 || !xhci->devs[slot_id])
876	return;
877
878	dev = xhci->devs[slot_id];
879
880	xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
881	if (!dev)
882	return;
883
884	trace_xhci_free_virt_device(vdev: dev);
885
886	if (dev->tt_info)
887	old_active_eps = dev->tt_info->active_eps;
888
889	for (i = 0; i < 31; i++) {
890	if (dev->eps[i].ring)
891	xhci_ring_free(xhci, ring: dev->eps[i].ring);
892	if (dev->eps[i].stream_info)
893	xhci_free_stream_info(xhci,
894	stream_info: dev->eps[i].stream_info);
895	/*
896	* Endpoints are normally deleted from the bandwidth list when
897	* endpoints are dropped, before device is freed.
898	* If host is dying or being removed then endpoints aren't
899	* dropped cleanly, so delete the endpoint from list here.
900	* Only applicable for hosts with software bandwidth checking.
901	*/
902
903	if (!list_empty(head: &dev->eps[i].bw_endpoint_list)) {
904	list_del_init(entry: &dev->eps[i].bw_endpoint_list);
905	xhci_dbg(xhci, "Slot %u endpoint %u not removed from BW list!\n",
906	slot_id, i);
907	}
908	}
909	/* If this is a hub, free the TT(s) from the TT list */
910	xhci_free_tt_info(xhci, virt_dev: dev, slot_id);
911	/* If necessary, update the number of active TTs on this root port */
912	xhci_update_tt_active_eps(xhci, virt_dev: dev, old_active_eps);
913
914	if (dev->in_ctx)
915	xhci_free_container_ctx(xhci, ctx: dev->in_ctx);
916	if (dev->out_ctx)
917	xhci_free_container_ctx(xhci, ctx: dev->out_ctx);
918
919	if (dev->udev && dev->udev->slot_id)
920	dev->udev->slot_id = 0;
921	if (dev->rhub_port && dev->rhub_port->slot_id == slot_id)
922	dev->rhub_port->slot_id = 0;
923	kfree(objp: xhci->devs[slot_id]);
924	xhci->devs[slot_id] = NULL;
925	}
926
927	/*
928	* Free a virt_device structure.
929	* If the virt_device added a tt_info (a hub) and has children pointing to
930	* that tt_info, then free the child first. Recursive.
931	* We can't rely on udev at this point to find child-parent relationships.
932	*/
933	static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
934	{
935	struct xhci_virt_device *vdev;
936	struct list_head *tt_list_head;
937	struct xhci_tt_bw_info *tt_info, *next;
938	int i;
939
940	vdev = xhci->devs[slot_id];
941	if (!vdev)
942	return;
943
944	if (!vdev->rhub_port) {
945	xhci_dbg(xhci, "Bad rhub port.\n");
946	goto out;
947	}
948
949	tt_list_head = &(xhci->rh_bw[vdev->rhub_port->hw_portnum].tts);
950	list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
951	/* is this a hub device that added a tt_info to the tts list */
952	if (tt_info->slot_id == slot_id) {
953	/* are any devices using this tt_info? */
954	for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
955	vdev = xhci->devs[i];
956	if (vdev && (vdev->tt_info == tt_info))
957	xhci_free_virt_devices_depth_first(
958	xhci, slot_id: i);
959	}
960	}
961	}
962	out:
963	/* we are now at a leaf device */
964	xhci_debugfs_remove_slot(xhci, slot_id);
965	xhci_free_virt_device(xhci, slot_id);
966	}
967
968	int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
969	struct usb_device *udev, gfp_t flags)
970	{
971	struct xhci_virt_device *dev;
972	int i;
973
974	/* Slot ID 0 is reserved */
975	if (slot_id == 0 || xhci->devs[slot_id]) {
976	xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
977	return 0;
978	}
979
980	dev = kzalloc(sizeof(*dev), flags);
981	if (!dev)
982	return 0;
983
984	dev->slot_id = slot_id;
985
986	/* Allocate the (output) device context that will be used in the HC. */
987	dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
988	if (!dev->out_ctx)
989	goto fail;
990
991	xhci_dbg(xhci, "Slot %d output ctx = 0x%pad (dma)\n", slot_id, &dev->out_ctx->dma);
992
993	/* Allocate the (input) device context for address device command */
994	dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
995	if (!dev->in_ctx)
996	goto fail;
997
998	xhci_dbg(xhci, "Slot %d input ctx = 0x%pad (dma)\n", slot_id, &dev->in_ctx->dma);
999
1000	/* Initialize the cancellation and bandwidth list for each ep */
1001	for (i = 0; i < 31; i++) {
1002	dev->eps[i].ep_index = i;
1003	dev->eps[i].vdev = dev;
1004	dev->eps[i].xhci = xhci;
1005	INIT_LIST_HEAD(list: &dev->eps[i].cancelled_td_list);
1006	INIT_LIST_HEAD(list: &dev->eps[i].bw_endpoint_list);
1007	}
1008
1009	/* Allocate endpoint 0 ring */
1010	dev->eps[0].ring = xhci_ring_alloc(xhci, num_segs: 2, type: TYPE_CTRL, max_packet: 0, flags);
1011	if (!dev->eps[0].ring)
1012	goto fail;
1013
1014	dev->udev = udev;
1015
1016	/* Point to output device context in dcbaa. */
1017	xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1018	xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1019	slot_id,
1020	&xhci->dcbaa->dev_context_ptrs[slot_id],
1021	le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1022
1023	trace_xhci_alloc_virt_device(vdev: dev);
1024
1025	xhci->devs[slot_id] = dev;
1026
1027	return 1;
1028	fail:
1029
1030	if (dev->in_ctx)
1031	xhci_free_container_ctx(xhci, ctx: dev->in_ctx);
1032	if (dev->out_ctx)
1033	xhci_free_container_ctx(xhci, ctx: dev->out_ctx);
1034	kfree(objp: dev);
1035
1036	return 0;
1037	}
1038
1039	void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1040	struct usb_device *udev)
1041	{
1042	struct xhci_virt_device *virt_dev;
1043	struct xhci_ep_ctx *ep0_ctx;
1044	struct xhci_ring *ep_ring;
1045
1046	virt_dev = xhci->devs[udev->slot_id];
1047	ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1048	ep_ring = virt_dev->eps[0].ring;
1049	/*
1050	* FIXME we don't keep track of the dequeue pointer very well after a
1051	* Set TR dequeue pointer, so we're setting the dequeue pointer of the
1052	* host to our enqueue pointer. This should only be called after a
1053	* configured device has reset, so all control transfers should have
1054	* been completed or cancelled before the reset.
1055	*/
1056	ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1057	ep_ring->enqueue)
1058	| ep_ring->cycle_state);
1059	}
1060
1061	/*
1062	* The xHCI roothub may have ports of differing speeds in any order in the port
1063	* status registers.
1064	*
1065	* The xHCI hardware wants to know the roothub port that the USB device
1066	* is attached to (or the roothub port its ancestor hub is attached to). All we
1067	* know is the index of that port under either the USB 2.0 or the USB 3.0
1068	* roothub, but that doesn't give us the real index into the HW port status
1069	* registers.
1070	*/
1071	static struct xhci_port *xhci_find_rhub_port(struct xhci_hcd *xhci, struct usb_device *udev)
1072	{
1073	struct usb_device *top_dev;
1074	struct xhci_hub *rhub;
1075	struct usb_hcd *hcd;
1076
1077	if (udev->speed >= USB_SPEED_SUPER)
1078	hcd = xhci_get_usb3_hcd(xhci);
1079	else
1080	hcd = xhci->main_hcd;
1081
1082	for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1083	top_dev = top_dev->parent)
1084	/* Found device below root hub */;
1085
1086	rhub = xhci_get_rhub(hcd);
1087	return rhub->ports[top_dev->portnum - 1];
1088	}
1089
1090	/* Setup an xHCI virtual device for a Set Address command */
1091	int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1092	{
1093	struct xhci_virt_device *dev;
1094	struct xhci_ep_ctx *ep0_ctx;
1095	struct xhci_slot_ctx *slot_ctx;
1096	u32 max_packets;
1097
1098	dev = xhci->devs[udev->slot_id];
1099	/* Slot ID 0 is reserved */
1100	if (udev->slot_id == 0 || !dev) {
1101	xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1102	udev->slot_id);
1103	return -EINVAL;
1104	}
1105	ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1106	slot_ctx = xhci_get_slot_ctx(xhci, ctx: dev->in_ctx);
1107
1108	/* 3) Only the control endpoint is valid - one endpoint context */
1109	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1110	switch (udev->speed) {
1111	case USB_SPEED_SUPER_PLUS:
1112	slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1113	max_packets = MAX_PACKET(512);
1114	break;
1115	case USB_SPEED_SUPER:
1116	slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1117	max_packets = MAX_PACKET(512);
1118	break;
1119	case USB_SPEED_HIGH:
1120	slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1121	max_packets = MAX_PACKET(64);
1122	break;
1123	/* USB core guesses at a 64-byte max packet first for FS devices */
1124	case USB_SPEED_FULL:
1125	slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1126	max_packets = MAX_PACKET(64);
1127	break;
1128	case USB_SPEED_LOW:
1129	slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1130	max_packets = MAX_PACKET(8);
1131	break;
1132	default:
1133	/* Speed was set earlier, this shouldn't happen. */
1134	return -EINVAL;
1135	}
1136	/* Find the root hub port this device is under */
1137	dev->rhub_port = xhci_find_rhub_port(xhci, udev);
1138	if (!dev->rhub_port)
1139	return -EINVAL;
1140	/* Slot ID is set to the device directly below the root hub */
1141	if (!udev->parent->parent)
1142	dev->rhub_port->slot_id = udev->slot_id;
1143	slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(dev->rhub_port->hw_portnum + 1));
1144	xhci_dbg(xhci, "Slot ID %d: HW portnum %d, hcd portnum %d\n",
1145	udev->slot_id, dev->rhub_port->hw_portnum, dev->rhub_port->hcd_portnum);
1146
1147	/* Find the right bandwidth table that this device will be a part of.
1148	* If this is a full speed device attached directly to a root port (or a
1149	* decendent of one), it counts as a primary bandwidth domain, not a
1150	* secondary bandwidth domain under a TT. An xhci_tt_info structure
1151	* will never be created for the HS root hub.
1152	*/
1153	if (!udev->tt || !udev->tt->hub->parent) {
1154	dev->bw_table = &xhci->rh_bw[dev->rhub_port->hw_portnum].bw_table;
1155	} else {
1156	struct xhci_root_port_bw_info *rh_bw;
1157	struct xhci_tt_bw_info *tt_bw;
1158
1159	rh_bw = &xhci->rh_bw[dev->rhub_port->hw_portnum];
1160	/* Find the right TT. */
1161	list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1162	if (tt_bw->slot_id != udev->tt->hub->slot_id)
1163	continue;
1164
1165	if (!dev->udev->tt->multi ||
1166	(udev->tt->multi &&
1167	tt_bw->ttport == dev->udev->ttport)) {
1168	dev->bw_table = &tt_bw->bw_table;
1169	dev->tt_info = tt_bw;
1170	break;
1171	}
1172	}
1173	if (!dev->tt_info)
1174	xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1175	}
1176
1177	/* Is this a LS/FS device under an external HS hub? */
1178	if (udev->tt && udev->tt->hub->parent) {
1179	slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1180	(udev->ttport << 8));
1181	if (udev->tt->multi)
1182	slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1183	}
1184	xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1185	xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1186
1187	/* Step 4 - ring already allocated */
1188	/* Step 5 */
1189	ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1190
1191	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1192	ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1193	max_packets);
1194
1195	ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1196	dev->eps[0].ring->cycle_state);
1197
1198	trace_xhci_setup_addressable_virt_device(vdev: dev);
1199
1200	/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1201
1202	return 0;
1203	}
1204
1205	/*
1206	* Convert interval expressed as 2^(bInterval - 1) == interval into
1207	* straight exponent value 2^n == interval.
1208	*
1209	*/
1210	static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1211	struct usb_host_endpoint *ep)
1212	{
1213	unsigned int interval;
1214
1215	interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1216	if (interval != ep->desc.bInterval - 1)
1217	dev_warn(&udev->dev,
1218	"ep %#x - rounding interval to %d %sframes\n",
1219	ep->desc.bEndpointAddress,
1220	1 << interval,
1221	udev->speed == USB_SPEED_FULL ? "" : "micro");
1222
1223	if (udev->speed == USB_SPEED_FULL) {
1224	/*
1225	* Full speed isoc endpoints specify interval in frames,
1226	* not microframes. We are using microframes everywhere,
1227	* so adjust accordingly.
1228	*/
1229	interval += 3; /* 1 frame = 2^3 uframes */
1230	}
1231
1232	return interval;
1233	}
1234
1235	/*
1236	* Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1237	* microframes, rounded down to nearest power of 2.
1238	*/
1239	static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1240	struct usb_host_endpoint *ep, unsigned int desc_interval,
1241	unsigned int min_exponent, unsigned int max_exponent)
1242	{
1243	unsigned int interval;
1244
1245	interval = fls(x: desc_interval) - 1;
1246	interval = clamp_val(interval, min_exponent, max_exponent);
1247	if ((1 << interval) != desc_interval)
1248	dev_dbg(&udev->dev,
1249	"ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1250	ep->desc.bEndpointAddress,
1251	1 << interval,
1252	desc_interval);
1253
1254	return interval;
1255	}
1256
1257	static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1258	struct usb_host_endpoint *ep)
1259	{
1260	if (ep->desc.bInterval == 0)
1261	return 0;
1262	return xhci_microframes_to_exponent(udev, ep,
1263	desc_interval: ep->desc.bInterval, min_exponent: 0, max_exponent: 15);
1264	}
1265
1266
1267	static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1268	struct usb_host_endpoint *ep)
1269	{
1270	return xhci_microframes_to_exponent(udev, ep,
1271	desc_interval: ep->desc.bInterval * 8, min_exponent: 3, max_exponent: 10);
1272	}
1273
1274	/* Return the polling or NAK interval.
1275	*
1276	* The polling interval is expressed in "microframes". If xHCI's Interval field
1277	* is set to N, it will service the endpoint every 2^(Interval)*125us.
1278	*
1279	* The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1280	* is set to 0.
1281	*/
1282	static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1283	struct usb_host_endpoint *ep)
1284	{
1285	unsigned int interval = 0;
1286
1287	switch (udev->speed) {
1288	case USB_SPEED_HIGH:
1289	/* Max NAK rate */
1290	if (usb_endpoint_xfer_control(epd: &ep->desc) ||
1291	usb_endpoint_xfer_bulk(epd: &ep->desc)) {
1292	interval = xhci_parse_microframe_interval(udev, ep);
1293	break;
1294	}
1295	fallthrough; /* SS and HS isoc/int have same decoding */
1296
1297	case USB_SPEED_SUPER_PLUS:
1298	case USB_SPEED_SUPER:
1299	if (usb_endpoint_xfer_int(epd: &ep->desc) ||
1300	usb_endpoint_xfer_isoc(epd: &ep->desc)) {
1301	interval = xhci_parse_exponent_interval(udev, ep);
1302	}
1303	break;
1304
1305	case USB_SPEED_FULL:
1306	if (usb_endpoint_xfer_isoc(epd: &ep->desc)) {
1307	interval = xhci_parse_exponent_interval(udev, ep);
1308	break;
1309	}
1310	/*
1311	* Fall through for interrupt endpoint interval decoding
1312	* since it uses the same rules as low speed interrupt
1313	* endpoints.
1314	*/
1315	fallthrough;
1316
1317	case USB_SPEED_LOW:
1318	if (usb_endpoint_xfer_int(epd: &ep->desc) ||
1319	usb_endpoint_xfer_isoc(epd: &ep->desc)) {
1320
1321	interval = xhci_parse_frame_interval(udev, ep);
1322	}
1323	break;
1324
1325	default:
1326	BUG();
1327	}
1328	return interval;
1329	}
1330
1331	/* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1332	* High speed endpoint descriptors can define "the number of additional
1333	* transaction opportunities per microframe", but that goes in the Max Burst
1334	* endpoint context field.
1335	*/
1336	static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1337	struct usb_host_endpoint *ep)
1338	{
1339	if (udev->speed < USB_SPEED_SUPER ||
1340	!usb_endpoint_xfer_isoc(epd: &ep->desc))
1341	return 0;
1342	return ep->ss_ep_comp.bmAttributes;
1343	}
1344
1345	static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1346	struct usb_host_endpoint *ep)
1347	{
1348	/* Super speed and Plus have max burst in ep companion desc */
1349	if (udev->speed >= USB_SPEED_SUPER)
1350	return ep->ss_ep_comp.bMaxBurst;
1351
1352	if (udev->speed == USB_SPEED_HIGH &&
1353	(usb_endpoint_xfer_isoc(epd: &ep->desc) ||
1354	usb_endpoint_xfer_int(epd: &ep->desc)))
1355	return usb_endpoint_maxp_mult(epd: &ep->desc) - 1;
1356
1357	return 0;
1358	}
1359
1360	static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1361	{
1362	int in;
1363
1364	in = usb_endpoint_dir_in(epd: &ep->desc);
1365
1366	switch (usb_endpoint_type(epd: &ep->desc)) {
1367	case USB_ENDPOINT_XFER_CONTROL:
1368	return CTRL_EP;
1369	case USB_ENDPOINT_XFER_BULK:
1370	return in ? BULK_IN_EP : BULK_OUT_EP;
1371	case USB_ENDPOINT_XFER_ISOC:
1372	return in ? ISOC_IN_EP : ISOC_OUT_EP;
1373	case USB_ENDPOINT_XFER_INT:
1374	return in ? INT_IN_EP : INT_OUT_EP;
1375	}
1376	return 0;
1377	}
1378
1379	/* Return the maximum endpoint service interval time (ESIT) payload.
1380	* Basically, this is the maxpacket size, multiplied by the burst size
1381	* and mult size.
1382	*/
1383	static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1384	struct usb_host_endpoint *ep)
1385	{
1386	int max_burst;
1387	int max_packet;
1388
1389	/* Only applies for interrupt or isochronous endpoints */
1390	if (usb_endpoint_xfer_control(epd: &ep->desc) ||
1391	usb_endpoint_xfer_bulk(epd: &ep->desc))
1392	return 0;
1393
1394	/* SuperSpeedPlus Isoc ep sending over 48k per esit */
1395	if ((udev->speed >= USB_SPEED_SUPER_PLUS) &&
1396	USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes))
1397	return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval);
1398
1399	/* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1400	if (udev->speed >= USB_SPEED_SUPER)
1401	return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1402
1403	max_packet = usb_endpoint_maxp(epd: &ep->desc);
1404	max_burst = usb_endpoint_maxp_mult(epd: &ep->desc);
1405	/* A 0 in max burst means 1 transfer per ESIT */
1406	return max_packet * max_burst;
1407	}
1408
1409	/* Set up an endpoint with one ring segment. Do not allocate stream rings.
1410	* Drivers will have to call usb_alloc_streams() to do that.
1411	*/
1412	int xhci_endpoint_init(struct xhci_hcd *xhci,
1413	struct xhci_virt_device *virt_dev,
1414	struct usb_device *udev,
1415	struct usb_host_endpoint *ep,
1416	gfp_t mem_flags)
1417	{
1418	unsigned int ep_index;
1419	struct xhci_ep_ctx *ep_ctx;
1420	struct xhci_ring *ep_ring;
1421	unsigned int max_packet;
1422	enum xhci_ring_type ring_type;
1423	u32 max_esit_payload;
1424	u32 endpoint_type;
1425	unsigned int max_burst;
1426	unsigned int interval;
1427	unsigned int mult;
1428	unsigned int avg_trb_len;
1429	unsigned int err_count = 0;
1430
1431	ep_index = xhci_get_endpoint_index(desc: &ep->desc);
1432	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1433
1434	endpoint_type = xhci_get_endpoint_type(ep);
1435	if (!endpoint_type)
1436	return -EINVAL;
1437
1438	ring_type = usb_endpoint_type(epd: &ep->desc);
1439
1440	/*
1441	* Get values to fill the endpoint context, mostly from ep descriptor.
1442	* The average TRB buffer lengt for bulk endpoints is unclear as we
1443	* have no clue on scatter gather list entry size. For Isoc and Int,
1444	* set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1445	*/
1446	max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1447	interval = xhci_get_endpoint_interval(udev, ep);
1448
1449	/* Periodic endpoint bInterval limit quirk */
1450	if (usb_endpoint_xfer_int(epd: &ep->desc) ||
1451	usb_endpoint_xfer_isoc(epd: &ep->desc)) {
1452	if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1453	udev->speed >= USB_SPEED_HIGH &&
1454	interval >= 7) {
1455	interval = 6;
1456	}
1457	}
1458
1459	mult = xhci_get_endpoint_mult(udev, ep);
1460	max_packet = usb_endpoint_maxp(epd: &ep->desc);
1461	max_burst = xhci_get_endpoint_max_burst(udev, ep);
1462	avg_trb_len = max_esit_payload;
1463
1464	/* FIXME dig Mult and streams info out of ep companion desc */
1465
1466	/* Allow 3 retries for everything but isoc, set CErr = 3 */
1467	if (!usb_endpoint_xfer_isoc(epd: &ep->desc))
1468	err_count = 3;
1469	/* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
1470	if (usb_endpoint_xfer_bulk(epd: &ep->desc)) {
1471	if (udev->speed == USB_SPEED_HIGH)
1472	max_packet = 512;
1473	if (udev->speed == USB_SPEED_FULL) {
1474	max_packet = rounddown_pow_of_two(max_packet);
1475	max_packet = clamp_val(max_packet, 8, 64);
1476	}
1477	}
1478	/* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1479	if (usb_endpoint_xfer_control(epd: &ep->desc) && xhci->hci_version >= 0x100)
1480	avg_trb_len = 8;
1481	/* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1482	if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2))
1483	mult = 0;
1484
1485	/* Set up the endpoint ring */
1486	virt_dev->eps[ep_index].new_ring =
1487	xhci_ring_alloc(xhci, num_segs: 2, type: ring_type, max_packet, flags: mem_flags);
1488	if (!virt_dev->eps[ep_index].new_ring)
1489	return -ENOMEM;
1490
1491	virt_dev->eps[ep_index].skip = false;
1492	ep_ring = virt_dev->eps[ep_index].new_ring;
1493
1494	/* Fill the endpoint context */
1495	ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1496	EP_INTERVAL(interval) |
1497	EP_MULT(mult));
1498	ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1499	MAX_PACKET(max_packet) |
1500	MAX_BURST(max_burst) |
1501	ERROR_COUNT(err_count));
1502	ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1503	ep_ring->cycle_state);
1504
1505	ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1506	EP_AVG_TRB_LENGTH(avg_trb_len));
1507
1508	return 0;
1509	}
1510
1511	void xhci_endpoint_zero(struct xhci_hcd *xhci,
1512	struct xhci_virt_device *virt_dev,
1513	struct usb_host_endpoint *ep)
1514	{
1515	unsigned int ep_index;
1516	struct xhci_ep_ctx *ep_ctx;
1517
1518	ep_index = xhci_get_endpoint_index(desc: &ep->desc);
1519	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1520
1521	ep_ctx->ep_info = 0;
1522	ep_ctx->ep_info2 = 0;
1523	ep_ctx->deq = 0;
1524	ep_ctx->tx_info = 0;
1525	/* Don't free the endpoint ring until the set interface or configuration
1526	* request succeeds.
1527	*/
1528	}
1529
1530	void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1531	{
1532	bw_info->ep_interval = 0;
1533	bw_info->mult = 0;
1534	bw_info->num_packets = 0;
1535	bw_info->max_packet_size = 0;
1536	bw_info->type = 0;
1537	bw_info->max_esit_payload = 0;
1538	}
1539
1540	void xhci_update_bw_info(struct xhci_hcd *xhci,
1541	struct xhci_container_ctx *in_ctx,
1542	struct xhci_input_control_ctx *ctrl_ctx,
1543	struct xhci_virt_device *virt_dev)
1544	{
1545	struct xhci_bw_info *bw_info;
1546	struct xhci_ep_ctx *ep_ctx;
1547	unsigned int ep_type;
1548	int i;
1549
1550	for (i = 1; i < 31; i++) {
1551	bw_info = &virt_dev->eps[i].bw_info;
1552
1553	/* We can't tell what endpoint type is being dropped, but
1554	* unconditionally clearing the bandwidth info for non-periodic
1555	* endpoints should be harmless because the info will never be
1556	* set in the first place.
1557	*/
1558	if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1559	/* Dropped endpoint */
1560	xhci_clear_endpoint_bw_info(bw_info);
1561	continue;
1562	}
1563
1564	if (EP_IS_ADDED(ctrl_ctx, i)) {
1565	ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1566	ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1567
1568	/* Ignore non-periodic endpoints */
1569	if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1570	ep_type != ISOC_IN_EP &&
1571	ep_type != INT_IN_EP)
1572	continue;
1573
1574	/* Added or changed endpoint */
1575	bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1576	le32_to_cpu(ep_ctx->ep_info));
1577	/* Number of packets and mult are zero-based in the
1578	* input context, but we want one-based for the
1579	* interval table.
1580	*/
1581	bw_info->mult = CTX_TO_EP_MULT(
1582	le32_to_cpu(ep_ctx->ep_info)) + 1;
1583	bw_info->num_packets = CTX_TO_MAX_BURST(
1584	le32_to_cpu(ep_ctx->ep_info2)) + 1;
1585	bw_info->max_packet_size = MAX_PACKET_DECODED(
1586	le32_to_cpu(ep_ctx->ep_info2));
1587	bw_info->type = ep_type;
1588	bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1589	le32_to_cpu(ep_ctx->tx_info));
1590	}
1591	}
1592	}
1593
1594	/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1595	* Useful when you want to change one particular aspect of the endpoint and then
1596	* issue a configure endpoint command.
1597	*/
1598	void xhci_endpoint_copy(struct xhci_hcd *xhci,
1599	struct xhci_container_ctx *in_ctx,
1600	struct xhci_container_ctx *out_ctx,
1601	unsigned int ep_index)
1602	{
1603	struct xhci_ep_ctx *out_ep_ctx;
1604	struct xhci_ep_ctx *in_ep_ctx;
1605
1606	out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1607	in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1608
1609	in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1610	in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1611	in_ep_ctx->deq = out_ep_ctx->deq;
1612	in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1613	if (xhci->quirks & XHCI_MTK_HOST) {
1614	in_ep_ctx->reserved[0] = out_ep_ctx->reserved[0];
1615	in_ep_ctx->reserved[1] = out_ep_ctx->reserved[1];
1616	}
1617	}
1618
1619	/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1620	* Useful when you want to change one particular aspect of the endpoint and then
1621	* issue a configure endpoint command. Only the context entries field matters,
1622	* but we'll copy the whole thing anyway.
1623	*/
1624	void xhci_slot_copy(struct xhci_hcd *xhci,
1625	struct xhci_container_ctx *in_ctx,
1626	struct xhci_container_ctx *out_ctx)
1627	{
1628	struct xhci_slot_ctx *in_slot_ctx;
1629	struct xhci_slot_ctx *out_slot_ctx;
1630
1631	in_slot_ctx = xhci_get_slot_ctx(xhci, ctx: in_ctx);
1632	out_slot_ctx = xhci_get_slot_ctx(xhci, ctx: out_ctx);
1633
1634	in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1635	in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1636	in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1637	in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1638	}
1639
1640	/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1641	static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1642	{
1643	int i;
1644	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1645	int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1646
1647	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
1648	fmt: "Allocating %d scratchpad buffers", num_sp);
1649
1650	if (!num_sp)
1651	return 0;
1652
1653	xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
1654	dev_to_node(dev));
1655	if (!xhci->scratchpad)
1656	goto fail_sp;
1657
1658	xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1659	array_size(sizeof(u64), num_sp),
1660	dma_handle: &xhci->scratchpad->sp_dma, gfp: flags);
1661	if (!xhci->scratchpad->sp_array)
1662	goto fail_sp2;
1663
1664	xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
1665	flags, dev_to_node(dev));
1666	if (!xhci->scratchpad->sp_buffers)
1667	goto fail_sp3;
1668
1669	xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1670	for (i = 0; i < num_sp; i++) {
1671	dma_addr_t dma;
1672	void *buf = dma_alloc_coherent(dev, size: xhci->page_size, dma_handle: &dma,
1673	gfp: flags);
1674	if (!buf)
1675	goto fail_sp4;
1676
1677	xhci->scratchpad->sp_array[i] = dma;
1678	xhci->scratchpad->sp_buffers[i] = buf;
1679	}
1680
1681	return 0;
1682
1683	fail_sp4:
1684	while (i--)
1685	dma_free_coherent(dev, size: xhci->page_size,
1686	cpu_addr: xhci->scratchpad->sp_buffers[i],
1687	dma_handle: xhci->scratchpad->sp_array[i]);
1688
1689	kfree(objp: xhci->scratchpad->sp_buffers);
1690
1691	fail_sp3:
1692	dma_free_coherent(dev, array_size(sizeof(u64), num_sp),
1693	cpu_addr: xhci->scratchpad->sp_array,
1694	dma_handle: xhci->scratchpad->sp_dma);
1695
1696	fail_sp2:
1697	kfree(objp: xhci->scratchpad);
1698	xhci->scratchpad = NULL;
1699
1700	fail_sp:
1701	return -ENOMEM;
1702	}
1703
1704	static void scratchpad_free(struct xhci_hcd *xhci)
1705	{
1706	int num_sp;
1707	int i;
1708	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1709
1710	if (!xhci->scratchpad)
1711	return;
1712
1713	num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1714
1715	for (i = 0; i < num_sp; i++) {
1716	dma_free_coherent(dev, size: xhci->page_size,
1717	cpu_addr: xhci->scratchpad->sp_buffers[i],
1718	dma_handle: xhci->scratchpad->sp_array[i]);
1719	}
1720	kfree(objp: xhci->scratchpad->sp_buffers);
1721	dma_free_coherent(dev, array_size(sizeof(u64), num_sp),
1722	cpu_addr: xhci->scratchpad->sp_array,
1723	dma_handle: xhci->scratchpad->sp_dma);
1724	kfree(objp: xhci->scratchpad);
1725	xhci->scratchpad = NULL;
1726	}
1727
1728	struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1729	bool allocate_completion, gfp_t mem_flags)
1730	{
1731	struct xhci_command *command;
1732	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1733
1734	command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
1735	if (!command)
1736	return NULL;
1737
1738	if (allocate_completion) {
1739	command->completion =
1740	kzalloc_node(sizeof(struct completion), mem_flags,
1741	dev_to_node(dev));
1742	if (!command->completion) {
1743	kfree(objp: command);
1744	return NULL;
1745	}
1746	init_completion(x: command->completion);
1747	}
1748
1749	command->status = 0;
1750	/* set default timeout to 5000 ms */
1751	command->timeout_ms = XHCI_CMD_DEFAULT_TIMEOUT;
1752	INIT_LIST_HEAD(list: &command->cmd_list);
1753	return command;
1754	}
1755
1756	struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1757	bool allocate_completion, gfp_t mem_flags)
1758	{
1759	struct xhci_command *command;
1760
1761	command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
1762	if (!command)
1763	return NULL;
1764
1765	command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1766	flags: mem_flags);
1767	if (!command->in_ctx) {
1768	kfree(objp: command->completion);
1769	kfree(objp: command);
1770	return NULL;
1771	}
1772	return command;
1773	}
1774
1775	void xhci_urb_free_priv(struct urb_priv *urb_priv)
1776	{
1777	kfree(objp: urb_priv);
1778	}
1779
1780	void xhci_free_command(struct xhci_hcd *xhci,
1781	struct xhci_command *command)
1782	{
1783	xhci_free_container_ctx(xhci,
1784	ctx: command->in_ctx);
1785	kfree(objp: command->completion);
1786	kfree(objp: command);
1787	}
1788
1789	static int xhci_alloc_erst(struct xhci_hcd *xhci,
1790	struct xhci_ring *evt_ring,
1791	struct xhci_erst *erst,
1792	gfp_t flags)
1793	{
1794	size_t size;
1795	unsigned int val;
1796	struct xhci_segment *seg;
1797	struct xhci_erst_entry *entry;
1798
1799	size = array_size(sizeof(struct xhci_erst_entry), evt_ring->num_segs);
1800	erst->entries = dma_alloc_coherent(dev: xhci_to_hcd(xhci)->self.sysdev,
1801	size, dma_handle: &erst->erst_dma_addr, gfp: flags);
1802	if (!erst->entries)
1803	return -ENOMEM;
1804
1805	erst->num_entries = evt_ring->num_segs;
1806
1807	seg = evt_ring->first_seg;
1808	for (val = 0; val < evt_ring->num_segs; val++) {
1809	entry = &erst->entries[val];
1810	entry->seg_addr = cpu_to_le64(seg->dma);
1811	entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
1812	entry->rsvd = 0;
1813	seg = seg->next;
1814	}
1815
1816	return 0;
1817	}
1818
1819	static void
1820	xhci_remove_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
1821	{
1822	u32 tmp;
1823
1824	if (!ir)
1825	return;
1826
1827	/*
1828	* Clean out interrupter registers except ERSTBA. Clearing either the
1829	* low or high 32 bits of ERSTBA immediately causes the controller to
1830	* dereference the partially cleared 64 bit address, causing IOMMU error.
1831	*/
1832	if (ir->ir_set) {
1833	tmp = readl(addr: &ir->ir_set->erst_size);
1834	tmp &= ~ERST_SIZE_MASK;
1835	writel(val: tmp, addr: &ir->ir_set->erst_size);
1836
1837	xhci_update_erst_dequeue(xhci, ir, clear_ehb: true);
1838	}
1839	}
1840
1841	static void
1842	xhci_free_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
1843	{
1844	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1845	size_t erst_size;
1846
1847	if (!ir)
1848	return;
1849
1850	erst_size = array_size(sizeof(struct xhci_erst_entry), ir->erst.num_entries);
1851	if (ir->erst.entries)
1852	dma_free_coherent(dev, size: erst_size,
1853	cpu_addr: ir->erst.entries,
1854	dma_handle: ir->erst.erst_dma_addr);
1855	ir->erst.entries = NULL;
1856
1857	/* free interrupter event ring */
1858	if (ir->event_ring)
1859	xhci_ring_free(xhci, ring: ir->event_ring);
1860
1861	ir->event_ring = NULL;
1862
1863	kfree(objp: ir);
1864	}
1865
1866	void xhci_remove_secondary_interrupter(struct usb_hcd *hcd, struct xhci_interrupter *ir)
1867	{
1868	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1869	unsigned int intr_num;
1870
1871	spin_lock_irq(lock: &xhci->lock);
1872
1873	/* interrupter 0 is primary interrupter, don't touch it */
1874	if (!ir || !ir->intr_num || ir->intr_num >= xhci->max_interrupters) {
1875	xhci_dbg(xhci, "Invalid secondary interrupter, can't remove\n");
1876	spin_unlock_irq(lock: &xhci->lock);
1877	return;
1878	}
1879
1880	/*
1881	* Cleanup secondary interrupter to ensure there are no pending events.
1882	* This also updates event ring dequeue pointer back to the start.
1883	*/
1884	xhci_skip_sec_intr_events(xhci, ring: ir->event_ring, ir);
1885	intr_num = ir->intr_num;
1886
1887	xhci_remove_interrupter(xhci, ir);
1888	xhci->interrupters[intr_num] = NULL;
1889
1890	spin_unlock_irq(lock: &xhci->lock);
1891
1892	xhci_free_interrupter(xhci, ir);
1893	}
1894	EXPORT_SYMBOL_GPL(xhci_remove_secondary_interrupter);
1895
1896	void xhci_mem_cleanup(struct xhci_hcd *xhci)
1897	{
1898	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1899	int i, j, num_ports;
1900
1901	cancel_delayed_work_sync(dwork: &xhci->cmd_timer);
1902
1903	for (i = 0; xhci->interrupters && i < xhci->max_interrupters; i++) {
1904	if (xhci->interrupters[i]) {
1905	xhci_remove_interrupter(xhci, ir: xhci->interrupters[i]);
1906	xhci_free_interrupter(xhci, ir: xhci->interrupters[i]);
1907	xhci->interrupters[i] = NULL;
1908	}
1909	}
1910	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "Freed interrupters");
1911
1912	if (xhci->cmd_ring)
1913	xhci_ring_free(xhci, ring: xhci->cmd_ring);
1914	xhci->cmd_ring = NULL;
1915	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "Freed command ring");
1916	xhci_cleanup_command_queue(xhci);
1917
1918	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1919	for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1920	struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1921	for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1922	struct list_head *ep = &bwt->interval_bw[j].endpoints;
1923	while (!list_empty(head: ep))
1924	list_del_init(entry: ep->next);
1925	}
1926	}
1927
1928	for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--)
1929	xhci_free_virt_devices_depth_first(xhci, slot_id: i);
1930
1931	dma_pool_destroy(pool: xhci->segment_pool);
1932	xhci->segment_pool = NULL;
1933	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "Freed segment pool");
1934
1935	dma_pool_destroy(pool: xhci->device_pool);
1936	xhci->device_pool = NULL;
1937	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "Freed device context pool");
1938
1939	dma_pool_destroy(pool: xhci->small_streams_pool);
1940	xhci->small_streams_pool = NULL;
1941	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
1942	fmt: "Freed small stream array pool");
1943
1944	dma_pool_destroy(pool: xhci->port_bw_pool);
1945	xhci->port_bw_pool = NULL;
1946	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
1947	fmt: "Freed xhci port bw array pool");
1948
1949	dma_pool_destroy(pool: xhci->medium_streams_pool);
1950	xhci->medium_streams_pool = NULL;
1951	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
1952	fmt: "Freed medium stream array pool");
1953
1954	if (xhci->dcbaa)
1955	dma_free_coherent(dev, size: sizeof(*xhci->dcbaa),
1956	cpu_addr: xhci->dcbaa, dma_handle: xhci->dcbaa->dma);
1957	xhci->dcbaa = NULL;
1958
1959	scratchpad_free(xhci);
1960
1961	if (!xhci->rh_bw)
1962	goto no_bw;
1963
1964	for (i = 0; i < num_ports; i++) {
1965	struct xhci_tt_bw_info *tt, *n;
1966	list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1967	list_del(entry: &tt->tt_list);
1968	kfree(objp: tt);
1969	}
1970	}
1971
1972	no_bw:
1973	xhci->cmd_ring_reserved_trbs = 0;
1974	xhci->usb2_rhub.num_ports = 0;
1975	xhci->usb3_rhub.num_ports = 0;
1976	xhci->num_active_eps = 0;
1977	kfree(objp: xhci->usb2_rhub.ports);
1978	kfree(objp: xhci->usb3_rhub.ports);
1979	kfree(objp: xhci->hw_ports);
1980	kfree(objp: xhci->rh_bw);
1981	for (i = 0; i < xhci->num_port_caps; i++)
1982	kfree(objp: xhci->port_caps[i].psi);
1983	kfree(objp: xhci->port_caps);
1984	kfree(objp: xhci->interrupters);
1985	xhci->num_port_caps = 0;
1986
1987	xhci->usb2_rhub.ports = NULL;
1988	xhci->usb3_rhub.ports = NULL;
1989	xhci->hw_ports = NULL;
1990	xhci->rh_bw = NULL;
1991	xhci->port_caps = NULL;
1992	xhci->interrupters = NULL;
1993
1994	xhci->page_size = 0;
1995	xhci->usb2_rhub.bus_state.bus_suspended = 0;
1996	xhci->usb3_rhub.bus_state.bus_suspended = 0;
1997	}
1998
1999	static void xhci_set_hc_event_deq(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
2000	{
2001	dma_addr_t deq;
2002
2003	deq = xhci_trb_virt_to_dma(seg: ir->event_ring->deq_seg,
2004	trb: ir->event_ring->dequeue);
2005	if (!deq)
2006	xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr.\n");
2007	/* Update HC event ring dequeue pointer */
2008	/* Don't clear the EHB bit (which is RW1C) because
2009	* there might be more events to service.
2010	*/
2011	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2012	fmt: "// Write event ring dequeue pointer, preserving EHB bit");
2013	xhci_write_64(xhci, val: deq & ERST_PTR_MASK, regs: &ir->ir_set->erst_dequeue);
2014	}
2015
2016	static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2017	__le32 __iomem *addr, int max_caps)
2018	{
2019	u32 temp, port_offset, port_count;
2020	int i;
2021	u8 major_revision, minor_revision, tmp_minor_revision;
2022	struct xhci_hub *rhub;
2023	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2024	struct xhci_port_cap *port_cap;
2025
2026	temp = readl(addr);
2027	major_revision = XHCI_EXT_PORT_MAJOR(temp);
2028	minor_revision = XHCI_EXT_PORT_MINOR(temp);
2029
2030	if (major_revision == 0x03) {
2031	rhub = &xhci->usb3_rhub;
2032	/*
2033	* Some hosts incorrectly use sub-minor version for minor
2034	* version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01
2035	* for bcdUSB 0x310). Since there is no USB release with sub
2036	* minor version 0x301 to 0x309, we can assume that they are
2037	* incorrect and fix it here.
2038	*/
2039	if (minor_revision > 0x00 && minor_revision < 0x10)
2040	minor_revision <<= 4;
2041	/*
2042	* Some zhaoxin's xHCI controller that follow usb3.1 spec
2043	* but only support Gen1.
2044	*/
2045	if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
2046	tmp_minor_revision = minor_revision;
2047	minor_revision = 0;
2048	}
2049
2050	} else if (major_revision <= 0x02) {
2051	rhub = &xhci->usb2_rhub;
2052	} else {
2053	xhci_warn(xhci, "Ignoring unknown port speed, Ext Cap %p, revision = 0x%x\n",
2054	addr, major_revision);
2055	/* Ignoring port protocol we can't understand. FIXME */
2056	return;
2057	}
2058
2059	/* Port offset and count in the third dword, see section 7.2 */
2060	temp = readl(addr: addr + 2);
2061	port_offset = XHCI_EXT_PORT_OFF(temp);
2062	port_count = XHCI_EXT_PORT_COUNT(temp);
2063	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2064	fmt: "Ext Cap %p, port offset = %u, count = %u, revision = 0x%x",
2065	addr, port_offset, port_count, major_revision);
2066	/* Port count includes the current port offset */
2067	if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2068	/* WTF? "Valid values are ‘1’ to MaxPorts" */
2069	return;
2070
2071	port_cap = &xhci->port_caps[xhci->num_port_caps++];
2072	if (xhci->num_port_caps > max_caps)
2073	return;
2074
2075	port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
2076
2077	if (port_cap->psi_count) {
2078	port_cap->psi = kcalloc_node(port_cap->psi_count,
2079	sizeof(*port_cap->psi),
2080	GFP_KERNEL, dev_to_node(dev));
2081	if (!port_cap->psi)
2082	port_cap->psi_count = 0;
2083
2084	port_cap->psi_uid_count++;
2085	for (i = 0; i < port_cap->psi_count; i++) {
2086	port_cap->psi[i] = readl(addr: addr + 4 + i);
2087
2088	/* count unique ID values, two consecutive entries can
2089	* have the same ID if link is assymetric
2090	*/
2091	if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) !=
2092	XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
2093	port_cap->psi_uid_count++;
2094
2095	if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
2096	major_revision == 0x03 &&
2097	XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
2098	minor_revision = tmp_minor_revision;
2099
2100	xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2101	XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
2102	XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
2103	XHCI_EXT_PORT_PLT(port_cap->psi[i]),
2104	XHCI_EXT_PORT_PFD(port_cap->psi[i]),
2105	XHCI_EXT_PORT_LP(port_cap->psi[i]),
2106	XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
2107	}
2108	}
2109
2110	rhub->maj_rev = major_revision;
2111
2112	if (rhub->min_rev < minor_revision)
2113	rhub->min_rev = minor_revision;
2114
2115	port_cap->maj_rev = major_revision;
2116	port_cap->min_rev = minor_revision;
2117	port_cap->protocol_caps = temp;
2118
2119	if ((xhci->hci_version >= 0x100) && (major_revision != 0x03) &&
2120	(temp & XHCI_HLC)) {
2121	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2122	fmt: "xHCI 1.0: support USB2 hardware lpm");
2123	xhci->hw_lpm_support = 1;
2124	}
2125
2126	port_offset--;
2127	for (i = port_offset; i < (port_offset + port_count); i++) {
2128	struct xhci_port *hw_port = &xhci->hw_ports[i];
2129	/* Duplicate entry. Ignore the port if the revisions differ. */
2130	if (hw_port->rhub) {
2131	xhci_warn(xhci, "Duplicate port entry, Ext Cap %p, port %u\n", addr, i);
2132	xhci_warn(xhci, "Port was marked as USB %u, duplicated as USB %u\n",
2133	hw_port->rhub->maj_rev, major_revision);
2134	/* Only adjust the roothub port counts if we haven't
2135	* found a similar duplicate.
2136	*/
2137	if (hw_port->rhub != rhub &&
2138	hw_port->hcd_portnum != DUPLICATE_ENTRY) {
2139	hw_port->rhub->num_ports--;
2140	hw_port->hcd_portnum = DUPLICATE_ENTRY;
2141	}
2142	continue;
2143	}
2144	hw_port->rhub = rhub;
2145	hw_port->port_cap = port_cap;
2146	rhub->num_ports++;
2147	}
2148	/* FIXME: Should we disable ports not in the Extended Capabilities? */
2149	}
2150
2151	static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2152	struct xhci_hub *rhub, gfp_t flags)
2153	{
2154	int port_index = 0;
2155	int i;
2156	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2157
2158	if (!rhub->num_ports)
2159	return;
2160	rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports),
2161	flags, dev_to_node(dev));
2162	if (!rhub->ports)
2163	return;
2164
2165	for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
2166	if (xhci->hw_ports[i].rhub != rhub ||
2167	xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
2168	continue;
2169	xhci->hw_ports[i].hcd_portnum = port_index;
2170	rhub->ports[port_index] = &xhci->hw_ports[i];
2171	port_index++;
2172	if (port_index == rhub->num_ports)
2173	break;
2174	}
2175	}
2176
2177	/*
2178	* Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2179	* specify what speeds each port is supposed to be. We can't count on the port
2180	* speed bits in the PORTSC register being correct until a device is connected,
2181	* but we need to set up the two fake roothubs with the correct number of USB
2182	* 3.0 and USB 2.0 ports at host controller initialization time.
2183	*/
2184	static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2185	{
2186	void __iomem *base;
2187	u32 offset;
2188	unsigned int num_ports;
2189	int i, j;
2190	int cap_count = 0;
2191	u32 cap_start;
2192	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2193
2194	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2195	xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports),
2196	flags, dev_to_node(dev));
2197	if (!xhci->hw_ports)
2198	return -ENOMEM;
2199
2200	for (i = 0; i < num_ports; i++) {
2201	xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base +
2202	NUM_PORT_REGS * i;
2203	xhci->hw_ports[i].hw_portnum = i;
2204
2205	init_completion(x: &xhci->hw_ports[i].rexit_done);
2206	init_completion(x: &xhci->hw_ports[i].u3exit_done);
2207	}
2208
2209	xhci->rh_bw = kcalloc_node(num_ports, sizeof(*xhci->rh_bw), flags,
2210	dev_to_node(dev));
2211	if (!xhci->rh_bw)
2212	return -ENOMEM;
2213	for (i = 0; i < num_ports; i++) {
2214	struct xhci_interval_bw_table *bw_table;
2215
2216	INIT_LIST_HEAD(list: &xhci->rh_bw[i].tts);
2217	bw_table = &xhci->rh_bw[i].bw_table;
2218	for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2219	INIT_LIST_HEAD(list: &bw_table->interval_bw[j].endpoints);
2220	}
2221	base = &xhci->cap_regs->hc_capbase;
2222
2223	cap_start = xhci_find_next_ext_cap(base, start: 0, XHCI_EXT_CAPS_PROTOCOL);
2224	if (!cap_start) {
2225	xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2226	return -ENODEV;
2227	}
2228
2229	offset = cap_start;
2230	/* count extended protocol capability entries for later caching */
2231	while (offset) {
2232	cap_count++;
2233	offset = xhci_find_next_ext_cap(base, start: offset,
2234	XHCI_EXT_CAPS_PROTOCOL);
2235	}
2236
2237	xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps),
2238	flags, dev_to_node(dev));
2239	if (!xhci->port_caps)
2240	return -ENOMEM;
2241
2242	offset = cap_start;
2243
2244	while (offset) {
2245	xhci_add_in_port(xhci, num_ports, addr: base + offset, max_caps: cap_count);
2246	if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports ==
2247	num_ports)
2248	break;
2249	offset = xhci_find_next_ext_cap(base, start: offset,
2250	XHCI_EXT_CAPS_PROTOCOL);
2251	}
2252	if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
2253	xhci_warn(xhci, "No ports on the roothubs?\n");
2254	return -ENODEV;
2255	}
2256	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2257	fmt: "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2258	xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2259
2260	/* Place limits on the number of roothub ports so that the hub
2261	* descriptors aren't longer than the USB core will allocate.
2262	*/
2263	if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2264	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2265	fmt: "Limiting USB 3.0 roothub ports to %u.",
2266	USB_SS_MAXPORTS);
2267	xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2268	}
2269	if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2270	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2271	fmt: "Limiting USB 2.0 roothub ports to %u.",
2272	USB_MAXCHILDREN);
2273	xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2274	}
2275
2276	if (!xhci->usb2_rhub.num_ports)
2277	xhci_info(xhci, "USB2 root hub has no ports\n");
2278
2279	if (!xhci->usb3_rhub.num_ports)
2280	xhci_info(xhci, "USB3 root hub has no ports\n");
2281
2282	xhci_create_rhub_port_array(xhci, rhub: &xhci->usb2_rhub, flags);
2283	xhci_create_rhub_port_array(xhci, rhub: &xhci->usb3_rhub, flags);
2284
2285	return 0;
2286	}
2287
2288	static struct xhci_interrupter *
2289	xhci_alloc_interrupter(struct xhci_hcd *xhci, unsigned int segs, gfp_t flags)
2290	{
2291	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2292	struct xhci_interrupter *ir;
2293	unsigned int max_segs;
2294	int ret;
2295
2296	if (!segs)
2297	segs = ERST_DEFAULT_SEGS;
2298
2299	max_segs = BIT(HCS_ERST_MAX(xhci->hcs_params2));
2300	segs = min(segs, max_segs);
2301
2302	ir = kzalloc_node(sizeof(*ir), flags, dev_to_node(dev));
2303	if (!ir)
2304	return NULL;
2305
2306	ir->event_ring = xhci_ring_alloc(xhci, num_segs: segs, type: TYPE_EVENT, max_packet: 0, flags);
2307	if (!ir->event_ring) {
2308	xhci_warn(xhci, "Failed to allocate interrupter event ring\n");
2309	kfree(objp: ir);
2310	return NULL;
2311	}
2312
2313	ret = xhci_alloc_erst(xhci, evt_ring: ir->event_ring, erst: &ir->erst, flags);
2314	if (ret) {
2315	xhci_warn(xhci, "Failed to allocate interrupter erst\n");
2316	xhci_ring_free(xhci, ring: ir->event_ring);
2317	kfree(objp: ir);
2318	return NULL;
2319	}
2320
2321	return ir;
2322	}
2323
2324	void xhci_add_interrupter(struct xhci_hcd *xhci, unsigned int intr_num)
2325	{
2326	struct xhci_interrupter *ir;
2327	u64 erst_base;
2328	u32 erst_size;
2329
2330	ir = xhci->interrupters[intr_num];
2331	ir->intr_num = intr_num;
2332	ir->ir_set = &xhci->run_regs->ir_set[intr_num];
2333
2334	/* set ERST count with the number of entries in the segment table */
2335	erst_size = readl(addr: &ir->ir_set->erst_size);
2336	erst_size &= ~ERST_SIZE_MASK;
2337	erst_size |= ir->event_ring->num_segs;
2338	writel(val: erst_size, addr: &ir->ir_set->erst_size);
2339
2340	erst_base = xhci_read_64(xhci, regs: &ir->ir_set->erst_base);
2341	erst_base &= ~ERST_BASE_ADDRESS_MASK;
2342	erst_base |= ir->erst.erst_dma_addr & ERST_BASE_ADDRESS_MASK;
2343	if (xhci->quirks & XHCI_WRITE_64_HI_LO)
2344	hi_lo_writeq(val: erst_base, addr: &ir->ir_set->erst_base);
2345	else
2346	xhci_write_64(xhci, val: erst_base, regs: &ir->ir_set->erst_base);
2347
2348	/* Set the event ring dequeue address of this interrupter */
2349	xhci_set_hc_event_deq(xhci, ir);
2350	}
2351
2352	struct xhci_interrupter *
2353	xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs,
2354	u32 imod_interval, unsigned int intr_num)
2355	{
2356	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2357	struct xhci_interrupter *ir;
2358	unsigned int i;
2359	int err = -ENOSPC;
2360
2361	if (!xhci->interrupters || xhci->max_interrupters <= 1 ||
2362	intr_num >= xhci->max_interrupters)
2363	return NULL;
2364
2365	ir = xhci_alloc_interrupter(xhci, segs, GFP_KERNEL);
2366	if (!ir)
2367	return NULL;
2368
2369	spin_lock_irq(lock: &xhci->lock);
2370	if (!intr_num) {
2371	/* Find available secondary interrupter, interrupter 0 is reserved for primary */
2372	for (i = 1; i < xhci->max_interrupters; i++) {
2373	if (!xhci->interrupters[i]) {
2374	xhci->interrupters[i] = ir;
2375	xhci_add_interrupter(xhci, intr_num: i);
2376	err = 0;
2377	break;
2378	}
2379	}
2380	} else {
2381	if (!xhci->interrupters[intr_num]) {
2382	xhci->interrupters[intr_num] = ir;
2383	xhci_add_interrupter(xhci, intr_num);
2384	err = 0;
2385	}
2386	}
2387	spin_unlock_irq(lock: &xhci->lock);
2388
2389	if (err) {
2390	xhci_warn(xhci, "Failed to add secondary interrupter, max interrupters %d\n",
2391	xhci->max_interrupters);
2392	xhci_free_interrupter(xhci, ir);
2393	return NULL;
2394	}
2395
2396	xhci_set_interrupter_moderation(ir, imod_interval);
2397
2398	xhci_dbg(xhci, "Add secondary interrupter %d, max interrupters %d\n",
2399	ir->intr_num, xhci->max_interrupters);
2400
2401	return ir;
2402	}
2403	EXPORT_SYMBOL_GPL(xhci_create_secondary_interrupter);
2404
2405	int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2406	{
2407	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2408	dma_addr_t dma;
2409
2410	/*
2411	* xHCI section 5.4.6 - Device Context array must be
2412	* "physically contiguous and 64-byte (cache line) aligned".
2413	*/
2414	xhci->dcbaa = dma_alloc_coherent(dev, size: sizeof(*xhci->dcbaa), dma_handle: &dma, gfp: flags);
2415	if (!xhci->dcbaa)
2416	goto fail;
2417
2418	xhci->dcbaa->dma = dma;
2419	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init,
2420	fmt: "Device context base array address = 0x%pad (DMA), %p (virt)",
2421	&xhci->dcbaa->dma, xhci->dcbaa);
2422
2423	/*
2424	* Initialize the ring segment pool. The ring must be a contiguous
2425	* structure comprised of TRBs. The TRBs must be 16 byte aligned,
2426	* however, the command ring segment needs 64-byte aligned segments
2427	* and our use of dma addresses in the trb_address_map radix tree needs
2428	* TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2429	*/
2430	if (xhci->quirks & XHCI_TRB_OVERFETCH)
2431	/* Buggy HC prefetches beyond segment bounds - allocate dummy space at the end */
2432	xhci->segment_pool = dma_pool_create(name: "xHCI ring segments", dev,
2433	TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, boundary: xhci->page_size * 2);
2434	else
2435	xhci->segment_pool = dma_pool_create(name: "xHCI ring segments", dev,
2436	TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, boundary: xhci->page_size);
2437	if (!xhci->segment_pool)
2438	goto fail;
2439
2440	/* See Table 46 and Note on Figure 55 */
2441	xhci->device_pool = dma_pool_create(name: "xHCI input/output contexts", dev, size: 2112, align: 64,
2442	boundary: xhci->page_size);
2443	if (!xhci->device_pool)
2444	goto fail;
2445
2446	/*
2447	* Linear stream context arrays don't have any boundary restrictions,
2448	* and only need to be 16-byte aligned.
2449	*/
2450	xhci->small_streams_pool = dma_pool_create(name: "xHCI 256 byte stream ctx arrays",
2451	dev, SMALL_STREAM_ARRAY_SIZE, align: 16, boundary: 0);
2452	if (!xhci->small_streams_pool)
2453	goto fail;
2454
2455	/*
2456	* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE will be
2457	* allocated with dma_alloc_coherent().
2458	*/
2459
2460	xhci->medium_streams_pool = dma_pool_create(name: "xHCI 1KB stream ctx arrays",
2461	dev, MEDIUM_STREAM_ARRAY_SIZE, align: 16, boundary: 0);
2462	if (!xhci->medium_streams_pool)
2463	goto fail;
2464
2465	/*
2466	* refer to xhci rev1_2 protocol 5.3.3 max ports is 255.
2467	* refer to xhci rev1_2 protocol 6.4.3.14 port bandwidth buffer need
2468	* to be 16-byte aligned.
2469	*/
2470	xhci->port_bw_pool = dma_pool_create(name: "xHCI 256 port bw ctx arrays",
2471	dev, GET_PORT_BW_ARRAY_SIZE, align: 16, boundary: 0);
2472	if (!xhci->port_bw_pool)
2473	goto fail;
2474
2475	/* Set up the command ring to have one segments for now. */
2476	xhci->cmd_ring = xhci_ring_alloc(xhci, num_segs: 1, type: TYPE_COMMAND, max_packet: 0, flags);
2477	if (!xhci->cmd_ring)
2478	goto fail;
2479
2480	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "Allocated command ring at %p", xhci->cmd_ring);
2481	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "First segment DMA is 0x%pad",
2482	&xhci->cmd_ring->first_seg->dma);
2483
2484	/*
2485	* Reserve one command ring TRB for disabling LPM.
2486	* Since the USB core grabs the shared usb_bus bandwidth mutex before
2487	* disabling LPM, we only need to reserve one TRB for all devices.
2488	*/
2489	xhci->cmd_ring_reserved_trbs++;
2490
2491	/* Allocate and set up primary interrupter 0 with an event ring. */
2492	xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "Allocating primary event ring");
2493	xhci->interrupters = kcalloc_node(xhci->max_interrupters, sizeof(*xhci->interrupters),
2494	flags, dev_to_node(dev));
2495	if (!xhci->interrupters)
2496	goto fail;
2497
2498	xhci->interrupters[0] = xhci_alloc_interrupter(xhci, segs: 0, flags);
2499	if (!xhci->interrupters[0])
2500	goto fail;
2501
2502	if (scratchpad_alloc(xhci, flags))
2503	goto fail;
2504
2505	if (xhci_setup_port_arrays(xhci, flags))
2506	goto fail;
2507
2508	return 0;
2509
2510	fail:
2511	xhci_halt(xhci);
2512	xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
2513	xhci_mem_cleanup(xhci);
2514	return -ENOMEM;
2515	}
2516