| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Airoha Watchdog Driver |
| 4 | * |
| 5 | * Copyright (c) 2024, AIROHA All rights reserved. |
| 6 | * |
| 7 | * Mayur Kumar <mayur.kumar@airoha.com> |
| 8 | * Christian Marangi <ansuelsmth@gmail.com> |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/bitfield.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/math.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/watchdog.h> |
| 23 | |
| 24 | /* Base address of timer and watchdog registers */ |
| 25 | #define TIMER_CTRL 0x0 |
| 26 | #define WDT_ENABLE BIT(25) |
| 27 | #define WDT_TIMER_INTERRUPT BIT(21) |
| 28 | /* Timer3 is used as Watchdog Timer */ |
| 29 | #define WDT_TIMER_ENABLE BIT(5) |
| 30 | #define WDT_TIMER_LOAD_VALUE 0x2c |
| 31 | #define WDT_TIMER_CUR_VALUE 0x30 |
| 32 | #define WDT_TIMER_VAL GENMASK(31, 0) |
| 33 | #define WDT_RELOAD 0x38 |
| 34 | #define WDT_RLD BIT(0) |
| 35 | |
| 36 | /* Airoha watchdog structure description */ |
| 37 | struct airoha_wdt_desc { |
| 38 | struct watchdog_device wdog_dev; |
| 39 | unsigned int wdt_freq; |
| 40 | void __iomem *base; |
| 41 | }; |
| 42 | |
| 43 | #define WDT_HEARTBEAT 24 |
| 44 | static int heartbeat = WDT_HEARTBEAT; |
| 45 | module_param(heartbeat, int, 0); |
| 46 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. (default=" |
| 47 | __MODULE_STRING(WDT_HEARTBEAT) ")" ); |
| 48 | |
| 49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 50 | module_param(nowayout, bool, 0); |
| 51 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
| 52 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")" ); |
| 53 | |
| 54 | static int airoha_wdt_start(struct watchdog_device *wdog_dev) |
| 55 | { |
| 56 | struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdd: wdog_dev); |
| 57 | u32 val; |
| 58 | |
| 59 | val = readl(addr: airoha_wdt->base + TIMER_CTRL); |
| 60 | val |= (WDT_TIMER_ENABLE | WDT_ENABLE | WDT_TIMER_INTERRUPT); |
| 61 | writel(val, addr: airoha_wdt->base + TIMER_CTRL); |
| 62 | val = wdog_dev->timeout * airoha_wdt->wdt_freq; |
| 63 | writel(val, addr: airoha_wdt->base + WDT_TIMER_LOAD_VALUE); |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | static int airoha_wdt_stop(struct watchdog_device *wdog_dev) |
| 69 | { |
| 70 | struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdd: wdog_dev); |
| 71 | u32 val; |
| 72 | |
| 73 | val = readl(addr: airoha_wdt->base + TIMER_CTRL); |
| 74 | val &= (~WDT_ENABLE & ~WDT_TIMER_ENABLE); |
| 75 | writel(val, addr: airoha_wdt->base + TIMER_CTRL); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static int airoha_wdt_ping(struct watchdog_device *wdog_dev) |
| 81 | { |
| 82 | struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdd: wdog_dev); |
| 83 | u32 val; |
| 84 | |
| 85 | val = readl(addr: airoha_wdt->base + WDT_RELOAD); |
| 86 | val |= WDT_RLD; |
| 87 | writel(val, addr: airoha_wdt->base + WDT_RELOAD); |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | static int airoha_wdt_set_timeout(struct watchdog_device *wdog_dev, unsigned int timeout) |
| 93 | { |
| 94 | wdog_dev->timeout = timeout; |
| 95 | |
| 96 | if (watchdog_active(wdd: wdog_dev)) { |
| 97 | airoha_wdt_stop(wdog_dev); |
| 98 | return airoha_wdt_start(wdog_dev); |
| 99 | } |
| 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | static unsigned int airoha_wdt_get_timeleft(struct watchdog_device *wdog_dev) |
| 105 | { |
| 106 | struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdd: wdog_dev); |
| 107 | u32 val; |
| 108 | |
| 109 | val = readl(addr: airoha_wdt->base + WDT_TIMER_CUR_VALUE); |
| 110 | return DIV_ROUND_UP(val, airoha_wdt->wdt_freq); |
| 111 | } |
| 112 | |
| 113 | static const struct watchdog_info airoha_wdt_info = { |
| 114 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
| 115 | .identity = "Airoha Watchdog" , |
| 116 | }; |
| 117 | |
| 118 | static const struct watchdog_ops airoha_wdt_ops = { |
| 119 | .owner = THIS_MODULE, |
| 120 | .start = airoha_wdt_start, |
| 121 | .stop = airoha_wdt_stop, |
| 122 | .ping = airoha_wdt_ping, |
| 123 | .set_timeout = airoha_wdt_set_timeout, |
| 124 | .get_timeleft = airoha_wdt_get_timeleft, |
| 125 | }; |
| 126 | |
| 127 | static int airoha_wdt_probe(struct platform_device *pdev) |
| 128 | { |
| 129 | struct airoha_wdt_desc *airoha_wdt; |
| 130 | struct watchdog_device *wdog_dev; |
| 131 | struct device *dev = &pdev->dev; |
| 132 | struct clk *bus_clk; |
| 133 | int ret; |
| 134 | |
| 135 | airoha_wdt = devm_kzalloc(dev, size: sizeof(*airoha_wdt), GFP_KERNEL); |
| 136 | if (!airoha_wdt) |
| 137 | return -ENOMEM; |
| 138 | |
| 139 | airoha_wdt->base = devm_platform_ioremap_resource(pdev, index: 0); |
| 140 | if (IS_ERR(ptr: airoha_wdt->base)) |
| 141 | return PTR_ERR(ptr: airoha_wdt->base); |
| 142 | |
| 143 | bus_clk = devm_clk_get_enabled(dev, id: "bus" ); |
| 144 | if (IS_ERR(ptr: bus_clk)) |
| 145 | return dev_err_probe(dev, err: PTR_ERR(ptr: bus_clk), |
| 146 | fmt: "failed to enable bus clock\n" ); |
| 147 | |
| 148 | /* Watchdog ticks at half the bus rate */ |
| 149 | airoha_wdt->wdt_freq = clk_get_rate(clk: bus_clk) / 2; |
| 150 | |
| 151 | /* Initialize struct watchdog device */ |
| 152 | wdog_dev = &airoha_wdt->wdog_dev; |
| 153 | wdog_dev->timeout = heartbeat; |
| 154 | wdog_dev->info = &airoha_wdt_info; |
| 155 | wdog_dev->ops = &airoha_wdt_ops; |
| 156 | /* Bus 300MHz, watchdog 150MHz, 28 seconds */ |
| 157 | wdog_dev->max_timeout = FIELD_MAX(WDT_TIMER_VAL) / airoha_wdt->wdt_freq; |
| 158 | wdog_dev->parent = dev; |
| 159 | |
| 160 | watchdog_set_drvdata(wdd: wdog_dev, data: airoha_wdt); |
| 161 | watchdog_set_nowayout(wdd: wdog_dev, nowayout); |
| 162 | watchdog_stop_on_unregister(wdd: wdog_dev); |
| 163 | |
| 164 | ret = devm_watchdog_register_device(dev, wdog_dev); |
| 165 | if (ret) |
| 166 | return ret; |
| 167 | |
| 168 | platform_set_drvdata(pdev, data: airoha_wdt); |
| 169 | return 0; |
| 170 | } |
| 171 | |
| 172 | static int airoha_wdt_suspend(struct device *dev) |
| 173 | { |
| 174 | struct airoha_wdt_desc *airoha_wdt = dev_get_drvdata(dev); |
| 175 | |
| 176 | if (watchdog_active(wdd: &airoha_wdt->wdog_dev)) |
| 177 | airoha_wdt_stop(wdog_dev: &airoha_wdt->wdog_dev); |
| 178 | |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | static int airoha_wdt_resume(struct device *dev) |
| 183 | { |
| 184 | struct airoha_wdt_desc *airoha_wdt = dev_get_drvdata(dev); |
| 185 | |
| 186 | if (watchdog_active(wdd: &airoha_wdt->wdog_dev)) { |
| 187 | airoha_wdt_start(wdog_dev: &airoha_wdt->wdog_dev); |
| 188 | airoha_wdt_ping(wdog_dev: &airoha_wdt->wdog_dev); |
| 189 | } |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | static const struct of_device_id airoha_wdt_of_match[] = { |
| 194 | { .compatible = "airoha,en7581-wdt" , }, |
| 195 | { }, |
| 196 | }; |
| 197 | |
| 198 | MODULE_DEVICE_TABLE(of, airoha_wdt_of_match); |
| 199 | |
| 200 | static DEFINE_SIMPLE_DEV_PM_OPS(airoha_wdt_pm_ops, airoha_wdt_suspend, airoha_wdt_resume); |
| 201 | |
| 202 | static struct platform_driver airoha_wdt_driver = { |
| 203 | .probe = airoha_wdt_probe, |
| 204 | .driver = { |
| 205 | .name = "airoha-wdt" , |
| 206 | .pm = pm_sleep_ptr(&airoha_wdt_pm_ops), |
| 207 | .of_match_table = airoha_wdt_of_match, |
| 208 | }, |
| 209 | }; |
| 210 | |
| 211 | module_platform_driver(airoha_wdt_driver); |
| 212 | |
| 213 | MODULE_AUTHOR("Mayur Kumar <mayur.kumar@airoha.com>" ); |
| 214 | MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>" ); |
| 215 | MODULE_DESCRIPTION("Airoha EN7581 Watchdog Driver" ); |
| 216 | MODULE_LICENSE("GPL" ); |
| 217 | |