1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016 IBM Corporation
4 *
5 * Joel Stanley <joel@jms.id.au>
6 */
7
8#include <linux/bits.h>
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/kstrtox.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/watchdog.h>
21
22static bool nowayout = WATCHDOG_NOWAYOUT;
23module_param(nowayout, bool, 0);
24MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
25 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
26struct aspeed_wdt_scu {
27 const char *compatible;
28 u32 reset_status_reg;
29 u32 wdt_reset_mask;
30 u32 wdt_reset_mask_shift;
31};
32
33struct aspeed_wdt_config {
34 u32 ext_pulse_width_mask;
35 u32 irq_shift;
36 u32 irq_mask;
37 struct aspeed_wdt_scu scu;
38 u32 num_reset_masks;
39};
40
41struct aspeed_wdt {
42 struct watchdog_device wdd;
43 void __iomem *base;
44 u32 ctrl;
45 const struct aspeed_wdt_config *cfg;
46};
47
48static const struct aspeed_wdt_config ast2400_config = {
49 .ext_pulse_width_mask = 0xff,
50 .irq_shift = 0,
51 .irq_mask = 0,
52 .scu = {
53 .compatible = "aspeed,ast2400-scu",
54 .reset_status_reg = 0x3c,
55 .wdt_reset_mask = 0x1,
56 .wdt_reset_mask_shift = 1,
57 },
58};
59
60static const struct aspeed_wdt_config ast2500_config = {
61 .ext_pulse_width_mask = 0xfffff,
62 .irq_shift = 12,
63 .irq_mask = GENMASK(31, 12),
64 .scu = {
65 .compatible = "aspeed,ast2500-scu",
66 .reset_status_reg = 0x3c,
67 .wdt_reset_mask = 0x1,
68 .wdt_reset_mask_shift = 2,
69 },
70 .num_reset_masks = 1,
71};
72
73static const struct aspeed_wdt_config ast2600_config = {
74 .ext_pulse_width_mask = 0xfffff,
75 .irq_shift = 0,
76 .irq_mask = GENMASK(31, 10),
77 .scu = {
78 .compatible = "aspeed,ast2600-scu",
79 .reset_status_reg = 0x74,
80 .wdt_reset_mask = 0xf,
81 .wdt_reset_mask_shift = 16,
82 },
83 .num_reset_masks = 2,
84};
85
86static const struct aspeed_wdt_config ast2700_config = {
87 .ext_pulse_width_mask = 0xfffff,
88 .irq_shift = 0,
89 .irq_mask = GENMASK(31, 10),
90 .scu = {
91 .compatible = "aspeed,ast2700-scu0",
92 .reset_status_reg = 0x70,
93 .wdt_reset_mask = 0xf,
94 .wdt_reset_mask_shift = 0,
95 },
96 .num_reset_masks = 5,
97};
98
99static const struct of_device_id aspeed_wdt_of_table[] = {
100 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
101 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
102 { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
103 { .compatible = "aspeed,ast2700-wdt", .data = &ast2700_config },
104 { },
105};
106MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
107
108#define WDT_STATUS 0x00
109#define WDT_RELOAD_VALUE 0x04
110#define WDT_RESTART 0x08
111#define WDT_CTRL 0x0C
112#define WDT_CTRL_BOOT_SECONDARY BIT(7)
113#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
114#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
115#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
116#define WDT_CTRL_1MHZ_CLK BIT(4)
117#define WDT_CTRL_WDT_EXT BIT(3)
118#define WDT_CTRL_WDT_INTR BIT(2)
119#define WDT_CTRL_RESET_SYSTEM BIT(1)
120#define WDT_CTRL_ENABLE BIT(0)
121#define WDT_TIMEOUT_STATUS 0x10
122#define WDT_TIMEOUT_STATUS_IRQ BIT(2)
123#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
124#define WDT_CLEAR_TIMEOUT_STATUS 0x14
125#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
126#define WDT_RESET_MASK1 0x1c
127#define WDT_RESET_MASK2 0x20
128
129/*
130 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
131 * enabled), specifically:
132 *
133 * * Pulse duration
134 * * Drive mode: push-pull vs open-drain
135 * * Polarity: Active high or active low
136 *
137 * Pulse duration configuration is available on both the AST2400 and AST2500,
138 * though the field changes between SoCs:
139 *
140 * AST2400: Bits 7:0
141 * AST2500: Bits 19:0
142 *
143 * This difference is captured in struct aspeed_wdt_config.
144 *
145 * The AST2500 exposes the drive mode and polarity options, but not in a
146 * regular fashion. For read purposes, bit 31 represents active high or low,
147 * and bit 30 represents push-pull or open-drain. With respect to write, magic
148 * values need to be written to the top byte to change the state of the drive
149 * mode and polarity bits. Any other value written to the top byte has no
150 * effect on the state of the drive mode or polarity bits. However, the pulse
151 * width value must be preserved (as desired) if written.
152 */
153#define WDT_RESET_WIDTH 0x18
154#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
155#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
156#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
157#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
158#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
159#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
160
161#define WDT_RESTART_MAGIC 0x4755
162
163/* 32 bits at 1MHz, in milliseconds */
164#define WDT_MAX_TIMEOUT_MS 4294967
165#define WDT_DEFAULT_TIMEOUT 30
166#define WDT_RATE_1MHZ 1000000
167
168static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
169{
170 return container_of(wdd, struct aspeed_wdt, wdd);
171}
172
173static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
174{
175 wdt->ctrl |= WDT_CTRL_ENABLE;
176
177 writel(val: 0, addr: wdt->base + WDT_CTRL);
178 writel(val: count, addr: wdt->base + WDT_RELOAD_VALUE);
179 writel(WDT_RESTART_MAGIC, addr: wdt->base + WDT_RESTART);
180 writel(val: wdt->ctrl, addr: wdt->base + WDT_CTRL);
181}
182
183static int aspeed_wdt_start(struct watchdog_device *wdd)
184{
185 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
186
187 aspeed_wdt_enable(wdt, count: wdd->timeout * WDT_RATE_1MHZ);
188
189 return 0;
190}
191
192static int aspeed_wdt_stop(struct watchdog_device *wdd)
193{
194 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
195
196 wdt->ctrl &= ~WDT_CTRL_ENABLE;
197 writel(val: wdt->ctrl, addr: wdt->base + WDT_CTRL);
198
199 return 0;
200}
201
202static int aspeed_wdt_ping(struct watchdog_device *wdd)
203{
204 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
205
206 writel(WDT_RESTART_MAGIC, addr: wdt->base + WDT_RESTART);
207
208 return 0;
209}
210
211static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
212 unsigned int timeout)
213{
214 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
215 u32 actual;
216
217 wdd->timeout = timeout;
218
219 actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
220
221 writel(val: actual * WDT_RATE_1MHZ, addr: wdt->base + WDT_RELOAD_VALUE);
222 writel(WDT_RESTART_MAGIC, addr: wdt->base + WDT_RESTART);
223
224 return 0;
225}
226
227static int aspeed_wdt_set_pretimeout(struct watchdog_device *wdd,
228 unsigned int pretimeout)
229{
230 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
231 u32 actual = pretimeout * WDT_RATE_1MHZ;
232 u32 s = wdt->cfg->irq_shift;
233 u32 m = wdt->cfg->irq_mask;
234
235 wdd->pretimeout = pretimeout;
236 wdt->ctrl &= ~m;
237 if (pretimeout)
238 wdt->ctrl |= ((actual << s) & m) | WDT_CTRL_WDT_INTR;
239 else
240 wdt->ctrl &= ~WDT_CTRL_WDT_INTR;
241
242 writel(val: wdt->ctrl, addr: wdt->base + WDT_CTRL);
243
244 return 0;
245}
246
247static int aspeed_wdt_restart(struct watchdog_device *wdd,
248 unsigned long action, void *data)
249{
250 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
251
252 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
253 aspeed_wdt_enable(wdt, count: 128 * WDT_RATE_1MHZ / 1000);
254
255 mdelay(1000);
256
257 return 0;
258}
259
260static void aspeed_wdt_update_bootstatus(struct platform_device *pdev,
261 struct aspeed_wdt *wdt)
262{
263 const struct resource *res;
264 struct aspeed_wdt_scu scu = wdt->cfg->scu;
265 struct regmap *scu_base;
266 u32 reset_mask_width;
267 u32 reset_mask_shift;
268 u32 idx = 0;
269 u32 status;
270 int ret;
271
272 if (!of_device_is_compatible(device: pdev->dev.of_node, "aspeed,ast2400-wdt")) {
273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
274 idx = ((intptr_t)wdt->base & 0x00000fff) / (uintptr_t)resource_size(res);
275 }
276
277 scu_base = syscon_regmap_lookup_by_compatible(s: scu.compatible);
278 if (IS_ERR(ptr: scu_base)) {
279 wdt->wdd.bootstatus = WDIOS_UNKNOWN;
280 return;
281 }
282
283 ret = regmap_read(map: scu_base, reg: scu.reset_status_reg, val: &status);
284 if (ret) {
285 wdt->wdd.bootstatus = WDIOS_UNKNOWN;
286 return;
287 }
288
289 reset_mask_width = hweight32(scu.wdt_reset_mask);
290 reset_mask_shift = scu.wdt_reset_mask_shift +
291 reset_mask_width * idx;
292
293 if (status & (scu.wdt_reset_mask << reset_mask_shift))
294 wdt->wdd.bootstatus = WDIOF_CARDRESET;
295
296 /* clear wdt reset event flag */
297 if (of_device_is_compatible(device: pdev->dev.of_node, "aspeed,ast2400-wdt") ||
298 of_device_is_compatible(device: pdev->dev.of_node, "aspeed,ast2500-wdt")) {
299 ret = regmap_read(map: scu_base, reg: scu.reset_status_reg, val: &status);
300 if (!ret) {
301 status &= ~(scu.wdt_reset_mask << reset_mask_shift);
302 regmap_write(map: scu_base, reg: scu.reset_status_reg, val: status);
303 }
304 } else {
305 regmap_write(map: scu_base, reg: scu.reset_status_reg,
306 val: scu.wdt_reset_mask << reset_mask_shift);
307 }
308}
309
310/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
311static ssize_t access_cs0_show(struct device *dev,
312 struct device_attribute *attr, char *buf)
313{
314 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
315 u32 status = readl(addr: wdt->base + WDT_TIMEOUT_STATUS);
316
317 return sysfs_emit(buf, fmt: "%u\n",
318 !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
319}
320
321static ssize_t access_cs0_store(struct device *dev,
322 struct device_attribute *attr, const char *buf,
323 size_t size)
324{
325 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
326 unsigned long val;
327
328 if (kstrtoul(s: buf, base: 10, res: &val))
329 return -EINVAL;
330
331 if (val)
332 writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
333 addr: wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
334
335 return size;
336}
337
338/*
339 * This attribute exists only if the system has booted from the alternate
340 * flash with 'alt-boot' option.
341 *
342 * At alternate flash the 'access_cs0' sysfs node provides:
343 * ast2400: a way to get access to the primary SPI flash chip at CS0
344 * after booting from the alternate chip at CS1.
345 * ast2500: a way to restore the normal address mapping from
346 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
347 *
348 * Clearing the boot code selection and timeout counter also resets to the
349 * initial state the chip select line mapping. When the SoC is in normal
350 * mapping state (i.e. booted from CS0), clearing those bits does nothing for
351 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
352 * wdt2 expiration) the behavior differs as described above.
353 *
354 * This option can be used with wdt2 (watchdog1) only.
355 */
356static DEVICE_ATTR_RW(access_cs0);
357
358static struct attribute *bswitch_attrs[] = {
359 &dev_attr_access_cs0.attr,
360 NULL
361};
362ATTRIBUTE_GROUPS(bswitch);
363
364static const struct watchdog_ops aspeed_wdt_ops = {
365 .start = aspeed_wdt_start,
366 .stop = aspeed_wdt_stop,
367 .ping = aspeed_wdt_ping,
368 .set_timeout = aspeed_wdt_set_timeout,
369 .set_pretimeout = aspeed_wdt_set_pretimeout,
370 .restart = aspeed_wdt_restart,
371 .owner = THIS_MODULE,
372};
373
374static const struct watchdog_info aspeed_wdt_info = {
375 .options = WDIOF_KEEPALIVEPING
376 | WDIOF_MAGICCLOSE
377 | WDIOF_SETTIMEOUT,
378 .identity = KBUILD_MODNAME,
379};
380
381static const struct watchdog_info aspeed_wdt_pretimeout_info = {
382 .options = WDIOF_KEEPALIVEPING
383 | WDIOF_PRETIMEOUT
384 | WDIOF_MAGICCLOSE
385 | WDIOF_SETTIMEOUT,
386 .identity = KBUILD_MODNAME,
387};
388
389static irqreturn_t aspeed_wdt_irq(int irq, void *arg)
390{
391 struct watchdog_device *wdd = arg;
392 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
393 u32 status = readl(addr: wdt->base + WDT_TIMEOUT_STATUS);
394
395 if (status & WDT_TIMEOUT_STATUS_IRQ)
396 watchdog_notify_pretimeout(wdd);
397
398 return IRQ_HANDLED;
399}
400
401static int aspeed_wdt_probe(struct platform_device *pdev)
402{
403 struct device *dev = &pdev->dev;
404 const struct of_device_id *ofdid;
405 struct aspeed_wdt *wdt;
406 struct device_node *np;
407 const char *reset_type;
408 u32 duration;
409 u32 status;
410 int ret;
411
412 wdt = devm_kzalloc(dev, size: sizeof(*wdt), GFP_KERNEL);
413 if (!wdt)
414 return -ENOMEM;
415
416 np = dev->of_node;
417
418 ofdid = of_match_node(matches: aspeed_wdt_of_table, node: np);
419 if (!ofdid)
420 return -EINVAL;
421 wdt->cfg = ofdid->data;
422
423 wdt->base = devm_platform_ioremap_resource(pdev, index: 0);
424 if (IS_ERR(ptr: wdt->base))
425 return PTR_ERR(ptr: wdt->base);
426
427 wdt->wdd.info = &aspeed_wdt_info;
428
429 if (wdt->cfg->irq_mask) {
430 int irq = platform_get_irq_optional(pdev, 0);
431
432 if (irq > 0) {
433 ret = devm_request_irq(dev, irq, handler: aspeed_wdt_irq,
434 IRQF_SHARED, devname: dev_name(dev),
435 dev_id: wdt);
436 if (ret)
437 return ret;
438
439 wdt->wdd.info = &aspeed_wdt_pretimeout_info;
440 }
441 }
442
443 wdt->wdd.ops = &aspeed_wdt_ops;
444 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
445 wdt->wdd.parent = dev;
446
447 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
448 watchdog_init_timeout(wdd: &wdt->wdd, timeout_parm: 0, dev);
449
450 watchdog_set_nowayout(wdd: &wdt->wdd, nowayout);
451
452 /*
453 * On clock rates:
454 * - ast2400 wdt can run at PCLK, or 1MHz
455 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1
456 * - ast2600 always runs at 1MHz
457 *
458 * Set the ast2400 to run at 1MHz as it simplifies the driver.
459 */
460 if (of_device_is_compatible(device: np, "aspeed,ast2400-wdt"))
461 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
462
463 /*
464 * Control reset on a per-device basis to ensure the
465 * host is not affected by a BMC reboot
466 */
467 ret = of_property_read_string(np, propname: "aspeed,reset-type", out_string: &reset_type);
468 if (ret) {
469 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
470 } else {
471 if (!strcmp(reset_type, "cpu"))
472 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
473 WDT_CTRL_RESET_SYSTEM;
474 else if (!strcmp(reset_type, "soc"))
475 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
476 WDT_CTRL_RESET_SYSTEM;
477 else if (!strcmp(reset_type, "system"))
478 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
479 WDT_CTRL_RESET_SYSTEM;
480 else if (strcmp(reset_type, "none"))
481 return -EINVAL;
482 }
483 if (of_property_read_bool(np, propname: "aspeed,external-signal"))
484 wdt->ctrl |= WDT_CTRL_WDT_EXT;
485 if (of_property_read_bool(np, propname: "aspeed,alt-boot"))
486 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
487
488 if (readl(addr: wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
489 /*
490 * The watchdog is running, but invoke aspeed_wdt_start() to
491 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
492 * configuration conforms to the driver's expectations.
493 * Primarily, ensure we're using the 1MHz clock source.
494 */
495 aspeed_wdt_start(wdd: &wdt->wdd);
496 set_bit(WDOG_HW_RUNNING, addr: &wdt->wdd.status);
497 }
498
499 if (!of_device_is_compatible(device: np, "aspeed,ast2400-wdt")) {
500 u32 reset_mask[5];
501 size_t nrstmask = wdt->cfg->num_reset_masks;
502 u32 reg = readl(addr: wdt->base + WDT_RESET_WIDTH);
503 int i;
504
505 reg &= wdt->cfg->ext_pulse_width_mask;
506 if (of_property_read_bool(np, propname: "aspeed,ext-active-high"))
507 reg |= WDT_ACTIVE_HIGH_MAGIC;
508 else
509 reg |= WDT_ACTIVE_LOW_MAGIC;
510
511 writel(val: reg, addr: wdt->base + WDT_RESET_WIDTH);
512
513 reg &= wdt->cfg->ext_pulse_width_mask;
514 if (of_property_read_bool(np, propname: "aspeed,ext-push-pull"))
515 reg |= WDT_PUSH_PULL_MAGIC;
516 else
517 reg |= WDT_OPEN_DRAIN_MAGIC;
518
519 writel(val: reg, addr: wdt->base + WDT_RESET_WIDTH);
520
521 ret = of_property_read_u32_array(np, propname: "aspeed,reset-mask", out_values: reset_mask, sz: nrstmask);
522 if (!ret) {
523 for (i = 0; i < nrstmask; i++)
524 writel(val: reset_mask[i], addr: wdt->base + WDT_RESET_MASK1 + i * 4);
525 }
526 }
527
528 if (!of_property_read_u32(np, propname: "aspeed,ext-pulse-duration", out_value: &duration)) {
529 u32 max_duration = wdt->cfg->ext_pulse_width_mask + 1;
530
531 if (duration == 0 || duration > max_duration) {
532 dev_err(dev, "Invalid pulse duration: %uus\n",
533 duration);
534 duration = max(1U, min(max_duration, duration));
535 dev_info(dev, "Pulse duration set to %uus\n",
536 duration);
537 }
538
539 /*
540 * The watchdog is always configured with a 1MHz source, so
541 * there is no need to scale the microsecond value. However we
542 * need to offset it - from the datasheet:
543 *
544 * "This register decides the asserting duration of wdt_ext and
545 * wdt_rstarm signal. The default value is 0xFF. It means the
546 * default asserting duration of wdt_ext and wdt_rstarm is
547 * 256us."
548 *
549 * This implies a value of 0 gives a 1us pulse.
550 */
551 writel(val: duration - 1, addr: wdt->base + WDT_RESET_WIDTH);
552 }
553
554 aspeed_wdt_update_bootstatus(pdev, wdt);
555
556 status = readl(addr: wdt->base + WDT_TIMEOUT_STATUS);
557 if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
558 if (of_device_is_compatible(device: np, "aspeed,ast2400-wdt") ||
559 of_device_is_compatible(device: np, "aspeed,ast2500-wdt"))
560 wdt->wdd.groups = bswitch_groups;
561 }
562
563 dev_set_drvdata(dev, data: wdt);
564
565 return devm_watchdog_register_device(dev, &wdt->wdd);
566}
567
568static struct platform_driver aspeed_watchdog_driver = {
569 .probe = aspeed_wdt_probe,
570 .driver = {
571 .name = KBUILD_MODNAME,
572 .of_match_table = aspeed_wdt_of_table,
573 },
574};
575
576static int __init aspeed_wdt_init(void)
577{
578 return platform_driver_register(&aspeed_watchdog_driver);
579}
580arch_initcall(aspeed_wdt_init);
581
582static void __exit aspeed_wdt_exit(void)
583{
584 platform_driver_unregister(&aspeed_watchdog_driver);
585}
586module_exit(aspeed_wdt_exit);
587
588MODULE_DESCRIPTION("Aspeed Watchdog Driver");
589MODULE_LICENSE("GPL");
590

source code of linux/drivers/watchdog/aspeed_wdt.c