1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SBSA(Server Base System Architecture) Generic Watchdog driver
4 *
5 * Copyright (c) 2015, Linaro Ltd.
6 * Author: Fu Wei <fu.wei@linaro.org>
7 * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
8 * Al Stone <al.stone@linaro.org>
9 * Timur Tabi <timur@codeaurora.org>
10 *
11 * ARM SBSA Generic Watchdog has two stage timeouts:
12 * the first signal (WS0) is for alerting the system by interrupt,
13 * the second one (WS1) is a real hardware reset.
14 * More details about the hardware specification of this device:
15 * ARM DEN0029B - Server Base System Architecture (SBSA)
16 *
17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
18 * or a two stages watchdog, it's set up by the module parameter "action".
19 * In the single stage mode, when the timeout is reached, your system
20 * will be reset by WS1. The first signal (WS0) is ignored.
21 * In the two stages mode, when the timeout is reached, the first signal (WS0)
22 * will trigger panic. If the system is getting into trouble and cannot be reset
23 * by panic or restart properly by the kdump kernel(if supported), then the
24 * second stage (as long as the first stage) will be reached, system will be
25 * reset by WS1. This function can help administrator to backup the system
26 * context info by panic console output or kdump.
27 *
28 * SBSA GWDT:
29 * if action is 1 (the two stages mode):
30 * |--------WOR-------WS0--------WOR-------WS1
31 * |----timeout-----(panic)----timeout-----reset
32 *
33 * if action is 0 (the single stage mode):
34 * |------WOR-----WS0(ignored)-----WOR------WS1
35 * |--------------timeout-------------------reset
36 *
37 * Note: Since this watchdog timer has two stages, and each stage is determined
38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
39 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode
40 * is half of that in the single stage mode.
41 */
42
43#include <linux/io.h>
44#include <linux/io-64-nonatomic-lo-hi.h>
45#include <linux/interrupt.h>
46#include <linux/mod_devicetable.h>
47#include <linux/module.h>
48#include <linux/moduleparam.h>
49#include <linux/platform_device.h>
50#include <linux/uaccess.h>
51#include <linux/watchdog.h>
52#include <asm/arch_timer.h>
53
54#define DRV_NAME "sbsa-gwdt"
55#define WATCHDOG_NAME "SBSA Generic Watchdog"
56
57/* SBSA Generic Watchdog register definitions */
58/* refresh frame */
59#define SBSA_GWDT_WRR 0x000
60
61/* control frame */
62#define SBSA_GWDT_WCS 0x000
63#define SBSA_GWDT_WOR 0x008
64#define SBSA_GWDT_WCV 0x010
65
66/* refresh/control frame */
67#define SBSA_GWDT_W_IIDR 0xfcc
68#define SBSA_GWDT_IDR 0xfd0
69
70/* Watchdog Control and Status Register */
71#define SBSA_GWDT_WCS_EN BIT(0)
72#define SBSA_GWDT_WCS_WS0 BIT(1)
73#define SBSA_GWDT_WCS_WS1 BIT(2)
74
75#define SBSA_GWDT_VERSION_MASK 0xF
76#define SBSA_GWDT_VERSION_SHIFT 16
77
78#define SBSA_GWDT_IMPL_MASK 0x7FF
79#define SBSA_GWDT_IMPL_SHIFT 0
80#define SBSA_GWDT_IMPL_MEDIATEK 0x426
81
82/**
83 * struct sbsa_gwdt - Internal representation of the SBSA GWDT
84 * @wdd: kernel watchdog_device structure
85 * @clk: store the System Counter clock frequency, in Hz.
86 * @version: store the architecture version
87 * @need_ws0_race_workaround:
88 * indicate whether to adjust wdd->timeout to avoid a race with WS0
89 * @refresh_base: Virtual address of the watchdog refresh frame
90 * @control_base: Virtual address of the watchdog control frame
91 */
92struct sbsa_gwdt {
93 struct watchdog_device wdd;
94 u32 clk;
95 int version;
96 bool need_ws0_race_workaround;
97 void __iomem *refresh_base;
98 void __iomem *control_base;
99};
100
101#define DEFAULT_TIMEOUT 10 /* seconds */
102
103static unsigned int timeout;
104module_param(timeout, uint, 0);
105MODULE_PARM_DESC(timeout,
106 "Watchdog timeout in seconds. (>=0, default="
107 __MODULE_STRING(DEFAULT_TIMEOUT) ")");
108
109/*
110 * action refers to action taken when watchdog gets WS0
111 * 0 = skip
112 * 1 = panic
113 * defaults to skip (0)
114 */
115static int action;
116module_param(action, int, 0);
117MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
118 "0 = skip(*) 1 = panic");
119
120static bool nowayout = WATCHDOG_NOWAYOUT;
121module_param(nowayout, bool, S_IRUGO);
122MODULE_PARM_DESC(nowayout,
123 "Watchdog cannot be stopped once started (default="
124 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
125
126/*
127 * Arm Base System Architecture 1.0 introduces watchdog v1 which
128 * increases the length watchdog offset register to 48 bits.
129 * - For version 0: WOR is 32 bits;
130 * - For version 1: WOR is 48 bits which comprises the register
131 * offset 0x8 and 0xC, and the bits [63:48] are reserved which are
132 * Read-As-Zero and Writes-Ignored.
133 */
134static u64 sbsa_gwdt_reg_read(struct sbsa_gwdt *gwdt)
135{
136 if (gwdt->version == 0)
137 return readl(addr: gwdt->control_base + SBSA_GWDT_WOR);
138 else
139 return lo_hi_readq(addr: gwdt->control_base + SBSA_GWDT_WOR);
140}
141
142static void sbsa_gwdt_reg_write(u64 val, struct sbsa_gwdt *gwdt)
143{
144 if (gwdt->version == 0)
145 writel(val: (u32)val, addr: gwdt->control_base + SBSA_GWDT_WOR);
146 else
147 lo_hi_writeq(val, addr: gwdt->control_base + SBSA_GWDT_WOR);
148}
149
150/*
151 * watchdog operation functions
152 */
153static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
154 unsigned int timeout)
155{
156 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
157
158 wdd->timeout = timeout;
159 timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000);
160
161 if (action)
162 sbsa_gwdt_reg_write(val: (u64)gwdt->clk * timeout, gwdt);
163 else
164 /*
165 * In the single stage mode, The first signal (WS0) is ignored,
166 * the timeout is (WOR * 2), so the WOR should be configured
167 * to half value of timeout.
168 */
169 sbsa_gwdt_reg_write(val: ((u64)gwdt->clk / 2) * timeout, gwdt);
170
171 /*
172 * Some watchdog hardware has a race condition where it will ignore
173 * sbsa_gwdt_keepalive() if it is called at the exact moment that a
174 * timeout occurs and WS0 is being asserted. Unfortunately, the default
175 * behavior of the watchdog core is very likely to trigger this race
176 * when action=0 because it programs WOR to be half of the desired
177 * timeout, and watchdog_next_keepalive() chooses the exact same time to
178 * send keepalive pings.
179 *
180 * This triggers a race where sbsa_gwdt_keepalive() can be called right
181 * as WS0 is being asserted, and affected hardware will ignore that
182 * write and continue to assert WS0. After another (timeout / 2)
183 * seconds, the same race happens again. If the driver wins then the
184 * explicit refresh will reset WS0 to false but if the hardware wins,
185 * then WS1 is asserted and the system resets.
186 *
187 * Avoid the problem by scheduling keepalive heartbeats one second later
188 * than the WOR timeout.
189 *
190 * This workaround might not be needed in a future revision of the
191 * hardware.
192 */
193 if (gwdt->need_ws0_race_workaround)
194 wdd->min_hw_heartbeat_ms = timeout * 500 + 1000;
195
196 return 0;
197}
198
199static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
200{
201 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
202 u64 timeleft = 0;
203
204 /*
205 * In the single stage mode, if WS0 is deasserted
206 * (watchdog is in the first stage),
207 * timeleft = WOR + (WCV - system counter)
208 */
209 if (!action &&
210 !(readl(addr: gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
211 timeleft += sbsa_gwdt_reg_read(gwdt);
212
213 timeleft += lo_hi_readq(addr: gwdt->control_base + SBSA_GWDT_WCV) -
214 arch_timer_read_counter();
215
216 do_div(timeleft, gwdt->clk);
217
218 return timeleft;
219}
220
221static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
222{
223 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
224
225 /*
226 * Writing WRR for an explicit watchdog refresh.
227 * You can write anyting (like 0).
228 */
229 writel(val: 0, addr: gwdt->refresh_base + SBSA_GWDT_WRR);
230
231 return 0;
232}
233
234static void sbsa_gwdt_get_version(struct watchdog_device *wdd)
235{
236 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
237 int iidr, ver, impl;
238
239 iidr = readl(addr: gwdt->control_base + SBSA_GWDT_W_IIDR);
240 ver = (iidr >> SBSA_GWDT_VERSION_SHIFT) & SBSA_GWDT_VERSION_MASK;
241 impl = (iidr >> SBSA_GWDT_IMPL_SHIFT) & SBSA_GWDT_IMPL_MASK;
242
243 gwdt->version = ver;
244 gwdt->need_ws0_race_workaround =
245 !action && (impl == SBSA_GWDT_IMPL_MEDIATEK);
246}
247
248static int sbsa_gwdt_start(struct watchdog_device *wdd)
249{
250 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
251
252 /* writing WCS will cause an explicit watchdog refresh */
253 writel(SBSA_GWDT_WCS_EN, addr: gwdt->control_base + SBSA_GWDT_WCS);
254
255 return 0;
256}
257
258static int sbsa_gwdt_stop(struct watchdog_device *wdd)
259{
260 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
261
262 /* Simply write 0 to WCS to clean WCS_EN bit */
263 writel(val: 0, addr: gwdt->control_base + SBSA_GWDT_WCS);
264
265 return 0;
266}
267
268static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
269{
270 panic(WATCHDOG_NAME " timeout");
271
272 return IRQ_HANDLED;
273}
274
275static const struct watchdog_info sbsa_gwdt_info = {
276 .identity = WATCHDOG_NAME,
277 .options = WDIOF_SETTIMEOUT |
278 WDIOF_KEEPALIVEPING |
279 WDIOF_MAGICCLOSE |
280 WDIOF_CARDRESET,
281};
282
283static const struct watchdog_ops sbsa_gwdt_ops = {
284 .owner = THIS_MODULE,
285 .start = sbsa_gwdt_start,
286 .stop = sbsa_gwdt_stop,
287 .ping = sbsa_gwdt_keepalive,
288 .set_timeout = sbsa_gwdt_set_timeout,
289 .get_timeleft = sbsa_gwdt_get_timeleft,
290};
291
292static int sbsa_gwdt_probe(struct platform_device *pdev)
293{
294 void __iomem *rf_base, *cf_base;
295 struct device *dev = &pdev->dev;
296 struct watchdog_device *wdd;
297 struct sbsa_gwdt *gwdt;
298 int ret, irq;
299 u32 status;
300
301 gwdt = devm_kzalloc(dev, size: sizeof(*gwdt), GFP_KERNEL);
302 if (!gwdt)
303 return -ENOMEM;
304 platform_set_drvdata(pdev, data: gwdt);
305
306 cf_base = devm_platform_ioremap_resource(pdev, index: 0);
307 if (IS_ERR(ptr: cf_base))
308 return PTR_ERR(ptr: cf_base);
309
310 rf_base = devm_platform_ioremap_resource(pdev, index: 1);
311 if (IS_ERR(ptr: rf_base))
312 return PTR_ERR(ptr: rf_base);
313
314 /*
315 * Get the frequency of system counter from the cp15 interface of ARM
316 * Generic timer. We don't need to check it, because if it returns "0",
317 * system would panic in very early stage.
318 */
319 gwdt->clk = arch_timer_get_cntfrq();
320 gwdt->refresh_base = rf_base;
321 gwdt->control_base = cf_base;
322
323 wdd = &gwdt->wdd;
324 wdd->parent = dev;
325 wdd->info = &sbsa_gwdt_info;
326 wdd->ops = &sbsa_gwdt_ops;
327 wdd->min_timeout = 1;
328 wdd->timeout = DEFAULT_TIMEOUT;
329 watchdog_set_drvdata(wdd, data: gwdt);
330 watchdog_set_nowayout(wdd, nowayout);
331 sbsa_gwdt_get_version(wdd);
332 if (gwdt->version == 0)
333 wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
334 else
335 wdd->max_hw_heartbeat_ms = GENMASK_ULL(47, 0) / gwdt->clk * 1000;
336
337 if (gwdt->need_ws0_race_workaround) {
338 /*
339 * A timeout of 3 seconds means that WOR will be set to 1.5
340 * seconds and the heartbeat will be scheduled every 2.5
341 * seconds.
342 */
343 wdd->min_timeout = 3;
344 }
345
346 status = readl(addr: cf_base + SBSA_GWDT_WCS);
347 if (status & SBSA_GWDT_WCS_WS1) {
348 dev_warn(dev, "System reset by WDT.\n");
349 wdd->bootstatus |= WDIOF_CARDRESET;
350 }
351 if (status & SBSA_GWDT_WCS_EN)
352 set_bit(WDOG_HW_RUNNING, addr: &wdd->status);
353
354 if (action) {
355 irq = platform_get_irq(pdev, 0);
356 if (irq < 0) {
357 action = 0;
358 dev_warn(dev, "unable to get ws0 interrupt.\n");
359 } else {
360 /*
361 * In case there is a pending ws0 interrupt, just ping
362 * the watchdog before registering the interrupt routine
363 */
364 writel(val: 0, addr: rf_base + SBSA_GWDT_WRR);
365 if (devm_request_irq(dev, irq, handler: sbsa_gwdt_interrupt, irqflags: 0,
366 devname: pdev->name, dev_id: gwdt)) {
367 action = 0;
368 dev_warn(dev, "unable to request IRQ %d.\n",
369 irq);
370 }
371 }
372 if (!action)
373 dev_warn(dev, "falling back to single stage mode.\n");
374 }
375 /*
376 * In the single stage mode, The first signal (WS0) is ignored,
377 * the timeout is (WOR * 2), so the maximum timeout should be doubled.
378 */
379 if (!action)
380 wdd->max_hw_heartbeat_ms *= 2;
381
382 watchdog_init_timeout(wdd, timeout_parm: timeout, dev);
383 /*
384 * Update timeout to WOR.
385 * Because of the explicit watchdog refresh mechanism,
386 * it's also a ping, if watchdog is enabled.
387 */
388 sbsa_gwdt_set_timeout(wdd, timeout: wdd->timeout);
389
390 watchdog_stop_on_reboot(wdd);
391 ret = devm_watchdog_register_device(dev, wdd);
392 if (ret)
393 return ret;
394
395 dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
396 wdd->timeout, gwdt->clk, action,
397 status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
398
399 return 0;
400}
401
402/* Disable watchdog if it is active during suspend */
403static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
404{
405 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
406
407 if (watchdog_hw_running(wdd: &gwdt->wdd))
408 sbsa_gwdt_stop(wdd: &gwdt->wdd);
409
410 return 0;
411}
412
413/* Enable watchdog if necessary */
414static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
415{
416 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
417
418 if (watchdog_hw_running(wdd: &gwdt->wdd))
419 sbsa_gwdt_start(wdd: &gwdt->wdd);
420
421 return 0;
422}
423
424static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
425 SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
426};
427
428static const struct of_device_id sbsa_gwdt_of_match[] = {
429 { .compatible = "arm,sbsa-gwdt", },
430 {},
431};
432MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
433
434static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
435 { .name = DRV_NAME, },
436 {},
437};
438MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
439
440static struct platform_driver sbsa_gwdt_driver = {
441 .driver = {
442 .name = DRV_NAME,
443 .pm = &sbsa_gwdt_pm_ops,
444 .of_match_table = sbsa_gwdt_of_match,
445 },
446 .probe = sbsa_gwdt_probe,
447 .id_table = sbsa_gwdt_pdev_match,
448};
449
450module_platform_driver(sbsa_gwdt_driver);
451
452MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
453MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
454MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
455MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
456MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
457MODULE_LICENSE("GPL v2");
458

source code of linux/drivers/watchdog/sbsa_gwdt.c