1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | #ifndef __SOUND_ICE1712_H |
3 | #define __SOUND_ICE1712_H |
4 | |
5 | /* |
6 | * ALSA driver for ICEnsemble ICE1712 (Envy24) |
7 | * |
8 | * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> |
9 | */ |
10 | |
11 | #include <linux/io.h> |
12 | #include <sound/control.h> |
13 | #include <sound/ac97_codec.h> |
14 | #include <sound/rawmidi.h> |
15 | #include <sound/i2c.h> |
16 | #include <sound/ak4xxx-adda.h> |
17 | #include <sound/ak4114.h> |
18 | #include <sound/pt2258.h> |
19 | #include <sound/pcm.h> |
20 | #include <sound/mpu401.h> |
21 | |
22 | |
23 | /* |
24 | * Direct registers |
25 | */ |
26 | |
27 | #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x) |
28 | |
29 | #define ICE1712_REG_CONTROL 0x00 /* byte */ |
30 | #define ICE1712_RESET 0x80 /* soft reset whole chip */ |
31 | #define ICE1712_SERR_ASSERT_DS_DMA 0x40 /* disabled SERR# assertion for the DS DMA Ch-C irq otherwise enabled */ |
32 | #define ICE1712_DOS_VOL 0x10 /* DOS WT/FM volume control */ |
33 | #define ICE1712_SERR_LEVEL 0x08 /* SERR# level otherwise edge */ |
34 | #define ICE1712_SERR_ASSERT_SB 0x02 /* disabled SERR# assertion for SB irq otherwise enabled */ |
35 | #define ICE1712_NATIVE 0x01 /* native mode otherwise SB */ |
36 | #define ICE1712_REG_IRQMASK 0x01 /* byte */ |
37 | #define ICE1712_IRQ_MPU1 0x80 /* MIDI irq mask */ |
38 | #define ICE1712_IRQ_TIMER 0x40 /* Timer mask */ |
39 | #define ICE1712_IRQ_MPU2 0x20 /* Secondary MIDI irq mask */ |
40 | #define ICE1712_IRQ_PROPCM 0x10 /* professional multi-track */ |
41 | #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */ |
42 | #define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */ |
43 | #define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */ |
44 | #define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */ |
45 | #define ICE1712_REG_IRQSTAT 0x02 /* byte */ |
46 | /* look to ICE1712_IRQ_* */ |
47 | #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */ |
48 | #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */ |
49 | #define ICE1712_REG_NMI_STAT1 0x05 /* byte */ |
50 | #define ICE1712_REG_NMI_DATA 0x06 /* byte */ |
51 | #define ICE1712_REG_NMI_INDEX 0x07 /* byte */ |
52 | #define ICE1712_REG_AC97_INDEX 0x08 /* byte */ |
53 | #define ICE1712_REG_AC97_CMD 0x09 /* byte */ |
54 | #define ICE1712_AC97_COLD 0x80 /* cold reset */ |
55 | #define ICE1712_AC97_WARM 0x40 /* warm reset */ |
56 | #define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */ |
57 | #define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */ |
58 | #define ICE1712_AC97_READY 0x08 /* codec ready status bit */ |
59 | #define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */ |
60 | #define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */ |
61 | #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */ |
62 | #define ICE1712_REG_MPU1_CTRL 0x0c /* byte */ |
63 | #define ICE1712_REG_MPU1_DATA 0x0d /* byte */ |
64 | #define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */ |
65 | #define ICE1712_I2C_WRITE 0x01 /* write direction */ |
66 | #define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */ |
67 | #define ICE1712_REG_I2C_DATA 0x12 /* byte */ |
68 | #define ICE1712_REG_I2C_CTRL 0x13 /* byte */ |
69 | #define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */ |
70 | #define ICE1712_I2C_BUSY 0x01 /* busy bit */ |
71 | #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */ |
72 | #define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */ |
73 | #define ICE1712_REG_SERR_SHADOW 0x1b /* byte */ |
74 | #define ICE1712_REG_MPU2_CTRL 0x1c /* byte */ |
75 | #define ICE1712_REG_MPU2_DATA 0x1d /* byte */ |
76 | #define ICE1712_REG_TIMER 0x1e /* word */ |
77 | |
78 | /* |
79 | * Indirect registers |
80 | */ |
81 | |
82 | #define ICE1712_IREG_PBK_COUNT_LO 0x00 |
83 | #define ICE1712_IREG_PBK_COUNT_HI 0x01 |
84 | #define ICE1712_IREG_PBK_CTRL 0x02 |
85 | #define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */ |
86 | #define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */ |
87 | #define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */ |
88 | #define ICE1712_IREG_PBK_RATE_LO 0x06 |
89 | #define ICE1712_IREG_PBK_RATE_MID 0x07 |
90 | #define ICE1712_IREG_PBK_RATE_HI 0x08 |
91 | #define ICE1712_IREG_CAP_COUNT_LO 0x10 |
92 | #define ICE1712_IREG_CAP_COUNT_HI 0x11 |
93 | #define ICE1712_IREG_CAP_CTRL 0x12 |
94 | #define ICE1712_IREG_GPIO_DATA 0x20 |
95 | #define ICE1712_IREG_GPIO_WRITE_MASK 0x21 |
96 | #define ICE1712_IREG_GPIO_DIRECTION 0x22 |
97 | #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30 |
98 | #define ICE1712_IREG_PRO_POWERDOWN 0x31 |
99 | |
100 | /* |
101 | * Consumer section direct DMA registers |
102 | */ |
103 | |
104 | #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x) |
105 | |
106 | #define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */ |
107 | #define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */ |
108 | #define ICE1712_DS_DATA 0x04 /* dword - channel data */ |
109 | #define ICE1712_DS_INDEX 0x08 /* dword - channel index */ |
110 | |
111 | /* |
112 | * Consumer section channel registers |
113 | */ |
114 | |
115 | #define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */ |
116 | #define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */ |
117 | #define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */ |
118 | #define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */ |
119 | #define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */ |
120 | #define ICE1712_BUFFER1 0x80 /* buffer1 is active */ |
121 | #define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */ |
122 | #define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */ |
123 | #define ICE1712_FLUSH 0x10 /* flush FIFO */ |
124 | #define ICE1712_STEREO 0x08 /* stereo */ |
125 | #define ICE1712_16BIT 0x04 /* 16-bit data */ |
126 | #define ICE1712_PAUSE 0x02 /* pause */ |
127 | #define ICE1712_START 0x01 /* start */ |
128 | #define ICE1712_DSC_RATE 0x05 /* dword - rate */ |
129 | #define ICE1712_DSC_VOLUME 0x06 /* word - volume control */ |
130 | |
131 | /* |
132 | * Professional multi-track direct control registers |
133 | */ |
134 | |
135 | #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x) |
136 | |
137 | #define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */ |
138 | #define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */ |
139 | #define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */ |
140 | #define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */ |
141 | #define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */ |
142 | #define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */ |
143 | #define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ |
144 | #define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */ |
145 | #define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */ |
146 | #define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */ |
147 | /* look to ICE1712_AC97_* */ |
148 | #define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */ |
149 | #define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */ |
150 | #define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */ |
151 | #define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */ |
152 | #define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */ |
153 | #define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */ |
154 | #define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */ |
155 | #define ICE1712_PLAYBACK_START 0x01 /* playback start */ |
156 | #define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */ |
157 | #define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */ |
158 | #define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */ |
159 | #define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */ |
160 | #define ICE1712_CAPTURE_START 0x01 /* capture start */ |
161 | #define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */ |
162 | #define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */ |
163 | #define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */ |
164 | #define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */ |
165 | #define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */ |
166 | #define ICE1712_MT_MONITOR_RATE 0x3b /* byte */ |
167 | #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */ |
168 | #define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */ |
169 | #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */ |
170 | #define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */ |
171 | |
172 | /* |
173 | * Codec configuration bits |
174 | */ |
175 | |
176 | /* PCI[60] System Configuration */ |
177 | #define ICE1712_CFG_CLOCK 0xc0 |
178 | #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */ |
179 | #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */ |
180 | #define ICE1712_CFG_EXT 0x80 /* external clock */ |
181 | #define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */ |
182 | #define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */ |
183 | #define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */ |
184 | #define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */ |
185 | /* PCI[61] AC-Link Configuration */ |
186 | #define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */ |
187 | #define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */ |
188 | /* PCI[62] I2S Features */ |
189 | #define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */ |
190 | #define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */ |
191 | #define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */ |
192 | #define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */ |
193 | /* PCI[63] S/PDIF Configuration */ |
194 | #define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */ |
195 | #define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */ |
196 | #define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */ |
197 | |
198 | /* |
199 | * DMA mode values |
200 | * identical with DMA_XXX on i386 architecture. |
201 | */ |
202 | #define ICE1712_DMA_MODE_WRITE 0x48 |
203 | #define ICE1712_DMA_AUTOINIT 0x10 |
204 | |
205 | |
206 | /* |
207 | * I2C EEPROM Address |
208 | */ |
209 | #define ICE_I2C_EEPROM_ADDR 0xA0 |
210 | |
211 | struct snd_ice1712; |
212 | |
213 | struct snd_ice1712_eeprom { |
214 | unsigned int subvendor; /* PCI[2c-2f] */ |
215 | unsigned char size; /* size of EEPROM image in bytes */ |
216 | unsigned char version; /* must be 1 (or 2 for vt1724) */ |
217 | unsigned char data[32]; |
218 | unsigned int gpiomask; |
219 | unsigned int gpiostate; |
220 | unsigned int gpiodir; |
221 | }; |
222 | |
223 | enum { |
224 | ICE_EEP1_CODEC = 0, /* 06 */ |
225 | ICE_EEP1_ACLINK, /* 07 */ |
226 | ICE_EEP1_I2SID, /* 08 */ |
227 | ICE_EEP1_SPDIF, /* 09 */ |
228 | ICE_EEP1_GPIO_MASK, /* 0a */ |
229 | ICE_EEP1_GPIO_STATE, /* 0b */ |
230 | ICE_EEP1_GPIO_DIR, /* 0c */ |
231 | ICE_EEP1_AC97_MAIN_LO, /* 0d */ |
232 | ICE_EEP1_AC97_MAIN_HI, /* 0e */ |
233 | ICE_EEP1_AC97_PCM_LO, /* 0f */ |
234 | ICE_EEP1_AC97_PCM_HI, /* 10 */ |
235 | ICE_EEP1_AC97_REC_LO, /* 11 */ |
236 | ICE_EEP1_AC97_REC_HI, /* 12 */ |
237 | ICE_EEP1_AC97_RECSRC, /* 13 */ |
238 | ICE_EEP1_DAC_ID, /* 14 */ |
239 | ICE_EEP1_DAC_ID1, |
240 | ICE_EEP1_DAC_ID2, |
241 | ICE_EEP1_DAC_ID3, |
242 | ICE_EEP1_ADC_ID, /* 18 */ |
243 | ICE_EEP1_ADC_ID1, |
244 | ICE_EEP1_ADC_ID2, |
245 | ICE_EEP1_ADC_ID3 |
246 | }; |
247 | |
248 | #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) |
249 | |
250 | |
251 | struct snd_ak4xxx_private { |
252 | unsigned int cif:1; /* CIF mode */ |
253 | unsigned char caddr; /* C0 and C1 bits */ |
254 | unsigned int data_mask; /* DATA gpio bit */ |
255 | unsigned int clk_mask; /* CLK gpio bit */ |
256 | unsigned int cs_mask; /* bit mask for select/deselect address */ |
257 | unsigned int cs_addr; /* bits to select address */ |
258 | unsigned int cs_none; /* bits to deselect address */ |
259 | unsigned int add_flags; /* additional bits at init */ |
260 | unsigned int mask_flags; /* total mask bits */ |
261 | struct snd_akm4xxx_ops { |
262 | void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate); |
263 | } ops; |
264 | }; |
265 | |
266 | struct snd_ice1712_spdif { |
267 | unsigned char cs8403_bits; |
268 | unsigned char cs8403_stream_bits; |
269 | struct snd_kcontrol *stream_ctl; |
270 | |
271 | struct snd_ice1712_spdif_ops { |
272 | void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *); |
273 | void (*setup_rate)(struct snd_ice1712 *, int rate); |
274 | void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *); |
275 | void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); |
276 | int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); |
277 | void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); |
278 | int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); |
279 | } ops; |
280 | }; |
281 | |
282 | struct snd_ice1712_card_info; |
283 | |
284 | struct snd_ice1712 { |
285 | unsigned long conp_dma_size; |
286 | unsigned long conc_dma_size; |
287 | unsigned long prop_dma_size; |
288 | unsigned long proc_dma_size; |
289 | int irq; |
290 | |
291 | unsigned long port; |
292 | unsigned long ddma_port; |
293 | unsigned long dmapath_port; |
294 | unsigned long profi_port; |
295 | |
296 | struct pci_dev *pci; |
297 | struct snd_card *card; |
298 | struct snd_pcm *pcm; |
299 | struct snd_pcm *pcm_ds; |
300 | struct snd_pcm *pcm_pro; |
301 | struct snd_pcm_substream *playback_con_substream; |
302 | struct snd_pcm_substream *playback_con_substream_ds[6]; |
303 | struct snd_pcm_substream *capture_con_substream; |
304 | struct snd_pcm_substream *playback_pro_substream; |
305 | struct snd_pcm_substream *capture_pro_substream; |
306 | unsigned int playback_pro_size; |
307 | unsigned int capture_pro_size; |
308 | unsigned int playback_con_virt_addr[6]; |
309 | unsigned int playback_con_active_buf[6]; |
310 | unsigned int capture_con_virt_addr; |
311 | unsigned int ac97_ext_id; |
312 | struct snd_ac97 *ac97; |
313 | struct snd_rawmidi *rmidi[2]; |
314 | |
315 | spinlock_t reg_lock; |
316 | struct snd_info_entry *proc_entry; |
317 | |
318 | struct snd_ice1712_eeprom eeprom; |
319 | const struct snd_ice1712_card_info *card_info; |
320 | |
321 | unsigned int pro_volumes[20]; |
322 | unsigned int omni:1; /* Delta Omni I/O */ |
323 | unsigned int dxr_enable:1; /* Terratec DXR enable for DMX6FIRE */ |
324 | unsigned int vt1724:1; |
325 | unsigned int vt1720:1; |
326 | unsigned int has_spdif:1; /* VT1720/4 - has SPDIF I/O */ |
327 | unsigned int force_pdma4:1; /* VT1720/4 - PDMA4 as non-spdif */ |
328 | unsigned int force_rdma1:1; /* VT1720/4 - RDMA1 as non-spdif */ |
329 | unsigned int midi_output:1; /* VT1720/4: MIDI output triggered */ |
330 | unsigned int midi_input:1; /* VT1720/4: MIDI input triggered */ |
331 | unsigned int own_routing:1; /* VT1720/4: use own routing ctls */ |
332 | unsigned int num_total_dacs; /* total DACs */ |
333 | unsigned int num_total_adcs; /* total ADCs */ |
334 | unsigned int cur_rate; /* current rate */ |
335 | |
336 | struct mutex open_mutex; |
337 | struct snd_pcm_substream *pcm_reserved[4]; |
338 | const struct snd_pcm_hw_constraint_list *hw_rates; /* card-specific rate constraints */ |
339 | |
340 | unsigned int akm_codecs; |
341 | struct snd_akm4xxx *akm; |
342 | struct snd_ice1712_spdif spdif; |
343 | |
344 | struct mutex i2c_mutex; /* I2C mutex for ICE1724 registers */ |
345 | struct snd_i2c_bus *i2c; /* I2C bus */ |
346 | struct snd_i2c_device *cs8427; /* CS8427 I2C device */ |
347 | unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */ |
348 | |
349 | struct ice1712_gpio { |
350 | unsigned int direction; /* current direction bits */ |
351 | unsigned int write_mask; /* current mask bits */ |
352 | unsigned int saved[2]; /* for ewx_i2c */ |
353 | /* operators */ |
354 | void (*set_mask)(struct snd_ice1712 *ice, unsigned int data); |
355 | unsigned int (*get_mask)(struct snd_ice1712 *ice); |
356 | void (*set_dir)(struct snd_ice1712 *ice, unsigned int data); |
357 | unsigned int (*get_dir)(struct snd_ice1712 *ice); |
358 | void (*set_data)(struct snd_ice1712 *ice, unsigned int data); |
359 | unsigned int (*get_data)(struct snd_ice1712 *ice); |
360 | /* misc operators - move to another place? */ |
361 | void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate); |
362 | void (*i2s_mclk_changed)(struct snd_ice1712 *ice); |
363 | } gpio; |
364 | struct mutex gpio_mutex; |
365 | |
366 | /* other board-specific data */ |
367 | void *spec; |
368 | |
369 | /* VT172x specific */ |
370 | int pro_rate_default; |
371 | int (*is_spdif_master)(struct snd_ice1712 *ice); |
372 | unsigned int (*get_rate)(struct snd_ice1712 *ice); |
373 | void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate); |
374 | unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate); |
375 | int (*set_spdif_clock)(struct snd_ice1712 *ice, int type); |
376 | int (*get_spdif_master_type)(struct snd_ice1712 *ice); |
377 | const char * const *ext_clock_names; |
378 | int ext_clock_count; |
379 | void (*pro_open)(struct snd_ice1712 *, struct snd_pcm_substream *); |
380 | #ifdef CONFIG_PM_SLEEP |
381 | int (*pm_suspend)(struct snd_ice1712 *); |
382 | int (*pm_resume)(struct snd_ice1712 *); |
383 | unsigned int pm_suspend_enabled:1; |
384 | unsigned int pm_saved_is_spdif_master:1; |
385 | unsigned int pm_saved_spdif_ctrl; |
386 | unsigned char pm_saved_spdif_cfg; |
387 | unsigned int pm_saved_route; |
388 | #endif |
389 | }; |
390 | |
391 | |
392 | /* |
393 | * gpio access functions |
394 | */ |
395 | static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits) |
396 | { |
397 | ice->gpio.set_dir(ice, bits); |
398 | } |
399 | |
400 | static inline unsigned int snd_ice1712_gpio_get_dir(struct snd_ice1712 *ice) |
401 | { |
402 | return ice->gpio.get_dir(ice); |
403 | } |
404 | |
405 | static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits) |
406 | { |
407 | ice->gpio.set_mask(ice, bits); |
408 | } |
409 | |
410 | static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val) |
411 | { |
412 | ice->gpio.set_data(ice, val); |
413 | } |
414 | |
415 | static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice) |
416 | { |
417 | return ice->gpio.get_data(ice); |
418 | } |
419 | |
420 | /* |
421 | * save and restore gpio status |
422 | * The access to gpio will be protected by mutex, so don't forget to |
423 | * restore! |
424 | */ |
425 | static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice) |
426 | { |
427 | mutex_lock(&ice->gpio_mutex); |
428 | ice->gpio.saved[0] = ice->gpio.direction; |
429 | ice->gpio.saved[1] = ice->gpio.write_mask; |
430 | } |
431 | |
432 | static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice) |
433 | { |
434 | ice->gpio.set_dir(ice, ice->gpio.saved[0]); |
435 | ice->gpio.set_mask(ice, ice->gpio.saved[1]); |
436 | ice->gpio.direction = ice->gpio.saved[0]; |
437 | ice->gpio.write_mask = ice->gpio.saved[1]; |
438 | mutex_unlock(lock: &ice->gpio_mutex); |
439 | } |
440 | |
441 | /* for bit controls */ |
442 | #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \ |
443 | { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \ |
444 | .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \ |
445 | .private_value = mask | (invert << 24) } |
446 | |
447 | int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); |
448 | int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); |
449 | |
450 | /* |
451 | * set gpio direction, write mask and data |
452 | */ |
453 | static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice, |
454 | unsigned int mask, unsigned int bits) |
455 | { |
456 | unsigned val; |
457 | |
458 | ice->gpio.direction |= mask; |
459 | snd_ice1712_gpio_set_dir(ice, bits: ice->gpio.direction); |
460 | val = snd_ice1712_gpio_read(ice); |
461 | val &= ~mask; |
462 | val |= mask & bits; |
463 | snd_ice1712_gpio_write(ice, val); |
464 | } |
465 | |
466 | static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice, |
467 | unsigned int mask) |
468 | { |
469 | ice->gpio.direction &= ~mask; |
470 | snd_ice1712_gpio_set_dir(ice, bits: ice->gpio.direction); |
471 | return snd_ice1712_gpio_read(ice) & mask; |
472 | } |
473 | |
474 | /* route access functions */ |
475 | int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift); |
476 | int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val, |
477 | int shift); |
478 | |
479 | int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice); |
480 | |
481 | int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak, |
482 | const struct snd_akm4xxx *template, |
483 | const struct snd_ak4xxx_private *priv, |
484 | struct snd_ice1712 *ice); |
485 | void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice); |
486 | int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice); |
487 | |
488 | int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr); |
489 | |
490 | static inline void snd_ice1712_write(struct snd_ice1712 *ice, u8 addr, u8 data) |
491 | { |
492 | outb(value: addr, ICEREG(ice, INDEX)); |
493 | outb(value: data, ICEREG(ice, DATA)); |
494 | } |
495 | |
496 | static inline u8 snd_ice1712_read(struct snd_ice1712 *ice, u8 addr) |
497 | { |
498 | outb(value: addr, ICEREG(ice, INDEX)); |
499 | return inb(ICEREG(ice, DATA)); |
500 | } |
501 | |
502 | |
503 | /* |
504 | * entry pointer |
505 | */ |
506 | |
507 | struct snd_ice1712_card_info { |
508 | unsigned int subvendor; |
509 | const char *name; |
510 | const char *model; |
511 | const char *driver; |
512 | int (*chip_init)(struct snd_ice1712 *); |
513 | void (*chip_exit)(struct snd_ice1712 *); |
514 | int (*build_controls)(struct snd_ice1712 *); |
515 | unsigned int no_mpu401:1; |
516 | unsigned int mpu401_1_info_flags; |
517 | unsigned int mpu401_2_info_flags; |
518 | const char *mpu401_1_name; |
519 | const char *mpu401_2_name; |
520 | const unsigned int eeprom_size; |
521 | const unsigned char *eeprom_data; |
522 | }; |
523 | |
524 | |
525 | #endif /* __SOUND_ICE1712_H */ |
526 | |