1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA modem driver for Intel ICH (i8x0) chipsets
4 *
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6 *
7 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
8 * of ALSA ICH sound driver intel8x0.c .
9 */
10
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/interrupt.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/module.h>
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/ac97_codec.h>
21#include <sound/info.h>
22#include <sound/initval.h>
23
24MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
25MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
26 "SiS 7013; NVidia MCP/2/2S/3 modems");
27MODULE_LICENSE("GPL");
28
29static int index = -2; /* Exclude the first card */
30static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
31static int ac97_clock;
32
33module_param(index, int, 0444);
34MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
35module_param(id, charp, 0444);
36MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
37module_param(ac97_clock, int, 0444);
38MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
39
40/* just for backward compatibility */
41static bool enable;
42module_param(enable, bool, 0444);
43
44/*
45 * Direct registers
46 */
47enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
48
49#define ICHREG(x) ICH_REG_##x
50
51#define DEFINE_REGSET(name,base) \
52enum { \
53 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
54 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
55 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
56 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
57 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
58 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
59 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
60}
61
62/* busmaster blocks */
63DEFINE_REGSET(OFF, 0); /* offset */
64
65/* values for each busmaster block */
66
67/* LVI */
68#define ICH_REG_LVI_MASK 0x1f
69
70/* SR */
71#define ICH_FIFOE 0x10 /* FIFO error */
72#define ICH_BCIS 0x08 /* buffer completion interrupt status */
73#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
74#define ICH_CELV 0x02 /* current equals last valid */
75#define ICH_DCH 0x01 /* DMA controller halted */
76
77/* PIV */
78#define ICH_REG_PIV_MASK 0x1f /* mask */
79
80/* CR */
81#define ICH_IOCE 0x10 /* interrupt on completion enable */
82#define ICH_FEIE 0x08 /* fifo error interrupt enable */
83#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
84#define ICH_RESETREGS 0x02 /* reset busmaster registers */
85#define ICH_STARTBM 0x01 /* start busmaster operation */
86
87
88/* global block */
89#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
90#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
91#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
92#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
93#define ICH_ACLINK 0x00000008 /* AClink shut off */
94#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
95#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
96#define ICH_GIE 0x00000001 /* GPI interrupt enable */
97#define ICH_REG_GLOB_STA 0x40 /* dword - global status */
98#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
99#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
100#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
101#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
102#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
103#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
104#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
105#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
106#define ICH_MD3 0x00020000 /* modem power down semaphore */
107#define ICH_AD3 0x00010000 /* audio power down semaphore */
108#define ICH_RCS 0x00008000 /* read completion status */
109#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
110#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
111#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
112#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
113#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
114#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
115#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
116#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
117#define ICH_POINT 0x00000040 /* playback interrupt */
118#define ICH_PIINT 0x00000020 /* capture interrupt */
119#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
120#define ICH_MOINT 0x00000004 /* modem playback interrupt */
121#define ICH_MIINT 0x00000002 /* modem capture interrupt */
122#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
123#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
124#define ICH_CAS 0x01 /* codec access semaphore */
125
126#define ICH_MAX_FRAGS 32 /* max hw frags */
127
128
129/*
130 *
131 */
132
133enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
134enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
135
136#define get_ichdev(substream) (substream->runtime->private_data)
137
138struct ichdev {
139 unsigned int ichd; /* ich device number */
140 unsigned long reg_offset; /* offset to bmaddr */
141 __le32 *bdbar; /* CPU address (32bit) */
142 unsigned int bdbar_addr; /* PCI bus address (32bit) */
143 struct snd_pcm_substream *substream;
144 unsigned int physbuf; /* physical address (32bit) */
145 unsigned int size;
146 unsigned int fragsize;
147 unsigned int fragsize1;
148 unsigned int position;
149 int frags;
150 int lvi;
151 int lvi_frag;
152 int civ;
153 int ack;
154 int ack_reload;
155 unsigned int ack_bit;
156 unsigned int roff_sr;
157 unsigned int roff_picb;
158 unsigned int int_sta_mask; /* interrupt status mask */
159 unsigned int ali_slot; /* ALI DMA slot */
160 struct snd_ac97 *ac97;
161};
162
163struct intel8x0m {
164 unsigned int device_type;
165
166 int irq;
167
168 void __iomem *addr;
169 void __iomem *bmaddr;
170
171 struct pci_dev *pci;
172 struct snd_card *card;
173
174 int pcm_devs;
175 struct snd_pcm *pcm[2];
176 struct ichdev ichd[2];
177
178 unsigned int in_ac97_init: 1;
179
180 struct snd_ac97_bus *ac97_bus;
181 struct snd_ac97 *ac97;
182
183 spinlock_t reg_lock;
184
185 struct snd_dma_buffer *bdbars;
186 u32 bdbars_count;
187 u32 int_sta_reg; /* interrupt status register */
188 u32 int_sta_mask; /* interrupt status mask */
189 unsigned int pcm_pos_shift;
190};
191
192static const struct pci_device_id snd_intel8x0m_ids[] = {
193 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */
194 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */
195 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */
196 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */
197 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */
198 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */
199 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */
200 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */
201 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */
202 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */
203 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */
204 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */
205 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */
206 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */
207 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */
208 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */
209#if 0
210 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
211#endif
212 { 0, }
213};
214
215MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
216
217/*
218 * Lowlevel I/O - busmaster
219 */
220
221static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
222{
223 return ioread8(chip->bmaddr + offset);
224}
225
226static inline u16 igetword(struct intel8x0m *chip, u32 offset)
227{
228 return ioread16(chip->bmaddr + offset);
229}
230
231static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
232{
233 return ioread32(chip->bmaddr + offset);
234}
235
236static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
237{
238 iowrite8(val, chip->bmaddr + offset);
239}
240
241static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
242{
243 iowrite16(val, chip->bmaddr + offset);
244}
245
246static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
247{
248 iowrite32(val, chip->bmaddr + offset);
249}
250
251/*
252 * Lowlevel I/O - AC'97 registers
253 */
254
255static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
256{
257 return ioread16(chip->addr + offset);
258}
259
260static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
261{
262 iowrite16(val, chip->addr + offset);
263}
264
265/*
266 * Basic I/O
267 */
268
269/*
270 * access to AC97 codec via normal i/o (for ICH and SIS7013)
271 */
272
273/* return the GLOB_STA bit for the corresponding codec */
274static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
275{
276 static const unsigned int codec_bit[3] = {
277 ICH_PCR, ICH_SCR, ICH_TCR
278 };
279 if (snd_BUG_ON(codec >= 3))
280 return ICH_PCR;
281 return codec_bit[codec];
282}
283
284static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
285{
286 int time;
287
288 if (codec > 1)
289 return -EIO;
290 codec = get_ich_codec_bit(chip, codec);
291
292 /* codec ready ? */
293 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
294 return -EIO;
295
296 /* Anyone holding a semaphore for 1 msec should be shot... */
297 time = 100;
298 do {
299 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
300 return 0;
301 udelay(usec: 10);
302 } while (time--);
303
304 /* access to some forbidden (non existent) ac97 registers will not
305 * reset the semaphore. So even if you don't get the semaphore, still
306 * continue the access. We don't need the semaphore anyway. */
307 dev_err(chip->card->dev,
308 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
309 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
310 iagetword(chip, offset: 0); /* clear semaphore flag */
311 /* I don't care about the semaphore */
312 return -EBUSY;
313}
314
315static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
316 unsigned short reg,
317 unsigned short val)
318{
319 struct intel8x0m *chip = ac97->private_data;
320
321 if (snd_intel8x0m_codec_semaphore(chip, codec: ac97->num) < 0) {
322 if (! chip->in_ac97_init)
323 dev_err(chip->card->dev,
324 "codec_write %d: semaphore is not ready for register 0x%x\n",
325 ac97->num, reg);
326 }
327 iaputword(chip, offset: reg + ac97->num * 0x80, val);
328}
329
330static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
331 unsigned short reg)
332{
333 struct intel8x0m *chip = ac97->private_data;
334 unsigned short res;
335 unsigned int tmp;
336
337 if (snd_intel8x0m_codec_semaphore(chip, codec: ac97->num) < 0) {
338 if (! chip->in_ac97_init)
339 dev_err(chip->card->dev,
340 "codec_read %d: semaphore is not ready for register 0x%x\n",
341 ac97->num, reg);
342 res = 0xffff;
343 } else {
344 res = iagetword(chip, offset: reg + ac97->num * 0x80);
345 tmp = igetdword(chip, ICHREG(GLOB_STA));
346 if (tmp & ICH_RCS) {
347 /* reset RCS and preserve other R/WC bits */
348 iputdword(chip, ICHREG(GLOB_STA),
349 val: tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
350 if (! chip->in_ac97_init)
351 dev_err(chip->card->dev,
352 "codec_read %d: read timeout for register 0x%x\n",
353 ac97->num, reg);
354 res = 0xffff;
355 }
356 }
357 if (reg == AC97_GPIO_STATUS)
358 iagetword(chip, offset: 0); /* clear semaphore */
359 return res;
360}
361
362
363/*
364 * DMA I/O
365 */
366static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
367{
368 int idx;
369 __le32 *bdbar = ichdev->bdbar;
370 unsigned long port = ichdev->reg_offset;
371
372 iputdword(chip, offset: port + ICH_REG_OFF_BDBAR, val: ichdev->bdbar_addr);
373 if (ichdev->size == ichdev->fragsize) {
374 ichdev->ack_reload = ichdev->ack = 2;
375 ichdev->fragsize1 = ichdev->fragsize >> 1;
376 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
377 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
378 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
379 ichdev->fragsize1 >> chip->pcm_pos_shift);
380 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
381 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
382 ichdev->fragsize1 >> chip->pcm_pos_shift);
383 }
384 ichdev->frags = 2;
385 } else {
386 ichdev->ack_reload = ichdev->ack = 1;
387 ichdev->fragsize1 = ichdev->fragsize;
388 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
389 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
390 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
391 ichdev->fragsize >> chip->pcm_pos_shift);
392 /*
393 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
394 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
395 */
396 }
397 ichdev->frags = ichdev->size / ichdev->fragsize;
398 }
399 iputbyte(chip, offset: port + ICH_REG_OFF_LVI, val: ichdev->lvi = ICH_REG_LVI_MASK);
400 ichdev->civ = 0;
401 iputbyte(chip, offset: port + ICH_REG_OFF_CIV, val: 0);
402 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
403 ichdev->position = 0;
404#if 0
405 dev_dbg(chip->card->dev,
406 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
407 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
408 ichdev->fragsize1);
409#endif
410 /* clear interrupts */
411 iputbyte(chip, offset: port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
412}
413
414/*
415 * Interrupt handler
416 */
417
418static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
419{
420 unsigned long port = ichdev->reg_offset;
421 int civ, i, step;
422 int ack = 0;
423
424 civ = igetbyte(chip, offset: port + ICH_REG_OFF_CIV);
425 if (civ == ichdev->civ) {
426 step = 1;
427 ichdev->civ++;
428 ichdev->civ &= ICH_REG_LVI_MASK;
429 } else {
430 step = civ - ichdev->civ;
431 if (step < 0)
432 step += ICH_REG_LVI_MASK + 1;
433 ichdev->civ = civ;
434 }
435
436 ichdev->position += step * ichdev->fragsize1;
437 ichdev->position %= ichdev->size;
438 ichdev->lvi += step;
439 ichdev->lvi &= ICH_REG_LVI_MASK;
440 iputbyte(chip, offset: port + ICH_REG_OFF_LVI, val: ichdev->lvi);
441 for (i = 0; i < step; i++) {
442 ichdev->lvi_frag++;
443 ichdev->lvi_frag %= ichdev->frags;
444 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
445 ichdev->lvi_frag *
446 ichdev->fragsize1);
447#if 0
448 dev_dbg(chip->card->dev,
449 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
450 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
451 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
452 inl(port + 4), inb(port + ICH_REG_OFF_CR));
453#endif
454 if (--ichdev->ack == 0) {
455 ichdev->ack = ichdev->ack_reload;
456 ack = 1;
457 }
458 }
459 if (ack && ichdev->substream) {
460 spin_unlock(lock: &chip->reg_lock);
461 snd_pcm_period_elapsed(substream: ichdev->substream);
462 spin_lock(lock: &chip->reg_lock);
463 }
464 iputbyte(chip, offset: port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
465}
466
467static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
468{
469 struct intel8x0m *chip = dev_id;
470 struct ichdev *ichdev;
471 unsigned int status;
472 unsigned int i;
473
474 guard(spinlock)(l: &chip->reg_lock);
475 status = igetdword(chip, offset: chip->int_sta_reg);
476 if (status == 0xffffffff) /* we are not yet resumed */
477 return IRQ_NONE;
478 if ((status & chip->int_sta_mask) == 0) {
479 if (status)
480 iputdword(chip, offset: chip->int_sta_reg, val: status);
481 return IRQ_NONE;
482 }
483
484 for (i = 0; i < chip->bdbars_count; i++) {
485 ichdev = &chip->ichd[i];
486 if (status & ichdev->int_sta_mask)
487 snd_intel8x0m_update(chip, ichdev);
488 }
489
490 /* ack them */
491 iputdword(chip, offset: chip->int_sta_reg, val: status & chip->int_sta_mask);
492
493 return IRQ_HANDLED;
494}
495
496/*
497 * PCM part
498 */
499
500static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
501{
502 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
503 struct ichdev *ichdev = get_ichdev(substream);
504 unsigned char val = 0;
505 unsigned long port = ichdev->reg_offset;
506
507 switch (cmd) {
508 case SNDRV_PCM_TRIGGER_START:
509 case SNDRV_PCM_TRIGGER_RESUME:
510 val = ICH_IOCE | ICH_STARTBM;
511 break;
512 case SNDRV_PCM_TRIGGER_STOP:
513 case SNDRV_PCM_TRIGGER_SUSPEND:
514 val = 0;
515 break;
516 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
517 val = ICH_IOCE;
518 break;
519 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
520 val = ICH_IOCE | ICH_STARTBM;
521 break;
522 default:
523 return -EINVAL;
524 }
525 iputbyte(chip, offset: port + ICH_REG_OFF_CR, val);
526 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
527 /* wait until DMA stopped */
528 while (!(igetbyte(chip, offset: port + ichdev->roff_sr) & ICH_DCH)) ;
529 /* reset whole DMA things */
530 iputbyte(chip, offset: port + ICH_REG_OFF_CR, ICH_RESETREGS);
531 }
532 return 0;
533}
534
535static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
536{
537 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
538 struct ichdev *ichdev = get_ichdev(substream);
539 size_t ptr1, ptr;
540
541 ptr1 = igetword(chip, offset: ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
542 if (ptr1 != 0)
543 ptr = ichdev->fragsize1 - ptr1;
544 else
545 ptr = 0;
546 ptr += ichdev->position;
547 if (ptr >= ichdev->size)
548 return 0;
549 return bytes_to_frames(runtime: substream->runtime, size: ptr);
550}
551
552static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
553{
554 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
555 struct snd_pcm_runtime *runtime = substream->runtime;
556 struct ichdev *ichdev = get_ichdev(substream);
557
558 ichdev->physbuf = runtime->dma_addr;
559 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
560 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
561 snd_ac97_write(ac97: ichdev->ac97, AC97_LINE1_RATE, value: runtime->rate);
562 snd_ac97_write(ac97: ichdev->ac97, AC97_LINE1_LEVEL, value: 0);
563 snd_intel8x0m_setup_periods(chip, ichdev);
564 return 0;
565}
566
567static const struct snd_pcm_hardware snd_intel8x0m_stream =
568{
569 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
570 SNDRV_PCM_INFO_BLOCK_TRANSFER |
571 SNDRV_PCM_INFO_MMAP_VALID |
572 SNDRV_PCM_INFO_PAUSE |
573 SNDRV_PCM_INFO_RESUME),
574 .formats = SNDRV_PCM_FMTBIT_S16_LE,
575 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
576 .rate_min = 8000,
577 .rate_max = 16000,
578 .channels_min = 1,
579 .channels_max = 1,
580 .buffer_bytes_max = 64 * 1024,
581 .period_bytes_min = 32,
582 .period_bytes_max = 64 * 1024,
583 .periods_min = 1,
584 .periods_max = 1024,
585 .fifo_size = 0,
586};
587
588
589static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
590{
591 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };
592 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
593 .count = ARRAY_SIZE(rates),
594 .list = rates,
595 .mask = 0,
596 };
597 struct snd_pcm_runtime *runtime = substream->runtime;
598 int err;
599
600 ichdev->substream = substream;
601 runtime->hw = snd_intel8x0m_stream;
602 err = snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_RATE,
603 l: &hw_constraints_rates);
604 if ( err < 0 )
605 return err;
606 runtime->private_data = ichdev;
607 return 0;
608}
609
610static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
611{
612 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
613
614 return snd_intel8x0m_pcm_open(substream, ichdev: &chip->ichd[ICHD_MDMOUT]);
615}
616
617static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
618{
619 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
620
621 chip->ichd[ICHD_MDMOUT].substream = NULL;
622 return 0;
623}
624
625static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
626{
627 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
628
629 return snd_intel8x0m_pcm_open(substream, ichdev: &chip->ichd[ICHD_MDMIN]);
630}
631
632static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
633{
634 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
635
636 chip->ichd[ICHD_MDMIN].substream = NULL;
637 return 0;
638}
639
640
641static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {
642 .open = snd_intel8x0m_playback_open,
643 .close = snd_intel8x0m_playback_close,
644 .prepare = snd_intel8x0m_pcm_prepare,
645 .trigger = snd_intel8x0m_pcm_trigger,
646 .pointer = snd_intel8x0m_pcm_pointer,
647};
648
649static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {
650 .open = snd_intel8x0m_capture_open,
651 .close = snd_intel8x0m_capture_close,
652 .prepare = snd_intel8x0m_pcm_prepare,
653 .trigger = snd_intel8x0m_pcm_trigger,
654 .pointer = snd_intel8x0m_pcm_pointer,
655};
656
657
658struct ich_pcm_table {
659 char *suffix;
660 const struct snd_pcm_ops *playback_ops;
661 const struct snd_pcm_ops *capture_ops;
662 size_t prealloc_size;
663 size_t prealloc_max_size;
664 int ac97_idx;
665};
666
667static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
668 const struct ich_pcm_table *rec)
669{
670 struct snd_pcm *pcm;
671 int err;
672 char name[32];
673
674 if (rec->suffix)
675 sprintf(buf: name, fmt: "Intel ICH - %s", rec->suffix);
676 else
677 strscpy(name, "Intel ICH");
678 err = snd_pcm_new(card: chip->card, id: name, device,
679 playback_count: rec->playback_ops ? 1 : 0,
680 capture_count: rec->capture_ops ? 1 : 0, rpcm: &pcm);
681 if (err < 0)
682 return err;
683
684 if (rec->playback_ops)
685 snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: rec->playback_ops);
686 if (rec->capture_ops)
687 snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: rec->capture_ops);
688
689 pcm->private_data = chip;
690 pcm->info_flags = 0;
691 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
692 if (rec->suffix)
693 sprintf(buf: pcm->name, fmt: "%s - %s", chip->card->shortname, rec->suffix);
694 else
695 strscpy(pcm->name, chip->card->shortname);
696 chip->pcm[device] = pcm;
697
698 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
699 data: &chip->pci->dev,
700 size: rec->prealloc_size,
701 max: rec->prealloc_max_size);
702
703 return 0;
704}
705
706static const struct ich_pcm_table intel_pcms[] = {
707 {
708 .suffix = "Modem",
709 .playback_ops = &snd_intel8x0m_playback_ops,
710 .capture_ops = &snd_intel8x0m_capture_ops,
711 .prealloc_size = 32 * 1024,
712 .prealloc_max_size = 64 * 1024,
713 },
714};
715
716static int snd_intel8x0m_pcm(struct intel8x0m *chip)
717{
718 int i, tblsize, device, err;
719 const struct ich_pcm_table *tbl, *rec;
720
721#if 1
722 tbl = intel_pcms;
723 tblsize = 1;
724#else
725 switch (chip->device_type) {
726 case DEVICE_NFORCE:
727 tbl = nforce_pcms;
728 tblsize = ARRAY_SIZE(nforce_pcms);
729 break;
730 case DEVICE_ALI:
731 tbl = ali_pcms;
732 tblsize = ARRAY_SIZE(ali_pcms);
733 break;
734 default:
735 tbl = intel_pcms;
736 tblsize = 2;
737 break;
738 }
739#endif
740 device = 0;
741 for (i = 0; i < tblsize; i++) {
742 rec = tbl + i;
743 if (i > 0 && rec->ac97_idx) {
744 /* activate PCM only when associated AC'97 codec */
745 if (! chip->ichd[rec->ac97_idx].ac97)
746 continue;
747 }
748 err = snd_intel8x0m_pcm1(chip, device, rec);
749 if (err < 0)
750 return err;
751 device++;
752 }
753
754 chip->pcm_devs = device;
755 return 0;
756}
757
758
759/*
760 * Mixer part
761 */
762
763static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
764{
765 struct intel8x0m *chip = bus->private_data;
766 chip->ac97_bus = NULL;
767}
768
769static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
770{
771 struct intel8x0m *chip = ac97->private_data;
772 chip->ac97 = NULL;
773}
774
775
776static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
777{
778 struct snd_ac97_bus *pbus;
779 struct snd_ac97_template ac97;
780 struct snd_ac97 *x97;
781 int err;
782 unsigned int glob_sta = 0;
783 static const struct snd_ac97_bus_ops ops = {
784 .write = snd_intel8x0m_codec_write,
785 .read = snd_intel8x0m_codec_read,
786 };
787
788 chip->in_ac97_init = 1;
789
790 memset(&ac97, 0, sizeof(ac97));
791 ac97.private_data = chip;
792 ac97.private_free = snd_intel8x0m_mixer_free_ac97;
793 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
794
795 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
796
797 err = snd_ac97_bus(card: chip->card, num: 0, ops: &ops, private_data: chip, rbus: &pbus);
798 if (err < 0)
799 goto __err;
800 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
801 if (ac97_clock >= 8000 && ac97_clock <= 48000)
802 pbus->clock = ac97_clock;
803 chip->ac97_bus = pbus;
804
805 ac97.pci = chip->pci;
806 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
807 err = snd_ac97_mixer(bus: pbus, template: &ac97, rac97: &x97);
808 if (err < 0) {
809 dev_err(chip->card->dev,
810 "Unable to initialize codec #%d\n", ac97.num);
811 if (ac97.num == 0)
812 goto __err;
813 return err;
814 }
815 chip->ac97 = x97;
816 if(ac97_is_modem(ac97: x97) && !chip->ichd[ICHD_MDMIN].ac97) {
817 chip->ichd[ICHD_MDMIN].ac97 = x97;
818 chip->ichd[ICHD_MDMOUT].ac97 = x97;
819 }
820
821 chip->in_ac97_init = 0;
822 return 0;
823
824 __err:
825 /* clear the cold-reset bit for the next chance */
826 if (chip->device_type != DEVICE_ALI)
827 iputdword(chip, ICHREG(GLOB_CNT),
828 val: igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
829 return err;
830}
831
832
833/*
834 *
835 */
836
837static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
838{
839 unsigned long end_time;
840 unsigned int cnt, status, nstatus;
841
842 /* put logic to right state */
843 /* first clear status bits */
844 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
845 cnt = igetdword(chip, ICHREG(GLOB_STA));
846 iputdword(chip, ICHREG(GLOB_STA), val: cnt & status);
847
848 /* ACLink on, 2 channels */
849 cnt = igetdword(chip, ICHREG(GLOB_CNT));
850 cnt &= ~(ICH_ACLINK);
851 /* finish cold or do warm reset */
852 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
853 iputdword(chip, ICHREG(GLOB_CNT), val: cnt);
854 usleep_range(min: 500, max: 1000); /* give warm reset some time */
855 end_time = jiffies + HZ / 4;
856 do {
857 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
858 goto __ok;
859 schedule_timeout_uninterruptible(timeout: 1);
860 } while (time_after_eq(end_time, jiffies));
861 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
862 igetdword(chip, ICHREG(GLOB_CNT)));
863 return -EIO;
864
865 __ok:
866 if (probing) {
867 /* wait for any codec ready status.
868 * Once it becomes ready it should remain ready
869 * as long as we do not disable the ac97 link.
870 */
871 end_time = jiffies + HZ;
872 do {
873 status = igetdword(chip, ICHREG(GLOB_STA)) &
874 (ICH_PCR | ICH_SCR | ICH_TCR);
875 if (status)
876 break;
877 schedule_timeout_uninterruptible(timeout: 1);
878 } while (time_after_eq(end_time, jiffies));
879 if (! status) {
880 /* no codec is found */
881 dev_err(chip->card->dev,
882 "codec_ready: codec is not ready [0x%x]\n",
883 igetdword(chip, ICHREG(GLOB_STA)));
884 return -EIO;
885 }
886
887 /* up to two codecs (modem cannot be tertiary with ICH4) */
888 nstatus = ICH_PCR | ICH_SCR;
889
890 /* wait for other codecs ready status. */
891 end_time = jiffies + HZ / 4;
892 while (status != nstatus && time_after_eq(end_time, jiffies)) {
893 schedule_timeout_uninterruptible(timeout: 1);
894 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
895 }
896
897 } else {
898 /* resume phase */
899 status = 0;
900 if (chip->ac97)
901 status |= get_ich_codec_bit(chip, codec: chip->ac97->num);
902 /* wait until all the probed codecs are ready */
903 end_time = jiffies + HZ;
904 do {
905 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
906 (ICH_PCR | ICH_SCR | ICH_TCR);
907 if (status == nstatus)
908 break;
909 schedule_timeout_uninterruptible(timeout: 1);
910 } while (time_after_eq(end_time, jiffies));
911 }
912
913 if (chip->device_type == DEVICE_SIS) {
914 /* unmute the output on SIS7013 */
915 iputword(chip, offset: 0x4c, val: igetword(chip, offset: 0x4c) | 1);
916 }
917
918 return 0;
919}
920
921static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
922{
923 unsigned int i;
924 int err;
925
926 err = snd_intel8x0m_ich_chip_init(chip, probing);
927 if (err < 0)
928 return err;
929 iagetword(chip, offset: 0); /* clear semaphore flag */
930
931 /* disable interrupts */
932 for (i = 0; i < chip->bdbars_count; i++)
933 iputbyte(chip, offset: ICH_REG_OFF_CR + chip->ichd[i].reg_offset, val: 0x00);
934 /* reset channels */
935 for (i = 0; i < chip->bdbars_count; i++)
936 iputbyte(chip, offset: ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
937 /* initialize Buffer Descriptor Lists */
938 for (i = 0; i < chip->bdbars_count; i++)
939 iputdword(chip, offset: ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, val: chip->ichd[i].bdbar_addr);
940 return 0;
941}
942
943static void snd_intel8x0m_free(struct snd_card *card)
944{
945 struct intel8x0m *chip = card->private_data;
946 unsigned int i;
947
948 if (chip->irq < 0)
949 goto __hw_end;
950 /* disable interrupts */
951 for (i = 0; i < chip->bdbars_count; i++)
952 iputbyte(chip, offset: ICH_REG_OFF_CR + chip->ichd[i].reg_offset, val: 0x00);
953 /* reset channels */
954 for (i = 0; i < chip->bdbars_count; i++)
955 iputbyte(chip, offset: ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
956 __hw_end:
957 if (chip->irq >= 0)
958 free_irq(chip->irq, chip);
959}
960
961/*
962 * power management
963 */
964static int intel8x0m_suspend(struct device *dev)
965{
966 struct snd_card *card = dev_get_drvdata(dev);
967 struct intel8x0m *chip = card->private_data;
968
969 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
970 snd_ac97_suspend(ac97: chip->ac97);
971 if (chip->irq >= 0) {
972 free_irq(chip->irq, chip);
973 chip->irq = -1;
974 card->sync_irq = -1;
975 }
976 return 0;
977}
978
979static int intel8x0m_resume(struct device *dev)
980{
981 struct pci_dev *pci = to_pci_dev(dev);
982 struct snd_card *card = dev_get_drvdata(dev);
983 struct intel8x0m *chip = card->private_data;
984
985 if (request_irq(irq: pci->irq, handler: snd_intel8x0m_interrupt,
986 IRQF_SHARED, KBUILD_MODNAME, dev: chip)) {
987 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
988 pci->irq);
989 snd_card_disconnect(card);
990 return -EIO;
991 }
992 chip->irq = pci->irq;
993 card->sync_irq = chip->irq;
994 snd_intel8x0m_chip_init(chip, probing: 0);
995 snd_ac97_resume(ac97: chip->ac97);
996
997 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
998 return 0;
999}
1000
1001static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
1002
1003static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1004 struct snd_info_buffer *buffer)
1005{
1006 struct intel8x0m *chip = entry->private_data;
1007 unsigned int tmp;
1008
1009 snd_iprintf(buffer, "Intel8x0m\n\n");
1010 if (chip->device_type == DEVICE_ALI)
1011 return;
1012 tmp = igetdword(chip, ICHREG(GLOB_STA));
1013 snd_iprintf(buffer, "Global control : 0x%08x\n",
1014 igetdword(chip, ICHREG(GLOB_CNT)));
1015 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1016 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1017 tmp & ICH_PCR ? " primary" : "",
1018 tmp & ICH_SCR ? " secondary" : "",
1019 tmp & ICH_TCR ? " tertiary" : "",
1020 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1021}
1022
1023static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
1024{
1025 snd_card_ro_proc_new(card: chip->card, name: "intel8x0m", private_data: chip,
1026 read: snd_intel8x0m_proc_read);
1027}
1028
1029struct ich_reg_info {
1030 unsigned int int_sta_mask;
1031 unsigned int offset;
1032};
1033
1034static int snd_intel8x0m_init(struct snd_card *card,
1035 struct pci_dev *pci,
1036 unsigned long device_type)
1037{
1038 struct intel8x0m *chip = card->private_data;
1039 int err;
1040 unsigned int i;
1041 unsigned int int_sta_masks;
1042 struct ichdev *ichdev;
1043 static const struct ich_reg_info intel_regs[2] = {
1044 { ICH_MIINT, 0 },
1045 { ICH_MOINT, 0x10 },
1046 };
1047 const struct ich_reg_info *tbl;
1048
1049 err = pcim_enable_device(pdev: pci);
1050 if (err < 0)
1051 return err;
1052
1053 spin_lock_init(&chip->reg_lock);
1054 chip->device_type = device_type;
1055 chip->card = card;
1056 chip->pci = pci;
1057 chip->irq = -1;
1058
1059 err = pcim_request_all_regions(pdev: pci, name: card->shortname);
1060 if (err < 0)
1061 return err;
1062
1063 if (device_type == DEVICE_ALI) {
1064 /* ALI5455 has no ac97 region */
1065 chip->bmaddr = pcim_iomap(pdev: pci, bar: 0, maxlen: 0);
1066 } else {
1067 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1068 chip->addr = pcim_iomap(pdev: pci, bar: 2, maxlen: 0);
1069 else
1070 chip->addr = pcim_iomap(pdev: pci, bar: 0, maxlen: 0);
1071 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1072 chip->bmaddr = pcim_iomap(pdev: pci, bar: 3, maxlen: 0);
1073 else
1074 chip->bmaddr = pcim_iomap(pdev: pci, bar: 1, maxlen: 0);
1075 }
1076
1077 /* initialize offsets */
1078 chip->bdbars_count = 2;
1079 tbl = intel_regs;
1080
1081 for (i = 0; i < chip->bdbars_count; i++) {
1082 ichdev = &chip->ichd[i];
1083 ichdev->ichd = i;
1084 ichdev->reg_offset = tbl[i].offset;
1085 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1086 if (device_type == DEVICE_SIS) {
1087 /* SiS 7013 swaps the registers */
1088 ichdev->roff_sr = ICH_REG_OFF_PICB;
1089 ichdev->roff_picb = ICH_REG_OFF_SR;
1090 } else {
1091 ichdev->roff_sr = ICH_REG_OFF_SR;
1092 ichdev->roff_picb = ICH_REG_OFF_PICB;
1093 }
1094 if (device_type == DEVICE_ALI)
1095 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1096 }
1097 /* SIS7013 handles the pcm data in bytes, others are in words */
1098 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1099
1100 /* allocate buffer descriptor lists */
1101 /* the start of each lists must be aligned to 8 bytes */
1102 chip->bdbars = snd_devm_alloc_pages(dev: &pci->dev, SNDRV_DMA_TYPE_DEV,
1103 size: chip->bdbars_count * sizeof(u32) *
1104 ICH_MAX_FRAGS * 2);
1105 if (!chip->bdbars)
1106 return -ENOMEM;
1107
1108 /* tables must be aligned to 8 bytes here, but the kernel pages
1109 are much bigger, so we don't care (on i386) */
1110 int_sta_masks = 0;
1111 for (i = 0; i < chip->bdbars_count; i++) {
1112 ichdev = &chip->ichd[i];
1113 ichdev->bdbar = ((__le32 *)chip->bdbars->area) + (i * ICH_MAX_FRAGS * 2);
1114 ichdev->bdbar_addr = chip->bdbars->addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1115 int_sta_masks |= ichdev->int_sta_mask;
1116 }
1117 chip->int_sta_reg = ICH_REG_GLOB_STA;
1118 chip->int_sta_mask = int_sta_masks;
1119
1120 pci_set_master(dev: pci);
1121
1122 err = snd_intel8x0m_chip_init(chip, probing: 1);
1123 if (err < 0)
1124 return err;
1125
1126 /* NOTE: we don't use devm version here since it's released /
1127 * re-acquired in PM callbacks.
1128 * It's released explicitly in snd_intel8x0m_free(), too.
1129 */
1130 if (request_irq(irq: pci->irq, handler: snd_intel8x0m_interrupt, IRQF_SHARED,
1131 KBUILD_MODNAME, dev: chip)) {
1132 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1133 return -EBUSY;
1134 }
1135 chip->irq = pci->irq;
1136 card->sync_irq = chip->irq;
1137
1138 card->private_free = snd_intel8x0m_free;
1139
1140 return 0;
1141}
1142
1143static struct shortname_table {
1144 unsigned int id;
1145 const char *s;
1146} shortnames[] = {
1147 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1148 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1149 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1150 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1151 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1152 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1153 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1154 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1155 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1156 { 0x7446, "AMD AMD768" },
1157 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1158 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1159 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1160 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1161 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1162 { 0x746e, "AMD AMD8111" },
1163#if 0
1164 { 0x5455, "ALi M5455" },
1165#endif
1166 { 0 },
1167};
1168
1169static int __snd_intel8x0m_probe(struct pci_dev *pci,
1170 const struct pci_device_id *pci_id)
1171{
1172 struct snd_card *card;
1173 struct intel8x0m *chip;
1174 int err;
1175 struct shortname_table *name;
1176
1177 err = snd_devm_card_new(parent: &pci->dev, idx: index, xid: id, THIS_MODULE,
1178 extra_size: sizeof(*chip), card_ret: &card);
1179 if (err < 0)
1180 return err;
1181 chip = card->private_data;
1182
1183 strscpy(card->driver, "ICH-MODEM");
1184 strscpy(card->shortname, "Intel ICH");
1185 for (name = shortnames; name->id; name++) {
1186 if (pci->device == name->id) {
1187 strscpy(card->shortname, name->s);
1188 break;
1189 }
1190 }
1191 strcat(p: card->shortname,q: " Modem");
1192
1193 err = snd_intel8x0m_init(card, pci, device_type: pci_id->driver_data);
1194 if (err < 0)
1195 return err;
1196
1197 err = snd_intel8x0m_mixer(chip, ac97_clock);
1198 if (err < 0)
1199 return err;
1200 err = snd_intel8x0m_pcm(chip);
1201 if (err < 0)
1202 return err;
1203
1204 snd_intel8x0m_proc_init(chip);
1205
1206 sprintf(buf: card->longname, fmt: "%s at irq %i",
1207 card->shortname, chip->irq);
1208
1209 err = snd_card_register(card);
1210 if (err < 0)
1211 return err;
1212 pci_set_drvdata(pdev: pci, data: card);
1213 return 0;
1214}
1215
1216static int snd_intel8x0m_probe(struct pci_dev *pci,
1217 const struct pci_device_id *pci_id)
1218{
1219 return snd_card_free_on_error(dev: &pci->dev, ret: __snd_intel8x0m_probe(pci, pci_id));
1220}
1221
1222static struct pci_driver intel8x0m_driver = {
1223 .name = KBUILD_MODNAME,
1224 .id_table = snd_intel8x0m_ids,
1225 .probe = snd_intel8x0m_probe,
1226 .driver = {
1227 .pm = &intel8x0m_pm,
1228 },
1229};
1230
1231module_pci_driver(intel8x0m_driver);
1232

source code of linux/sound/pci/intel8x0m.c