1// SPDX-License-Identifier: GPL-2.0
2//
3// Ingenic JZ4760 CODEC driver
4//
5// Copyright (C) 2021, Christophe Branchereau <cbranchereau@gmail.com>
6// Copyright (C) 2021, Paul Cercueil <paul@crapouillou.net>
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/regmap.h>
14#include <linux/time64.h>
15
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18#include <sound/soc-dai.h>
19#include <sound/soc-dapm.h>
20#include <sound/tlv.h>
21
22#define ICDC_RGADW_OFFSET 0x00
23#define ICDC_RGDATA_OFFSET 0x04
24
25/* ICDC internal register access control register(RGADW) */
26#define ICDC_RGADW_RGWR BIT(16)
27#define ICDC_RGADW_RGADDR_MASK GENMASK(14, 8)
28#define ICDC_RGADW_RGDIN_MASK GENMASK(7, 0)
29
30/* ICDC internal register data output register (RGDATA)*/
31#define ICDC_RGDATA_IRQ BIT(8)
32#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, 0)
33
34/* Internal register space, accessed through regmap */
35enum {
36 JZ4760_CODEC_REG_SR,
37 JZ4760_CODEC_REG_AICR,
38 JZ4760_CODEC_REG_CR1,
39 JZ4760_CODEC_REG_CR2,
40 JZ4760_CODEC_REG_CR3,
41 JZ4760_CODEC_REG_CR4,
42 JZ4760_CODEC_REG_CCR1,
43 JZ4760_CODEC_REG_CCR2,
44 JZ4760_CODEC_REG_PMR1,
45 JZ4760_CODEC_REG_PMR2,
46 JZ4760_CODEC_REG_ICR,
47 JZ4760_CODEC_REG_IFR,
48 JZ4760_CODEC_REG_GCR1,
49 JZ4760_CODEC_REG_GCR2,
50 JZ4760_CODEC_REG_GCR3,
51 JZ4760_CODEC_REG_GCR4,
52 JZ4760_CODEC_REG_GCR5,
53 JZ4760_CODEC_REG_GCR6,
54 JZ4760_CODEC_REG_GCR7,
55 JZ4760_CODEC_REG_GCR8,
56 JZ4760_CODEC_REG_GCR9,
57 JZ4760_CODEC_REG_AGC1,
58 JZ4760_CODEC_REG_AGC2,
59 JZ4760_CODEC_REG_AGC3,
60 JZ4760_CODEC_REG_AGC4,
61 JZ4760_CODEC_REG_AGC5,
62 JZ4760_CODEC_REG_MIX1,
63 JZ4760_CODEC_REG_MIX2,
64};
65
66#define REG_AICR_DAC_ADWL_MASK GENMASK(7, 6)
67#define REG_AICR_DAC_SERIAL BIT(3)
68#define REG_AICR_DAC_I2S BIT(1)
69
70#define REG_AICR_ADC_ADWL_MASK GENMASK(5, 4)
71
72#define REG_AICR_ADC_SERIAL BIT(2)
73#define REG_AICR_ADC_I2S BIT(0)
74
75#define REG_CR1_HP_LOAD BIT(7)
76#define REG_CR1_HP_MUTE BIT(5)
77#define REG_CR1_LO_MUTE_OFFSET 4
78#define REG_CR1_BTL_MUTE_OFFSET 3
79#define REG_CR1_OUTSEL_OFFSET 0
80#define REG_CR1_OUTSEL_MASK GENMASK(1, REG_CR1_OUTSEL_OFFSET)
81
82#define REG_CR2_DAC_MONO BIT(7)
83#define REG_CR2_DAC_MUTE BIT(5)
84#define REG_CR2_DAC_NOMAD BIT(1)
85#define REG_CR2_DAC_RIGHT_ONLY BIT(0)
86
87#define REG_CR3_ADC_INSEL_OFFSET 2
88#define REG_CR3_ADC_INSEL_MASK GENMASK(3, REG_CR3_ADC_INSEL_OFFSET)
89#define REG_CR3_MICSTEREO_OFFSET 1
90#define REG_CR3_MICDIFF_OFFSET 0
91
92#define REG_CR4_ADC_HPF_OFFSET 7
93#define REG_CR4_ADC_RIGHT_ONLY BIT(0)
94
95#define REG_CCR1_CRYSTAL_MASK GENMASK(3, 0)
96
97#define REG_CCR2_DAC_FREQ_MASK GENMASK(7, 4)
98#define REG_CCR2_ADC_FREQ_MASK GENMASK(3, 0)
99
100#define REG_PMR1_SB BIT(7)
101#define REG_PMR1_SB_SLEEP BIT(6)
102#define REG_PMR1_SB_AIP_OFFSET 5
103#define REG_PMR1_SB_LINE_OFFSET 4
104#define REG_PMR1_SB_MIC1_OFFSET 3
105#define REG_PMR1_SB_MIC2_OFFSET 2
106#define REG_PMR1_SB_BYPASS_OFFSET 1
107#define REG_PMR1_SB_MICBIAS_OFFSET 0
108
109#define REG_PMR2_SB_ADC_OFFSET 4
110#define REG_PMR2_SB_HP_OFFSET 3
111#define REG_PMR2_SB_BTL_OFFSET 2
112#define REG_PMR2_SB_LOUT_OFFSET 1
113#define REG_PMR2_SB_DAC_OFFSET 0
114
115#define REG_ICR_INT_FORM_MASK GENMASK(7, 6)
116#define REG_ICR_ALL_MASK GENMASK(5, 0)
117#define REG_ICR_JACK_MASK BIT(5)
118#define REG_ICR_SCMC_MASK BIT(4)
119#define REG_ICR_RUP_MASK BIT(3)
120#define REG_ICR_RDO_MASK BIT(2)
121#define REG_ICR_GUP_MASK BIT(1)
122#define REG_ICR_GDO_MASK BIT(0)
123
124#define REG_IFR_ALL_MASK GENMASK(5, 0)
125#define REG_IFR_JACK BIT(6)
126#define REG_IFR_JACK_EVENT BIT(5)
127#define REG_IFR_SCMC BIT(4)
128#define REG_IFR_RUP BIT(3)
129#define REG_IFR_RDO BIT(2)
130#define REG_IFR_GUP BIT(1)
131#define REG_IFR_GDO BIT(0)
132
133#define REG_GCR_GAIN_OFFSET 0
134#define REG_GCR_GAIN_MAX 0x1f
135
136#define REG_GCR_RL BIT(7)
137
138#define REG_GCR_GIM1_MASK GENMASK(5, 3)
139#define REG_GCR_GIM2_MASK GENMASK(2, 0)
140#define REG_GCR_GIM_GAIN_MAX 7
141
142#define REG_AGC1_EN BIT(7)
143#define REG_AGC1_TARGET_MASK GENMASK(5, 2)
144
145#define REG_AGC2_NG_THR_MASK GENMASK(6, 4)
146#define REG_AGC2_HOLD_MASK GENMASK(3, 0)
147
148#define REG_AGC3_ATK_MASK GENMASK(7, 4)
149#define REG_AGC3_DCY_MASK GENMASK(3, 0)
150
151#define REG_AGC4_AGC_MAX_MASK GENMASK(4, 0)
152
153#define REG_AGC5_AGC_MIN_MASK GENMASK(4, 0)
154
155#define REG_MIX1_MIX_REC_MASK GENMASK(7, 6)
156#define REG_MIX1_GIMIX_MASK GENMASK(4, 0)
157
158#define REG_MIX2_DAC_MIX_MASK GENMASK(7, 6)
159#define REG_MIX2_GOMIX_MASK GENMASK(4, 0)
160
161/* codec private data */
162struct jz_codec {
163 struct device *dev;
164 struct regmap *regmap;
165 void __iomem *base;
166 struct clk *clk;
167};
168
169static int jz4760_codec_set_bias_level(struct snd_soc_component *codec,
170 enum snd_soc_bias_level level)
171{
172 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(c: codec);
173 struct regmap *regmap = jz_codec->regmap;
174
175 switch (level) {
176 case SND_SOC_BIAS_PREPARE:
177 /* Reset all interrupt flags. */
178 regmap_write(map: regmap, reg: JZ4760_CODEC_REG_IFR, REG_IFR_ALL_MASK);
179
180 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_PMR1, REG_PMR1_SB);
181 msleep(msecs: 250);
182 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_PMR1, REG_PMR1_SB_SLEEP);
183 msleep(msecs: 400);
184 break;
185 case SND_SOC_BIAS_STANDBY:
186 regmap_set_bits(map: regmap, reg: JZ4760_CODEC_REG_PMR1, REG_PMR1_SB_SLEEP);
187 regmap_set_bits(map: regmap, reg: JZ4760_CODEC_REG_PMR1, REG_PMR1_SB);
188 break;
189 default:
190 break;
191 }
192
193 return 0;
194}
195
196static int jz4760_codec_startup(struct snd_pcm_substream *substream,
197 struct snd_soc_dai *dai)
198{
199 struct snd_soc_component *codec = dai->component;
200 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component: codec);
201 int ret = 0;
202
203 /*
204 * SYSCLK output from the codec to the AIC is required to keep the
205 * DMA transfer going during playback when all audible outputs have
206 * been disabled.
207 */
208 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
209 ret = snd_soc_dapm_force_enable_pin(dapm, pin: "SYSCLK");
210 return ret;
211}
212
213static void jz4760_codec_shutdown(struct snd_pcm_substream *substream,
214 struct snd_soc_dai *dai)
215{
216 struct snd_soc_component *codec = dai->component;
217 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component: codec);
218
219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
220 snd_soc_dapm_disable_pin(dapm, pin: "SYSCLK");
221}
222
223
224static int jz4760_codec_pcm_trigger(struct snd_pcm_substream *substream,
225 int cmd, struct snd_soc_dai *dai)
226{
227 struct snd_soc_component *codec = dai->component;
228 int ret = 0;
229
230 switch (cmd) {
231 case SNDRV_PCM_TRIGGER_START:
232 case SNDRV_PCM_TRIGGER_RESUME:
233 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
234 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
235 snd_soc_component_force_bias_level(component: codec, level: SND_SOC_BIAS_ON);
236 break;
237 case SNDRV_PCM_TRIGGER_STOP:
238 case SNDRV_PCM_TRIGGER_SUSPEND:
239 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
240 /* do nothing */
241 break;
242 default:
243 ret = -EINVAL;
244 }
245
246 return ret;
247}
248
249static int jz4760_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
250{
251 struct snd_soc_component *codec = dai->component;
252 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(c: codec);
253 unsigned int gain_bit = mute ? REG_IFR_GDO : REG_IFR_GUP;
254 unsigned int val, reg;
255 int change, err;
256
257 change = snd_soc_component_update_bits(component: codec, reg: JZ4760_CODEC_REG_CR2,
258 REG_CR2_DAC_MUTE,
259 val: mute ? REG_CR2_DAC_MUTE : 0);
260 if (change == 1) {
261 regmap_read(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_PMR2, val: &val);
262
263 if (val & BIT(REG_PMR2_SB_DAC_OFFSET))
264 return 1;
265
266 err = regmap_read_poll_timeout(jz_codec->regmap,
267 JZ4760_CODEC_REG_IFR,
268 val, val & gain_bit,
269 1000, 1 * USEC_PER_SEC);
270 if (err) {
271 dev_err(jz_codec->dev,
272 "Timeout while setting digital mute: %d", err);
273 return err;
274 }
275
276 /* clear GUP/GDO flag */
277 regmap_write(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_IFR, val: gain_bit);
278 }
279
280 regmap_read(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_CR2, val: &reg);
281
282 return 0;
283}
284
285/* unit: 0.01dB */
286static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 100);
287static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
288static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 100);
289static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0);
290static const DECLARE_TLV_DB_MINMAX(mixer_tlv, -3100, 0);
291
292/* Unconditional controls. */
293static const struct snd_kcontrol_new jz4760_codec_snd_controls[] = {
294 /* record gain control */
295 SOC_DOUBLE_R_TLV("PCM Capture Volume",
296 JZ4760_CODEC_REG_GCR9, JZ4760_CODEC_REG_GCR8,
297 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 0, adc_tlv),
298
299 SOC_DOUBLE_R_TLV("Line In Bypass Playback Volume",
300 JZ4760_CODEC_REG_GCR4, JZ4760_CODEC_REG_GCR3,
301 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, linein_tlv),
302
303 SOC_SINGLE_TLV("Mixer Capture Volume",
304 JZ4760_CODEC_REG_MIX1,
305 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv),
306
307 SOC_SINGLE_TLV("Mixer Playback Volume",
308 JZ4760_CODEC_REG_MIX2,
309 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv),
310
311 SOC_SINGLE("High-Pass Filter Capture Switch",
312 JZ4760_CODEC_REG_CR4,
313 REG_CR4_ADC_HPF_OFFSET, 1, 0),
314};
315
316static const struct snd_kcontrol_new jz4760_codec_pcm_playback_controls[] = {
317 SOC_DAPM_DOUBLE_R_TLV("Volume", JZ4760_CODEC_REG_GCR6, JZ4760_CODEC_REG_GCR5,
318 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, dac_tlv),
319};
320
321static const struct snd_kcontrol_new jz4760_codec_hp_playback_controls[] = {
322 SOC_DAPM_DOUBLE_R_TLV("Volume", JZ4760_CODEC_REG_GCR2, JZ4760_CODEC_REG_GCR1,
323 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, out_tlv),
324};
325
326static int hpout_event(struct snd_soc_dapm_widget *w,
327 struct snd_kcontrol *kcontrol, int event)
328{
329 struct snd_soc_component *codec = snd_soc_dapm_to_component(dapm: w->dapm);
330 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(c: codec);
331 unsigned int val;
332 int err;
333
334 switch (event) {
335 case SND_SOC_DAPM_PRE_PMU:
336 /* unmute HP */
337 regmap_clear_bits(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_CR1,
338 REG_CR1_HP_MUTE);
339 break;
340
341 case SND_SOC_DAPM_POST_PMU:
342 /* wait for ramp-up complete (RUP) */
343 err = regmap_read_poll_timeout(jz_codec->regmap,
344 JZ4760_CODEC_REG_IFR,
345 val, val & REG_IFR_RUP,
346 1000, 1 * USEC_PER_SEC);
347 if (err) {
348 dev_err(jz_codec->dev, "RUP timeout: %d", err);
349 return err;
350 }
351
352 /* clear RUP flag */
353 regmap_set_bits(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_IFR,
354 REG_IFR_RUP);
355
356 break;
357
358 case SND_SOC_DAPM_POST_PMD:
359 /* mute HP */
360 regmap_set_bits(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_CR1,
361 REG_CR1_HP_MUTE);
362
363 err = regmap_read_poll_timeout(jz_codec->regmap,
364 JZ4760_CODEC_REG_IFR,
365 val, val & REG_IFR_RDO,
366 1000, 1 * USEC_PER_SEC);
367 if (err) {
368 dev_err(jz_codec->dev, "RDO timeout: %d", err);
369 return err;
370 }
371
372 /* clear RDO flag */
373 regmap_set_bits(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_IFR,
374 REG_IFR_RDO);
375
376 break;
377 }
378
379 return 0;
380}
381
382static const char * const jz4760_codec_hp_texts[] = {
383 "PCM", "Line In", "Mic 1", "Mic 2"
384};
385
386static const unsigned int jz4760_codec_hp_values[] = { 3, 2, 0, 1 };
387
388static SOC_VALUE_ENUM_SINGLE_DECL(jz4760_codec_hp_enum,
389 JZ4760_CODEC_REG_CR1,
390 REG_CR1_OUTSEL_OFFSET,
391 REG_CR1_OUTSEL_MASK >> REG_CR1_OUTSEL_OFFSET,
392 jz4760_codec_hp_texts,
393 jz4760_codec_hp_values);
394static const struct snd_kcontrol_new jz4760_codec_hp_source =
395 SOC_DAPM_ENUM("Route", jz4760_codec_hp_enum);
396
397static const char * const jz4760_codec_cap_texts[] = {
398 "Line In", "Mic 1", "Mic 2"
399};
400
401static const unsigned int jz4760_codec_cap_values[] = { 2, 0, 1 };
402
403static SOC_VALUE_ENUM_SINGLE_DECL(jz4760_codec_cap_enum,
404 JZ4760_CODEC_REG_CR3,
405 REG_CR3_ADC_INSEL_OFFSET,
406 REG_CR3_ADC_INSEL_MASK >> REG_CR3_ADC_INSEL_OFFSET,
407 jz4760_codec_cap_texts,
408 jz4760_codec_cap_values);
409static const struct snd_kcontrol_new jz4760_codec_cap_source =
410 SOC_DAPM_ENUM("Route", jz4760_codec_cap_enum);
411
412static const struct snd_kcontrol_new jz4760_codec_mic_controls[] = {
413 SOC_DAPM_SINGLE("Stereo Capture Switch", JZ4760_CODEC_REG_CR3,
414 REG_CR3_MICSTEREO_OFFSET, 1, 0),
415};
416
417static const struct snd_kcontrol_new jz4760_codec_line_out_switch =
418 SOC_DAPM_SINGLE("Switch", JZ4760_CODEC_REG_CR1,
419 REG_CR1_LO_MUTE_OFFSET, 0, 0);
420static const struct snd_kcontrol_new jz4760_codec_btl_out_switch =
421 SOC_DAPM_SINGLE("Switch", JZ4760_CODEC_REG_CR1,
422 REG_CR1_BTL_MUTE_OFFSET, 0, 0);
423
424static const struct snd_soc_dapm_widget jz4760_codec_dapm_widgets[] = {
425 SND_SOC_DAPM_PGA_E("HP Out", JZ4760_CODEC_REG_PMR2,
426 REG_PMR2_SB_HP_OFFSET, 1, NULL, 0, hpout_event,
427 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
428 SND_SOC_DAPM_POST_PMD),
429
430 SND_SOC_DAPM_SWITCH("Line Out", JZ4760_CODEC_REG_PMR2,
431 REG_PMR2_SB_LOUT_OFFSET, 1,
432 &jz4760_codec_line_out_switch),
433
434 SND_SOC_DAPM_SWITCH("BTL Out", JZ4760_CODEC_REG_PMR2,
435 REG_PMR2_SB_BTL_OFFSET, 1,
436 &jz4760_codec_btl_out_switch),
437
438 SND_SOC_DAPM_PGA("Line In", JZ4760_CODEC_REG_PMR1,
439 REG_PMR1_SB_LINE_OFFSET, 1, NULL, 0),
440
441 SND_SOC_DAPM_MUX("Headphones Source", SND_SOC_NOPM, 0, 0,
442 &jz4760_codec_hp_source),
443
444 SND_SOC_DAPM_MUX("Capture Source", SND_SOC_NOPM, 0, 0,
445 &jz4760_codec_cap_source),
446
447 SND_SOC_DAPM_PGA("Mic 1", JZ4760_CODEC_REG_PMR1,
448 REG_PMR1_SB_MIC1_OFFSET, 1, NULL, 0),
449
450 SND_SOC_DAPM_PGA("Mic 2", JZ4760_CODEC_REG_PMR1,
451 REG_PMR1_SB_MIC2_OFFSET, 1, NULL, 0),
452
453 SND_SOC_DAPM_PGA("Mic Diff", JZ4760_CODEC_REG_CR3,
454 REG_CR3_MICDIFF_OFFSET, 0, NULL, 0),
455
456 SND_SOC_DAPM_MIXER("Mic", SND_SOC_NOPM, 0, 0,
457 jz4760_codec_mic_controls,
458 ARRAY_SIZE(jz4760_codec_mic_controls)),
459
460 SND_SOC_DAPM_PGA("Line In Bypass", JZ4760_CODEC_REG_PMR1,
461 REG_PMR1_SB_BYPASS_OFFSET, 1, NULL, 0),
462
463 SND_SOC_DAPM_ADC("ADC", "Capture", JZ4760_CODEC_REG_PMR2,
464 REG_PMR2_SB_ADC_OFFSET, 1),
465
466 SND_SOC_DAPM_DAC("DAC", "Playback", JZ4760_CODEC_REG_PMR2,
467 REG_PMR2_SB_DAC_OFFSET, 1),
468
469 SND_SOC_DAPM_MIXER("PCM Playback", SND_SOC_NOPM, 0, 0,
470 jz4760_codec_pcm_playback_controls,
471 ARRAY_SIZE(jz4760_codec_pcm_playback_controls)),
472
473 SND_SOC_DAPM_MIXER("Headphones Playback", SND_SOC_NOPM, 0, 0,
474 jz4760_codec_hp_playback_controls,
475 ARRAY_SIZE(jz4760_codec_hp_playback_controls)),
476
477 SND_SOC_DAPM_SUPPLY("MICBIAS", JZ4760_CODEC_REG_PMR1,
478 REG_PMR1_SB_MICBIAS_OFFSET, 1, NULL, 0),
479
480 SND_SOC_DAPM_INPUT("MIC1P"),
481 SND_SOC_DAPM_INPUT("MIC1N"),
482 SND_SOC_DAPM_INPUT("MIC2P"),
483 SND_SOC_DAPM_INPUT("MIC2N"),
484
485 SND_SOC_DAPM_INPUT("LLINEIN"),
486 SND_SOC_DAPM_INPUT("RLINEIN"),
487
488 SND_SOC_DAPM_OUTPUT("LHPOUT"),
489 SND_SOC_DAPM_OUTPUT("RHPOUT"),
490
491 SND_SOC_DAPM_OUTPUT("LOUT"),
492 SND_SOC_DAPM_OUTPUT("ROUT"),
493
494 SND_SOC_DAPM_OUTPUT("BTLP"),
495 SND_SOC_DAPM_OUTPUT("BTLN"),
496
497 SND_SOC_DAPM_OUTPUT("SYSCLK"),
498};
499
500/* Unconditional routes. */
501static const struct snd_soc_dapm_route jz4760_codec_dapm_routes[] = {
502 { "Mic 1", NULL, "MIC1P" },
503 { "Mic Diff", NULL, "MIC1N" },
504 { "Mic 1", NULL, "Mic Diff" },
505 { "Mic 2", NULL, "MIC2P" },
506 { "Mic Diff", NULL, "MIC2N" },
507 { "Mic 2", NULL, "Mic Diff" },
508
509 { "Line In", NULL, "LLINEIN" },
510 { "Line In", NULL, "RLINEIN" },
511
512 { "Mic", "Stereo Capture Switch", "Mic 1" },
513 { "Mic", "Stereo Capture Switch", "Mic 2" },
514 { "Headphones Source", "Mic 1", "Mic" },
515 { "Headphones Source", "Mic 2", "Mic" },
516 { "Capture Source", "Mic 1", "Mic" },
517 { "Capture Source", "Mic 2", "Mic" },
518
519 { "Capture Source", "Line In", "Line In" },
520 { "Capture Source", "Mic 1", "Mic 1" },
521 { "Capture Source", "Mic 2", "Mic 2" },
522 { "ADC", NULL, "Capture Source" },
523
524 { "Line In Bypass", NULL, "Line In" },
525
526 { "Headphones Source", "Mic 1", "Mic 1" },
527 { "Headphones Source", "Mic 2", "Mic 2" },
528 { "Headphones Source", "Line In", "Line In Bypass" },
529 { "Headphones Source", "PCM", "Headphones Playback" },
530 { "HP Out", NULL, "Headphones Source" },
531
532 { "LHPOUT", NULL, "HP Out" },
533 { "RHPOUT", NULL, "HP Out" },
534 { "Line Out", "Switch", "HP Out" },
535
536 { "LOUT", NULL, "Line Out" },
537 { "ROUT", NULL, "Line Out" },
538 { "BTL Out", "Switch", "Line Out" },
539
540 { "BTLP", NULL, "BTL Out"},
541 { "BTLN", NULL, "BTL Out"},
542
543 { "PCM Playback", "Volume", "DAC" },
544 { "Headphones Playback", "Volume", "PCM Playback" },
545
546 { "SYSCLK", NULL, "DAC" },
547};
548
549static void jz4760_codec_codec_init_regs(struct snd_soc_component *codec)
550{
551 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(c: codec);
552 struct regmap *regmap = jz_codec->regmap;
553
554 /* Collect updates for later sending. */
555 regcache_cache_only(map: regmap, enable: true);
556
557 /* default Amp output to PCM */
558 regmap_set_bits(map: regmap, reg: JZ4760_CODEC_REG_CR1, REG_CR1_OUTSEL_MASK);
559
560 /* Disable stereo mic */
561 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_CR3,
562 BIT(REG_CR3_MICSTEREO_OFFSET));
563
564 /* Set mic 1 as default source for ADC */
565 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_CR3,
566 REG_CR3_ADC_INSEL_MASK);
567
568 /* ADC/DAC: serial + i2s */
569 regmap_set_bits(map: regmap, reg: JZ4760_CODEC_REG_AICR,
570 REG_AICR_ADC_SERIAL | REG_AICR_ADC_I2S |
571 REG_AICR_DAC_SERIAL | REG_AICR_DAC_I2S);
572
573 /* The generated IRQ is a high level */
574 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_ICR, REG_ICR_INT_FORM_MASK);
575 regmap_update_bits(map: regmap, reg: JZ4760_CODEC_REG_ICR, REG_ICR_ALL_MASK,
576 REG_ICR_JACK_MASK | REG_ICR_RUP_MASK |
577 REG_ICR_RDO_MASK | REG_ICR_GUP_MASK |
578 REG_ICR_GDO_MASK);
579
580 /* 12M oscillator */
581 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_CCR1, REG_CCR1_CRYSTAL_MASK);
582
583 /* 0: 16ohm/220uF, 1: 10kohm/1uF */
584 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_CR1, REG_CR1_HP_LOAD);
585
586 /* default to NOMAD */
587 regmap_set_bits(map: jz_codec->regmap, reg: JZ4760_CODEC_REG_CR2,
588 REG_CR2_DAC_NOMAD);
589
590 /* disable automatic gain */
591 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_AGC1, REG_AGC1_EN);
592
593 /* Independent L/R DAC gain control */
594 regmap_clear_bits(map: regmap, reg: JZ4760_CODEC_REG_GCR5,
595 REG_GCR_RL);
596
597 /* Send collected updates. */
598 regcache_cache_only(map: regmap, enable: false);
599 regcache_sync(map: regmap);
600}
601
602static int jz4760_codec_codec_probe(struct snd_soc_component *codec)
603{
604 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(c: codec);
605
606 clk_prepare_enable(clk: jz_codec->clk);
607
608 jz4760_codec_codec_init_regs(codec);
609
610 return 0;
611}
612
613static void jz4760_codec_codec_remove(struct snd_soc_component *codec)
614{
615 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(c: codec);
616
617 clk_disable_unprepare(clk: jz_codec->clk);
618}
619
620static const struct snd_soc_component_driver jz4760_codec_soc_codec_dev = {
621 .probe = jz4760_codec_codec_probe,
622 .remove = jz4760_codec_codec_remove,
623 .set_bias_level = jz4760_codec_set_bias_level,
624 .controls = jz4760_codec_snd_controls,
625 .num_controls = ARRAY_SIZE(jz4760_codec_snd_controls),
626 .dapm_widgets = jz4760_codec_dapm_widgets,
627 .num_dapm_widgets = ARRAY_SIZE(jz4760_codec_dapm_widgets),
628 .dapm_routes = jz4760_codec_dapm_routes,
629 .num_dapm_routes = ARRAY_SIZE(jz4760_codec_dapm_routes),
630 .suspend_bias_off = 1,
631 .use_pmdown_time = 1,
632};
633
634static const unsigned int jz4760_codec_sample_rates[] = {
635 96000, 48000, 44100, 32000,
636 24000, 22050, 16000, 12000,
637 11025, 9600, 8000,
638};
639
640static int jz4760_codec_hw_params(struct snd_pcm_substream *substream,
641 struct snd_pcm_hw_params *params,
642 struct snd_soc_dai *dai)
643{
644 struct jz_codec *codec = snd_soc_component_get_drvdata(c: dai->component);
645 unsigned int rate, bit_width;
646
647 switch (params_format(p: params)) {
648 case SNDRV_PCM_FORMAT_S16_LE:
649 bit_width = 0;
650 break;
651 case SNDRV_PCM_FORMAT_S18_3LE:
652 bit_width = 1;
653 break;
654 case SNDRV_PCM_FORMAT_S20_3LE:
655 bit_width = 2;
656 break;
657 case SNDRV_PCM_FORMAT_S24_3LE:
658 bit_width = 3;
659 break;
660 default:
661 return -EINVAL;
662 }
663
664 for (rate = 0; rate < ARRAY_SIZE(jz4760_codec_sample_rates); rate++) {
665 if (jz4760_codec_sample_rates[rate] == params_rate(p: params))
666 break;
667 }
668
669 if (rate == ARRAY_SIZE(jz4760_codec_sample_rates))
670 return -EINVAL;
671
672 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
673 regmap_update_bits(map: codec->regmap, reg: JZ4760_CODEC_REG_AICR,
674 REG_AICR_DAC_ADWL_MASK,
675 FIELD_PREP(REG_AICR_DAC_ADWL_MASK, bit_width));
676 regmap_update_bits(map: codec->regmap, reg: JZ4760_CODEC_REG_CCR2,
677 REG_CCR2_DAC_FREQ_MASK,
678 FIELD_PREP(REG_CCR2_DAC_FREQ_MASK, rate));
679 } else {
680 regmap_update_bits(map: codec->regmap, reg: JZ4760_CODEC_REG_AICR,
681 REG_AICR_ADC_ADWL_MASK,
682 FIELD_PREP(REG_AICR_ADC_ADWL_MASK, bit_width));
683 regmap_update_bits(map: codec->regmap, reg: JZ4760_CODEC_REG_CCR2,
684 REG_CCR2_ADC_FREQ_MASK,
685 FIELD_PREP(REG_CCR2_ADC_FREQ_MASK, rate));
686 }
687
688 return 0;
689}
690
691static const struct snd_soc_dai_ops jz4760_codec_dai_ops = {
692 .startup = jz4760_codec_startup,
693 .shutdown = jz4760_codec_shutdown,
694 .hw_params = jz4760_codec_hw_params,
695 .trigger = jz4760_codec_pcm_trigger,
696 .mute_stream = jz4760_codec_mute_stream,
697 .no_capture_mute = 1,
698};
699
700#define JZ_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
701 SNDRV_PCM_FMTBIT_S18_3LE | \
702 SNDRV_PCM_FMTBIT_S20_3LE | \
703 SNDRV_PCM_FMTBIT_S24_3LE)
704
705static struct snd_soc_dai_driver jz4760_codec_dai = {
706 .name = "jz4760-hifi",
707 .playback = {
708 .stream_name = "Playback",
709 .channels_min = 2,
710 .channels_max = 2,
711 .rates = SNDRV_PCM_RATE_8000_96000,
712 .formats = JZ_CODEC_FORMATS,
713 },
714 .capture = {
715 .stream_name = "Capture",
716 .channels_min = 2,
717 .channels_max = 2,
718 .rates = SNDRV_PCM_RATE_8000_96000,
719 .formats = JZ_CODEC_FORMATS,
720 },
721 .ops = &jz4760_codec_dai_ops,
722};
723
724static bool jz4760_codec_volatile(struct device *dev, unsigned int reg)
725{
726 return reg == JZ4760_CODEC_REG_SR || reg == JZ4760_CODEC_REG_IFR;
727}
728
729static bool jz4760_codec_writeable(struct device *dev, unsigned int reg)
730{
731 switch (reg) {
732 case JZ4760_CODEC_REG_SR:
733 return false;
734 default:
735 return true;
736 }
737}
738
739static int jz4760_codec_io_wait(struct jz_codec *codec)
740{
741 u32 reg;
742
743 return readl_poll_timeout(codec->base + ICDC_RGADW_OFFSET, reg,
744 !(reg & ICDC_RGADW_RGWR),
745 1000, 1 * USEC_PER_SEC);
746}
747
748static int jz4760_codec_reg_read(void *context, unsigned int reg,
749 unsigned int *val)
750{
751 struct jz_codec *codec = context;
752 unsigned int i;
753 u32 tmp;
754 int ret;
755
756 ret = jz4760_codec_io_wait(codec);
757 if (ret)
758 return ret;
759
760 tmp = readl(addr: codec->base + ICDC_RGADW_OFFSET);
761 tmp &= ~ICDC_RGADW_RGADDR_MASK;
762 tmp |= FIELD_PREP(ICDC_RGADW_RGADDR_MASK, reg);
763 writel(val: tmp, addr: codec->base + ICDC_RGADW_OFFSET);
764
765 /* wait 6+ cycles */
766 for (i = 0; i < 6; i++)
767 *val = readl(addr: codec->base + ICDC_RGDATA_OFFSET) &
768 ICDC_RGDATA_RGDOUT_MASK;
769
770 return 0;
771}
772
773static int jz4760_codec_reg_write(void *context, unsigned int reg,
774 unsigned int val)
775{
776 struct jz_codec *codec = context;
777 int ret;
778
779 ret = jz4760_codec_io_wait(codec);
780 if (ret)
781 return ret;
782
783 writel(ICDC_RGADW_RGWR | FIELD_PREP(ICDC_RGADW_RGADDR_MASK, reg) | val,
784 addr: codec->base + ICDC_RGADW_OFFSET);
785
786 ret = jz4760_codec_io_wait(codec);
787 if (ret)
788 return ret;
789
790 return 0;
791}
792
793static const u8 jz4760_codec_reg_defaults[] = {
794 0x00, 0xFC, 0x1B, 0x20, 0x00, 0x80, 0x00, 0x00,
795 0xFF, 0x1F, 0x3F, 0x00, 0x06, 0x06, 0x06, 0x06,
796 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x07, 0x44,
797 0x1F, 0x00, 0x00, 0x00
798};
799
800static const struct regmap_config jz4760_codec_regmap_config = {
801 .reg_bits = 7,
802 .val_bits = 8,
803
804 .max_register = JZ4760_CODEC_REG_MIX2,
805 .volatile_reg = jz4760_codec_volatile,
806 .writeable_reg = jz4760_codec_writeable,
807
808 .reg_read = jz4760_codec_reg_read,
809 .reg_write = jz4760_codec_reg_write,
810
811 .reg_defaults_raw = jz4760_codec_reg_defaults,
812 .num_reg_defaults_raw = ARRAY_SIZE(jz4760_codec_reg_defaults),
813 .cache_type = REGCACHE_FLAT,
814};
815
816static int jz4760_codec_probe(struct platform_device *pdev)
817{
818 struct device *dev = &pdev->dev;
819 struct jz_codec *codec;
820 int ret;
821
822 codec = devm_kzalloc(dev, size: sizeof(*codec), GFP_KERNEL);
823 if (!codec)
824 return -ENOMEM;
825
826 codec->dev = dev;
827
828 codec->base = devm_platform_ioremap_resource(pdev, index: 0);
829 if (IS_ERR(ptr: codec->base))
830 return PTR_ERR(ptr: codec->base);
831
832 codec->regmap = devm_regmap_init(dev, NULL, codec,
833 &jz4760_codec_regmap_config);
834 if (IS_ERR(ptr: codec->regmap))
835 return PTR_ERR(ptr: codec->regmap);
836
837 codec->clk = devm_clk_get(dev, id: "aic");
838 if (IS_ERR(ptr: codec->clk))
839 return PTR_ERR(ptr: codec->clk);
840
841 platform_set_drvdata(pdev, data: codec);
842
843 ret = devm_snd_soc_register_component(dev, component_driver: &jz4760_codec_soc_codec_dev,
844 dai_drv: &jz4760_codec_dai, num_dai: 1);
845 if (ret) {
846 dev_err(dev, "Failed to register codec: %d\n", ret);
847 return ret;
848 }
849
850 return 0;
851}
852
853static const struct of_device_id jz4760_codec_of_matches[] = {
854 { .compatible = "ingenic,jz4760-codec", },
855 { /* sentinel */ }
856};
857MODULE_DEVICE_TABLE(of, jz4760_codec_of_matches);
858
859static struct platform_driver jz4760_codec_driver = {
860 .probe = jz4760_codec_probe,
861 .driver = {
862 .name = "jz4760-codec",
863 .of_match_table = jz4760_codec_of_matches,
864 },
865};
866module_platform_driver(jz4760_codec_driver);
867
868MODULE_DESCRIPTION("JZ4760 SoC internal codec driver");
869MODULE_AUTHOR("Christophe Branchereau <cbranchereau@gmail.com>");
870MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
871MODULE_LICENSE("GPL v2");
872

source code of linux/sound/soc/codecs/jz4760.c