1//===-- Hexagon.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "Symbols.h"
11#include "SyntheticSections.h"
12#include "Target.h"
13#include "llvm/BinaryFormat/ELF.h"
14#include "llvm/Support/Endian.h"
15
16using namespace llvm;
17using namespace llvm::object;
18using namespace llvm::support::endian;
19using namespace llvm::ELF;
20using namespace lld;
21using namespace lld::elf;
22
23namespace {
24class Hexagon final : public TargetInfo {
25public:
26 Hexagon(Ctx &);
27 uint32_t calcEFlags() const override;
28 RelExpr getRelExpr(RelType type, const Symbol &s,
29 const uint8_t *loc) const override;
30 RelType getDynRel(RelType type) const override;
31 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
32 void relocate(uint8_t *loc, const Relocation &rel,
33 uint64_t val) const override;
34 void writePltHeader(uint8_t *buf) const override;
35 void writePlt(uint8_t *buf, const Symbol &sym,
36 uint64_t pltEntryAddr) const override;
37};
38} // namespace
39
40Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
41 pltRel = R_HEX_JMP_SLOT;
42 relativeRel = R_HEX_RELATIVE;
43 gotRel = R_HEX_GLOB_DAT;
44 symbolicRel = R_HEX_32;
45
46 gotBaseSymInGotPlt = true;
47 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The
48 // next 3 are reserved for the dynamic loader.
49 gotPltHeaderEntriesNum = 4;
50
51 pltEntrySize = 16;
52 pltHeaderSize = 32;
53
54 // Hexagon Linux uses 64K pages by default.
55 defaultMaxPageSize = 0x10000;
56 tlsGotRel = R_HEX_TPREL_32;
57 tlsModuleIndexRel = R_HEX_DTPMOD_32;
58 tlsOffsetRel = R_HEX_DTPREL_32;
59}
60
61uint32_t Hexagon::calcEFlags() const {
62 // The architecture revision must always be equal to or greater than
63 // greatest revision in the list of inputs.
64 std::optional<uint32_t> ret;
65 for (InputFile *f : ctx.objectFiles) {
66 uint32_t eflags = cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
67 if (!ret || eflags > *ret)
68 ret = eflags;
69 }
70 return ret.value_or(/* Default Arch Rev: */ u: EF_HEXAGON_MACH_V68);
71}
72
73static uint32_t applyMask(uint32_t mask, uint32_t data) {
74 uint32_t result = 0;
75 size_t off = 0;
76
77 for (size_t bit = 0; bit != 32; ++bit) {
78 uint32_t valBit = (data >> off) & 1;
79 uint32_t maskBit = (mask >> bit) & 1;
80 if (maskBit) {
81 result |= (valBit << bit);
82 ++off;
83 }
84 }
85 return result;
86}
87
88RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
89 const uint8_t *loc) const {
90 switch (type) {
91 case R_HEX_NONE:
92 return R_NONE;
93 case R_HEX_6_X:
94 case R_HEX_8_X:
95 case R_HEX_9_X:
96 case R_HEX_10_X:
97 case R_HEX_11_X:
98 case R_HEX_12_X:
99 case R_HEX_16_X:
100 case R_HEX_32:
101 case R_HEX_32_6_X:
102 case R_HEX_HI16:
103 case R_HEX_LO16:
104 case R_HEX_DTPREL_32:
105 return R_ABS;
106 case R_HEX_B9_PCREL:
107 case R_HEX_B13_PCREL:
108 case R_HEX_B15_PCREL:
109 case R_HEX_6_PCREL_X:
110 case R_HEX_32_PCREL:
111 return R_PC;
112 case R_HEX_B9_PCREL_X:
113 case R_HEX_B15_PCREL_X:
114 case R_HEX_B22_PCREL:
115 case R_HEX_PLT_B22_PCREL:
116 case R_HEX_B22_PCREL_X:
117 case R_HEX_B32_PCREL_X:
118 case R_HEX_GD_PLT_B22_PCREL:
119 case R_HEX_GD_PLT_B22_PCREL_X:
120 case R_HEX_GD_PLT_B32_PCREL_X:
121 return R_PLT_PC;
122 case R_HEX_IE_32_6_X:
123 case R_HEX_IE_16_X:
124 case R_HEX_IE_HI16:
125 case R_HEX_IE_LO16:
126 return R_GOT;
127 case R_HEX_GD_GOT_11_X:
128 case R_HEX_GD_GOT_16_X:
129 case R_HEX_GD_GOT_32_6_X:
130 return R_TLSGD_GOTPLT;
131 case R_HEX_GOTREL_11_X:
132 case R_HEX_GOTREL_16_X:
133 case R_HEX_GOTREL_32_6_X:
134 case R_HEX_GOTREL_HI16:
135 case R_HEX_GOTREL_LO16:
136 return R_GOTPLTREL;
137 case R_HEX_GOT_11_X:
138 case R_HEX_GOT_16_X:
139 case R_HEX_GOT_32_6_X:
140 return R_GOTPLT;
141 case R_HEX_IE_GOT_11_X:
142 case R_HEX_IE_GOT_16_X:
143 case R_HEX_IE_GOT_32_6_X:
144 case R_HEX_IE_GOT_HI16:
145 case R_HEX_IE_GOT_LO16:
146 return R_GOTPLT;
147 case R_HEX_TPREL_11_X:
148 case R_HEX_TPREL_16:
149 case R_HEX_TPREL_16_X:
150 case R_HEX_TPREL_32_6_X:
151 case R_HEX_TPREL_HI16:
152 case R_HEX_TPREL_LO16:
153 return R_TPREL;
154 default:
155 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
156 << ") against symbol " << &s;
157 return R_NONE;
158 }
159}
160
161// There are (arguably too) many relocation masks for the DSP's
162// R_HEX_6_X type. The table below is used to select the correct mask
163// for the given instruction.
164struct InstructionMask {
165 uint32_t cmpMask;
166 uint32_t relocMask;
167};
168static const InstructionMask r6[] = {
169 {.cmpMask: 0x38000000, .relocMask: 0x0000201f}, {.cmpMask: 0x39000000, .relocMask: 0x0000201f},
170 {.cmpMask: 0x3e000000, .relocMask: 0x00001f80}, {.cmpMask: 0x3f000000, .relocMask: 0x00001f80},
171 {.cmpMask: 0x40000000, .relocMask: 0x000020f8}, {.cmpMask: 0x41000000, .relocMask: 0x000007e0},
172 {.cmpMask: 0x42000000, .relocMask: 0x000020f8}, {.cmpMask: 0x43000000, .relocMask: 0x000007e0},
173 {.cmpMask: 0x44000000, .relocMask: 0x000020f8}, {.cmpMask: 0x45000000, .relocMask: 0x000007e0},
174 {.cmpMask: 0x46000000, .relocMask: 0x000020f8}, {.cmpMask: 0x47000000, .relocMask: 0x000007e0},
175 {.cmpMask: 0x6a000000, .relocMask: 0x00001f80}, {.cmpMask: 0x7c000000, .relocMask: 0x001f2000},
176 {.cmpMask: 0x9a000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9b000000, .relocMask: 0x00000f60},
177 {.cmpMask: 0x9c000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9d000000, .relocMask: 0x00000f60},
178 {.cmpMask: 0x9f000000, .relocMask: 0x001f0100}, {.cmpMask: 0xab000000, .relocMask: 0x0000003f},
179 {.cmpMask: 0xad000000, .relocMask: 0x0000003f}, {.cmpMask: 0xaf000000, .relocMask: 0x00030078},
180 {.cmpMask: 0xd7000000, .relocMask: 0x006020e0}, {.cmpMask: 0xd8000000, .relocMask: 0x006020e0},
181 {.cmpMask: 0xdb000000, .relocMask: 0x006020e0}, {.cmpMask: 0xdf000000, .relocMask: 0x006020e0}};
182
183constexpr uint32_t instParsePacketEnd = 0x0000c000;
184
185static bool isDuplex(uint32_t insn) {
186 // Duplex forms have a fixed mask and parse bits 15:14 are always
187 // zero. Non-duplex insns will always have at least one bit set in the
188 // parse field.
189 return (instParsePacketEnd & insn) == 0;
190}
191
192static uint32_t findMaskR6(Ctx &ctx, uint32_t insn) {
193 if (isDuplex(insn))
194 return 0x03f00000;
195
196 for (InstructionMask i : r6)
197 if ((0xff000000 & insn) == i.cmpMask)
198 return i.relocMask;
199
200 Err(ctx) << "unrecognized instruction for 6_X relocation: 0x"
201 << utohexstr(X: insn, LowerCase: true);
202 return 0;
203}
204
205static uint32_t findMaskR8(uint32_t insn) {
206 if ((0xff000000 & insn) == 0xde000000)
207 return 0x00e020e8;
208 if ((0xff000000 & insn) == 0x3c000000)
209 return 0x0000207f;
210 return 0x00001fe0;
211}
212
213static uint32_t findMaskR11(uint32_t insn) {
214 if ((0xff000000 & insn) == 0xa1000000)
215 return 0x060020ff;
216 return 0x06003fe0;
217}
218
219static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) {
220 if (isDuplex(insn))
221 return 0x03f00000;
222
223 // Clear the end-packet-parse bits:
224 insn = insn & ~instParsePacketEnd;
225
226 if ((0xff000000 & insn) == 0x48000000)
227 return 0x061f20ff;
228 if ((0xff000000 & insn) == 0x49000000)
229 return 0x061f3fe0;
230 if ((0xff000000 & insn) == 0x78000000)
231 return 0x00df3fe0;
232 if ((0xff000000 & insn) == 0xb0000000)
233 return 0x0fe03fe0;
234
235 if ((0xff802000 & insn) == 0x74000000)
236 return 0x00001fe0;
237 if ((0xff802000 & insn) == 0x74002000)
238 return 0x00001fe0;
239 if ((0xff802000 & insn) == 0x74800000)
240 return 0x00001fe0;
241 if ((0xff802000 & insn) == 0x74802000)
242 return 0x00001fe0;
243
244 for (InstructionMask i : r6)
245 if ((0xff000000 & insn) == i.cmpMask)
246 return i.relocMask;
247
248 Err(ctx) << "unrecognized instruction for 16_X type: 0x" << utohexstr(X: insn);
249 return 0;
250}
251
252static void or32le(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) | v); }
253
254void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
255 uint64_t val) const {
256 switch (rel.type) {
257 case R_HEX_NONE:
258 break;
259 case R_HEX_6_PCREL_X:
260 case R_HEX_6_X:
261 or32le(p: loc, v: applyMask(mask: findMaskR6(ctx, insn: read32le(P: loc)), data: val));
262 break;
263 case R_HEX_8_X:
264 or32le(p: loc, v: applyMask(mask: findMaskR8(insn: read32le(P: loc)), data: val));
265 break;
266 case R_HEX_9_X:
267 or32le(p: loc, v: applyMask(mask: 0x00003fe0, data: val & 0x3f));
268 break;
269 case R_HEX_10_X:
270 or32le(p: loc, v: applyMask(mask: 0x00203fe0, data: val & 0x3f));
271 break;
272 case R_HEX_11_X:
273 case R_HEX_GD_GOT_11_X:
274 case R_HEX_IE_GOT_11_X:
275 case R_HEX_GOT_11_X:
276 case R_HEX_GOTREL_11_X:
277 case R_HEX_TPREL_11_X:
278 or32le(p: loc, v: applyMask(mask: findMaskR11(insn: read32le(P: loc)), data: val & 0x3f));
279 break;
280 case R_HEX_12_X:
281 or32le(p: loc, v: applyMask(mask: 0x000007e0, data: val));
282 break;
283 case R_HEX_16_X: // These relocs only have 6 effective bits.
284 case R_HEX_IE_16_X:
285 case R_HEX_IE_GOT_16_X:
286 case R_HEX_GD_GOT_16_X:
287 case R_HEX_GOT_16_X:
288 case R_HEX_GOTREL_16_X:
289 case R_HEX_TPREL_16_X:
290 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0x3f));
291 break;
292 case R_HEX_TPREL_16:
293 or32le(p: loc, v: applyMask(mask: findMaskR16(ctx, insn: read32le(P: loc)), data: val & 0xffff));
294 break;
295 case R_HEX_32:
296 case R_HEX_32_PCREL:
297 case R_HEX_DTPREL_32:
298 or32le(p: loc, v: val);
299 break;
300 case R_HEX_32_6_X:
301 case R_HEX_GD_GOT_32_6_X:
302 case R_HEX_GOT_32_6_X:
303 case R_HEX_GOTREL_32_6_X:
304 case R_HEX_IE_GOT_32_6_X:
305 case R_HEX_IE_32_6_X:
306 case R_HEX_TPREL_32_6_X:
307 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
308 break;
309 case R_HEX_B9_PCREL:
310 checkInt(ctx, loc, v: val, n: 11, rel);
311 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val >> 2));
312 break;
313 case R_HEX_B9_PCREL_X:
314 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val & 0x3f));
315 break;
316 case R_HEX_B13_PCREL:
317 checkInt(ctx, loc, v: val, n: 15, rel);
318 or32le(p: loc, v: applyMask(mask: 0x00202ffe, data: val >> 2));
319 break;
320 case R_HEX_B15_PCREL:
321 checkInt(ctx, loc, v: val, n: 17, rel);
322 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val >> 2));
323 break;
324 case R_HEX_B15_PCREL_X:
325 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val & 0x3f));
326 break;
327 case R_HEX_B22_PCREL:
328 case R_HEX_GD_PLT_B22_PCREL:
329 case R_HEX_PLT_B22_PCREL:
330 checkInt(ctx, loc, v: val, n: 24, rel);
331 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val >> 2));
332 break;
333 case R_HEX_B22_PCREL_X:
334 case R_HEX_GD_PLT_B22_PCREL_X:
335 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val & 0x3f));
336 break;
337 case R_HEX_B32_PCREL_X:
338 case R_HEX_GD_PLT_B32_PCREL_X:
339 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
340 break;
341 case R_HEX_GOTREL_HI16:
342 case R_HEX_HI16:
343 case R_HEX_IE_GOT_HI16:
344 case R_HEX_IE_HI16:
345 case R_HEX_TPREL_HI16:
346 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val >> 16));
347 break;
348 case R_HEX_GOTREL_LO16:
349 case R_HEX_LO16:
350 case R_HEX_IE_GOT_LO16:
351 case R_HEX_IE_LO16:
352 case R_HEX_TPREL_LO16:
353 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val));
354 break;
355 default:
356 llvm_unreachable("unknown relocation");
357 }
358}
359
360void Hexagon::writePltHeader(uint8_t *buf) const {
361 const uint8_t pltData[] = {
362 0x00, 0x40, 0x00, 0x00, // { immext (#0)
363 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
364 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
365 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
366 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
367 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
368 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
369 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
370 };
371 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
372
373 // Offset from PLT0 to the GOT.
374 uint64_t off = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
375 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: off);
376 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: off);
377}
378
379void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
380 uint64_t pltEntryAddr) const {
381 const uint8_t inst[] = {
382 0x00, 0x40, 0x00, 0x00, // { immext (#0)
383 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
384 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
385 0x00, 0xc0, 0x9c, 0x52, // jumpr r28
386 };
387 memcpy(dest: buf, src: inst, n: sizeof(inst));
388
389 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
390 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
391 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
392}
393
394RelType Hexagon::getDynRel(RelType type) const {
395 if (type == R_HEX_32)
396 return type;
397 return R_HEX_NONE;
398}
399
400int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
401 switch (type) {
402 case R_HEX_NONE:
403 case R_HEX_GLOB_DAT:
404 case R_HEX_JMP_SLOT:
405 return 0;
406 case R_HEX_32:
407 case R_HEX_RELATIVE:
408 case R_HEX_DTPMOD_32:
409 case R_HEX_DTPREL_32:
410 case R_HEX_TPREL_32:
411 return SignExtend64<32>(x: read32(ctx, p: buf));
412 default:
413 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
414 return 0;
415 }
416}
417
418void elf::setHexagonTargetInfo(Ctx &ctx) { ctx.target.reset(p: new Hexagon(ctx)); }
419

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source code of lld/ELF/Arch/Hexagon.cpp