1//===-- Hexagon.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "Symbols.h"
11#include "SyntheticSections.h"
12#include "Target.h"
13#include "lld/Common/ErrorHandler.h"
14#include "llvm/BinaryFormat/ELF.h"
15#include "llvm/Support/Endian.h"
16
17using namespace llvm;
18using namespace llvm::object;
19using namespace llvm::support::endian;
20using namespace llvm::ELF;
21using namespace lld;
22using namespace lld::elf;
23
24namespace {
25class Hexagon final : public TargetInfo {
26public:
27 Hexagon();
28 uint32_t calcEFlags() const override;
29 RelExpr getRelExpr(RelType type, const Symbol &s,
30 const uint8_t *loc) const override;
31 RelType getDynRel(RelType type) const override;
32 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
33 void relocate(uint8_t *loc, const Relocation &rel,
34 uint64_t val) const override;
35 void writePltHeader(uint8_t *buf) const override;
36 void writePlt(uint8_t *buf, const Symbol &sym,
37 uint64_t pltEntryAddr) const override;
38};
39} // namespace
40
41Hexagon::Hexagon() {
42 pltRel = R_HEX_JMP_SLOT;
43 relativeRel = R_HEX_RELATIVE;
44 gotRel = R_HEX_GLOB_DAT;
45 symbolicRel = R_HEX_32;
46
47 gotBaseSymInGotPlt = true;
48 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The
49 // next 3 are reserved for the dynamic loader.
50 gotPltHeaderEntriesNum = 4;
51
52 pltEntrySize = 16;
53 pltHeaderSize = 32;
54
55 // Hexagon Linux uses 64K pages by default.
56 defaultMaxPageSize = 0x10000;
57 tlsGotRel = R_HEX_TPREL_32;
58 tlsModuleIndexRel = R_HEX_DTPMOD_32;
59 tlsOffsetRel = R_HEX_DTPREL_32;
60}
61
62uint32_t Hexagon::calcEFlags() const {
63 assert(!ctx.objectFiles.empty());
64
65 // The architecture revision must always be equal to or greater than
66 // greatest revision in the list of inputs.
67 uint32_t ret = 0;
68 for (InputFile *f : ctx.objectFiles) {
69 uint32_t eflags = cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
70 if (eflags > ret)
71 ret = eflags;
72 }
73 return ret;
74}
75
76static uint32_t applyMask(uint32_t mask, uint32_t data) {
77 uint32_t result = 0;
78 size_t off = 0;
79
80 for (size_t bit = 0; bit != 32; ++bit) {
81 uint32_t valBit = (data >> off) & 1;
82 uint32_t maskBit = (mask >> bit) & 1;
83 if (maskBit) {
84 result |= (valBit << bit);
85 ++off;
86 }
87 }
88 return result;
89}
90
91RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
92 const uint8_t *loc) const {
93 switch (type) {
94 case R_HEX_NONE:
95 return R_NONE;
96 case R_HEX_6_X:
97 case R_HEX_8_X:
98 case R_HEX_9_X:
99 case R_HEX_10_X:
100 case R_HEX_11_X:
101 case R_HEX_12_X:
102 case R_HEX_16_X:
103 case R_HEX_32:
104 case R_HEX_32_6_X:
105 case R_HEX_HI16:
106 case R_HEX_LO16:
107 case R_HEX_DTPREL_32:
108 return R_ABS;
109 case R_HEX_B9_PCREL:
110 case R_HEX_B13_PCREL:
111 case R_HEX_B15_PCREL:
112 case R_HEX_6_PCREL_X:
113 case R_HEX_32_PCREL:
114 return R_PC;
115 case R_HEX_B9_PCREL_X:
116 case R_HEX_B15_PCREL_X:
117 case R_HEX_B22_PCREL:
118 case R_HEX_PLT_B22_PCREL:
119 case R_HEX_B22_PCREL_X:
120 case R_HEX_B32_PCREL_X:
121 case R_HEX_GD_PLT_B22_PCREL:
122 case R_HEX_GD_PLT_B22_PCREL_X:
123 case R_HEX_GD_PLT_B32_PCREL_X:
124 return R_PLT_PC;
125 case R_HEX_IE_32_6_X:
126 case R_HEX_IE_16_X:
127 case R_HEX_IE_HI16:
128 case R_HEX_IE_LO16:
129 return R_GOT;
130 case R_HEX_GD_GOT_11_X:
131 case R_HEX_GD_GOT_16_X:
132 case R_HEX_GD_GOT_32_6_X:
133 return R_TLSGD_GOTPLT;
134 case R_HEX_GOTREL_11_X:
135 case R_HEX_GOTREL_16_X:
136 case R_HEX_GOTREL_32_6_X:
137 case R_HEX_GOTREL_HI16:
138 case R_HEX_GOTREL_LO16:
139 return R_GOTPLTREL;
140 case R_HEX_GOT_11_X:
141 case R_HEX_GOT_16_X:
142 case R_HEX_GOT_32_6_X:
143 return R_GOTPLT;
144 case R_HEX_IE_GOT_11_X:
145 case R_HEX_IE_GOT_16_X:
146 case R_HEX_IE_GOT_32_6_X:
147 case R_HEX_IE_GOT_HI16:
148 case R_HEX_IE_GOT_LO16:
149 return R_GOTPLT;
150 case R_HEX_TPREL_11_X:
151 case R_HEX_TPREL_16:
152 case R_HEX_TPREL_16_X:
153 case R_HEX_TPREL_32_6_X:
154 case R_HEX_TPREL_HI16:
155 case R_HEX_TPREL_LO16:
156 return R_TPREL;
157 default:
158 error(msg: getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
159 ") against symbol " + toString(s));
160 return R_NONE;
161 }
162}
163
164// There are (arguably too) many relocation masks for the DSP's
165// R_HEX_6_X type. The table below is used to select the correct mask
166// for the given instruction.
167struct InstructionMask {
168 uint32_t cmpMask;
169 uint32_t relocMask;
170};
171static const InstructionMask r6[] = {
172 {.cmpMask: 0x38000000, .relocMask: 0x0000201f}, {.cmpMask: 0x39000000, .relocMask: 0x0000201f},
173 {.cmpMask: 0x3e000000, .relocMask: 0x00001f80}, {.cmpMask: 0x3f000000, .relocMask: 0x00001f80},
174 {.cmpMask: 0x40000000, .relocMask: 0x000020f8}, {.cmpMask: 0x41000000, .relocMask: 0x000007e0},
175 {.cmpMask: 0x42000000, .relocMask: 0x000020f8}, {.cmpMask: 0x43000000, .relocMask: 0x000007e0},
176 {.cmpMask: 0x44000000, .relocMask: 0x000020f8}, {.cmpMask: 0x45000000, .relocMask: 0x000007e0},
177 {.cmpMask: 0x46000000, .relocMask: 0x000020f8}, {.cmpMask: 0x47000000, .relocMask: 0x000007e0},
178 {.cmpMask: 0x6a000000, .relocMask: 0x00001f80}, {.cmpMask: 0x7c000000, .relocMask: 0x001f2000},
179 {.cmpMask: 0x9a000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9b000000, .relocMask: 0x00000f60},
180 {.cmpMask: 0x9c000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9d000000, .relocMask: 0x00000f60},
181 {.cmpMask: 0x9f000000, .relocMask: 0x001f0100}, {.cmpMask: 0xab000000, .relocMask: 0x0000003f},
182 {.cmpMask: 0xad000000, .relocMask: 0x0000003f}, {.cmpMask: 0xaf000000, .relocMask: 0x00030078},
183 {.cmpMask: 0xd7000000, .relocMask: 0x006020e0}, {.cmpMask: 0xd8000000, .relocMask: 0x006020e0},
184 {.cmpMask: 0xdb000000, .relocMask: 0x006020e0}, {.cmpMask: 0xdf000000, .relocMask: 0x006020e0}};
185
186static bool isDuplex(uint32_t insn) {
187 // Duplex forms have a fixed mask and parse bits 15:14 are always
188 // zero. Non-duplex insns will always have at least one bit set in the
189 // parse field.
190 return (0xC000 & insn) == 0;
191}
192
193static uint32_t findMaskR6(uint32_t insn) {
194 if (isDuplex(insn))
195 return 0x03f00000;
196
197 for (InstructionMask i : r6)
198 if ((0xff000000 & insn) == i.cmpMask)
199 return i.relocMask;
200
201 error(msg: "unrecognized instruction for 6_X relocation: 0x" +
202 utohexstr(X: insn));
203 return 0;
204}
205
206static uint32_t findMaskR8(uint32_t insn) {
207 if ((0xff000000 & insn) == 0xde000000)
208 return 0x00e020e8;
209 if ((0xff000000 & insn) == 0x3c000000)
210 return 0x0000207f;
211 return 0x00001fe0;
212}
213
214static uint32_t findMaskR11(uint32_t insn) {
215 if ((0xff000000 & insn) == 0xa1000000)
216 return 0x060020ff;
217 return 0x06003fe0;
218}
219
220static uint32_t findMaskR16(uint32_t insn) {
221 if ((0xff000000 & insn) == 0x48000000)
222 return 0x061f20ff;
223 if ((0xff000000 & insn) == 0x49000000)
224 return 0x061f3fe0;
225 if ((0xff000000 & insn) == 0x78000000)
226 return 0x00df3fe0;
227 if ((0xff000000 & insn) == 0xb0000000)
228 return 0x0fe03fe0;
229
230 if (isDuplex(insn))
231 return 0x03f00000;
232
233 for (InstructionMask i : r6)
234 if ((0xff000000 & insn) == i.cmpMask)
235 return i.relocMask;
236
237 error(msg: "unrecognized instruction for 16_X type: 0x" +
238 utohexstr(X: insn));
239 return 0;
240}
241
242static void or32le(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) | v); }
243
244void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
245 uint64_t val) const {
246 switch (rel.type) {
247 case R_HEX_NONE:
248 break;
249 case R_HEX_6_PCREL_X:
250 case R_HEX_6_X:
251 or32le(p: loc, v: applyMask(mask: findMaskR6(insn: read32le(P: loc)), data: val));
252 break;
253 case R_HEX_8_X:
254 or32le(p: loc, v: applyMask(mask: findMaskR8(insn: read32le(P: loc)), data: val));
255 break;
256 case R_HEX_9_X:
257 or32le(p: loc, v: applyMask(mask: 0x00003fe0, data: val & 0x3f));
258 break;
259 case R_HEX_10_X:
260 or32le(p: loc, v: applyMask(mask: 0x00203fe0, data: val & 0x3f));
261 break;
262 case R_HEX_11_X:
263 case R_HEX_GD_GOT_11_X:
264 case R_HEX_IE_GOT_11_X:
265 case R_HEX_GOT_11_X:
266 case R_HEX_GOTREL_11_X:
267 case R_HEX_TPREL_11_X:
268 or32le(p: loc, v: applyMask(mask: findMaskR11(insn: read32le(P: loc)), data: val & 0x3f));
269 break;
270 case R_HEX_12_X:
271 or32le(p: loc, v: applyMask(mask: 0x000007e0, data: val));
272 break;
273 case R_HEX_16_X: // These relocs only have 6 effective bits.
274 case R_HEX_IE_16_X:
275 case R_HEX_IE_GOT_16_X:
276 case R_HEX_GD_GOT_16_X:
277 case R_HEX_GOT_16_X:
278 case R_HEX_GOTREL_16_X:
279 case R_HEX_TPREL_16_X:
280 or32le(p: loc, v: applyMask(mask: findMaskR16(insn: read32le(P: loc)), data: val & 0x3f));
281 break;
282 case R_HEX_TPREL_16:
283 or32le(p: loc, v: applyMask(mask: findMaskR16(insn: read32le(P: loc)), data: val & 0xffff));
284 break;
285 case R_HEX_32:
286 case R_HEX_32_PCREL:
287 case R_HEX_DTPREL_32:
288 or32le(p: loc, v: val);
289 break;
290 case R_HEX_32_6_X:
291 case R_HEX_GD_GOT_32_6_X:
292 case R_HEX_GOT_32_6_X:
293 case R_HEX_GOTREL_32_6_X:
294 case R_HEX_IE_GOT_32_6_X:
295 case R_HEX_IE_32_6_X:
296 case R_HEX_TPREL_32_6_X:
297 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
298 break;
299 case R_HEX_B9_PCREL:
300 checkInt(loc, v: val, n: 11, rel);
301 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val >> 2));
302 break;
303 case R_HEX_B9_PCREL_X:
304 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val & 0x3f));
305 break;
306 case R_HEX_B13_PCREL:
307 checkInt(loc, v: val, n: 15, rel);
308 or32le(p: loc, v: applyMask(mask: 0x00202ffe, data: val >> 2));
309 break;
310 case R_HEX_B15_PCREL:
311 checkInt(loc, v: val, n: 17, rel);
312 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val >> 2));
313 break;
314 case R_HEX_B15_PCREL_X:
315 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val & 0x3f));
316 break;
317 case R_HEX_B22_PCREL:
318 case R_HEX_GD_PLT_B22_PCREL:
319 case R_HEX_PLT_B22_PCREL:
320 checkInt(loc, v: val, n: 22, rel);
321 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val >> 2));
322 break;
323 case R_HEX_B22_PCREL_X:
324 case R_HEX_GD_PLT_B22_PCREL_X:
325 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val & 0x3f));
326 break;
327 case R_HEX_B32_PCREL_X:
328 case R_HEX_GD_PLT_B32_PCREL_X:
329 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
330 break;
331 case R_HEX_GOTREL_HI16:
332 case R_HEX_HI16:
333 case R_HEX_IE_GOT_HI16:
334 case R_HEX_IE_HI16:
335 case R_HEX_TPREL_HI16:
336 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val >> 16));
337 break;
338 case R_HEX_GOTREL_LO16:
339 case R_HEX_LO16:
340 case R_HEX_IE_GOT_LO16:
341 case R_HEX_IE_LO16:
342 case R_HEX_TPREL_LO16:
343 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val));
344 break;
345 default:
346 llvm_unreachable("unknown relocation");
347 }
348}
349
350void Hexagon::writePltHeader(uint8_t *buf) const {
351 const uint8_t pltData[] = {
352 0x00, 0x40, 0x00, 0x00, // { immext (#0)
353 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
354 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
355 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
356 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
357 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
358 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
359 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
360 };
361 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
362
363 // Offset from PLT0 to the GOT.
364 uint64_t off = in.gotPlt->getVA() - in.plt->getVA();
365 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: off);
366 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: off);
367}
368
369void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
370 uint64_t pltEntryAddr) const {
371 const uint8_t inst[] = {
372 0x00, 0x40, 0x00, 0x00, // { immext (#0)
373 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
374 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
375 0x00, 0xc0, 0x9c, 0x52, // jumpr r28
376 };
377 memcpy(dest: buf, src: inst, n: sizeof(inst));
378
379 uint64_t gotPltEntryAddr = sym.getGotPltVA();
380 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
381 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
382}
383
384RelType Hexagon::getDynRel(RelType type) const {
385 if (type == R_HEX_32)
386 return type;
387 return R_HEX_NONE;
388}
389
390int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
391 switch (type) {
392 case R_HEX_NONE:
393 case R_HEX_GLOB_DAT:
394 case R_HEX_JMP_SLOT:
395 return 0;
396 case R_HEX_32:
397 case R_HEX_RELATIVE:
398 case R_HEX_DTPMOD_32:
399 case R_HEX_DTPREL_32:
400 case R_HEX_TPREL_32:
401 return SignExtend64<32>(x: read32(p: buf));
402 default:
403 internalLinkerError(loc: getErrorLocation(loc: buf),
404 msg: "cannot read addend for relocation " + toString(type));
405 return 0;
406 }
407}
408
409TargetInfo *elf::getHexagonTargetInfo() {
410 static Hexagon target;
411 return &target;
412}
413

source code of lld/ELF/Arch/Hexagon.cpp