1 | //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | /// \file |
10 | /// |
11 | /// This class has methods called by AMDGPUAsmPrinter to accumulate and print |
12 | /// the PAL metadata. |
13 | // |
14 | //===----------------------------------------------------------------------===// |
15 | // |
16 | |
17 | #include "AMDGPUPALMetadata.h" |
18 | #include "AMDGPUPTNote.h" |
19 | #include "SIDefines.h" |
20 | #include "llvm/BinaryFormat/ELF.h" |
21 | #include "llvm/IR/Constants.h" |
22 | #include "llvm/IR/Module.h" |
23 | #include "llvm/Support/AMDGPUMetadata.h" |
24 | #include "llvm/Support/EndianStream.h" |
25 | |
26 | using namespace llvm; |
27 | using namespace llvm::AMDGPU; |
28 | |
29 | // Read the PAL metadata from IR metadata, where it was put by the frontend. |
30 | void AMDGPUPALMetadata::readFromIR(Module &M) { |
31 | auto NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata.msgpack" ); |
32 | if (NamedMD && NamedMD->getNumOperands()) { |
33 | // This is the new msgpack format for metadata. It is a NamedMD containing |
34 | // an MDTuple containing an MDString containing the msgpack data. |
35 | BlobType = ELF::NT_AMDGPU_METADATA; |
36 | auto MDN = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0)); |
37 | if (MDN && MDN->getNumOperands()) { |
38 | if (auto MDS = dyn_cast<MDString>(Val: MDN->getOperand(I: 0))) |
39 | setFromMsgPackBlob(MDS->getString()); |
40 | } |
41 | return; |
42 | } |
43 | BlobType = ELF::NT_AMD_PAL_METADATA; |
44 | NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata" ); |
45 | if (!NamedMD || !NamedMD->getNumOperands()) { |
46 | // Emit msgpack metadata by default |
47 | BlobType = ELF::NT_AMDGPU_METADATA; |
48 | return; |
49 | } |
50 | // This is the old reg=value pair format for metadata. It is a NamedMD |
51 | // containing an MDTuple containing a number of MDNodes each of which is an |
52 | // integer value, and each two integer values forms a key=value pair that we |
53 | // store as Registers[key]=value in the map. |
54 | auto Tuple = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0)); |
55 | if (!Tuple) |
56 | return; |
57 | for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { |
58 | auto Key = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I)); |
59 | auto Val = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I: I + 1)); |
60 | if (!Key || !Val) |
61 | continue; |
62 | setRegister(Reg: Key->getZExtValue(), Val: Val->getZExtValue()); |
63 | } |
64 | } |
65 | |
66 | // Set PAL metadata from a binary blob from the applicable .note record. |
67 | // Returns false if bad format. Blob must remain valid for the lifetime of the |
68 | // Metadata. |
69 | bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) { |
70 | BlobType = Type; |
71 | if (Type == ELF::NT_AMD_PAL_METADATA) |
72 | return setFromLegacyBlob(Blob); |
73 | return setFromMsgPackBlob(Blob); |
74 | } |
75 | |
76 | // Set PAL metadata from legacy (array of key=value pairs) blob. |
77 | bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) { |
78 | auto Data = reinterpret_cast<const uint32_t *>(Blob.data()); |
79 | for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I) |
80 | setRegister(Reg: Data[I * 2], Val: Data[I * 2 + 1]); |
81 | return true; |
82 | } |
83 | |
84 | // Set PAL metadata from msgpack blob. |
85 | bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) { |
86 | return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false); |
87 | } |
88 | |
89 | // Given the calling convention, calculate the register number for rsrc1. In |
90 | // principle the register number could change in future hardware, but we know |
91 | // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so |
92 | // we can use fixed values. |
93 | static unsigned getRsrc1Reg(CallingConv::ID CC) { |
94 | switch (CC) { |
95 | default: |
96 | return PALMD::R_2E12_COMPUTE_PGM_RSRC1; |
97 | case CallingConv::AMDGPU_LS: |
98 | return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS; |
99 | case CallingConv::AMDGPU_HS: |
100 | return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS; |
101 | case CallingConv::AMDGPU_ES: |
102 | return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES; |
103 | case CallingConv::AMDGPU_GS: |
104 | return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS; |
105 | case CallingConv::AMDGPU_VS: |
106 | return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS; |
107 | case CallingConv::AMDGPU_PS: |
108 | return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS; |
109 | } |
110 | } |
111 | |
112 | // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used |
113 | // with a constant offset to access any non-register shader-specific PAL |
114 | // metadata key. |
115 | static unsigned getScratchSizeKey(CallingConv::ID CC) { |
116 | switch (CC) { |
117 | case CallingConv::AMDGPU_PS: |
118 | return PALMD::Key::PS_SCRATCH_SIZE; |
119 | case CallingConv::AMDGPU_VS: |
120 | return PALMD::Key::VS_SCRATCH_SIZE; |
121 | case CallingConv::AMDGPU_GS: |
122 | return PALMD::Key::GS_SCRATCH_SIZE; |
123 | case CallingConv::AMDGPU_ES: |
124 | return PALMD::Key::ES_SCRATCH_SIZE; |
125 | case CallingConv::AMDGPU_HS: |
126 | return PALMD::Key::HS_SCRATCH_SIZE; |
127 | case CallingConv::AMDGPU_LS: |
128 | return PALMD::Key::LS_SCRATCH_SIZE; |
129 | default: |
130 | return PALMD::Key::CS_SCRATCH_SIZE; |
131 | } |
132 | } |
133 | |
134 | // Set the rsrc1 register in the metadata for a particular shader stage. |
135 | // In fact this ORs the value into any previous setting of the register. |
136 | void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { |
137 | setRegister(Reg: getRsrc1Reg(CC), Val); |
138 | } |
139 | |
140 | // Set the rsrc2 register in the metadata for a particular shader stage. |
141 | // In fact this ORs the value into any previous setting of the register. |
142 | void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { |
143 | setRegister(Reg: getRsrc1Reg(CC) + 1, Val); |
144 | } |
145 | |
146 | // Set the SPI_PS_INPUT_ENA register in the metadata. |
147 | // In fact this ORs the value into any previous setting of the register. |
148 | void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) { |
149 | setRegister(Reg: PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val); |
150 | } |
151 | |
152 | // Set the SPI_PS_INPUT_ADDR register in the metadata. |
153 | // In fact this ORs the value into any previous setting of the register. |
154 | void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) { |
155 | setRegister(Reg: PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val); |
156 | } |
157 | |
158 | // Get a register from the metadata, or 0 if not currently set. |
159 | unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { |
160 | auto Regs = getRegisters(); |
161 | auto It = Regs.find(Key: MsgPackDoc.getNode(V: Reg)); |
162 | if (It == Regs.end()) |
163 | return 0; |
164 | auto N = It->second; |
165 | if (N.getKind() != msgpack::Type::UInt) |
166 | return 0; |
167 | return N.getUInt(); |
168 | } |
169 | |
170 | // Set a register in the metadata. |
171 | // In fact this ORs the value into any previous setting of the register. |
172 | void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) { |
173 | if (!isLegacy()) { |
174 | // In the new MsgPack format, ignore register numbered >= 0x10000000. It |
175 | // is a PAL ABI pseudo-register in the old non-MsgPack format. |
176 | if (Reg >= 0x10000000) |
177 | return; |
178 | } |
179 | auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)]; |
180 | if (N.getKind() == msgpack::Type::UInt) |
181 | Val |= N.getUInt(); |
182 | N = N.getDocument()->getNode(V: Val); |
183 | } |
184 | |
185 | // Set the entry point name for one shader. |
186 | void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) { |
187 | if (isLegacy()) |
188 | return; |
189 | // Msgpack format. |
190 | getHwStage(CC)[".entry_point" ] = MsgPackDoc.getNode(V: Name, /*Copy=*/true); |
191 | } |
192 | |
193 | // Set the number of used vgprs in the metadata. This is an optional |
194 | // advisory record for logging etc; wave dispatch actually uses the rsrc1 |
195 | // register for the shader stage to determine the number of vgprs to |
196 | // allocate. |
197 | void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) { |
198 | if (isLegacy()) { |
199 | // Old non-msgpack format. |
200 | unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + |
201 | PALMD::Key::VS_NUM_USED_VGPRS - |
202 | PALMD::Key::VS_SCRATCH_SIZE; |
203 | setRegister(Reg: NumUsedVgprsKey, Val); |
204 | return; |
205 | } |
206 | // Msgpack format. |
207 | getHwStage(CC)[".vgpr_count" ] = MsgPackDoc.getNode(V: Val); |
208 | } |
209 | |
210 | // Set the number of used agprs in the metadata. |
211 | void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) { |
212 | getHwStage(CC)[".agpr_count" ] = Val; |
213 | } |
214 | |
215 | // Set the number of used sgprs in the metadata. This is an optional advisory |
216 | // record for logging etc; wave dispatch actually uses the rsrc1 register for |
217 | // the shader stage to determine the number of sgprs to allocate. |
218 | void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) { |
219 | if (isLegacy()) { |
220 | // Old non-msgpack format. |
221 | unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + |
222 | PALMD::Key::VS_NUM_USED_SGPRS - |
223 | PALMD::Key::VS_SCRATCH_SIZE; |
224 | setRegister(Reg: NumUsedSgprsKey, Val); |
225 | return; |
226 | } |
227 | // Msgpack format. |
228 | getHwStage(CC)[".sgpr_count" ] = MsgPackDoc.getNode(V: Val); |
229 | } |
230 | |
231 | // Set the scratch size in the metadata. |
232 | void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { |
233 | if (isLegacy()) { |
234 | // Old non-msgpack format. |
235 | setRegister(Reg: getScratchSizeKey(CC), Val); |
236 | return; |
237 | } |
238 | // Msgpack format. |
239 | getHwStage(CC)[".scratch_memory_size" ] = MsgPackDoc.getNode(V: Val); |
240 | } |
241 | |
242 | // Set the stack frame size of a function in the metadata. |
243 | void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) { |
244 | auto Node = getShaderFunction(Name: FnName); |
245 | Node[".stack_frame_size_in_bytes" ] = MsgPackDoc.getNode(V: Val); |
246 | Node[".backend_stack_size" ] = MsgPackDoc.getNode(V: Val); |
247 | } |
248 | |
249 | // Set the amount of LDS used in bytes in the metadata. |
250 | void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) { |
251 | auto Node = getShaderFunction(Name: FnName); |
252 | Node[".lds_size" ] = MsgPackDoc.getNode(V: Val); |
253 | } |
254 | |
255 | // Set the number of used vgprs in the metadata. |
256 | void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName, |
257 | unsigned Val) { |
258 | auto Node = getShaderFunction(Name: FnName); |
259 | Node[".vgpr_count" ] = MsgPackDoc.getNode(V: Val); |
260 | } |
261 | |
262 | // Set the number of used vgprs in the metadata. |
263 | void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName, |
264 | unsigned Val) { |
265 | auto Node = getShaderFunction(Name: FnName); |
266 | Node[".sgpr_count" ] = MsgPackDoc.getNode(V: Val); |
267 | } |
268 | |
269 | // Set the hardware register bit in PAL metadata to enable wave32 on the |
270 | // shader of the given calling convention. |
271 | void AMDGPUPALMetadata::setWave32(unsigned CC) { |
272 | switch (CC) { |
273 | case CallingConv::AMDGPU_HS: |
274 | setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1)); |
275 | break; |
276 | case CallingConv::AMDGPU_GS: |
277 | setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1)); |
278 | break; |
279 | case CallingConv::AMDGPU_VS: |
280 | setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1)); |
281 | break; |
282 | case CallingConv::AMDGPU_PS: |
283 | setRegister(Reg: PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1)); |
284 | break; |
285 | case CallingConv::AMDGPU_CS: |
286 | setRegister(Reg: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, |
287 | S_00B800_CS_W32_EN(1)); |
288 | break; |
289 | } |
290 | } |
291 | |
292 | // Convert a register number to name, for display by toString(). |
293 | // Returns nullptr if none. |
294 | static const char *getRegisterName(unsigned RegNum) { |
295 | // Table of registers. |
296 | static const struct RegInfo { |
297 | unsigned Num; |
298 | const char *Name; |
299 | } RegInfoTable[] = { |
300 | // Registers that code generation sets/modifies metadata for. |
301 | {.Num: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, .Name: "SPI_SHADER_PGM_RSRC1_VS" }, |
302 | {.Num: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, .Name: "SPI_SHADER_PGM_RSRC2_VS" }, |
303 | {.Num: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, .Name: "SPI_SHADER_PGM_RSRC1_LS" }, |
304 | {.Num: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, .Name: "SPI_SHADER_PGM_RSRC2_LS" }, |
305 | {.Num: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, .Name: "SPI_SHADER_PGM_RSRC1_HS" }, |
306 | {.Num: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, .Name: "SPI_SHADER_PGM_RSRC2_HS" }, |
307 | {.Num: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, .Name: "SPI_SHADER_PGM_RSRC1_ES" }, |
308 | {.Num: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, .Name: "SPI_SHADER_PGM_RSRC2_ES" }, |
309 | {.Num: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, .Name: "SPI_SHADER_PGM_RSRC1_GS" }, |
310 | {.Num: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, .Name: "SPI_SHADER_PGM_RSRC2_GS" }, |
311 | {.Num: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, .Name: "COMPUTE_DISPATCH_INITIATOR" }, |
312 | {.Num: PALMD::R_2E12_COMPUTE_PGM_RSRC1, .Name: "COMPUTE_PGM_RSRC1" }, |
313 | {.Num: PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, .Name: "COMPUTE_PGM_RSRC2" }, |
314 | {.Num: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, .Name: "SPI_SHADER_PGM_RSRC1_PS" }, |
315 | {.Num: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, .Name: "SPI_SHADER_PGM_RSRC2_PS" }, |
316 | {.Num: PALMD::R_A1B3_SPI_PS_INPUT_ENA, .Name: "SPI_PS_INPUT_ENA" }, |
317 | {.Num: PALMD::R_A1B4_SPI_PS_INPUT_ADDR, .Name: "SPI_PS_INPUT_ADDR" }, |
318 | {.Num: PALMD::R_A1B6_SPI_PS_IN_CONTROL, .Name: "SPI_PS_IN_CONTROL" }, |
319 | {.Num: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, .Name: "VGT_SHADER_STAGES_EN" }, |
320 | |
321 | // Registers not known to code generation. |
322 | {.Num: 0x2c07, .Name: "SPI_SHADER_PGM_RSRC3_PS" }, |
323 | {.Num: 0x2c46, .Name: "SPI_SHADER_PGM_RSRC3_VS" }, |
324 | {.Num: 0x2c87, .Name: "SPI_SHADER_PGM_RSRC3_GS" }, |
325 | {.Num: 0x2cc7, .Name: "SPI_SHADER_PGM_RSRC3_ES" }, |
326 | {.Num: 0x2d07, .Name: "SPI_SHADER_PGM_RSRC3_HS" }, |
327 | {.Num: 0x2d47, .Name: "SPI_SHADER_PGM_RSRC3_LS" }, |
328 | |
329 | {.Num: 0xa1c3, .Name: "SPI_SHADER_POS_FORMAT" }, |
330 | {.Num: 0xa1b1, .Name: "SPI_VS_OUT_CONFIG" }, |
331 | {.Num: 0xa207, .Name: "PA_CL_VS_OUT_CNTL" }, |
332 | {.Num: 0xa204, .Name: "PA_CL_CLIP_CNTL" }, |
333 | {.Num: 0xa206, .Name: "PA_CL_VTE_CNTL" }, |
334 | {.Num: 0xa2f9, .Name: "PA_SU_VTX_CNTL" }, |
335 | {.Num: 0xa293, .Name: "PA_SC_MODE_CNTL_1" }, |
336 | {.Num: 0xa2a1, .Name: "VGT_PRIMITIVEID_EN" }, |
337 | {.Num: 0x2c81, .Name: "SPI_SHADER_PGM_RSRC4_GS" }, |
338 | {.Num: 0x2e18, .Name: "COMPUTE_TMPRING_SIZE" }, |
339 | {.Num: 0xa1b5, .Name: "SPI_INTERP_CONTROL_0" }, |
340 | {.Num: 0xa1ba, .Name: "SPI_TMPRING_SIZE" }, |
341 | {.Num: 0xa1c4, .Name: "SPI_SHADER_Z_FORMAT" }, |
342 | {.Num: 0xa1c5, .Name: "SPI_SHADER_COL_FORMAT" }, |
343 | {.Num: 0xa203, .Name: "DB_SHADER_CONTROL" }, |
344 | {.Num: 0xa08f, .Name: "CB_SHADER_MASK" }, |
345 | {.Num: 0xa191, .Name: "SPI_PS_INPUT_CNTL_0" }, |
346 | {.Num: 0xa192, .Name: "SPI_PS_INPUT_CNTL_1" }, |
347 | {.Num: 0xa193, .Name: "SPI_PS_INPUT_CNTL_2" }, |
348 | {.Num: 0xa194, .Name: "SPI_PS_INPUT_CNTL_3" }, |
349 | {.Num: 0xa195, .Name: "SPI_PS_INPUT_CNTL_4" }, |
350 | {.Num: 0xa196, .Name: "SPI_PS_INPUT_CNTL_5" }, |
351 | {.Num: 0xa197, .Name: "SPI_PS_INPUT_CNTL_6" }, |
352 | {.Num: 0xa198, .Name: "SPI_PS_INPUT_CNTL_7" }, |
353 | {.Num: 0xa199, .Name: "SPI_PS_INPUT_CNTL_8" }, |
354 | {.Num: 0xa19a, .Name: "SPI_PS_INPUT_CNTL_9" }, |
355 | {.Num: 0xa19b, .Name: "SPI_PS_INPUT_CNTL_10" }, |
356 | {.Num: 0xa19c, .Name: "SPI_PS_INPUT_CNTL_11" }, |
357 | {.Num: 0xa19d, .Name: "SPI_PS_INPUT_CNTL_12" }, |
358 | {.Num: 0xa19e, .Name: "SPI_PS_INPUT_CNTL_13" }, |
359 | {.Num: 0xa19f, .Name: "SPI_PS_INPUT_CNTL_14" }, |
360 | {.Num: 0xa1a0, .Name: "SPI_PS_INPUT_CNTL_15" }, |
361 | {.Num: 0xa1a1, .Name: "SPI_PS_INPUT_CNTL_16" }, |
362 | {.Num: 0xa1a2, .Name: "SPI_PS_INPUT_CNTL_17" }, |
363 | {.Num: 0xa1a3, .Name: "SPI_PS_INPUT_CNTL_18" }, |
364 | {.Num: 0xa1a4, .Name: "SPI_PS_INPUT_CNTL_19" }, |
365 | {.Num: 0xa1a5, .Name: "SPI_PS_INPUT_CNTL_20" }, |
366 | {.Num: 0xa1a6, .Name: "SPI_PS_INPUT_CNTL_21" }, |
367 | {.Num: 0xa1a7, .Name: "SPI_PS_INPUT_CNTL_22" }, |
368 | {.Num: 0xa1a8, .Name: "SPI_PS_INPUT_CNTL_23" }, |
369 | {.Num: 0xa1a9, .Name: "SPI_PS_INPUT_CNTL_24" }, |
370 | {.Num: 0xa1aa, .Name: "SPI_PS_INPUT_CNTL_25" }, |
371 | {.Num: 0xa1ab, .Name: "SPI_PS_INPUT_CNTL_26" }, |
372 | {.Num: 0xa1ac, .Name: "SPI_PS_INPUT_CNTL_27" }, |
373 | {.Num: 0xa1ad, .Name: "SPI_PS_INPUT_CNTL_28" }, |
374 | {.Num: 0xa1ae, .Name: "SPI_PS_INPUT_CNTL_29" }, |
375 | {.Num: 0xa1af, .Name: "SPI_PS_INPUT_CNTL_30" }, |
376 | {.Num: 0xa1b0, .Name: "SPI_PS_INPUT_CNTL_31" }, |
377 | |
378 | {.Num: 0xa2ce, .Name: "VGT_GS_MAX_VERT_OUT" }, |
379 | {.Num: 0xa2ab, .Name: "VGT_ESGS_RING_ITEMSIZE" }, |
380 | {.Num: 0xa290, .Name: "VGT_GS_MODE" }, |
381 | {.Num: 0xa291, .Name: "VGT_GS_ONCHIP_CNTL" }, |
382 | {.Num: 0xa2d7, .Name: "VGT_GS_VERT_ITEMSIZE" }, |
383 | {.Num: 0xa2d8, .Name: "VGT_GS_VERT_ITEMSIZE_1" }, |
384 | {.Num: 0xa2d9, .Name: "VGT_GS_VERT_ITEMSIZE_2" }, |
385 | {.Num: 0xa2da, .Name: "VGT_GS_VERT_ITEMSIZE_3" }, |
386 | {.Num: 0xa298, .Name: "VGT_GSVS_RING_OFFSET_1" }, |
387 | {.Num: 0xa299, .Name: "VGT_GSVS_RING_OFFSET_2" }, |
388 | {.Num: 0xa29a, .Name: "VGT_GSVS_RING_OFFSET_3" }, |
389 | |
390 | {.Num: 0xa2e4, .Name: "VGT_GS_INSTANCE_CNT" }, |
391 | {.Num: 0xa297, .Name: "VGT_GS_PER_VS" }, |
392 | {.Num: 0xa29b, .Name: "VGT_GS_OUT_PRIM_TYPE" }, |
393 | {.Num: 0xa2ac, .Name: "VGT_GSVS_RING_ITEMSIZE" }, |
394 | |
395 | {.Num: 0xa2ad, .Name: "VGT_REUSE_OFF" }, |
396 | {.Num: 0xa1b8, .Name: "SPI_BARYC_CNTL" }, |
397 | |
398 | {.Num: 0x2c4c, .Name: "SPI_SHADER_USER_DATA_VS_0" }, |
399 | {.Num: 0x2c4d, .Name: "SPI_SHADER_USER_DATA_VS_1" }, |
400 | {.Num: 0x2c4e, .Name: "SPI_SHADER_USER_DATA_VS_2" }, |
401 | {.Num: 0x2c4f, .Name: "SPI_SHADER_USER_DATA_VS_3" }, |
402 | {.Num: 0x2c50, .Name: "SPI_SHADER_USER_DATA_VS_4" }, |
403 | {.Num: 0x2c51, .Name: "SPI_SHADER_USER_DATA_VS_5" }, |
404 | {.Num: 0x2c52, .Name: "SPI_SHADER_USER_DATA_VS_6" }, |
405 | {.Num: 0x2c53, .Name: "SPI_SHADER_USER_DATA_VS_7" }, |
406 | {.Num: 0x2c54, .Name: "SPI_SHADER_USER_DATA_VS_8" }, |
407 | {.Num: 0x2c55, .Name: "SPI_SHADER_USER_DATA_VS_9" }, |
408 | {.Num: 0x2c56, .Name: "SPI_SHADER_USER_DATA_VS_10" }, |
409 | {.Num: 0x2c57, .Name: "SPI_SHADER_USER_DATA_VS_11" }, |
410 | {.Num: 0x2c58, .Name: "SPI_SHADER_USER_DATA_VS_12" }, |
411 | {.Num: 0x2c59, .Name: "SPI_SHADER_USER_DATA_VS_13" }, |
412 | {.Num: 0x2c5a, .Name: "SPI_SHADER_USER_DATA_VS_14" }, |
413 | {.Num: 0x2c5b, .Name: "SPI_SHADER_USER_DATA_VS_15" }, |
414 | {.Num: 0x2c5c, .Name: "SPI_SHADER_USER_DATA_VS_16" }, |
415 | {.Num: 0x2c5d, .Name: "SPI_SHADER_USER_DATA_VS_17" }, |
416 | {.Num: 0x2c5e, .Name: "SPI_SHADER_USER_DATA_VS_18" }, |
417 | {.Num: 0x2c5f, .Name: "SPI_SHADER_USER_DATA_VS_19" }, |
418 | {.Num: 0x2c60, .Name: "SPI_SHADER_USER_DATA_VS_20" }, |
419 | {.Num: 0x2c61, .Name: "SPI_SHADER_USER_DATA_VS_21" }, |
420 | {.Num: 0x2c62, .Name: "SPI_SHADER_USER_DATA_VS_22" }, |
421 | {.Num: 0x2c63, .Name: "SPI_SHADER_USER_DATA_VS_23" }, |
422 | {.Num: 0x2c64, .Name: "SPI_SHADER_USER_DATA_VS_24" }, |
423 | {.Num: 0x2c65, .Name: "SPI_SHADER_USER_DATA_VS_25" }, |
424 | {.Num: 0x2c66, .Name: "SPI_SHADER_USER_DATA_VS_26" }, |
425 | {.Num: 0x2c67, .Name: "SPI_SHADER_USER_DATA_VS_27" }, |
426 | {.Num: 0x2c68, .Name: "SPI_SHADER_USER_DATA_VS_28" }, |
427 | {.Num: 0x2c69, .Name: "SPI_SHADER_USER_DATA_VS_29" }, |
428 | {.Num: 0x2c6a, .Name: "SPI_SHADER_USER_DATA_VS_30" }, |
429 | {.Num: 0x2c6b, .Name: "SPI_SHADER_USER_DATA_VS_31" }, |
430 | |
431 | {.Num: 0x2c8c, .Name: "SPI_SHADER_USER_DATA_GS_0" }, |
432 | {.Num: 0x2c8d, .Name: "SPI_SHADER_USER_DATA_GS_1" }, |
433 | {.Num: 0x2c8e, .Name: "SPI_SHADER_USER_DATA_GS_2" }, |
434 | {.Num: 0x2c8f, .Name: "SPI_SHADER_USER_DATA_GS_3" }, |
435 | {.Num: 0x2c90, .Name: "SPI_SHADER_USER_DATA_GS_4" }, |
436 | {.Num: 0x2c91, .Name: "SPI_SHADER_USER_DATA_GS_5" }, |
437 | {.Num: 0x2c92, .Name: "SPI_SHADER_USER_DATA_GS_6" }, |
438 | {.Num: 0x2c93, .Name: "SPI_SHADER_USER_DATA_GS_7" }, |
439 | {.Num: 0x2c94, .Name: "SPI_SHADER_USER_DATA_GS_8" }, |
440 | {.Num: 0x2c95, .Name: "SPI_SHADER_USER_DATA_GS_9" }, |
441 | {.Num: 0x2c96, .Name: "SPI_SHADER_USER_DATA_GS_10" }, |
442 | {.Num: 0x2c97, .Name: "SPI_SHADER_USER_DATA_GS_11" }, |
443 | {.Num: 0x2c98, .Name: "SPI_SHADER_USER_DATA_GS_12" }, |
444 | {.Num: 0x2c99, .Name: "SPI_SHADER_USER_DATA_GS_13" }, |
445 | {.Num: 0x2c9a, .Name: "SPI_SHADER_USER_DATA_GS_14" }, |
446 | {.Num: 0x2c9b, .Name: "SPI_SHADER_USER_DATA_GS_15" }, |
447 | {.Num: 0x2c9c, .Name: "SPI_SHADER_USER_DATA_GS_16" }, |
448 | {.Num: 0x2c9d, .Name: "SPI_SHADER_USER_DATA_GS_17" }, |
449 | {.Num: 0x2c9e, .Name: "SPI_SHADER_USER_DATA_GS_18" }, |
450 | {.Num: 0x2c9f, .Name: "SPI_SHADER_USER_DATA_GS_19" }, |
451 | {.Num: 0x2ca0, .Name: "SPI_SHADER_USER_DATA_GS_20" }, |
452 | {.Num: 0x2ca1, .Name: "SPI_SHADER_USER_DATA_GS_21" }, |
453 | {.Num: 0x2ca2, .Name: "SPI_SHADER_USER_DATA_GS_22" }, |
454 | {.Num: 0x2ca3, .Name: "SPI_SHADER_USER_DATA_GS_23" }, |
455 | {.Num: 0x2ca4, .Name: "SPI_SHADER_USER_DATA_GS_24" }, |
456 | {.Num: 0x2ca5, .Name: "SPI_SHADER_USER_DATA_GS_25" }, |
457 | {.Num: 0x2ca6, .Name: "SPI_SHADER_USER_DATA_GS_26" }, |
458 | {.Num: 0x2ca7, .Name: "SPI_SHADER_USER_DATA_GS_27" }, |
459 | {.Num: 0x2ca8, .Name: "SPI_SHADER_USER_DATA_GS_28" }, |
460 | {.Num: 0x2ca9, .Name: "SPI_SHADER_USER_DATA_GS_29" }, |
461 | {.Num: 0x2caa, .Name: "SPI_SHADER_USER_DATA_GS_30" }, |
462 | {.Num: 0x2cab, .Name: "SPI_SHADER_USER_DATA_GS_31" }, |
463 | |
464 | {.Num: 0x2ccc, .Name: "SPI_SHADER_USER_DATA_ES_0" }, |
465 | {.Num: 0x2ccd, .Name: "SPI_SHADER_USER_DATA_ES_1" }, |
466 | {.Num: 0x2cce, .Name: "SPI_SHADER_USER_DATA_ES_2" }, |
467 | {.Num: 0x2ccf, .Name: "SPI_SHADER_USER_DATA_ES_3" }, |
468 | {.Num: 0x2cd0, .Name: "SPI_SHADER_USER_DATA_ES_4" }, |
469 | {.Num: 0x2cd1, .Name: "SPI_SHADER_USER_DATA_ES_5" }, |
470 | {.Num: 0x2cd2, .Name: "SPI_SHADER_USER_DATA_ES_6" }, |
471 | {.Num: 0x2cd3, .Name: "SPI_SHADER_USER_DATA_ES_7" }, |
472 | {.Num: 0x2cd4, .Name: "SPI_SHADER_USER_DATA_ES_8" }, |
473 | {.Num: 0x2cd5, .Name: "SPI_SHADER_USER_DATA_ES_9" }, |
474 | {.Num: 0x2cd6, .Name: "SPI_SHADER_USER_DATA_ES_10" }, |
475 | {.Num: 0x2cd7, .Name: "SPI_SHADER_USER_DATA_ES_11" }, |
476 | {.Num: 0x2cd8, .Name: "SPI_SHADER_USER_DATA_ES_12" }, |
477 | {.Num: 0x2cd9, .Name: "SPI_SHADER_USER_DATA_ES_13" }, |
478 | {.Num: 0x2cda, .Name: "SPI_SHADER_USER_DATA_ES_14" }, |
479 | {.Num: 0x2cdb, .Name: "SPI_SHADER_USER_DATA_ES_15" }, |
480 | {.Num: 0x2cdc, .Name: "SPI_SHADER_USER_DATA_ES_16" }, |
481 | {.Num: 0x2cdd, .Name: "SPI_SHADER_USER_DATA_ES_17" }, |
482 | {.Num: 0x2cde, .Name: "SPI_SHADER_USER_DATA_ES_18" }, |
483 | {.Num: 0x2cdf, .Name: "SPI_SHADER_USER_DATA_ES_19" }, |
484 | {.Num: 0x2ce0, .Name: "SPI_SHADER_USER_DATA_ES_20" }, |
485 | {.Num: 0x2ce1, .Name: "SPI_SHADER_USER_DATA_ES_21" }, |
486 | {.Num: 0x2ce2, .Name: "SPI_SHADER_USER_DATA_ES_22" }, |
487 | {.Num: 0x2ce3, .Name: "SPI_SHADER_USER_DATA_ES_23" }, |
488 | {.Num: 0x2ce4, .Name: "SPI_SHADER_USER_DATA_ES_24" }, |
489 | {.Num: 0x2ce5, .Name: "SPI_SHADER_USER_DATA_ES_25" }, |
490 | {.Num: 0x2ce6, .Name: "SPI_SHADER_USER_DATA_ES_26" }, |
491 | {.Num: 0x2ce7, .Name: "SPI_SHADER_USER_DATA_ES_27" }, |
492 | {.Num: 0x2ce8, .Name: "SPI_SHADER_USER_DATA_ES_28" }, |
493 | {.Num: 0x2ce9, .Name: "SPI_SHADER_USER_DATA_ES_29" }, |
494 | {.Num: 0x2cea, .Name: "SPI_SHADER_USER_DATA_ES_30" }, |
495 | {.Num: 0x2ceb, .Name: "SPI_SHADER_USER_DATA_ES_31" }, |
496 | |
497 | {.Num: 0x2c0c, .Name: "SPI_SHADER_USER_DATA_PS_0" }, |
498 | {.Num: 0x2c0d, .Name: "SPI_SHADER_USER_DATA_PS_1" }, |
499 | {.Num: 0x2c0e, .Name: "SPI_SHADER_USER_DATA_PS_2" }, |
500 | {.Num: 0x2c0f, .Name: "SPI_SHADER_USER_DATA_PS_3" }, |
501 | {.Num: 0x2c10, .Name: "SPI_SHADER_USER_DATA_PS_4" }, |
502 | {.Num: 0x2c11, .Name: "SPI_SHADER_USER_DATA_PS_5" }, |
503 | {.Num: 0x2c12, .Name: "SPI_SHADER_USER_DATA_PS_6" }, |
504 | {.Num: 0x2c13, .Name: "SPI_SHADER_USER_DATA_PS_7" }, |
505 | {.Num: 0x2c14, .Name: "SPI_SHADER_USER_DATA_PS_8" }, |
506 | {.Num: 0x2c15, .Name: "SPI_SHADER_USER_DATA_PS_9" }, |
507 | {.Num: 0x2c16, .Name: "SPI_SHADER_USER_DATA_PS_10" }, |
508 | {.Num: 0x2c17, .Name: "SPI_SHADER_USER_DATA_PS_11" }, |
509 | {.Num: 0x2c18, .Name: "SPI_SHADER_USER_DATA_PS_12" }, |
510 | {.Num: 0x2c19, .Name: "SPI_SHADER_USER_DATA_PS_13" }, |
511 | {.Num: 0x2c1a, .Name: "SPI_SHADER_USER_DATA_PS_14" }, |
512 | {.Num: 0x2c1b, .Name: "SPI_SHADER_USER_DATA_PS_15" }, |
513 | {.Num: 0x2c1c, .Name: "SPI_SHADER_USER_DATA_PS_16" }, |
514 | {.Num: 0x2c1d, .Name: "SPI_SHADER_USER_DATA_PS_17" }, |
515 | {.Num: 0x2c1e, .Name: "SPI_SHADER_USER_DATA_PS_18" }, |
516 | {.Num: 0x2c1f, .Name: "SPI_SHADER_USER_DATA_PS_19" }, |
517 | {.Num: 0x2c20, .Name: "SPI_SHADER_USER_DATA_PS_20" }, |
518 | {.Num: 0x2c21, .Name: "SPI_SHADER_USER_DATA_PS_21" }, |
519 | {.Num: 0x2c22, .Name: "SPI_SHADER_USER_DATA_PS_22" }, |
520 | {.Num: 0x2c23, .Name: "SPI_SHADER_USER_DATA_PS_23" }, |
521 | {.Num: 0x2c24, .Name: "SPI_SHADER_USER_DATA_PS_24" }, |
522 | {.Num: 0x2c25, .Name: "SPI_SHADER_USER_DATA_PS_25" }, |
523 | {.Num: 0x2c26, .Name: "SPI_SHADER_USER_DATA_PS_26" }, |
524 | {.Num: 0x2c27, .Name: "SPI_SHADER_USER_DATA_PS_27" }, |
525 | {.Num: 0x2c28, .Name: "SPI_SHADER_USER_DATA_PS_28" }, |
526 | {.Num: 0x2c29, .Name: "SPI_SHADER_USER_DATA_PS_29" }, |
527 | {.Num: 0x2c2a, .Name: "SPI_SHADER_USER_DATA_PS_30" }, |
528 | {.Num: 0x2c2b, .Name: "SPI_SHADER_USER_DATA_PS_31" }, |
529 | |
530 | {.Num: 0x2e40, .Name: "COMPUTE_USER_DATA_0" }, |
531 | {.Num: 0x2e41, .Name: "COMPUTE_USER_DATA_1" }, |
532 | {.Num: 0x2e42, .Name: "COMPUTE_USER_DATA_2" }, |
533 | {.Num: 0x2e43, .Name: "COMPUTE_USER_DATA_3" }, |
534 | {.Num: 0x2e44, .Name: "COMPUTE_USER_DATA_4" }, |
535 | {.Num: 0x2e45, .Name: "COMPUTE_USER_DATA_5" }, |
536 | {.Num: 0x2e46, .Name: "COMPUTE_USER_DATA_6" }, |
537 | {.Num: 0x2e47, .Name: "COMPUTE_USER_DATA_7" }, |
538 | {.Num: 0x2e48, .Name: "COMPUTE_USER_DATA_8" }, |
539 | {.Num: 0x2e49, .Name: "COMPUTE_USER_DATA_9" }, |
540 | {.Num: 0x2e4a, .Name: "COMPUTE_USER_DATA_10" }, |
541 | {.Num: 0x2e4b, .Name: "COMPUTE_USER_DATA_11" }, |
542 | {.Num: 0x2e4c, .Name: "COMPUTE_USER_DATA_12" }, |
543 | {.Num: 0x2e4d, .Name: "COMPUTE_USER_DATA_13" }, |
544 | {.Num: 0x2e4e, .Name: "COMPUTE_USER_DATA_14" }, |
545 | {.Num: 0x2e4f, .Name: "COMPUTE_USER_DATA_15" }, |
546 | |
547 | {.Num: 0x2e07, .Name: "COMPUTE_NUM_THREAD_X" }, |
548 | {.Num: 0x2e08, .Name: "COMPUTE_NUM_THREAD_Y" }, |
549 | {.Num: 0x2e09, .Name: "COMPUTE_NUM_THREAD_Z" }, |
550 | {.Num: 0xa2db, .Name: "VGT_TF_PARAM" }, |
551 | {.Num: 0xa2d6, .Name: "VGT_LS_HS_CONFIG" }, |
552 | {.Num: 0xa287, .Name: "VGT_HOS_MIN_TESS_LEVEL" }, |
553 | {.Num: 0xa286, .Name: "VGT_HOS_MAX_TESS_LEVEL" }, |
554 | {.Num: 0xa2f8, .Name: "PA_SC_AA_CONFIG" }, |
555 | {.Num: 0xa310, .Name: "PA_SC_SHADER_CONTROL" }, |
556 | {.Num: 0xa313, .Name: "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL" }, |
557 | |
558 | {.Num: 0x2d0c, .Name: "SPI_SHADER_USER_DATA_HS_0" }, |
559 | {.Num: 0x2d0d, .Name: "SPI_SHADER_USER_DATA_HS_1" }, |
560 | {.Num: 0x2d0e, .Name: "SPI_SHADER_USER_DATA_HS_2" }, |
561 | {.Num: 0x2d0f, .Name: "SPI_SHADER_USER_DATA_HS_3" }, |
562 | {.Num: 0x2d10, .Name: "SPI_SHADER_USER_DATA_HS_4" }, |
563 | {.Num: 0x2d11, .Name: "SPI_SHADER_USER_DATA_HS_5" }, |
564 | {.Num: 0x2d12, .Name: "SPI_SHADER_USER_DATA_HS_6" }, |
565 | {.Num: 0x2d13, .Name: "SPI_SHADER_USER_DATA_HS_7" }, |
566 | {.Num: 0x2d14, .Name: "SPI_SHADER_USER_DATA_HS_8" }, |
567 | {.Num: 0x2d15, .Name: "SPI_SHADER_USER_DATA_HS_9" }, |
568 | {.Num: 0x2d16, .Name: "SPI_SHADER_USER_DATA_HS_10" }, |
569 | {.Num: 0x2d17, .Name: "SPI_SHADER_USER_DATA_HS_11" }, |
570 | {.Num: 0x2d18, .Name: "SPI_SHADER_USER_DATA_HS_12" }, |
571 | {.Num: 0x2d19, .Name: "SPI_SHADER_USER_DATA_HS_13" }, |
572 | {.Num: 0x2d1a, .Name: "SPI_SHADER_USER_DATA_HS_14" }, |
573 | {.Num: 0x2d1b, .Name: "SPI_SHADER_USER_DATA_HS_15" }, |
574 | {.Num: 0x2d1c, .Name: "SPI_SHADER_USER_DATA_HS_16" }, |
575 | {.Num: 0x2d1d, .Name: "SPI_SHADER_USER_DATA_HS_17" }, |
576 | {.Num: 0x2d1e, .Name: "SPI_SHADER_USER_DATA_HS_18" }, |
577 | {.Num: 0x2d1f, .Name: "SPI_SHADER_USER_DATA_HS_19" }, |
578 | {.Num: 0x2d20, .Name: "SPI_SHADER_USER_DATA_HS_20" }, |
579 | {.Num: 0x2d21, .Name: "SPI_SHADER_USER_DATA_HS_21" }, |
580 | {.Num: 0x2d22, .Name: "SPI_SHADER_USER_DATA_HS_22" }, |
581 | {.Num: 0x2d23, .Name: "SPI_SHADER_USER_DATA_HS_23" }, |
582 | {.Num: 0x2d24, .Name: "SPI_SHADER_USER_DATA_HS_24" }, |
583 | {.Num: 0x2d25, .Name: "SPI_SHADER_USER_DATA_HS_25" }, |
584 | {.Num: 0x2d26, .Name: "SPI_SHADER_USER_DATA_HS_26" }, |
585 | {.Num: 0x2d27, .Name: "SPI_SHADER_USER_DATA_HS_27" }, |
586 | {.Num: 0x2d28, .Name: "SPI_SHADER_USER_DATA_HS_28" }, |
587 | {.Num: 0x2d29, .Name: "SPI_SHADER_USER_DATA_HS_29" }, |
588 | {.Num: 0x2d2a, .Name: "SPI_SHADER_USER_DATA_HS_30" }, |
589 | {.Num: 0x2d2b, .Name: "SPI_SHADER_USER_DATA_HS_31" }, |
590 | |
591 | {.Num: 0x2d4c, .Name: "SPI_SHADER_USER_DATA_LS_0" }, |
592 | {.Num: 0x2d4d, .Name: "SPI_SHADER_USER_DATA_LS_1" }, |
593 | {.Num: 0x2d4e, .Name: "SPI_SHADER_USER_DATA_LS_2" }, |
594 | {.Num: 0x2d4f, .Name: "SPI_SHADER_USER_DATA_LS_3" }, |
595 | {.Num: 0x2d50, .Name: "SPI_SHADER_USER_DATA_LS_4" }, |
596 | {.Num: 0x2d51, .Name: "SPI_SHADER_USER_DATA_LS_5" }, |
597 | {.Num: 0x2d52, .Name: "SPI_SHADER_USER_DATA_LS_6" }, |
598 | {.Num: 0x2d53, .Name: "SPI_SHADER_USER_DATA_LS_7" }, |
599 | {.Num: 0x2d54, .Name: "SPI_SHADER_USER_DATA_LS_8" }, |
600 | {.Num: 0x2d55, .Name: "SPI_SHADER_USER_DATA_LS_9" }, |
601 | {.Num: 0x2d56, .Name: "SPI_SHADER_USER_DATA_LS_10" }, |
602 | {.Num: 0x2d57, .Name: "SPI_SHADER_USER_DATA_LS_11" }, |
603 | {.Num: 0x2d58, .Name: "SPI_SHADER_USER_DATA_LS_12" }, |
604 | {.Num: 0x2d59, .Name: "SPI_SHADER_USER_DATA_LS_13" }, |
605 | {.Num: 0x2d5a, .Name: "SPI_SHADER_USER_DATA_LS_14" }, |
606 | {.Num: 0x2d5b, .Name: "SPI_SHADER_USER_DATA_LS_15" }, |
607 | |
608 | {.Num: 0xa2aa, .Name: "IA_MULTI_VGT_PARAM" }, |
609 | {.Num: 0xa2a5, .Name: "VGT_GS_MAX_PRIMS_PER_SUBGROUP" }, |
610 | {.Num: 0xa2e6, .Name: "VGT_STRMOUT_BUFFER_CONFIG" }, |
611 | {.Num: 0xa2e5, .Name: "VGT_STRMOUT_CONFIG" }, |
612 | {.Num: 0xa2b5, .Name: "VGT_STRMOUT_VTX_STRIDE_0" }, |
613 | {.Num: 0xa2b9, .Name: "VGT_STRMOUT_VTX_STRIDE_1" }, |
614 | {.Num: 0xa2bd, .Name: "VGT_STRMOUT_VTX_STRIDE_2" }, |
615 | {.Num: 0xa2c1, .Name: "VGT_STRMOUT_VTX_STRIDE_3" }, |
616 | {.Num: 0xa316, .Name: "VGT_VERTEX_REUSE_BLOCK_CNTL" }, |
617 | |
618 | {.Num: 0x2e28, .Name: "COMPUTE_PGM_RSRC3" }, |
619 | {.Num: 0x2e2a, .Name: "COMPUTE_SHADER_CHKSUM" }, |
620 | {.Num: 0x2e24, .Name: "COMPUTE_USER_ACCUM_0" }, |
621 | {.Num: 0x2e25, .Name: "COMPUTE_USER_ACCUM_1" }, |
622 | {.Num: 0x2e26, .Name: "COMPUTE_USER_ACCUM_2" }, |
623 | {.Num: 0x2e27, .Name: "COMPUTE_USER_ACCUM_3" }, |
624 | {.Num: 0xa1ff, .Name: "GE_MAX_OUTPUT_PER_SUBGROUP" }, |
625 | {.Num: 0xa2d3, .Name: "GE_NGG_SUBGRP_CNTL" }, |
626 | {.Num: 0xc25f, .Name: "GE_STEREO_CNTL" }, |
627 | {.Num: 0xc262, .Name: "GE_USER_VGPR_EN" }, |
628 | {.Num: 0xc258, .Name: "IA_MULTI_VGT_PARAM_PIPED" }, |
629 | {.Num: 0xa210, .Name: "PA_STEREO_CNTL" }, |
630 | {.Num: 0xa1c2, .Name: "SPI_SHADER_IDX_FORMAT" }, |
631 | {.Num: 0x2c80, .Name: "SPI_SHADER_PGM_CHKSUM_GS" }, |
632 | {.Num: 0x2d00, .Name: "SPI_SHADER_PGM_CHKSUM_HS" }, |
633 | {.Num: 0x2c06, .Name: "SPI_SHADER_PGM_CHKSUM_PS" }, |
634 | {.Num: 0x2c45, .Name: "SPI_SHADER_PGM_CHKSUM_VS" }, |
635 | {.Num: 0x2c88, .Name: "SPI_SHADER_PGM_LO_GS" }, |
636 | {.Num: 0x2cb2, .Name: "SPI_SHADER_USER_ACCUM_ESGS_0" }, |
637 | {.Num: 0x2cb3, .Name: "SPI_SHADER_USER_ACCUM_ESGS_1" }, |
638 | {.Num: 0x2cb4, .Name: "SPI_SHADER_USER_ACCUM_ESGS_2" }, |
639 | {.Num: 0x2cb5, .Name: "SPI_SHADER_USER_ACCUM_ESGS_3" }, |
640 | {.Num: 0x2d32, .Name: "SPI_SHADER_USER_ACCUM_LSHS_0" }, |
641 | {.Num: 0x2d33, .Name: "SPI_SHADER_USER_ACCUM_LSHS_1" }, |
642 | {.Num: 0x2d34, .Name: "SPI_SHADER_USER_ACCUM_LSHS_2" }, |
643 | {.Num: 0x2d35, .Name: "SPI_SHADER_USER_ACCUM_LSHS_3" }, |
644 | {.Num: 0x2c32, .Name: "SPI_SHADER_USER_ACCUM_PS_0" }, |
645 | {.Num: 0x2c33, .Name: "SPI_SHADER_USER_ACCUM_PS_1" }, |
646 | {.Num: 0x2c34, .Name: "SPI_SHADER_USER_ACCUM_PS_2" }, |
647 | {.Num: 0x2c35, .Name: "SPI_SHADER_USER_ACCUM_PS_3" }, |
648 | {.Num: 0x2c72, .Name: "SPI_SHADER_USER_ACCUM_VS_0" }, |
649 | {.Num: 0x2c73, .Name: "SPI_SHADER_USER_ACCUM_VS_1" }, |
650 | {.Num: 0x2c74, .Name: "SPI_SHADER_USER_ACCUM_VS_2" }, |
651 | {.Num: 0x2c75, .Name: "SPI_SHADER_USER_ACCUM_VS_3" }, |
652 | |
653 | {.Num: 0, .Name: nullptr}}; |
654 | auto Entry = RegInfoTable; |
655 | for (; Entry->Num && Entry->Num != RegNum; ++Entry) |
656 | ; |
657 | return Entry->Name; |
658 | } |
659 | |
660 | // Convert the accumulated PAL metadata into an asm directive. |
661 | void AMDGPUPALMetadata::toString(std::string &String) { |
662 | String.clear(); |
663 | if (!BlobType) |
664 | return; |
665 | raw_string_ostream Stream(String); |
666 | if (isLegacy()) { |
667 | if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil) |
668 | return; |
669 | // Old linear reg=val format. |
670 | Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' '; |
671 | auto Regs = getRegisters(); |
672 | for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { |
673 | if (I != Regs.begin()) |
674 | Stream << ','; |
675 | unsigned Reg = I->first.getUInt(); |
676 | unsigned Val = I->second.getUInt(); |
677 | Stream << "0x" << Twine::utohexstr(Val: Reg) << ",0x" << Twine::utohexstr(Val); |
678 | } |
679 | Stream << '\n'; |
680 | return; |
681 | } |
682 | |
683 | // New msgpack-based format -- output as YAML (with unsigned numbers in hex), |
684 | // but first change the registers map to use names. |
685 | MsgPackDoc.setHexMode(); |
686 | auto &RegsObj = refRegisters(); |
687 | auto OrigRegs = RegsObj.getMap(); |
688 | RegsObj = MsgPackDoc.getMapNode(); |
689 | for (auto I : OrigRegs) { |
690 | auto Key = I.first; |
691 | if (const char *RegName = getRegisterName(RegNum: Key.getUInt())) { |
692 | std::string KeyName = Key.toString(); |
693 | KeyName += " (" ; |
694 | KeyName += RegName; |
695 | KeyName += ')'; |
696 | Key = MsgPackDoc.getNode(V: KeyName, /*Copy=*/true); |
697 | } |
698 | RegsObj.getMap()[Key] = I.second; |
699 | } |
700 | |
701 | // Output as YAML. |
702 | Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n'; |
703 | MsgPackDoc.toYAML(OS&: Stream); |
704 | Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n'; |
705 | |
706 | // Restore original registers map. |
707 | RegsObj = OrigRegs; |
708 | } |
709 | |
710 | // Convert the accumulated PAL metadata into a binary blob for writing as |
711 | // a .note record of the specified AMD type. Returns an empty blob if |
712 | // there is no PAL metadata, |
713 | void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) { |
714 | if (Type == ELF::NT_AMD_PAL_METADATA) |
715 | toLegacyBlob(Blob); |
716 | else if (Type) |
717 | toMsgPackBlob(Blob); |
718 | } |
719 | |
720 | void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) { |
721 | Blob.clear(); |
722 | auto Registers = getRegisters(); |
723 | if (Registers.getMap().empty()) |
724 | return; |
725 | raw_string_ostream OS(Blob); |
726 | support::endian::Writer EW(OS, llvm::endianness::little); |
727 | for (auto I : Registers.getMap()) { |
728 | EW.write(Val: uint32_t(I.first.getUInt())); |
729 | EW.write(Val: uint32_t(I.second.getUInt())); |
730 | } |
731 | } |
732 | |
733 | void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) { |
734 | Blob.clear(); |
735 | MsgPackDoc.writeToBlob(Blob); |
736 | } |
737 | |
738 | // Set PAL metadata from YAML text. Returns false if failed. |
739 | bool AMDGPUPALMetadata::setFromString(StringRef S) { |
740 | BlobType = ELF::NT_AMDGPU_METADATA; |
741 | if (!MsgPackDoc.fromYAML(S)) |
742 | return false; |
743 | |
744 | // In the registers map, some keys may be of the form "0xa191 |
745 | // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a |
746 | // string. We need to turn it into a number. |
747 | auto &RegsObj = refRegisters(); |
748 | auto OrigRegs = RegsObj; |
749 | RegsObj = MsgPackDoc.getMapNode(); |
750 | Registers = RegsObj.getMap(); |
751 | bool Ok = true; |
752 | for (auto I : OrigRegs.getMap()) { |
753 | auto Key = I.first; |
754 | if (Key.getKind() == msgpack::Type::String) { |
755 | StringRef S = Key.getString(); |
756 | uint64_t Val; |
757 | if (S.consumeInteger(Radix: 0, Result&: Val)) { |
758 | Ok = false; |
759 | errs() << "Unrecognized PAL metadata register key '" << S << "'\n" ; |
760 | continue; |
761 | } |
762 | Key = MsgPackDoc.getNode(V: uint64_t(Val)); |
763 | } |
764 | Registers.getMap()[Key] = I.second; |
765 | } |
766 | return Ok; |
767 | } |
768 | |
769 | // Reference (create if necessary) the node for the registers map. |
770 | msgpack::DocNode &AMDGPUPALMetadata::refRegisters() { |
771 | auto &N = |
772 | MsgPackDoc.getRoot() |
773 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines" )] |
774 | .getArray(/*Convert=*/true)[0] |
775 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".registers" )]; |
776 | N.getMap(/*Convert=*/true); |
777 | return N; |
778 | } |
779 | |
780 | // Get (create if necessary) the registers map. |
781 | msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { |
782 | if (Registers.isEmpty()) |
783 | Registers = refRegisters(); |
784 | return Registers.getMap(); |
785 | } |
786 | |
787 | // Reference (create if necessary) the node for the shader functions map. |
788 | msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() { |
789 | auto &N = |
790 | MsgPackDoc.getRoot() |
791 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines" )] |
792 | .getArray(/*Convert=*/true)[0] |
793 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".shader_functions" )]; |
794 | N.getMap(/*Convert=*/true); |
795 | return N; |
796 | } |
797 | |
798 | // Get (create if necessary) the shader functions map. |
799 | msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() { |
800 | if (ShaderFunctions.isEmpty()) |
801 | ShaderFunctions = refShaderFunctions(); |
802 | return ShaderFunctions.getMap(); |
803 | } |
804 | |
805 | // Get (create if necessary) a function in the shader functions map. |
806 | msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) { |
807 | auto Functions = getShaderFunctions(); |
808 | return Functions[Name].getMap(/*Convert=*/true); |
809 | } |
810 | |
811 | msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() { |
812 | auto &N = |
813 | MsgPackDoc.getRoot() |
814 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines" )] |
815 | .getArray(/*Convert=*/true)[0] |
816 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".compute_registers" )]; |
817 | N.getMap(/*Convert=*/true); |
818 | return N; |
819 | } |
820 | |
821 | msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() { |
822 | if (ComputeRegisters.isEmpty()) |
823 | ComputeRegisters = refComputeRegisters(); |
824 | return ComputeRegisters.getMap(); |
825 | } |
826 | |
827 | msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() { |
828 | auto &N = |
829 | MsgPackDoc.getRoot() |
830 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines" )] |
831 | .getArray(/*Convert=*/true)[0] |
832 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".graphics_registers" )]; |
833 | N.getMap(/*Convert=*/true); |
834 | return N; |
835 | } |
836 | |
837 | msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() { |
838 | if (GraphicsRegisters.isEmpty()) |
839 | GraphicsRegisters = refGraphicsRegisters(); |
840 | return GraphicsRegisters.getMap(); |
841 | } |
842 | |
843 | // Return the PAL metadata hardware shader stage name. |
844 | static const char *getStageName(CallingConv::ID CC) { |
845 | switch (CC) { |
846 | case CallingConv::AMDGPU_PS: |
847 | return ".ps" ; |
848 | case CallingConv::AMDGPU_VS: |
849 | return ".vs" ; |
850 | case CallingConv::AMDGPU_GS: |
851 | return ".gs" ; |
852 | case CallingConv::AMDGPU_ES: |
853 | return ".es" ; |
854 | case CallingConv::AMDGPU_HS: |
855 | return ".hs" ; |
856 | case CallingConv::AMDGPU_LS: |
857 | return ".ls" ; |
858 | case CallingConv::AMDGPU_Gfx: |
859 | llvm_unreachable("Callable shader has no hardware stage" ); |
860 | default: |
861 | return ".cs" ; |
862 | } |
863 | } |
864 | |
865 | msgpack::DocNode &AMDGPUPALMetadata::refHwStage() { |
866 | auto &N = |
867 | MsgPackDoc.getRoot() |
868 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines" )] |
869 | .getArray(/*Convert=*/true)[0] |
870 | .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".hardware_stages" )]; |
871 | N.getMap(/*Convert=*/true); |
872 | return N; |
873 | } |
874 | |
875 | // Get (create if necessary) the .hardware_stages entry for the given calling |
876 | // convention. |
877 | msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) { |
878 | if (HwStages.isEmpty()) |
879 | HwStages = refHwStage(); |
880 | return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true); |
881 | } |
882 | |
883 | // Get .note record vendor name of metadata blob to be emitted. |
884 | const char *AMDGPUPALMetadata::getVendor() const { |
885 | return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3; |
886 | } |
887 | |
888 | // Get .note record type of metadata blob to be emitted: |
889 | // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or |
890 | // ELF::NT_AMDGPU_METADATA (MsgPack format), or |
891 | // 0 (no PAL metadata). |
892 | unsigned AMDGPUPALMetadata::getType() const { |
893 | return BlobType; |
894 | } |
895 | |
896 | // Return whether the blob type is legacy PAL metadata. |
897 | bool AMDGPUPALMetadata::isLegacy() const { |
898 | return BlobType == ELF::NT_AMD_PAL_METADATA; |
899 | } |
900 | |
901 | // Set legacy PAL metadata format. |
902 | void AMDGPUPALMetadata::setLegacy() { |
903 | BlobType = ELF::NT_AMD_PAL_METADATA; |
904 | } |
905 | |
906 | // Erase all PAL metadata. |
907 | void AMDGPUPALMetadata::reset() { |
908 | MsgPackDoc.clear(); |
909 | Registers = MsgPackDoc.getEmptyNode(); |
910 | HwStages = MsgPackDoc.getEmptyNode(); |
911 | ShaderFunctions = MsgPackDoc.getEmptyNode(); |
912 | } |
913 | |
914 | unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) { |
915 | assert(idx < 2 && |
916 | "illegal index to PAL version - should be 0 (major) or 1 (minor)" ); |
917 | if (!VersionChecked) { |
918 | if (Version.isEmpty()) { |
919 | auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true); |
920 | auto I = M.find(Key: MsgPackDoc.getNode(V: "amdpal.version" )); |
921 | if (I != M.end()) |
922 | Version = I->second; |
923 | } |
924 | VersionChecked = true; |
925 | } |
926 | if (Version.isEmpty()) |
927 | // Default to 2.6 if there's no version info |
928 | return idx ? 6 : 2; |
929 | return Version.getArray()[idx].getUInt(); |
930 | } |
931 | |
932 | unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(idx: 0); } |
933 | |
934 | unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(idx: 1); } |
935 | |
936 | // Set the field in a given .hardware_stages entry |
937 | void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) { |
938 | getHwStage(CC)[field] = Val; |
939 | } |
940 | |
941 | void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) { |
942 | getHwStage(CC)[field] = Val; |
943 | } |
944 | |
945 | void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) { |
946 | getComputeRegisters()[field] = Val; |
947 | } |
948 | |
949 | void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) { |
950 | getComputeRegisters()[field] = Val; |
951 | } |
952 | |
953 | msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) { |
954 | auto M = getComputeRegisters(); |
955 | auto I = M.find(Key: field); |
956 | return I == M.end() ? nullptr : &I->second; |
957 | } |
958 | |
959 | bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) { |
960 | if (auto N = refComputeRegister(field)) |
961 | return N->getUInt() == Val; |
962 | return false; |
963 | } |
964 | |
965 | bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) { |
966 | if (auto N = refComputeRegister(field)) |
967 | return N->getBool() == Val; |
968 | return false; |
969 | } |
970 | |
971 | void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) { |
972 | getGraphicsRegisters()[field] = Val; |
973 | } |
974 | |
975 | void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) { |
976 | getGraphicsRegisters()[field] = Val; |
977 | } |
978 | |
979 | void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2, |
980 | unsigned Val) { |
981 | getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val; |
982 | } |
983 | |
984 | void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2, |
985 | bool Val) { |
986 | getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val; |
987 | } |
988 | |