1//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMInstrInfo.h"
14#include "ARM.h"
15#include "ARMConstantPoolValue.h"
16#include "ARMMachineFunctionInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/LiveVariables.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/GlobalVariable.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCInst.h"
29using namespace llvm;
30
31ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
32
33/// Return the noop instruction to use for a noop.
34MCInst ARMInstrInfo::getNop() const {
35 MCInst NopInst;
36 if (hasNOP()) {
37 NopInst.setOpcode(ARM::HINT);
38 NopInst.addOperand(Op: MCOperand::createImm(Val: 0));
39 NopInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
40 NopInst.addOperand(Op: MCOperand::createReg(Reg: 0));
41 } else {
42 NopInst.setOpcode(ARM::MOVr);
43 NopInst.addOperand(Op: MCOperand::createReg(ARM::Reg: R0));
44 NopInst.addOperand(Op: MCOperand::createReg(ARM::Reg: R0));
45 NopInst.addOperand(Op: MCOperand::createImm(Val: ARMCC::AL));
46 NopInst.addOperand(Op: MCOperand::createReg(Reg: 0));
47 NopInst.addOperand(Op: MCOperand::createReg(Reg: 0));
48 }
49 return NopInst;
50}
51
52unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
53 switch (Opc) {
54 default:
55 break;
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM:
59 case ARM::LDR_POST_REG:
60 return ARM::LDRi12;
61 case ARM::LDRH_PRE:
62 case ARM::LDRH_POST:
63 return ARM::LDRH;
64 case ARM::LDRB_PRE_IMM:
65 case ARM::LDRB_PRE_REG:
66 case ARM::LDRB_POST_IMM:
67 case ARM::LDRB_POST_REG:
68 return ARM::LDRBi12;
69 case ARM::LDRSH_PRE:
70 case ARM::LDRSH_POST:
71 return ARM::LDRSH;
72 case ARM::LDRSB_PRE:
73 case ARM::LDRSB_POST:
74 return ARM::LDRSB;
75 case ARM::STR_PRE_IMM:
76 case ARM::STR_PRE_REG:
77 case ARM::STR_POST_IMM:
78 case ARM::STR_POST_REG:
79 return ARM::STRi12;
80 case ARM::STRH_PRE:
81 case ARM::STRH_POST:
82 return ARM::STRH;
83 case ARM::STRB_PRE_IMM:
84 case ARM::STRB_PRE_REG:
85 case ARM::STRB_POST_IMM:
86 case ARM::STRB_POST_REG:
87 return ARM::STRBi12;
88 }
89
90 return 0;
91}
92
93void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI) const {
94 MachineFunction &MF = *MI->getParent()->getParent();
95 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
96 const TargetMachine &TM = MF.getTarget();
97 Module &M = *MF.getFunction().getParent();
98
99 if (M.getStackProtectorGuard() == "tls") {
100 expandLoadStackGuardBase(MI, ARM::LoadImmOpc: MRC, ARM::LoadOpc: LDRi12);
101 return;
102 }
103
104 const GlobalValue *GV =
105 cast<GlobalValue>(Val: (*MI->memoperands_begin())->getValue());
106
107 bool ForceELFGOTPIC = Subtarget.isTargetELF() && !GV->isDSOLocal();
108 if (!Subtarget.useMovt() || ForceELFGOTPIC) {
109 // For ELF non-PIC, use GOT PIC code sequence as well because R_ARM_GOT_ABS
110 // does not have assembler support.
111 if (TM.isPositionIndependent() || ForceELFGOTPIC)
112 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
113 else
114 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
115 return;
116 }
117
118 if (!TM.isPositionIndependent()) {
119 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
120 return;
121 }
122
123 if (!Subtarget.isGVIndirectSymbol(GV)) {
124 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
125 return;
126 }
127
128 MachineBasicBlock &MBB = *MI->getParent();
129 DebugLoc DL = MI->getDebugLoc();
130 Register Reg = MI->getOperand(i: 0).getReg();
131 MachineInstrBuilder MIB;
132
133 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
134 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
135 auto Flags = MachineMemOperand::MOLoad |
136 MachineMemOperand::MODereferenceable |
137 MachineMemOperand::MOInvariant;
138 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
139 PtrInfo: MachinePointerInfo::getGOT(MF&: *MBB.getParent()), F: Flags, Size: 4, BaseAlignment: Align(4));
140 MIB.addMemOperand(MMO);
141 BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
142 .addReg(Reg, RegState::Kill)
143 .addImm(0)
144 .cloneMemRefs(*MI)
145 .add(predOps(ARMCC::AL));
146}
147

source code of llvm/lib/Target/ARM/ARMInstrInfo.cpp