1//=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the NVPTX implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXFrameLowering.h"
14#include "NVPTX.h"
15#include "NVPTXRegisterInfo.h"
16#include "NVPTXSubtarget.h"
17#include "NVPTXTargetMachine.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetInstrInfo.h"
23#include "llvm/MC/MachineLocation.h"
24
25using namespace llvm;
26
27NVPTXFrameLowering::NVPTXFrameLowering()
28 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, Align(8), 0) {}
29
30bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
31
32void NVPTXFrameLowering::emitPrologue(MachineFunction &MF,
33 MachineBasicBlock &MBB) const {
34 if (MF.getFrameInfo().hasStackObjects()) {
35 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
36 MachineBasicBlock::iterator MBBI = MBB.begin();
37 MachineRegisterInfo &MR = MF.getRegInfo();
38
39 const NVPTXRegisterInfo *NRI =
40 MF.getSubtarget<NVPTXSubtarget>().getRegisterInfo();
41
42 // This instruction really occurs before first instruction
43 // in the BB, so giving it no debug location.
44 DebugLoc dl = DebugLoc();
45
46 // Emits
47 // mov %SPL, %depot;
48 // cvta.local %SP, %SPL;
49 // for local address accesses in MF.
50 bool Is64Bit =
51 static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit();
52 unsigned CvtaLocalOpcode =
53 (Is64Bit ? NVPTX::cvta_local_64 : NVPTX::cvta_local);
54 unsigned MovDepotOpcode =
55 (Is64Bit ? NVPTX::MOV_DEPOT_ADDR_64 : NVPTX::MOV_DEPOT_ADDR);
56 if (!MR.use_empty(RegNo: NRI->getFrameRegister(MF))) {
57 // If %SP is not used, do not bother emitting "cvta.local %SP, %SPL".
58 MBBI = BuildMI(BB&: MBB, I: MBBI, MIMD: dl,
59 MCID: MF.getSubtarget().getInstrInfo()->get(Opcode: CvtaLocalOpcode),
60 DestReg: NRI->getFrameRegister(MF))
61 .addReg(RegNo: NRI->getFrameLocalRegister(MF));
62 }
63 if (!MR.use_empty(RegNo: NRI->getFrameLocalRegister(MF))) {
64 BuildMI(BB&: MBB, I: MBBI, MIMD: dl,
65 MCID: MF.getSubtarget().getInstrInfo()->get(Opcode: MovDepotOpcode),
66 DestReg: NRI->getFrameLocalRegister(MF))
67 .addImm(Val: MF.getFunctionNumber());
68 }
69 }
70}
71
72StackOffset
73NVPTXFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
74 Register &FrameReg) const {
75 const MachineFrameInfo &MFI = MF.getFrameInfo();
76 FrameReg = NVPTX::VRDepot;
77 return StackOffset::getFixed(Fixed: MFI.getObjectOffset(ObjectIdx: FI) -
78 getOffsetOfLocalArea());
79}
80
81void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
82 MachineBasicBlock &MBB) const {}
83
84// This function eliminates ADJCALLSTACKDOWN,
85// ADJCALLSTACKUP pseudo instructions
86MachineBasicBlock::iterator NVPTXFrameLowering::eliminateCallFramePseudoInstr(
87 MachineFunction &MF, MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I) const {
89 // Simply discard ADJCALLSTACKDOWN,
90 // ADJCALLSTACKUP instructions.
91 return MBB.erase(I);
92}
93
94TargetFrameLowering::DwarfFrameBase
95NVPTXFrameLowering::getDwarfFrameBase(const MachineFunction &MF) const {
96 return {.Kind: DwarfFrameBase::CFA, .Location: {.Reg: 0}};
97}
98

source code of llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp