1use crate::{
2 core_arch::{simd::*, x86::*, x86_64::*},
3 intrinsics::simd::*,
4 mem::transmute,
5};
6
7#[cfg(test)]
8use stdarch_test::assert_instr;
9
10/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
11///
12/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
13#[inline]
14#[target_feature(enable = "avx512f")]
15#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
16#[cfg_attr(test, assert_instr(vcvtsd2si))]
17pub unsafe fn _mm_cvtsd_i64(a: __m128d) -> i64 {
18 _mm_cvtsd_si64(a)
19}
20
21/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
22///
23/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
24#[inline]
25#[target_feature(enable = "avx512f")]
26#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
27#[cfg_attr(test, assert_instr(vcvtss2si))]
28pub unsafe fn _mm_cvtss_i64(a: __m128) -> i64 {
29 _mm_cvtss_si64(a)
30}
31
32/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
33///
34/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
35#[inline]
36#[target_feature(enable = "avx512f")]
37#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
38#[cfg_attr(test, assert_instr(vcvtss2usi))]
39pub unsafe fn _mm_cvtss_u64(a: __m128) -> u64 {
40 vcvtss2usi64(a:a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
41}
42
43/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
44///
45/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
46#[inline]
47#[target_feature(enable = "avx512f")]
48#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
49#[cfg_attr(test, assert_instr(vcvtsd2usi))]
50pub unsafe fn _mm_cvtsd_u64(a: __m128d) -> u64 {
51 vcvtsd2usi64(a:a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
52}
53
54/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
55///
56/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti32_ss&expand=1643)
57#[inline]
58#[target_feature(enable = "avx512f")]
59#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
60#[cfg_attr(test, assert_instr(vcvtsi2ss))]
61pub unsafe fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
62 let b: f32 = b as f32;
63 simd_insert!(a, 0, b)
64}
65
66/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
67///
68/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
69#[inline]
70#[target_feature(enable = "avx512f")]
71#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
72#[cfg_attr(test, assert_instr(vcvtsi2sd))]
73pub unsafe fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
74 let b: f64 = b as f64;
75 simd_insert!(a, 0, b)
76}
77
78/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
79///
80/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
81#[inline]
82#[target_feature(enable = "avx512f")]
83#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
84#[cfg_attr(test, assert_instr(vcvtusi2ss))]
85pub unsafe fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
86 let b: f32 = b as f32;
87 simd_insert!(a, 0, b)
88}
89
90/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
91///
92/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
93#[inline]
94#[target_feature(enable = "avx512f")]
95#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
96#[cfg_attr(test, assert_instr(vcvtusi2sd))]
97pub unsafe fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
98 let b: f64 = b as f64;
99 simd_insert!(a, 0, b)
100}
101
102/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
103///
104/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
105#[inline]
106#[target_feature(enable = "avx512f")]
107#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
108#[cfg_attr(test, assert_instr(vcvtsd2si))]
109pub unsafe fn _mm_cvttsd_i64(a: __m128d) -> i64 {
110 vcvtsd2si64(a:a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
111}
112
113/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
114///
115/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
116#[inline]
117#[target_feature(enable = "avx512f")]
118#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
119#[cfg_attr(test, assert_instr(vcvtsd2usi))]
120pub unsafe fn _mm_cvttsd_u64(a: __m128d) -> u64 {
121 vcvtsd2usi64(a:a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
122}
123
124/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
125///
126/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
127#[inline]
128#[target_feature(enable = "avx512f")]
129#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
130#[cfg_attr(test, assert_instr(vcvtss2si))]
131pub unsafe fn _mm_cvttss_i64(a: __m128) -> i64 {
132 vcvtss2si64(a:a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
133}
134
135/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
136///
137/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
138#[inline]
139#[target_feature(enable = "avx512f")]
140#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
141#[cfg_attr(test, assert_instr(vcvtss2usi))]
142pub unsafe fn _mm_cvttss_u64(a: __m128) -> u64 {
143 vcvtss2usi64(a:a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
144}
145
146/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
147/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
148/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
149/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
150/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
151/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
152/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
153///
154/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
155#[inline]
156#[target_feature(enable = "avx512f")]
157#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
158#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
159#[rustc_legacy_const_generics(2)]
160pub unsafe fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
161 static_assert_rounding!(ROUNDING);
162 let a: f64x2 = a.as_f64x2();
163 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
164 transmute(src:r)
165}
166
167/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
168/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
169/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
170/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
171/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
172/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
173/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
174///
175/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
176#[inline]
177#[target_feature(enable = "avx512f")]
178#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
179#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
180#[rustc_legacy_const_generics(2)]
181pub unsafe fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
182 static_assert_rounding!(ROUNDING);
183 let a: f64x2 = a.as_f64x2();
184 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
185 transmute(src:r)
186}
187
188/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
189/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
190/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
191/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
192/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
193/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
194/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
195///
196/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
197#[inline]
198#[target_feature(enable = "avx512f")]
199#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
200#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
201#[rustc_legacy_const_generics(2)]
202pub unsafe fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
203 static_assert_rounding!(ROUNDING);
204 let a: f32x4 = a.as_f32x4();
205 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
206 transmute(src:r)
207}
208
209/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
210/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
211/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
212/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
213/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
214/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
215/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
216///
217/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
218#[inline]
219#[target_feature(enable = "avx512f")]
220#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
221#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
222#[rustc_legacy_const_generics(2)]
223pub unsafe fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
224 static_assert_rounding!(ROUNDING);
225 let a: f64x2 = a.as_f64x2();
226 let r: f64x2 = vcvtusi2sd64(a, b, ROUNDING);
227 transmute(src:r)
228}
229
230/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
231/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
232/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
233/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
234/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
235/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
236/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
237///
238/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
239#[inline]
240#[target_feature(enable = "avx512f")]
241#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
242#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
243#[rustc_legacy_const_generics(2)]
244pub unsafe fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
245 static_assert_rounding!(ROUNDING);
246 let a: f32x4 = a.as_f32x4();
247 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
248 transmute(src:r)
249}
250
251/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
252/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
253/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
254/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
255/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
256/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
257/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
258///
259/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
260#[inline]
261#[target_feature(enable = "avx512f")]
262#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
263#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
264#[rustc_legacy_const_generics(2)]
265pub unsafe fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
266 static_assert_rounding!(ROUNDING);
267 let a: f32x4 = a.as_f32x4();
268 let r: f32x4 = vcvtusi2ss64(a, b, ROUNDING);
269 transmute(src:r)
270}
271
272/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
273/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
274/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
275/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
276/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
277/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
278/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
279///
280/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
281#[inline]
282#[target_feature(enable = "avx512f")]
283#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
284#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
285#[rustc_legacy_const_generics(1)]
286pub unsafe fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
287 static_assert_rounding!(ROUNDING);
288 let a: f64x2 = a.as_f64x2();
289 vcvtsd2si64(a, ROUNDING)
290}
291
292/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
293/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
294/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
295/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
296/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
297/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
298/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
299///
300/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
301#[inline]
302#[target_feature(enable = "avx512f")]
303#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
304#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
305#[rustc_legacy_const_generics(1)]
306pub unsafe fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
307 static_assert_rounding!(ROUNDING);
308 let a: f64x2 = a.as_f64x2();
309 vcvtsd2si64(a, ROUNDING)
310}
311
312/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
313/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
314/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
315/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
316/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
317/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
318/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
319///
320/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
321#[inline]
322#[target_feature(enable = "avx512f")]
323#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
324#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
325#[rustc_legacy_const_generics(1)]
326pub unsafe fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
327 static_assert_rounding!(ROUNDING);
328 let a: f64x2 = a.as_f64x2();
329 vcvtsd2usi64(a, ROUNDING)
330}
331
332/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
333/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
334/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
335/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
336/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
337/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
338/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
339///
340/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
341#[inline]
342#[target_feature(enable = "avx512f")]
343#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
344#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
345#[rustc_legacy_const_generics(1)]
346pub unsafe fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
347 static_assert_rounding!(ROUNDING);
348 let a: f32x4 = a.as_f32x4();
349 vcvtss2si64(a, ROUNDING)
350}
351
352/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
353/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
354/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
355/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
356/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
357/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
358/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
359///
360/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
361#[inline]
362#[target_feature(enable = "avx512f")]
363#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
364#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
365#[rustc_legacy_const_generics(1)]
366pub unsafe fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
367 static_assert_rounding!(ROUNDING);
368 let a: f32x4 = a.as_f32x4();
369 vcvtss2si64(a, ROUNDING)
370}
371
372/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
373/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
374/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
375/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
376/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
377/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
378/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
379///
380/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
381#[inline]
382#[target_feature(enable = "avx512f")]
383#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
384#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
385#[rustc_legacy_const_generics(1)]
386pub unsafe fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
387 static_assert_rounding!(ROUNDING);
388 let a: f32x4 = a.as_f32x4();
389 vcvtss2usi64(a, ROUNDING)
390}
391
392/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
393/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
394///
395/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
396#[inline]
397#[target_feature(enable = "avx512f")]
398#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
399#[cfg_attr(test, assert_instr(vcvtsd2si, SAE = 8))]
400#[rustc_legacy_const_generics(1)]
401pub unsafe fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
402 static_assert_sae!(SAE);
403 let a: f64x2 = a.as_f64x2();
404 vcvtsd2si64(a, SAE)
405}
406
407/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
408/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
409///
410/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
411#[inline]
412#[target_feature(enable = "avx512f")]
413#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
414#[cfg_attr(test, assert_instr(vcvtsd2si, SAE = 8))]
415#[rustc_legacy_const_generics(1)]
416pub unsafe fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
417 static_assert_sae!(SAE);
418 let a: f64x2 = a.as_f64x2();
419 vcvtsd2si64(a, SAE)
420}
421
422/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
423/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
424///
425/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
426#[inline]
427#[target_feature(enable = "avx512f")]
428#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
429#[cfg_attr(test, assert_instr(vcvtsd2usi, SAE = 8))]
430#[rustc_legacy_const_generics(1)]
431pub unsafe fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
432 static_assert_sae!(SAE);
433 let a: f64x2 = a.as_f64x2();
434 vcvtsd2usi64(a, SAE)
435}
436
437/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
438/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
439///
440/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
441#[inline]
442#[target_feature(enable = "avx512f")]
443#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
444#[cfg_attr(test, assert_instr(vcvtss2si, SAE = 8))]
445#[rustc_legacy_const_generics(1)]
446pub unsafe fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
447 static_assert_sae!(SAE);
448 let a: f32x4 = a.as_f32x4();
449 vcvtss2si64(a, SAE)
450}
451
452/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
453/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
454///
455/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
456#[inline]
457#[target_feature(enable = "avx512f")]
458#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
459#[cfg_attr(test, assert_instr(vcvtss2si, SAE = 8))]
460#[rustc_legacy_const_generics(1)]
461pub unsafe fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
462 static_assert_sae!(SAE);
463 let a: f32x4 = a.as_f32x4();
464 vcvtss2si64(a, SAE)
465}
466
467/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
468/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
469///
470/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
471#[inline]
472#[target_feature(enable = "avx512f")]
473#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
474#[cfg_attr(test, assert_instr(vcvtss2usi, SAE = 8))]
475#[rustc_legacy_const_generics(1)]
476pub unsafe fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
477 static_assert_sae!(SAE);
478 let a: f32x4 = a.as_f32x4();
479 vcvtss2usi64(a, SAE)
480}
481
482#[allow(improper_ctypes)]
483extern "C" {
484 #[link_name = "llvm.x86.avx512.vcvtss2si64"]
485 fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
486 #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
487 fn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
488 #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
489 fn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
490 #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
491 fn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
492
493 #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
494 fn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
495 #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
496 fn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
497 #[link_name = "llvm.x86.avx512.cvtusi642ss"]
498 fn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
499 #[link_name = "llvm.x86.avx512.cvtusi642sd"]
500 fn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
501}
502
503#[cfg(test)]
504mod tests {
505
506 use stdarch_test::simd_test;
507
508 use crate::core_arch::x86::*;
509 use crate::core_arch::x86_64::*;
510 use crate::hint::black_box;
511
512 #[simd_test(enable = "avx512f")]
513 unsafe fn test_mm512_abs_epi64() {
514 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
515 let r = _mm512_abs_epi64(a);
516 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
517 assert_eq_m512i(r, e);
518 }
519
520 #[simd_test(enable = "avx512f")]
521 unsafe fn test_mm512_mask_abs_epi64() {
522 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
523 let r = _mm512_mask_abs_epi64(a, 0, a);
524 assert_eq_m512i(r, a);
525 let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
526 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
527 assert_eq_m512i(r, e);
528 }
529
530 #[simd_test(enable = "avx512f")]
531 unsafe fn test_mm512_maskz_abs_epi64() {
532 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
533 let r = _mm512_maskz_abs_epi64(0, a);
534 assert_eq_m512i(r, _mm512_setzero_si512());
535 let r = _mm512_maskz_abs_epi64(0b11111111, a);
536 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
537 assert_eq_m512i(r, e);
538 }
539
540 #[simd_test(enable = "avx512f,avx512vl")]
541 unsafe fn test_mm256_abs_epi64() {
542 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
543 let r = _mm256_abs_epi64(a);
544 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
545 assert_eq_m256i(r, e);
546 }
547
548 #[simd_test(enable = "avx512f,avx512vl")]
549 unsafe fn test_mm256_mask_abs_epi64() {
550 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
551 let r = _mm256_mask_abs_epi64(a, 0, a);
552 assert_eq_m256i(r, a);
553 let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
554 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
555 assert_eq_m256i(r, e);
556 }
557
558 #[simd_test(enable = "avx512f,avx512vl")]
559 unsafe fn test_mm256_maskz_abs_epi64() {
560 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
561 let r = _mm256_maskz_abs_epi64(0, a);
562 assert_eq_m256i(r, _mm256_setzero_si256());
563 let r = _mm256_maskz_abs_epi64(0b00001111, a);
564 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
565 assert_eq_m256i(r, e);
566 }
567
568 #[simd_test(enable = "avx512f")]
569 unsafe fn test_mm512_abs_pd() {
570 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
571 let r = _mm512_abs_pd(a);
572 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
573 assert_eq_m512d(r, e);
574 }
575
576 #[simd_test(enable = "avx512f")]
577 unsafe fn test_mm512_mask_abs_pd() {
578 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
579 let r = _mm512_mask_abs_pd(a, 0, a);
580 assert_eq_m512d(r, a);
581 let r = _mm512_mask_abs_pd(a, 0b00001111, a);
582 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
583 assert_eq_m512d(r, e);
584 }
585
586 #[simd_test(enable = "avx512f")]
587 unsafe fn test_mm512_mask_mov_epi64() {
588 let src = _mm512_set1_epi64(1);
589 let a = _mm512_set1_epi64(2);
590 let r = _mm512_mask_mov_epi64(src, 0, a);
591 assert_eq_m512i(r, src);
592 let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
593 assert_eq_m512i(r, a);
594 }
595
596 #[simd_test(enable = "avx512f")]
597 unsafe fn test_mm512_maskz_mov_epi64() {
598 let a = _mm512_set1_epi64(2);
599 let r = _mm512_maskz_mov_epi64(0, a);
600 assert_eq_m512i(r, _mm512_setzero_si512());
601 let r = _mm512_maskz_mov_epi64(0b11111111, a);
602 assert_eq_m512i(r, a);
603 }
604
605 #[simd_test(enable = "avx512f,avx512vl")]
606 unsafe fn test_mm256_mask_mov_epi64() {
607 let src = _mm256_set1_epi64x(1);
608 let a = _mm256_set1_epi64x(2);
609 let r = _mm256_mask_mov_epi64(src, 0, a);
610 assert_eq_m256i(r, src);
611 let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
612 assert_eq_m256i(r, a);
613 }
614
615 #[simd_test(enable = "avx512f,avx512vl")]
616 unsafe fn test_mm256_maskz_mov_epi64() {
617 let a = _mm256_set1_epi64x(2);
618 let r = _mm256_maskz_mov_epi64(0, a);
619 assert_eq_m256i(r, _mm256_setzero_si256());
620 let r = _mm256_maskz_mov_epi64(0b00001111, a);
621 assert_eq_m256i(r, a);
622 }
623
624 #[simd_test(enable = "avx512f,avx512vl")]
625 unsafe fn test_mm_mask_mov_epi64() {
626 let src = _mm_set1_epi64x(1);
627 let a = _mm_set1_epi64x(2);
628 let r = _mm_mask_mov_epi64(src, 0, a);
629 assert_eq_m128i(r, src);
630 let r = _mm_mask_mov_epi64(src, 0b00000011, a);
631 assert_eq_m128i(r, a);
632 }
633
634 #[simd_test(enable = "avx512f,avx512vl")]
635 unsafe fn test_mm_maskz_mov_epi64() {
636 let a = _mm_set1_epi64x(2);
637 let r = _mm_maskz_mov_epi64(0, a);
638 assert_eq_m128i(r, _mm_setzero_si128());
639 let r = _mm_maskz_mov_epi64(0b00000011, a);
640 assert_eq_m128i(r, a);
641 }
642
643 #[simd_test(enable = "avx512f")]
644 unsafe fn test_mm512_mask_mov_pd() {
645 let src = _mm512_set1_pd(1.);
646 let a = _mm512_set1_pd(2.);
647 let r = _mm512_mask_mov_pd(src, 0, a);
648 assert_eq_m512d(r, src);
649 let r = _mm512_mask_mov_pd(src, 0b11111111, a);
650 assert_eq_m512d(r, a);
651 }
652
653 #[simd_test(enable = "avx512f")]
654 unsafe fn test_mm512_maskz_mov_pd() {
655 let a = _mm512_set1_pd(2.);
656 let r = _mm512_maskz_mov_pd(0, a);
657 assert_eq_m512d(r, _mm512_setzero_pd());
658 let r = _mm512_maskz_mov_pd(0b11111111, a);
659 assert_eq_m512d(r, a);
660 }
661
662 #[simd_test(enable = "avx512f,avx512vl")]
663 unsafe fn test_mm256_mask_mov_pd() {
664 let src = _mm256_set1_pd(1.);
665 let a = _mm256_set1_pd(2.);
666 let r = _mm256_mask_mov_pd(src, 0, a);
667 assert_eq_m256d(r, src);
668 let r = _mm256_mask_mov_pd(src, 0b00001111, a);
669 assert_eq_m256d(r, a);
670 }
671
672 #[simd_test(enable = "avx512f,avx512vl")]
673 unsafe fn test_mm256_maskz_mov_pd() {
674 let a = _mm256_set1_pd(2.);
675 let r = _mm256_maskz_mov_pd(0, a);
676 assert_eq_m256d(r, _mm256_setzero_pd());
677 let r = _mm256_maskz_mov_pd(0b00001111, a);
678 assert_eq_m256d(r, a);
679 }
680
681 #[simd_test(enable = "avx512f,avx512vl")]
682 unsafe fn test_mm_mask_mov_pd() {
683 let src = _mm_set1_pd(1.);
684 let a = _mm_set1_pd(2.);
685 let r = _mm_mask_mov_pd(src, 0, a);
686 assert_eq_m128d(r, src);
687 let r = _mm_mask_mov_pd(src, 0b00000011, a);
688 assert_eq_m128d(r, a);
689 }
690
691 #[simd_test(enable = "avx512f,avx512vl")]
692 unsafe fn test_mm_maskz_mov_pd() {
693 let a = _mm_set1_pd(2.);
694 let r = _mm_maskz_mov_pd(0, a);
695 assert_eq_m128d(r, _mm_setzero_pd());
696 let r = _mm_maskz_mov_pd(0b00000011, a);
697 assert_eq_m128d(r, a);
698 }
699
700 #[simd_test(enable = "avx512f")]
701 unsafe fn test_mm512_add_epi64() {
702 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
703 let b = _mm512_set1_epi64(1);
704 let r = _mm512_add_epi64(a, b);
705 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
706 assert_eq_m512i(r, e);
707 }
708
709 #[simd_test(enable = "avx512f")]
710 unsafe fn test_mm512_mask_add_epi64() {
711 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
712 let b = _mm512_set1_epi64(1);
713 let r = _mm512_mask_add_epi64(a, 0, a, b);
714 assert_eq_m512i(r, a);
715 let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
716 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
717 assert_eq_m512i(r, e);
718 }
719
720 #[simd_test(enable = "avx512f")]
721 unsafe fn test_mm512_maskz_add_epi64() {
722 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
723 let b = _mm512_set1_epi64(1);
724 let r = _mm512_maskz_add_epi64(0, a, b);
725 assert_eq_m512i(r, _mm512_setzero_si512());
726 let r = _mm512_maskz_add_epi64(0b00001111, a, b);
727 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
728 assert_eq_m512i(r, e);
729 }
730
731 #[simd_test(enable = "avx512f,avx512vl")]
732 unsafe fn test_mm256_mask_add_epi64() {
733 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
734 let b = _mm256_set1_epi64x(1);
735 let r = _mm256_mask_add_epi64(a, 0, a, b);
736 assert_eq_m256i(r, a);
737 let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
738 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
739 assert_eq_m256i(r, e);
740 }
741
742 #[simd_test(enable = "avx512f,avx512vl")]
743 unsafe fn test_mm256_maskz_add_epi64() {
744 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
745 let b = _mm256_set1_epi64x(1);
746 let r = _mm256_maskz_add_epi64(0, a, b);
747 assert_eq_m256i(r, _mm256_setzero_si256());
748 let r = _mm256_maskz_add_epi64(0b00001111, a, b);
749 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
750 assert_eq_m256i(r, e);
751 }
752
753 #[simd_test(enable = "avx512f,avx512vl")]
754 unsafe fn test_mm_mask_add_epi64() {
755 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
756 let b = _mm_set1_epi64x(1);
757 let r = _mm_mask_add_epi64(a, 0, a, b);
758 assert_eq_m128i(r, a);
759 let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
760 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
761 assert_eq_m128i(r, e);
762 }
763
764 #[simd_test(enable = "avx512f,avx512vl")]
765 unsafe fn test_mm_maskz_add_epi64() {
766 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
767 let b = _mm_set1_epi64x(1);
768 let r = _mm_maskz_add_epi64(0, a, b);
769 assert_eq_m128i(r, _mm_setzero_si128());
770 let r = _mm_maskz_add_epi64(0b00000011, a, b);
771 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
772 assert_eq_m128i(r, e);
773 }
774
775 #[simd_test(enable = "avx512f")]
776 unsafe fn test_mm512_add_pd() {
777 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
778 let b = _mm512_set1_pd(1.);
779 let r = _mm512_add_pd(a, b);
780 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
781 assert_eq_m512d(r, e);
782 }
783
784 #[simd_test(enable = "avx512f")]
785 unsafe fn test_mm512_mask_add_pd() {
786 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
787 let b = _mm512_set1_pd(1.);
788 let r = _mm512_mask_add_pd(a, 0, a, b);
789 assert_eq_m512d(r, a);
790 let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
791 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
792 assert_eq_m512d(r, e);
793 }
794
795 #[simd_test(enable = "avx512f")]
796 unsafe fn test_mm512_maskz_add_pd() {
797 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
798 let b = _mm512_set1_pd(1.);
799 let r = _mm512_maskz_add_pd(0, a, b);
800 assert_eq_m512d(r, _mm512_setzero_pd());
801 let r = _mm512_maskz_add_pd(0b00001111, a, b);
802 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
803 assert_eq_m512d(r, e);
804 }
805
806 #[simd_test(enable = "avx512f,avx512vl")]
807 unsafe fn test_mm256_mask_add_pd() {
808 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
809 let b = _mm256_set1_pd(1.);
810 let r = _mm256_mask_add_pd(a, 0, a, b);
811 assert_eq_m256d(r, a);
812 let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
813 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
814 assert_eq_m256d(r, e);
815 }
816
817 #[simd_test(enable = "avx512f,avx512vl")]
818 unsafe fn test_mm256_maskz_add_pd() {
819 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
820 let b = _mm256_set1_pd(1.);
821 let r = _mm256_maskz_add_pd(0, a, b);
822 assert_eq_m256d(r, _mm256_setzero_pd());
823 let r = _mm256_maskz_add_pd(0b00001111, a, b);
824 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
825 assert_eq_m256d(r, e);
826 }
827
828 #[simd_test(enable = "avx512f,avx512vl")]
829 unsafe fn test_mm_mask_add_pd() {
830 let a = _mm_set_pd(f64::MAX, f64::MIN);
831 let b = _mm_set1_pd(1.);
832 let r = _mm_mask_add_pd(a, 0, a, b);
833 assert_eq_m128d(r, a);
834 let r = _mm_mask_add_pd(a, 0b00000011, a, b);
835 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
836 assert_eq_m128d(r, e);
837 }
838
839 #[simd_test(enable = "avx512f,avx512vl")]
840 unsafe fn test_mm_maskz_add_pd() {
841 let a = _mm_set_pd(f64::MAX, f64::MIN);
842 let b = _mm_set1_pd(1.);
843 let r = _mm_maskz_add_pd(0, a, b);
844 assert_eq_m128d(r, _mm_setzero_pd());
845 let r = _mm_maskz_add_pd(0b00000011, a, b);
846 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
847 assert_eq_m128d(r, e);
848 }
849
850 #[simd_test(enable = "avx512f")]
851 unsafe fn test_mm512_sub_epi64() {
852 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
853 let b = _mm512_set1_epi64(1);
854 let r = _mm512_sub_epi64(a, b);
855 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
856 assert_eq_m512i(r, e);
857 }
858
859 #[simd_test(enable = "avx512f")]
860 unsafe fn test_mm512_mask_sub_epi64() {
861 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
862 let b = _mm512_set1_epi64(1);
863 let r = _mm512_mask_sub_epi64(a, 0, a, b);
864 assert_eq_m512i(r, a);
865 let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
866 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
867 assert_eq_m512i(r, e);
868 }
869
870 #[simd_test(enable = "avx512f")]
871 unsafe fn test_mm512_maskz_sub_epi64() {
872 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
873 let b = _mm512_set1_epi64(1);
874 let r = _mm512_maskz_sub_epi64(0, a, b);
875 assert_eq_m512i(r, _mm512_setzero_si512());
876 let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
877 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
878 assert_eq_m512i(r, e);
879 }
880
881 #[simd_test(enable = "avx512f,avx512vl")]
882 unsafe fn test_mm256_mask_sub_epi64() {
883 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
884 let b = _mm256_set1_epi64x(1);
885 let r = _mm256_mask_sub_epi64(a, 0, a, b);
886 assert_eq_m256i(r, a);
887 let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
888 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
889 assert_eq_m256i(r, e);
890 }
891
892 #[simd_test(enable = "avx512f,avx512vl")]
893 unsafe fn test_mm256_maskz_sub_epi64() {
894 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
895 let b = _mm256_set1_epi64x(1);
896 let r = _mm256_maskz_sub_epi64(0, a, b);
897 assert_eq_m256i(r, _mm256_setzero_si256());
898 let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
899 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
900 assert_eq_m256i(r, e);
901 }
902
903 #[simd_test(enable = "avx512f,avx512vl")]
904 unsafe fn test_mm_mask_sub_epi64() {
905 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
906 let b = _mm_set1_epi64x(1);
907 let r = _mm_mask_sub_epi64(a, 0, a, b);
908 assert_eq_m128i(r, a);
909 let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
910 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
911 assert_eq_m128i(r, e);
912 }
913
914 #[simd_test(enable = "avx512f,avx512vl")]
915 unsafe fn test_mm_maskz_sub_epi64() {
916 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
917 let b = _mm_set1_epi64x(1);
918 let r = _mm_maskz_sub_epi64(0, a, b);
919 assert_eq_m128i(r, _mm_setzero_si128());
920 let r = _mm_maskz_sub_epi64(0b00000011, a, b);
921 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
922 assert_eq_m128i(r, e);
923 }
924
925 #[simd_test(enable = "avx512f")]
926 unsafe fn test_mm512_sub_pd() {
927 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
928 let b = _mm512_set1_pd(1.);
929 let r = _mm512_sub_pd(a, b);
930 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
931 assert_eq_m512d(r, e);
932 }
933
934 #[simd_test(enable = "avx512f")]
935 unsafe fn test_mm512_mask_sub_pd() {
936 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
937 let b = _mm512_set1_pd(1.);
938 let r = _mm512_mask_sub_pd(a, 0, a, b);
939 assert_eq_m512d(r, a);
940 let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
941 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
942 assert_eq_m512d(r, e);
943 }
944
945 #[simd_test(enable = "avx512f")]
946 unsafe fn test_mm512_maskz_sub_pd() {
947 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
948 let b = _mm512_set1_pd(1.);
949 let r = _mm512_maskz_sub_pd(0, a, b);
950 assert_eq_m512d(r, _mm512_setzero_pd());
951 let r = _mm512_maskz_sub_pd(0b00001111, a, b);
952 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
953 assert_eq_m512d(r, e);
954 }
955
956 #[simd_test(enable = "avx512f,avx512vl")]
957 unsafe fn test_mm256_mask_sub_pd() {
958 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
959 let b = _mm256_set1_pd(1.);
960 let r = _mm256_mask_sub_pd(a, 0, a, b);
961 assert_eq_m256d(r, a);
962 let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
963 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
964 assert_eq_m256d(r, e);
965 }
966
967 #[simd_test(enable = "avx512f,avx512vl")]
968 unsafe fn test_mm256_maskz_sub_pd() {
969 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
970 let b = _mm256_set1_pd(1.);
971 let r = _mm256_maskz_sub_pd(0, a, b);
972 assert_eq_m256d(r, _mm256_setzero_pd());
973 let r = _mm256_maskz_sub_pd(0b00001111, a, b);
974 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
975 assert_eq_m256d(r, e);
976 }
977
978 #[simd_test(enable = "avx512f,avx512vl")]
979 unsafe fn test_mm_mask_sub_pd() {
980 let a = _mm_set_pd(f64::MAX, f64::MIN);
981 let b = _mm_set1_pd(1.);
982 let r = _mm_mask_sub_pd(a, 0, a, b);
983 assert_eq_m128d(r, a);
984 let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
985 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
986 assert_eq_m128d(r, e);
987 }
988
989 #[simd_test(enable = "avx512f,avx512vl")]
990 unsafe fn test_mm_maskz_sub_pd() {
991 let a = _mm_set_pd(f64::MAX, f64::MIN);
992 let b = _mm_set1_pd(1.);
993 let r = _mm_maskz_sub_pd(0, a, b);
994 assert_eq_m128d(r, _mm_setzero_pd());
995 let r = _mm_maskz_sub_pd(0b00000011, a, b);
996 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
997 assert_eq_m128d(r, e);
998 }
999
1000 #[simd_test(enable = "avx512f")]
1001 unsafe fn test_mm512_mul_epi32() {
1002 let a = _mm512_set1_epi32(1);
1003 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1004 let r = _mm512_mul_epi32(a, b);
1005 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1006 assert_eq_m512i(r, e);
1007 }
1008
1009 #[simd_test(enable = "avx512f")]
1010 unsafe fn test_mm512_mask_mul_epi32() {
1011 let a = _mm512_set1_epi32(1);
1012 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1013 let r = _mm512_mask_mul_epi32(a, 0, a, b);
1014 assert_eq_m512i(r, a);
1015 let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1016 #[rustfmt::skip]
1017 let e = _mm512_set_epi64(
1018 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1019 7, 5, 3, 1,
1020 );
1021 assert_eq_m512i(r, e);
1022 }
1023
1024 #[simd_test(enable = "avx512f")]
1025 unsafe fn test_mm512_maskz_mul_epi32() {
1026 let a = _mm512_set1_epi32(1);
1027 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1028 let r = _mm512_maskz_mul_epi32(0, a, b);
1029 assert_eq_m512i(r, _mm512_setzero_si512());
1030 let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1031 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1032 assert_eq_m512i(r, e);
1033 }
1034
1035 #[simd_test(enable = "avx512f,avx512vl")]
1036 unsafe fn test_mm256_mask_mul_epi32() {
1037 let a = _mm256_set1_epi32(1);
1038 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1039 let r = _mm256_mask_mul_epi32(a, 0, a, b);
1040 assert_eq_m256i(r, a);
1041 let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1042 let e = _mm256_set_epi64x(2, 4, 6, 8);
1043 assert_eq_m256i(r, e);
1044 }
1045
1046 #[simd_test(enable = "avx512f,avx512vl")]
1047 unsafe fn test_mm256_maskz_mul_epi32() {
1048 let a = _mm256_set1_epi32(1);
1049 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1050 let r = _mm256_maskz_mul_epi32(0, a, b);
1051 assert_eq_m256i(r, _mm256_setzero_si256());
1052 let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1053 let e = _mm256_set_epi64x(2, 4, 6, 8);
1054 assert_eq_m256i(r, e);
1055 }
1056
1057 #[simd_test(enable = "avx512f,avx512vl")]
1058 unsafe fn test_mm_mask_mul_epi32() {
1059 let a = _mm_set1_epi32(1);
1060 let b = _mm_set_epi32(1, 2, 3, 4);
1061 let r = _mm_mask_mul_epi32(a, 0, a, b);
1062 assert_eq_m128i(r, a);
1063 let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1064 let e = _mm_set_epi64x(2, 4);
1065 assert_eq_m128i(r, e);
1066 }
1067
1068 #[simd_test(enable = "avx512f,avx512vl")]
1069 unsafe fn test_mm_maskz_mul_epi32() {
1070 let a = _mm_set1_epi32(1);
1071 let b = _mm_set_epi32(1, 2, 3, 4);
1072 let r = _mm_maskz_mul_epi32(0, a, b);
1073 assert_eq_m128i(r, _mm_setzero_si128());
1074 let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1075 let e = _mm_set_epi64x(2, 4);
1076 assert_eq_m128i(r, e);
1077 }
1078
1079 #[simd_test(enable = "avx512f")]
1080 unsafe fn test_mm512_mul_epu32() {
1081 let a = _mm512_set1_epi32(1);
1082 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1083 let r = _mm512_mul_epu32(a, b);
1084 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1085 assert_eq_m512i(r, e);
1086 }
1087
1088 #[simd_test(enable = "avx512f")]
1089 unsafe fn test_mm512_mask_mul_epu32() {
1090 let a = _mm512_set1_epi32(1);
1091 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1092 let r = _mm512_mask_mul_epu32(a, 0, a, b);
1093 assert_eq_m512i(r, a);
1094 let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1095 #[rustfmt::skip]
1096 let e = _mm512_set_epi64(
1097 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1098 7, 5, 3, 1,
1099 );
1100 assert_eq_m512i(r, e);
1101 }
1102
1103 #[simd_test(enable = "avx512f")]
1104 unsafe fn test_mm512_maskz_mul_epu32() {
1105 let a = _mm512_set1_epi32(1);
1106 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1107 let r = _mm512_maskz_mul_epu32(0, a, b);
1108 assert_eq_m512i(r, _mm512_setzero_si512());
1109 let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1110 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1111 assert_eq_m512i(r, e);
1112 }
1113
1114 #[simd_test(enable = "avx512f,avx512vl")]
1115 unsafe fn test_mm256_mask_mul_epu32() {
1116 let a = _mm256_set1_epi32(1);
1117 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1118 let r = _mm256_mask_mul_epu32(a, 0, a, b);
1119 assert_eq_m256i(r, a);
1120 let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1121 let e = _mm256_set_epi64x(2, 4, 6, 8);
1122 assert_eq_m256i(r, e);
1123 }
1124
1125 #[simd_test(enable = "avx512f,avx512vl")]
1126 unsafe fn test_mm256_maskz_mul_epu32() {
1127 let a = _mm256_set1_epi32(1);
1128 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1129 let r = _mm256_maskz_mul_epu32(0, a, b);
1130 assert_eq_m256i(r, _mm256_setzero_si256());
1131 let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1132 let e = _mm256_set_epi64x(2, 4, 6, 8);
1133 assert_eq_m256i(r, e);
1134 }
1135
1136 #[simd_test(enable = "avx512f,avx512vl")]
1137 unsafe fn test_mm_mask_mul_epu32() {
1138 let a = _mm_set1_epi32(1);
1139 let b = _mm_set_epi32(1, 2, 3, 4);
1140 let r = _mm_mask_mul_epu32(a, 0, a, b);
1141 assert_eq_m128i(r, a);
1142 let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1143 let e = _mm_set_epi64x(2, 4);
1144 assert_eq_m128i(r, e);
1145 }
1146
1147 #[simd_test(enable = "avx512f,avx512vl")]
1148 unsafe fn test_mm_maskz_mul_epu32() {
1149 let a = _mm_set1_epi32(1);
1150 let b = _mm_set_epi32(1, 2, 3, 4);
1151 let r = _mm_maskz_mul_epu32(0, a, b);
1152 assert_eq_m128i(r, _mm_setzero_si128());
1153 let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1154 let e = _mm_set_epi64x(2, 4);
1155 assert_eq_m128i(r, e);
1156 }
1157
1158 #[simd_test(enable = "avx512f")]
1159 unsafe fn test_mm512_mullox_epi64() {
1160 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1161 let b = _mm512_set1_epi64(2);
1162 let r = _mm512_mullox_epi64(a, b);
1163 let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1164 assert_eq_m512i(r, e);
1165 }
1166
1167 #[simd_test(enable = "avx512f")]
1168 unsafe fn test_mm512_mask_mullox_epi64() {
1169 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1170 let b = _mm512_set1_epi64(2);
1171 let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1172 assert_eq_m512i(r, a);
1173 let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1174 let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1175 assert_eq_m512i(r, e);
1176 }
1177
1178 #[simd_test(enable = "avx512f")]
1179 unsafe fn test_mm512_mul_pd() {
1180 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1181 let b = _mm512_set1_pd(2.);
1182 let r = _mm512_mul_pd(a, b);
1183 #[rustfmt::skip]
1184 let e = _mm512_setr_pd(
1185 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1186 f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1187 );
1188 assert_eq_m512d(r, e);
1189 }
1190
1191 #[simd_test(enable = "avx512f")]
1192 unsafe fn test_mm512_mask_mul_pd() {
1193 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1194 let b = _mm512_set1_pd(2.);
1195 let r = _mm512_mask_mul_pd(a, 0, a, b);
1196 assert_eq_m512d(r, a);
1197 let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1198 #[rustfmt::skip]
1199 let e = _mm512_setr_pd(
1200 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1201 f64::MAX, f64::MIN, -100., -32.,
1202 );
1203 assert_eq_m512d(r, e);
1204 }
1205
1206 #[simd_test(enable = "avx512f")]
1207 unsafe fn test_mm512_maskz_mul_pd() {
1208 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1209 let b = _mm512_set1_pd(2.);
1210 let r = _mm512_maskz_mul_pd(0, a, b);
1211 assert_eq_m512d(r, _mm512_setzero_pd());
1212 let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1213 let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1214 assert_eq_m512d(r, e);
1215 }
1216
1217 #[simd_test(enable = "avx512f,avx512vl")]
1218 unsafe fn test_mm256_mask_mul_pd() {
1219 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1220 let b = _mm256_set1_pd(2.);
1221 let r = _mm256_mask_mul_pd(a, 0, a, b);
1222 assert_eq_m256d(r, a);
1223 let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1224 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1225 assert_eq_m256d(r, e);
1226 }
1227
1228 #[simd_test(enable = "avx512f,avx512vl")]
1229 unsafe fn test_mm256_maskz_mul_pd() {
1230 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1231 let b = _mm256_set1_pd(2.);
1232 let r = _mm256_maskz_mul_pd(0, a, b);
1233 assert_eq_m256d(r, _mm256_setzero_pd());
1234 let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1235 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1236 assert_eq_m256d(r, e);
1237 }
1238
1239 #[simd_test(enable = "avx512f,avx512vl")]
1240 unsafe fn test_mm_mask_mul_pd() {
1241 let a = _mm_set_pd(f64::MAX, f64::MIN);
1242 let b = _mm_set1_pd(2.);
1243 let r = _mm_mask_mul_pd(a, 0, a, b);
1244 assert_eq_m128d(r, a);
1245 let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1246 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1247 assert_eq_m128d(r, e);
1248 }
1249
1250 #[simd_test(enable = "avx512f,avx512vl")]
1251 unsafe fn test_mm_maskz_mul_pd() {
1252 let a = _mm_set_pd(f64::MAX, f64::MIN);
1253 let b = _mm_set1_pd(2.);
1254 let r = _mm_maskz_mul_pd(0, a, b);
1255 assert_eq_m128d(r, _mm_setzero_pd());
1256 let r = _mm_maskz_mul_pd(0b00000011, a, b);
1257 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1258 assert_eq_m128d(r, e);
1259 }
1260
1261 #[simd_test(enable = "avx512f")]
1262 unsafe fn test_mm512_div_pd() {
1263 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1264 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1265 let r = _mm512_div_pd(a, b);
1266 #[rustfmt::skip]
1267 let e = _mm512_setr_pd(
1268 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1269 f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1270 );
1271 assert_eq_m512d(r, e);
1272 }
1273
1274 #[simd_test(enable = "avx512f")]
1275 unsafe fn test_mm512_mask_div_pd() {
1276 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1277 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1278 let r = _mm512_mask_div_pd(a, 0, a, b);
1279 assert_eq_m512d(r, a);
1280 let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1281 #[rustfmt::skip]
1282 let e = _mm512_setr_pd(
1283 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1284 f64::MAX, f64::MIN, -100., -32.,
1285 );
1286 assert_eq_m512d(r, e);
1287 }
1288
1289 #[simd_test(enable = "avx512f")]
1290 unsafe fn test_mm512_maskz_div_pd() {
1291 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1292 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1293 let r = _mm512_maskz_div_pd(0, a, b);
1294 assert_eq_m512d(r, _mm512_setzero_pd());
1295 let r = _mm512_maskz_div_pd(0b00001111, a, b);
1296 let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1297 assert_eq_m512d(r, e);
1298 }
1299
1300 #[simd_test(enable = "avx512f,avx512vl")]
1301 unsafe fn test_mm256_mask_div_pd() {
1302 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1303 let b = _mm256_set_pd(2., 2., 0., 0.);
1304 let r = _mm256_mask_div_pd(a, 0, a, b);
1305 assert_eq_m256d(r, a);
1306 let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1307 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1308 assert_eq_m256d(r, e);
1309 }
1310
1311 #[simd_test(enable = "avx512f,avx512vl")]
1312 unsafe fn test_mm256_maskz_div_pd() {
1313 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1314 let b = _mm256_set_pd(2., 2., 0., 0.);
1315 let r = _mm256_maskz_div_pd(0, a, b);
1316 assert_eq_m256d(r, _mm256_setzero_pd());
1317 let r = _mm256_maskz_div_pd(0b00001111, a, b);
1318 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1319 assert_eq_m256d(r, e);
1320 }
1321
1322 #[simd_test(enable = "avx512f,avx512vl")]
1323 unsafe fn test_mm_mask_div_pd() {
1324 let a = _mm_set_pd(f64::MAX, f64::MIN);
1325 let b = _mm_set_pd(0., 0.);
1326 let r = _mm_mask_div_pd(a, 0, a, b);
1327 assert_eq_m128d(r, a);
1328 let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1329 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1330 assert_eq_m128d(r, e);
1331 }
1332
1333 #[simd_test(enable = "avx512f,avx512vl")]
1334 unsafe fn test_mm_maskz_div_pd() {
1335 let a = _mm_set_pd(f64::MAX, f64::MIN);
1336 let b = _mm_set_pd(0., 0.);
1337 let r = _mm_maskz_div_pd(0, a, b);
1338 assert_eq_m128d(r, _mm_setzero_pd());
1339 let r = _mm_maskz_div_pd(0b00000011, a, b);
1340 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1341 assert_eq_m128d(r, e);
1342 }
1343
1344 #[simd_test(enable = "avx512f")]
1345 unsafe fn test_mm512_max_epi64() {
1346 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1347 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1348 let r = _mm512_max_epi64(a, b);
1349 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1350 assert_eq_m512i(r, e);
1351 }
1352
1353 #[simd_test(enable = "avx512f")]
1354 unsafe fn test_mm512_mask_max_epi64() {
1355 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1356 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1357 let r = _mm512_mask_max_epi64(a, 0, a, b);
1358 assert_eq_m512i(r, a);
1359 let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1360 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1361 assert_eq_m512i(r, e);
1362 }
1363
1364 #[simd_test(enable = "avx512f")]
1365 unsafe fn test_mm512_maskz_max_epi64() {
1366 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1367 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1368 let r = _mm512_maskz_max_epi64(0, a, b);
1369 assert_eq_m512i(r, _mm512_setzero_si512());
1370 let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1371 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1372 assert_eq_m512i(r, e);
1373 }
1374
1375 #[simd_test(enable = "avx512f,avx512vl")]
1376 unsafe fn test_mm256_max_epi64() {
1377 let a = _mm256_set_epi64x(0, 1, 2, 3);
1378 let b = _mm256_set_epi64x(3, 2, 1, 0);
1379 let r = _mm256_max_epi64(a, b);
1380 let e = _mm256_set_epi64x(3, 2, 2, 3);
1381 assert_eq_m256i(r, e);
1382 }
1383
1384 #[simd_test(enable = "avx512f,avx512vl")]
1385 unsafe fn test_mm256_mask_max_epi64() {
1386 let a = _mm256_set_epi64x(0, 1, 2, 3);
1387 let b = _mm256_set_epi64x(3, 2, 1, 0);
1388 let r = _mm256_mask_max_epi64(a, 0, a, b);
1389 assert_eq_m256i(r, a);
1390 let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1391 let e = _mm256_set_epi64x(3, 2, 2, 3);
1392 assert_eq_m256i(r, e);
1393 }
1394
1395 #[simd_test(enable = "avx512f,avx512vl")]
1396 unsafe fn test_mm256_maskz_max_epi64() {
1397 let a = _mm256_set_epi64x(0, 1, 2, 3);
1398 let b = _mm256_set_epi64x(3, 2, 1, 0);
1399 let r = _mm256_maskz_max_epi64(0, a, b);
1400 assert_eq_m256i(r, _mm256_setzero_si256());
1401 let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1402 let e = _mm256_set_epi64x(3, 2, 2, 3);
1403 assert_eq_m256i(r, e);
1404 }
1405
1406 #[simd_test(enable = "avx512f,avx512vl")]
1407 unsafe fn test_mm_max_epi64() {
1408 let a = _mm_set_epi64x(2, 3);
1409 let b = _mm_set_epi64x(3, 2);
1410 let r = _mm_max_epi64(a, b);
1411 let e = _mm_set_epi64x(3, 3);
1412 assert_eq_m128i(r, e);
1413 }
1414
1415 #[simd_test(enable = "avx512f,avx512vl")]
1416 unsafe fn test_mm_mask_max_epi64() {
1417 let a = _mm_set_epi64x(2, 3);
1418 let b = _mm_set_epi64x(3, 2);
1419 let r = _mm_mask_max_epi64(a, 0, a, b);
1420 assert_eq_m128i(r, a);
1421 let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1422 let e = _mm_set_epi64x(3, 3);
1423 assert_eq_m128i(r, e);
1424 }
1425
1426 #[simd_test(enable = "avx512f,avx512vl")]
1427 unsafe fn test_mm_maskz_max_epi64() {
1428 let a = _mm_set_epi64x(2, 3);
1429 let b = _mm_set_epi64x(3, 2);
1430 let r = _mm_maskz_max_epi64(0, a, b);
1431 assert_eq_m128i(r, _mm_setzero_si128());
1432 let r = _mm_maskz_max_epi64(0b00000011, a, b);
1433 let e = _mm_set_epi64x(3, 3);
1434 assert_eq_m128i(r, e);
1435 }
1436
1437 #[simd_test(enable = "avx512f")]
1438 unsafe fn test_mm512_max_pd() {
1439 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1440 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1441 let r = _mm512_max_pd(a, b);
1442 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1443 assert_eq_m512d(r, e);
1444 }
1445
1446 #[simd_test(enable = "avx512f")]
1447 unsafe fn test_mm512_mask_max_pd() {
1448 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1449 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1450 let r = _mm512_mask_max_pd(a, 0, a, b);
1451 assert_eq_m512d(r, a);
1452 let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1453 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1454 assert_eq_m512d(r, e);
1455 }
1456
1457 #[simd_test(enable = "avx512f")]
1458 unsafe fn test_mm512_maskz_max_pd() {
1459 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1460 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1461 let r = _mm512_maskz_max_pd(0, a, b);
1462 assert_eq_m512d(r, _mm512_setzero_pd());
1463 let r = _mm512_maskz_max_pd(0b00001111, a, b);
1464 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1465 assert_eq_m512d(r, e);
1466 }
1467
1468 #[simd_test(enable = "avx512f,avx512vl")]
1469 unsafe fn test_mm256_mask_max_pd() {
1470 let a = _mm256_set_pd(0., 1., 2., 3.);
1471 let b = _mm256_set_pd(3., 2., 1., 0.);
1472 let r = _mm256_mask_max_pd(a, 0, a, b);
1473 assert_eq_m256d(r, a);
1474 let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1475 let e = _mm256_set_pd(3., 2., 2., 3.);
1476 assert_eq_m256d(r, e);
1477 }
1478
1479 #[simd_test(enable = "avx512f,avx512vl")]
1480 unsafe fn test_mm256_maskz_max_pd() {
1481 let a = _mm256_set_pd(0., 1., 2., 3.);
1482 let b = _mm256_set_pd(3., 2., 1., 0.);
1483 let r = _mm256_maskz_max_pd(0, a, b);
1484 assert_eq_m256d(r, _mm256_setzero_pd());
1485 let r = _mm256_maskz_max_pd(0b00001111, a, b);
1486 let e = _mm256_set_pd(3., 2., 2., 3.);
1487 assert_eq_m256d(r, e);
1488 }
1489
1490 #[simd_test(enable = "avx512f,avx512vl")]
1491 unsafe fn test_mm_mask_max_pd() {
1492 let a = _mm_set_pd(2., 3.);
1493 let b = _mm_set_pd(3., 2.);
1494 let r = _mm_mask_max_pd(a, 0, a, b);
1495 assert_eq_m128d(r, a);
1496 let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1497 let e = _mm_set_pd(3., 3.);
1498 assert_eq_m128d(r, e);
1499 }
1500
1501 #[simd_test(enable = "avx512f,avx512vl")]
1502 unsafe fn test_mm_maskz_max_pd() {
1503 let a = _mm_set_pd(2., 3.);
1504 let b = _mm_set_pd(3., 2.);
1505 let r = _mm_maskz_max_pd(0, a, b);
1506 assert_eq_m128d(r, _mm_setzero_pd());
1507 let r = _mm_maskz_max_pd(0b00000011, a, b);
1508 let e = _mm_set_pd(3., 3.);
1509 assert_eq_m128d(r, e);
1510 }
1511
1512 #[simd_test(enable = "avx512f")]
1513 unsafe fn test_mm512_max_epu64() {
1514 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1515 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1516 let r = _mm512_max_epu64(a, b);
1517 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1518 assert_eq_m512i(r, e);
1519 }
1520
1521 #[simd_test(enable = "avx512f")]
1522 unsafe fn test_mm512_mask_max_epu64() {
1523 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1524 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1525 let r = _mm512_mask_max_epu64(a, 0, a, b);
1526 assert_eq_m512i(r, a);
1527 let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1528 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1529 assert_eq_m512i(r, e);
1530 }
1531
1532 #[simd_test(enable = "avx512f")]
1533 unsafe fn test_mm512_maskz_max_epu64() {
1534 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1535 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1536 let r = _mm512_maskz_max_epu64(0, a, b);
1537 assert_eq_m512i(r, _mm512_setzero_si512());
1538 let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1539 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1540 assert_eq_m512i(r, e);
1541 }
1542
1543 #[simd_test(enable = "avx512f,avx512vl")]
1544 unsafe fn test_mm256_max_epu64() {
1545 let a = _mm256_set_epi64x(0, 1, 2, 3);
1546 let b = _mm256_set_epi64x(3, 2, 1, 0);
1547 let r = _mm256_max_epu64(a, b);
1548 let e = _mm256_set_epi64x(3, 2, 2, 3);
1549 assert_eq_m256i(r, e);
1550 }
1551
1552 #[simd_test(enable = "avx512f,avx512vl")]
1553 unsafe fn test_mm256_mask_max_epu64() {
1554 let a = _mm256_set_epi64x(0, 1, 2, 3);
1555 let b = _mm256_set_epi64x(3, 2, 1, 0);
1556 let r = _mm256_mask_max_epu64(a, 0, a, b);
1557 assert_eq_m256i(r, a);
1558 let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1559 let e = _mm256_set_epi64x(3, 2, 2, 3);
1560 assert_eq_m256i(r, e);
1561 }
1562
1563 #[simd_test(enable = "avx512f,avx512vl")]
1564 unsafe fn test_mm256_maskz_max_epu64() {
1565 let a = _mm256_set_epi64x(0, 1, 2, 3);
1566 let b = _mm256_set_epi64x(3, 2, 1, 0);
1567 let r = _mm256_maskz_max_epu64(0, a, b);
1568 assert_eq_m256i(r, _mm256_setzero_si256());
1569 let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1570 let e = _mm256_set_epi64x(3, 2, 2, 3);
1571 assert_eq_m256i(r, e);
1572 }
1573
1574 #[simd_test(enable = "avx512f,avx512vl")]
1575 unsafe fn test_mm_max_epu64() {
1576 let a = _mm_set_epi64x(2, 3);
1577 let b = _mm_set_epi64x(3, 2);
1578 let r = _mm_max_epu64(a, b);
1579 let e = _mm_set_epi64x(3, 3);
1580 assert_eq_m128i(r, e);
1581 }
1582
1583 #[simd_test(enable = "avx512f,avx512vl")]
1584 unsafe fn test_mm_mask_max_epu64() {
1585 let a = _mm_set_epi64x(2, 3);
1586 let b = _mm_set_epi64x(3, 2);
1587 let r = _mm_mask_max_epu64(a, 0, a, b);
1588 assert_eq_m128i(r, a);
1589 let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1590 let e = _mm_set_epi64x(3, 3);
1591 assert_eq_m128i(r, e);
1592 }
1593
1594 #[simd_test(enable = "avx512f,avx512vl")]
1595 unsafe fn test_mm_maskz_max_epu64() {
1596 let a = _mm_set_epi64x(2, 3);
1597 let b = _mm_set_epi64x(3, 2);
1598 let r = _mm_maskz_max_epu64(0, a, b);
1599 assert_eq_m128i(r, _mm_setzero_si128());
1600 let r = _mm_maskz_max_epu64(0b00000011, a, b);
1601 let e = _mm_set_epi64x(3, 3);
1602 assert_eq_m128i(r, e);
1603 }
1604
1605 #[simd_test(enable = "avx512f")]
1606 unsafe fn test_mm512_min_epi64() {
1607 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1608 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1609 let r = _mm512_min_epi64(a, b);
1610 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1611 assert_eq_m512i(r, e);
1612 }
1613
1614 #[simd_test(enable = "avx512f")]
1615 unsafe fn test_mm512_mask_min_epi64() {
1616 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1617 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1618 let r = _mm512_mask_min_epi64(a, 0, a, b);
1619 assert_eq_m512i(r, a);
1620 let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1621 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1622 assert_eq_m512i(r, e);
1623 }
1624
1625 #[simd_test(enable = "avx512f")]
1626 unsafe fn test_mm512_maskz_min_epi64() {
1627 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1628 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1629 let r = _mm512_maskz_min_epi64(0, a, b);
1630 assert_eq_m512i(r, _mm512_setzero_si512());
1631 let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1632 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1633 assert_eq_m512i(r, e);
1634 }
1635
1636 #[simd_test(enable = "avx512f,avx512vl")]
1637 unsafe fn test_mm256_min_epi64() {
1638 let a = _mm256_set_epi64x(0, 1, 2, 3);
1639 let b = _mm256_set_epi64x(3, 2, 1, 0);
1640 let r = _mm256_min_epi64(a, b);
1641 let e = _mm256_set_epi64x(0, 1, 1, 0);
1642 assert_eq_m256i(r, e);
1643 }
1644
1645 #[simd_test(enable = "avx512f,avx512vl")]
1646 unsafe fn test_mm256_mask_min_epi64() {
1647 let a = _mm256_set_epi64x(0, 1, 2, 3);
1648 let b = _mm256_set_epi64x(3, 2, 1, 0);
1649 let r = _mm256_mask_min_epi64(a, 0, a, b);
1650 assert_eq_m256i(r, a);
1651 let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1652 let e = _mm256_set_epi64x(0, 1, 1, 0);
1653 assert_eq_m256i(r, e);
1654 }
1655
1656 #[simd_test(enable = "avx512f,avx512vl")]
1657 unsafe fn test_mm256_maskz_min_epi64() {
1658 let a = _mm256_set_epi64x(0, 1, 2, 3);
1659 let b = _mm256_set_epi64x(3, 2, 1, 0);
1660 let r = _mm256_maskz_min_epi64(0, a, b);
1661 assert_eq_m256i(r, _mm256_setzero_si256());
1662 let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1663 let e = _mm256_set_epi64x(0, 1, 1, 0);
1664 assert_eq_m256i(r, e);
1665 }
1666
1667 #[simd_test(enable = "avx512f")]
1668 unsafe fn test_mm512_min_pd() {
1669 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1670 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1671 let r = _mm512_min_pd(a, b);
1672 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1673 assert_eq_m512d(r, e);
1674 }
1675
1676 #[simd_test(enable = "avx512f")]
1677 unsafe fn test_mm512_mask_min_pd() {
1678 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1679 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1680 let r = _mm512_mask_min_pd(a, 0, a, b);
1681 assert_eq_m512d(r, a);
1682 let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1683 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1684 assert_eq_m512d(r, e);
1685 }
1686
1687 #[simd_test(enable = "avx512f")]
1688 unsafe fn test_mm512_maskz_min_pd() {
1689 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1690 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1691 let r = _mm512_maskz_min_pd(0, a, b);
1692 assert_eq_m512d(r, _mm512_setzero_pd());
1693 let r = _mm512_maskz_min_pd(0b00001111, a, b);
1694 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1695 assert_eq_m512d(r, e);
1696 }
1697
1698 #[simd_test(enable = "avx512f,avx512vl")]
1699 unsafe fn test_mm256_mask_min_pd() {
1700 let a = _mm256_set_pd(0., 1., 2., 3.);
1701 let b = _mm256_set_pd(3., 2., 1., 0.);
1702 let r = _mm256_mask_min_pd(a, 0, a, b);
1703 assert_eq_m256d(r, a);
1704 let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1705 let e = _mm256_set_pd(0., 1., 1., 0.);
1706 assert_eq_m256d(r, e);
1707 }
1708
1709 #[simd_test(enable = "avx512f,avx512vl")]
1710 unsafe fn test_mm256_maskz_min_pd() {
1711 let a = _mm256_set_pd(0., 1., 2., 3.);
1712 let b = _mm256_set_pd(3., 2., 1., 0.);
1713 let r = _mm256_maskz_min_pd(0, a, b);
1714 assert_eq_m256d(r, _mm256_setzero_pd());
1715 let r = _mm256_maskz_min_pd(0b00001111, a, b);
1716 let e = _mm256_set_pd(0., 1., 1., 0.);
1717 assert_eq_m256d(r, e);
1718 }
1719
1720 #[simd_test(enable = "avx512f,avx512vl")]
1721 unsafe fn test_mm_mask_min_pd() {
1722 let a = _mm_set_pd(0., 1.);
1723 let b = _mm_set_pd(1., 0.);
1724 let r = _mm_mask_min_pd(a, 0, a, b);
1725 assert_eq_m128d(r, a);
1726 let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1727 let e = _mm_set_pd(0., 0.);
1728 assert_eq_m128d(r, e);
1729 }
1730
1731 #[simd_test(enable = "avx512f,avx512vl")]
1732 unsafe fn test_mm_maskz_min_pd() {
1733 let a = _mm_set_pd(0., 1.);
1734 let b = _mm_set_pd(1., 0.);
1735 let r = _mm_maskz_min_pd(0, a, b);
1736 assert_eq_m128d(r, _mm_setzero_pd());
1737 let r = _mm_maskz_min_pd(0b00000011, a, b);
1738 let e = _mm_set_pd(0., 0.);
1739 assert_eq_m128d(r, e);
1740 }
1741
1742 #[simd_test(enable = "avx512f")]
1743 unsafe fn test_mm512_min_epu64() {
1744 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1745 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1746 let r = _mm512_min_epu64(a, b);
1747 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1748 assert_eq_m512i(r, e);
1749 }
1750
1751 #[simd_test(enable = "avx512f")]
1752 unsafe fn test_mm512_mask_min_epu64() {
1753 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1754 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1755 let r = _mm512_mask_min_epu64(a, 0, a, b);
1756 assert_eq_m512i(r, a);
1757 let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1758 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1759 assert_eq_m512i(r, e);
1760 }
1761
1762 #[simd_test(enable = "avx512f")]
1763 unsafe fn test_mm512_maskz_min_epu64() {
1764 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1765 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1766 let r = _mm512_maskz_min_epu64(0, a, b);
1767 assert_eq_m512i(r, _mm512_setzero_si512());
1768 let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1769 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1770 assert_eq_m512i(r, e);
1771 }
1772
1773 #[simd_test(enable = "avx512f,avx512vl")]
1774 unsafe fn test_mm256_min_epu64() {
1775 let a = _mm256_set_epi64x(0, 1, 2, 3);
1776 let b = _mm256_set_epi64x(3, 2, 1, 0);
1777 let r = _mm256_min_epu64(a, b);
1778 let e = _mm256_set_epi64x(0, 1, 1, 0);
1779 assert_eq_m256i(r, e);
1780 }
1781
1782 #[simd_test(enable = "avx512f,avx512vl")]
1783 unsafe fn test_mm256_mask_min_epu64() {
1784 let a = _mm256_set_epi64x(0, 1, 2, 3);
1785 let b = _mm256_set_epi64x(3, 2, 1, 0);
1786 let r = _mm256_mask_min_epu64(a, 0, a, b);
1787 assert_eq_m256i(r, a);
1788 let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1789 let e = _mm256_set_epi64x(0, 1, 1, 0);
1790 assert_eq_m256i(r, e);
1791 }
1792
1793 #[simd_test(enable = "avx512f,avx512vl")]
1794 unsafe fn test_mm256_maskz_min_epu64() {
1795 let a = _mm256_set_epi64x(0, 1, 2, 3);
1796 let b = _mm256_set_epi64x(3, 2, 1, 0);
1797 let r = _mm256_maskz_min_epu64(0, a, b);
1798 assert_eq_m256i(r, _mm256_setzero_si256());
1799 let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1800 let e = _mm256_set_epi64x(0, 1, 1, 0);
1801 assert_eq_m256i(r, e);
1802 }
1803
1804 #[simd_test(enable = "avx512f,avx512vl")]
1805 unsafe fn test_mm_min_epu64() {
1806 let a = _mm_set_epi64x(0, 1);
1807 let b = _mm_set_epi64x(1, 0);
1808 let r = _mm_min_epu64(a, b);
1809 let e = _mm_set_epi64x(0, 0);
1810 assert_eq_m128i(r, e);
1811 }
1812
1813 #[simd_test(enable = "avx512f,avx512vl")]
1814 unsafe fn test_mm_mask_min_epu64() {
1815 let a = _mm_set_epi64x(0, 1);
1816 let b = _mm_set_epi64x(1, 0);
1817 let r = _mm_mask_min_epu64(a, 0, a, b);
1818 assert_eq_m128i(r, a);
1819 let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1820 let e = _mm_set_epi64x(0, 0);
1821 assert_eq_m128i(r, e);
1822 }
1823
1824 #[simd_test(enable = "avx512f,avx512vl")]
1825 unsafe fn test_mm_maskz_min_epu64() {
1826 let a = _mm_set_epi64x(0, 1);
1827 let b = _mm_set_epi64x(1, 0);
1828 let r = _mm_maskz_min_epu64(0, a, b);
1829 assert_eq_m128i(r, _mm_setzero_si128());
1830 let r = _mm_maskz_min_epu64(0b00000011, a, b);
1831 let e = _mm_set_epi64x(0, 0);
1832 assert_eq_m128i(r, e);
1833 }
1834
1835 #[simd_test(enable = "avx512f")]
1836 unsafe fn test_mm512_sqrt_pd() {
1837 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1838 let r = _mm512_sqrt_pd(a);
1839 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1840 assert_eq_m512d(r, e);
1841 }
1842
1843 #[simd_test(enable = "avx512f")]
1844 unsafe fn test_mm512_mask_sqrt_pd() {
1845 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1846 let r = _mm512_mask_sqrt_pd(a, 0, a);
1847 assert_eq_m512d(r, a);
1848 let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1849 let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1850 assert_eq_m512d(r, e);
1851 }
1852
1853 #[simd_test(enable = "avx512f")]
1854 unsafe fn test_mm512_maskz_sqrt_pd() {
1855 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1856 let r = _mm512_maskz_sqrt_pd(0, a);
1857 assert_eq_m512d(r, _mm512_setzero_pd());
1858 let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1859 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1860 assert_eq_m512d(r, e);
1861 }
1862
1863 #[simd_test(enable = "avx512f,avx512vl")]
1864 unsafe fn test_mm256_mask_sqrt_pd() {
1865 let a = _mm256_set_pd(0., 1., 4., 9.);
1866 let r = _mm256_mask_sqrt_pd(a, 0, a);
1867 assert_eq_m256d(r, a);
1868 let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
1869 let e = _mm256_set_pd(0., 1., 2., 3.);
1870 assert_eq_m256d(r, e);
1871 }
1872
1873 #[simd_test(enable = "avx512f,avx512vl")]
1874 unsafe fn test_mm256_maskz_sqrt_pd() {
1875 let a = _mm256_set_pd(0., 1., 4., 9.);
1876 let r = _mm256_maskz_sqrt_pd(0, a);
1877 assert_eq_m256d(r, _mm256_setzero_pd());
1878 let r = _mm256_maskz_sqrt_pd(0b00001111, a);
1879 let e = _mm256_set_pd(0., 1., 2., 3.);
1880 assert_eq_m256d(r, e);
1881 }
1882
1883 #[simd_test(enable = "avx512f,avx512vl")]
1884 unsafe fn test_mm_mask_sqrt_pd() {
1885 let a = _mm_set_pd(0., 1.);
1886 let r = _mm_mask_sqrt_pd(a, 0, a);
1887 assert_eq_m128d(r, a);
1888 let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
1889 let e = _mm_set_pd(0., 1.);
1890 assert_eq_m128d(r, e);
1891 }
1892
1893 #[simd_test(enable = "avx512f,avx512vl")]
1894 unsafe fn test_mm_maskz_sqrt_pd() {
1895 let a = _mm_set_pd(0., 1.);
1896 let r = _mm_maskz_sqrt_pd(0, a);
1897 assert_eq_m128d(r, _mm_setzero_pd());
1898 let r = _mm_maskz_sqrt_pd(0b00000011, a);
1899 let e = _mm_set_pd(0., 1.);
1900 assert_eq_m128d(r, e);
1901 }
1902
1903 #[simd_test(enable = "avx512f")]
1904 unsafe fn test_mm512_fmadd_pd() {
1905 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1906 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1907 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1908 let r = _mm512_fmadd_pd(a, b, c);
1909 let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
1910 assert_eq_m512d(r, e);
1911 }
1912
1913 #[simd_test(enable = "avx512f")]
1914 unsafe fn test_mm512_mask_fmadd_pd() {
1915 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1916 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1917 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1918 let r = _mm512_mask_fmadd_pd(a, 0, b, c);
1919 assert_eq_m512d(r, a);
1920 let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
1921 let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
1922 assert_eq_m512d(r, e);
1923 }
1924
1925 #[simd_test(enable = "avx512f")]
1926 unsafe fn test_mm512_maskz_fmadd_pd() {
1927 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1928 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1929 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1930 let r = _mm512_maskz_fmadd_pd(0, a, b, c);
1931 assert_eq_m512d(r, _mm512_setzero_pd());
1932 let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
1933 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
1934 assert_eq_m512d(r, e);
1935 }
1936
1937 #[simd_test(enable = "avx512f")]
1938 unsafe fn test_mm512_mask3_fmadd_pd() {
1939 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1940 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1941 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
1942 let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
1943 assert_eq_m512d(r, c);
1944 let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
1945 let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
1946 assert_eq_m512d(r, e);
1947 }
1948
1949 #[simd_test(enable = "avx512f,avx512vl")]
1950 unsafe fn test_mm256_mask_fmadd_pd() {
1951 let a = _mm256_set1_pd(1.);
1952 let b = _mm256_set_pd(0., 1., 2., 3.);
1953 let c = _mm256_set1_pd(1.);
1954 let r = _mm256_mask_fmadd_pd(a, 0, b, c);
1955 assert_eq_m256d(r, a);
1956 let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
1957 let e = _mm256_set_pd(1., 2., 3., 4.);
1958 assert_eq_m256d(r, e);
1959 }
1960
1961 #[simd_test(enable = "avx512f,avx512vl")]
1962 unsafe fn test_mm256_maskz_fmadd_pd() {
1963 let a = _mm256_set1_pd(1.);
1964 let b = _mm256_set_pd(0., 1., 2., 3.);
1965 let c = _mm256_set1_pd(1.);
1966 let r = _mm256_maskz_fmadd_pd(0, a, b, c);
1967 assert_eq_m256d(r, _mm256_setzero_pd());
1968 let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
1969 let e = _mm256_set_pd(1., 2., 3., 4.);
1970 assert_eq_m256d(r, e);
1971 }
1972
1973 #[simd_test(enable = "avx512f,avx512vl")]
1974 unsafe fn test_mm256_mask3_fmadd_pd() {
1975 let a = _mm256_set1_pd(1.);
1976 let b = _mm256_set_pd(0., 1., 2., 3.);
1977 let c = _mm256_set1_pd(1.);
1978 let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
1979 assert_eq_m256d(r, c);
1980 let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
1981 let e = _mm256_set_pd(1., 2., 3., 4.);
1982 assert_eq_m256d(r, e);
1983 }
1984
1985 #[simd_test(enable = "avx512f,avx512vl")]
1986 unsafe fn test_mm_mask_fmadd_pd() {
1987 let a = _mm_set1_pd(1.);
1988 let b = _mm_set_pd(0., 1.);
1989 let c = _mm_set1_pd(1.);
1990 let r = _mm_mask_fmadd_pd(a, 0, b, c);
1991 assert_eq_m128d(r, a);
1992 let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
1993 let e = _mm_set_pd(1., 2.);
1994 assert_eq_m128d(r, e);
1995 }
1996
1997 #[simd_test(enable = "avx512f,avx512vl")]
1998 unsafe fn test_mm_maskz_fmadd_pd() {
1999 let a = _mm_set1_pd(1.);
2000 let b = _mm_set_pd(0., 1.);
2001 let c = _mm_set1_pd(1.);
2002 let r = _mm_maskz_fmadd_pd(0, a, b, c);
2003 assert_eq_m128d(r, _mm_setzero_pd());
2004 let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2005 let e = _mm_set_pd(1., 2.);
2006 assert_eq_m128d(r, e);
2007 }
2008
2009 #[simd_test(enable = "avx512f,avx512vl")]
2010 unsafe fn test_mm_mask3_fmadd_pd() {
2011 let a = _mm_set1_pd(1.);
2012 let b = _mm_set_pd(0., 1.);
2013 let c = _mm_set1_pd(1.);
2014 let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2015 assert_eq_m128d(r, c);
2016 let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2017 let e = _mm_set_pd(1., 2.);
2018 assert_eq_m128d(r, e);
2019 }
2020
2021 #[simd_test(enable = "avx512f")]
2022 unsafe fn test_mm512_fmsub_pd() {
2023 let a = _mm512_set1_pd(1.);
2024 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2025 let c = _mm512_set1_pd(1.);
2026 let r = _mm512_fmsub_pd(a, b, c);
2027 let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2028 assert_eq_m512d(r, e);
2029 }
2030
2031 #[simd_test(enable = "avx512f")]
2032 unsafe fn test_mm512_mask_fmsub_pd() {
2033 let a = _mm512_set1_pd(1.);
2034 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2035 let c = _mm512_set1_pd(1.);
2036 let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2037 assert_eq_m512d(r, a);
2038 let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2039 let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2040 assert_eq_m512d(r, e);
2041 }
2042
2043 #[simd_test(enable = "avx512f")]
2044 unsafe fn test_mm512_maskz_fmsub_pd() {
2045 let a = _mm512_set1_pd(1.);
2046 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2047 let c = _mm512_set1_pd(1.);
2048 let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2049 assert_eq_m512d(r, _mm512_setzero_pd());
2050 let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2051 let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2052 assert_eq_m512d(r, e);
2053 }
2054
2055 #[simd_test(enable = "avx512f")]
2056 unsafe fn test_mm512_mask3_fmsub_pd() {
2057 let a = _mm512_set1_pd(1.);
2058 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2059 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2060 let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2061 assert_eq_m512d(r, c);
2062 let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2063 let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2064 assert_eq_m512d(r, e);
2065 }
2066
2067 #[simd_test(enable = "avx512f,avx512vl")]
2068 unsafe fn test_mm256_mask_fmsub_pd() {
2069 let a = _mm256_set1_pd(1.);
2070 let b = _mm256_set_pd(0., 1., 2., 3.);
2071 let c = _mm256_set1_pd(1.);
2072 let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2073 assert_eq_m256d(r, a);
2074 let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2075 let e = _mm256_set_pd(-1., 0., 1., 2.);
2076 assert_eq_m256d(r, e);
2077 }
2078
2079 #[simd_test(enable = "avx512f,avx512vl")]
2080 unsafe fn test_mm256_maskz_fmsub_pd() {
2081 let a = _mm256_set1_pd(1.);
2082 let b = _mm256_set_pd(0., 1., 2., 3.);
2083 let c = _mm256_set1_pd(1.);
2084 let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2085 assert_eq_m256d(r, _mm256_setzero_pd());
2086 let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2087 let e = _mm256_set_pd(-1., 0., 1., 2.);
2088 assert_eq_m256d(r, e);
2089 }
2090
2091 #[simd_test(enable = "avx512f,avx512vl")]
2092 unsafe fn test_mm256_mask3_fmsub_pd() {
2093 let a = _mm256_set1_pd(1.);
2094 let b = _mm256_set_pd(0., 1., 2., 3.);
2095 let c = _mm256_set1_pd(1.);
2096 let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2097 assert_eq_m256d(r, c);
2098 let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2099 let e = _mm256_set_pd(-1., 0., 1., 2.);
2100 assert_eq_m256d(r, e);
2101 }
2102
2103 #[simd_test(enable = "avx512f,avx512vl")]
2104 unsafe fn test_mm_mask_fmsub_pd() {
2105 let a = _mm_set1_pd(1.);
2106 let b = _mm_set_pd(0., 1.);
2107 let c = _mm_set1_pd(1.);
2108 let r = _mm_mask_fmsub_pd(a, 0, b, c);
2109 assert_eq_m128d(r, a);
2110 let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2111 let e = _mm_set_pd(-1., 0.);
2112 assert_eq_m128d(r, e);
2113 }
2114
2115 #[simd_test(enable = "avx512f,avx512vl")]
2116 unsafe fn test_mm_maskz_fmsub_pd() {
2117 let a = _mm_set1_pd(1.);
2118 let b = _mm_set_pd(0., 1.);
2119 let c = _mm_set1_pd(1.);
2120 let r = _mm_maskz_fmsub_pd(0, a, b, c);
2121 assert_eq_m128d(r, _mm_setzero_pd());
2122 let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2123 let e = _mm_set_pd(-1., 0.);
2124 assert_eq_m128d(r, e);
2125 }
2126
2127 #[simd_test(enable = "avx512f,avx512vl")]
2128 unsafe fn test_mm_mask3_fmsub_pd() {
2129 let a = _mm_set1_pd(1.);
2130 let b = _mm_set_pd(0., 1.);
2131 let c = _mm_set1_pd(1.);
2132 let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2133 assert_eq_m128d(r, c);
2134 let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2135 let e = _mm_set_pd(-1., 0.);
2136 assert_eq_m128d(r, e);
2137 }
2138
2139 #[simd_test(enable = "avx512f")]
2140 unsafe fn test_mm512_fmaddsub_pd() {
2141 let a = _mm512_set1_pd(1.);
2142 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2143 let c = _mm512_set1_pd(1.);
2144 let r = _mm512_fmaddsub_pd(a, b, c);
2145 let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2146 assert_eq_m512d(r, e);
2147 }
2148
2149 #[simd_test(enable = "avx512f")]
2150 unsafe fn test_mm512_mask_fmaddsub_pd() {
2151 let a = _mm512_set1_pd(1.);
2152 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2153 let c = _mm512_set1_pd(1.);
2154 let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2155 assert_eq_m512d(r, a);
2156 let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2157 let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2158 assert_eq_m512d(r, e);
2159 }
2160
2161 #[simd_test(enable = "avx512f")]
2162 unsafe fn test_mm512_maskz_fmaddsub_pd() {
2163 let a = _mm512_set1_pd(1.);
2164 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2165 let c = _mm512_set1_pd(1.);
2166 let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2167 assert_eq_m512d(r, _mm512_setzero_pd());
2168 let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2169 let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2170 assert_eq_m512d(r, e);
2171 }
2172
2173 #[simd_test(enable = "avx512f")]
2174 unsafe fn test_mm512_mask3_fmaddsub_pd() {
2175 let a = _mm512_set1_pd(1.);
2176 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2177 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2178 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2179 assert_eq_m512d(r, c);
2180 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2181 let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2182 assert_eq_m512d(r, e);
2183 }
2184
2185 #[simd_test(enable = "avx512f,avx512vl")]
2186 unsafe fn test_mm256_mask_fmaddsub_pd() {
2187 let a = _mm256_set1_pd(1.);
2188 let b = _mm256_set_pd(0., 1., 2., 3.);
2189 let c = _mm256_set1_pd(1.);
2190 let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2191 assert_eq_m256d(r, a);
2192 let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2193 let e = _mm256_set_pd(1., 0., 3., 2.);
2194 assert_eq_m256d(r, e);
2195 }
2196
2197 #[simd_test(enable = "avx512f,avx512vl")]
2198 unsafe fn test_mm256_maskz_fmaddsub_pd() {
2199 let a = _mm256_set1_pd(1.);
2200 let b = _mm256_set_pd(0., 1., 2., 3.);
2201 let c = _mm256_set1_pd(1.);
2202 let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2203 assert_eq_m256d(r, _mm256_setzero_pd());
2204 let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2205 let e = _mm256_set_pd(1., 0., 3., 2.);
2206 assert_eq_m256d(r, e);
2207 }
2208
2209 #[simd_test(enable = "avx512f,avx512vl")]
2210 unsafe fn test_mm256_mask3_fmaddsub_pd() {
2211 let a = _mm256_set1_pd(1.);
2212 let b = _mm256_set_pd(0., 1., 2., 3.);
2213 let c = _mm256_set1_pd(1.);
2214 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2215 assert_eq_m256d(r, c);
2216 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2217 let e = _mm256_set_pd(1., 0., 3., 2.);
2218 assert_eq_m256d(r, e);
2219 }
2220
2221 #[simd_test(enable = "avx512f,avx512vl")]
2222 unsafe fn test_mm_mask_fmaddsub_pd() {
2223 let a = _mm_set1_pd(1.);
2224 let b = _mm_set_pd(0., 1.);
2225 let c = _mm_set1_pd(1.);
2226 let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2227 assert_eq_m128d(r, a);
2228 let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2229 let e = _mm_set_pd(1., 0.);
2230 assert_eq_m128d(r, e);
2231 }
2232
2233 #[simd_test(enable = "avx512f,avx512vl")]
2234 unsafe fn test_mm_maskz_fmaddsub_pd() {
2235 let a = _mm_set1_pd(1.);
2236 let b = _mm_set_pd(0., 1.);
2237 let c = _mm_set1_pd(1.);
2238 let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2239 assert_eq_m128d(r, _mm_setzero_pd());
2240 let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2241 let e = _mm_set_pd(1., 0.);
2242 assert_eq_m128d(r, e);
2243 }
2244
2245 #[simd_test(enable = "avx512f,avx512vl")]
2246 unsafe fn test_mm_mask3_fmaddsub_pd() {
2247 let a = _mm_set1_pd(1.);
2248 let b = _mm_set_pd(0., 1.);
2249 let c = _mm_set1_pd(1.);
2250 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2251 assert_eq_m128d(r, c);
2252 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2253 let e = _mm_set_pd(1., 0.);
2254 assert_eq_m128d(r, e);
2255 }
2256
2257 #[simd_test(enable = "avx512f")]
2258 unsafe fn test_mm512_fmsubadd_pd() {
2259 let a = _mm512_set1_pd(1.);
2260 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2261 let c = _mm512_set1_pd(1.);
2262 let r = _mm512_fmsubadd_pd(a, b, c);
2263 let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2264 assert_eq_m512d(r, e);
2265 }
2266
2267 #[simd_test(enable = "avx512f")]
2268 unsafe fn test_mm512_mask_fmsubadd_pd() {
2269 let a = _mm512_set1_pd(1.);
2270 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2271 let c = _mm512_set1_pd(1.);
2272 let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2273 assert_eq_m512d(r, a);
2274 let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2275 let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2276 assert_eq_m512d(r, e);
2277 }
2278
2279 #[simd_test(enable = "avx512f")]
2280 unsafe fn test_mm512_maskz_fmsubadd_pd() {
2281 let a = _mm512_set1_pd(1.);
2282 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2283 let c = _mm512_set1_pd(1.);
2284 let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2285 assert_eq_m512d(r, _mm512_setzero_pd());
2286 let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2287 let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2288 assert_eq_m512d(r, e);
2289 }
2290
2291 #[simd_test(enable = "avx512f")]
2292 unsafe fn test_mm512_mask3_fmsubadd_pd() {
2293 let a = _mm512_set1_pd(1.);
2294 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2295 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2296 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2297 assert_eq_m512d(r, c);
2298 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2299 let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2300 assert_eq_m512d(r, e);
2301 }
2302
2303 #[simd_test(enable = "avx512f,avx512vl")]
2304 unsafe fn test_mm256_mask_fmsubadd_pd() {
2305 let a = _mm256_set1_pd(1.);
2306 let b = _mm256_set_pd(0., 1., 2., 3.);
2307 let c = _mm256_set1_pd(1.);
2308 let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2309 assert_eq_m256d(r, a);
2310 let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2311 let e = _mm256_set_pd(-1., 2., 1., 4.);
2312 assert_eq_m256d(r, e);
2313 }
2314
2315 #[simd_test(enable = "avx512f,avx512vl")]
2316 unsafe fn test_mm256_maskz_fmsubadd_pd() {
2317 let a = _mm256_set1_pd(1.);
2318 let b = _mm256_set_pd(0., 1., 2., 3.);
2319 let c = _mm256_set1_pd(1.);
2320 let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2321 assert_eq_m256d(r, _mm256_setzero_pd());
2322 let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2323 let e = _mm256_set_pd(-1., 2., 1., 4.);
2324 assert_eq_m256d(r, e);
2325 }
2326
2327 #[simd_test(enable = "avx512f,avx512vl")]
2328 unsafe fn test_mm256_mask3_fmsubadd_pd() {
2329 let a = _mm256_set1_pd(1.);
2330 let b = _mm256_set_pd(0., 1., 2., 3.);
2331 let c = _mm256_set1_pd(1.);
2332 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2333 assert_eq_m256d(r, c);
2334 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2335 let e = _mm256_set_pd(-1., 2., 1., 4.);
2336 assert_eq_m256d(r, e);
2337 }
2338
2339 #[simd_test(enable = "avx512f,avx512vl")]
2340 unsafe fn test_mm_mask_fmsubadd_pd() {
2341 let a = _mm_set1_pd(1.);
2342 let b = _mm_set_pd(0., 1.);
2343 let c = _mm_set1_pd(1.);
2344 let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2345 assert_eq_m128d(r, a);
2346 let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2347 let e = _mm_set_pd(-1., 2.);
2348 assert_eq_m128d(r, e);
2349 }
2350
2351 #[simd_test(enable = "avx512f,avx512vl")]
2352 unsafe fn test_mm_maskz_fmsubadd_pd() {
2353 let a = _mm_set1_pd(1.);
2354 let b = _mm_set_pd(0., 1.);
2355 let c = _mm_set1_pd(1.);
2356 let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2357 assert_eq_m128d(r, _mm_setzero_pd());
2358 let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2359 let e = _mm_set_pd(-1., 2.);
2360 assert_eq_m128d(r, e);
2361 }
2362
2363 #[simd_test(enable = "avx512f,avx512vl")]
2364 unsafe fn test_mm_mask3_fmsubadd_pd() {
2365 let a = _mm_set1_pd(1.);
2366 let b = _mm_set_pd(0., 1.);
2367 let c = _mm_set1_pd(1.);
2368 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2369 assert_eq_m128d(r, c);
2370 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2371 let e = _mm_set_pd(-1., 2.);
2372 assert_eq_m128d(r, e);
2373 }
2374
2375 #[simd_test(enable = "avx512f")]
2376 unsafe fn test_mm512_fnmadd_pd() {
2377 let a = _mm512_set1_pd(1.);
2378 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2379 let c = _mm512_set1_pd(1.);
2380 let r = _mm512_fnmadd_pd(a, b, c);
2381 let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2382 assert_eq_m512d(r, e);
2383 }
2384
2385 #[simd_test(enable = "avx512f")]
2386 unsafe fn test_mm512_mask_fnmadd_pd() {
2387 let a = _mm512_set1_pd(1.);
2388 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2389 let c = _mm512_set1_pd(1.);
2390 let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2391 assert_eq_m512d(r, a);
2392 let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2393 let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2394 assert_eq_m512d(r, e);
2395 }
2396
2397 #[simd_test(enable = "avx512f")]
2398 unsafe fn test_mm512_maskz_fnmadd_pd() {
2399 let a = _mm512_set1_pd(1.);
2400 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2401 let c = _mm512_set1_pd(1.);
2402 let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2403 assert_eq_m512d(r, _mm512_setzero_pd());
2404 let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2405 let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2406 assert_eq_m512d(r, e);
2407 }
2408
2409 #[simd_test(enable = "avx512f")]
2410 unsafe fn test_mm512_mask3_fnmadd_pd() {
2411 let a = _mm512_set1_pd(1.);
2412 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2413 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2414 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2415 assert_eq_m512d(r, c);
2416 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2417 let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2418 assert_eq_m512d(r, e);
2419 }
2420
2421 #[simd_test(enable = "avx512f,avx512vl")]
2422 unsafe fn test_mm256_mask_fnmadd_pd() {
2423 let a = _mm256_set1_pd(1.);
2424 let b = _mm256_set_pd(0., 1., 2., 3.);
2425 let c = _mm256_set1_pd(1.);
2426 let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2427 assert_eq_m256d(r, a);
2428 let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2429 let e = _mm256_set_pd(1., 0., -1., -2.);
2430 assert_eq_m256d(r, e);
2431 }
2432
2433 #[simd_test(enable = "avx512f,avx512vl")]
2434 unsafe fn test_mm256_maskz_fnmadd_pd() {
2435 let a = _mm256_set1_pd(1.);
2436 let b = _mm256_set_pd(0., 1., 2., 3.);
2437 let c = _mm256_set1_pd(1.);
2438 let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2439 assert_eq_m256d(r, _mm256_setzero_pd());
2440 let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2441 let e = _mm256_set_pd(1., 0., -1., -2.);
2442 assert_eq_m256d(r, e);
2443 }
2444
2445 #[simd_test(enable = "avx512f,avx512vl")]
2446 unsafe fn test_mm256_mask3_fnmadd_pd() {
2447 let a = _mm256_set1_pd(1.);
2448 let b = _mm256_set_pd(0., 1., 2., 3.);
2449 let c = _mm256_set1_pd(1.);
2450 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2451 assert_eq_m256d(r, c);
2452 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2453 let e = _mm256_set_pd(1., 0., -1., -2.);
2454 assert_eq_m256d(r, e);
2455 }
2456
2457 #[simd_test(enable = "avx512f,avx512vl")]
2458 unsafe fn test_mm_mask_fnmadd_pd() {
2459 let a = _mm_set1_pd(1.);
2460 let b = _mm_set_pd(0., 1.);
2461 let c = _mm_set1_pd(1.);
2462 let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2463 assert_eq_m128d(r, a);
2464 let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2465 let e = _mm_set_pd(1., 0.);
2466 assert_eq_m128d(r, e);
2467 }
2468
2469 #[simd_test(enable = "avx512f,avx512vl")]
2470 unsafe fn test_mm_maskz_fnmadd_pd() {
2471 let a = _mm_set1_pd(1.);
2472 let b = _mm_set_pd(0., 1.);
2473 let c = _mm_set1_pd(1.);
2474 let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2475 assert_eq_m128d(r, _mm_setzero_pd());
2476 let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2477 let e = _mm_set_pd(1., 0.);
2478 assert_eq_m128d(r, e);
2479 }
2480
2481 #[simd_test(enable = "avx512f,avx512vl")]
2482 unsafe fn test_mm_mask3_fnmadd_pd() {
2483 let a = _mm_set1_pd(1.);
2484 let b = _mm_set_pd(0., 1.);
2485 let c = _mm_set1_pd(1.);
2486 let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2487 assert_eq_m128d(r, c);
2488 let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2489 let e = _mm_set_pd(1., 0.);
2490 assert_eq_m128d(r, e);
2491 }
2492
2493 #[simd_test(enable = "avx512f")]
2494 unsafe fn test_mm512_fnmsub_pd() {
2495 let a = _mm512_set1_pd(1.);
2496 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2497 let c = _mm512_set1_pd(1.);
2498 let r = _mm512_fnmsub_pd(a, b, c);
2499 let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2500 assert_eq_m512d(r, e);
2501 }
2502
2503 #[simd_test(enable = "avx512f")]
2504 unsafe fn test_mm512_mask_fnmsub_pd() {
2505 let a = _mm512_set1_pd(1.);
2506 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2507 let c = _mm512_set1_pd(1.);
2508 let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2509 assert_eq_m512d(r, a);
2510 let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2511 let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2512 assert_eq_m512d(r, e);
2513 }
2514
2515 #[simd_test(enable = "avx512f")]
2516 unsafe fn test_mm512_maskz_fnmsub_pd() {
2517 let a = _mm512_set1_pd(1.);
2518 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2519 let c = _mm512_set1_pd(1.);
2520 let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2521 assert_eq_m512d(r, _mm512_setzero_pd());
2522 let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2523 let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2524 assert_eq_m512d(r, e);
2525 }
2526
2527 #[simd_test(enable = "avx512f")]
2528 unsafe fn test_mm512_mask3_fnmsub_pd() {
2529 let a = _mm512_set1_pd(1.);
2530 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2531 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2532 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2533 assert_eq_m512d(r, c);
2534 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2535 let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2536 assert_eq_m512d(r, e);
2537 }
2538
2539 #[simd_test(enable = "avx512f,avx512vl")]
2540 unsafe fn test_mm256_mask_fnmsub_pd() {
2541 let a = _mm256_set1_pd(1.);
2542 let b = _mm256_set_pd(0., 1., 2., 3.);
2543 let c = _mm256_set1_pd(1.);
2544 let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2545 assert_eq_m256d(r, a);
2546 let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2547 let e = _mm256_set_pd(-1., -2., -3., -4.);
2548 assert_eq_m256d(r, e);
2549 }
2550
2551 #[simd_test(enable = "avx512f,avx512vl")]
2552 unsafe fn test_mm256_maskz_fnmsub_pd() {
2553 let a = _mm256_set1_pd(1.);
2554 let b = _mm256_set_pd(0., 1., 2., 3.);
2555 let c = _mm256_set1_pd(1.);
2556 let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2557 assert_eq_m256d(r, _mm256_setzero_pd());
2558 let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2559 let e = _mm256_set_pd(-1., -2., -3., -4.);
2560 assert_eq_m256d(r, e);
2561 }
2562
2563 #[simd_test(enable = "avx512f,avx512vl")]
2564 unsafe fn test_mm256_mask3_fnmsub_pd() {
2565 let a = _mm256_set1_pd(1.);
2566 let b = _mm256_set_pd(0., 1., 2., 3.);
2567 let c = _mm256_set1_pd(1.);
2568 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2569 assert_eq_m256d(r, c);
2570 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2571 let e = _mm256_set_pd(-1., -2., -3., -4.);
2572 assert_eq_m256d(r, e);
2573 }
2574
2575 #[simd_test(enable = "avx512f,avx512vl")]
2576 unsafe fn test_mm_mask_fnmsub_pd() {
2577 let a = _mm_set1_pd(1.);
2578 let b = _mm_set_pd(0., 1.);
2579 let c = _mm_set1_pd(1.);
2580 let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2581 assert_eq_m128d(r, a);
2582 let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2583 let e = _mm_set_pd(-1., -2.);
2584 assert_eq_m128d(r, e);
2585 }
2586
2587 #[simd_test(enable = "avx512f,avx512vl")]
2588 unsafe fn test_mm_maskz_fnmsub_pd() {
2589 let a = _mm_set1_pd(1.);
2590 let b = _mm_set_pd(0., 1.);
2591 let c = _mm_set1_pd(1.);
2592 let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2593 assert_eq_m128d(r, _mm_setzero_pd());
2594 let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2595 let e = _mm_set_pd(-1., -2.);
2596 assert_eq_m128d(r, e);
2597 }
2598
2599 #[simd_test(enable = "avx512f,avx512vl")]
2600 unsafe fn test_mm_mask3_fnmsub_pd() {
2601 let a = _mm_set1_pd(1.);
2602 let b = _mm_set_pd(0., 1.);
2603 let c = _mm_set1_pd(1.);
2604 let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2605 assert_eq_m128d(r, c);
2606 let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2607 let e = _mm_set_pd(-1., -2.);
2608 assert_eq_m128d(r, e);
2609 }
2610
2611 #[simd_test(enable = "avx512f")]
2612 unsafe fn test_mm512_rcp14_pd() {
2613 let a = _mm512_set1_pd(3.);
2614 let r = _mm512_rcp14_pd(a);
2615 let e = _mm512_set1_pd(0.3333320617675781);
2616 assert_eq_m512d(r, e);
2617 }
2618
2619 #[simd_test(enable = "avx512f")]
2620 unsafe fn test_mm512_mask_rcp14_pd() {
2621 let a = _mm512_set1_pd(3.);
2622 let r = _mm512_mask_rcp14_pd(a, 0, a);
2623 assert_eq_m512d(r, a);
2624 let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2625 #[rustfmt::skip]
2626 let e = _mm512_setr_pd(
2627 3., 3., 3., 3.,
2628 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2629 );
2630 assert_eq_m512d(r, e);
2631 }
2632
2633 #[simd_test(enable = "avx512f")]
2634 unsafe fn test_mm512_maskz_rcp14_pd() {
2635 let a = _mm512_set1_pd(3.);
2636 let r = _mm512_maskz_rcp14_pd(0, a);
2637 assert_eq_m512d(r, _mm512_setzero_pd());
2638 let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2639 #[rustfmt::skip]
2640 let e = _mm512_setr_pd(
2641 0., 0., 0., 0.,
2642 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2643 );
2644 assert_eq_m512d(r, e);
2645 }
2646
2647 #[simd_test(enable = "avx512f,avx512vl")]
2648 unsafe fn test_mm256_rcp14_pd() {
2649 let a = _mm256_set1_pd(3.);
2650 let r = _mm256_rcp14_pd(a);
2651 let e = _mm256_set1_pd(0.3333320617675781);
2652 assert_eq_m256d(r, e);
2653 }
2654
2655 #[simd_test(enable = "avx512f,avx512vl")]
2656 unsafe fn test_mm256_mask_rcp14_pd() {
2657 let a = _mm256_set1_pd(3.);
2658 let r = _mm256_mask_rcp14_pd(a, 0, a);
2659 assert_eq_m256d(r, a);
2660 let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2661 let e = _mm256_set1_pd(0.3333320617675781);
2662 assert_eq_m256d(r, e);
2663 }
2664
2665 #[simd_test(enable = "avx512f,avx512vl")]
2666 unsafe fn test_mm256_maskz_rcp14_pd() {
2667 let a = _mm256_set1_pd(3.);
2668 let r = _mm256_maskz_rcp14_pd(0, a);
2669 assert_eq_m256d(r, _mm256_setzero_pd());
2670 let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2671 let e = _mm256_set1_pd(0.3333320617675781);
2672 assert_eq_m256d(r, e);
2673 }
2674
2675 #[simd_test(enable = "avx512f,avx512vl")]
2676 unsafe fn test_mm_rcp14_pd() {
2677 let a = _mm_set1_pd(3.);
2678 let r = _mm_rcp14_pd(a);
2679 let e = _mm_set1_pd(0.3333320617675781);
2680 assert_eq_m128d(r, e);
2681 }
2682
2683 #[simd_test(enable = "avx512f,avx512vl")]
2684 unsafe fn test_mm_mask_rcp14_pd() {
2685 let a = _mm_set1_pd(3.);
2686 let r = _mm_mask_rcp14_pd(a, 0, a);
2687 assert_eq_m128d(r, a);
2688 let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2689 let e = _mm_set1_pd(0.3333320617675781);
2690 assert_eq_m128d(r, e);
2691 }
2692
2693 #[simd_test(enable = "avx512f,avx512vl")]
2694 unsafe fn test_mm_maskz_rcp14_pd() {
2695 let a = _mm_set1_pd(3.);
2696 let r = _mm_maskz_rcp14_pd(0, a);
2697 assert_eq_m128d(r, _mm_setzero_pd());
2698 let r = _mm_maskz_rcp14_pd(0b00000011, a);
2699 let e = _mm_set1_pd(0.3333320617675781);
2700 assert_eq_m128d(r, e);
2701 }
2702
2703 #[simd_test(enable = "avx512f")]
2704 unsafe fn test_mm512_rsqrt14_pd() {
2705 let a = _mm512_set1_pd(3.);
2706 let r = _mm512_rsqrt14_pd(a);
2707 let e = _mm512_set1_pd(0.5773391723632813);
2708 assert_eq_m512d(r, e);
2709 }
2710
2711 #[simd_test(enable = "avx512f")]
2712 unsafe fn test_mm512_mask_rsqrt14_pd() {
2713 let a = _mm512_set1_pd(3.);
2714 let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2715 assert_eq_m512d(r, a);
2716 let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2717 #[rustfmt::skip]
2718 let e = _mm512_setr_pd(
2719 3., 3., 3., 3.,
2720 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2721 );
2722 assert_eq_m512d(r, e);
2723 }
2724
2725 #[simd_test(enable = "avx512f")]
2726 unsafe fn test_mm512_maskz_rsqrt14_pd() {
2727 let a = _mm512_set1_pd(3.);
2728 let r = _mm512_maskz_rsqrt14_pd(0, a);
2729 assert_eq_m512d(r, _mm512_setzero_pd());
2730 let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2731 #[rustfmt::skip]
2732 let e = _mm512_setr_pd(
2733 0., 0., 0., 0.,
2734 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2735 );
2736 assert_eq_m512d(r, e);
2737 }
2738
2739 #[simd_test(enable = "avx512f,avx512vl")]
2740 unsafe fn test_mm256_mask_rsqrt14_pd() {
2741 let a = _mm256_set1_pd(3.);
2742 let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2743 assert_eq_m256d(r, a);
2744 let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2745 let e = _mm256_set1_pd(0.5773391723632813);
2746 assert_eq_m256d(r, e);
2747 }
2748
2749 #[simd_test(enable = "avx512f,avx512vl")]
2750 unsafe fn test_mm256_maskz_rsqrt14_pd() {
2751 let a = _mm256_set1_pd(3.);
2752 let r = _mm256_maskz_rsqrt14_pd(0, a);
2753 assert_eq_m256d(r, _mm256_setzero_pd());
2754 let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2755 let e = _mm256_set1_pd(0.5773391723632813);
2756 assert_eq_m256d(r, e);
2757 }
2758
2759 #[simd_test(enable = "avx512f,avx512vl")]
2760 unsafe fn test_mm_mask_rsqrt14_pd() {
2761 let a = _mm_set1_pd(3.);
2762 let r = _mm_mask_rsqrt14_pd(a, 0, a);
2763 assert_eq_m128d(r, a);
2764 let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2765 let e = _mm_set1_pd(0.5773391723632813);
2766 assert_eq_m128d(r, e);
2767 }
2768
2769 #[simd_test(enable = "avx512f,avx512vl")]
2770 unsafe fn test_mm_maskz_rsqrt14_pd() {
2771 let a = _mm_set1_pd(3.);
2772 let r = _mm_maskz_rsqrt14_pd(0, a);
2773 assert_eq_m128d(r, _mm_setzero_pd());
2774 let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2775 let e = _mm_set1_pd(0.5773391723632813);
2776 assert_eq_m128d(r, e);
2777 }
2778
2779 #[simd_test(enable = "avx512f")]
2780 unsafe fn test_mm512_getexp_pd() {
2781 let a = _mm512_set1_pd(3.);
2782 let r = _mm512_getexp_pd(a);
2783 let e = _mm512_set1_pd(1.);
2784 assert_eq_m512d(r, e);
2785 }
2786
2787 #[simd_test(enable = "avx512f")]
2788 unsafe fn test_mm512_mask_getexp_pd() {
2789 let a = _mm512_set1_pd(3.);
2790 let r = _mm512_mask_getexp_pd(a, 0, a);
2791 assert_eq_m512d(r, a);
2792 let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2793 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2794 assert_eq_m512d(r, e);
2795 }
2796
2797 #[simd_test(enable = "avx512f")]
2798 unsafe fn test_mm512_maskz_getexp_pd() {
2799 let a = _mm512_set1_pd(3.);
2800 let r = _mm512_maskz_getexp_pd(0, a);
2801 assert_eq_m512d(r, _mm512_setzero_pd());
2802 let r = _mm512_maskz_getexp_pd(0b11110000, a);
2803 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2804 assert_eq_m512d(r, e);
2805 }
2806
2807 #[simd_test(enable = "avx512f,avx512vl")]
2808 unsafe fn test_mm256_getexp_pd() {
2809 let a = _mm256_set1_pd(3.);
2810 let r = _mm256_getexp_pd(a);
2811 let e = _mm256_set1_pd(1.);
2812 assert_eq_m256d(r, e);
2813 }
2814
2815 #[simd_test(enable = "avx512f,avx512vl")]
2816 unsafe fn test_mm256_mask_getexp_pd() {
2817 let a = _mm256_set1_pd(3.);
2818 let r = _mm256_mask_getexp_pd(a, 0, a);
2819 assert_eq_m256d(r, a);
2820 let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2821 let e = _mm256_set1_pd(1.);
2822 assert_eq_m256d(r, e);
2823 }
2824
2825 #[simd_test(enable = "avx512f,avx512vl")]
2826 unsafe fn test_mm256_maskz_getexp_pd() {
2827 let a = _mm256_set1_pd(3.);
2828 let r = _mm256_maskz_getexp_pd(0, a);
2829 assert_eq_m256d(r, _mm256_setzero_pd());
2830 let r = _mm256_maskz_getexp_pd(0b00001111, a);
2831 let e = _mm256_set1_pd(1.);
2832 assert_eq_m256d(r, e);
2833 }
2834
2835 #[simd_test(enable = "avx512f,avx512vl")]
2836 unsafe fn test_mm_getexp_pd() {
2837 let a = _mm_set1_pd(3.);
2838 let r = _mm_getexp_pd(a);
2839 let e = _mm_set1_pd(1.);
2840 assert_eq_m128d(r, e);
2841 }
2842
2843 #[simd_test(enable = "avx512f,avx512vl")]
2844 unsafe fn test_mm_mask_getexp_pd() {
2845 let a = _mm_set1_pd(3.);
2846 let r = _mm_mask_getexp_pd(a, 0, a);
2847 assert_eq_m128d(r, a);
2848 let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2849 let e = _mm_set1_pd(1.);
2850 assert_eq_m128d(r, e);
2851 }
2852
2853 #[simd_test(enable = "avx512f,avx512vl")]
2854 unsafe fn test_mm_maskz_getexp_pd() {
2855 let a = _mm_set1_pd(3.);
2856 let r = _mm_maskz_getexp_pd(0, a);
2857 assert_eq_m128d(r, _mm_setzero_pd());
2858 let r = _mm_maskz_getexp_pd(0b00000011, a);
2859 let e = _mm_set1_pd(1.);
2860 assert_eq_m128d(r, e);
2861 }
2862
2863 #[simd_test(enable = "avx512f")]
2864 unsafe fn test_mm512_roundscale_pd() {
2865 let a = _mm512_set1_pd(1.1);
2866 let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
2867 let e = _mm512_set1_pd(1.0);
2868 assert_eq_m512d(r, e);
2869 }
2870
2871 #[simd_test(enable = "avx512f")]
2872 unsafe fn test_mm512_mask_roundscale_pd() {
2873 let a = _mm512_set1_pd(1.1);
2874 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2875 let e = _mm512_set1_pd(1.1);
2876 assert_eq_m512d(r, e);
2877 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
2878 let e = _mm512_set1_pd(1.0);
2879 assert_eq_m512d(r, e);
2880 }
2881
2882 #[simd_test(enable = "avx512f")]
2883 unsafe fn test_mm512_maskz_roundscale_pd() {
2884 let a = _mm512_set1_pd(1.1);
2885 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2886 assert_eq_m512d(r, _mm512_setzero_pd());
2887 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
2888 let e = _mm512_set1_pd(1.0);
2889 assert_eq_m512d(r, e);
2890 }
2891
2892 #[simd_test(enable = "avx512f,avx512vl")]
2893 unsafe fn test_mm256_roundscale_pd() {
2894 let a = _mm256_set1_pd(1.1);
2895 let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
2896 let e = _mm256_set1_pd(1.0);
2897 assert_eq_m256d(r, e);
2898 }
2899
2900 #[simd_test(enable = "avx512f,avx512vl")]
2901 unsafe fn test_mm256_mask_roundscale_pd() {
2902 let a = _mm256_set1_pd(1.1);
2903 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2904 assert_eq_m256d(r, a);
2905 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
2906 let e = _mm256_set1_pd(1.0);
2907 assert_eq_m256d(r, e);
2908 }
2909
2910 #[simd_test(enable = "avx512f,avx512vl")]
2911 unsafe fn test_mm256_maskz_roundscale_pd() {
2912 let a = _mm256_set1_pd(1.1);
2913 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2914 assert_eq_m256d(r, _mm256_setzero_pd());
2915 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
2916 let e = _mm256_set1_pd(1.0);
2917 assert_eq_m256d(r, e);
2918 }
2919
2920 #[simd_test(enable = "avx512f,avx512vl")]
2921 unsafe fn test_mm_roundscale_pd() {
2922 let a = _mm_set1_pd(1.1);
2923 let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
2924 let e = _mm_set1_pd(1.0);
2925 assert_eq_m128d(r, e);
2926 }
2927
2928 #[simd_test(enable = "avx512f,avx512vl")]
2929 unsafe fn test_mm_mask_roundscale_pd() {
2930 let a = _mm_set1_pd(1.1);
2931 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2932 let e = _mm_set1_pd(1.1);
2933 assert_eq_m128d(r, e);
2934 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
2935 let e = _mm_set1_pd(1.0);
2936 assert_eq_m128d(r, e);
2937 }
2938
2939 #[simd_test(enable = "avx512f,avx512vl")]
2940 unsafe fn test_mm_maskz_roundscale_pd() {
2941 let a = _mm_set1_pd(1.1);
2942 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2943 assert_eq_m128d(r, _mm_setzero_pd());
2944 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
2945 let e = _mm_set1_pd(1.0);
2946 assert_eq_m128d(r, e);
2947 }
2948
2949 #[simd_test(enable = "avx512f")]
2950 unsafe fn test_mm512_scalef_pd() {
2951 let a = _mm512_set1_pd(1.);
2952 let b = _mm512_set1_pd(3.);
2953 let r = _mm512_scalef_pd(a, b);
2954 let e = _mm512_set1_pd(8.);
2955 assert_eq_m512d(r, e);
2956 }
2957
2958 #[simd_test(enable = "avx512f")]
2959 unsafe fn test_mm512_mask_scalef_pd() {
2960 let a = _mm512_set1_pd(1.);
2961 let b = _mm512_set1_pd(3.);
2962 let r = _mm512_mask_scalef_pd(a, 0, a, b);
2963 assert_eq_m512d(r, a);
2964 let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
2965 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
2966 assert_eq_m512d(r, e);
2967 }
2968
2969 #[simd_test(enable = "avx512f")]
2970 unsafe fn test_mm512_maskz_scalef_pd() {
2971 let a = _mm512_set1_pd(1.);
2972 let b = _mm512_set1_pd(3.);
2973 let r = _mm512_maskz_scalef_pd(0, a, b);
2974 assert_eq_m512d(r, _mm512_setzero_pd());
2975 let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
2976 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
2977 assert_eq_m512d(r, e);
2978 }
2979
2980 #[simd_test(enable = "avx512f,avx512vl")]
2981 unsafe fn test_mm256_scalef_pd() {
2982 let a = _mm256_set1_pd(1.);
2983 let b = _mm256_set1_pd(3.);
2984 let r = _mm256_scalef_pd(a, b);
2985 let e = _mm256_set1_pd(8.);
2986 assert_eq_m256d(r, e);
2987 }
2988
2989 #[simd_test(enable = "avx512f,avx512vl")]
2990 unsafe fn test_mm256_mask_scalef_pd() {
2991 let a = _mm256_set1_pd(1.);
2992 let b = _mm256_set1_pd(3.);
2993 let r = _mm256_mask_scalef_pd(a, 0, a, b);
2994 assert_eq_m256d(r, a);
2995 let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
2996 let e = _mm256_set1_pd(8.);
2997 assert_eq_m256d(r, e);
2998 }
2999
3000 #[simd_test(enable = "avx512f,avx512vl")]
3001 unsafe fn test_mm256_maskz_scalef_pd() {
3002 let a = _mm256_set1_pd(1.);
3003 let b = _mm256_set1_pd(3.);
3004 let r = _mm256_maskz_scalef_pd(0, a, b);
3005 assert_eq_m256d(r, _mm256_setzero_pd());
3006 let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3007 let e = _mm256_set1_pd(8.);
3008 assert_eq_m256d(r, e);
3009 }
3010
3011 #[simd_test(enable = "avx512f,avx512vl")]
3012 unsafe fn test_mm_scalef_pd() {
3013 let a = _mm_set1_pd(1.);
3014 let b = _mm_set1_pd(3.);
3015 let r = _mm_scalef_pd(a, b);
3016 let e = _mm_set1_pd(8.);
3017 assert_eq_m128d(r, e);
3018 }
3019
3020 #[simd_test(enable = "avx512f,avx512vl")]
3021 unsafe fn test_mm_mask_scalef_pd() {
3022 let a = _mm_set1_pd(1.);
3023 let b = _mm_set1_pd(3.);
3024 let r = _mm_mask_scalef_pd(a, 0, a, b);
3025 assert_eq_m128d(r, a);
3026 let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3027 let e = _mm_set1_pd(8.);
3028 assert_eq_m128d(r, e);
3029 }
3030
3031 #[simd_test(enable = "avx512f,avx512vl")]
3032 unsafe fn test_mm_maskz_scalef_pd() {
3033 let a = _mm_set1_pd(1.);
3034 let b = _mm_set1_pd(3.);
3035 let r = _mm_maskz_scalef_pd(0, a, b);
3036 assert_eq_m128d(r, _mm_setzero_pd());
3037 let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3038 let e = _mm_set1_pd(8.);
3039 assert_eq_m128d(r, e);
3040 }
3041
3042 #[simd_test(enable = "avx512f")]
3043 unsafe fn test_mm512_fixupimm_pd() {
3044 let a = _mm512_set1_pd(f64::NAN);
3045 let b = _mm512_set1_pd(f64::MAX);
3046 let c = _mm512_set1_epi64(i32::MAX as i64);
3047 let r = _mm512_fixupimm_pd::<5>(a, b, c);
3048 let e = _mm512_set1_pd(0.0);
3049 assert_eq_m512d(r, e);
3050 }
3051
3052 #[simd_test(enable = "avx512f")]
3053 unsafe fn test_mm512_mask_fixupimm_pd() {
3054 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3055 let b = _mm512_set1_pd(f64::MAX);
3056 let c = _mm512_set1_epi64(i32::MAX as i64);
3057 let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3058 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3059 assert_eq_m512d(r, e);
3060 }
3061
3062 #[simd_test(enable = "avx512f")]
3063 unsafe fn test_mm512_maskz_fixupimm_pd() {
3064 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3065 let b = _mm512_set1_pd(f64::MAX);
3066 let c = _mm512_set1_epi64(i32::MAX as i64);
3067 let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3068 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3069 assert_eq_m512d(r, e);
3070 }
3071
3072 #[simd_test(enable = "avx512f,avx512vl")]
3073 unsafe fn test_mm256_fixupimm_pd() {
3074 let a = _mm256_set1_pd(f64::NAN);
3075 let b = _mm256_set1_pd(f64::MAX);
3076 let c = _mm256_set1_epi64x(i32::MAX as i64);
3077 let r = _mm256_fixupimm_pd::<5>(a, b, c);
3078 let e = _mm256_set1_pd(0.0);
3079 assert_eq_m256d(r, e);
3080 }
3081
3082 #[simd_test(enable = "avx512f,avx512vl")]
3083 unsafe fn test_mm256_mask_fixupimm_pd() {
3084 let a = _mm256_set1_pd(f64::NAN);
3085 let b = _mm256_set1_pd(f64::MAX);
3086 let c = _mm256_set1_epi64x(i32::MAX as i64);
3087 let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3088 let e = _mm256_set1_pd(0.0);
3089 assert_eq_m256d(r, e);
3090 }
3091
3092 #[simd_test(enable = "avx512f,avx512vl")]
3093 unsafe fn test_mm256_maskz_fixupimm_pd() {
3094 let a = _mm256_set1_pd(f64::NAN);
3095 let b = _mm256_set1_pd(f64::MAX);
3096 let c = _mm256_set1_epi64x(i32::MAX as i64);
3097 let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3098 let e = _mm256_set1_pd(0.0);
3099 assert_eq_m256d(r, e);
3100 }
3101
3102 #[simd_test(enable = "avx512f,avx512vl")]
3103 unsafe fn test_mm_fixupimm_pd() {
3104 let a = _mm_set1_pd(f64::NAN);
3105 let b = _mm_set1_pd(f64::MAX);
3106 let c = _mm_set1_epi64x(i32::MAX as i64);
3107 let r = _mm_fixupimm_pd::<5>(a, b, c);
3108 let e = _mm_set1_pd(0.0);
3109 assert_eq_m128d(r, e);
3110 }
3111
3112 #[simd_test(enable = "avx512f,avx512vl")]
3113 unsafe fn test_mm_mask_fixupimm_pd() {
3114 let a = _mm_set1_pd(f64::NAN);
3115 let b = _mm_set1_pd(f64::MAX);
3116 let c = _mm_set1_epi64x(i32::MAX as i64);
3117 let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3118 let e = _mm_set1_pd(0.0);
3119 assert_eq_m128d(r, e);
3120 }
3121
3122 #[simd_test(enable = "avx512f,avx512vl")]
3123 unsafe fn test_mm_maskz_fixupimm_pd() {
3124 let a = _mm_set1_pd(f64::NAN);
3125 let b = _mm_set1_pd(f64::MAX);
3126 let c = _mm_set1_epi64x(i32::MAX as i64);
3127 let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3128 let e = _mm_set1_pd(0.0);
3129 assert_eq_m128d(r, e);
3130 }
3131
3132 #[simd_test(enable = "avx512f")]
3133 unsafe fn test_mm512_ternarylogic_epi64() {
3134 let a = _mm512_set1_epi64(1 << 2);
3135 let b = _mm512_set1_epi64(1 << 1);
3136 let c = _mm512_set1_epi64(1 << 0);
3137 let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3138 let e = _mm512_set1_epi64(0);
3139 assert_eq_m512i(r, e);
3140 }
3141
3142 #[simd_test(enable = "avx512f")]
3143 unsafe fn test_mm512_mask_ternarylogic_epi64() {
3144 let src = _mm512_set1_epi64(1 << 2);
3145 let a = _mm512_set1_epi64(1 << 1);
3146 let b = _mm512_set1_epi64(1 << 0);
3147 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3148 assert_eq_m512i(r, src);
3149 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3150 let e = _mm512_set1_epi64(0);
3151 assert_eq_m512i(r, e);
3152 }
3153
3154 #[simd_test(enable = "avx512f")]
3155 unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3156 let a = _mm512_set1_epi64(1 << 2);
3157 let b = _mm512_set1_epi64(1 << 1);
3158 let c = _mm512_set1_epi64(1 << 0);
3159 let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3160 assert_eq_m512i(r, _mm512_setzero_si512());
3161 let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3162 let e = _mm512_set1_epi64(0);
3163 assert_eq_m512i(r, e);
3164 }
3165
3166 #[simd_test(enable = "avx512f,avx512vl")]
3167 unsafe fn test_mm256_ternarylogic_epi64() {
3168 let a = _mm256_set1_epi64x(1 << 2);
3169 let b = _mm256_set1_epi64x(1 << 1);
3170 let c = _mm256_set1_epi64x(1 << 0);
3171 let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3172 let e = _mm256_set1_epi64x(0);
3173 assert_eq_m256i(r, e);
3174 }
3175
3176 #[simd_test(enable = "avx512f,avx512vl")]
3177 unsafe fn test_mm256_mask_ternarylogic_epi64() {
3178 let src = _mm256_set1_epi64x(1 << 2);
3179 let a = _mm256_set1_epi64x(1 << 1);
3180 let b = _mm256_set1_epi64x(1 << 0);
3181 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3182 assert_eq_m256i(r, src);
3183 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3184 let e = _mm256_set1_epi64x(0);
3185 assert_eq_m256i(r, e);
3186 }
3187
3188 #[simd_test(enable = "avx512f,avx512vl")]
3189 unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3190 let a = _mm256_set1_epi64x(1 << 2);
3191 let b = _mm256_set1_epi64x(1 << 1);
3192 let c = _mm256_set1_epi64x(1 << 0);
3193 let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3194 assert_eq_m256i(r, _mm256_setzero_si256());
3195 let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3196 let e = _mm256_set1_epi64x(0);
3197 assert_eq_m256i(r, e);
3198 }
3199
3200 #[simd_test(enable = "avx512f,avx512vl")]
3201 unsafe fn test_mm_ternarylogic_epi64() {
3202 let a = _mm_set1_epi64x(1 << 2);
3203 let b = _mm_set1_epi64x(1 << 1);
3204 let c = _mm_set1_epi64x(1 << 0);
3205 let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3206 let e = _mm_set1_epi64x(0);
3207 assert_eq_m128i(r, e);
3208 }
3209
3210 #[simd_test(enable = "avx512f,avx512vl")]
3211 unsafe fn test_mm_mask_ternarylogic_epi64() {
3212 let src = _mm_set1_epi64x(1 << 2);
3213 let a = _mm_set1_epi64x(1 << 1);
3214 let b = _mm_set1_epi64x(1 << 0);
3215 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3216 assert_eq_m128i(r, src);
3217 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3218 let e = _mm_set1_epi64x(0);
3219 assert_eq_m128i(r, e);
3220 }
3221
3222 #[simd_test(enable = "avx512f,avx512vl")]
3223 unsafe fn test_mm_maskz_ternarylogic_epi64() {
3224 let a = _mm_set1_epi64x(1 << 2);
3225 let b = _mm_set1_epi64x(1 << 1);
3226 let c = _mm_set1_epi64x(1 << 0);
3227 let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3228 assert_eq_m128i(r, _mm_setzero_si128());
3229 let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3230 let e = _mm_set1_epi64x(0);
3231 assert_eq_m128i(r, e);
3232 }
3233
3234 #[simd_test(enable = "avx512f")]
3235 unsafe fn test_mm512_getmant_pd() {
3236 let a = _mm512_set1_pd(10.);
3237 let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3238 let e = _mm512_set1_pd(1.25);
3239 assert_eq_m512d(r, e);
3240 }
3241
3242 #[simd_test(enable = "avx512f")]
3243 unsafe fn test_mm512_mask_getmant_pd() {
3244 let a = _mm512_set1_pd(10.);
3245 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3246 assert_eq_m512d(r, a);
3247 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3248 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3249 assert_eq_m512d(r, e);
3250 }
3251
3252 #[simd_test(enable = "avx512f")]
3253 unsafe fn test_mm512_maskz_getmant_pd() {
3254 let a = _mm512_set1_pd(10.);
3255 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3256 assert_eq_m512d(r, _mm512_setzero_pd());
3257 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3258 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3259 assert_eq_m512d(r, e);
3260 }
3261
3262 #[simd_test(enable = "avx512f,avx512vl")]
3263 unsafe fn test_mm256_getmant_pd() {
3264 let a = _mm256_set1_pd(10.);
3265 let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3266 let e = _mm256_set1_pd(1.25);
3267 assert_eq_m256d(r, e);
3268 }
3269
3270 #[simd_test(enable = "avx512f,avx512vl")]
3271 unsafe fn test_mm256_mask_getmant_pd() {
3272 let a = _mm256_set1_pd(10.);
3273 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3274 assert_eq_m256d(r, a);
3275 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3276 let e = _mm256_set1_pd(1.25);
3277 assert_eq_m256d(r, e);
3278 }
3279
3280 #[simd_test(enable = "avx512f,avx512vl")]
3281 unsafe fn test_mm256_maskz_getmant_pd() {
3282 let a = _mm256_set1_pd(10.);
3283 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3284 assert_eq_m256d(r, _mm256_setzero_pd());
3285 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3286 let e = _mm256_set1_pd(1.25);
3287 assert_eq_m256d(r, e);
3288 }
3289
3290 #[simd_test(enable = "avx512f,avx512vl")]
3291 unsafe fn test_mm_getmant_pd() {
3292 let a = _mm_set1_pd(10.);
3293 let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3294 let e = _mm_set1_pd(1.25);
3295 assert_eq_m128d(r, e);
3296 }
3297
3298 #[simd_test(enable = "avx512f,avx512vl")]
3299 unsafe fn test_mm_mask_getmant_pd() {
3300 let a = _mm_set1_pd(10.);
3301 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3302 assert_eq_m128d(r, a);
3303 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3304 let e = _mm_set1_pd(1.25);
3305 assert_eq_m128d(r, e);
3306 }
3307
3308 #[simd_test(enable = "avx512f,avx512vl")]
3309 unsafe fn test_mm_maskz_getmant_pd() {
3310 let a = _mm_set1_pd(10.);
3311 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3312 assert_eq_m128d(r, _mm_setzero_pd());
3313 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3314 let e = _mm_set1_pd(1.25);
3315 assert_eq_m128d(r, e);
3316 }
3317
3318 #[simd_test(enable = "avx512f")]
3319 unsafe fn test_mm512_cvtps_pd() {
3320 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3321 let r = _mm512_cvtps_pd(a);
3322 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3323 assert_eq_m512d(r, e);
3324 }
3325
3326 #[simd_test(enable = "avx512f")]
3327 unsafe fn test_mm512_mask_cvtps_pd() {
3328 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3329 let src = _mm512_set1_pd(0.);
3330 let r = _mm512_mask_cvtps_pd(src, 0, a);
3331 assert_eq_m512d(r, src);
3332 let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3333 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3334 assert_eq_m512d(r, e);
3335 }
3336
3337 #[simd_test(enable = "avx512f")]
3338 unsafe fn test_mm512_maskz_cvtps_pd() {
3339 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3340 let r = _mm512_maskz_cvtps_pd(0, a);
3341 assert_eq_m512d(r, _mm512_setzero_pd());
3342 let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3343 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3344 assert_eq_m512d(r, e);
3345 }
3346
3347 #[simd_test(enable = "avx512f")]
3348 unsafe fn test_mm512_cvtpslo_pd() {
3349 let v2 = _mm512_setr_ps(
3350 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3351 );
3352 let r = _mm512_cvtpslo_pd(v2);
3353 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3354 assert_eq_m512d(r, e);
3355 }
3356
3357 #[simd_test(enable = "avx512f")]
3358 unsafe fn test_mm512_mask_cvtpslo_pd() {
3359 let v2 = _mm512_setr_ps(
3360 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3361 );
3362 let src = _mm512_set1_pd(0.);
3363 let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3364 assert_eq_m512d(r, src);
3365 let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3366 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3367 assert_eq_m512d(r, e);
3368 }
3369
3370 #[simd_test(enable = "avx512f")]
3371 unsafe fn test_mm512_cvtpd_ps() {
3372 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3373 let r = _mm512_cvtpd_ps(a);
3374 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3375 assert_eq_m256(r, e);
3376 }
3377
3378 #[simd_test(enable = "avx512f")]
3379 unsafe fn test_mm512_mask_cvtpd_ps() {
3380 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3381 let src = _mm256_set1_ps(0.);
3382 let r = _mm512_mask_cvtpd_ps(src, 0, a);
3383 assert_eq_m256(r, src);
3384 let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3385 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3386 assert_eq_m256(r, e);
3387 }
3388
3389 #[simd_test(enable = "avx512f")]
3390 unsafe fn test_mm512_maskz_cvtpd_ps() {
3391 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3392 let r = _mm512_maskz_cvtpd_ps(0, a);
3393 assert_eq_m256(r, _mm256_setzero_ps());
3394 let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3395 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3396 assert_eq_m256(r, e);
3397 }
3398
3399 #[simd_test(enable = "avx512f,avx512vl")]
3400 unsafe fn test_mm256_mask_cvtpd_ps() {
3401 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3402 let src = _mm_set1_ps(0.);
3403 let r = _mm256_mask_cvtpd_ps(src, 0, a);
3404 assert_eq_m128(r, src);
3405 let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3406 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3407 assert_eq_m128(r, e);
3408 }
3409
3410 #[simd_test(enable = "avx512f,avx512vl")]
3411 unsafe fn test_mm256_maskz_cvtpd_ps() {
3412 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3413 let r = _mm256_maskz_cvtpd_ps(0, a);
3414 assert_eq_m128(r, _mm_setzero_ps());
3415 let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3416 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3417 assert_eq_m128(r, e);
3418 }
3419
3420 #[simd_test(enable = "avx512f,avx512vl")]
3421 unsafe fn test_mm_mask_cvtpd_ps() {
3422 let a = _mm_set_pd(6., -7.5);
3423 let src = _mm_set1_ps(0.);
3424 let r = _mm_mask_cvtpd_ps(src, 0, a);
3425 assert_eq_m128(r, src);
3426 let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3427 let e = _mm_set_ps(0., 0., 6., -7.5);
3428 assert_eq_m128(r, e);
3429 }
3430
3431 #[simd_test(enable = "avx512f,avx512vl")]
3432 unsafe fn test_mm_maskz_cvtpd_ps() {
3433 let a = _mm_set_pd(6., -7.5);
3434 let r = _mm_maskz_cvtpd_ps(0, a);
3435 assert_eq_m128(r, _mm_setzero_ps());
3436 let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3437 let e = _mm_set_ps(0., 0., 6., -7.5);
3438 assert_eq_m128(r, e);
3439 }
3440
3441 #[simd_test(enable = "avx512f")]
3442 unsafe fn test_mm512_cvtpd_epi32() {
3443 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3444 let r = _mm512_cvtpd_epi32(a);
3445 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3446 assert_eq_m256i(r, e);
3447 }
3448
3449 #[simd_test(enable = "avx512f")]
3450 unsafe fn test_mm512_mask_cvtpd_epi32() {
3451 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3452 let src = _mm256_set1_epi32(0);
3453 let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3454 assert_eq_m256i(r, src);
3455 let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3456 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3457 assert_eq_m256i(r, e);
3458 }
3459
3460 #[simd_test(enable = "avx512f")]
3461 unsafe fn test_mm512_maskz_cvtpd_epi32() {
3462 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3463 let r = _mm512_maskz_cvtpd_epi32(0, a);
3464 assert_eq_m256i(r, _mm256_setzero_si256());
3465 let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3466 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3467 assert_eq_m256i(r, e);
3468 }
3469
3470 #[simd_test(enable = "avx512f,avx512vl")]
3471 unsafe fn test_mm256_mask_cvtpd_epi32() {
3472 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3473 let src = _mm_set1_epi32(0);
3474 let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3475 assert_eq_m128i(r, src);
3476 let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3477 let e = _mm_set_epi32(4, -6, 6, -8);
3478 assert_eq_m128i(r, e);
3479 }
3480
3481 #[simd_test(enable = "avx512f,avx512vl")]
3482 unsafe fn test_mm256_maskz_cvtpd_epi32() {
3483 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3484 let r = _mm256_maskz_cvtpd_epi32(0, a);
3485 assert_eq_m128i(r, _mm_setzero_si128());
3486 let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3487 let e = _mm_set_epi32(4, -6, 6, -8);
3488 assert_eq_m128i(r, e);
3489 }
3490
3491 #[simd_test(enable = "avx512f,avx512vl")]
3492 unsafe fn test_mm_mask_cvtpd_epi32() {
3493 let a = _mm_set_pd(6., -7.5);
3494 let src = _mm_set1_epi32(0);
3495 let r = _mm_mask_cvtpd_epi32(src, 0, a);
3496 assert_eq_m128i(r, src);
3497 let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3498 let e = _mm_set_epi32(0, 0, 6, -8);
3499 assert_eq_m128i(r, e);
3500 }
3501
3502 #[simd_test(enable = "avx512f,avx512vl")]
3503 unsafe fn test_mm_maskz_cvtpd_epi32() {
3504 let a = _mm_set_pd(6., -7.5);
3505 let r = _mm_maskz_cvtpd_epi32(0, a);
3506 assert_eq_m128i(r, _mm_setzero_si128());
3507 let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3508 let e = _mm_set_epi32(0, 0, 6, -8);
3509 assert_eq_m128i(r, e);
3510 }
3511
3512 #[simd_test(enable = "avx512f")]
3513 unsafe fn test_mm512_cvtpd_epu32() {
3514 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3515 let r = _mm512_cvtpd_epu32(a);
3516 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3517 assert_eq_m256i(r, e);
3518 }
3519
3520 #[simd_test(enable = "avx512f")]
3521 unsafe fn test_mm512_mask_cvtpd_epu32() {
3522 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3523 let src = _mm256_set1_epi32(0);
3524 let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3525 assert_eq_m256i(r, src);
3526 let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3527 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3528 assert_eq_m256i(r, e);
3529 }
3530
3531 #[simd_test(enable = "avx512f")]
3532 unsafe fn test_mm512_maskz_cvtpd_epu32() {
3533 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3534 let r = _mm512_maskz_cvtpd_epu32(0, a);
3535 assert_eq_m256i(r, _mm256_setzero_si256());
3536 let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3537 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3538 assert_eq_m256i(r, e);
3539 }
3540
3541 #[simd_test(enable = "avx512f,avx512vl")]
3542 unsafe fn test_mm256_cvtpd_epu32() {
3543 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3544 let r = _mm256_cvtpd_epu32(a);
3545 let e = _mm_set_epi32(4, 6, 6, 8);
3546 assert_eq_m128i(r, e);
3547 }
3548
3549 #[simd_test(enable = "avx512f,avx512vl")]
3550 unsafe fn test_mm256_mask_cvtpd_epu32() {
3551 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3552 let src = _mm_set1_epi32(0);
3553 let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3554 assert_eq_m128i(r, src);
3555 let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3556 let e = _mm_set_epi32(4, 6, 6, 8);
3557 assert_eq_m128i(r, e);
3558 }
3559
3560 #[simd_test(enable = "avx512f,avx512vl")]
3561 unsafe fn test_mm256_maskz_cvtpd_epu32() {
3562 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3563 let r = _mm256_maskz_cvtpd_epu32(0, a);
3564 assert_eq_m128i(r, _mm_setzero_si128());
3565 let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3566 let e = _mm_set_epi32(4, 6, 6, 8);
3567 assert_eq_m128i(r, e);
3568 }
3569
3570 #[simd_test(enable = "avx512f,avx512vl")]
3571 unsafe fn test_mm_cvtpd_epu32() {
3572 let a = _mm_set_pd(6., 7.5);
3573 let r = _mm_cvtpd_epu32(a);
3574 let e = _mm_set_epi32(0, 0, 6, 8);
3575 assert_eq_m128i(r, e);
3576 }
3577
3578 #[simd_test(enable = "avx512f,avx512vl")]
3579 unsafe fn test_mm_mask_cvtpd_epu32() {
3580 let a = _mm_set_pd(6., 7.5);
3581 let src = _mm_set1_epi32(0);
3582 let r = _mm_mask_cvtpd_epu32(src, 0, a);
3583 assert_eq_m128i(r, src);
3584 let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3585 let e = _mm_set_epi32(0, 0, 6, 8);
3586 assert_eq_m128i(r, e);
3587 }
3588
3589 #[simd_test(enable = "avx512f,avx512vl")]
3590 unsafe fn test_mm_maskz_cvtpd_epu32() {
3591 let a = _mm_set_pd(6., 7.5);
3592 let r = _mm_maskz_cvtpd_epu32(0, a);
3593 assert_eq_m128i(r, _mm_setzero_si128());
3594 let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3595 let e = _mm_set_epi32(0, 0, 6, 8);
3596 assert_eq_m128i(r, e);
3597 }
3598
3599 #[simd_test(enable = "avx512f")]
3600 unsafe fn test_mm512_cvtpd_pslo() {
3601 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3602 let r = _mm512_cvtpd_pslo(v2);
3603 let e = _mm512_setr_ps(
3604 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3605 );
3606 assert_eq_m512(r, e);
3607 }
3608
3609 #[simd_test(enable = "avx512f")]
3610 unsafe fn test_mm512_mask_cvtpd_pslo() {
3611 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3612 let src = _mm512_set1_ps(0.);
3613 let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3614 assert_eq_m512(r, src);
3615 let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3616 let e = _mm512_setr_ps(
3617 0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3618 );
3619 assert_eq_m512(r, e);
3620 }
3621
3622 #[simd_test(enable = "avx512f")]
3623 unsafe fn test_mm512_cvtepi8_epi64() {
3624 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3625 let r = _mm512_cvtepi8_epi64(a);
3626 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3627 assert_eq_m512i(r, e);
3628 }
3629
3630 #[simd_test(enable = "avx512f")]
3631 unsafe fn test_mm512_mask_cvtepi8_epi64() {
3632 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3633 let src = _mm512_set1_epi64(-1);
3634 let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3635 assert_eq_m512i(r, src);
3636 let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3637 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3638 assert_eq_m512i(r, e);
3639 }
3640
3641 #[simd_test(enable = "avx512f")]
3642 unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3643 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3644 let r = _mm512_maskz_cvtepi8_epi64(0, a);
3645 assert_eq_m512i(r, _mm512_setzero_si512());
3646 let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3647 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3648 assert_eq_m512i(r, e);
3649 }
3650
3651 #[simd_test(enable = "avx512f,avx512vl")]
3652 unsafe fn test_mm256_mask_cvtepi8_epi64() {
3653 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3654 let src = _mm256_set1_epi64x(-1);
3655 let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3656 assert_eq_m256i(r, src);
3657 let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3658 let e = _mm256_set_epi64x(12, 13, 14, 15);
3659 assert_eq_m256i(r, e);
3660 }
3661
3662 #[simd_test(enable = "avx512f,avx512vl")]
3663 unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3664 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3665 let r = _mm256_maskz_cvtepi8_epi64(0, a);
3666 assert_eq_m256i(r, _mm256_setzero_si256());
3667 let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3668 let e = _mm256_set_epi64x(12, 13, 14, 15);
3669 assert_eq_m256i(r, e);
3670 }
3671
3672 #[simd_test(enable = "avx512f,avx512vl")]
3673 unsafe fn test_mm_mask_cvtepi8_epi64() {
3674 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3675 let src = _mm_set1_epi64x(-1);
3676 let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3677 assert_eq_m128i(r, src);
3678 let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3679 let e = _mm_set_epi64x(14, 15);
3680 assert_eq_m128i(r, e);
3681 }
3682
3683 #[simd_test(enable = "avx512f,avx512vl")]
3684 unsafe fn test_mm_maskz_cvtepi8_epi64() {
3685 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3686 let r = _mm_maskz_cvtepi8_epi64(0, a);
3687 assert_eq_m128i(r, _mm_setzero_si128());
3688 let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3689 let e = _mm_set_epi64x(14, 15);
3690 assert_eq_m128i(r, e);
3691 }
3692
3693 #[simd_test(enable = "avx512f")]
3694 unsafe fn test_mm512_cvtepu8_epi64() {
3695 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3696 let r = _mm512_cvtepu8_epi64(a);
3697 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3698 assert_eq_m512i(r, e);
3699 }
3700
3701 #[simd_test(enable = "avx512f")]
3702 unsafe fn test_mm512_mask_cvtepu8_epi64() {
3703 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3704 let src = _mm512_set1_epi64(-1);
3705 let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3706 assert_eq_m512i(r, src);
3707 let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3708 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3709 assert_eq_m512i(r, e);
3710 }
3711
3712 #[simd_test(enable = "avx512f")]
3713 unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3714 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3715 let r = _mm512_maskz_cvtepu8_epi64(0, a);
3716 assert_eq_m512i(r, _mm512_setzero_si512());
3717 let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3718 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3719 assert_eq_m512i(r, e);
3720 }
3721
3722 #[simd_test(enable = "avx512f,avx512vl")]
3723 unsafe fn test_mm256_mask_cvtepu8_epi64() {
3724 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3725 let src = _mm256_set1_epi64x(-1);
3726 let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3727 assert_eq_m256i(r, src);
3728 let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3729 let e = _mm256_set_epi64x(12, 13, 14, 15);
3730 assert_eq_m256i(r, e);
3731 }
3732
3733 #[simd_test(enable = "avx512f,avx512vl")]
3734 unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3735 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3736 let r = _mm256_maskz_cvtepu8_epi64(0, a);
3737 assert_eq_m256i(r, _mm256_setzero_si256());
3738 let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3739 let e = _mm256_set_epi64x(12, 13, 14, 15);
3740 assert_eq_m256i(r, e);
3741 }
3742
3743 #[simd_test(enable = "avx512f,avx512vl")]
3744 unsafe fn test_mm_mask_cvtepu8_epi64() {
3745 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3746 let src = _mm_set1_epi64x(-1);
3747 let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3748 assert_eq_m128i(r, src);
3749 let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3750 let e = _mm_set_epi64x(14, 15);
3751 assert_eq_m128i(r, e);
3752 }
3753
3754 #[simd_test(enable = "avx512f,avx512vl")]
3755 unsafe fn test_mm_maskz_cvtepu8_epi64() {
3756 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3757 let r = _mm_maskz_cvtepu8_epi64(0, a);
3758 assert_eq_m128i(r, _mm_setzero_si128());
3759 let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3760 let e = _mm_set_epi64x(14, 15);
3761 assert_eq_m128i(r, e);
3762 }
3763
3764 #[simd_test(enable = "avx512f")]
3765 unsafe fn test_mm512_cvtepi16_epi64() {
3766 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3767 let r = _mm512_cvtepi16_epi64(a);
3768 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3769 assert_eq_m512i(r, e);
3770 }
3771
3772 #[simd_test(enable = "avx512f")]
3773 unsafe fn test_mm512_mask_cvtepi16_epi64() {
3774 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3775 let src = _mm512_set1_epi64(-1);
3776 let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3777 assert_eq_m512i(r, src);
3778 let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3779 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3780 assert_eq_m512i(r, e);
3781 }
3782
3783 #[simd_test(enable = "avx512f")]
3784 unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3785 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3786 let r = _mm512_maskz_cvtepi16_epi64(0, a);
3787 assert_eq_m512i(r, _mm512_setzero_si512());
3788 let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3789 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3790 assert_eq_m512i(r, e);
3791 }
3792
3793 #[simd_test(enable = "avx512f,avx512vl")]
3794 unsafe fn test_mm256_mask_cvtepi16_epi64() {
3795 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3796 let src = _mm256_set1_epi64x(-1);
3797 let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3798 assert_eq_m256i(r, src);
3799 let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3800 let e = _mm256_set_epi64x(12, 13, 14, 15);
3801 assert_eq_m256i(r, e);
3802 }
3803
3804 #[simd_test(enable = "avx512f,avx512vl")]
3805 unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3806 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3807 let r = _mm256_maskz_cvtepi16_epi64(0, a);
3808 assert_eq_m256i(r, _mm256_setzero_si256());
3809 let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3810 let e = _mm256_set_epi64x(12, 13, 14, 15);
3811 assert_eq_m256i(r, e);
3812 }
3813
3814 #[simd_test(enable = "avx512f,avx512vl")]
3815 unsafe fn test_mm_mask_cvtepi16_epi64() {
3816 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3817 let src = _mm_set1_epi64x(-1);
3818 let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3819 assert_eq_m128i(r, src);
3820 let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3821 let e = _mm_set_epi64x(14, 15);
3822 assert_eq_m128i(r, e);
3823 }
3824
3825 #[simd_test(enable = "avx512f,avx512vl")]
3826 unsafe fn test_mm_maskz_cvtepi16_epi64() {
3827 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3828 let r = _mm_maskz_cvtepi16_epi64(0, a);
3829 assert_eq_m128i(r, _mm_setzero_si128());
3830 let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3831 let e = _mm_set_epi64x(14, 15);
3832 assert_eq_m128i(r, e);
3833 }
3834
3835 #[simd_test(enable = "avx512f")]
3836 unsafe fn test_mm512_cvtepu16_epi64() {
3837 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3838 let r = _mm512_cvtepu16_epi64(a);
3839 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3840 assert_eq_m512i(r, e);
3841 }
3842
3843 #[simd_test(enable = "avx512f")]
3844 unsafe fn test_mm512_mask_cvtepu16_epi64() {
3845 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3846 let src = _mm512_set1_epi64(-1);
3847 let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3848 assert_eq_m512i(r, src);
3849 let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3850 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3851 assert_eq_m512i(r, e);
3852 }
3853
3854 #[simd_test(enable = "avx512f")]
3855 unsafe fn test_mm512_maskz_cvtepu16_epi64() {
3856 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3857 let r = _mm512_maskz_cvtepu16_epi64(0, a);
3858 assert_eq_m512i(r, _mm512_setzero_si512());
3859 let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
3860 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3861 assert_eq_m512i(r, e);
3862 }
3863
3864 #[simd_test(enable = "avx512f,avx512vl")]
3865 unsafe fn test_mm256_mask_cvtepu16_epi64() {
3866 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3867 let src = _mm256_set1_epi64x(-1);
3868 let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
3869 assert_eq_m256i(r, src);
3870 let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
3871 let e = _mm256_set_epi64x(12, 13, 14, 15);
3872 assert_eq_m256i(r, e);
3873 }
3874
3875 #[simd_test(enable = "avx512f,avx512vl")]
3876 unsafe fn test_mm256_maskz_cvtepu16_epi64() {
3877 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3878 let r = _mm256_maskz_cvtepu16_epi64(0, a);
3879 assert_eq_m256i(r, _mm256_setzero_si256());
3880 let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
3881 let e = _mm256_set_epi64x(12, 13, 14, 15);
3882 assert_eq_m256i(r, e);
3883 }
3884
3885 #[simd_test(enable = "avx512f,avx512vl")]
3886 unsafe fn test_mm_mask_cvtepu16_epi64() {
3887 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3888 let src = _mm_set1_epi64x(-1);
3889 let r = _mm_mask_cvtepu16_epi64(src, 0, a);
3890 assert_eq_m128i(r, src);
3891 let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
3892 let e = _mm_set_epi64x(14, 15);
3893 assert_eq_m128i(r, e);
3894 }
3895
3896 #[simd_test(enable = "avx512f,avx512vl")]
3897 unsafe fn test_mm_maskz_cvtepu16_epi64() {
3898 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3899 let r = _mm_maskz_cvtepu16_epi64(0, a);
3900 assert_eq_m128i(r, _mm_setzero_si128());
3901 let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
3902 let e = _mm_set_epi64x(14, 15);
3903 assert_eq_m128i(r, e);
3904 }
3905
3906 #[simd_test(enable = "avx512f")]
3907 unsafe fn test_mm512_cvtepi32_epi64() {
3908 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3909 let r = _mm512_cvtepi32_epi64(a);
3910 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3911 assert_eq_m512i(r, e);
3912 }
3913
3914 #[simd_test(enable = "avx512f")]
3915 unsafe fn test_mm512_mask_cvtepi32_epi64() {
3916 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3917 let src = _mm512_set1_epi64(-1);
3918 let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
3919 assert_eq_m512i(r, src);
3920 let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
3921 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3922 assert_eq_m512i(r, e);
3923 }
3924
3925 #[simd_test(enable = "avx512f")]
3926 unsafe fn test_mm512_maskz_cvtepi32_epi64() {
3927 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3928 let r = _mm512_maskz_cvtepi32_epi64(0, a);
3929 assert_eq_m512i(r, _mm512_setzero_si512());
3930 let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
3931 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3932 assert_eq_m512i(r, e);
3933 }
3934
3935 #[simd_test(enable = "avx512f,avx512vl")]
3936 unsafe fn test_mm256_mask_cvtepi32_epi64() {
3937 let a = _mm_set_epi32(8, 9, 10, 11);
3938 let src = _mm256_set1_epi64x(-1);
3939 let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
3940 assert_eq_m256i(r, src);
3941 let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
3942 let e = _mm256_set_epi64x(8, 9, 10, 11);
3943 assert_eq_m256i(r, e);
3944 }
3945
3946 #[simd_test(enable = "avx512f,avx512vl")]
3947 unsafe fn test_mm256_maskz_cvtepi32_epi64() {
3948 let a = _mm_set_epi32(8, 9, 10, 11);
3949 let r = _mm256_maskz_cvtepi32_epi64(0, a);
3950 assert_eq_m256i(r, _mm256_setzero_si256());
3951 let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
3952 let e = _mm256_set_epi64x(8, 9, 10, 11);
3953 assert_eq_m256i(r, e);
3954 }
3955
3956 #[simd_test(enable = "avx512f,avx512vl")]
3957 unsafe fn test_mm_mask_cvtepi32_epi64() {
3958 let a = _mm_set_epi32(8, 9, 10, 11);
3959 let src = _mm_set1_epi64x(0);
3960 let r = _mm_mask_cvtepi32_epi64(src, 0, a);
3961 assert_eq_m128i(r, src);
3962 let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
3963 let e = _mm_set_epi64x(10, 11);
3964 assert_eq_m128i(r, e);
3965 }
3966
3967 #[simd_test(enable = "avx512f,avx512vl")]
3968 unsafe fn test_mm_maskz_cvtepi32_epi64() {
3969 let a = _mm_set_epi32(8, 9, 10, 11);
3970 let r = _mm_maskz_cvtepi32_epi64(0, a);
3971 assert_eq_m128i(r, _mm_setzero_si128());
3972 let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
3973 let e = _mm_set_epi64x(10, 11);
3974 assert_eq_m128i(r, e);
3975 }
3976
3977 #[simd_test(enable = "avx512f")]
3978 unsafe fn test_mm512_cvtepu32_epi64() {
3979 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3980 let r = _mm512_cvtepu32_epi64(a);
3981 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3982 assert_eq_m512i(r, e);
3983 }
3984
3985 #[simd_test(enable = "avx512f")]
3986 unsafe fn test_mm512_mask_cvtepu32_epi64() {
3987 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3988 let src = _mm512_set1_epi64(-1);
3989 let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
3990 assert_eq_m512i(r, src);
3991 let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
3992 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3993 assert_eq_m512i(r, e);
3994 }
3995
3996 #[simd_test(enable = "avx512f")]
3997 unsafe fn test_mm512_maskz_cvtepu32_epi64() {
3998 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3999 let r = _mm512_maskz_cvtepu32_epi64(0, a);
4000 assert_eq_m512i(r, _mm512_setzero_si512());
4001 let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4002 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4003 assert_eq_m512i(r, e);
4004 }
4005
4006 #[simd_test(enable = "avx512f,avx512vl")]
4007 unsafe fn test_mm256_mask_cvtepu32_epi64() {
4008 let a = _mm_set_epi32(12, 13, 14, 15);
4009 let src = _mm256_set1_epi64x(-1);
4010 let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4011 assert_eq_m256i(r, src);
4012 let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4013 let e = _mm256_set_epi64x(12, 13, 14, 15);
4014 assert_eq_m256i(r, e);
4015 }
4016
4017 #[simd_test(enable = "avx512f,avx512vl")]
4018 unsafe fn test_mm256_maskz_cvtepu32_epi64() {
4019 let a = _mm_set_epi32(12, 13, 14, 15);
4020 let r = _mm256_maskz_cvtepu32_epi64(0, a);
4021 assert_eq_m256i(r, _mm256_setzero_si256());
4022 let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4023 let e = _mm256_set_epi64x(12, 13, 14, 15);
4024 assert_eq_m256i(r, e);
4025 }
4026
4027 #[simd_test(enable = "avx512f,avx512vl")]
4028 unsafe fn test_mm_mask_cvtepu32_epi64() {
4029 let a = _mm_set_epi32(12, 13, 14, 15);
4030 let src = _mm_set1_epi64x(-1);
4031 let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4032 assert_eq_m128i(r, src);
4033 let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4034 let e = _mm_set_epi64x(14, 15);
4035 assert_eq_m128i(r, e);
4036 }
4037
4038 #[simd_test(enable = "avx512f,avx512vl")]
4039 unsafe fn test_mm_maskz_cvtepu32_epi64() {
4040 let a = _mm_set_epi32(12, 13, 14, 15);
4041 let r = _mm_maskz_cvtepu32_epi64(0, a);
4042 assert_eq_m128i(r, _mm_setzero_si128());
4043 let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4044 let e = _mm_set_epi64x(14, 15);
4045 assert_eq_m128i(r, e);
4046 }
4047
4048 #[simd_test(enable = "avx512f")]
4049 unsafe fn test_mm512_cvtepi32_pd() {
4050 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4051 let r = _mm512_cvtepi32_pd(a);
4052 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4053 assert_eq_m512d(r, e);
4054 }
4055
4056 #[simd_test(enable = "avx512f")]
4057 unsafe fn test_mm512_mask_cvtepi32_pd() {
4058 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4059 let src = _mm512_set1_pd(-1.);
4060 let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4061 assert_eq_m512d(r, src);
4062 let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4063 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4064 assert_eq_m512d(r, e);
4065 }
4066
4067 #[simd_test(enable = "avx512f")]
4068 unsafe fn test_mm512_maskz_cvtepi32_pd() {
4069 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4070 let r = _mm512_maskz_cvtepi32_pd(0, a);
4071 assert_eq_m512d(r, _mm512_setzero_pd());
4072 let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4073 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4074 assert_eq_m512d(r, e);
4075 }
4076
4077 #[simd_test(enable = "avx512f,avx512vl")]
4078 unsafe fn test_mm256_mask_cvtepi32_pd() {
4079 let a = _mm_set_epi32(12, 13, 14, 15);
4080 let src = _mm256_set1_pd(-1.);
4081 let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4082 assert_eq_m256d(r, src);
4083 let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4084 let e = _mm256_set_pd(12., 13., 14., 15.);
4085 assert_eq_m256d(r, e);
4086 }
4087
4088 #[simd_test(enable = "avx512f,avx512vl")]
4089 unsafe fn test_mm256_maskz_cvtepi32_pd() {
4090 let a = _mm_set_epi32(12, 13, 14, 15);
4091 let r = _mm256_maskz_cvtepi32_pd(0, a);
4092 assert_eq_m256d(r, _mm256_setzero_pd());
4093 let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4094 let e = _mm256_set_pd(12., 13., 14., 15.);
4095 assert_eq_m256d(r, e);
4096 }
4097
4098 #[simd_test(enable = "avx512f,avx512vl")]
4099 unsafe fn test_mm_mask_cvtepi32_pd() {
4100 let a = _mm_set_epi32(12, 13, 14, 15);
4101 let src = _mm_set1_pd(-1.);
4102 let r = _mm_mask_cvtepi32_pd(src, 0, a);
4103 assert_eq_m128d(r, src);
4104 let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4105 let e = _mm_set_pd(14., 15.);
4106 assert_eq_m128d(r, e);
4107 }
4108
4109 #[simd_test(enable = "avx512f,avx512vl")]
4110 unsafe fn test_mm_maskz_cvtepi32_pd() {
4111 let a = _mm_set_epi32(12, 13, 14, 15);
4112 let r = _mm_maskz_cvtepi32_pd(0, a);
4113 assert_eq_m128d(r, _mm_setzero_pd());
4114 let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4115 let e = _mm_set_pd(14., 15.);
4116 assert_eq_m128d(r, e);
4117 }
4118
4119 #[simd_test(enable = "avx512f")]
4120 unsafe fn test_mm512_cvtepu32_pd() {
4121 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4122 let r = _mm512_cvtepu32_pd(a);
4123 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4124 assert_eq_m512d(r, e);
4125 }
4126
4127 #[simd_test(enable = "avx512f")]
4128 unsafe fn test_mm512_mask_cvtepu32_pd() {
4129 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4130 let src = _mm512_set1_pd(-1.);
4131 let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4132 assert_eq_m512d(r, src);
4133 let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4134 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4135 assert_eq_m512d(r, e);
4136 }
4137
4138 #[simd_test(enable = "avx512f")]
4139 unsafe fn test_mm512_maskz_cvtepu32_pd() {
4140 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4141 let r = _mm512_maskz_cvtepu32_pd(0, a);
4142 assert_eq_m512d(r, _mm512_setzero_pd());
4143 let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4144 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4145 assert_eq_m512d(r, e);
4146 }
4147
4148 #[simd_test(enable = "avx512f,avx512vl")]
4149 unsafe fn test_mm256_cvtepu32_pd() {
4150 let a = _mm_set_epi32(12, 13, 14, 15);
4151 let r = _mm256_cvtepu32_pd(a);
4152 let e = _mm256_set_pd(12., 13., 14., 15.);
4153 assert_eq_m256d(r, e);
4154 }
4155
4156 #[simd_test(enable = "avx512f,avx512vl")]
4157 unsafe fn test_mm256_mask_cvtepu32_pd() {
4158 let a = _mm_set_epi32(12, 13, 14, 15);
4159 let src = _mm256_set1_pd(-1.);
4160 let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4161 assert_eq_m256d(r, src);
4162 let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4163 let e = _mm256_set_pd(12., 13., 14., 15.);
4164 assert_eq_m256d(r, e);
4165 }
4166
4167 #[simd_test(enable = "avx512f,avx512vl")]
4168 unsafe fn test_mm256_maskz_cvtepu32_pd() {
4169 let a = _mm_set_epi32(12, 13, 14, 15);
4170 let r = _mm256_maskz_cvtepu32_pd(0, a);
4171 assert_eq_m256d(r, _mm256_setzero_pd());
4172 let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4173 let e = _mm256_set_pd(12., 13., 14., 15.);
4174 assert_eq_m256d(r, e);
4175 }
4176
4177 #[simd_test(enable = "avx512f,avx512vl")]
4178 unsafe fn test_mm_cvtepu32_pd() {
4179 let a = _mm_set_epi32(12, 13, 14, 15);
4180 let r = _mm_cvtepu32_pd(a);
4181 let e = _mm_set_pd(14., 15.);
4182 assert_eq_m128d(r, e);
4183 }
4184
4185 #[simd_test(enable = "avx512f,avx512vl")]
4186 unsafe fn test_mm_mask_cvtepu32_pd() {
4187 let a = _mm_set_epi32(12, 13, 14, 15);
4188 let src = _mm_set1_pd(-1.);
4189 let r = _mm_mask_cvtepu32_pd(src, 0, a);
4190 assert_eq_m128d(r, src);
4191 let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4192 let e = _mm_set_pd(14., 15.);
4193 assert_eq_m128d(r, e);
4194 }
4195
4196 #[simd_test(enable = "avx512f,avx512vl")]
4197 unsafe fn test_mm_maskz_cvtepu32_pd() {
4198 let a = _mm_set_epi32(12, 13, 14, 15);
4199 let r = _mm_maskz_cvtepu32_pd(0, a);
4200 assert_eq_m128d(r, _mm_setzero_pd());
4201 let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4202 let e = _mm_set_pd(14., 15.);
4203 assert_eq_m128d(r, e);
4204 }
4205
4206 #[simd_test(enable = "avx512f")]
4207 unsafe fn test_mm512_cvtepi32lo_pd() {
4208 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4209 let r = _mm512_cvtepi32lo_pd(a);
4210 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4211 assert_eq_m512d(r, e);
4212 }
4213
4214 #[simd_test(enable = "avx512f")]
4215 unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4216 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4217 let src = _mm512_set1_pd(-1.);
4218 let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4219 assert_eq_m512d(r, src);
4220 let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4221 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4222 assert_eq_m512d(r, e);
4223 }
4224
4225 #[simd_test(enable = "avx512f")]
4226 unsafe fn test_mm512_cvtepu32lo_pd() {
4227 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4228 let r = _mm512_cvtepu32lo_pd(a);
4229 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4230 assert_eq_m512d(r, e);
4231 }
4232
4233 #[simd_test(enable = "avx512f")]
4234 unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4235 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4236 let src = _mm512_set1_pd(-1.);
4237 let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4238 assert_eq_m512d(r, src);
4239 let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4240 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4241 assert_eq_m512d(r, e);
4242 }
4243
4244 #[simd_test(enable = "avx512f")]
4245 unsafe fn test_mm512_cvtepi64_epi32() {
4246 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4247 let r = _mm512_cvtepi64_epi32(a);
4248 let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4249 assert_eq_m256i(r, e);
4250 }
4251
4252 #[simd_test(enable = "avx512f")]
4253 unsafe fn test_mm512_mask_cvtepi64_epi32() {
4254 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4255 let src = _mm256_set1_epi32(-1);
4256 let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4257 assert_eq_m256i(r, src);
4258 let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4259 let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4260 assert_eq_m256i(r, e);
4261 }
4262
4263 #[simd_test(enable = "avx512f")]
4264 unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4265 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4266 let r = _mm512_maskz_cvtepi64_epi32(0, a);
4267 assert_eq_m256i(r, _mm256_setzero_si256());
4268 let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4269 let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4270 assert_eq_m256i(r, e);
4271 }
4272
4273 #[simd_test(enable = "avx512f,avx512vl")]
4274 unsafe fn test_mm256_cvtepi64_epi32() {
4275 let a = _mm256_set_epi64x(1, 2, 3, 4);
4276 let r = _mm256_cvtepi64_epi32(a);
4277 let e = _mm_set_epi32(1, 2, 3, 4);
4278 assert_eq_m128i(r, e);
4279 }
4280
4281 #[simd_test(enable = "avx512f,avx512vl")]
4282 unsafe fn test_mm256_mask_cvtepi64_epi32() {
4283 let a = _mm256_set_epi64x(1, 2, 3, 4);
4284 let src = _mm_set1_epi32(0);
4285 let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4286 assert_eq_m128i(r, src);
4287 let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4288 let e = _mm_set_epi32(1, 2, 3, 4);
4289 assert_eq_m128i(r, e);
4290 }
4291
4292 #[simd_test(enable = "avx512f,avx512vl")]
4293 unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4294 let a = _mm256_set_epi64x(1, 2, 3, 4);
4295 let r = _mm256_maskz_cvtepi64_epi32(0, a);
4296 assert_eq_m128i(r, _mm_setzero_si128());
4297 let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4298 let e = _mm_set_epi32(1, 2, 3, 4);
4299 assert_eq_m128i(r, e);
4300 }
4301
4302 #[simd_test(enable = "avx512f,avx512vl")]
4303 unsafe fn test_mm_cvtepi64_epi32() {
4304 let a = _mm_set_epi64x(3, 4);
4305 let r = _mm_cvtepi64_epi32(a);
4306 let e = _mm_set_epi32(0, 0, 3, 4);
4307 assert_eq_m128i(r, e);
4308 }
4309
4310 #[simd_test(enable = "avx512f,avx512vl")]
4311 unsafe fn test_mm_mask_cvtepi64_epi32() {
4312 let a = _mm_set_epi64x(3, 4);
4313 let src = _mm_set1_epi32(0);
4314 let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4315 assert_eq_m128i(r, src);
4316 let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4317 let e = _mm_set_epi32(0, 0, 3, 4);
4318 assert_eq_m128i(r, e);
4319 }
4320
4321 #[simd_test(enable = "avx512f,avx512vl")]
4322 unsafe fn test_mm_maskz_cvtepi64_epi32() {
4323 let a = _mm_set_epi64x(3, 4);
4324 let r = _mm_maskz_cvtepi64_epi32(0, a);
4325 assert_eq_m128i(r, _mm_setzero_si128());
4326 let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4327 let e = _mm_set_epi32(0, 0, 3, 4);
4328 assert_eq_m128i(r, e);
4329 }
4330
4331 #[simd_test(enable = "avx512f")]
4332 unsafe fn test_mm512_cvtepi64_epi16() {
4333 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4334 let r = _mm512_cvtepi64_epi16(a);
4335 let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4336 assert_eq_m128i(r, e);
4337 }
4338
4339 #[simd_test(enable = "avx512f")]
4340 unsafe fn test_mm512_mask_cvtepi64_epi16() {
4341 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4342 let src = _mm_set1_epi16(-1);
4343 let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4344 assert_eq_m128i(r, src);
4345 let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4346 let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4347 assert_eq_m128i(r, e);
4348 }
4349
4350 #[simd_test(enable = "avx512f")]
4351 unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4352 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4353 let r = _mm512_maskz_cvtepi64_epi16(0, a);
4354 assert_eq_m128i(r, _mm_setzero_si128());
4355 let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4356 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4357 assert_eq_m128i(r, e);
4358 }
4359
4360 #[simd_test(enable = "avx512f,avx512vl")]
4361 unsafe fn test_mm256_cvtepi64_epi16() {
4362 let a = _mm256_set_epi64x(12, 13, 14, 15);
4363 let r = _mm256_cvtepi64_epi16(a);
4364 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4365 assert_eq_m128i(r, e);
4366 }
4367
4368 #[simd_test(enable = "avx512f,avx512vl")]
4369 unsafe fn test_mm256_mask_cvtepi64_epi16() {
4370 let a = _mm256_set_epi64x(12, 13, 14, 15);
4371 let src = _mm_set1_epi16(0);
4372 let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4373 assert_eq_m128i(r, src);
4374 let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4375 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4376 assert_eq_m128i(r, e);
4377 }
4378
4379 #[simd_test(enable = "avx512f,avx512vl")]
4380 unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4381 let a = _mm256_set_epi64x(12, 13, 14, 15);
4382 let r = _mm256_maskz_cvtepi64_epi16(0, a);
4383 assert_eq_m128i(r, _mm_setzero_si128());
4384 let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4385 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4386 assert_eq_m128i(r, e);
4387 }
4388
4389 #[simd_test(enable = "avx512f,avx512vl")]
4390 unsafe fn test_mm_cvtepi64_epi16() {
4391 let a = _mm_set_epi64x(14, 15);
4392 let r = _mm_cvtepi64_epi16(a);
4393 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4394 assert_eq_m128i(r, e);
4395 }
4396
4397 #[simd_test(enable = "avx512f,avx512vl")]
4398 unsafe fn test_mm_mask_cvtepi64_epi16() {
4399 let a = _mm_set_epi64x(14, 15);
4400 let src = _mm_set1_epi16(0);
4401 let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4402 assert_eq_m128i(r, src);
4403 let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4404 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4405 assert_eq_m128i(r, e);
4406 }
4407
4408 #[simd_test(enable = "avx512f,avx512vl")]
4409 unsafe fn test_mm_maskz_cvtepi64_epi16() {
4410 let a = _mm_set_epi64x(14, 15);
4411 let r = _mm_maskz_cvtepi64_epi16(0, a);
4412 assert_eq_m128i(r, _mm_setzero_si128());
4413 let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4414 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4415 assert_eq_m128i(r, e);
4416 }
4417
4418 #[simd_test(enable = "avx512f")]
4419 unsafe fn test_mm512_cvtepi64_epi8() {
4420 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4421 let r = _mm512_cvtepi64_epi8(a);
4422 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4423 assert_eq_m128i(r, e);
4424 }
4425
4426 #[simd_test(enable = "avx512f")]
4427 unsafe fn test_mm512_mask_cvtepi64_epi8() {
4428 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4429 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4430 let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4431 assert_eq_m128i(r, src);
4432 let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4433 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4434 assert_eq_m128i(r, e);
4435 }
4436
4437 #[simd_test(enable = "avx512f")]
4438 unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4439 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4440 let r = _mm512_maskz_cvtepi64_epi8(0, a);
4441 assert_eq_m128i(r, _mm_setzero_si128());
4442 let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4443 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4444 assert_eq_m128i(r, e);
4445 }
4446
4447 #[simd_test(enable = "avx512f,avx512vl")]
4448 unsafe fn test_mm256_cvtepi64_epi8() {
4449 let a = _mm256_set_epi64x(12, 13, 14, 15);
4450 let r = _mm256_cvtepi64_epi8(a);
4451 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4452 assert_eq_m128i(r, e);
4453 }
4454
4455 #[simd_test(enable = "avx512f,avx512vl")]
4456 unsafe fn test_mm256_mask_cvtepi64_epi8() {
4457 let a = _mm256_set_epi64x(12, 13, 14, 15);
4458 let src = _mm_set1_epi8(0);
4459 let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4460 assert_eq_m128i(r, src);
4461 let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4462 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4463 assert_eq_m128i(r, e);
4464 }
4465
4466 #[simd_test(enable = "avx512f,avx512vl")]
4467 unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4468 let a = _mm256_set_epi64x(12, 13, 14, 15);
4469 let r = _mm256_maskz_cvtepi64_epi8(0, a);
4470 assert_eq_m128i(r, _mm_setzero_si128());
4471 let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4472 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4473 assert_eq_m128i(r, e);
4474 }
4475
4476 #[simd_test(enable = "avx512f,avx512vl")]
4477 unsafe fn test_mm_cvtepi64_epi8() {
4478 let a = _mm_set_epi64x(14, 15);
4479 let r = _mm_cvtepi64_epi8(a);
4480 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4481 assert_eq_m128i(r, e);
4482 }
4483
4484 #[simd_test(enable = "avx512f,avx512vl")]
4485 unsafe fn test_mm_mask_cvtepi64_epi8() {
4486 let a = _mm_set_epi64x(14, 15);
4487 let src = _mm_set1_epi8(0);
4488 let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4489 assert_eq_m128i(r, src);
4490 let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4491 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4492 assert_eq_m128i(r, e);
4493 }
4494
4495 #[simd_test(enable = "avx512f,avx512vl")]
4496 unsafe fn test_mm_maskz_cvtepi64_epi8() {
4497 let a = _mm_set_epi64x(14, 15);
4498 let r = _mm_maskz_cvtepi64_epi8(0, a);
4499 assert_eq_m128i(r, _mm_setzero_si128());
4500 let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4501 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4502 assert_eq_m128i(r, e);
4503 }
4504
4505 #[simd_test(enable = "avx512f")]
4506 unsafe fn test_mm512_cvtsepi64_epi32() {
4507 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4508 let r = _mm512_cvtsepi64_epi32(a);
4509 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4510 assert_eq_m256i(r, e);
4511 }
4512
4513 #[simd_test(enable = "avx512f")]
4514 unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4515 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4516 let src = _mm256_set1_epi32(-1);
4517 let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4518 assert_eq_m256i(r, src);
4519 let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4520 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4521 assert_eq_m256i(r, e);
4522 }
4523
4524 #[simd_test(enable = "avx512f")]
4525 unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4526 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4527 let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4528 assert_eq_m256i(r, _mm256_setzero_si256());
4529 let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4530 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4531 assert_eq_m256i(r, e);
4532 }
4533
4534 #[simd_test(enable = "avx512f,avx512vl")]
4535 unsafe fn test_mm256_cvtsepi64_epi32() {
4536 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4537 let r = _mm256_cvtsepi64_epi32(a);
4538 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4539 assert_eq_m128i(r, e);
4540 }
4541
4542 #[simd_test(enable = "avx512f,avx512vl")]
4543 unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4544 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4545 let src = _mm_set1_epi32(-1);
4546 let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4547 assert_eq_m128i(r, src);
4548 let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4549 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4550 assert_eq_m128i(r, e);
4551 }
4552
4553 #[simd_test(enable = "avx512f,avx512vl")]
4554 unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4555 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4556 let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4557 assert_eq_m128i(r, _mm_setzero_si128());
4558 let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4559 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4560 assert_eq_m128i(r, e);
4561 }
4562
4563 #[simd_test(enable = "avx512f,avx512vl")]
4564 unsafe fn test_mm_cvtsepi64_epi32() {
4565 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4566 let r = _mm_cvtsepi64_epi32(a);
4567 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4568 assert_eq_m128i(r, e);
4569 }
4570
4571 #[simd_test(enable = "avx512f,avx512vl")]
4572 unsafe fn test_mm_mask_cvtsepi64_epi32() {
4573 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4574 let src = _mm_set1_epi32(0);
4575 let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4576 assert_eq_m128i(r, src);
4577 let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4578 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4579 assert_eq_m128i(r, e);
4580 }
4581
4582 #[simd_test(enable = "avx512f,avx512vl")]
4583 unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4584 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4585 let r = _mm_maskz_cvtsepi64_epi32(0, a);
4586 assert_eq_m128i(r, _mm_setzero_si128());
4587 let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4588 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4589 assert_eq_m128i(r, e);
4590 }
4591
4592 #[simd_test(enable = "avx512f")]
4593 unsafe fn test_mm512_cvtsepi64_epi16() {
4594 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4595 let r = _mm512_cvtsepi64_epi16(a);
4596 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4597 assert_eq_m128i(r, e);
4598 }
4599
4600 #[simd_test(enable = "avx512f")]
4601 unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4602 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4603 let src = _mm_set1_epi16(-1);
4604 let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4605 assert_eq_m128i(r, src);
4606 let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4607 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4608 assert_eq_m128i(r, e);
4609 }
4610
4611 #[simd_test(enable = "avx512f")]
4612 unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4613 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4614 let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4615 assert_eq_m128i(r, _mm_setzero_si128());
4616 let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4617 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4618 assert_eq_m128i(r, e);
4619 }
4620
4621 #[simd_test(enable = "avx512f,avx512vl")]
4622 unsafe fn test_mm256_cvtsepi64_epi16() {
4623 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4624 let r = _mm256_cvtsepi64_epi16(a);
4625 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4626 assert_eq_m128i(r, e);
4627 }
4628
4629 #[simd_test(enable = "avx512f,avx512vl")]
4630 unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4631 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4632 let src = _mm_set1_epi16(0);
4633 let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4634 assert_eq_m128i(r, src);
4635 let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4636 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4637 assert_eq_m128i(r, e);
4638 }
4639
4640 #[simd_test(enable = "avx512f,avx512vl")]
4641 unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4642 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4643 let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4644 assert_eq_m128i(r, _mm_setzero_si128());
4645 let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4646 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4647 assert_eq_m128i(r, e);
4648 }
4649
4650 #[simd_test(enable = "avx512f,avx512vl")]
4651 unsafe fn test_mm_cvtsepi64_epi16() {
4652 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4653 let r = _mm_cvtsepi64_epi16(a);
4654 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4655 assert_eq_m128i(r, e);
4656 }
4657
4658 #[simd_test(enable = "avx512f,avx512vl")]
4659 unsafe fn test_mm_mask_cvtsepi64_epi16() {
4660 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4661 let src = _mm_set1_epi16(0);
4662 let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4663 assert_eq_m128i(r, src);
4664 let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4665 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4666 assert_eq_m128i(r, e);
4667 }
4668
4669 #[simd_test(enable = "avx512f,avx512vl")]
4670 unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4671 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4672 let r = _mm_maskz_cvtsepi64_epi16(0, a);
4673 assert_eq_m128i(r, _mm_setzero_si128());
4674 let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4675 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4676 assert_eq_m128i(r, e);
4677 }
4678
4679 #[simd_test(enable = "avx512f")]
4680 unsafe fn test_mm512_cvtsepi64_epi8() {
4681 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4682 let r = _mm512_cvtsepi64_epi8(a);
4683 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4684 assert_eq_m128i(r, e);
4685 }
4686
4687 #[simd_test(enable = "avx512f")]
4688 unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4689 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4690 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4691 let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4692 assert_eq_m128i(r, src);
4693 let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4694 #[rustfmt::skip]
4695 let e = _mm_set_epi8(
4696 0, 0, 0, 0,
4697 0, 0, 0, 0,
4698 -1, -1, -1, -1,
4699 4, 5, i8::MIN, i8::MAX,
4700 );
4701 assert_eq_m128i(r, e);
4702 }
4703
4704 #[simd_test(enable = "avx512f")]
4705 unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4706 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4707 let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4708 assert_eq_m128i(r, _mm_setzero_si128());
4709 let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4710 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4711 assert_eq_m128i(r, e);
4712 }
4713
4714 #[simd_test(enable = "avx512f,avx512vl")]
4715 unsafe fn test_mm256_cvtsepi64_epi8() {
4716 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4717 let r = _mm256_cvtsepi64_epi8(a);
4718 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4719 assert_eq_m128i(r, e);
4720 }
4721
4722 #[simd_test(enable = "avx512f,avx512vl")]
4723 unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4724 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4725 let src = _mm_set1_epi8(0);
4726 let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4727 assert_eq_m128i(r, src);
4728 let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4729 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4730 assert_eq_m128i(r, e);
4731 }
4732
4733 #[simd_test(enable = "avx512f,avx512vl")]
4734 unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4735 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4736 let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4737 assert_eq_m128i(r, _mm_setzero_si128());
4738 let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4739 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4740 assert_eq_m128i(r, e);
4741 }
4742
4743 #[simd_test(enable = "avx512f,avx512vl")]
4744 unsafe fn test_mm_cvtsepi64_epi8() {
4745 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4746 let r = _mm_cvtsepi64_epi8(a);
4747 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4748 assert_eq_m128i(r, e);
4749 }
4750
4751 #[simd_test(enable = "avx512f,avx512vl")]
4752 unsafe fn test_mm_mask_cvtsepi64_epi8() {
4753 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4754 let src = _mm_set1_epi8(0);
4755 let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4756 assert_eq_m128i(r, src);
4757 let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4758 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4759 assert_eq_m128i(r, e);
4760 }
4761
4762 #[simd_test(enable = "avx512f,avx512vl")]
4763 unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4764 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4765 let r = _mm_maskz_cvtsepi64_epi8(0, a);
4766 assert_eq_m128i(r, _mm_setzero_si128());
4767 let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4768 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4769 assert_eq_m128i(r, e);
4770 }
4771
4772 #[simd_test(enable = "avx512f")]
4773 unsafe fn test_mm512_cvtusepi64_epi32() {
4774 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4775 let r = _mm512_cvtusepi64_epi32(a);
4776 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4777 assert_eq_m256i(r, e);
4778 }
4779
4780 #[simd_test(enable = "avx512f")]
4781 unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4782 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4783 let src = _mm256_set1_epi32(-1);
4784 let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4785 assert_eq_m256i(r, src);
4786 let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4787 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4788 assert_eq_m256i(r, e);
4789 }
4790
4791 #[simd_test(enable = "avx512f")]
4792 unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4793 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4794 let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4795 assert_eq_m256i(r, _mm256_setzero_si256());
4796 let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4797 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4798 assert_eq_m256i(r, e);
4799 }
4800
4801 #[simd_test(enable = "avx512f,avx512vl")]
4802 unsafe fn test_mm256_cvtusepi64_epi32() {
4803 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4804 let r = _mm256_cvtusepi64_epi32(a);
4805 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4806 assert_eq_m128i(r, e);
4807 }
4808
4809 #[simd_test(enable = "avx512f,avx512vl")]
4810 unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4811 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4812 let src = _mm_set1_epi32(0);
4813 let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4814 assert_eq_m128i(r, src);
4815 let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4816 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4817 assert_eq_m128i(r, e);
4818 }
4819
4820 #[simd_test(enable = "avx512f,avx512vl")]
4821 unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4822 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4823 let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4824 assert_eq_m128i(r, _mm_setzero_si128());
4825 let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4826 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4827 assert_eq_m128i(r, e);
4828 }
4829
4830 #[simd_test(enable = "avx512f,avx512vl")]
4831 unsafe fn test_mm_cvtusepi64_epi32() {
4832 let a = _mm_set_epi64x(6, i64::MAX);
4833 let r = _mm_cvtusepi64_epi32(a);
4834 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4835 assert_eq_m128i(r, e);
4836 }
4837
4838 #[simd_test(enable = "avx512f,avx512vl")]
4839 unsafe fn test_mm_mask_cvtusepi64_epi32() {
4840 let a = _mm_set_epi64x(6, i64::MAX);
4841 let src = _mm_set1_epi32(0);
4842 let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4843 assert_eq_m128i(r, src);
4844 let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4845 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4846 assert_eq_m128i(r, e);
4847 }
4848
4849 #[simd_test(enable = "avx512f,avx512vl")]
4850 unsafe fn test_mm_maskz_cvtusepi64_epi32() {
4851 let a = _mm_set_epi64x(6, i64::MAX);
4852 let r = _mm_maskz_cvtusepi64_epi32(0, a);
4853 assert_eq_m128i(r, _mm_setzero_si128());
4854 let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
4855 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4856 assert_eq_m128i(r, e);
4857 }
4858
4859 #[simd_test(enable = "avx512f")]
4860 unsafe fn test_mm512_cvtusepi64_epi16() {
4861 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4862 let r = _mm512_cvtusepi64_epi16(a);
4863 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
4864 assert_eq_m128i(r, e);
4865 }
4866
4867 #[simd_test(enable = "avx512f")]
4868 unsafe fn test_mm512_mask_cvtusepi64_epi16() {
4869 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4870 let src = _mm_set1_epi16(-1);
4871 let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
4872 assert_eq_m128i(r, src);
4873 let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
4874 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
4875 assert_eq_m128i(r, e);
4876 }
4877
4878 #[simd_test(enable = "avx512f")]
4879 unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
4880 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4881 let r = _mm512_maskz_cvtusepi64_epi16(0, a);
4882 assert_eq_m128i(r, _mm_setzero_si128());
4883 let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
4884 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
4885 assert_eq_m128i(r, e);
4886 }
4887
4888 #[simd_test(enable = "avx512f,avx512vl")]
4889 unsafe fn test_mm256_cvtusepi64_epi16() {
4890 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4891 let r = _mm256_cvtusepi64_epi16(a);
4892 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4893 assert_eq_m128i(r, e);
4894 }
4895
4896 #[simd_test(enable = "avx512f,avx512vl")]
4897 unsafe fn test_mm256_mask_cvtusepi64_epi16() {
4898 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4899 let src = _mm_set1_epi16(0);
4900 let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
4901 assert_eq_m128i(r, src);
4902 let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
4903 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4904 assert_eq_m128i(r, e);
4905 }
4906
4907 #[simd_test(enable = "avx512f,avx512vl")]
4908 unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
4909 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4910 let r = _mm256_maskz_cvtusepi64_epi16(0, a);
4911 assert_eq_m128i(r, _mm_setzero_si128());
4912 let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
4913 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4914 assert_eq_m128i(r, e);
4915 }
4916
4917 #[simd_test(enable = "avx512f,avx512vl")]
4918 unsafe fn test_mm_cvtusepi64_epi16() {
4919 let a = _mm_set_epi64x(6, i64::MAX);
4920 let r = _mm_cvtusepi64_epi16(a);
4921 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
4922 assert_eq_m128i(r, e);
4923 }
4924
4925 #[simd_test(enable = "avx512f,avx512vl")]
4926 unsafe fn test_mm_mask_cvtusepi64_epi16() {
4927 let a = _mm_set_epi64x(6, i64::MAX);
4928 let src = _mm_set1_epi16(0);
4929 let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
4930 assert_eq_m128i(r, src);
4931 let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
4932 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
4933 assert_eq_m128i(r, e);
4934 }
4935
4936 #[simd_test(enable = "avx512f,avx512vl")]
4937 unsafe fn test_mm_maskz_cvtusepi64_epi16() {
4938 let a = _mm_set_epi64x(6, i64::MAX);
4939 let r = _mm_maskz_cvtusepi64_epi16(0, a);
4940 assert_eq_m128i(r, _mm_setzero_si128());
4941 let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
4942 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
4943 assert_eq_m128i(r, e);
4944 }
4945
4946 #[simd_test(enable = "avx512f")]
4947 unsafe fn test_mm512_cvtusepi64_epi8() {
4948 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4949 let r = _mm512_cvtusepi64_epi8(a);
4950 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
4951 assert_eq_m128i(r, e);
4952 }
4953
4954 #[simd_test(enable = "avx512f")]
4955 unsafe fn test_mm512_mask_cvtusepi64_epi8() {
4956 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4957 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4958 let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
4959 assert_eq_m128i(r, src);
4960 let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
4961 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
4962 assert_eq_m128i(r, e);
4963 }
4964
4965 #[simd_test(enable = "avx512f")]
4966 unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
4967 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4968 let r = _mm512_maskz_cvtusepi64_epi8(0, a);
4969 assert_eq_m128i(r, _mm_setzero_si128());
4970 let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
4971 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
4972 assert_eq_m128i(r, e);
4973 }
4974
4975 #[simd_test(enable = "avx512f,avx512vl")]
4976 unsafe fn test_mm256_cvtusepi64_epi8() {
4977 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4978 let r = _mm256_cvtusepi64_epi8(a);
4979 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
4980 assert_eq_m128i(r, e);
4981 }
4982
4983 #[simd_test(enable = "avx512f,avx512vl")]
4984 unsafe fn test_mm256_mask_cvtusepi64_epi8() {
4985 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4986 let src = _mm_set1_epi8(0);
4987 let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
4988 assert_eq_m128i(r, src);
4989 let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
4990 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
4991 assert_eq_m128i(r, e);
4992 }
4993
4994 #[simd_test(enable = "avx512f,avx512vl")]
4995 unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
4996 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4997 let r = _mm256_maskz_cvtusepi64_epi8(0, a);
4998 assert_eq_m128i(r, _mm_setzero_si128());
4999 let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5000 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5001 assert_eq_m128i(r, e);
5002 }
5003
5004 #[simd_test(enable = "avx512f,avx512vl")]
5005 unsafe fn test_mm_cvtusepi64_epi8() {
5006 let a = _mm_set_epi64x(6, i64::MAX);
5007 let r = _mm_cvtusepi64_epi8(a);
5008 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5009 assert_eq_m128i(r, e);
5010 }
5011
5012 #[simd_test(enable = "avx512f,avx512vl")]
5013 unsafe fn test_mm_mask_cvtusepi64_epi8() {
5014 let a = _mm_set_epi64x(6, i64::MAX);
5015 let src = _mm_set1_epi8(0);
5016 let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5017 assert_eq_m128i(r, src);
5018 let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5019 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5020 assert_eq_m128i(r, e);
5021 }
5022
5023 #[simd_test(enable = "avx512f,avx512vl")]
5024 unsafe fn test_mm_maskz_cvtusepi64_epi8() {
5025 let a = _mm_set_epi64x(6, i64::MAX);
5026 let r = _mm_maskz_cvtusepi64_epi8(0, a);
5027 assert_eq_m128i(r, _mm_setzero_si128());
5028 let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5029 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5030 assert_eq_m128i(r, e);
5031 }
5032
5033 #[simd_test(enable = "avx512f")]
5034 unsafe fn test_mm512_cvtt_roundpd_epi32() {
5035 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5036 let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5037 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5038 assert_eq_m256i(r, e);
5039 }
5040
5041 #[simd_test(enable = "avx512f")]
5042 unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5043 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5044 let src = _mm256_set1_epi32(0);
5045 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5046 assert_eq_m256i(r, src);
5047 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5048 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5049 assert_eq_m256i(r, e);
5050 }
5051
5052 #[simd_test(enable = "avx512f")]
5053 unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5054 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5055 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5056 assert_eq_m256i(r, _mm256_setzero_si256());
5057 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5058 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5059 assert_eq_m256i(r, e);
5060 }
5061
5062 #[simd_test(enable = "avx512f")]
5063 unsafe fn test_mm512_cvtt_roundpd_epu32() {
5064 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5065 let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5066 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5067 assert_eq_m256i(r, e);
5068 }
5069
5070 #[simd_test(enable = "avx512f")]
5071 unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5072 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5073 let src = _mm256_set1_epi32(0);
5074 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5075 assert_eq_m256i(r, src);
5076 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5077 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5078 assert_eq_m256i(r, e);
5079 }
5080
5081 #[simd_test(enable = "avx512f")]
5082 unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5083 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5084 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5085 assert_eq_m256i(r, _mm256_setzero_si256());
5086 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5087 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5088 assert_eq_m256i(r, e);
5089 }
5090
5091 #[simd_test(enable = "avx512f")]
5092 unsafe fn test_mm512_cvttpd_epi32() {
5093 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5094 let r = _mm512_cvttpd_epi32(a);
5095 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5096 assert_eq_m256i(r, e);
5097 }
5098
5099 #[simd_test(enable = "avx512f")]
5100 unsafe fn test_mm512_mask_cvttpd_epi32() {
5101 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5102 let src = _mm256_set1_epi32(0);
5103 let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5104 assert_eq_m256i(r, src);
5105 let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5106 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5107 assert_eq_m256i(r, e);
5108 }
5109
5110 #[simd_test(enable = "avx512f")]
5111 unsafe fn test_mm512_maskz_cvttpd_epi32() {
5112 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5113 let r = _mm512_maskz_cvttpd_epi32(0, a);
5114 assert_eq_m256i(r, _mm256_setzero_si256());
5115 let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5116 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5117 assert_eq_m256i(r, e);
5118 }
5119
5120 #[simd_test(enable = "avx512f,avx512vl")]
5121 unsafe fn test_mm256_mask_cvttpd_epi32() {
5122 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5123 let src = _mm_set1_epi32(0);
5124 let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5125 assert_eq_m128i(r, src);
5126 let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5127 let e = _mm_setr_epi32(4, -5, 6, -7);
5128 assert_eq_m128i(r, e);
5129 }
5130
5131 #[simd_test(enable = "avx512f,avx512vl")]
5132 unsafe fn test_mm256_maskz_cvttpd_epi32() {
5133 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5134 let r = _mm256_maskz_cvttpd_epi32(0, a);
5135 assert_eq_m128i(r, _mm_setzero_si128());
5136 let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5137 let e = _mm_setr_epi32(4, -5, 6, -7);
5138 assert_eq_m128i(r, e);
5139 }
5140
5141 #[simd_test(enable = "avx512f,avx512vl")]
5142 unsafe fn test_mm_mask_cvttpd_epi32() {
5143 let a = _mm_set_pd(6., -7.5);
5144 let src = _mm_set1_epi32(0);
5145 let r = _mm_mask_cvttpd_epi32(src, 0, a);
5146 assert_eq_m128i(r, src);
5147 let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5148 let e = _mm_set_epi32(0, 0, 6, -7);
5149 assert_eq_m128i(r, e);
5150 }
5151
5152 #[simd_test(enable = "avx512f,avx512vl")]
5153 unsafe fn test_mm_maskz_cvttpd_epi32() {
5154 let a = _mm_set_pd(6., -7.5);
5155 let r = _mm_maskz_cvttpd_epi32(0, a);
5156 assert_eq_m128i(r, _mm_setzero_si128());
5157 let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5158 let e = _mm_set_epi32(0, 0, 6, -7);
5159 assert_eq_m128i(r, e);
5160 }
5161
5162 #[simd_test(enable = "avx512f")]
5163 unsafe fn test_mm512_cvttpd_epu32() {
5164 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5165 let r = _mm512_cvttpd_epu32(a);
5166 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5167 assert_eq_m256i(r, e);
5168 }
5169
5170 #[simd_test(enable = "avx512f")]
5171 unsafe fn test_mm512_mask_cvttpd_epu32() {
5172 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5173 let src = _mm256_set1_epi32(0);
5174 let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5175 assert_eq_m256i(r, src);
5176 let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5177 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5178 assert_eq_m256i(r, e);
5179 }
5180
5181 #[simd_test(enable = "avx512f")]
5182 unsafe fn test_mm512_maskz_cvttpd_epu32() {
5183 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5184 let r = _mm512_maskz_cvttpd_epu32(0, a);
5185 assert_eq_m256i(r, _mm256_setzero_si256());
5186 let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5187 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5188 assert_eq_m256i(r, e);
5189 }
5190
5191 #[simd_test(enable = "avx512f,avx512vl")]
5192 unsafe fn test_mm256_cvttpd_epu32() {
5193 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5194 let r = _mm256_cvttpd_epu32(a);
5195 let e = _mm_set_epi32(4, 5, 6, 7);
5196 assert_eq_m128i(r, e);
5197 }
5198
5199 #[simd_test(enable = "avx512f,avx512vl")]
5200 unsafe fn test_mm256_mask_cvttpd_epu32() {
5201 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5202 let src = _mm_set1_epi32(0);
5203 let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5204 assert_eq_m128i(r, src);
5205 let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5206 let e = _mm_set_epi32(4, 5, 6, 7);
5207 assert_eq_m128i(r, e);
5208 }
5209
5210 #[simd_test(enable = "avx512f,avx512vl")]
5211 unsafe fn test_mm256_maskz_cvttpd_epu32() {
5212 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5213 let r = _mm256_maskz_cvttpd_epu32(0, a);
5214 assert_eq_m128i(r, _mm_setzero_si128());
5215 let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5216 let e = _mm_set_epi32(4, 5, 6, 7);
5217 assert_eq_m128i(r, e);
5218 }
5219
5220 #[simd_test(enable = "avx512f,avx512vl")]
5221 unsafe fn test_mm_cvttpd_epu32() {
5222 let a = _mm_set_pd(6., 7.5);
5223 let r = _mm_cvttpd_epu32(a);
5224 let e = _mm_set_epi32(0, 0, 6, 7);
5225 assert_eq_m128i(r, e);
5226 }
5227
5228 #[simd_test(enable = "avx512f,avx512vl")]
5229 unsafe fn test_mm_mask_cvttpd_epu32() {
5230 let a = _mm_set_pd(6., 7.5);
5231 let src = _mm_set1_epi32(0);
5232 let r = _mm_mask_cvttpd_epu32(src, 0, a);
5233 assert_eq_m128i(r, src);
5234 let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5235 let e = _mm_set_epi32(0, 0, 6, 7);
5236 assert_eq_m128i(r, e);
5237 }
5238
5239 #[simd_test(enable = "avx512f,avx512vl")]
5240 unsafe fn test_mm_maskz_cvttpd_epu32() {
5241 let a = _mm_set_pd(6., 7.5);
5242 let r = _mm_maskz_cvttpd_epu32(0, a);
5243 assert_eq_m128i(r, _mm_setzero_si128());
5244 let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5245 let e = _mm_set_epi32(0, 0, 6, 7);
5246 assert_eq_m128i(r, e);
5247 }
5248
5249 #[simd_test(enable = "avx512f")]
5250 unsafe fn test_mm512_add_round_pd() {
5251 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5252 let b = _mm512_set1_pd(-1.);
5253 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5254 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5255 assert_eq_m512d(r, e);
5256 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5257 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5258 assert_eq_m512d(r, e);
5259 }
5260
5261 #[simd_test(enable = "avx512f")]
5262 unsafe fn test_mm512_mask_add_round_pd() {
5263 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5264 let b = _mm512_set1_pd(-1.);
5265 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5266 a, 0, a, b,
5267 );
5268 assert_eq_m512d(r, a);
5269 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5270 a, 0b11110000, a, b,
5271 );
5272 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5273 assert_eq_m512d(r, e);
5274 }
5275
5276 #[simd_test(enable = "avx512f")]
5277 unsafe fn test_mm512_maskz_add_round_pd() {
5278 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5279 let b = _mm512_set1_pd(-1.);
5280 let r =
5281 _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5282 assert_eq_m512d(r, _mm512_setzero_pd());
5283 let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5284 0b11110000, a, b,
5285 );
5286 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5287 assert_eq_m512d(r, e);
5288 }
5289
5290 #[simd_test(enable = "avx512f")]
5291 unsafe fn test_mm512_sub_round_pd() {
5292 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5293 let b = _mm512_set1_pd(1.);
5294 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5295 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5296 assert_eq_m512d(r, e);
5297 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5298 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5299 assert_eq_m512d(r, e);
5300 }
5301
5302 #[simd_test(enable = "avx512f")]
5303 unsafe fn test_mm512_mask_sub_round_pd() {
5304 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5305 let b = _mm512_set1_pd(1.);
5306 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5307 a, 0, a, b,
5308 );
5309 assert_eq_m512d(r, a);
5310 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5311 a, 0b11110000, a, b,
5312 );
5313 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5314 assert_eq_m512d(r, e);
5315 }
5316
5317 #[simd_test(enable = "avx512f")]
5318 unsafe fn test_mm512_maskz_sub_round_pd() {
5319 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5320 let b = _mm512_set1_pd(1.);
5321 let r =
5322 _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5323 assert_eq_m512d(r, _mm512_setzero_pd());
5324 let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5325 0b11110000, a, b,
5326 );
5327 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5328 assert_eq_m512d(r, e);
5329 }
5330
5331 #[simd_test(enable = "avx512f")]
5332 unsafe fn test_mm512_mul_round_pd() {
5333 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5334 let b = _mm512_set1_pd(0.1);
5335 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5336 let e = _mm512_setr_pd(
5337 0.8,
5338 0.9500000000000001,
5339 1.,
5340 1.1500000000000001,
5341 1.2000000000000002,
5342 1.35,
5343 1.4000000000000001,
5344 0.,
5345 );
5346 assert_eq_m512d(r, e);
5347 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5348 let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5349 assert_eq_m512d(r, e);
5350 }
5351
5352 #[simd_test(enable = "avx512f")]
5353 unsafe fn test_mm512_mask_mul_round_pd() {
5354 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5355 let b = _mm512_set1_pd(0.1);
5356 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5357 a, 0, a, b,
5358 );
5359 assert_eq_m512d(r, a);
5360 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5361 a, 0b11110000, a, b,
5362 );
5363 let e = _mm512_setr_pd(
5364 8.,
5365 9.5,
5366 10.,
5367 11.5,
5368 1.2000000000000002,
5369 1.35,
5370 1.4000000000000001,
5371 0.,
5372 );
5373 assert_eq_m512d(r, e);
5374 }
5375
5376 #[simd_test(enable = "avx512f")]
5377 unsafe fn test_mm512_maskz_mul_round_pd() {
5378 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5379 let b = _mm512_set1_pd(0.1);
5380 let r =
5381 _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5382 assert_eq_m512d(r, _mm512_setzero_pd());
5383 let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5384 0b11110000, a, b,
5385 );
5386 let e = _mm512_setr_pd(
5387 0.,
5388 0.,
5389 0.,
5390 0.,
5391 1.2000000000000002,
5392 1.35,
5393 1.4000000000000001,
5394 0.,
5395 );
5396 assert_eq_m512d(r, e);
5397 }
5398
5399 #[simd_test(enable = "avx512f")]
5400 unsafe fn test_mm512_div_round_pd() {
5401 let a = _mm512_set1_pd(1.);
5402 let b = _mm512_set1_pd(3.);
5403 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5404 let e = _mm512_set1_pd(0.3333333333333333);
5405 assert_eq_m512d(r, e);
5406 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5407 let e = _mm512_set1_pd(0.3333333333333333);
5408 assert_eq_m512d(r, e);
5409 }
5410
5411 #[simd_test(enable = "avx512f")]
5412 unsafe fn test_mm512_mask_div_round_pd() {
5413 let a = _mm512_set1_pd(1.);
5414 let b = _mm512_set1_pd(3.);
5415 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5416 a, 0, a, b,
5417 );
5418 assert_eq_m512d(r, a);
5419 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5420 a, 0b11110000, a, b,
5421 );
5422 let e = _mm512_setr_pd(
5423 1.,
5424 1.,
5425 1.,
5426 1.,
5427 0.3333333333333333,
5428 0.3333333333333333,
5429 0.3333333333333333,
5430 0.3333333333333333,
5431 );
5432 assert_eq_m512d(r, e);
5433 }
5434
5435 #[simd_test(enable = "avx512f")]
5436 unsafe fn test_mm512_maskz_div_round_pd() {
5437 let a = _mm512_set1_pd(1.);
5438 let b = _mm512_set1_pd(3.);
5439 let r =
5440 _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5441 assert_eq_m512d(r, _mm512_setzero_pd());
5442 let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5443 0b11110000, a, b,
5444 );
5445 let e = _mm512_setr_pd(
5446 0.,
5447 0.,
5448 0.,
5449 0.,
5450 0.3333333333333333,
5451 0.3333333333333333,
5452 0.3333333333333333,
5453 0.3333333333333333,
5454 );
5455 assert_eq_m512d(r, e);
5456 }
5457
5458 #[simd_test(enable = "avx512f")]
5459 unsafe fn test_mm512_sqrt_round_pd() {
5460 let a = _mm512_set1_pd(3.);
5461 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5462 let e = _mm512_set1_pd(1.7320508075688772);
5463 assert_eq_m512d(r, e);
5464 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5465 let e = _mm512_set1_pd(1.7320508075688774);
5466 assert_eq_m512d(r, e);
5467 }
5468
5469 #[simd_test(enable = "avx512f")]
5470 unsafe fn test_mm512_mask_sqrt_round_pd() {
5471 let a = _mm512_set1_pd(3.);
5472 let r =
5473 _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5474 assert_eq_m512d(r, a);
5475 let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5476 a, 0b11110000, a,
5477 );
5478 let e = _mm512_setr_pd(
5479 3.,
5480 3.,
5481 3.,
5482 3.,
5483 1.7320508075688772,
5484 1.7320508075688772,
5485 1.7320508075688772,
5486 1.7320508075688772,
5487 );
5488 assert_eq_m512d(r, e);
5489 }
5490
5491 #[simd_test(enable = "avx512f")]
5492 unsafe fn test_mm512_maskz_sqrt_round_pd() {
5493 let a = _mm512_set1_pd(3.);
5494 let r =
5495 _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5496 assert_eq_m512d(r, _mm512_setzero_pd());
5497 let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5498 0b11110000, a,
5499 );
5500 let e = _mm512_setr_pd(
5501 0.,
5502 0.,
5503 0.,
5504 0.,
5505 1.7320508075688772,
5506 1.7320508075688772,
5507 1.7320508075688772,
5508 1.7320508075688772,
5509 );
5510 assert_eq_m512d(r, e);
5511 }
5512
5513 #[simd_test(enable = "avx512f")]
5514 unsafe fn test_mm512_fmadd_round_pd() {
5515 let a = _mm512_set1_pd(0.000000000000000007);
5516 let b = _mm512_set1_pd(1.);
5517 let c = _mm512_set1_pd(-1.);
5518 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5519 let e = _mm512_set1_pd(-1.);
5520 assert_eq_m512d(r, e);
5521 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5522 let e = _mm512_set1_pd(-0.9999999999999999);
5523 assert_eq_m512d(r, e);
5524 }
5525
5526 #[simd_test(enable = "avx512f")]
5527 unsafe fn test_mm512_mask_fmadd_round_pd() {
5528 let a = _mm512_set1_pd(0.000000000000000007);
5529 let b = _mm512_set1_pd(1.);
5530 let c = _mm512_set1_pd(-1.);
5531 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5532 a, 0, b, c,
5533 );
5534 assert_eq_m512d(r, a);
5535 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5536 a, 0b00001111, b, c,
5537 );
5538 let e = _mm512_setr_pd(
5539 -1.,
5540 -1.,
5541 -1.,
5542 -1.,
5543 0.000000000000000007,
5544 0.000000000000000007,
5545 0.000000000000000007,
5546 0.000000000000000007,
5547 );
5548 assert_eq_m512d(r, e);
5549 }
5550
5551 #[simd_test(enable = "avx512f")]
5552 unsafe fn test_mm512_maskz_fmadd_round_pd() {
5553 let a = _mm512_set1_pd(0.000000000000000007);
5554 let b = _mm512_set1_pd(1.);
5555 let c = _mm512_set1_pd(-1.);
5556 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5557 0, a, b, c,
5558 );
5559 assert_eq_m512d(r, _mm512_setzero_pd());
5560 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5561 0b00001111, a, b, c,
5562 );
5563 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5564 assert_eq_m512d(r, e);
5565 }
5566
5567 #[simd_test(enable = "avx512f")]
5568 unsafe fn test_mm512_mask3_fmadd_round_pd() {
5569 let a = _mm512_set1_pd(0.000000000000000007);
5570 let b = _mm512_set1_pd(1.);
5571 let c = _mm512_set1_pd(-1.);
5572 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5573 a, b, c, 0,
5574 );
5575 assert_eq_m512d(r, c);
5576 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5577 a, b, c, 0b00001111,
5578 );
5579 let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5580 assert_eq_m512d(r, e);
5581 }
5582
5583 #[simd_test(enable = "avx512f")]
5584 unsafe fn test_mm512_fmsub_round_pd() {
5585 let a = _mm512_set1_pd(0.000000000000000007);
5586 let b = _mm512_set1_pd(1.);
5587 let c = _mm512_set1_pd(1.);
5588 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5589 let e = _mm512_set1_pd(-1.);
5590 assert_eq_m512d(r, e);
5591 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5592 let e = _mm512_set1_pd(-0.9999999999999999);
5593 assert_eq_m512d(r, e);
5594 }
5595
5596 #[simd_test(enable = "avx512f")]
5597 unsafe fn test_mm512_mask_fmsub_round_pd() {
5598 let a = _mm512_set1_pd(0.000000000000000007);
5599 let b = _mm512_set1_pd(1.);
5600 let c = _mm512_set1_pd(1.);
5601 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5602 a, 0, b, c,
5603 );
5604 assert_eq_m512d(r, a);
5605 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5606 a, 0b00001111, b, c,
5607 );
5608 let e = _mm512_setr_pd(
5609 -1.,
5610 -1.,
5611 -1.,
5612 -1.,
5613 0.000000000000000007,
5614 0.000000000000000007,
5615 0.000000000000000007,
5616 0.000000000000000007,
5617 );
5618 assert_eq_m512d(r, e);
5619 }
5620
5621 #[simd_test(enable = "avx512f")]
5622 unsafe fn test_mm512_maskz_fmsub_round_pd() {
5623 let a = _mm512_set1_pd(0.000000000000000007);
5624 let b = _mm512_set1_pd(1.);
5625 let c = _mm512_set1_pd(1.);
5626 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5627 0, a, b, c,
5628 );
5629 assert_eq_m512d(r, _mm512_setzero_pd());
5630 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5631 0b00001111, a, b, c,
5632 );
5633 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5634 assert_eq_m512d(r, e);
5635 }
5636
5637 #[simd_test(enable = "avx512f")]
5638 unsafe fn test_mm512_mask3_fmsub_round_pd() {
5639 let a = _mm512_set1_pd(0.000000000000000007);
5640 let b = _mm512_set1_pd(1.);
5641 let c = _mm512_set1_pd(1.);
5642 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5643 a, b, c, 0,
5644 );
5645 assert_eq_m512d(r, c);
5646 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5647 a, b, c, 0b00001111,
5648 );
5649 let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5650 assert_eq_m512d(r, e);
5651 }
5652
5653 #[simd_test(enable = "avx512f")]
5654 unsafe fn test_mm512_fmaddsub_round_pd() {
5655 let a = _mm512_set1_pd(0.000000000000000007);
5656 let b = _mm512_set1_pd(1.);
5657 let c = _mm512_set1_pd(-1.);
5658 let r =
5659 _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5660 let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5661 assert_eq_m512d(r, e);
5662 let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5663 let e = _mm512_setr_pd(
5664 1.,
5665 -0.9999999999999999,
5666 1.,
5667 -0.9999999999999999,
5668 1.,
5669 -0.9999999999999999,
5670 1.,
5671 -0.9999999999999999,
5672 );
5673 assert_eq_m512d(r, e);
5674 }
5675
5676 #[simd_test(enable = "avx512f")]
5677 unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5678 let a = _mm512_set1_pd(0.000000000000000007);
5679 let b = _mm512_set1_pd(1.);
5680 let c = _mm512_set1_pd(-1.);
5681 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5682 a, 0, b, c,
5683 );
5684 assert_eq_m512d(r, a);
5685 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5686 a, 0b00001111, b, c,
5687 );
5688 let e = _mm512_setr_pd(
5689 1.,
5690 -1.,
5691 1.,
5692 -1.,
5693 0.000000000000000007,
5694 0.000000000000000007,
5695 0.000000000000000007,
5696 0.000000000000000007,
5697 );
5698 assert_eq_m512d(r, e);
5699 }
5700
5701 #[simd_test(enable = "avx512f")]
5702 unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5703 let a = _mm512_set1_pd(0.000000000000000007);
5704 let b = _mm512_set1_pd(1.);
5705 let c = _mm512_set1_pd(-1.);
5706 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5707 0, a, b, c,
5708 );
5709 assert_eq_m512d(r, _mm512_setzero_pd());
5710 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5711 0b00001111, a, b, c,
5712 );
5713 let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5714 assert_eq_m512d(r, e);
5715 }
5716
5717 #[simd_test(enable = "avx512f")]
5718 unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5719 let a = _mm512_set1_pd(0.000000000000000007);
5720 let b = _mm512_set1_pd(1.);
5721 let c = _mm512_set1_pd(-1.);
5722 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5723 a, b, c, 0,
5724 );
5725 assert_eq_m512d(r, c);
5726 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5727 a, b, c, 0b00001111,
5728 );
5729 let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5730 assert_eq_m512d(r, e);
5731 }
5732
5733 #[simd_test(enable = "avx512f")]
5734 unsafe fn test_mm512_fmsubadd_round_pd() {
5735 let a = _mm512_set1_pd(0.000000000000000007);
5736 let b = _mm512_set1_pd(1.);
5737 let c = _mm512_set1_pd(-1.);
5738 let r =
5739 _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5740 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5741 assert_eq_m512d(r, e);
5742 let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5743 let e = _mm512_setr_pd(
5744 -0.9999999999999999,
5745 1.,
5746 -0.9999999999999999,
5747 1.,
5748 -0.9999999999999999,
5749 1.,
5750 -0.9999999999999999,
5751 1.,
5752 );
5753 assert_eq_m512d(r, e);
5754 }
5755
5756 #[simd_test(enable = "avx512f")]
5757 unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5758 let a = _mm512_set1_pd(0.000000000000000007);
5759 let b = _mm512_set1_pd(1.);
5760 let c = _mm512_set1_pd(-1.);
5761 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5762 a, 0, b, c,
5763 );
5764 assert_eq_m512d(r, a);
5765 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5766 a, 0b00001111, b, c,
5767 );
5768 let e = _mm512_setr_pd(
5769 -1.,
5770 1.,
5771 -1.,
5772 1.,
5773 0.000000000000000007,
5774 0.000000000000000007,
5775 0.000000000000000007,
5776 0.000000000000000007,
5777 );
5778 assert_eq_m512d(r, e);
5779 }
5780
5781 #[simd_test(enable = "avx512f")]
5782 unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5783 let a = _mm512_set1_pd(0.000000000000000007);
5784 let b = _mm512_set1_pd(1.);
5785 let c = _mm512_set1_pd(-1.);
5786 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5787 0, a, b, c,
5788 );
5789 assert_eq_m512d(r, _mm512_setzero_pd());
5790 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5791 0b00001111, a, b, c,
5792 );
5793 let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5794 assert_eq_m512d(r, e);
5795 }
5796
5797 #[simd_test(enable = "avx512f")]
5798 unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5799 let a = _mm512_set1_pd(0.000000000000000007);
5800 let b = _mm512_set1_pd(1.);
5801 let c = _mm512_set1_pd(-1.);
5802 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5803 a, b, c, 0,
5804 );
5805 assert_eq_m512d(r, c);
5806 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5807 a, b, c, 0b00001111,
5808 );
5809 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5810 assert_eq_m512d(r, e);
5811 }
5812
5813 #[simd_test(enable = "avx512f")]
5814 unsafe fn test_mm512_fnmadd_round_pd() {
5815 let a = _mm512_set1_pd(0.000000000000000007);
5816 let b = _mm512_set1_pd(1.);
5817 let c = _mm512_set1_pd(1.);
5818 let r =
5819 _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5820 let e = _mm512_set1_pd(1.);
5821 assert_eq_m512d(r, e);
5822 let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5823 let e = _mm512_set1_pd(0.9999999999999999);
5824 assert_eq_m512d(r, e);
5825 }
5826
5827 #[simd_test(enable = "avx512f")]
5828 unsafe fn test_mm512_mask_fnmadd_round_pd() {
5829 let a = _mm512_set1_pd(0.000000000000000007);
5830 let b = _mm512_set1_pd(1.);
5831 let c = _mm512_set1_pd(1.);
5832 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5833 a, 0, b, c,
5834 );
5835 assert_eq_m512d(r, a);
5836 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5837 a, 0b00001111, b, c,
5838 );
5839 let e = _mm512_setr_pd(
5840 1.,
5841 1.,
5842 1.,
5843 1.,
5844 0.000000000000000007,
5845 0.000000000000000007,
5846 0.000000000000000007,
5847 0.000000000000000007,
5848 );
5849 assert_eq_m512d(r, e);
5850 }
5851
5852 #[simd_test(enable = "avx512f")]
5853 unsafe fn test_mm512_maskz_fnmadd_round_pd() {
5854 let a = _mm512_set1_pd(0.000000000000000007);
5855 let b = _mm512_set1_pd(1.);
5856 let c = _mm512_set1_pd(1.);
5857 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5858 0, a, b, c,
5859 );
5860 assert_eq_m512d(r, _mm512_setzero_pd());
5861 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5862 0b00001111, a, b, c,
5863 );
5864 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
5865 assert_eq_m512d(r, e);
5866 }
5867
5868 #[simd_test(enable = "avx512f")]
5869 unsafe fn test_mm512_mask3_fnmadd_round_pd() {
5870 let a = _mm512_set1_pd(0.000000000000000007);
5871 let b = _mm512_set1_pd(1.);
5872 let c = _mm512_set1_pd(1.);
5873 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5874 a, b, c, 0,
5875 );
5876 assert_eq_m512d(r, c);
5877 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5878 a, b, c, 0b00001111,
5879 );
5880 let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
5881 assert_eq_m512d(r, e);
5882 }
5883
5884 #[simd_test(enable = "avx512f")]
5885 unsafe fn test_mm512_fnmsub_round_pd() {
5886 let a = _mm512_set1_pd(0.000000000000000007);
5887 let b = _mm512_set1_pd(1.);
5888 let c = _mm512_set1_pd(-1.);
5889 let r =
5890 _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5891 let e = _mm512_set1_pd(1.);
5892 assert_eq_m512d(r, e);
5893 let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5894 let e = _mm512_set1_pd(0.9999999999999999);
5895 assert_eq_m512d(r, e);
5896 }
5897
5898 #[simd_test(enable = "avx512f")]
5899 unsafe fn test_mm512_mask_fnmsub_round_pd() {
5900 let a = _mm512_set1_pd(0.000000000000000007);
5901 let b = _mm512_set1_pd(1.);
5902 let c = _mm512_set1_pd(-1.);
5903 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5904 a, 0, b, c,
5905 );
5906 assert_eq_m512d(r, a);
5907 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5908 a, 0b00001111, b, c,
5909 );
5910 let e = _mm512_setr_pd(
5911 1.,
5912 1.,
5913 1.,
5914 1.,
5915 0.000000000000000007,
5916 0.000000000000000007,
5917 0.000000000000000007,
5918 0.000000000000000007,
5919 );
5920 assert_eq_m512d(r, e);
5921 }
5922
5923 #[simd_test(enable = "avx512f")]
5924 unsafe fn test_mm512_maskz_fnmsub_round_pd() {
5925 let a = _mm512_set1_pd(0.000000000000000007);
5926 let b = _mm512_set1_pd(1.);
5927 let c = _mm512_set1_pd(-1.);
5928 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5929 0, a, b, c,
5930 );
5931 assert_eq_m512d(r, _mm512_setzero_pd());
5932 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5933 0b00001111, a, b, c,
5934 );
5935 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
5936 assert_eq_m512d(r, e);
5937 }
5938
5939 #[simd_test(enable = "avx512f")]
5940 unsafe fn test_mm512_mask3_fnmsub_round_pd() {
5941 let a = _mm512_set1_pd(0.000000000000000007);
5942 let b = _mm512_set1_pd(1.);
5943 let c = _mm512_set1_pd(-1.);
5944 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5945 a, b, c, 0,
5946 );
5947 assert_eq_m512d(r, c);
5948 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5949 a, b, c, 0b00001111,
5950 );
5951 let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
5952 assert_eq_m512d(r, e);
5953 }
5954
5955 #[simd_test(enable = "avx512f")]
5956 unsafe fn test_mm512_max_round_pd() {
5957 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5958 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5959 let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
5960 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
5961 assert_eq_m512d(r, e);
5962 }
5963
5964 #[simd_test(enable = "avx512f")]
5965 unsafe fn test_mm512_mask_max_round_pd() {
5966 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5967 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5968 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
5969 assert_eq_m512d(r, a);
5970 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
5971 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
5972 assert_eq_m512d(r, e);
5973 }
5974
5975 #[simd_test(enable = "avx512f")]
5976 unsafe fn test_mm512_maskz_max_round_pd() {
5977 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5978 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5979 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
5980 assert_eq_m512d(r, _mm512_setzero_pd());
5981 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
5982 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
5983 assert_eq_m512d(r, e);
5984 }
5985
5986 #[simd_test(enable = "avx512f")]
5987 unsafe fn test_mm512_min_round_pd() {
5988 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5989 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5990 let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
5991 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
5992 assert_eq_m512d(r, e);
5993 }
5994
5995 #[simd_test(enable = "avx512f")]
5996 unsafe fn test_mm512_mask_min_round_pd() {
5997 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5998 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5999 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6000 assert_eq_m512d(r, a);
6001 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6002 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6003 assert_eq_m512d(r, e);
6004 }
6005
6006 #[simd_test(enable = "avx512f")]
6007 unsafe fn test_mm512_maskz_min_round_pd() {
6008 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6009 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6010 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6011 assert_eq_m512d(r, _mm512_setzero_pd());
6012 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6013 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6014 assert_eq_m512d(r, e);
6015 }
6016
6017 #[simd_test(enable = "avx512f")]
6018 unsafe fn test_mm512_getexp_round_pd() {
6019 let a = _mm512_set1_pd(3.);
6020 let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6021 let e = _mm512_set1_pd(1.);
6022 assert_eq_m512d(r, e);
6023 }
6024
6025 #[simd_test(enable = "avx512f")]
6026 unsafe fn test_mm512_mask_getexp_round_pd() {
6027 let a = _mm512_set1_pd(3.);
6028 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6029 assert_eq_m512d(r, a);
6030 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6031 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6032 assert_eq_m512d(r, e);
6033 }
6034
6035 #[simd_test(enable = "avx512f")]
6036 unsafe fn test_mm512_maskz_getexp_round_pd() {
6037 let a = _mm512_set1_pd(3.);
6038 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6039 assert_eq_m512d(r, _mm512_setzero_pd());
6040 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6041 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6042 assert_eq_m512d(r, e);
6043 }
6044
6045 #[simd_test(enable = "avx512f")]
6046 unsafe fn test_mm512_roundscale_round_pd() {
6047 let a = _mm512_set1_pd(1.1);
6048 let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6049 let e = _mm512_set1_pd(1.0);
6050 assert_eq_m512d(r, e);
6051 }
6052
6053 #[simd_test(enable = "avx512f")]
6054 unsafe fn test_mm512_mask_roundscale_round_pd() {
6055 let a = _mm512_set1_pd(1.1);
6056 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6057 let e = _mm512_set1_pd(1.1);
6058 assert_eq_m512d(r, e);
6059 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6060 let e = _mm512_set1_pd(1.0);
6061 assert_eq_m512d(r, e);
6062 }
6063
6064 #[simd_test(enable = "avx512f")]
6065 unsafe fn test_mm512_maskz_roundscale_round_pd() {
6066 let a = _mm512_set1_pd(1.1);
6067 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6068 assert_eq_m512d(r, _mm512_setzero_pd());
6069 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6070 let e = _mm512_set1_pd(1.0);
6071 assert_eq_m512d(r, e);
6072 }
6073
6074 #[simd_test(enable = "avx512f")]
6075 unsafe fn test_mm512_scalef_round_pd() {
6076 let a = _mm512_set1_pd(1.);
6077 let b = _mm512_set1_pd(3.);
6078 let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6079 let e = _mm512_set1_pd(8.);
6080 assert_eq_m512d(r, e);
6081 }
6082
6083 #[simd_test(enable = "avx512f")]
6084 unsafe fn test_mm512_mask_scalef_round_pd() {
6085 let a = _mm512_set1_pd(1.);
6086 let b = _mm512_set1_pd(3.);
6087 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6088 a, 0, a, b,
6089 );
6090 assert_eq_m512d(r, a);
6091 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6092 a, 0b11110000, a, b,
6093 );
6094 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6095 assert_eq_m512d(r, e);
6096 }
6097
6098 #[simd_test(enable = "avx512f")]
6099 unsafe fn test_mm512_maskz_scalef_round_pd() {
6100 let a = _mm512_set1_pd(1.);
6101 let b = _mm512_set1_pd(3.);
6102 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6103 0, a, b,
6104 );
6105 assert_eq_m512d(r, _mm512_setzero_pd());
6106 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6107 0b11110000, a, b,
6108 );
6109 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6110 assert_eq_m512d(r, e);
6111 }
6112
6113 #[simd_test(enable = "avx512f")]
6114 unsafe fn test_mm512_fixupimm_round_pd() {
6115 let a = _mm512_set1_pd(f64::NAN);
6116 let b = _mm512_set1_pd(f64::MAX);
6117 let c = _mm512_set1_epi64(i32::MAX as i64);
6118 let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6119 let e = _mm512_set1_pd(0.0);
6120 assert_eq_m512d(r, e);
6121 }
6122
6123 #[simd_test(enable = "avx512f")]
6124 unsafe fn test_mm512_mask_fixupimm_round_pd() {
6125 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6126 let b = _mm512_set1_pd(f64::MAX);
6127 let c = _mm512_set1_epi64(i32::MAX as i64);
6128 let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6129 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6130 assert_eq_m512d(r, e);
6131 }
6132
6133 #[simd_test(enable = "avx512f")]
6134 unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6135 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6136 let b = _mm512_set1_pd(f64::MAX);
6137 let c = _mm512_set1_epi64(i32::MAX as i64);
6138 let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6139 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6140 assert_eq_m512d(r, e);
6141 }
6142
6143 #[simd_test(enable = "avx512f")]
6144 unsafe fn test_mm512_getmant_round_pd() {
6145 let a = _mm512_set1_pd(10.);
6146 let r = _mm512_getmant_round_pd::<
6147 _MM_MANT_NORM_1_2,
6148 _MM_MANT_SIGN_SRC,
6149 _MM_FROUND_CUR_DIRECTION,
6150 >(a);
6151 let e = _mm512_set1_pd(1.25);
6152 assert_eq_m512d(r, e);
6153 }
6154
6155 #[simd_test(enable = "avx512f")]
6156 unsafe fn test_mm512_mask_getmant_round_pd() {
6157 let a = _mm512_set1_pd(10.);
6158 let r = _mm512_mask_getmant_round_pd::<
6159 _MM_MANT_NORM_1_2,
6160 _MM_MANT_SIGN_SRC,
6161 _MM_FROUND_CUR_DIRECTION,
6162 >(a, 0, a);
6163 assert_eq_m512d(r, a);
6164 let r = _mm512_mask_getmant_round_pd::<
6165 _MM_MANT_NORM_1_2,
6166 _MM_MANT_SIGN_SRC,
6167 _MM_FROUND_CUR_DIRECTION,
6168 >(a, 0b11110000, a);
6169 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6170 assert_eq_m512d(r, e);
6171 }
6172
6173 #[simd_test(enable = "avx512f")]
6174 unsafe fn test_mm512_maskz_getmant_round_pd() {
6175 let a = _mm512_set1_pd(10.);
6176 let r = _mm512_maskz_getmant_round_pd::<
6177 _MM_MANT_NORM_1_2,
6178 _MM_MANT_SIGN_SRC,
6179 _MM_FROUND_CUR_DIRECTION,
6180 >(0, a);
6181 assert_eq_m512d(r, _mm512_setzero_pd());
6182 let r = _mm512_maskz_getmant_round_pd::<
6183 _MM_MANT_NORM_1_2,
6184 _MM_MANT_SIGN_SRC,
6185 _MM_FROUND_CUR_DIRECTION,
6186 >(0b11110000, a);
6187 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6188 assert_eq_m512d(r, e);
6189 }
6190
6191 #[simd_test(enable = "avx512f")]
6192 unsafe fn test_mm512_cvt_roundps_pd() {
6193 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6194 let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6195 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6196 assert_eq_m512d(r, e);
6197 }
6198
6199 #[simd_test(enable = "avx512f")]
6200 unsafe fn test_mm512_mask_cvt_roundps_pd() {
6201 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6202 let src = _mm512_set1_pd(0.);
6203 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6204 assert_eq_m512d(r, src);
6205 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6206 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6207 assert_eq_m512d(r, e);
6208 }
6209
6210 #[simd_test(enable = "avx512f")]
6211 unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6212 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6213 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6214 assert_eq_m512d(r, _mm512_setzero_pd());
6215 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6216 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6217 assert_eq_m512d(r, e);
6218 }
6219
6220 #[simd_test(enable = "avx512f")]
6221 unsafe fn test_mm512_cvt_roundpd_ps() {
6222 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6223 let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6224 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6225 assert_eq_m256(r, e);
6226 }
6227
6228 #[simd_test(enable = "avx512f")]
6229 unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6230 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6231 let src = _mm256_set1_ps(0.);
6232 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6233 assert_eq_m256(r, src);
6234 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6235 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6236 assert_eq_m256(r, e);
6237 }
6238
6239 #[simd_test(enable = "avx512f")]
6240 unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6241 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6242 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6243 assert_eq_m256(r, _mm256_setzero_ps());
6244 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6245 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6246 assert_eq_m256(r, e);
6247 }
6248
6249 #[simd_test(enable = "avx512f")]
6250 unsafe fn test_mm512_cvt_roundpd_epi32() {
6251 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6252 let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6253 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6254 assert_eq_m256i(r, e);
6255 }
6256
6257 #[simd_test(enable = "avx512f")]
6258 unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6259 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6260 let src = _mm256_set1_epi32(0);
6261 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6262 assert_eq_m256i(r, src);
6263 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6264 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6265 assert_eq_m256i(r, e);
6266 }
6267
6268 #[simd_test(enable = "avx512f")]
6269 unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6270 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6271 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6272 assert_eq_m256i(r, _mm256_setzero_si256());
6273 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6274 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6275 assert_eq_m256i(r, e);
6276 }
6277
6278 #[simd_test(enable = "avx512f")]
6279 unsafe fn test_mm512_cvt_roundpd_epu32() {
6280 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6281 let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6282 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6283 assert_eq_m256i(r, e);
6284 }
6285
6286 #[simd_test(enable = "avx512f")]
6287 unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6288 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6289 let src = _mm256_set1_epi32(0);
6290 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6291 assert_eq_m256i(r, src);
6292 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6293 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6294 assert_eq_m256i(r, e);
6295 }
6296
6297 #[simd_test(enable = "avx512f")]
6298 unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6299 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6300 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6301 assert_eq_m256i(r, _mm256_setzero_si256());
6302 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6303 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6304 assert_eq_m256i(r, e);
6305 }
6306
6307 #[simd_test(enable = "avx512f")]
6308 unsafe fn test_mm512_setzero_pd() {
6309 assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6310 }
6311
6312 unsafe fn test_mm512_set1_epi64() {
6313 let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6314 assert_eq_m512i(r, _mm512_set1_epi64(2));
6315 }
6316
6317 #[simd_test(enable = "avx512f")]
6318 unsafe fn test_mm512_set1_pd() {
6319 let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6320 assert_eq_m512d(expected, _mm512_set1_pd(2.));
6321 }
6322
6323 unsafe fn test_mm512_set4_epi64() {
6324 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6325 assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6326 }
6327
6328 #[simd_test(enable = "avx512f")]
6329 unsafe fn test_mm512_set4_pd() {
6330 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6331 assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6332 }
6333
6334 unsafe fn test_mm512_setr4_epi64() {
6335 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6336 assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6337 }
6338
6339 #[simd_test(enable = "avx512f")]
6340 unsafe fn test_mm512_setr4_pd() {
6341 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6342 assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6343 }
6344
6345 #[simd_test(enable = "avx512f")]
6346 unsafe fn test_mm512_cmplt_pd_mask() {
6347 #[rustfmt::skip]
6348 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6349 let b = _mm512_set1_pd(-1.);
6350 let m = _mm512_cmplt_pd_mask(a, b);
6351 assert_eq!(m, 0b00000101);
6352 }
6353
6354 #[simd_test(enable = "avx512f")]
6355 unsafe fn test_mm512_mask_cmplt_pd_mask() {
6356 #[rustfmt::skip]
6357 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6358 let b = _mm512_set1_pd(-1.);
6359 let mask = 0b01100110;
6360 let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6361 assert_eq!(r, 0b00000100);
6362 }
6363
6364 #[simd_test(enable = "avx512f")]
6365 unsafe fn test_mm512_cmpnlt_pd_mask() {
6366 #[rustfmt::skip]
6367 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6368 let b = _mm512_set1_pd(-1.);
6369 assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6370 }
6371
6372 #[simd_test(enable = "avx512f")]
6373 unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6374 #[rustfmt::skip]
6375 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6376 let b = _mm512_set1_pd(-1.);
6377 let mask = 0b01111010;
6378 assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6379 }
6380
6381 #[simd_test(enable = "avx512f")]
6382 unsafe fn test_mm512_cmple_pd_mask() {
6383 #[rustfmt::skip]
6384 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6385 let b = _mm512_set1_pd(-1.);
6386 assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6387 }
6388
6389 #[simd_test(enable = "avx512f")]
6390 unsafe fn test_mm512_mask_cmple_pd_mask() {
6391 #[rustfmt::skip]
6392 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6393 let b = _mm512_set1_pd(-1.);
6394 let mask = 0b01111010;
6395 assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6396 }
6397
6398 #[simd_test(enable = "avx512f")]
6399 unsafe fn test_mm512_cmpnle_pd_mask() {
6400 #[rustfmt::skip]
6401 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6402 let b = _mm512_set1_pd(-1.);
6403 let m = _mm512_cmpnle_pd_mask(b, a);
6404 assert_eq!(m, 0b00001101);
6405 }
6406
6407 #[simd_test(enable = "avx512f")]
6408 unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6409 #[rustfmt::skip]
6410 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6411 let b = _mm512_set1_pd(-1.);
6412 let mask = 0b01100110;
6413 let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6414 assert_eq!(r, 0b00000100);
6415 }
6416
6417 #[simd_test(enable = "avx512f")]
6418 unsafe fn test_mm512_cmpeq_pd_mask() {
6419 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6420 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6421 let m = _mm512_cmpeq_pd_mask(b, a);
6422 assert_eq!(m, 0b11001101);
6423 }
6424
6425 #[simd_test(enable = "avx512f")]
6426 unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6427 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6428 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6429 let mask = 0b01111010;
6430 let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6431 assert_eq!(r, 0b01001000);
6432 }
6433
6434 #[simd_test(enable = "avx512f")]
6435 unsafe fn test_mm512_cmpneq_pd_mask() {
6436 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6437 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6438 let m = _mm512_cmpneq_pd_mask(b, a);
6439 assert_eq!(m, 0b00110010);
6440 }
6441
6442 #[simd_test(enable = "avx512f")]
6443 unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6444 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6445 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6446 let mask = 0b01111010;
6447 let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6448 assert_eq!(r, 0b00110010)
6449 }
6450
6451 #[simd_test(enable = "avx512f")]
6452 unsafe fn test_mm512_cmp_pd_mask() {
6453 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6454 let b = _mm512_set1_pd(-1.);
6455 let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6456 assert_eq!(m, 0b00000101);
6457 }
6458
6459 #[simd_test(enable = "avx512f")]
6460 unsafe fn test_mm512_mask_cmp_pd_mask() {
6461 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6462 let b = _mm512_set1_pd(-1.);
6463 let mask = 0b01100110;
6464 let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6465 assert_eq!(r, 0b00000100);
6466 }
6467
6468 #[simd_test(enable = "avx512f,avx512vl")]
6469 unsafe fn test_mm256_cmp_pd_mask() {
6470 let a = _mm256_set_pd(0., 1., -1., 13.);
6471 let b = _mm256_set1_pd(1.);
6472 let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6473 assert_eq!(m, 0b00001010);
6474 }
6475
6476 #[simd_test(enable = "avx512f,avx512vl")]
6477 unsafe fn test_mm256_mask_cmp_pd_mask() {
6478 let a = _mm256_set_pd(0., 1., -1., 13.);
6479 let b = _mm256_set1_pd(1.);
6480 let mask = 0b11111111;
6481 let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6482 assert_eq!(r, 0b00001010);
6483 }
6484
6485 #[simd_test(enable = "avx512f,avx512vl")]
6486 unsafe fn test_mm_cmp_pd_mask() {
6487 let a = _mm_set_pd(0., 1.);
6488 let b = _mm_set1_pd(1.);
6489 let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6490 assert_eq!(m, 0b00000010);
6491 }
6492
6493 #[simd_test(enable = "avx512f,avx512vl")]
6494 unsafe fn test_mm_mask_cmp_pd_mask() {
6495 let a = _mm_set_pd(0., 1.);
6496 let b = _mm_set1_pd(1.);
6497 let mask = 0b11111111;
6498 let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6499 assert_eq!(r, 0b00000010);
6500 }
6501
6502 #[simd_test(enable = "avx512f")]
6503 unsafe fn test_mm512_cmp_round_pd_mask() {
6504 #[rustfmt::skip]
6505 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6506 let b = _mm512_set1_pd(-1.);
6507 let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6508 assert_eq!(m, 0b00000101);
6509 }
6510
6511 #[simd_test(enable = "avx512f")]
6512 unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6513 #[rustfmt::skip]
6514 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6515 let b = _mm512_set1_pd(-1.);
6516 let mask = 0b01100110;
6517 let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6518 assert_eq!(r, 0b00000100);
6519 }
6520
6521 #[simd_test(enable = "avx512f")]
6522 unsafe fn test_mm512_cmpord_pd_mask() {
6523 #[rustfmt::skip]
6524 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6525 #[rustfmt::skip]
6526 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6527 let m = _mm512_cmpord_pd_mask(a, b);
6528 assert_eq!(m, 0b00000101);
6529 }
6530
6531 #[simd_test(enable = "avx512f")]
6532 unsafe fn test_mm512_mask_cmpord_pd_mask() {
6533 #[rustfmt::skip]
6534 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6535 #[rustfmt::skip]
6536 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6537 let mask = 0b11000011;
6538 let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6539 assert_eq!(m, 0b00000001);
6540 }
6541
6542 #[simd_test(enable = "avx512f")]
6543 unsafe fn test_mm512_cmpunord_pd_mask() {
6544 #[rustfmt::skip]
6545 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6546 #[rustfmt::skip]
6547 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6548 let m = _mm512_cmpunord_pd_mask(a, b);
6549
6550 assert_eq!(m, 0b11111010);
6551 }
6552
6553 #[simd_test(enable = "avx512f")]
6554 unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6555 #[rustfmt::skip]
6556 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6557 #[rustfmt::skip]
6558 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6559 let mask = 0b00001111;
6560 let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6561 assert_eq!(m, 0b000001010);
6562 }
6563
6564 #[simd_test(enable = "avx512f")]
6565 unsafe fn test_mm512_cmplt_epu64_mask() {
6566 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6567 let b = _mm512_set1_epi64(-1);
6568 let m = _mm512_cmplt_epu64_mask(a, b);
6569 assert_eq!(m, 0b11001111);
6570 }
6571
6572 #[simd_test(enable = "avx512f")]
6573 unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6574 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6575 let b = _mm512_set1_epi64(-1);
6576 let mask = 0b01111010;
6577 let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6578 assert_eq!(r, 0b01001010);
6579 }
6580
6581 #[simd_test(enable = "avx512f,avx512vl")]
6582 unsafe fn test_mm256_cmplt_epu64_mask() {
6583 let a = _mm256_set_epi64x(0, 1, 2, 100);
6584 let b = _mm256_set1_epi64x(2);
6585 let r = _mm256_cmplt_epu64_mask(a, b);
6586 assert_eq!(r, 0b00001100);
6587 }
6588
6589 #[simd_test(enable = "avx512f,avx512vl")]
6590 unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6591 let a = _mm256_set_epi64x(0, 1, 2, 100);
6592 let b = _mm256_set1_epi64x(2);
6593 let mask = 0b11111111;
6594 let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6595 assert_eq!(r, 0b00001100);
6596 }
6597
6598 #[simd_test(enable = "avx512f,avx512vl")]
6599 unsafe fn test_mm_cmplt_epu64_mask() {
6600 let a = _mm_set_epi64x(0, 1);
6601 let b = _mm_set1_epi64x(2);
6602 let r = _mm_cmplt_epu64_mask(a, b);
6603 assert_eq!(r, 0b00000011);
6604 }
6605
6606 #[simd_test(enable = "avx512f,avx512vl")]
6607 unsafe fn test_mm_mask_cmplt_epu64_mask() {
6608 let a = _mm_set_epi64x(0, 1);
6609 let b = _mm_set1_epi64x(2);
6610 let mask = 0b11111111;
6611 let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6612 assert_eq!(r, 0b00000011);
6613 }
6614
6615 #[simd_test(enable = "avx512f")]
6616 unsafe fn test_mm512_cmpgt_epu64_mask() {
6617 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6618 let b = _mm512_set1_epi64(-1);
6619 let m = _mm512_cmpgt_epu64_mask(b, a);
6620 assert_eq!(m, 0b11001111);
6621 }
6622
6623 #[simd_test(enable = "avx512f")]
6624 unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6625 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6626 let b = _mm512_set1_epi64(-1);
6627 let mask = 0b01111010;
6628 let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6629 assert_eq!(r, 0b01001010);
6630 }
6631
6632 #[simd_test(enable = "avx512f,avx512vl")]
6633 unsafe fn test_mm256_cmpgt_epu64_mask() {
6634 let a = _mm256_set_epi64x(0, 1, 2, 3);
6635 let b = _mm256_set1_epi64x(1);
6636 let r = _mm256_cmpgt_epu64_mask(a, b);
6637 assert_eq!(r, 0b00000011);
6638 }
6639
6640 #[simd_test(enable = "avx512f,avx512vl")]
6641 unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6642 let a = _mm256_set_epi64x(0, 1, 2, 3);
6643 let b = _mm256_set1_epi64x(1);
6644 let mask = 0b11111111;
6645 let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6646 assert_eq!(r, 0b00000011);
6647 }
6648
6649 #[simd_test(enable = "avx512f,avx512vl")]
6650 unsafe fn test_mm_cmpgt_epu64_mask() {
6651 let a = _mm_set_epi64x(1, 2);
6652 let b = _mm_set1_epi64x(1);
6653 let r = _mm_cmpgt_epu64_mask(a, b);
6654 assert_eq!(r, 0b00000001);
6655 }
6656
6657 #[simd_test(enable = "avx512f,avx512vl")]
6658 unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6659 let a = _mm_set_epi64x(1, 2);
6660 let b = _mm_set1_epi64x(1);
6661 let mask = 0b11111111;
6662 let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6663 assert_eq!(r, 0b00000001);
6664 }
6665
6666 #[simd_test(enable = "avx512f")]
6667 unsafe fn test_mm512_cmple_epu64_mask() {
6668 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6669 let b = _mm512_set1_epi64(-1);
6670 assert_eq!(
6671 _mm512_cmple_epu64_mask(a, b),
6672 !_mm512_cmpgt_epu64_mask(a, b)
6673 )
6674 }
6675
6676 #[simd_test(enable = "avx512f")]
6677 unsafe fn test_mm512_mask_cmple_epu64_mask() {
6678 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6679 let b = _mm512_set1_epi64(-1);
6680 let mask = 0b01111010;
6681 assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6682 }
6683
6684 #[simd_test(enable = "avx512f,avx512vl")]
6685 unsafe fn test_mm256_cmple_epu64_mask() {
6686 let a = _mm256_set_epi64x(0, 1, 2, 1);
6687 let b = _mm256_set1_epi64x(1);
6688 let r = _mm256_cmple_epu64_mask(a, b);
6689 assert_eq!(r, 0b00001101)
6690 }
6691
6692 #[simd_test(enable = "avx512f,avx512vl")]
6693 unsafe fn test_mm256_mask_cmple_epu64_mask() {
6694 let a = _mm256_set_epi64x(0, 1, 2, 1);
6695 let b = _mm256_set1_epi64x(1);
6696 let mask = 0b11111111;
6697 let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6698 assert_eq!(r, 0b00001101)
6699 }
6700
6701 #[simd_test(enable = "avx512f,avx512vl")]
6702 unsafe fn test_mm_cmple_epu64_mask() {
6703 let a = _mm_set_epi64x(0, 1);
6704 let b = _mm_set1_epi64x(1);
6705 let r = _mm_cmple_epu64_mask(a, b);
6706 assert_eq!(r, 0b00000011)
6707 }
6708
6709 #[simd_test(enable = "avx512f,avx512vl")]
6710 unsafe fn test_mm_mask_cmple_epu64_mask() {
6711 let a = _mm_set_epi64x(0, 1);
6712 let b = _mm_set1_epi64x(1);
6713 let mask = 0b11111111;
6714 let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6715 assert_eq!(r, 0b00000011)
6716 }
6717
6718 #[simd_test(enable = "avx512f")]
6719 unsafe fn test_mm512_cmpge_epu64_mask() {
6720 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6721 let b = _mm512_set1_epi64(-1);
6722 assert_eq!(
6723 _mm512_cmpge_epu64_mask(a, b),
6724 !_mm512_cmplt_epu64_mask(a, b)
6725 );
6726 }
6727
6728 #[simd_test(enable = "avx512f")]
6729 unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6730 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6731 let b = _mm512_set1_epi64(-1);
6732 let mask = 0b11111111;
6733 let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6734 assert_eq!(r, 0b00110000);
6735 }
6736
6737 #[simd_test(enable = "avx512f,avx512vl")]
6738 unsafe fn test_mm256_cmpge_epu64_mask() {
6739 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6740 let b = _mm256_set1_epi64x(1);
6741 let r = _mm256_cmpge_epu64_mask(a, b);
6742 assert_eq!(r, 0b00000111);
6743 }
6744
6745 #[simd_test(enable = "avx512f,avx512vl")]
6746 unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6747 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6748 let b = _mm256_set1_epi64x(1);
6749 let mask = 0b11111111;
6750 let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6751 assert_eq!(r, 0b00000111);
6752 }
6753
6754 #[simd_test(enable = "avx512f,avx512vl")]
6755 unsafe fn test_mm_cmpge_epu64_mask() {
6756 let a = _mm_set_epi64x(0, 1);
6757 let b = _mm_set1_epi64x(1);
6758 let r = _mm_cmpge_epu64_mask(a, b);
6759 assert_eq!(r, 0b00000001);
6760 }
6761
6762 #[simd_test(enable = "avx512f,avx512vl")]
6763 unsafe fn test_mm_mask_cmpge_epu64_mask() {
6764 let a = _mm_set_epi64x(0, 1);
6765 let b = _mm_set1_epi64x(1);
6766 let mask = 0b11111111;
6767 let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6768 assert_eq!(r, 0b00000001);
6769 }
6770
6771 #[simd_test(enable = "avx512f")]
6772 unsafe fn test_mm512_cmpeq_epu64_mask() {
6773 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6774 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6775 let m = _mm512_cmpeq_epu64_mask(b, a);
6776 assert_eq!(m, 0b11001111);
6777 }
6778
6779 #[simd_test(enable = "avx512f")]
6780 unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6781 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6782 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6783 let mask = 0b01111010;
6784 let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6785 assert_eq!(r, 0b01001010);
6786 }
6787
6788 #[simd_test(enable = "avx512f,avx512vl")]
6789 unsafe fn test_mm256_cmpeq_epu64_mask() {
6790 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6791 let b = _mm256_set_epi64x(0, 1, 13, 42);
6792 let m = _mm256_cmpeq_epu64_mask(b, a);
6793 assert_eq!(m, 0b00001100);
6794 }
6795
6796 #[simd_test(enable = "avx512f,avx512vl")]
6797 unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6798 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6799 let b = _mm256_set_epi64x(0, 1, 13, 42);
6800 let mask = 0b11111111;
6801 let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6802 assert_eq!(r, 0b00001100);
6803 }
6804
6805 #[simd_test(enable = "avx512f,avx512vl")]
6806 unsafe fn test_mm_cmpeq_epu64_mask() {
6807 let a = _mm_set_epi64x(0, 1);
6808 let b = _mm_set_epi64x(0, 1);
6809 let m = _mm_cmpeq_epu64_mask(b, a);
6810 assert_eq!(m, 0b00000011);
6811 }
6812
6813 #[simd_test(enable = "avx512f,avx512vl")]
6814 unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6815 let a = _mm_set_epi64x(0, 1);
6816 let b = _mm_set_epi64x(0, 1);
6817 let mask = 0b11111111;
6818 let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6819 assert_eq!(r, 0b00000011);
6820 }
6821
6822 #[simd_test(enable = "avx512f")]
6823 unsafe fn test_mm512_cmpneq_epu64_mask() {
6824 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6825 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6826 let m = _mm512_cmpneq_epu64_mask(b, a);
6827 assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6828 }
6829
6830 #[simd_test(enable = "avx512f")]
6831 unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6832 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6833 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6834 let mask = 0b01111010;
6835 let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6836 assert_eq!(r, 0b00110010);
6837 }
6838
6839 #[simd_test(enable = "avx512f,avx512vl")]
6840 unsafe fn test_mm256_cmpneq_epu64_mask() {
6841 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6842 let b = _mm256_set_epi64x(0, 1, 13, 42);
6843 let r = _mm256_cmpneq_epu64_mask(b, a);
6844 assert_eq!(r, 0b00000011);
6845 }
6846
6847 #[simd_test(enable = "avx512f,avx512vl")]
6848 unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
6849 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6850 let b = _mm256_set_epi64x(0, 1, 13, 42);
6851 let mask = 0b11111111;
6852 let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
6853 assert_eq!(r, 0b00000011);
6854 }
6855
6856 #[simd_test(enable = "avx512f,avx512vl")]
6857 unsafe fn test_mm_cmpneq_epu64_mask() {
6858 let a = _mm_set_epi64x(-1, u64::MAX as i64);
6859 let b = _mm_set_epi64x(13, 42);
6860 let r = _mm_cmpneq_epu64_mask(b, a);
6861 assert_eq!(r, 0b00000011);
6862 }
6863
6864 #[simd_test(enable = "avx512f,avx512vl")]
6865 unsafe fn test_mm_mask_cmpneq_epu64_mask() {
6866 let a = _mm_set_epi64x(-1, u64::MAX as i64);
6867 let b = _mm_set_epi64x(13, 42);
6868 let mask = 0b11111111;
6869 let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
6870 assert_eq!(r, 0b00000011);
6871 }
6872
6873 #[simd_test(enable = "avx512f")]
6874 unsafe fn test_mm512_cmp_epu64_mask() {
6875 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6876 let b = _mm512_set1_epi64(-1);
6877 let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6878 assert_eq!(m, 0b11001111);
6879 }
6880
6881 #[simd_test(enable = "avx512f")]
6882 unsafe fn test_mm512_mask_cmp_epu64_mask() {
6883 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6884 let b = _mm512_set1_epi64(-1);
6885 let mask = 0b01111010;
6886 let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6887 assert_eq!(r, 0b01001010);
6888 }
6889
6890 #[simd_test(enable = "avx512f,avx512vl")]
6891 unsafe fn test_mm256_cmp_epu64_mask() {
6892 let a = _mm256_set_epi64x(0, 1, -1, 100);
6893 let b = _mm256_set1_epi64x(1);
6894 let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6895 assert_eq!(m, 0b00001000);
6896 }
6897
6898 #[simd_test(enable = "avx512f,avx512vl")]
6899 unsafe fn test_mm256_mask_cmp_epu64_mask() {
6900 let a = _mm256_set_epi64x(0, 1, -1, 100);
6901 let b = _mm256_set1_epi64x(1);
6902 let mask = 0b11111111;
6903 let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6904 assert_eq!(r, 0b00001000);
6905 }
6906
6907 #[simd_test(enable = "avx512f,avx512vl")]
6908 unsafe fn test_mm_cmp_epu64_mask() {
6909 let a = _mm_set_epi64x(0, 1);
6910 let b = _mm_set1_epi64x(1);
6911 let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6912 assert_eq!(m, 0b00000010);
6913 }
6914
6915 #[simd_test(enable = "avx512f,avx512vl")]
6916 unsafe fn test_mm_mask_cmp_epu64_mask() {
6917 let a = _mm_set_epi64x(0, 1);
6918 let b = _mm_set1_epi64x(1);
6919 let mask = 0b11111111;
6920 let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6921 assert_eq!(r, 0b00000010);
6922 }
6923
6924 #[simd_test(enable = "avx512f")]
6925 unsafe fn test_mm512_cmplt_epi64_mask() {
6926 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6927 let b = _mm512_set1_epi64(-1);
6928 let m = _mm512_cmplt_epi64_mask(a, b);
6929 assert_eq!(m, 0b00000101);
6930 }
6931
6932 #[simd_test(enable = "avx512f")]
6933 unsafe fn test_mm512_mask_cmplt_epi64_mask() {
6934 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6935 let b = _mm512_set1_epi64(-1);
6936 let mask = 0b01100110;
6937 let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
6938 assert_eq!(r, 0b00000100);
6939 }
6940
6941 #[simd_test(enable = "avx512f,avx512vl")]
6942 unsafe fn test_mm256_cmplt_epi64_mask() {
6943 let a = _mm256_set_epi64x(0, 1, -1, -13);
6944 let b = _mm256_set1_epi64x(-1);
6945 let r = _mm256_cmplt_epi64_mask(a, b);
6946 assert_eq!(r, 0b00000001);
6947 }
6948
6949 #[simd_test(enable = "avx512f,avx512vl")]
6950 unsafe fn test_mm256_mask_cmplt_epi64_mask() {
6951 let a = _mm256_set_epi64x(0, 1, -1, -13);
6952 let b = _mm256_set1_epi64x(-1);
6953 let mask = 0b11111111;
6954 let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
6955 assert_eq!(r, 0b00000001);
6956 }
6957
6958 #[simd_test(enable = "avx512f,avx512vl")]
6959 unsafe fn test_mm_cmplt_epi64_mask() {
6960 let a = _mm_set_epi64x(-1, -13);
6961 let b = _mm_set1_epi64x(-1);
6962 let r = _mm_cmplt_epi64_mask(a, b);
6963 assert_eq!(r, 0b00000001);
6964 }
6965
6966 #[simd_test(enable = "avx512f,avx512vl")]
6967 unsafe fn test_mm_mask_cmplt_epi64_mask() {
6968 let a = _mm_set_epi64x(-1, -13);
6969 let b = _mm_set1_epi64x(-1);
6970 let mask = 0b11111111;
6971 let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
6972 assert_eq!(r, 0b00000001);
6973 }
6974
6975 #[simd_test(enable = "avx512f")]
6976 unsafe fn test_mm512_cmpgt_epi64_mask() {
6977 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6978 let b = _mm512_set1_epi64(-1);
6979 let m = _mm512_cmpgt_epi64_mask(b, a);
6980 assert_eq!(m, 0b00000101);
6981 }
6982
6983 #[simd_test(enable = "avx512f")]
6984 unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
6985 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6986 let b = _mm512_set1_epi64(-1);
6987 let mask = 0b01100110;
6988 let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
6989 assert_eq!(r, 0b00000100);
6990 }
6991
6992 #[simd_test(enable = "avx512f,avx512vl")]
6993 unsafe fn test_mm256_cmpgt_epi64_mask() {
6994 let a = _mm256_set_epi64x(0, 1, -1, 13);
6995 let b = _mm256_set1_epi64x(-1);
6996 let r = _mm256_cmpgt_epi64_mask(a, b);
6997 assert_eq!(r, 0b00001101);
6998 }
6999
7000 #[simd_test(enable = "avx512f,avx512vl")]
7001 unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
7002 let a = _mm256_set_epi64x(0, 1, -1, 13);
7003 let b = _mm256_set1_epi64x(-1);
7004 let mask = 0b11111111;
7005 let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7006 assert_eq!(r, 0b00001101);
7007 }
7008
7009 #[simd_test(enable = "avx512f,avx512vl")]
7010 unsafe fn test_mm_cmpgt_epi64_mask() {
7011 let a = _mm_set_epi64x(0, -1);
7012 let b = _mm_set1_epi64x(-1);
7013 let r = _mm_cmpgt_epi64_mask(a, b);
7014 assert_eq!(r, 0b00000010);
7015 }
7016
7017 #[simd_test(enable = "avx512f,avx512vl")]
7018 unsafe fn test_mm_mask_cmpgt_epi64_mask() {
7019 let a = _mm_set_epi64x(0, -1);
7020 let b = _mm_set1_epi64x(-1);
7021 let mask = 0b11111111;
7022 let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7023 assert_eq!(r, 0b00000010);
7024 }
7025
7026 #[simd_test(enable = "avx512f")]
7027 unsafe fn test_mm512_cmple_epi64_mask() {
7028 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7029 let b = _mm512_set1_epi64(-1);
7030 assert_eq!(
7031 _mm512_cmple_epi64_mask(a, b),
7032 !_mm512_cmpgt_epi64_mask(a, b)
7033 )
7034 }
7035
7036 #[simd_test(enable = "avx512f")]
7037 unsafe fn test_mm512_mask_cmple_epi64_mask() {
7038 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7039 let b = _mm512_set1_epi64(-1);
7040 let mask = 0b01111010;
7041 assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7042 }
7043
7044 #[simd_test(enable = "avx512f,avx512vl")]
7045 unsafe fn test_mm256_cmple_epi64_mask() {
7046 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7047 let b = _mm256_set1_epi64x(-1);
7048 let r = _mm256_cmple_epi64_mask(a, b);
7049 assert_eq!(r, 0b00000010)
7050 }
7051
7052 #[simd_test(enable = "avx512f,avx512vl")]
7053 unsafe fn test_mm256_mask_cmple_epi64_mask() {
7054 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7055 let b = _mm256_set1_epi64x(-1);
7056 let mask = 0b11111111;
7057 let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7058 assert_eq!(r, 0b00000010)
7059 }
7060
7061 #[simd_test(enable = "avx512f,avx512vl")]
7062 unsafe fn test_mm_cmple_epi64_mask() {
7063 let a = _mm_set_epi64x(0, 1);
7064 let b = _mm_set1_epi64x(1);
7065 let r = _mm_cmple_epi64_mask(a, b);
7066 assert_eq!(r, 0b00000011)
7067 }
7068
7069 #[simd_test(enable = "avx512f,avx512vl")]
7070 unsafe fn test_mm_mask_cmple_epi64_mask() {
7071 let a = _mm_set_epi64x(0, 1);
7072 let b = _mm_set1_epi64x(1);
7073 let mask = 0b11111111;
7074 let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7075 assert_eq!(r, 0b00000011)
7076 }
7077
7078 #[simd_test(enable = "avx512f")]
7079 unsafe fn test_mm512_cmpge_epi64_mask() {
7080 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7081 let b = _mm512_set1_epi64(-1);
7082 assert_eq!(
7083 _mm512_cmpge_epi64_mask(a, b),
7084 !_mm512_cmplt_epi64_mask(a, b)
7085 )
7086 }
7087
7088 #[simd_test(enable = "avx512f")]
7089 unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7090 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7091 let b = _mm512_set1_epi64(-1);
7092 let mask = 0b11111111;
7093 let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7094 assert_eq!(r, 0b11111010);
7095 }
7096
7097 #[simd_test(enable = "avx512f,avx512vl")]
7098 unsafe fn test_mm256_cmpge_epi64_mask() {
7099 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7100 let b = _mm256_set1_epi64x(-1);
7101 let r = _mm256_cmpge_epi64_mask(a, b);
7102 assert_eq!(r, 0b00001111);
7103 }
7104
7105 #[simd_test(enable = "avx512f,avx512vl")]
7106 unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7107 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7108 let b = _mm256_set1_epi64x(-1);
7109 let mask = 0b11111111;
7110 let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7111 assert_eq!(r, 0b00001111);
7112 }
7113
7114 #[simd_test(enable = "avx512f,avx512vl")]
7115 unsafe fn test_mm_cmpge_epi64_mask() {
7116 let a = _mm_set_epi64x(0, 1);
7117 let b = _mm_set1_epi64x(-1);
7118 let r = _mm_cmpge_epi64_mask(a, b);
7119 assert_eq!(r, 0b00000011);
7120 }
7121
7122 #[simd_test(enable = "avx512f,avx512vl")]
7123 unsafe fn test_mm_mask_cmpge_epi64_mask() {
7124 let a = _mm_set_epi64x(0, 1);
7125 let b = _mm_set1_epi64x(-1);
7126 let mask = 0b11111111;
7127 let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7128 assert_eq!(r, 0b00000011);
7129 }
7130
7131 #[simd_test(enable = "avx512f")]
7132 unsafe fn test_mm512_cmpeq_epi64_mask() {
7133 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7134 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7135 let m = _mm512_cmpeq_epi64_mask(b, a);
7136 assert_eq!(m, 0b11001111);
7137 }
7138
7139 #[simd_test(enable = "avx512f")]
7140 unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7141 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7142 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7143 let mask = 0b01111010;
7144 let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7145 assert_eq!(r, 0b01001010);
7146 }
7147
7148 #[simd_test(enable = "avx512f,avx512vl")]
7149 unsafe fn test_mm256_cmpeq_epi64_mask() {
7150 let a = _mm256_set_epi64x(0, 1, -1, 13);
7151 let b = _mm256_set_epi64x(0, 1, 13, 42);
7152 let m = _mm256_cmpeq_epi64_mask(b, a);
7153 assert_eq!(m, 0b00001100);
7154 }
7155
7156 #[simd_test(enable = "avx512f,avx512vl")]
7157 unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7158 let a = _mm256_set_epi64x(0, 1, -1, 13);
7159 let b = _mm256_set_epi64x(0, 1, 13, 42);
7160 let mask = 0b11111111;
7161 let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7162 assert_eq!(r, 0b00001100);
7163 }
7164
7165 #[simd_test(enable = "avx512f,avx512vl")]
7166 unsafe fn test_mm_cmpeq_epi64_mask() {
7167 let a = _mm_set_epi64x(0, 1);
7168 let b = _mm_set_epi64x(0, 1);
7169 let m = _mm_cmpeq_epi64_mask(b, a);
7170 assert_eq!(m, 0b00000011);
7171 }
7172
7173 #[simd_test(enable = "avx512f,avx512vl")]
7174 unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7175 let a = _mm_set_epi64x(0, 1);
7176 let b = _mm_set_epi64x(0, 1);
7177 let mask = 0b11111111;
7178 let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7179 assert_eq!(r, 0b00000011);
7180 }
7181
7182 #[simd_test(enable = "avx512f")]
7183 unsafe fn test_mm512_set_epi64() {
7184 let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7185 assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7186 }
7187
7188 #[simd_test(enable = "avx512f")]
7189 unsafe fn test_mm512_setr_epi64() {
7190 let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7191 assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7192 }
7193
7194 unsafe fn test_mm512_cmpneq_epi64_mask() {
7195 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7196 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7197 let m = _mm512_cmpneq_epi64_mask(b, a);
7198 assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7199 }
7200
7201 #[simd_test(enable = "avx512f")]
7202 unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7203 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7204 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7205 let mask = 0b01111010;
7206 let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7207 assert_eq!(r, 0b00110010)
7208 }
7209
7210 #[simd_test(enable = "avx512f,avx512vl")]
7211 unsafe fn test_mm256_cmpneq_epi64_mask() {
7212 let a = _mm256_set_epi64x(0, 1, -1, 13);
7213 let b = _mm256_set_epi64x(0, 1, 13, 42);
7214 let r = _mm256_cmpneq_epi64_mask(b, a);
7215 assert_eq!(r, 0b00000011)
7216 }
7217
7218 #[simd_test(enable = "avx512f,avx512vl")]
7219 unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7220 let a = _mm256_set_epi64x(0, 1, -1, 13);
7221 let b = _mm256_set_epi64x(0, 1, 13, 42);
7222 let mask = 0b11111111;
7223 let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7224 assert_eq!(r, 0b00000011)
7225 }
7226
7227 #[simd_test(enable = "avx512f,avx512vl")]
7228 unsafe fn test_mm_cmpneq_epi64_mask() {
7229 let a = _mm_set_epi64x(-1, 13);
7230 let b = _mm_set_epi64x(13, 42);
7231 let r = _mm_cmpneq_epi64_mask(b, a);
7232 assert_eq!(r, 0b00000011)
7233 }
7234
7235 #[simd_test(enable = "avx512f,avx512vl")]
7236 unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7237 let a = _mm_set_epi64x(-1, 13);
7238 let b = _mm_set_epi64x(13, 42);
7239 let mask = 0b11111111;
7240 let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7241 assert_eq!(r, 0b00000011)
7242 }
7243
7244 #[simd_test(enable = "avx512f")]
7245 unsafe fn test_mm512_cmp_epi64_mask() {
7246 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7247 let b = _mm512_set1_epi64(-1);
7248 let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7249 assert_eq!(m, 0b00000101);
7250 }
7251
7252 #[simd_test(enable = "avx512f")]
7253 unsafe fn test_mm512_mask_cmp_epi64_mask() {
7254 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7255 let b = _mm512_set1_epi64(-1);
7256 let mask = 0b01100110;
7257 let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7258 assert_eq!(r, 0b00000100);
7259 }
7260
7261 #[simd_test(enable = "avx512f,avx512vl")]
7262 unsafe fn test_mm256_cmp_epi64_mask() {
7263 let a = _mm256_set_epi64x(0, 1, -1, 13);
7264 let b = _mm256_set1_epi64x(1);
7265 let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7266 assert_eq!(m, 0b00001010);
7267 }
7268
7269 #[simd_test(enable = "avx512f,avx512vl")]
7270 unsafe fn test_mm256_mask_cmp_epi64_mask() {
7271 let a = _mm256_set_epi64x(0, 1, -1, 13);
7272 let b = _mm256_set1_epi64x(1);
7273 let mask = 0b11111111;
7274 let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7275 assert_eq!(r, 0b00001010);
7276 }
7277
7278 #[simd_test(enable = "avx512f,avx512vl")]
7279 unsafe fn test_mm_cmp_epi64_mask() {
7280 let a = _mm_set_epi64x(0, 1);
7281 let b = _mm_set1_epi64x(1);
7282 let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7283 assert_eq!(m, 0b00000010);
7284 }
7285
7286 #[simd_test(enable = "avx512f,avx512vl")]
7287 unsafe fn test_mm_mask_cmp_epi64_mask() {
7288 let a = _mm_set_epi64x(0, 1);
7289 let b = _mm_set1_epi64x(1);
7290 let mask = 0b11111111;
7291 let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7292 assert_eq!(r, 0b00000010);
7293 }
7294
7295 #[simd_test(enable = "avx512f")]
7296 unsafe fn test_mm512_i32gather_pd() {
7297 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7298 // A multiplier of 8 is word-addressing
7299 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7300 let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr() as *const u8);
7301 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7302 }
7303
7304 #[simd_test(enable = "avx512f")]
7305 unsafe fn test_mm512_mask_i32gather_pd() {
7306 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7307 let src = _mm512_set1_pd(2.);
7308 let mask = 0b10101010;
7309 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7310 // A multiplier of 8 is word-addressing
7311 let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7312 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7313 }
7314
7315 #[simd_test(enable = "avx512f")]
7316 unsafe fn test_mm512_i64gather_pd() {
7317 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7318 // A multiplier of 8 is word-addressing
7319 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7320 let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr() as *const u8);
7321 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7322 }
7323
7324 #[simd_test(enable = "avx512f")]
7325 unsafe fn test_mm512_mask_i64gather_pd() {
7326 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7327 let src = _mm512_set1_pd(2.);
7328 let mask = 0b10101010;
7329 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7330 // A multiplier of 8 is word-addressing
7331 let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7332 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7333 }
7334
7335 #[simd_test(enable = "avx512f")]
7336 unsafe fn test_mm512_i64gather_ps() {
7337 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7338 // A multiplier of 4 is word-addressing
7339 #[rustfmt::skip]
7340 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7341 let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr() as *const u8);
7342 assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7343 }
7344
7345 #[simd_test(enable = "avx512f")]
7346 unsafe fn test_mm512_mask_i64gather_ps() {
7347 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7348 let src = _mm256_set1_ps(2.);
7349 let mask = 0b10101010;
7350 #[rustfmt::skip]
7351 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7352 // A multiplier of 4 is word-addressing
7353 let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr() as *const u8);
7354 assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7355 }
7356
7357 #[simd_test(enable = "avx512f")]
7358 unsafe fn test_mm512_i32gather_epi64() {
7359 let mut arr = [0i64; 128];
7360 for i in 0..128i64 {
7361 arr[i as usize] = i;
7362 }
7363 // A multiplier of 8 is word-addressing
7364 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7365 let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7366 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7367 }
7368
7369 #[simd_test(enable = "avx512f")]
7370 unsafe fn test_mm512_mask_i32gather_epi64() {
7371 let mut arr = [0i64; 128];
7372 for i in 0..128i64 {
7373 arr[i as usize] = i;
7374 }
7375 let src = _mm512_set1_epi64(2);
7376 let mask = 0b10101010;
7377 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7378 // A multiplier of 8 is word-addressing
7379 let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7380 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7381 }
7382
7383 #[simd_test(enable = "avx512f")]
7384 unsafe fn test_mm512_i64gather_epi64() {
7385 let mut arr = [0i64; 128];
7386 for i in 0..128i64 {
7387 arr[i as usize] = i;
7388 }
7389 // A multiplier of 8 is word-addressing
7390 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7391 let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7392 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7393 }
7394
7395 #[simd_test(enable = "avx512f")]
7396 unsafe fn test_mm512_mask_i64gather_epi64() {
7397 let mut arr = [0i64; 128];
7398 for i in 0..128i64 {
7399 arr[i as usize] = i;
7400 }
7401 let src = _mm512_set1_epi64(2);
7402 let mask = 0b10101010;
7403 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7404 // A multiplier of 8 is word-addressing
7405 let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7406 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7407 }
7408
7409 #[simd_test(enable = "avx512f")]
7410 unsafe fn test_mm512_i64gather_epi32() {
7411 let mut arr = [0i64; 128];
7412 for i in 0..128i64 {
7413 arr[i as usize] = i;
7414 }
7415 // A multiplier of 8 is word-addressing
7416 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7417 let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const u8);
7418 assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7419 }
7420
7421 #[simd_test(enable = "avx512f")]
7422 unsafe fn test_mm512_mask_i64gather_epi32() {
7423 let mut arr = [0i64; 128];
7424 for i in 0..128i64 {
7425 arr[i as usize] = i;
7426 }
7427 let src = _mm256_set1_epi32(2);
7428 let mask = 0b10101010;
7429 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7430 // A multiplier of 8 is word-addressing
7431 let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const u8);
7432 assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7433 }
7434
7435 #[simd_test(enable = "avx512f")]
7436 unsafe fn test_mm512_i32scatter_pd() {
7437 let mut arr = [0f64; 128];
7438 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7439 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7440 // A multiplier of 8 is word-addressing
7441 _mm512_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7442 let mut expected = [0f64; 128];
7443 for i in 0..8 {
7444 expected[i * 16] = (i + 1) as f64;
7445 }
7446 assert_eq!(&arr[..], &expected[..],);
7447 }
7448
7449 #[simd_test(enable = "avx512f")]
7450 unsafe fn test_mm512_mask_i32scatter_pd() {
7451 let mut arr = [0f64; 128];
7452 let mask = 0b10101010;
7453 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7454 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7455 // A multiplier of 8 is word-addressing
7456 _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7457 let mut expected = [0f64; 128];
7458 for i in 0..4 {
7459 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7460 }
7461 assert_eq!(&arr[..], &expected[..],);
7462 }
7463
7464 #[simd_test(enable = "avx512f")]
7465 unsafe fn test_mm512_i64scatter_pd() {
7466 let mut arr = [0f64; 128];
7467 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7468 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7469 // A multiplier of 8 is word-addressing
7470 _mm512_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7471 let mut expected = [0f64; 128];
7472 for i in 0..8 {
7473 expected[i * 16] = (i + 1) as f64;
7474 }
7475 assert_eq!(&arr[..], &expected[..],);
7476 }
7477
7478 #[simd_test(enable = "avx512f")]
7479 unsafe fn test_mm512_mask_i64scatter_pd() {
7480 let mut arr = [0f64; 128];
7481 let mask = 0b10101010;
7482 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7483 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7484 // A multiplier of 8 is word-addressing
7485 _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7486 let mut expected = [0f64; 128];
7487 for i in 0..4 {
7488 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7489 }
7490 assert_eq!(&arr[..], &expected[..],);
7491 }
7492
7493 #[simd_test(enable = "avx512f")]
7494 unsafe fn test_mm512_i64scatter_ps() {
7495 let mut arr = [0f32; 128];
7496 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7497 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7498 // A multiplier of 4 is word-addressing
7499 _mm512_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7500 let mut expected = [0f32; 128];
7501 for i in 0..8 {
7502 expected[i * 16] = (i + 1) as f32;
7503 }
7504 assert_eq!(&arr[..], &expected[..],);
7505 }
7506
7507 #[simd_test(enable = "avx512f")]
7508 unsafe fn test_mm512_mask_i64scatter_ps() {
7509 let mut arr = [0f32; 128];
7510 let mask = 0b10101010;
7511 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7512 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7513 // A multiplier of 4 is word-addressing
7514 _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7515 let mut expected = [0f32; 128];
7516 for i in 0..4 {
7517 expected[i * 32 + 16] = 2. * (i + 1) as f32;
7518 }
7519 assert_eq!(&arr[..], &expected[..],);
7520 }
7521
7522 #[simd_test(enable = "avx512f")]
7523 unsafe fn test_mm512_i32scatter_epi64() {
7524 let mut arr = [0i64; 128];
7525 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7526 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7527 // A multiplier of 8 is word-addressing
7528 _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7529 let mut expected = [0i64; 128];
7530 for i in 0..8 {
7531 expected[i * 16] = (i + 1) as i64;
7532 }
7533 assert_eq!(&arr[..], &expected[..],);
7534 }
7535
7536 #[simd_test(enable = "avx512f")]
7537 unsafe fn test_mm512_mask_i32scatter_epi64() {
7538 let mut arr = [0i64; 128];
7539 let mask = 0b10101010;
7540 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7541 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7542 // A multiplier of 8 is word-addressing
7543 _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7544 let mut expected = [0i64; 128];
7545 for i in 0..4 {
7546 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7547 }
7548 assert_eq!(&arr[..], &expected[..],);
7549 }
7550
7551 #[simd_test(enable = "avx512f,avx512vl")]
7552 unsafe fn test_mm256_i32scatter_epi64() {
7553 let mut arr = [0i64; 64];
7554 let index = _mm_setr_epi32(0, 16, 32, 48);
7555 let src = _mm256_setr_epi64x(1, 2, 3, 4);
7556 // A multiplier of 8 is word-addressing
7557 _mm256_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7558 let mut expected = [0i64; 64];
7559 for i in 0..4 {
7560 expected[i * 16] = (i + 1) as i64;
7561 }
7562 assert_eq!(&arr[..], &expected[..],);
7563 }
7564
7565 #[simd_test(enable = "avx512f")]
7566 unsafe fn test_mm512_i64scatter_epi64() {
7567 let mut arr = [0i64; 128];
7568 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7569 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7570 // A multiplier of 8 is word-addressing
7571 _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7572 let mut expected = [0i64; 128];
7573 for i in 0..8 {
7574 expected[i * 16] = (i + 1) as i64;
7575 }
7576 assert_eq!(&arr[..], &expected[..],);
7577 }
7578
7579 #[simd_test(enable = "avx512f")]
7580 unsafe fn test_mm512_mask_i64scatter_epi64() {
7581 let mut arr = [0i64; 128];
7582 let mask = 0b10101010;
7583 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7584 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7585 // A multiplier of 8 is word-addressing
7586 _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7587 let mut expected = [0i64; 128];
7588 for i in 0..4 {
7589 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7590 }
7591 assert_eq!(&arr[..], &expected[..],);
7592 }
7593
7594 #[simd_test(enable = "avx512f")]
7595 unsafe fn test_mm512_i64scatter_epi32() {
7596 let mut arr = [0i32; 128];
7597 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7598 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7599 // A multiplier of 4 is word-addressing
7600 _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7601 let mut expected = [0i32; 128];
7602 for i in 0..8 {
7603 expected[i * 16] = (i + 1) as i32;
7604 }
7605 assert_eq!(&arr[..], &expected[..],);
7606 }
7607
7608 #[simd_test(enable = "avx512f")]
7609 unsafe fn test_mm512_mask_i64scatter_epi32() {
7610 let mut arr = [0i32; 128];
7611 let mask = 0b10101010;
7612 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7613 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7614 // A multiplier of 4 is word-addressing
7615 _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7616 let mut expected = [0i32; 128];
7617 for i in 0..4 {
7618 expected[i * 32 + 16] = 2 * (i + 1) as i32;
7619 }
7620 assert_eq!(&arr[..], &expected[..],);
7621 }
7622
7623 #[simd_test(enable = "avx512f")]
7624 unsafe fn test_mm512_rol_epi64() {
7625 #[rustfmt::skip]
7626 let a = _mm512_set_epi64(
7627 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7628 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7629 );
7630 let r = _mm512_rol_epi64::<1>(a);
7631 #[rustfmt::skip]
7632 let e = _mm512_set_epi64(
7633 1 << 0, 1 << 33, 1 << 33, 1 << 33,
7634 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7635 );
7636 assert_eq_m512i(r, e);
7637 }
7638
7639 #[simd_test(enable = "avx512f")]
7640 unsafe fn test_mm512_mask_rol_epi64() {
7641 #[rustfmt::skip]
7642 let a = _mm512_set_epi64(
7643 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7644 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7645 );
7646 let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
7647 assert_eq_m512i(r, a);
7648 let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
7649 #[rustfmt::skip]
7650 let e = _mm512_set_epi64(
7651 1 << 0, 1 << 33, 1 << 33, 1 << 33,
7652 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7653 );
7654 assert_eq_m512i(r, e);
7655 }
7656
7657 #[simd_test(enable = "avx512f")]
7658 unsafe fn test_mm512_maskz_rol_epi64() {
7659 #[rustfmt::skip]
7660 let a = _mm512_set_epi64(
7661 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7662 1 << 32, 1 << 32, 1 << 32, 1 << 63,
7663 );
7664 let r = _mm512_maskz_rol_epi64::<1>(0, a);
7665 assert_eq_m512i(r, _mm512_setzero_si512());
7666 let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
7667 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
7668 assert_eq_m512i(r, e);
7669 }
7670
7671 #[simd_test(enable = "avx512f,avx512vl")]
7672 unsafe fn test_mm256_rol_epi64() {
7673 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7674 let r = _mm256_rol_epi64::<1>(a);
7675 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
7676 assert_eq_m256i(r, e);
7677 }
7678
7679 #[simd_test(enable = "avx512f,avx512vl")]
7680 unsafe fn test_mm256_mask_rol_epi64() {
7681 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7682 let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
7683 assert_eq_m256i(r, a);
7684 let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
7685 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
7686 assert_eq_m256i(r, e);
7687 }
7688
7689 #[simd_test(enable = "avx512f,avx512vl")]
7690 unsafe fn test_mm256_maskz_rol_epi64() {
7691 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7692 let r = _mm256_maskz_rol_epi64::<1>(0, a);
7693 assert_eq_m256i(r, _mm256_setzero_si256());
7694 let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
7695 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
7696 assert_eq_m256i(r, e);
7697 }
7698
7699 #[simd_test(enable = "avx512f,avx512vl")]
7700 unsafe fn test_mm_rol_epi64() {
7701 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7702 let r = _mm_rol_epi64::<1>(a);
7703 let e = _mm_set_epi64x(1 << 0, 1 << 33);
7704 assert_eq_m128i(r, e);
7705 }
7706
7707 #[simd_test(enable = "avx512f,avx512vl")]
7708 unsafe fn test_mm_mask_rol_epi64() {
7709 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7710 let r = _mm_mask_rol_epi64::<1>(a, 0, a);
7711 assert_eq_m128i(r, a);
7712 let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
7713 let e = _mm_set_epi64x(1 << 0, 1 << 33);
7714 assert_eq_m128i(r, e);
7715 }
7716
7717 #[simd_test(enable = "avx512f,avx512vl")]
7718 unsafe fn test_mm_maskz_rol_epi64() {
7719 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7720 let r = _mm_maskz_rol_epi64::<1>(0, a);
7721 assert_eq_m128i(r, _mm_setzero_si128());
7722 let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
7723 let e = _mm_set_epi64x(1 << 0, 1 << 33);
7724 assert_eq_m128i(r, e);
7725 }
7726
7727 #[simd_test(enable = "avx512f")]
7728 unsafe fn test_mm512_ror_epi64() {
7729 #[rustfmt::skip]
7730 let a = _mm512_set_epi64(
7731 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7732 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7733 );
7734 let r = _mm512_ror_epi64::<1>(a);
7735 #[rustfmt::skip]
7736 let e = _mm512_set_epi64(
7737 1 << 63, 1 << 31, 1 << 31, 1 << 31,
7738 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7739 );
7740 assert_eq_m512i(r, e);
7741 }
7742
7743 #[simd_test(enable = "avx512f")]
7744 unsafe fn test_mm512_mask_ror_epi64() {
7745 #[rustfmt::skip]
7746 let a = _mm512_set_epi64(
7747 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7748 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7749 );
7750 let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
7751 assert_eq_m512i(r, a);
7752 let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
7753 #[rustfmt::skip]
7754 let e = _mm512_set_epi64(
7755 1 << 63, 1 << 31, 1 << 31, 1 << 31,
7756 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7757 );
7758 assert_eq_m512i(r, e);
7759 }
7760
7761 #[simd_test(enable = "avx512f")]
7762 unsafe fn test_mm512_maskz_ror_epi64() {
7763 #[rustfmt::skip]
7764 let a = _mm512_set_epi64(
7765 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7766 1 << 32, 1 << 32, 1 << 32, 1 << 0,
7767 );
7768 let r = _mm512_maskz_ror_epi64::<1>(0, a);
7769 assert_eq_m512i(r, _mm512_setzero_si512());
7770 let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
7771 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
7772 assert_eq_m512i(r, e);
7773 }
7774
7775 #[simd_test(enable = "avx512f,avx512vl")]
7776 unsafe fn test_mm256_ror_epi64() {
7777 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
7778 let r = _mm256_ror_epi64::<1>(a);
7779 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
7780 assert_eq_m256i(r, e);
7781 }
7782
7783 #[simd_test(enable = "avx512f,avx512vl")]
7784 unsafe fn test_mm256_mask_ror_epi64() {
7785 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
7786 let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
7787 assert_eq_m256i(r, a);
7788 let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
7789 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
7790 assert_eq_m256i(r, e);
7791 }
7792
7793 #[simd_test(enable = "avx512f,avx512vl")]
7794 unsafe fn test_mm256_maskz_ror_epi64() {
7795 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
7796 let r = _mm256_maskz_ror_epi64::<1>(0, a);
7797 assert_eq_m256i(r, _mm256_setzero_si256());
7798 let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
7799 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
7800 assert_eq_m256i(r, e);
7801 }
7802
7803 #[simd_test(enable = "avx512f,avx512vl")]
7804 unsafe fn test_mm_ror_epi64() {
7805 let a = _mm_set_epi64x(1 << 0, 1 << 32);
7806 let r = _mm_ror_epi64::<1>(a);
7807 let e = _mm_set_epi64x(1 << 63, 1 << 31);
7808 assert_eq_m128i(r, e);
7809 }
7810
7811 #[simd_test(enable = "avx512f,avx512vl")]
7812 unsafe fn test_mm_mask_ror_epi64() {
7813 let a = _mm_set_epi64x(1 << 0, 1 << 32);
7814 let r = _mm_mask_ror_epi64::<1>(a, 0, a);
7815 assert_eq_m128i(r, a);
7816 let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
7817 let e = _mm_set_epi64x(1 << 63, 1 << 31);
7818 assert_eq_m128i(r, e);
7819 }
7820
7821 #[simd_test(enable = "avx512f,avx512vl")]
7822 unsafe fn test_mm_maskz_ror_epi64() {
7823 let a = _mm_set_epi64x(1 << 0, 1 << 32);
7824 let r = _mm_maskz_ror_epi64::<1>(0, a);
7825 assert_eq_m128i(r, _mm_setzero_si128());
7826 let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
7827 let e = _mm_set_epi64x(1 << 63, 1 << 31);
7828 assert_eq_m128i(r, e);
7829 }
7830
7831 #[simd_test(enable = "avx512f")]
7832 unsafe fn test_mm512_slli_epi64() {
7833 #[rustfmt::skip]
7834 let a = _mm512_set_epi64(
7835 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7836 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7837 );
7838 let r = _mm512_slli_epi64::<1>(a);
7839 #[rustfmt::skip]
7840 let e = _mm512_set_epi64(
7841 0, 1 << 33, 1 << 33, 1 << 33,
7842 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7843 );
7844 assert_eq_m512i(r, e);
7845 }
7846
7847 #[simd_test(enable = "avx512f")]
7848 unsafe fn test_mm512_mask_slli_epi64() {
7849 #[rustfmt::skip]
7850 let a = _mm512_set_epi64(
7851 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7852 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7853 );
7854 let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
7855 assert_eq_m512i(r, a);
7856 let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
7857 #[rustfmt::skip]
7858 let e = _mm512_set_epi64(
7859 0, 1 << 33, 1 << 33, 1 << 33,
7860 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7861 );
7862 assert_eq_m512i(r, e);
7863 }
7864
7865 #[simd_test(enable = "avx512f")]
7866 unsafe fn test_mm512_maskz_slli_epi64() {
7867 #[rustfmt::skip]
7868 let a = _mm512_set_epi64(
7869 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7870 1 << 32, 1 << 32, 1 << 32, 1 << 63,
7871 );
7872 let r = _mm512_maskz_slli_epi64::<1>(0, a);
7873 assert_eq_m512i(r, _mm512_setzero_si512());
7874 let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
7875 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
7876 assert_eq_m512i(r, e);
7877 }
7878
7879 #[simd_test(enable = "avx512f,avx512vl")]
7880 unsafe fn test_mm256_mask_slli_epi64() {
7881 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7882 let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
7883 assert_eq_m256i(r, a);
7884 let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
7885 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
7886 assert_eq_m256i(r, e);
7887 }
7888
7889 #[simd_test(enable = "avx512f,avx512vl")]
7890 unsafe fn test_mm256_maskz_slli_epi64() {
7891 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7892 let r = _mm256_maskz_slli_epi64::<1>(0, a);
7893 assert_eq_m256i(r, _mm256_setzero_si256());
7894 let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
7895 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
7896 assert_eq_m256i(r, e);
7897 }
7898
7899 #[simd_test(enable = "avx512f,avx512vl")]
7900 unsafe fn test_mm_mask_slli_epi64() {
7901 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7902 let r = _mm_mask_slli_epi64::<1>(a, 0, a);
7903 assert_eq_m128i(r, a);
7904 let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
7905 let e = _mm_set_epi64x(0, 1 << 33);
7906 assert_eq_m128i(r, e);
7907 }
7908
7909 #[simd_test(enable = "avx512f,avx512vl")]
7910 unsafe fn test_mm_maskz_slli_epi64() {
7911 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7912 let r = _mm_maskz_slli_epi64::<1>(0, a);
7913 assert_eq_m128i(r, _mm_setzero_si128());
7914 let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
7915 let e = _mm_set_epi64x(0, 1 << 33);
7916 assert_eq_m128i(r, e);
7917 }
7918
7919 #[simd_test(enable = "avx512f")]
7920 unsafe fn test_mm512_srli_epi64() {
7921 #[rustfmt::skip]
7922 let a = _mm512_set_epi64(
7923 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7924 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7925 );
7926 let r = _mm512_srli_epi64::<1>(a);
7927 #[rustfmt::skip]
7928 let e = _mm512_set_epi64(
7929 0, 1 << 31, 1 << 31, 1 << 31,
7930 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7931 );
7932 assert_eq_m512i(r, e);
7933 }
7934
7935 #[simd_test(enable = "avx512f")]
7936 unsafe fn test_mm512_mask_srli_epi64() {
7937 #[rustfmt::skip]
7938 let a = _mm512_set_epi64(
7939 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7940 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7941 );
7942 let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
7943 assert_eq_m512i(r, a);
7944 let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
7945 #[rustfmt::skip]
7946 let e = _mm512_set_epi64(
7947 0, 1 << 31, 1 << 31, 1 << 31,
7948 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7949 );
7950 assert_eq_m512i(r, e);
7951 }
7952
7953 #[simd_test(enable = "avx512f")]
7954 unsafe fn test_mm512_maskz_srli_epi64() {
7955 #[rustfmt::skip]
7956 let a = _mm512_set_epi64(
7957 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7958 1 << 32, 1 << 32, 1 << 32, 1 << 0,
7959 );
7960 let r = _mm512_maskz_srli_epi64::<1>(0, a);
7961 assert_eq_m512i(r, _mm512_setzero_si512());
7962 let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
7963 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
7964 assert_eq_m512i(r, e);
7965 }
7966
7967 #[simd_test(enable = "avx512f,avx512vl")]
7968 unsafe fn test_mm256_mask_srli_epi64() {
7969 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
7970 let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
7971 assert_eq_m256i(r, a);
7972 let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
7973 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
7974 assert_eq_m256i(r, e);
7975 }
7976
7977 #[simd_test(enable = "avx512f,avx512vl")]
7978 unsafe fn test_mm256_maskz_srli_epi64() {
7979 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
7980 let r = _mm256_maskz_srli_epi64::<1>(0, a);
7981 assert_eq_m256i(r, _mm256_setzero_si256());
7982 let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
7983 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
7984 assert_eq_m256i(r, e);
7985 }
7986
7987 #[simd_test(enable = "avx512f,avx512vl")]
7988 unsafe fn test_mm_mask_srli_epi64() {
7989 let a = _mm_set_epi64x(1 << 5, 0);
7990 let r = _mm_mask_srli_epi64::<1>(a, 0, a);
7991 assert_eq_m128i(r, a);
7992 let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
7993 let e = _mm_set_epi64x(1 << 4, 0);
7994 assert_eq_m128i(r, e);
7995 }
7996
7997 #[simd_test(enable = "avx512f,avx512vl")]
7998 unsafe fn test_mm_maskz_srli_epi64() {
7999 let a = _mm_set_epi64x(1 << 5, 0);
8000 let r = _mm_maskz_srli_epi64::<1>(0, a);
8001 assert_eq_m128i(r, _mm_setzero_si128());
8002 let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8003 let e = _mm_set_epi64x(1 << 4, 0);
8004 assert_eq_m128i(r, e);
8005 }
8006
8007 #[simd_test(enable = "avx512f")]
8008 unsafe fn test_mm512_rolv_epi64() {
8009 #[rustfmt::skip]
8010 let a = _mm512_set_epi64(
8011 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8012 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8013 );
8014 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8015 let r = _mm512_rolv_epi64(a, b);
8016 #[rustfmt::skip]
8017 let e = _mm512_set_epi64(
8018 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8019 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8020 );
8021 assert_eq_m512i(r, e);
8022 }
8023
8024 #[simd_test(enable = "avx512f")]
8025 unsafe fn test_mm512_mask_rolv_epi64() {
8026 #[rustfmt::skip]
8027 let a = _mm512_set_epi64(
8028 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8029 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8030 );
8031 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8032 let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8033 assert_eq_m512i(r, a);
8034 let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8035 #[rustfmt::skip]
8036 let e = _mm512_set_epi64(
8037 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8038 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8039 );
8040 assert_eq_m512i(r, e);
8041 }
8042
8043 #[simd_test(enable = "avx512f")]
8044 unsafe fn test_mm512_maskz_rolv_epi64() {
8045 #[rustfmt::skip]
8046 let a = _mm512_set_epi64(
8047 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8048 1 << 32, 1 << 32, 1 << 32, 1 << 62,
8049 );
8050 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8051 let r = _mm512_maskz_rolv_epi64(0, a, b);
8052 assert_eq_m512i(r, _mm512_setzero_si512());
8053 let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8054 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8055 assert_eq_m512i(r, e);
8056 }
8057
8058 #[simd_test(enable = "avx512f,avx512vl")]
8059 unsafe fn test_mm256_rolv_epi64() {
8060 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8061 let b = _mm256_set_epi64x(0, 1, 2, 3);
8062 let r = _mm256_rolv_epi64(a, b);
8063 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8064 assert_eq_m256i(r, e);
8065 }
8066
8067 #[simd_test(enable = "avx512f,avx512vl")]
8068 unsafe fn test_mm256_mask_rolv_epi64() {
8069 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8070 let b = _mm256_set_epi64x(0, 1, 2, 3);
8071 let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8072 assert_eq_m256i(r, a);
8073 let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8074 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8075 assert_eq_m256i(r, e);
8076 }
8077
8078 #[simd_test(enable = "avx512f,avx512vl")]
8079 unsafe fn test_mm256_maskz_rolv_epi64() {
8080 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8081 let b = _mm256_set_epi64x(0, 1, 2, 3);
8082 let r = _mm256_maskz_rolv_epi64(0, a, b);
8083 assert_eq_m256i(r, _mm256_setzero_si256());
8084 let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8085 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8086 assert_eq_m256i(r, e);
8087 }
8088
8089 #[simd_test(enable = "avx512f,avx512vl")]
8090 unsafe fn test_mm_rolv_epi64() {
8091 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8092 let b = _mm_set_epi64x(0, 1);
8093 let r = _mm_rolv_epi64(a, b);
8094 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8095 assert_eq_m128i(r, e);
8096 }
8097
8098 #[simd_test(enable = "avx512f,avx512vl")]
8099 unsafe fn test_mm_mask_rolv_epi64() {
8100 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8101 let b = _mm_set_epi64x(0, 1);
8102 let r = _mm_mask_rolv_epi64(a, 0, a, b);
8103 assert_eq_m128i(r, a);
8104 let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8105 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8106 assert_eq_m128i(r, e);
8107 }
8108
8109 #[simd_test(enable = "avx512f,avx512vl")]
8110 unsafe fn test_mm_maskz_rolv_epi64() {
8111 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8112 let b = _mm_set_epi64x(0, 1);
8113 let r = _mm_maskz_rolv_epi64(0, a, b);
8114 assert_eq_m128i(r, _mm_setzero_si128());
8115 let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8116 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8117 assert_eq_m128i(r, e);
8118 }
8119
8120 #[simd_test(enable = "avx512f")]
8121 unsafe fn test_mm512_rorv_epi64() {
8122 #[rustfmt::skip]
8123 let a = _mm512_set_epi64(
8124 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8125 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8126 );
8127 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8128 let r = _mm512_rorv_epi64(a, b);
8129 #[rustfmt::skip]
8130 let e = _mm512_set_epi64(
8131 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8132 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8133 );
8134 assert_eq_m512i(r, e);
8135 }
8136
8137 #[simd_test(enable = "avx512f")]
8138 unsafe fn test_mm512_mask_rorv_epi64() {
8139 #[rustfmt::skip]
8140 let a = _mm512_set_epi64(
8141 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8142 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8143 );
8144 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8145 let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8146 assert_eq_m512i(r, a);
8147 let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8148 #[rustfmt::skip]
8149 let e = _mm512_set_epi64(
8150 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8151 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8152 );
8153 assert_eq_m512i(r, e);
8154 }
8155
8156 #[simd_test(enable = "avx512f")]
8157 unsafe fn test_mm512_maskz_rorv_epi64() {
8158 #[rustfmt::skip]
8159 let a = _mm512_set_epi64(
8160 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8161 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8162 );
8163 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8164 let r = _mm512_maskz_rorv_epi64(0, a, b);
8165 assert_eq_m512i(r, _mm512_setzero_si512());
8166 let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8167 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8168 assert_eq_m512i(r, e);
8169 }
8170
8171 #[simd_test(enable = "avx512f,avx512vl")]
8172 unsafe fn test_mm256_rorv_epi64() {
8173 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8174 let b = _mm256_set_epi64x(0, 1, 2, 3);
8175 let r = _mm256_rorv_epi64(a, b);
8176 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8177 assert_eq_m256i(r, e);
8178 }
8179
8180 #[simd_test(enable = "avx512f,avx512vl")]
8181 unsafe fn test_mm256_mask_rorv_epi64() {
8182 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8183 let b = _mm256_set_epi64x(0, 1, 2, 3);
8184 let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8185 assert_eq_m256i(r, a);
8186 let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8187 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8188 assert_eq_m256i(r, e);
8189 }
8190
8191 #[simd_test(enable = "avx512f,avx512vl")]
8192 unsafe fn test_mm256_maskz_rorv_epi64() {
8193 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8194 let b = _mm256_set_epi64x(0, 1, 2, 3);
8195 let r = _mm256_maskz_rorv_epi64(0, a, b);
8196 assert_eq_m256i(r, _mm256_setzero_si256());
8197 let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8198 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8199 assert_eq_m256i(r, e);
8200 }
8201
8202 #[simd_test(enable = "avx512f,avx512vl")]
8203 unsafe fn test_mm_rorv_epi64() {
8204 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8205 let b = _mm_set_epi64x(0, 1);
8206 let r = _mm_rorv_epi64(a, b);
8207 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8208 assert_eq_m128i(r, e);
8209 }
8210
8211 #[simd_test(enable = "avx512f,avx512vl")]
8212 unsafe fn test_mm_mask_rorv_epi64() {
8213 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8214 let b = _mm_set_epi64x(0, 1);
8215 let r = _mm_mask_rorv_epi64(a, 0, a, b);
8216 assert_eq_m128i(r, a);
8217 let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8218 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8219 assert_eq_m128i(r, e);
8220 }
8221
8222 #[simd_test(enable = "avx512f,avx512vl")]
8223 unsafe fn test_mm_maskz_rorv_epi64() {
8224 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8225 let b = _mm_set_epi64x(0, 1);
8226 let r = _mm_maskz_rorv_epi64(0, a, b);
8227 assert_eq_m128i(r, _mm_setzero_si128());
8228 let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8229 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8230 assert_eq_m128i(r, e);
8231 }
8232
8233 #[simd_test(enable = "avx512f")]
8234 unsafe fn test_mm512_sllv_epi64() {
8235 #[rustfmt::skip]
8236 let a = _mm512_set_epi64(
8237 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8238 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8239 );
8240 let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8241 let r = _mm512_sllv_epi64(a, count);
8242 #[rustfmt::skip]
8243 let e = _mm512_set_epi64(
8244 1 << 32, 0, 1 << 34, 1 << 35,
8245 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8246 );
8247 assert_eq_m512i(r, e);
8248 }
8249
8250 #[simd_test(enable = "avx512f")]
8251 unsafe fn test_mm512_mask_sllv_epi64() {
8252 #[rustfmt::skip]
8253 let a = _mm512_set_epi64(
8254 1 << 32, 1 << 32, 1 << 63, 1 << 32,
8255 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8256 );
8257 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8258 let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8259 assert_eq_m512i(r, a);
8260 let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8261 #[rustfmt::skip]
8262 let e = _mm512_set_epi64(
8263 1 << 32, 1 << 33, 0, 1 << 35,
8264 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8265 );
8266 assert_eq_m512i(r, e);
8267 }
8268
8269 #[simd_test(enable = "avx512f")]
8270 unsafe fn test_mm512_maskz_sllv_epi64() {
8271 #[rustfmt::skip]
8272 let a = _mm512_set_epi64(
8273 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8274 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8275 );
8276 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8277 let r = _mm512_maskz_sllv_epi64(0, a, count);
8278 assert_eq_m512i(r, _mm512_setzero_si512());
8279 let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8280 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8281 assert_eq_m512i(r, e);
8282 }
8283
8284 #[simd_test(enable = "avx512f,avx512vl")]
8285 unsafe fn test_mm256_mask_sllv_epi64() {
8286 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8287 let count = _mm256_set_epi64x(0, 1, 2, 3);
8288 let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8289 assert_eq_m256i(r, a);
8290 let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8291 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8292 assert_eq_m256i(r, e);
8293 }
8294
8295 #[simd_test(enable = "avx512f,avx512vl")]
8296 unsafe fn test_mm256_maskz_sllv_epi64() {
8297 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8298 let count = _mm256_set_epi64x(0, 1, 2, 3);
8299 let r = _mm256_maskz_sllv_epi64(0, a, count);
8300 assert_eq_m256i(r, _mm256_setzero_si256());
8301 let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8302 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8303 assert_eq_m256i(r, e);
8304 }
8305
8306 #[simd_test(enable = "avx512f,avx512vl")]
8307 unsafe fn test_mm_mask_sllv_epi64() {
8308 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8309 let count = _mm_set_epi64x(2, 3);
8310 let r = _mm_mask_sllv_epi64(a, 0, a, count);
8311 assert_eq_m128i(r, a);
8312 let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
8313 let e = _mm_set_epi64x(0, 1 << 35);
8314 assert_eq_m128i(r, e);
8315 }
8316
8317 #[simd_test(enable = "avx512f,avx512vl")]
8318 unsafe fn test_mm_maskz_sllv_epi64() {
8319 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8320 let count = _mm_set_epi64x(2, 3);
8321 let r = _mm_maskz_sllv_epi64(0, a, count);
8322 assert_eq_m128i(r, _mm_setzero_si128());
8323 let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
8324 let e = _mm_set_epi64x(0, 1 << 35);
8325 assert_eq_m128i(r, e);
8326 }
8327
8328 #[simd_test(enable = "avx512f")]
8329 unsafe fn test_mm512_srlv_epi64() {
8330 #[rustfmt::skip]
8331 let a = _mm512_set_epi64(
8332 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8333 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8334 );
8335 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8336 let r = _mm512_srlv_epi64(a, count);
8337 #[rustfmt::skip]
8338 let e = _mm512_set_epi64(
8339 1 << 32, 0, 1 << 30, 1 << 29,
8340 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8341 );
8342 assert_eq_m512i(r, e);
8343 }
8344
8345 #[simd_test(enable = "avx512f")]
8346 unsafe fn test_mm512_mask_srlv_epi64() {
8347 #[rustfmt::skip]
8348 let a = _mm512_set_epi64(
8349 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8350 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8351 );
8352 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8353 let r = _mm512_mask_srlv_epi64(a, 0, a, count);
8354 assert_eq_m512i(r, a);
8355 let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
8356 #[rustfmt::skip]
8357 let e = _mm512_set_epi64(
8358 1 << 32, 0, 1 << 30, 1 << 29,
8359 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8360 );
8361 assert_eq_m512i(r, e);
8362 }
8363
8364 #[simd_test(enable = "avx512f")]
8365 unsafe fn test_mm512_maskz_srlv_epi64() {
8366 #[rustfmt::skip]
8367 let a = _mm512_set_epi64(
8368 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8369 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8370 );
8371 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8372 let r = _mm512_maskz_srlv_epi64(0, a, count);
8373 assert_eq_m512i(r, _mm512_setzero_si512());
8374 let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
8375 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
8376 assert_eq_m512i(r, e);
8377 }
8378
8379 #[simd_test(enable = "avx512f,avx512vl")]
8380 unsafe fn test_mm256_mask_srlv_epi64() {
8381 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8382 let count = _mm256_set1_epi64x(1);
8383 let r = _mm256_mask_srlv_epi64(a, 0, a, count);
8384 assert_eq_m256i(r, a);
8385 let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
8386 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8387 assert_eq_m256i(r, e);
8388 }
8389
8390 #[simd_test(enable = "avx512f,avx512vl")]
8391 unsafe fn test_mm256_maskz_srlv_epi64() {
8392 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8393 let count = _mm256_set1_epi64x(1);
8394 let r = _mm256_maskz_srlv_epi64(0, a, count);
8395 assert_eq_m256i(r, _mm256_setzero_si256());
8396 let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
8397 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8398 assert_eq_m256i(r, e);
8399 }
8400
8401 #[simd_test(enable = "avx512f,avx512vl")]
8402 unsafe fn test_mm_mask_srlv_epi64() {
8403 let a = _mm_set_epi64x(1 << 5, 0);
8404 let count = _mm_set1_epi64x(1);
8405 let r = _mm_mask_srlv_epi64(a, 0, a, count);
8406 assert_eq_m128i(r, a);
8407 let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
8408 let e = _mm_set_epi64x(1 << 4, 0);
8409 assert_eq_m128i(r, e);
8410 }
8411
8412 #[simd_test(enable = "avx512f,avx512vl")]
8413 unsafe fn test_mm_maskz_srlv_epi64() {
8414 let a = _mm_set_epi64x(1 << 5, 0);
8415 let count = _mm_set1_epi64x(1);
8416 let r = _mm_maskz_srlv_epi64(0, a, count);
8417 assert_eq_m128i(r, _mm_setzero_si128());
8418 let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
8419 let e = _mm_set_epi64x(1 << 4, 0);
8420 assert_eq_m128i(r, e);
8421 }
8422
8423 #[simd_test(enable = "avx512f")]
8424 unsafe fn test_mm512_sll_epi64() {
8425 #[rustfmt::skip]
8426 let a = _mm512_set_epi64(
8427 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8428 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8429 );
8430 let count = _mm_set_epi64x(0, 1);
8431 let r = _mm512_sll_epi64(a, count);
8432 #[rustfmt::skip]
8433 let e = _mm512_set_epi64(
8434 0, 1 << 33, 1 << 33, 1 << 33,
8435 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8436 );
8437 assert_eq_m512i(r, e);
8438 let count = _mm_set_epi64x(1, 0);
8439 let r = _mm512_sll_epi64(a, count);
8440 assert_eq_m512i(r, a);
8441 }
8442
8443 #[simd_test(enable = "avx512f")]
8444 unsafe fn test_mm512_mask_sll_epi64() {
8445 #[rustfmt::skip]
8446 let a = _mm512_set_epi64(
8447 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8448 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8449 );
8450 let count = _mm_set_epi64x(0, 1);
8451 let r = _mm512_mask_sll_epi64(a, 0, a, count);
8452 assert_eq_m512i(r, a);
8453 let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
8454 #[rustfmt::skip]
8455 let e = _mm512_set_epi64(
8456 0, 1 << 33, 1 << 33, 1 << 33,
8457 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8458 );
8459 assert_eq_m512i(r, e);
8460 }
8461
8462 #[simd_test(enable = "avx512f")]
8463 unsafe fn test_mm512_maskz_sll_epi64() {
8464 #[rustfmt::skip]
8465 let a = _mm512_set_epi64(
8466 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8467 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8468 );
8469 let count = _mm_set_epi64x(0, 1);
8470 let r = _mm512_maskz_sll_epi64(0, a, count);
8471 assert_eq_m512i(r, _mm512_setzero_si512());
8472 let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
8473 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8474 assert_eq_m512i(r, e);
8475 }
8476
8477 #[simd_test(enable = "avx512f,avx512vl")]
8478 unsafe fn test_mm256_mask_sll_epi64() {
8479 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8480 let count = _mm_set_epi64x(0, 1);
8481 let r = _mm256_mask_sll_epi64(a, 0, a, count);
8482 assert_eq_m256i(r, a);
8483 let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
8484 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8485 assert_eq_m256i(r, e);
8486 }
8487
8488 #[simd_test(enable = "avx512f,avx512vl")]
8489 unsafe fn test_mm256_maskz_sll_epi64() {
8490 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8491 let count = _mm_set_epi64x(0, 1);
8492 let r = _mm256_maskz_sll_epi64(0, a, count);
8493 assert_eq_m256i(r, _mm256_setzero_si256());
8494 let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
8495 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8496 assert_eq_m256i(r, e);
8497 }
8498
8499 #[simd_test(enable = "avx512f,avx512vl")]
8500 unsafe fn test_mm_mask_sll_epi64() {
8501 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8502 let count = _mm_set_epi64x(0, 1);
8503 let r = _mm_mask_sll_epi64(a, 0, a, count);
8504 assert_eq_m128i(r, a);
8505 let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
8506 let e = _mm_set_epi64x(0, 1 << 33);
8507 assert_eq_m128i(r, e);
8508 }
8509
8510 #[simd_test(enable = "avx512f,avx512vl")]
8511 unsafe fn test_mm_maskz_sll_epi64() {
8512 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8513 let count = _mm_set_epi64x(0, 1);
8514 let r = _mm_maskz_sll_epi64(0, a, count);
8515 assert_eq_m128i(r, _mm_setzero_si128());
8516 let r = _mm_maskz_sll_epi64(0b00000011, a, count);
8517 let e = _mm_set_epi64x(0, 1 << 33);
8518 assert_eq_m128i(r, e);
8519 }
8520
8521 #[simd_test(enable = "avx512f")]
8522 unsafe fn test_mm512_srl_epi64() {
8523 #[rustfmt::skip]
8524 let a = _mm512_set_epi64(
8525 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8526 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8527 );
8528 let count = _mm_set_epi64x(0, 1);
8529 let r = _mm512_srl_epi64(a, count);
8530 #[rustfmt::skip]
8531 let e = _mm512_set_epi64(
8532 0, 1 << 31, 1 << 31, 1 << 31,
8533 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8534 );
8535 assert_eq_m512i(r, e);
8536 }
8537
8538 #[simd_test(enable = "avx512f")]
8539 unsafe fn test_mm512_mask_srl_epi64() {
8540 #[rustfmt::skip]
8541 let a = _mm512_set_epi64(
8542 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8543 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8544 );
8545 let count = _mm_set_epi64x(0, 1);
8546 let r = _mm512_mask_srl_epi64(a, 0, a, count);
8547 assert_eq_m512i(r, a);
8548 let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
8549 #[rustfmt::skip]
8550 let e = _mm512_set_epi64(
8551 0, 1 << 31, 1 << 31, 1 << 31,
8552 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8553 );
8554 assert_eq_m512i(r, e);
8555 }
8556
8557 #[simd_test(enable = "avx512f")]
8558 unsafe fn test_mm512_maskz_srl_epi64() {
8559 #[rustfmt::skip]
8560 let a = _mm512_set_epi64(
8561 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8562 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8563 );
8564 let count = _mm_set_epi64x(0, 1);
8565 let r = _mm512_maskz_srl_epi64(0, a, count);
8566 assert_eq_m512i(r, _mm512_setzero_si512());
8567 let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
8568 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8569 assert_eq_m512i(r, e);
8570 }
8571
8572 #[simd_test(enable = "avx512f,avx512vl")]
8573 unsafe fn test_mm256_mask_srl_epi64() {
8574 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8575 let count = _mm_set_epi64x(0, 1);
8576 let r = _mm256_mask_srl_epi64(a, 0, a, count);
8577 assert_eq_m256i(r, a);
8578 let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
8579 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8580 assert_eq_m256i(r, e);
8581 }
8582
8583 #[simd_test(enable = "avx512f,avx512vl")]
8584 unsafe fn test_mm256_maskz_srl_epi64() {
8585 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8586 let count = _mm_set_epi64x(0, 1);
8587 let r = _mm256_maskz_srl_epi64(0, a, count);
8588 assert_eq_m256i(r, _mm256_setzero_si256());
8589 let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
8590 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8591 assert_eq_m256i(r, e);
8592 }
8593
8594 #[simd_test(enable = "avx512f,avx512vl")]
8595 unsafe fn test_mm_mask_srl_epi64() {
8596 let a = _mm_set_epi64x(1 << 5, 0);
8597 let count = _mm_set_epi64x(0, 1);
8598 let r = _mm_mask_srl_epi64(a, 0, a, count);
8599 assert_eq_m128i(r, a);
8600 let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
8601 let e = _mm_set_epi64x(1 << 4, 0);
8602 assert_eq_m128i(r, e);
8603 }
8604
8605 #[simd_test(enable = "avx512f,avx512vl")]
8606 unsafe fn test_mm_maskz_srl_epi64() {
8607 let a = _mm_set_epi64x(1 << 5, 0);
8608 let count = _mm_set_epi64x(0, 1);
8609 let r = _mm_maskz_srl_epi64(0, a, count);
8610 assert_eq_m128i(r, _mm_setzero_si128());
8611 let r = _mm_maskz_srl_epi64(0b00000011, a, count);
8612 let e = _mm_set_epi64x(1 << 4, 0);
8613 assert_eq_m128i(r, e);
8614 }
8615
8616 #[simd_test(enable = "avx512f")]
8617 unsafe fn test_mm512_sra_epi64() {
8618 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8619 let count = _mm_set_epi64x(0, 2);
8620 let r = _mm512_sra_epi64(a, count);
8621 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
8622 assert_eq_m512i(r, e);
8623 }
8624
8625 #[simd_test(enable = "avx512f")]
8626 unsafe fn test_mm512_mask_sra_epi64() {
8627 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8628 let count = _mm_set_epi64x(0, 2);
8629 let r = _mm512_mask_sra_epi64(a, 0, a, count);
8630 assert_eq_m512i(r, a);
8631 let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
8632 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
8633 assert_eq_m512i(r, e);
8634 }
8635
8636 #[simd_test(enable = "avx512f")]
8637 unsafe fn test_mm512_maskz_sra_epi64() {
8638 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8639 let count = _mm_set_epi64x(0, 2);
8640 let r = _mm512_maskz_sra_epi64(0, a, count);
8641 assert_eq_m512i(r, _mm512_setzero_si512());
8642 let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
8643 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
8644 assert_eq_m512i(r, e);
8645 }
8646
8647 #[simd_test(enable = "avx512f,avx512vl")]
8648 unsafe fn test_mm256_sra_epi64() {
8649 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8650 let count = _mm_set_epi64x(0, 1);
8651 let r = _mm256_sra_epi64(a, count);
8652 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8653 assert_eq_m256i(r, e);
8654 }
8655
8656 #[simd_test(enable = "avx512f,avx512vl")]
8657 unsafe fn test_mm256_mask_sra_epi64() {
8658 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8659 let count = _mm_set_epi64x(0, 1);
8660 let r = _mm256_mask_sra_epi64(a, 0, a, count);
8661 assert_eq_m256i(r, a);
8662 let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
8663 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8664 assert_eq_m256i(r, e);
8665 }
8666
8667 #[simd_test(enable = "avx512f,avx512vl")]
8668 unsafe fn test_mm256_maskz_sra_epi64() {
8669 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8670 let count = _mm_set_epi64x(0, 1);
8671 let r = _mm256_maskz_sra_epi64(0, a, count);
8672 assert_eq_m256i(r, _mm256_setzero_si256());
8673 let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
8674 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8675 assert_eq_m256i(r, e);
8676 }
8677
8678 #[simd_test(enable = "avx512f,avx512vl")]
8679 unsafe fn test_mm_sra_epi64() {
8680 let a = _mm_set_epi64x(1 << 5, 0);
8681 let count = _mm_set_epi64x(0, 1);
8682 let r = _mm_sra_epi64(a, count);
8683 let e = _mm_set_epi64x(1 << 4, 0);
8684 assert_eq_m128i(r, e);
8685 }
8686
8687 #[simd_test(enable = "avx512f,avx512vl")]
8688 unsafe fn test_mm_mask_sra_epi64() {
8689 let a = _mm_set_epi64x(1 << 5, 0);
8690 let count = _mm_set_epi64x(0, 1);
8691 let r = _mm_mask_sra_epi64(a, 0, a, count);
8692 assert_eq_m128i(r, a);
8693 let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
8694 let e = _mm_set_epi64x(1 << 4, 0);
8695 assert_eq_m128i(r, e);
8696 }
8697
8698 #[simd_test(enable = "avx512f,avx512vl")]
8699 unsafe fn test_mm_maskz_sra_epi64() {
8700 let a = _mm_set_epi64x(1 << 5, 0);
8701 let count = _mm_set_epi64x(0, 1);
8702 let r = _mm_maskz_sra_epi64(0, a, count);
8703 assert_eq_m128i(r, _mm_setzero_si128());
8704 let r = _mm_maskz_sra_epi64(0b00000011, a, count);
8705 let e = _mm_set_epi64x(1 << 4, 0);
8706 assert_eq_m128i(r, e);
8707 }
8708
8709 #[simd_test(enable = "avx512f")]
8710 unsafe fn test_mm512_srav_epi64() {
8711 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8712 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
8713 let r = _mm512_srav_epi64(a, count);
8714 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
8715 assert_eq_m512i(r, e);
8716 }
8717
8718 #[simd_test(enable = "avx512f")]
8719 unsafe fn test_mm512_mask_srav_epi64() {
8720 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8721 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
8722 let r = _mm512_mask_srav_epi64(a, 0, a, count);
8723 assert_eq_m512i(r, a);
8724 let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
8725 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
8726 assert_eq_m512i(r, e);
8727 }
8728
8729 #[simd_test(enable = "avx512f")]
8730 unsafe fn test_mm512_maskz_srav_epi64() {
8731 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8732 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
8733 let r = _mm512_maskz_srav_epi64(0, a, count);
8734 assert_eq_m512i(r, _mm512_setzero_si512());
8735 let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
8736 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
8737 assert_eq_m512i(r, e);
8738 }
8739
8740 #[simd_test(enable = "avx512f,avx512vl")]
8741 unsafe fn test_mm256_srav_epi64() {
8742 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8743 let count = _mm256_set1_epi64x(1);
8744 let r = _mm256_srav_epi64(a, count);
8745 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8746 assert_eq_m256i(r, e);
8747 }
8748
8749 #[simd_test(enable = "avx512f,avx512vl")]
8750 unsafe fn test_mm256_mask_srav_epi64() {
8751 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8752 let count = _mm256_set1_epi64x(1);
8753 let r = _mm256_mask_srav_epi64(a, 0, a, count);
8754 assert_eq_m256i(r, a);
8755 let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
8756 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8757 assert_eq_m256i(r, e);
8758 }
8759
8760 #[simd_test(enable = "avx512f,avx512vl")]
8761 unsafe fn test_mm256_maskz_srav_epi64() {
8762 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8763 let count = _mm256_set1_epi64x(1);
8764 let r = _mm256_maskz_srav_epi64(0, a, count);
8765 assert_eq_m256i(r, _mm256_setzero_si256());
8766 let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
8767 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8768 assert_eq_m256i(r, e);
8769 }
8770
8771 #[simd_test(enable = "avx512f,avx512vl")]
8772 unsafe fn test_mm_srav_epi64() {
8773 let a = _mm_set_epi64x(1 << 5, 0);
8774 let count = _mm_set1_epi64x(1);
8775 let r = _mm_srav_epi64(a, count);
8776 let e = _mm_set_epi64x(1 << 4, 0);
8777 assert_eq_m128i(r, e);
8778 }
8779
8780 #[simd_test(enable = "avx512f,avx512vl")]
8781 unsafe fn test_mm_mask_srav_epi64() {
8782 let a = _mm_set_epi64x(1 << 5, 0);
8783 let count = _mm_set1_epi64x(1);
8784 let r = _mm_mask_srav_epi64(a, 0, a, count);
8785 assert_eq_m128i(r, a);
8786 let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
8787 let e = _mm_set_epi64x(1 << 4, 0);
8788 assert_eq_m128i(r, e);
8789 }
8790
8791 #[simd_test(enable = "avx512f,avx512vl")]
8792 unsafe fn test_mm_maskz_srav_epi64() {
8793 let a = _mm_set_epi64x(1 << 5, 0);
8794 let count = _mm_set1_epi64x(1);
8795 let r = _mm_maskz_srav_epi64(0, a, count);
8796 assert_eq_m128i(r, _mm_setzero_si128());
8797 let r = _mm_maskz_srav_epi64(0b00000011, a, count);
8798 let e = _mm_set_epi64x(1 << 4, 0);
8799 assert_eq_m128i(r, e);
8800 }
8801
8802 #[simd_test(enable = "avx512f")]
8803 unsafe fn test_mm512_srai_epi64() {
8804 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
8805 let r = _mm512_srai_epi64::<2>(a);
8806 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
8807 assert_eq_m512i(r, e);
8808 }
8809
8810 #[simd_test(enable = "avx512f")]
8811 unsafe fn test_mm512_mask_srai_epi64() {
8812 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
8813 let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
8814 assert_eq_m512i(r, a);
8815 let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
8816 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
8817 assert_eq_m512i(r, e);
8818 }
8819
8820 #[simd_test(enable = "avx512f")]
8821 unsafe fn test_mm512_maskz_srai_epi64() {
8822 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
8823 let r = _mm512_maskz_srai_epi64::<2>(0, a);
8824 assert_eq_m512i(r, _mm512_setzero_si512());
8825 let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
8826 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
8827 assert_eq_m512i(r, e);
8828 }
8829
8830 #[simd_test(enable = "avx512f,avx512vl")]
8831 unsafe fn test_mm256_srai_epi64() {
8832 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8833 let r = _mm256_srai_epi64::<1>(a);
8834 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8835 assert_eq_m256i(r, e);
8836 }
8837
8838 #[simd_test(enable = "avx512f,avx512vl")]
8839 unsafe fn test_mm256_mask_srai_epi64() {
8840 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8841 let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
8842 assert_eq_m256i(r, a);
8843 let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
8844 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8845 assert_eq_m256i(r, e);
8846 }
8847
8848 #[simd_test(enable = "avx512f,avx512vl")]
8849 unsafe fn test_mm256_maskz_srai_epi64() {
8850 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8851 let r = _mm256_maskz_srai_epi64::<1>(0, a);
8852 assert_eq_m256i(r, _mm256_setzero_si256());
8853 let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
8854 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8855 assert_eq_m256i(r, e);
8856 }
8857
8858 #[simd_test(enable = "avx512f,avx512vl")]
8859 unsafe fn test_mm_srai_epi64() {
8860 let a = _mm_set_epi64x(1 << 5, 0);
8861 let r = _mm_srai_epi64::<1>(a);
8862 let e = _mm_set_epi64x(1 << 4, 0);
8863 assert_eq_m128i(r, e);
8864 }
8865
8866 #[simd_test(enable = "avx512f,avx512vl")]
8867 unsafe fn test_mm_mask_srai_epi64() {
8868 let a = _mm_set_epi64x(1 << 5, 0);
8869 let r = _mm_mask_srai_epi64::<1>(a, 0, a);
8870 assert_eq_m128i(r, a);
8871 let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
8872 let e = _mm_set_epi64x(1 << 4, 0);
8873 assert_eq_m128i(r, e);
8874 }
8875
8876 #[simd_test(enable = "avx512f,avx512vl")]
8877 unsafe fn test_mm_maskz_srai_epi64() {
8878 let a = _mm_set_epi64x(1 << 5, 0);
8879 let r = _mm_maskz_srai_epi64::<1>(0, a);
8880 assert_eq_m128i(r, _mm_setzero_si128());
8881 let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
8882 let e = _mm_set_epi64x(1 << 4, 0);
8883 assert_eq_m128i(r, e);
8884 }
8885
8886 #[simd_test(enable = "avx512f")]
8887 unsafe fn test_mm512_permute_pd() {
8888 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
8889 let r = _mm512_permute_pd::<0b11_11_11_11>(a);
8890 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
8891 assert_eq_m512d(r, e);
8892 }
8893
8894 #[simd_test(enable = "avx512f")]
8895 unsafe fn test_mm512_mask_permute_pd() {
8896 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
8897 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
8898 assert_eq_m512d(r, a);
8899 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
8900 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
8901 assert_eq_m512d(r, e);
8902 }
8903
8904 #[simd_test(enable = "avx512f")]
8905 unsafe fn test_mm512_maskz_permute_pd() {
8906 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
8907 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
8908 assert_eq_m512d(r, _mm512_setzero_pd());
8909 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
8910 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
8911 assert_eq_m512d(r, e);
8912 }
8913
8914 #[simd_test(enable = "avx512f,avx512vl")]
8915 unsafe fn test_mm256_mask_permute_pd() {
8916 let a = _mm256_set_pd(3., 2., 1., 0.);
8917 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
8918 assert_eq_m256d(r, a);
8919 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
8920 let e = _mm256_set_pd(3., 3., 1., 1.);
8921 assert_eq_m256d(r, e);
8922 }
8923
8924 #[simd_test(enable = "avx512f,avx512vl")]
8925 unsafe fn test_mm256_maskz_permute_pd() {
8926 let a = _mm256_set_pd(3., 2., 1., 0.);
8927 let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
8928 assert_eq_m256d(r, _mm256_setzero_pd());
8929 let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
8930 let e = _mm256_set_pd(3., 3., 1., 1.);
8931 assert_eq_m256d(r, e);
8932 }
8933
8934 #[simd_test(enable = "avx512f,avx512vl")]
8935 unsafe fn test_mm_mask_permute_pd() {
8936 let a = _mm_set_pd(1., 0.);
8937 let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
8938 assert_eq_m128d(r, a);
8939 let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
8940 let e = _mm_set_pd(1., 1.);
8941 assert_eq_m128d(r, e);
8942 }
8943
8944 #[simd_test(enable = "avx512f,avx512vl")]
8945 unsafe fn test_mm_maskz_permute_pd() {
8946 let a = _mm_set_pd(1., 0.);
8947 let r = _mm_maskz_permute_pd::<0b11>(0, a);
8948 assert_eq_m128d(r, _mm_setzero_pd());
8949 let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
8950 let e = _mm_set_pd(1., 1.);
8951 assert_eq_m128d(r, e);
8952 }
8953
8954 #[simd_test(enable = "avx512f")]
8955 unsafe fn test_mm512_permutex_epi64() {
8956 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8957 let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
8958 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
8959 assert_eq_m512i(r, e);
8960 }
8961
8962 #[simd_test(enable = "avx512f")]
8963 unsafe fn test_mm512_mask_permutex_epi64() {
8964 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8965 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
8966 assert_eq_m512i(r, a);
8967 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
8968 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
8969 assert_eq_m512i(r, e);
8970 }
8971
8972 #[simd_test(enable = "avx512f")]
8973 unsafe fn test_mm512_maskz_permutex_epi64() {
8974 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8975 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
8976 assert_eq_m512i(r, _mm512_setzero_si512());
8977 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
8978 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
8979 assert_eq_m512i(r, e);
8980 }
8981
8982 #[simd_test(enable = "avx512f,avx512vl")]
8983 unsafe fn test_mm256_permutex_epi64() {
8984 let a = _mm256_set_epi64x(3, 2, 1, 0);
8985 let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
8986 let e = _mm256_set_epi64x(3, 3, 3, 3);
8987 assert_eq_m256i(r, e);
8988 }
8989
8990 #[simd_test(enable = "avx512f,avx512vl")]
8991 unsafe fn test_mm256_mask_permutex_epi64() {
8992 let a = _mm256_set_epi64x(3, 2, 1, 0);
8993 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
8994 assert_eq_m256i(r, a);
8995 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
8996 let e = _mm256_set_epi64x(3, 3, 3, 3);
8997 assert_eq_m256i(r, e);
8998 }
8999
9000 #[simd_test(enable = "avx512f")]
9001 unsafe fn test_mm256_maskz_permutex_epi64() {
9002 let a = _mm256_set_epi64x(3, 2, 1, 0);
9003 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9004 assert_eq_m256i(r, _mm256_setzero_si256());
9005 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9006 let e = _mm256_set_epi64x(3, 3, 3, 3);
9007 assert_eq_m256i(r, e);
9008 }
9009
9010 #[simd_test(enable = "avx512f")]
9011 unsafe fn test_mm512_permutex_pd() {
9012 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9013 let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9014 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9015 assert_eq_m512d(r, e);
9016 }
9017
9018 #[simd_test(enable = "avx512f")]
9019 unsafe fn test_mm512_mask_permutex_pd() {
9020 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9021 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9022 assert_eq_m512d(r, a);
9023 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9024 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9025 assert_eq_m512d(r, e);
9026 }
9027
9028 #[simd_test(enable = "avx512f")]
9029 unsafe fn test_mm512_maskz_permutex_pd() {
9030 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9031 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9032 assert_eq_m512d(r, _mm512_setzero_pd());
9033 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9034 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9035 assert_eq_m512d(r, e);
9036 }
9037
9038 #[simd_test(enable = "avx512f,avx512vl")]
9039 unsafe fn test_mm256_permutex_pd() {
9040 let a = _mm256_set_pd(0., 1., 2., 3.);
9041 let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9042 let e = _mm256_set_pd(0., 0., 0., 0.);
9043 assert_eq_m256d(r, e);
9044 }
9045
9046 #[simd_test(enable = "avx512f,avx512vl")]
9047 unsafe fn test_mm256_mask_permutex_pd() {
9048 let a = _mm256_set_pd(0., 1., 2., 3.);
9049 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9050 assert_eq_m256d(r, a);
9051 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9052 let e = _mm256_set_pd(0., 0., 0., 0.);
9053 assert_eq_m256d(r, e);
9054 }
9055
9056 #[simd_test(enable = "avx512f,avx512vl")]
9057 unsafe fn test_mm256_maskz_permutex_pd() {
9058 let a = _mm256_set_pd(0., 1., 2., 3.);
9059 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9060 assert_eq_m256d(r, _mm256_setzero_pd());
9061 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9062 let e = _mm256_set_pd(0., 0., 0., 0.);
9063 assert_eq_m256d(r, e);
9064 }
9065
9066 #[simd_test(enable = "avx512f")]
9067 unsafe fn test_mm512_permutevar_pd() {
9068 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9069 let b = _mm512_set1_epi64(0b1);
9070 let r = _mm512_permutevar_pd(a, b);
9071 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9072 assert_eq_m512d(r, e);
9073 }
9074
9075 #[simd_test(enable = "avx512f")]
9076 unsafe fn test_mm512_mask_permutevar_pd() {
9077 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9078 let b = _mm512_set1_epi64(0b1);
9079 let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9080 assert_eq_m512d(r, a);
9081 let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9082 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9083 assert_eq_m512d(r, e);
9084 }
9085
9086 #[simd_test(enable = "avx512f")]
9087 unsafe fn test_mm512_maskz_permutevar_pd() {
9088 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9089 let b = _mm512_set1_epi64(0b1);
9090 let r = _mm512_maskz_permutevar_pd(0, a, b);
9091 assert_eq_m512d(r, _mm512_setzero_pd());
9092 let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9093 let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9094 assert_eq_m512d(r, e);
9095 }
9096
9097 #[simd_test(enable = "avx512f,avx512vl")]
9098 unsafe fn test_mm256_mask_permutevar_pd() {
9099 let a = _mm256_set_pd(0., 1., 2., 3.);
9100 let b = _mm256_set1_epi64x(0b1);
9101 let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9102 assert_eq_m256d(r, a);
9103 let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9104 let e = _mm256_set_pd(1., 1., 3., 3.);
9105 assert_eq_m256d(r, e);
9106 }
9107
9108 #[simd_test(enable = "avx512f,avx512vl")]
9109 unsafe fn test_mm256_maskz_permutevar_pd() {
9110 let a = _mm256_set_pd(0., 1., 2., 3.);
9111 let b = _mm256_set1_epi64x(0b1);
9112 let r = _mm256_maskz_permutevar_pd(0, a, b);
9113 assert_eq_m256d(r, _mm256_setzero_pd());
9114 let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9115 let e = _mm256_set_pd(1., 1., 3., 3.);
9116 assert_eq_m256d(r, e);
9117 }
9118
9119 #[simd_test(enable = "avx512f,avx512vl")]
9120 unsafe fn test_mm_mask_permutevar_pd() {
9121 let a = _mm_set_pd(0., 1.);
9122 let b = _mm_set1_epi64x(0b1);
9123 let r = _mm_mask_permutevar_pd(a, 0, a, b);
9124 assert_eq_m128d(r, a);
9125 let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9126 let e = _mm_set_pd(1., 1.);
9127 assert_eq_m128d(r, e);
9128 }
9129
9130 #[simd_test(enable = "avx512f,avx512vl")]
9131 unsafe fn test_mm_maskz_permutevar_pd() {
9132 let a = _mm_set_pd(0., 1.);
9133 let b = _mm_set1_epi64x(0b1);
9134 let r = _mm_maskz_permutevar_pd(0, a, b);
9135 assert_eq_m128d(r, _mm_setzero_pd());
9136 let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9137 let e = _mm_set_pd(1., 1.);
9138 assert_eq_m128d(r, e);
9139 }
9140
9141 #[simd_test(enable = "avx512f")]
9142 unsafe fn test_mm512_permutexvar_epi64() {
9143 let idx = _mm512_set1_epi64(1);
9144 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9145 let r = _mm512_permutexvar_epi64(idx, a);
9146 let e = _mm512_set1_epi64(6);
9147 assert_eq_m512i(r, e);
9148 }
9149
9150 #[simd_test(enable = "avx512f")]
9151 unsafe fn test_mm512_mask_permutexvar_epi64() {
9152 let idx = _mm512_set1_epi64(1);
9153 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9154 let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9155 assert_eq_m512i(r, a);
9156 let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9157 let e = _mm512_set1_epi64(6);
9158 assert_eq_m512i(r, e);
9159 }
9160
9161 #[simd_test(enable = "avx512f")]
9162 unsafe fn test_mm512_maskz_permutexvar_epi64() {
9163 let idx = _mm512_set1_epi64(1);
9164 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9165 let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9166 assert_eq_m512i(r, _mm512_setzero_si512());
9167 let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9168 let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9169 assert_eq_m512i(r, e);
9170 }
9171
9172 #[simd_test(enable = "avx512f,avx512vl")]
9173 unsafe fn test_mm256_permutexvar_epi64() {
9174 let idx = _mm256_set1_epi64x(1);
9175 let a = _mm256_set_epi64x(0, 1, 2, 3);
9176 let r = _mm256_permutexvar_epi64(idx, a);
9177 let e = _mm256_set1_epi64x(2);
9178 assert_eq_m256i(r, e);
9179 }
9180
9181 #[simd_test(enable = "avx512f,avx512vl")]
9182 unsafe fn test_mm256_mask_permutexvar_epi64() {
9183 let idx = _mm256_set1_epi64x(1);
9184 let a = _mm256_set_epi64x(0, 1, 2, 3);
9185 let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9186 assert_eq_m256i(r, a);
9187 let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9188 let e = _mm256_set1_epi64x(2);
9189 assert_eq_m256i(r, e);
9190 }
9191
9192 #[simd_test(enable = "avx512f,avx512vl")]
9193 unsafe fn test_mm256_maskz_permutexvar_epi64() {
9194 let idx = _mm256_set1_epi64x(1);
9195 let a = _mm256_set_epi64x(0, 1, 2, 3);
9196 let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9197 assert_eq_m256i(r, _mm256_setzero_si256());
9198 let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9199 let e = _mm256_set1_epi64x(2);
9200 assert_eq_m256i(r, e);
9201 }
9202
9203 #[simd_test(enable = "avx512f")]
9204 unsafe fn test_mm512_permutexvar_pd() {
9205 let idx = _mm512_set1_epi64(1);
9206 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9207 let r = _mm512_permutexvar_pd(idx, a);
9208 let e = _mm512_set1_pd(6.);
9209 assert_eq_m512d(r, e);
9210 }
9211
9212 #[simd_test(enable = "avx512f")]
9213 unsafe fn test_mm512_mask_permutexvar_pd() {
9214 let idx = _mm512_set1_epi64(1);
9215 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9216 let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9217 assert_eq_m512d(r, a);
9218 let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9219 let e = _mm512_set1_pd(6.);
9220 assert_eq_m512d(r, e);
9221 }
9222
9223 #[simd_test(enable = "avx512f")]
9224 unsafe fn test_mm512_maskz_permutexvar_pd() {
9225 let idx = _mm512_set1_epi64(1);
9226 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9227 let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9228 assert_eq_m512d(r, _mm512_setzero_pd());
9229 let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9230 let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9231 assert_eq_m512d(r, e);
9232 }
9233
9234 #[simd_test(enable = "avx512f,avx512vl")]
9235 unsafe fn test_mm256_permutexvar_pd() {
9236 let idx = _mm256_set1_epi64x(1);
9237 let a = _mm256_set_pd(0., 1., 2., 3.);
9238 let r = _mm256_permutexvar_pd(idx, a);
9239 let e = _mm256_set1_pd(2.);
9240 assert_eq_m256d(r, e);
9241 }
9242
9243 #[simd_test(enable = "avx512f,avx512vl")]
9244 unsafe fn test_mm256_mask_permutexvar_pd() {
9245 let idx = _mm256_set1_epi64x(1);
9246 let a = _mm256_set_pd(0., 1., 2., 3.);
9247 let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9248 assert_eq_m256d(r, a);
9249 let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9250 let e = _mm256_set1_pd(2.);
9251 assert_eq_m256d(r, e);
9252 }
9253
9254 #[simd_test(enable = "avx512f,avx512vl")]
9255 unsafe fn test_mm256_maskz_permutexvar_pd() {
9256 let idx = _mm256_set1_epi64x(1);
9257 let a = _mm256_set_pd(0., 1., 2., 3.);
9258 let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9259 assert_eq_m256d(r, _mm256_setzero_pd());
9260 let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9261 let e = _mm256_set1_pd(2.);
9262 assert_eq_m256d(r, e);
9263 }
9264
9265 #[simd_test(enable = "avx512f")]
9266 unsafe fn test_mm512_permutex2var_epi64() {
9267 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9268 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9269 let b = _mm512_set1_epi64(100);
9270 let r = _mm512_permutex2var_epi64(a, idx, b);
9271 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9272 assert_eq_m512i(r, e);
9273 }
9274
9275 #[simd_test(enable = "avx512f")]
9276 unsafe fn test_mm512_mask_permutex2var_epi64() {
9277 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9278 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9279 let b = _mm512_set1_epi64(100);
9280 let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9281 assert_eq_m512i(r, a);
9282 let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9283 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9284 assert_eq_m512i(r, e);
9285 }
9286
9287 #[simd_test(enable = "avx512f")]
9288 unsafe fn test_mm512_maskz_permutex2var_epi64() {
9289 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9290 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9291 let b = _mm512_set1_epi64(100);
9292 let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9293 assert_eq_m512i(r, _mm512_setzero_si512());
9294 let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9295 let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9296 assert_eq_m512i(r, e);
9297 }
9298
9299 #[simd_test(enable = "avx512f")]
9300 unsafe fn test_mm512_mask2_permutex2var_epi64() {
9301 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9302 let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9303 let b = _mm512_set1_epi64(100);
9304 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
9305 assert_eq_m512i(r, idx);
9306 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9307 let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
9308 assert_eq_m512i(r, e);
9309 }
9310
9311 #[simd_test(enable = "avx512f,avx512vl")]
9312 unsafe fn test_mm256_permutex2var_epi64() {
9313 let a = _mm256_set_epi64x(0, 1, 2, 3);
9314 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9315 let b = _mm256_set1_epi64x(100);
9316 let r = _mm256_permutex2var_epi64(a, idx, b);
9317 let e = _mm256_set_epi64x(2, 100, 1, 100);
9318 assert_eq_m256i(r, e);
9319 }
9320
9321 #[simd_test(enable = "avx512f,avx512vl")]
9322 unsafe fn test_mm256_mask_permutex2var_epi64() {
9323 let a = _mm256_set_epi64x(0, 1, 2, 3);
9324 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9325 let b = _mm256_set1_epi64x(100);
9326 let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
9327 assert_eq_m256i(r, a);
9328 let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
9329 let e = _mm256_set_epi64x(2, 100, 1, 100);
9330 assert_eq_m256i(r, e);
9331 }
9332
9333 #[simd_test(enable = "avx512f,avx512vl")]
9334 unsafe fn test_mm256_maskz_permutex2var_epi64() {
9335 let a = _mm256_set_epi64x(0, 1, 2, 3);
9336 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9337 let b = _mm256_set1_epi64x(100);
9338 let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
9339 assert_eq_m256i(r, _mm256_setzero_si256());
9340 let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9341 let e = _mm256_set_epi64x(2, 100, 1, 100);
9342 assert_eq_m256i(r, e);
9343 }
9344
9345 #[simd_test(enable = "avx512f,avx512vl")]
9346 unsafe fn test_mm256_mask2_permutex2var_epi64() {
9347 let a = _mm256_set_epi64x(0, 1, 2, 3);
9348 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9349 let b = _mm256_set1_epi64x(100);
9350 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
9351 assert_eq_m256i(r, idx);
9352 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9353 let e = _mm256_set_epi64x(2, 100, 1, 100);
9354 assert_eq_m256i(r, e);
9355 }
9356
9357 #[simd_test(enable = "avx512f,avx512vl")]
9358 unsafe fn test_mm_permutex2var_epi64() {
9359 let a = _mm_set_epi64x(0, 1);
9360 let idx = _mm_set_epi64x(1, 1 << 1);
9361 let b = _mm_set1_epi64x(100);
9362 let r = _mm_permutex2var_epi64(a, idx, b);
9363 let e = _mm_set_epi64x(0, 100);
9364 assert_eq_m128i(r, e);
9365 }
9366
9367 #[simd_test(enable = "avx512f,avx512vl")]
9368 unsafe fn test_mm_mask_permutex2var_epi64() {
9369 let a = _mm_set_epi64x(0, 1);
9370 let idx = _mm_set_epi64x(1, 1 << 1);
9371 let b = _mm_set1_epi64x(100);
9372 let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
9373 assert_eq_m128i(r, a);
9374 let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
9375 let e = _mm_set_epi64x(0, 100);
9376 assert_eq_m128i(r, e);
9377 }
9378
9379 #[simd_test(enable = "avx512f,avx512vl")]
9380 unsafe fn test_mm_maskz_permutex2var_epi64() {
9381 let a = _mm_set_epi64x(0, 1);
9382 let idx = _mm_set_epi64x(1, 1 << 1);
9383 let b = _mm_set1_epi64x(100);
9384 let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
9385 assert_eq_m128i(r, _mm_setzero_si128());
9386 let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
9387 let e = _mm_set_epi64x(0, 100);
9388 assert_eq_m128i(r, e);
9389 }
9390
9391 #[simd_test(enable = "avx512f,avx512vl")]
9392 unsafe fn test_mm_mask2_permutex2var_epi64() {
9393 let a = _mm_set_epi64x(0, 1);
9394 let idx = _mm_set_epi64x(1, 1 << 1);
9395 let b = _mm_set1_epi64x(100);
9396 let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
9397 assert_eq_m128i(r, idx);
9398 let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
9399 let e = _mm_set_epi64x(0, 100);
9400 assert_eq_m128i(r, e);
9401 }
9402
9403 #[simd_test(enable = "avx512f")]
9404 unsafe fn test_mm512_permutex2var_pd() {
9405 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9406 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9407 let b = _mm512_set1_pd(100.);
9408 let r = _mm512_permutex2var_pd(a, idx, b);
9409 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
9410 assert_eq_m512d(r, e);
9411 }
9412
9413 #[simd_test(enable = "avx512f")]
9414 unsafe fn test_mm512_mask_permutex2var_pd() {
9415 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9416 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9417 let b = _mm512_set1_pd(100.);
9418 let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
9419 assert_eq_m512d(r, a);
9420 let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
9421 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
9422 assert_eq_m512d(r, e);
9423 }
9424
9425 #[simd_test(enable = "avx512f")]
9426 unsafe fn test_mm512_maskz_permutex2var_pd() {
9427 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9428 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9429 let b = _mm512_set1_pd(100.);
9430 let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
9431 assert_eq_m512d(r, _mm512_setzero_pd());
9432 let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
9433 let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
9434 assert_eq_m512d(r, e);
9435 }
9436
9437 #[simd_test(enable = "avx512f")]
9438 unsafe fn test_mm512_mask2_permutex2var_pd() {
9439 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9440 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9441 let b = _mm512_set1_pd(100.);
9442 let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
9443 assert_eq_m512d(r, _mm512_castsi512_pd(idx));
9444 let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
9445 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
9446 assert_eq_m512d(r, e);
9447 }
9448
9449 #[simd_test(enable = "avx512f,avx512vl")]
9450 unsafe fn test_mm256_permutex2var_pd() {
9451 let a = _mm256_set_pd(0., 1., 2., 3.);
9452 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9453 let b = _mm256_set1_pd(100.);
9454 let r = _mm256_permutex2var_pd(a, idx, b);
9455 let e = _mm256_set_pd(2., 100., 1., 100.);
9456 assert_eq_m256d(r, e);
9457 }
9458
9459 #[simd_test(enable = "avx512f,avx512vl")]
9460 unsafe fn test_mm256_mask_permutex2var_pd() {
9461 let a = _mm256_set_pd(0., 1., 2., 3.);
9462 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9463 let b = _mm256_set1_pd(100.);
9464 let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
9465 assert_eq_m256d(r, a);
9466 let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
9467 let e = _mm256_set_pd(2., 100., 1., 100.);
9468 assert_eq_m256d(r, e);
9469 }
9470
9471 #[simd_test(enable = "avx512f,avx512vl")]
9472 unsafe fn test_mm256_maskz_permutex2var_pd() {
9473 let a = _mm256_set_pd(0., 1., 2., 3.);
9474 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9475 let b = _mm256_set1_pd(100.);
9476 let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
9477 assert_eq_m256d(r, _mm256_setzero_pd());
9478 let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
9479 let e = _mm256_set_pd(2., 100., 1., 100.);
9480 assert_eq_m256d(r, e);
9481 }
9482
9483 #[simd_test(enable = "avx512f,avx512vl")]
9484 unsafe fn test_mm256_mask2_permutex2var_pd() {
9485 let a = _mm256_set_pd(0., 1., 2., 3.);
9486 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9487 let b = _mm256_set1_pd(100.);
9488 let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
9489 assert_eq_m256d(r, _mm256_castsi256_pd(idx));
9490 let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
9491 let e = _mm256_set_pd(2., 100., 1., 100.);
9492 assert_eq_m256d(r, e);
9493 }
9494
9495 #[simd_test(enable = "avx512f,avx512vl")]
9496 unsafe fn test_mm_permutex2var_pd() {
9497 let a = _mm_set_pd(0., 1.);
9498 let idx = _mm_set_epi64x(1, 1 << 1);
9499 let b = _mm_set1_pd(100.);
9500 let r = _mm_permutex2var_pd(a, idx, b);
9501 let e = _mm_set_pd(0., 100.);
9502 assert_eq_m128d(r, e);
9503 }
9504
9505 #[simd_test(enable = "avx512f,avx512vl")]
9506 unsafe fn test_mm_mask_permutex2var_pd() {
9507 let a = _mm_set_pd(0., 1.);
9508 let idx = _mm_set_epi64x(1, 1 << 1);
9509 let b = _mm_set1_pd(100.);
9510 let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
9511 assert_eq_m128d(r, a);
9512 let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
9513 let e = _mm_set_pd(0., 100.);
9514 assert_eq_m128d(r, e);
9515 }
9516
9517 #[simd_test(enable = "avx512f,avx512vl")]
9518 unsafe fn test_mm_maskz_permutex2var_pd() {
9519 let a = _mm_set_pd(0., 1.);
9520 let idx = _mm_set_epi64x(1, 1 << 1);
9521 let b = _mm_set1_pd(100.);
9522 let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
9523 assert_eq_m128d(r, _mm_setzero_pd());
9524 let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
9525 let e = _mm_set_pd(0., 100.);
9526 assert_eq_m128d(r, e);
9527 }
9528
9529 #[simd_test(enable = "avx512f,avx512vl")]
9530 unsafe fn test_mm_mask2_permutex2var_pd() {
9531 let a = _mm_set_pd(0., 1.);
9532 let idx = _mm_set_epi64x(1, 1 << 1);
9533 let b = _mm_set1_pd(100.);
9534 let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
9535 assert_eq_m128d(r, _mm_castsi128_pd(idx));
9536 let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
9537 let e = _mm_set_pd(0., 100.);
9538 assert_eq_m128d(r, e);
9539 }
9540
9541 #[simd_test(enable = "avx512f,avx512vl")]
9542 unsafe fn test_mm256_mask_shuffle_pd() {
9543 let a = _mm256_set_pd(1., 4., 5., 8.);
9544 let b = _mm256_set_pd(2., 3., 6., 7.);
9545 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
9546 assert_eq_m256d(r, a);
9547 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
9548 let e = _mm256_set_pd(2., 1., 6., 5.);
9549 assert_eq_m256d(r, e);
9550 }
9551
9552 #[simd_test(enable = "avx512f,avx512vl")]
9553 unsafe fn test_mm256_maskz_shuffle_pd() {
9554 let a = _mm256_set_pd(1., 4., 5., 8.);
9555 let b = _mm256_set_pd(2., 3., 6., 7.);
9556 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
9557 assert_eq_m256d(r, _mm256_setzero_pd());
9558 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
9559 let e = _mm256_set_pd(2., 1., 6., 5.);
9560 assert_eq_m256d(r, e);
9561 }
9562
9563 #[simd_test(enable = "avx512f,avx512vl")]
9564 unsafe fn test_mm_mask_shuffle_pd() {
9565 let a = _mm_set_pd(1., 4.);
9566 let b = _mm_set_pd(2., 3.);
9567 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
9568 assert_eq_m128d(r, a);
9569 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
9570 let e = _mm_set_pd(2., 1.);
9571 assert_eq_m128d(r, e);
9572 }
9573
9574 #[simd_test(enable = "avx512f,avx512vl")]
9575 unsafe fn test_mm_maskz_shuffle_pd() {
9576 let a = _mm_set_pd(1., 4.);
9577 let b = _mm_set_pd(2., 3.);
9578 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
9579 assert_eq_m128d(r, _mm_setzero_pd());
9580 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
9581 let e = _mm_set_pd(2., 1.);
9582 assert_eq_m128d(r, e);
9583 }
9584
9585 #[simd_test(enable = "avx512f")]
9586 unsafe fn test_mm512_shuffle_i64x2() {
9587 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
9588 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
9589 let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
9590 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
9591 assert_eq_m512i(r, e);
9592 }
9593
9594 #[simd_test(enable = "avx512f")]
9595 unsafe fn test_mm512_mask_shuffle_i64x2() {
9596 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
9597 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
9598 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
9599 assert_eq_m512i(r, a);
9600 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
9601 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
9602 assert_eq_m512i(r, e);
9603 }
9604
9605 #[simd_test(enable = "avx512f")]
9606 unsafe fn test_mm512_maskz_shuffle_i64x2() {
9607 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
9608 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
9609 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
9610 assert_eq_m512i(r, _mm512_setzero_si512());
9611 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
9612 let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
9613 assert_eq_m512i(r, e);
9614 }
9615
9616 #[simd_test(enable = "avx512f,avx512vl")]
9617 unsafe fn test_mm256_shuffle_i64x2() {
9618 let a = _mm256_set_epi64x(1, 4, 5, 8);
9619 let b = _mm256_set_epi64x(2, 3, 6, 7);
9620 let r = _mm256_shuffle_i64x2::<0b00>(a, b);
9621 let e = _mm256_set_epi64x(6, 7, 5, 8);
9622 assert_eq_m256i(r, e);
9623 }
9624
9625 #[simd_test(enable = "avx512f,avx512vl")]
9626 unsafe fn test_mm256_mask_shuffle_i64x2() {
9627 let a = _mm256_set_epi64x(1, 4, 5, 8);
9628 let b = _mm256_set_epi64x(2, 3, 6, 7);
9629 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
9630 assert_eq_m256i(r, a);
9631 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
9632 let e = _mm256_set_epi64x(6, 7, 5, 8);
9633 assert_eq_m256i(r, e);
9634 }
9635
9636 #[simd_test(enable = "avx512f,avx512vl")]
9637 unsafe fn test_mm256_maskz_shuffle_i64x2() {
9638 let a = _mm256_set_epi64x(1, 4, 5, 8);
9639 let b = _mm256_set_epi64x(2, 3, 6, 7);
9640 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
9641 assert_eq_m256i(r, _mm256_setzero_si256());
9642 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
9643 let e = _mm256_set_epi64x(6, 7, 5, 8);
9644 assert_eq_m256i(r, e);
9645 }
9646
9647 #[simd_test(enable = "avx512f")]
9648 unsafe fn test_mm512_shuffle_f64x2() {
9649 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
9650 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
9651 let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
9652 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
9653 assert_eq_m512d(r, e);
9654 }
9655
9656 #[simd_test(enable = "avx512f")]
9657 unsafe fn test_mm512_mask_shuffle_f64x2() {
9658 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
9659 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
9660 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
9661 assert_eq_m512d(r, a);
9662 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
9663 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
9664 assert_eq_m512d(r, e);
9665 }
9666
9667 #[simd_test(enable = "avx512f")]
9668 unsafe fn test_mm512_maskz_shuffle_f64x2() {
9669 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
9670 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
9671 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
9672 assert_eq_m512d(r, _mm512_setzero_pd());
9673 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
9674 let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
9675 assert_eq_m512d(r, e);
9676 }
9677
9678 #[simd_test(enable = "avx512f,avx512vl")]
9679 unsafe fn test_mm256_shuffle_f64x2() {
9680 let a = _mm256_set_pd(1., 4., 5., 8.);
9681 let b = _mm256_set_pd(2., 3., 6., 7.);
9682 let r = _mm256_shuffle_f64x2::<0b00>(a, b);
9683 let e = _mm256_set_pd(6., 7., 5., 8.);
9684 assert_eq_m256d(r, e);
9685 }
9686
9687 #[simd_test(enable = "avx512f,avx512vl")]
9688 unsafe fn test_mm256_mask_shuffle_f64x2() {
9689 let a = _mm256_set_pd(1., 4., 5., 8.);
9690 let b = _mm256_set_pd(2., 3., 6., 7.);
9691 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
9692 assert_eq_m256d(r, a);
9693 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
9694 let e = _mm256_set_pd(6., 7., 5., 8.);
9695 assert_eq_m256d(r, e);
9696 }
9697
9698 #[simd_test(enable = "avx512f,avx512vl")]
9699 unsafe fn test_mm256_maskz_shuffle_f64x2() {
9700 let a = _mm256_set_pd(1., 4., 5., 8.);
9701 let b = _mm256_set_pd(2., 3., 6., 7.);
9702 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
9703 assert_eq_m256d(r, _mm256_setzero_pd());
9704 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
9705 let e = _mm256_set_pd(6., 7., 5., 8.);
9706 assert_eq_m256d(r, e);
9707 }
9708
9709 #[simd_test(enable = "avx512f")]
9710 unsafe fn test_mm512_movedup_pd() {
9711 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9712 let r = _mm512_movedup_pd(a);
9713 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9714 assert_eq_m512d(r, e);
9715 }
9716
9717 #[simd_test(enable = "avx512f")]
9718 unsafe fn test_mm512_mask_movedup_pd() {
9719 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9720 let r = _mm512_mask_movedup_pd(a, 0, a);
9721 assert_eq_m512d(r, a);
9722 let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
9723 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9724 assert_eq_m512d(r, e);
9725 }
9726
9727 #[simd_test(enable = "avx512f")]
9728 unsafe fn test_mm512_maskz_movedup_pd() {
9729 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9730 let r = _mm512_maskz_movedup_pd(0, a);
9731 assert_eq_m512d(r, _mm512_setzero_pd());
9732 let r = _mm512_maskz_movedup_pd(0b00001111, a);
9733 let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
9734 assert_eq_m512d(r, e);
9735 }
9736
9737 #[simd_test(enable = "avx512f,avx512vl")]
9738 unsafe fn test_mm256_mask_movedup_pd() {
9739 let a = _mm256_set_pd(1., 2., 3., 4.);
9740 let r = _mm256_mask_movedup_pd(a, 0, a);
9741 assert_eq_m256d(r, a);
9742 let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
9743 let e = _mm256_set_pd(2., 2., 4., 4.);
9744 assert_eq_m256d(r, e);
9745 }
9746
9747 #[simd_test(enable = "avx512f,avx512vl")]
9748 unsafe fn test_mm256_maskz_movedup_pd() {
9749 let a = _mm256_set_pd(1., 2., 3., 4.);
9750 let r = _mm256_maskz_movedup_pd(0, a);
9751 assert_eq_m256d(r, _mm256_setzero_pd());
9752 let r = _mm256_maskz_movedup_pd(0b00001111, a);
9753 let e = _mm256_set_pd(2., 2., 4., 4.);
9754 assert_eq_m256d(r, e);
9755 }
9756
9757 #[simd_test(enable = "avx512f,avx512vl")]
9758 unsafe fn test_mm_mask_movedup_pd() {
9759 let a = _mm_set_pd(1., 2.);
9760 let r = _mm_mask_movedup_pd(a, 0, a);
9761 assert_eq_m128d(r, a);
9762 let r = _mm_mask_movedup_pd(a, 0b00000011, a);
9763 let e = _mm_set_pd(2., 2.);
9764 assert_eq_m128d(r, e);
9765 }
9766
9767 #[simd_test(enable = "avx512f,avx512vl")]
9768 unsafe fn test_mm_maskz_movedup_pd() {
9769 let a = _mm_set_pd(1., 2.);
9770 let r = _mm_maskz_movedup_pd(0, a);
9771 assert_eq_m128d(r, _mm_setzero_pd());
9772 let r = _mm_maskz_movedup_pd(0b00000011, a);
9773 let e = _mm_set_pd(2., 2.);
9774 assert_eq_m128d(r, e);
9775 }
9776
9777 #[simd_test(enable = "avx512f")]
9778 unsafe fn test_mm512_inserti64x4() {
9779 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
9780 let b = _mm256_setr_epi64x(17, 18, 19, 20);
9781 let r = _mm512_inserti64x4::<1>(a, b);
9782 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
9783 assert_eq_m512i(r, e);
9784 }
9785
9786 #[simd_test(enable = "avx512f")]
9787 unsafe fn test_mm512_mask_inserti64x4() {
9788 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
9789 let b = _mm256_setr_epi64x(17, 18, 19, 20);
9790 let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
9791 assert_eq_m512i(r, a);
9792 let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
9793 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
9794 assert_eq_m512i(r, e);
9795 }
9796
9797 #[simd_test(enable = "avx512f")]
9798 unsafe fn test_mm512_maskz_inserti64x4() {
9799 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
9800 let b = _mm256_setr_epi64x(17, 18, 19, 20);
9801 let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
9802 assert_eq_m512i(r, _mm512_setzero_si512());
9803 let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
9804 let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
9805 assert_eq_m512i(r, e);
9806 }
9807
9808 #[simd_test(enable = "avx512f")]
9809 unsafe fn test_mm512_insertf64x4() {
9810 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9811 let b = _mm256_setr_pd(17., 18., 19., 20.);
9812 let r = _mm512_insertf64x4::<1>(a, b);
9813 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
9814 assert_eq_m512d(r, e);
9815 }
9816
9817 #[simd_test(enable = "avx512f")]
9818 unsafe fn test_mm512_mask_insertf64x4() {
9819 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9820 let b = _mm256_setr_pd(17., 18., 19., 20.);
9821 let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
9822 assert_eq_m512d(r, a);
9823 let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
9824 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
9825 assert_eq_m512d(r, e);
9826 }
9827
9828 #[simd_test(enable = "avx512f")]
9829 unsafe fn test_mm512_maskz_insertf64x4() {
9830 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9831 let b = _mm256_setr_pd(17., 18., 19., 20.);
9832 let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
9833 assert_eq_m512d(r, _mm512_setzero_pd());
9834 let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
9835 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
9836 assert_eq_m512d(r, e);
9837 }
9838
9839 #[simd_test(enable = "avx512f")]
9840 unsafe fn test_mm512_castpd128_pd512() {
9841 let a = _mm_setr_pd(17., 18.);
9842 let r = _mm512_castpd128_pd512(a);
9843 let e = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
9844 assert_eq_m512d(r, e);
9845 }
9846
9847 #[simd_test(enable = "avx512f")]
9848 unsafe fn test_mm512_castpd256_pd512() {
9849 let a = _mm256_setr_pd(17., 18., 19., 20.);
9850 let r = _mm512_castpd256_pd512(a);
9851 let e = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
9852 assert_eq_m512d(r, e);
9853 }
9854
9855 #[simd_test(enable = "avx512f")]
9856 unsafe fn test_mm512_zextpd128_pd512() {
9857 let a = _mm_setr_pd(17., 18.);
9858 let r = _mm512_zextpd128_pd512(a);
9859 let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
9860 assert_eq_m512d(r, e);
9861 }
9862
9863 #[simd_test(enable = "avx512f")]
9864 unsafe fn test_mm512_zextpd256_pd512() {
9865 let a = _mm256_setr_pd(17., 18., 19., 20.);
9866 let r = _mm512_zextpd256_pd512(a);
9867 let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
9868 assert_eq_m512d(r, e);
9869 }
9870
9871 #[simd_test(enable = "avx512f")]
9872 unsafe fn test_mm512_castpd512_pd128() {
9873 let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
9874 let r = _mm512_castpd512_pd128(a);
9875 let e = _mm_setr_pd(17., 18.);
9876 assert_eq_m128d(r, e);
9877 }
9878
9879 #[simd_test(enable = "avx512f")]
9880 unsafe fn test_mm512_castpd512_pd256() {
9881 let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
9882 let r = _mm512_castpd512_pd256(a);
9883 let e = _mm256_setr_pd(17., 18., 19., 20.);
9884 assert_eq_m256d(r, e);
9885 }
9886
9887 #[simd_test(enable = "avx512f")]
9888 unsafe fn test_mm512_castpd_ps() {
9889 let a = _mm512_set1_pd(1.);
9890 let r = _mm512_castpd_ps(a);
9891 let e = _mm512_set_ps(
9892 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
9893 1.875, 0.0,
9894 );
9895 assert_eq_m512(r, e);
9896 }
9897
9898 #[simd_test(enable = "avx512f")]
9899 unsafe fn test_mm512_castpd_si512() {
9900 let a = _mm512_set1_pd(1.);
9901 let r = _mm512_castpd_si512(a);
9902 let e = _mm512_set_epi32(
9903 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
9904 0, 1072693248, 0, 1072693248, 0,
9905 );
9906 assert_eq_m512i(r, e);
9907 }
9908
9909 #[simd_test(enable = "avx512f")]
9910 unsafe fn test_mm512_castsi128_si512() {
9911 let a = _mm_setr_epi64x(17, 18);
9912 let r = _mm512_castsi128_si512(a);
9913 let e = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
9914 assert_eq_m512i(r, e);
9915 }
9916
9917 #[simd_test(enable = "avx512f")]
9918 unsafe fn test_mm512_castsi256_si512() {
9919 let a = _mm256_setr_epi64x(17, 18, 19, 20);
9920 let r = _mm512_castsi256_si512(a);
9921 let e = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
9922 assert_eq_m512i(r, e);
9923 }
9924
9925 #[simd_test(enable = "avx512f")]
9926 unsafe fn test_mm512_zextsi128_si512() {
9927 let a = _mm_setr_epi64x(17, 18);
9928 let r = _mm512_zextsi128_si512(a);
9929 let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
9930 assert_eq_m512i(r, e);
9931 }
9932
9933 #[simd_test(enable = "avx512f")]
9934 unsafe fn test_mm512_zextsi256_si512() {
9935 let a = _mm256_setr_epi64x(17, 18, 19, 20);
9936 let r = _mm512_zextsi256_si512(a);
9937 let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
9938 assert_eq_m512i(r, e);
9939 }
9940
9941 #[simd_test(enable = "avx512f")]
9942 unsafe fn test_mm512_castsi512_si128() {
9943 let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
9944 let r = _mm512_castsi512_si128(a);
9945 let e = _mm_setr_epi64x(17, 18);
9946 assert_eq_m128i(r, e);
9947 }
9948
9949 #[simd_test(enable = "avx512f")]
9950 unsafe fn test_mm512_castsi512_si256() {
9951 let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
9952 let r = _mm512_castsi512_si256(a);
9953 let e = _mm256_setr_epi64x(17, 18, 19, 20);
9954 assert_eq_m256i(r, e);
9955 }
9956
9957 #[simd_test(enable = "avx512f")]
9958 unsafe fn test_mm512_castsi512_ps() {
9959 let a = _mm512_set1_epi64(1 << 62);
9960 let r = _mm512_castsi512_ps(a);
9961 let e = _mm512_set_ps(
9962 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
9963 );
9964 assert_eq_m512(r, e);
9965 }
9966
9967 #[simd_test(enable = "avx512f")]
9968 unsafe fn test_mm512_castsi512_pd() {
9969 let a = _mm512_set1_epi64(1 << 62);
9970 let r = _mm512_castsi512_pd(a);
9971 let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
9972 assert_eq_m512d(r, e);
9973 }
9974
9975 #[simd_test(enable = "avx512f")]
9976 unsafe fn test_mm512_broadcastq_epi64() {
9977 let a = _mm_setr_epi64x(17, 18);
9978 let r = _mm512_broadcastq_epi64(a);
9979 let e = _mm512_set1_epi64(17);
9980 assert_eq_m512i(r, e);
9981 }
9982
9983 #[simd_test(enable = "avx512f")]
9984 unsafe fn test_mm512_mask_broadcastq_epi64() {
9985 let src = _mm512_set1_epi64(18);
9986 let a = _mm_setr_epi64x(17, 18);
9987 let r = _mm512_mask_broadcastq_epi64(src, 0, a);
9988 assert_eq_m512i(r, src);
9989 let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
9990 let e = _mm512_set1_epi64(17);
9991 assert_eq_m512i(r, e);
9992 }
9993
9994 #[simd_test(enable = "avx512f")]
9995 unsafe fn test_mm512_maskz_broadcastq_epi64() {
9996 let a = _mm_setr_epi64x(17, 18);
9997 let r = _mm512_maskz_broadcastq_epi64(0, a);
9998 assert_eq_m512i(r, _mm512_setzero_si512());
9999 let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10000 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10001 assert_eq_m512i(r, e);
10002 }
10003
10004 #[simd_test(enable = "avx512f,avx512vl")]
10005 unsafe fn test_mm256_mask_broadcastq_epi64() {
10006 let src = _mm256_set1_epi64x(18);
10007 let a = _mm_set_epi64x(17, 18);
10008 let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10009 assert_eq_m256i(r, src);
10010 let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10011 let e = _mm256_set1_epi64x(18);
10012 assert_eq_m256i(r, e);
10013 }
10014
10015 #[simd_test(enable = "avx512f,avx512vl")]
10016 unsafe fn test_mm256_maskz_broadcastq_epi64() {
10017 let a = _mm_set_epi64x(17, 18);
10018 let r = _mm256_maskz_broadcastq_epi64(0, a);
10019 assert_eq_m256i(r, _mm256_setzero_si256());
10020 let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10021 let e = _mm256_set1_epi64x(18);
10022 assert_eq_m256i(r, e);
10023 }
10024
10025 #[simd_test(enable = "avx512f,avx512vl")]
10026 unsafe fn test_mm_mask_broadcastq_epi64() {
10027 let src = _mm_set1_epi64x(18);
10028 let a = _mm_set_epi64x(17, 18);
10029 let r = _mm_mask_broadcastq_epi64(src, 0, a);
10030 assert_eq_m128i(r, src);
10031 let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10032 let e = _mm_set1_epi64x(18);
10033 assert_eq_m128i(r, e);
10034 }
10035
10036 #[simd_test(enable = "avx512f,avx512vl")]
10037 unsafe fn test_mm_maskz_broadcastq_epi64() {
10038 let a = _mm_set_epi64x(17, 18);
10039 let r = _mm_maskz_broadcastq_epi64(0, a);
10040 assert_eq_m128i(r, _mm_setzero_si128());
10041 let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10042 let e = _mm_set1_epi64x(18);
10043 assert_eq_m128i(r, e);
10044 }
10045
10046 #[simd_test(enable = "avx512f")]
10047 unsafe fn test_mm512_broadcastsd_pd() {
10048 let a = _mm_set_pd(17., 18.);
10049 let r = _mm512_broadcastsd_pd(a);
10050 let e = _mm512_set1_pd(18.);
10051 assert_eq_m512d(r, e);
10052 }
10053
10054 #[simd_test(enable = "avx512f")]
10055 unsafe fn test_mm512_mask_broadcastsd_pd() {
10056 let src = _mm512_set1_pd(18.);
10057 let a = _mm_set_pd(17., 18.);
10058 let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10059 assert_eq_m512d(r, src);
10060 let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10061 let e = _mm512_set1_pd(18.);
10062 assert_eq_m512d(r, e);
10063 }
10064
10065 #[simd_test(enable = "avx512f")]
10066 unsafe fn test_mm512_maskz_broadcastsd_pd() {
10067 let a = _mm_set_pd(17., 18.);
10068 let r = _mm512_maskz_broadcastsd_pd(0, a);
10069 assert_eq_m512d(r, _mm512_setzero_pd());
10070 let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10071 let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10072 assert_eq_m512d(r, e);
10073 }
10074
10075 #[simd_test(enable = "avx512f,avx512vl")]
10076 unsafe fn test_mm256_mask_broadcastsd_pd() {
10077 let src = _mm256_set1_pd(18.);
10078 let a = _mm_set_pd(17., 18.);
10079 let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10080 assert_eq_m256d(r, src);
10081 let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10082 let e = _mm256_set1_pd(18.);
10083 assert_eq_m256d(r, e);
10084 }
10085
10086 #[simd_test(enable = "avx512f,avx512vl")]
10087 unsafe fn test_mm256_maskz_broadcastsd_pd() {
10088 let a = _mm_set_pd(17., 18.);
10089 let r = _mm256_maskz_broadcastsd_pd(0, a);
10090 assert_eq_m256d(r, _mm256_setzero_pd());
10091 let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10092 let e = _mm256_set1_pd(18.);
10093 assert_eq_m256d(r, e);
10094 }
10095
10096 #[simd_test(enable = "avx512f")]
10097 unsafe fn test_mm512_broadcast_i64x4() {
10098 let a = _mm256_set_epi64x(17, 18, 19, 20);
10099 let r = _mm512_broadcast_i64x4(a);
10100 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10101 assert_eq_m512i(r, e);
10102 }
10103
10104 #[simd_test(enable = "avx512f")]
10105 unsafe fn test_mm512_mask_broadcast_i64x4() {
10106 let src = _mm512_set1_epi64(18);
10107 let a = _mm256_set_epi64x(17, 18, 19, 20);
10108 let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10109 assert_eq_m512i(r, src);
10110 let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10111 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10112 assert_eq_m512i(r, e);
10113 }
10114
10115 #[simd_test(enable = "avx512f")]
10116 unsafe fn test_mm512_maskz_broadcast_i64x4() {
10117 let a = _mm256_set_epi64x(17, 18, 19, 20);
10118 let r = _mm512_maskz_broadcast_i64x4(0, a);
10119 assert_eq_m512i(r, _mm512_setzero_si512());
10120 let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10121 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10122 assert_eq_m512i(r, e);
10123 }
10124
10125 #[simd_test(enable = "avx512f")]
10126 unsafe fn test_mm512_broadcast_f64x4() {
10127 let a = _mm256_set_pd(17., 18., 19., 20.);
10128 let r = _mm512_broadcast_f64x4(a);
10129 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10130 assert_eq_m512d(r, e);
10131 }
10132
10133 #[simd_test(enable = "avx512f")]
10134 unsafe fn test_mm512_mask_broadcast_f64x4() {
10135 let src = _mm512_set1_pd(18.);
10136 let a = _mm256_set_pd(17., 18., 19., 20.);
10137 let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10138 assert_eq_m512d(r, src);
10139 let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10140 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10141 assert_eq_m512d(r, e);
10142 }
10143
10144 #[simd_test(enable = "avx512f")]
10145 unsafe fn test_mm512_maskz_broadcast_f64x4() {
10146 let a = _mm256_set_pd(17., 18., 19., 20.);
10147 let r = _mm512_maskz_broadcast_f64x4(0, a);
10148 assert_eq_m512d(r, _mm512_setzero_pd());
10149 let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10150 let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10151 assert_eq_m512d(r, e);
10152 }
10153
10154 #[simd_test(enable = "avx512f")]
10155 unsafe fn test_mm512_mask_blend_epi64() {
10156 let a = _mm512_set1_epi64(1);
10157 let b = _mm512_set1_epi64(2);
10158 let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10159 let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10160 assert_eq_m512i(r, e);
10161 }
10162
10163 #[simd_test(enable = "avx512f,avx512vl")]
10164 unsafe fn test_mm256_mask_blend_epi64() {
10165 let a = _mm256_set1_epi64x(1);
10166 let b = _mm256_set1_epi64x(2);
10167 let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10168 let e = _mm256_set1_epi64x(2);
10169 assert_eq_m256i(r, e);
10170 }
10171
10172 #[simd_test(enable = "avx512f,avx512vl")]
10173 unsafe fn test_mm_mask_blend_epi64() {
10174 let a = _mm_set1_epi64x(1);
10175 let b = _mm_set1_epi64x(2);
10176 let r = _mm_mask_blend_epi64(0b00000011, a, b);
10177 let e = _mm_set1_epi64x(2);
10178 assert_eq_m128i(r, e);
10179 }
10180
10181 #[simd_test(enable = "avx512f")]
10182 unsafe fn test_mm512_mask_blend_pd() {
10183 let a = _mm512_set1_pd(1.);
10184 let b = _mm512_set1_pd(2.);
10185 let r = _mm512_mask_blend_pd(0b11110000, a, b);
10186 let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10187 assert_eq_m512d(r, e);
10188 }
10189
10190 #[simd_test(enable = "avx512f,avx512vl")]
10191 unsafe fn test_mm256_mask_blend_pd() {
10192 let a = _mm256_set1_pd(1.);
10193 let b = _mm256_set1_pd(2.);
10194 let r = _mm256_mask_blend_pd(0b00001111, a, b);
10195 let e = _mm256_set1_pd(2.);
10196 assert_eq_m256d(r, e);
10197 }
10198
10199 #[simd_test(enable = "avx512f,avx512vl")]
10200 unsafe fn test_mm_mask_blend_pd() {
10201 let a = _mm_set1_pd(1.);
10202 let b = _mm_set1_pd(2.);
10203 let r = _mm_mask_blend_pd(0b00000011, a, b);
10204 let e = _mm_set1_pd(2.);
10205 assert_eq_m128d(r, e);
10206 }
10207
10208 #[simd_test(enable = "avx512f")]
10209 unsafe fn test_mm512_unpackhi_epi64() {
10210 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10211 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10212 let r = _mm512_unpackhi_epi64(a, b);
10213 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10214 assert_eq_m512i(r, e);
10215 }
10216
10217 #[simd_test(enable = "avx512f")]
10218 unsafe fn test_mm512_mask_unpackhi_epi64() {
10219 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10220 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10221 let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10222 assert_eq_m512i(r, a);
10223 let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10224 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10225 assert_eq_m512i(r, e);
10226 }
10227
10228 #[simd_test(enable = "avx512f")]
10229 unsafe fn test_mm512_maskz_unpackhi_epi64() {
10230 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10231 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10232 let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10233 assert_eq_m512i(r, _mm512_setzero_si512());
10234 let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10235 let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10236 assert_eq_m512i(r, e);
10237 }
10238
10239 #[simd_test(enable = "avx512f,avx512vl")]
10240 unsafe fn test_mm256_mask_unpackhi_epi64() {
10241 let a = _mm256_set_epi64x(1, 2, 3, 4);
10242 let b = _mm256_set_epi64x(17, 18, 19, 20);
10243 let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10244 assert_eq_m256i(r, a);
10245 let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10246 let e = _mm256_set_epi64x(17, 1, 19, 3);
10247 assert_eq_m256i(r, e);
10248 }
10249
10250 #[simd_test(enable = "avx512f,avx512vl")]
10251 unsafe fn test_mm256_maskz_unpackhi_epi64() {
10252 let a = _mm256_set_epi64x(1, 2, 3, 4);
10253 let b = _mm256_set_epi64x(17, 18, 19, 20);
10254 let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10255 assert_eq_m256i(r, _mm256_setzero_si256());
10256 let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10257 let e = _mm256_set_epi64x(17, 1, 19, 3);
10258 assert_eq_m256i(r, e);
10259 }
10260
10261 #[simd_test(enable = "avx512f,avx512vl")]
10262 unsafe fn test_mm_mask_unpackhi_epi64() {
10263 let a = _mm_set_epi64x(1, 2);
10264 let b = _mm_set_epi64x(17, 18);
10265 let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10266 assert_eq_m128i(r, a);
10267 let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10268 let e = _mm_set_epi64x(17, 1);
10269 assert_eq_m128i(r, e);
10270 }
10271
10272 #[simd_test(enable = "avx512f,avx512vl")]
10273 unsafe fn test_mm_maskz_unpackhi_epi64() {
10274 let a = _mm_set_epi64x(1, 2);
10275 let b = _mm_set_epi64x(17, 18);
10276 let r = _mm_maskz_unpackhi_epi64(0, a, b);
10277 assert_eq_m128i(r, _mm_setzero_si128());
10278 let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10279 let e = _mm_set_epi64x(17, 1);
10280 assert_eq_m128i(r, e);
10281 }
10282
10283 #[simd_test(enable = "avx512f")]
10284 unsafe fn test_mm512_unpackhi_pd() {
10285 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10286 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10287 let r = _mm512_unpackhi_pd(a, b);
10288 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10289 assert_eq_m512d(r, e);
10290 }
10291
10292 #[simd_test(enable = "avx512f")]
10293 unsafe fn test_mm512_mask_unpackhi_pd() {
10294 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10295 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10296 let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10297 assert_eq_m512d(r, a);
10298 let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10299 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10300 assert_eq_m512d(r, e);
10301 }
10302
10303 #[simd_test(enable = "avx512f")]
10304 unsafe fn test_mm512_maskz_unpackhi_pd() {
10305 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10306 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10307 let r = _mm512_maskz_unpackhi_pd(0, a, b);
10308 assert_eq_m512d(r, _mm512_setzero_pd());
10309 let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
10310 let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
10311 assert_eq_m512d(r, e);
10312 }
10313
10314 #[simd_test(enable = "avx512f,avx512vl")]
10315 unsafe fn test_mm256_mask_unpackhi_pd() {
10316 let a = _mm256_set_pd(1., 2., 3., 4.);
10317 let b = _mm256_set_pd(17., 18., 19., 20.);
10318 let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
10319 assert_eq_m256d(r, a);
10320 let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
10321 let e = _mm256_set_pd(17., 1., 19., 3.);
10322 assert_eq_m256d(r, e);
10323 }
10324
10325 #[simd_test(enable = "avx512f,avx512vl")]
10326 unsafe fn test_mm256_maskz_unpackhi_pd() {
10327 let a = _mm256_set_pd(1., 2., 3., 4.);
10328 let b = _mm256_set_pd(17., 18., 19., 20.);
10329 let r = _mm256_maskz_unpackhi_pd(0, a, b);
10330 assert_eq_m256d(r, _mm256_setzero_pd());
10331 let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
10332 let e = _mm256_set_pd(17., 1., 19., 3.);
10333 assert_eq_m256d(r, e);
10334 }
10335
10336 #[simd_test(enable = "avx512f,avx512vl")]
10337 unsafe fn test_mm_mask_unpackhi_pd() {
10338 let a = _mm_set_pd(1., 2.);
10339 let b = _mm_set_pd(17., 18.);
10340 let r = _mm_mask_unpackhi_pd(a, 0, a, b);
10341 assert_eq_m128d(r, a);
10342 let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
10343 let e = _mm_set_pd(17., 1.);
10344 assert_eq_m128d(r, e);
10345 }
10346
10347 #[simd_test(enable = "avx512f,avx512vl")]
10348 unsafe fn test_mm_maskz_unpackhi_pd() {
10349 let a = _mm_set_pd(1., 2.);
10350 let b = _mm_set_pd(17., 18.);
10351 let r = _mm_maskz_unpackhi_pd(0, a, b);
10352 assert_eq_m128d(r, _mm_setzero_pd());
10353 let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
10354 let e = _mm_set_pd(17., 1.);
10355 assert_eq_m128d(r, e);
10356 }
10357
10358 #[simd_test(enable = "avx512f")]
10359 unsafe fn test_mm512_unpacklo_epi64() {
10360 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10361 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10362 let r = _mm512_unpacklo_epi64(a, b);
10363 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
10364 assert_eq_m512i(r, e);
10365 }
10366
10367 #[simd_test(enable = "avx512f")]
10368 unsafe fn test_mm512_mask_unpacklo_epi64() {
10369 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10370 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10371 let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
10372 assert_eq_m512i(r, a);
10373 let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
10374 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
10375 assert_eq_m512i(r, e);
10376 }
10377
10378 #[simd_test(enable = "avx512f")]
10379 unsafe fn test_mm512_maskz_unpacklo_epi64() {
10380 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10381 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10382 let r = _mm512_maskz_unpacklo_epi64(0, a, b);
10383 assert_eq_m512i(r, _mm512_setzero_si512());
10384 let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
10385 let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
10386 assert_eq_m512i(r, e);
10387 }
10388
10389 #[simd_test(enable = "avx512f,avx512vl")]
10390 unsafe fn test_mm256_mask_unpacklo_epi64() {
10391 let a = _mm256_set_epi64x(1, 2, 3, 4);
10392 let b = _mm256_set_epi64x(17, 18, 19, 20);
10393 let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
10394 assert_eq_m256i(r, a);
10395 let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
10396 let e = _mm256_set_epi64x(18, 2, 20, 4);
10397 assert_eq_m256i(r, e);
10398 }
10399
10400 #[simd_test(enable = "avx512f,avx512vl")]
10401 unsafe fn test_mm256_maskz_unpacklo_epi64() {
10402 let a = _mm256_set_epi64x(1, 2, 3, 4);
10403 let b = _mm256_set_epi64x(17, 18, 19, 20);
10404 let r = _mm256_maskz_unpacklo_epi64(0, a, b);
10405 assert_eq_m256i(r, _mm256_setzero_si256());
10406 let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
10407 let e = _mm256_set_epi64x(18, 2, 20, 4);
10408 assert_eq_m256i(r, e);
10409 }
10410
10411 #[simd_test(enable = "avx512f,avx512vl")]
10412 unsafe fn test_mm_mask_unpacklo_epi64() {
10413 let a = _mm_set_epi64x(1, 2);
10414 let b = _mm_set_epi64x(17, 18);
10415 let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
10416 assert_eq_m128i(r, a);
10417 let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
10418 let e = _mm_set_epi64x(18, 2);
10419 assert_eq_m128i(r, e);
10420 }
10421
10422 #[simd_test(enable = "avx512f,avx512vl")]
10423 unsafe fn test_mm_maskz_unpacklo_epi64() {
10424 let a = _mm_set_epi64x(1, 2);
10425 let b = _mm_set_epi64x(17, 18);
10426 let r = _mm_maskz_unpacklo_epi64(0, a, b);
10427 assert_eq_m128i(r, _mm_setzero_si128());
10428 let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
10429 let e = _mm_set_epi64x(18, 2);
10430 assert_eq_m128i(r, e);
10431 }
10432
10433 #[simd_test(enable = "avx512f")]
10434 unsafe fn test_mm512_unpacklo_pd() {
10435 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10436 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10437 let r = _mm512_unpacklo_pd(a, b);
10438 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
10439 assert_eq_m512d(r, e);
10440 }
10441
10442 #[simd_test(enable = "avx512f")]
10443 unsafe fn test_mm512_mask_unpacklo_pd() {
10444 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10445 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10446 let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
10447 assert_eq_m512d(r, a);
10448 let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
10449 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
10450 assert_eq_m512d(r, e);
10451 }
10452
10453 #[simd_test(enable = "avx512f")]
10454 unsafe fn test_mm512_maskz_unpacklo_pd() {
10455 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10456 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10457 let r = _mm512_maskz_unpacklo_pd(0, a, b);
10458 assert_eq_m512d(r, _mm512_setzero_pd());
10459 let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
10460 let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
10461 assert_eq_m512d(r, e);
10462 }
10463
10464 #[simd_test(enable = "avx512f,avx512vl")]
10465 unsafe fn test_mm256_mask_unpacklo_pd() {
10466 let a = _mm256_set_pd(1., 2., 3., 4.);
10467 let b = _mm256_set_pd(17., 18., 19., 20.);
10468 let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
10469 assert_eq_m256d(r, a);
10470 let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
10471 let e = _mm256_set_pd(18., 2., 20., 4.);
10472 assert_eq_m256d(r, e);
10473 }
10474
10475 #[simd_test(enable = "avx512f,avx512vl")]
10476 unsafe fn test_mm256_maskz_unpacklo_pd() {
10477 let a = _mm256_set_pd(1., 2., 3., 4.);
10478 let b = _mm256_set_pd(17., 18., 19., 20.);
10479 let r = _mm256_maskz_unpacklo_pd(0, a, b);
10480 assert_eq_m256d(r, _mm256_setzero_pd());
10481 let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
10482 let e = _mm256_set_pd(18., 2., 20., 4.);
10483 assert_eq_m256d(r, e);
10484 }
10485
10486 #[simd_test(enable = "avx512f,avx512vl")]
10487 unsafe fn test_mm_mask_unpacklo_pd() {
10488 let a = _mm_set_pd(1., 2.);
10489 let b = _mm_set_pd(17., 18.);
10490 let r = _mm_mask_unpacklo_pd(a, 0, a, b);
10491 assert_eq_m128d(r, a);
10492 let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
10493 let e = _mm_set_pd(18., 2.);
10494 assert_eq_m128d(r, e);
10495 }
10496
10497 #[simd_test(enable = "avx512f,avx512vl")]
10498 unsafe fn test_mm_maskz_unpacklo_pd() {
10499 let a = _mm_set_pd(1., 2.);
10500 let b = _mm_set_pd(17., 18.);
10501 let r = _mm_maskz_unpacklo_pd(0, a, b);
10502 assert_eq_m128d(r, _mm_setzero_pd());
10503 let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
10504 let e = _mm_set_pd(18., 2.);
10505 assert_eq_m128d(r, e);
10506 }
10507
10508 #[simd_test(enable = "avx512f")]
10509 unsafe fn test_mm512_alignr_epi64() {
10510 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
10511 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
10512 let r = _mm512_alignr_epi64::<0>(a, b);
10513 assert_eq_m512i(r, b);
10514 let r = _mm512_alignr_epi64::<8>(a, b);
10515 assert_eq_m512i(r, b);
10516 let r = _mm512_alignr_epi64::<1>(a, b);
10517 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
10518 assert_eq_m512i(r, e);
10519 }
10520
10521 #[simd_test(enable = "avx512f")]
10522 unsafe fn test_mm512_mask_alignr_epi64() {
10523 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
10524 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
10525 let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
10526 assert_eq_m512i(r, a);
10527 let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
10528 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
10529 assert_eq_m512i(r, e);
10530 }
10531
10532 #[simd_test(enable = "avx512f")]
10533 unsafe fn test_mm512_maskz_alignr_epi64() {
10534 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
10535 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
10536 let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
10537 assert_eq_m512i(r, _mm512_setzero_si512());
10538 let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
10539 let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
10540 assert_eq_m512i(r, e);
10541 }
10542
10543 #[simd_test(enable = "avx512f,avx512vl")]
10544 unsafe fn test_mm256_alignr_epi64() {
10545 let a = _mm256_set_epi64x(4, 3, 2, 1);
10546 let b = _mm256_set_epi64x(8, 7, 6, 5);
10547 let r = _mm256_alignr_epi64::<0>(a, b);
10548 let e = _mm256_set_epi64x(8, 7, 6, 5);
10549 assert_eq_m256i(r, e);
10550 let r = _mm256_alignr_epi64::<6>(a, b);
10551 let e = _mm256_set_epi64x(6, 5, 4, 3);
10552 assert_eq_m256i(r, e);
10553 }
10554
10555 #[simd_test(enable = "avx512f,avx512vl")]
10556 unsafe fn test_mm256_mask_alignr_epi64() {
10557 let a = _mm256_set_epi64x(4, 3, 2, 1);
10558 let b = _mm256_set_epi64x(8, 7, 6, 5);
10559 let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
10560 assert_eq_m256i(r, a);
10561 let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
10562 let e = _mm256_set_epi64x(8, 7, 6, 5);
10563 assert_eq_m256i(r, e);
10564 }
10565
10566 #[simd_test(enable = "avx512f,avx512vl")]
10567 unsafe fn test_mm256_maskz_alignr_epi64() {
10568 let a = _mm256_set_epi64x(4, 3, 2, 1);
10569 let b = _mm256_set_epi64x(8, 7, 6, 5);
10570 let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
10571 assert_eq_m256i(r, _mm256_setzero_si256());
10572 let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
10573 let e = _mm256_set_epi64x(8, 7, 6, 5);
10574 assert_eq_m256i(r, e);
10575 }
10576
10577 #[simd_test(enable = "avx512f,avx512vl")]
10578 unsafe fn test_mm_alignr_epi64() {
10579 let a = _mm_set_epi64x(2, 1);
10580 let b = _mm_set_epi64x(4, 3);
10581 let r = _mm_alignr_epi64::<0>(a, b);
10582 let e = _mm_set_epi64x(4, 3);
10583 assert_eq_m128i(r, e);
10584 }
10585
10586 #[simd_test(enable = "avx512f,avx512vl")]
10587 unsafe fn test_mm_mask_alignr_epi64() {
10588 let a = _mm_set_epi64x(2, 1);
10589 let b = _mm_set_epi64x(4, 3);
10590 let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
10591 assert_eq_m128i(r, a);
10592 let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
10593 let e = _mm_set_epi64x(4, 3);
10594 assert_eq_m128i(r, e);
10595 }
10596
10597 #[simd_test(enable = "avx512f,avx512vl")]
10598 unsafe fn test_mm_maskz_alignr_epi64() {
10599 let a = _mm_set_epi64x(2, 1);
10600 let b = _mm_set_epi64x(4, 3);
10601 let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
10602 assert_eq_m128i(r, _mm_setzero_si128());
10603 let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
10604 let e = _mm_set_epi64x(4, 3);
10605 assert_eq_m128i(r, e);
10606 }
10607
10608 #[simd_test(enable = "avx512f")]
10609 unsafe fn test_mm512_and_epi64() {
10610 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10611 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10612 let r = _mm512_and_epi64(a, b);
10613 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10614 assert_eq_m512i(r, e);
10615 }
10616
10617 #[simd_test(enable = "avx512f")]
10618 unsafe fn test_mm512_mask_and_epi64() {
10619 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10620 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10621 let r = _mm512_mask_and_epi64(a, 0, a, b);
10622 assert_eq_m512i(r, a);
10623 let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
10624 let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10625 assert_eq_m512i(r, e);
10626 }
10627
10628 #[simd_test(enable = "avx512f")]
10629 unsafe fn test_mm512_maskz_and_epi64() {
10630 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10631 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10632 let r = _mm512_maskz_and_epi64(0, a, b);
10633 assert_eq_m512i(r, _mm512_setzero_si512());
10634 let r = _mm512_maskz_and_epi64(0b00001111, a, b);
10635 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10636 assert_eq_m512i(r, e);
10637 }
10638
10639 #[simd_test(enable = "avx512f,avx512vl")]
10640 unsafe fn test_mm256_mask_and_epi64() {
10641 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10642 let b = _mm256_set1_epi64x(1 << 0);
10643 let r = _mm256_mask_and_epi64(a, 0, a, b);
10644 assert_eq_m256i(r, a);
10645 let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
10646 let e = _mm256_set1_epi64x(1 << 0);
10647 assert_eq_m256i(r, e);
10648 }
10649
10650 #[simd_test(enable = "avx512f,avx512vl")]
10651 unsafe fn test_mm256_maskz_and_epi64() {
10652 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10653 let b = _mm256_set1_epi64x(1 << 0);
10654 let r = _mm256_maskz_and_epi64(0, a, b);
10655 assert_eq_m256i(r, _mm256_setzero_si256());
10656 let r = _mm256_maskz_and_epi64(0b00001111, a, b);
10657 let e = _mm256_set1_epi64x(1 << 0);
10658 assert_eq_m256i(r, e);
10659 }
10660
10661 #[simd_test(enable = "avx512f,avx512vl")]
10662 unsafe fn test_mm_mask_and_epi64() {
10663 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10664 let b = _mm_set1_epi64x(1 << 0);
10665 let r = _mm_mask_and_epi64(a, 0, a, b);
10666 assert_eq_m128i(r, a);
10667 let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
10668 let e = _mm_set1_epi64x(1 << 0);
10669 assert_eq_m128i(r, e);
10670 }
10671
10672 #[simd_test(enable = "avx512f,avx512vl")]
10673 unsafe fn test_mm_maskz_and_epi64() {
10674 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10675 let b = _mm_set1_epi64x(1 << 0);
10676 let r = _mm_maskz_and_epi64(0, a, b);
10677 assert_eq_m128i(r, _mm_setzero_si128());
10678 let r = _mm_maskz_and_epi64(0b00000011, a, b);
10679 let e = _mm_set1_epi64x(1 << 0);
10680 assert_eq_m128i(r, e);
10681 }
10682
10683 #[simd_test(enable = "avx512f")]
10684 unsafe fn test_mm512_and_si512() {
10685 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10686 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10687 let r = _mm512_and_epi64(a, b);
10688 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10689 assert_eq_m512i(r, e);
10690 }
10691
10692 #[simd_test(enable = "avx512f")]
10693 unsafe fn test_mm512_or_epi64() {
10694 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10695 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10696 let r = _mm512_or_epi64(a, b);
10697 #[rustfmt::skip]
10698 let e = _mm512_set_epi64(
10699 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
10700 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
10701 );
10702 assert_eq_m512i(r, e);
10703 }
10704
10705 #[simd_test(enable = "avx512f")]
10706 unsafe fn test_mm512_mask_or_epi64() {
10707 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10708 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10709 let r = _mm512_mask_or_epi64(a, 0, a, b);
10710 assert_eq_m512i(r, a);
10711 let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
10712 #[rustfmt::skip]
10713 let e = _mm512_set_epi64(
10714 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
10715 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
10716 );
10717 assert_eq_m512i(r, e);
10718 }
10719
10720 #[simd_test(enable = "avx512f")]
10721 unsafe fn test_mm512_maskz_or_epi64() {
10722 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10723 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10724 let r = _mm512_maskz_or_epi64(0, a, b);
10725 assert_eq_m512i(r, _mm512_setzero_si512());
10726 let r = _mm512_maskz_or_epi64(0b00001111, a, b);
10727 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10728 assert_eq_m512i(r, e);
10729 }
10730
10731 #[simd_test(enable = "avx512f,avx512vl")]
10732 unsafe fn test_mm256_or_epi64() {
10733 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10734 let b = _mm256_set1_epi64x(1 << 13);
10735 let r = _mm256_or_epi64(a, b);
10736 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10737 assert_eq_m256i(r, e);
10738 }
10739
10740 #[simd_test(enable = "avx512f,avx512vl")]
10741 unsafe fn test_mm256_mask_or_epi64() {
10742 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10743 let b = _mm256_set1_epi64x(1 << 13);
10744 let r = _mm256_mask_or_epi64(a, 0, a, b);
10745 assert_eq_m256i(r, a);
10746 let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
10747 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10748 assert_eq_m256i(r, e);
10749 }
10750
10751 #[simd_test(enable = "avx512f,avx512vl")]
10752 unsafe fn test_mm256_maskz_or_epi64() {
10753 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10754 let b = _mm256_set1_epi64x(1 << 13);
10755 let r = _mm256_maskz_or_epi64(0, a, b);
10756 assert_eq_m256i(r, _mm256_setzero_si256());
10757 let r = _mm256_maskz_or_epi64(0b00001111, a, b);
10758 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10759 assert_eq_m256i(r, e);
10760 }
10761
10762 #[simd_test(enable = "avx512f,avx512vl")]
10763 unsafe fn test_mm_or_epi64() {
10764 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10765 let b = _mm_set1_epi64x(1 << 13);
10766 let r = _mm_or_epi64(a, b);
10767 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10768 assert_eq_m128i(r, e);
10769 }
10770
10771 #[simd_test(enable = "avx512f,avx512vl")]
10772 unsafe fn test_mm_mask_or_epi64() {
10773 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10774 let b = _mm_set1_epi64x(1 << 13);
10775 let r = _mm_mask_or_epi64(a, 0, a, b);
10776 assert_eq_m128i(r, a);
10777 let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
10778 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10779 assert_eq_m128i(r, e);
10780 }
10781
10782 #[simd_test(enable = "avx512f,avx512vl")]
10783 unsafe fn test_mm_maskz_or_epi64() {
10784 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10785 let b = _mm_set1_epi64x(1 << 13);
10786 let r = _mm_maskz_or_epi64(0, a, b);
10787 assert_eq_m128i(r, _mm_setzero_si128());
10788 let r = _mm_maskz_or_epi64(0b00000011, a, b);
10789 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10790 assert_eq_m128i(r, e);
10791 }
10792
10793 #[simd_test(enable = "avx512f")]
10794 unsafe fn test_mm512_or_si512() {
10795 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10796 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10797 let r = _mm512_or_epi64(a, b);
10798 #[rustfmt::skip]
10799 let e = _mm512_set_epi64(
10800 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
10801 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
10802 );
10803 assert_eq_m512i(r, e);
10804 }
10805
10806 #[simd_test(enable = "avx512f")]
10807 unsafe fn test_mm512_xor_epi64() {
10808 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10809 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10810 let r = _mm512_xor_epi64(a, b);
10811 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
10812 assert_eq_m512i(r, e);
10813 }
10814
10815 #[simd_test(enable = "avx512f")]
10816 unsafe fn test_mm512_mask_xor_epi64() {
10817 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10818 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10819 let r = _mm512_mask_xor_epi64(a, 0, a, b);
10820 assert_eq_m512i(r, a);
10821 let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
10822 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
10823 assert_eq_m512i(r, e);
10824 }
10825
10826 #[simd_test(enable = "avx512f")]
10827 unsafe fn test_mm512_maskz_xor_epi64() {
10828 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10829 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10830 let r = _mm512_maskz_xor_epi64(0, a, b);
10831 assert_eq_m512i(r, _mm512_setzero_si512());
10832 let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
10833 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
10834 assert_eq_m512i(r, e);
10835 }
10836
10837 #[simd_test(enable = "avx512f,avx512vl")]
10838 unsafe fn test_mm256_xor_epi64() {
10839 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10840 let b = _mm256_set1_epi64x(1 << 13);
10841 let r = _mm256_xor_epi64(a, b);
10842 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10843 assert_eq_m256i(r, e);
10844 }
10845
10846 #[simd_test(enable = "avx512f,avx512vl")]
10847 unsafe fn test_mm256_mask_xor_epi64() {
10848 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10849 let b = _mm256_set1_epi64x(1 << 13);
10850 let r = _mm256_mask_xor_epi64(a, 0, a, b);
10851 assert_eq_m256i(r, a);
10852 let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
10853 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10854 assert_eq_m256i(r, e);
10855 }
10856
10857 #[simd_test(enable = "avx512f,avx512vl")]
10858 unsafe fn test_mm256_maskz_xor_epi64() {
10859 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10860 let b = _mm256_set1_epi64x(1 << 13);
10861 let r = _mm256_maskz_xor_epi64(0, a, b);
10862 assert_eq_m256i(r, _mm256_setzero_si256());
10863 let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
10864 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10865 assert_eq_m256i(r, e);
10866 }
10867
10868 #[simd_test(enable = "avx512f,avx512vl")]
10869 unsafe fn test_mm_xor_epi64() {
10870 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10871 let b = _mm_set1_epi64x(1 << 13);
10872 let r = _mm_xor_epi64(a, b);
10873 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10874 assert_eq_m128i(r, e);
10875 }
10876
10877 #[simd_test(enable = "avx512f,avx512vl")]
10878 unsafe fn test_mm_mask_xor_epi64() {
10879 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10880 let b = _mm_set1_epi64x(1 << 13);
10881 let r = _mm_mask_xor_epi64(a, 0, a, b);
10882 assert_eq_m128i(r, a);
10883 let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
10884 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10885 assert_eq_m128i(r, e);
10886 }
10887
10888 #[simd_test(enable = "avx512f,avx512vl")]
10889 unsafe fn test_mm_maskz_xor_epi64() {
10890 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10891 let b = _mm_set1_epi64x(1 << 13);
10892 let r = _mm_maskz_xor_epi64(0, a, b);
10893 assert_eq_m128i(r, _mm_setzero_si128());
10894 let r = _mm_maskz_xor_epi64(0b00000011, a, b);
10895 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10896 assert_eq_m128i(r, e);
10897 }
10898
10899 #[simd_test(enable = "avx512f")]
10900 unsafe fn test_mm512_xor_si512() {
10901 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10902 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10903 let r = _mm512_xor_epi64(a, b);
10904 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
10905 assert_eq_m512i(r, e);
10906 }
10907
10908 #[simd_test(enable = "avx512f")]
10909 unsafe fn test_mm512_andnot_epi64() {
10910 let a = _mm512_set1_epi64(0);
10911 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10912 let r = _mm512_andnot_epi64(a, b);
10913 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
10914 assert_eq_m512i(r, e);
10915 }
10916
10917 #[simd_test(enable = "avx512f")]
10918 unsafe fn test_mm512_mask_andnot_epi64() {
10919 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
10920 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10921 let r = _mm512_mask_andnot_epi64(a, 0, a, b);
10922 assert_eq_m512i(r, a);
10923 let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
10924 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
10925 assert_eq_m512i(r, e);
10926 }
10927
10928 #[simd_test(enable = "avx512f")]
10929 unsafe fn test_mm512_maskz_andnot_epi64() {
10930 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
10931 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10932 let r = _mm512_maskz_andnot_epi64(0, a, b);
10933 assert_eq_m512i(r, _mm512_setzero_si512());
10934 let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
10935 #[rustfmt::skip]
10936 let e = _mm512_set_epi64(
10937 0, 0, 0, 0,
10938 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
10939 );
10940 assert_eq_m512i(r, e);
10941 }
10942
10943 #[simd_test(enable = "avx512f,avx512vl")]
10944 unsafe fn test_mm256_mask_andnot_epi64() {
10945 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
10946 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10947 let r = _mm256_mask_andnot_epi64(a, 0, a, b);
10948 assert_eq_m256i(r, a);
10949 let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
10950 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10951 assert_eq_m256i(r, e);
10952 }
10953
10954 #[simd_test(enable = "avx512f,avx512vl")]
10955 unsafe fn test_mm256_maskz_andnot_epi64() {
10956 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
10957 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10958 let r = _mm256_maskz_andnot_epi64(0, a, b);
10959 assert_eq_m256i(r, _mm256_setzero_si256());
10960 let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
10961 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10962 assert_eq_m256i(r, e);
10963 }
10964
10965 #[simd_test(enable = "avx512f,avx512vl")]
10966 unsafe fn test_mm_mask_andnot_epi64() {
10967 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
10968 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
10969 let r = _mm_mask_andnot_epi64(a, 0, a, b);
10970 assert_eq_m128i(r, a);
10971 let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
10972 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
10973 assert_eq_m128i(r, e);
10974 }
10975
10976 #[simd_test(enable = "avx512f,avx512vl")]
10977 unsafe fn test_mm_maskz_andnot_epi64() {
10978 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
10979 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
10980 let r = _mm_maskz_andnot_epi64(0, a, b);
10981 assert_eq_m128i(r, _mm_setzero_si128());
10982 let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
10983 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
10984 assert_eq_m128i(r, e);
10985 }
10986
10987 #[simd_test(enable = "avx512f")]
10988 unsafe fn test_mm512_andnot_si512() {
10989 let a = _mm512_set1_epi64(0);
10990 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10991 let r = _mm512_andnot_si512(a, b);
10992 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
10993 assert_eq_m512i(r, e);
10994 }
10995
10996 #[simd_test(enable = "avx512f")]
10997 unsafe fn test_mm512_reduce_add_epi64() {
10998 let a = _mm512_set1_epi64(1);
10999 let e: i64 = _mm512_reduce_add_epi64(a);
11000 assert_eq!(8, e);
11001 }
11002
11003 #[simd_test(enable = "avx512f")]
11004 unsafe fn test_mm512_mask_reduce_add_epi64() {
11005 let a = _mm512_set1_epi64(1);
11006 let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11007 assert_eq!(4, e);
11008 }
11009
11010 #[simd_test(enable = "avx512f")]
11011 unsafe fn test_mm512_reduce_add_pd() {
11012 let a = _mm512_set1_pd(1.);
11013 let e: f64 = _mm512_reduce_add_pd(a);
11014 assert_eq!(8., e);
11015 }
11016
11017 #[simd_test(enable = "avx512f")]
11018 unsafe fn test_mm512_mask_reduce_add_pd() {
11019 let a = _mm512_set1_pd(1.);
11020 let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11021 assert_eq!(4., e);
11022 }
11023
11024 #[simd_test(enable = "avx512f")]
11025 unsafe fn test_mm512_reduce_mul_epi64() {
11026 let a = _mm512_set1_epi64(2);
11027 let e: i64 = _mm512_reduce_mul_epi64(a);
11028 assert_eq!(256, e);
11029 }
11030
11031 #[simd_test(enable = "avx512f")]
11032 unsafe fn test_mm512_mask_reduce_mul_epi64() {
11033 let a = _mm512_set1_epi64(2);
11034 let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11035 assert_eq!(16, e);
11036 }
11037
11038 #[simd_test(enable = "avx512f")]
11039 unsafe fn test_mm512_reduce_mul_pd() {
11040 let a = _mm512_set1_pd(2.);
11041 let e: f64 = _mm512_reduce_mul_pd(a);
11042 assert_eq!(256., e);
11043 }
11044
11045 #[simd_test(enable = "avx512f")]
11046 unsafe fn test_mm512_mask_reduce_mul_pd() {
11047 let a = _mm512_set1_pd(2.);
11048 let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11049 assert_eq!(16., e);
11050 }
11051
11052 #[simd_test(enable = "avx512f")]
11053 unsafe fn test_mm512_reduce_max_epi64() {
11054 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11055 let e: i64 = _mm512_reduce_max_epi64(a);
11056 assert_eq!(7, e);
11057 }
11058
11059 #[simd_test(enable = "avx512f")]
11060 unsafe fn test_mm512_mask_reduce_max_epi64() {
11061 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11062 let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11063 assert_eq!(3, e);
11064 }
11065
11066 #[simd_test(enable = "avx512f")]
11067 unsafe fn test_mm512_reduce_max_epu64() {
11068 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11069 let e: u64 = _mm512_reduce_max_epu64(a);
11070 assert_eq!(7, e);
11071 }
11072
11073 #[simd_test(enable = "avx512f")]
11074 unsafe fn test_mm512_mask_reduce_max_epu64() {
11075 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11076 let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11077 assert_eq!(3, e);
11078 }
11079
11080 #[simd_test(enable = "avx512f")]
11081 unsafe fn test_mm512_reduce_max_pd() {
11082 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11083 let e: f64 = _mm512_reduce_max_pd(a);
11084 assert_eq!(7., e);
11085 }
11086
11087 #[simd_test(enable = "avx512f")]
11088 unsafe fn test_mm512_mask_reduce_max_pd() {
11089 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11090 let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11091 assert_eq!(3., e);
11092 }
11093
11094 #[simd_test(enable = "avx512f")]
11095 unsafe fn test_mm512_reduce_min_epi64() {
11096 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11097 let e: i64 = _mm512_reduce_min_epi64(a);
11098 assert_eq!(0, e);
11099 }
11100
11101 #[simd_test(enable = "avx512f")]
11102 unsafe fn test_mm512_mask_reduce_min_epi64() {
11103 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11104 let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11105 assert_eq!(0, e);
11106 }
11107
11108 #[simd_test(enable = "avx512f")]
11109 unsafe fn test_mm512_reduce_min_epu64() {
11110 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11111 let e: u64 = _mm512_reduce_min_epu64(a);
11112 assert_eq!(0, e);
11113 }
11114
11115 #[simd_test(enable = "avx512f")]
11116 unsafe fn test_mm512_mask_reduce_min_epu64() {
11117 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11118 let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11119 assert_eq!(0, e);
11120 }
11121
11122 #[simd_test(enable = "avx512f")]
11123 unsafe fn test_mm512_reduce_min_pd() {
11124 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11125 let e: f64 = _mm512_reduce_min_pd(a);
11126 assert_eq!(0., e);
11127 }
11128
11129 #[simd_test(enable = "avx512f")]
11130 unsafe fn test_mm512_mask_reduce_min_pd() {
11131 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11132 let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11133 assert_eq!(0., e);
11134 }
11135
11136 #[simd_test(enable = "avx512f")]
11137 unsafe fn test_mm512_reduce_and_epi64() {
11138 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11139 let e: i64 = _mm512_reduce_and_epi64(a);
11140 assert_eq!(0, e);
11141 }
11142
11143 #[simd_test(enable = "avx512f")]
11144 unsafe fn test_mm512_mask_reduce_and_epi64() {
11145 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11146 let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11147 assert_eq!(1, e);
11148 }
11149
11150 #[simd_test(enable = "avx512f")]
11151 unsafe fn test_mm512_reduce_or_epi64() {
11152 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11153 let e: i64 = _mm512_reduce_or_epi64(a);
11154 assert_eq!(3, e);
11155 }
11156
11157 #[simd_test(enable = "avx512f")]
11158 unsafe fn test_mm512_mask_reduce_or_epi64() {
11159 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11160 let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11161 assert_eq!(1, e);
11162 }
11163
11164 #[simd_test(enable = "avx512f")]
11165 unsafe fn test_mm512_extractf64x4_pd() {
11166 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11167 let r = _mm512_extractf64x4_pd::<1>(a);
11168 let e = _mm256_setr_pd(5., 6., 7., 8.);
11169 assert_eq_m256d(r, e);
11170 }
11171
11172 #[simd_test(enable = "avx512f")]
11173 unsafe fn test_mm512_mask_extractf64x4_pd() {
11174 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11175 let src = _mm256_set1_pd(100.);
11176 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11177 assert_eq_m256d(r, src);
11178 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11179 let e = _mm256_setr_pd(5., 6., 7., 8.);
11180 assert_eq_m256d(r, e);
11181 }
11182
11183 #[simd_test(enable = "avx512f")]
11184 unsafe fn test_mm512_maskz_extractf64x4_pd() {
11185 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11186 let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11187 assert_eq_m256d(r, _mm256_setzero_pd());
11188 let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11189 let e = _mm256_setr_pd(5., 0., 0., 0.);
11190 assert_eq_m256d(r, e);
11191 }
11192
11193 #[simd_test(enable = "avx512f")]
11194 unsafe fn test_mm512_extracti64x4_epi64() {
11195 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11196 let r = _mm512_extracti64x4_epi64::<0x1>(a);
11197 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11198 assert_eq_m256i(r, e);
11199 }
11200
11201 #[simd_test(enable = "avx512f")]
11202 unsafe fn test_mm512_mask_extracti64x4_epi64() {
11203 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11204 let src = _mm256_set1_epi64x(100);
11205 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11206 assert_eq_m256i(r, src);
11207 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11208 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11209 assert_eq_m256i(r, e);
11210 }
11211
11212 #[simd_test(enable = "avx512f")]
11213 unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11214 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11215 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11216 assert_eq_m256i(r, _mm256_setzero_si256());
11217 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11218 let e = _mm256_setr_epi64x(5, 0, 0, 0);
11219 assert_eq_m256i(r, e);
11220 }
11221
11222 #[simd_test(enable = "avx512f")]
11223 unsafe fn test_mm512_mask_compress_epi64() {
11224 let src = _mm512_set1_epi64(200);
11225 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11226 let r = _mm512_mask_compress_epi64(src, 0, a);
11227 assert_eq_m512i(r, src);
11228 let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11229 let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11230 assert_eq_m512i(r, e);
11231 }
11232
11233 #[simd_test(enable = "avx512f")]
11234 unsafe fn test_mm512_maskz_compress_epi64() {
11235 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11236 let r = _mm512_maskz_compress_epi64(0, a);
11237 assert_eq_m512i(r, _mm512_setzero_si512());
11238 let r = _mm512_maskz_compress_epi64(0b01010101, a);
11239 let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11240 assert_eq_m512i(r, e);
11241 }
11242
11243 #[simd_test(enable = "avx512f,avx512vl")]
11244 unsafe fn test_mm256_mask_compress_epi64() {
11245 let src = _mm256_set1_epi64x(200);
11246 let a = _mm256_set_epi64x(0, 1, 2, 3);
11247 let r = _mm256_mask_compress_epi64(src, 0, a);
11248 assert_eq_m256i(r, src);
11249 let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11250 let e = _mm256_set_epi64x(200, 200, 1, 3);
11251 assert_eq_m256i(r, e);
11252 }
11253
11254 #[simd_test(enable = "avx512f,avx512vl")]
11255 unsafe fn test_mm256_maskz_compress_epi64() {
11256 let a = _mm256_set_epi64x(0, 1, 2, 3);
11257 let r = _mm256_maskz_compress_epi64(0, a);
11258 assert_eq_m256i(r, _mm256_setzero_si256());
11259 let r = _mm256_maskz_compress_epi64(0b00000101, a);
11260 let e = _mm256_set_epi64x(0, 0, 1, 3);
11261 assert_eq_m256i(r, e);
11262 }
11263
11264 #[simd_test(enable = "avx512f,avx512vl")]
11265 unsafe fn test_mm_mask_compress_epi64() {
11266 let src = _mm_set1_epi64x(200);
11267 let a = _mm_set_epi64x(0, 1);
11268 let r = _mm_mask_compress_epi64(src, 0, a);
11269 assert_eq_m128i(r, src);
11270 let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11271 let e = _mm_set_epi64x(200, 1);
11272 assert_eq_m128i(r, e);
11273 }
11274
11275 #[simd_test(enable = "avx512f,avx512vl")]
11276 unsafe fn test_mm_maskz_compress_epi64() {
11277 let a = _mm_set_epi64x(0, 1);
11278 let r = _mm_maskz_compress_epi64(0, a);
11279 assert_eq_m128i(r, _mm_setzero_si128());
11280 let r = _mm_maskz_compress_epi64(0b00000001, a);
11281 let e = _mm_set_epi64x(0, 1);
11282 assert_eq_m128i(r, e);
11283 }
11284
11285 #[simd_test(enable = "avx512f")]
11286 unsafe fn test_mm512_mask_compress_pd() {
11287 let src = _mm512_set1_pd(200.);
11288 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11289 let r = _mm512_mask_compress_pd(src, 0, a);
11290 assert_eq_m512d(r, src);
11291 let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11292 let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11293 assert_eq_m512d(r, e);
11294 }
11295
11296 #[simd_test(enable = "avx512f")]
11297 unsafe fn test_mm512_maskz_compress_pd() {
11298 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11299 let r = _mm512_maskz_compress_pd(0, a);
11300 assert_eq_m512d(r, _mm512_setzero_pd());
11301 let r = _mm512_maskz_compress_pd(0b01010101, a);
11302 let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11303 assert_eq_m512d(r, e);
11304 }
11305
11306 #[simd_test(enable = "avx512f,avx512vl")]
11307 unsafe fn test_mm256_mask_compress_pd() {
11308 let src = _mm256_set1_pd(200.);
11309 let a = _mm256_set_pd(0., 1., 2., 3.);
11310 let r = _mm256_mask_compress_pd(src, 0, a);
11311 assert_eq_m256d(r, src);
11312 let r = _mm256_mask_compress_pd(src, 0b00000101, a);
11313 let e = _mm256_set_pd(200., 200., 1., 3.);
11314 assert_eq_m256d(r, e);
11315 }
11316
11317 #[simd_test(enable = "avx512f,avx512vl")]
11318 unsafe fn test_mm256_maskz_compress_pd() {
11319 let a = _mm256_set_pd(0., 1., 2., 3.);
11320 let r = _mm256_maskz_compress_pd(0, a);
11321 assert_eq_m256d(r, _mm256_setzero_pd());
11322 let r = _mm256_maskz_compress_pd(0b00000101, a);
11323 let e = _mm256_set_pd(0., 0., 1., 3.);
11324 assert_eq_m256d(r, e);
11325 }
11326
11327 #[simd_test(enable = "avx512f,avx512vl")]
11328 unsafe fn test_mm_mask_compress_pd() {
11329 let src = _mm_set1_pd(200.);
11330 let a = _mm_set_pd(0., 1.);
11331 let r = _mm_mask_compress_pd(src, 0, a);
11332 assert_eq_m128d(r, src);
11333 let r = _mm_mask_compress_pd(src, 0b00000001, a);
11334 let e = _mm_set_pd(200., 1.);
11335 assert_eq_m128d(r, e);
11336 }
11337
11338 #[simd_test(enable = "avx512f,avx512vl")]
11339 unsafe fn test_mm_maskz_compress_pd() {
11340 let a = _mm_set_pd(0., 1.);
11341 let r = _mm_maskz_compress_pd(0, a);
11342 assert_eq_m128d(r, _mm_setzero_pd());
11343 let r = _mm_maskz_compress_pd(0b00000001, a);
11344 let e = _mm_set_pd(0., 1.);
11345 assert_eq_m128d(r, e);
11346 }
11347
11348 #[simd_test(enable = "avx512f")]
11349 unsafe fn test_mm512_mask_expand_epi64() {
11350 let src = _mm512_set1_epi64(200);
11351 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11352 let r = _mm512_mask_expand_epi64(src, 0, a);
11353 assert_eq_m512i(r, src);
11354 let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
11355 let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
11356 assert_eq_m512i(r, e);
11357 }
11358
11359 #[simd_test(enable = "avx512f")]
11360 unsafe fn test_mm512_maskz_expand_epi64() {
11361 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11362 let r = _mm512_maskz_expand_epi64(0, a);
11363 assert_eq_m512i(r, _mm512_setzero_si512());
11364 let r = _mm512_maskz_expand_epi64(0b01010101, a);
11365 let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
11366 assert_eq_m512i(r, e);
11367 }
11368
11369 #[simd_test(enable = "avx512f,avx512vl")]
11370 unsafe fn test_mm256_mask_expand_epi64() {
11371 let src = _mm256_set1_epi64x(200);
11372 let a = _mm256_set_epi64x(0, 1, 2, 3);
11373 let r = _mm256_mask_expand_epi64(src, 0, a);
11374 assert_eq_m256i(r, src);
11375 let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
11376 let e = _mm256_set_epi64x(200, 2, 200, 3);
11377 assert_eq_m256i(r, e);
11378 }
11379
11380 #[simd_test(enable = "avx512f,avx512vl")]
11381 unsafe fn test_mm256_maskz_expand_epi64() {
11382 let a = _mm256_set_epi64x(0, 1, 2, 3);
11383 let r = _mm256_maskz_expand_epi64(0, a);
11384 assert_eq_m256i(r, _mm256_setzero_si256());
11385 let r = _mm256_maskz_expand_epi64(0b00000101, a);
11386 let e = _mm256_set_epi64x(0, 2, 0, 3);
11387 assert_eq_m256i(r, e);
11388 }
11389
11390 #[simd_test(enable = "avx512f,avx512vl")]
11391 unsafe fn test_mm_mask_expand_epi64() {
11392 let src = _mm_set1_epi64x(200);
11393 let a = _mm_set_epi64x(0, 1);
11394 let r = _mm_mask_expand_epi64(src, 0, a);
11395 assert_eq_m128i(r, src);
11396 let r = _mm_mask_expand_epi64(src, 0b00000001, a);
11397 let e = _mm_set_epi64x(200, 1);
11398 assert_eq_m128i(r, e);
11399 }
11400
11401 #[simd_test(enable = "avx512f,avx512vl")]
11402 unsafe fn test_mm_maskz_expand_epi64() {
11403 let a = _mm_set_epi64x(0, 1);
11404 let r = _mm_maskz_expand_epi64(0, a);
11405 assert_eq_m128i(r, _mm_setzero_si128());
11406 let r = _mm_maskz_expand_epi64(0b00000001, a);
11407 let e = _mm_set_epi64x(0, 1);
11408 assert_eq_m128i(r, e);
11409 }
11410
11411 #[simd_test(enable = "avx512f")]
11412 unsafe fn test_mm512_mask_expand_pd() {
11413 let src = _mm512_set1_pd(200.);
11414 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11415 let r = _mm512_mask_expand_pd(src, 0, a);
11416 assert_eq_m512d(r, src);
11417 let r = _mm512_mask_expand_pd(src, 0b01010101, a);
11418 let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
11419 assert_eq_m512d(r, e);
11420 }
11421
11422 #[simd_test(enable = "avx512f")]
11423 unsafe fn test_mm512_maskz_expand_pd() {
11424 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11425 let r = _mm512_maskz_expand_pd(0, a);
11426 assert_eq_m512d(r, _mm512_setzero_pd());
11427 let r = _mm512_maskz_expand_pd(0b01010101, a);
11428 let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
11429 assert_eq_m512d(r, e);
11430 }
11431
11432 #[simd_test(enable = "avx512f,avx512vl")]
11433 unsafe fn test_mm256_mask_expand_pd() {
11434 let src = _mm256_set1_pd(200.);
11435 let a = _mm256_set_pd(0., 1., 2., 3.);
11436 let r = _mm256_mask_expand_pd(src, 0, a);
11437 assert_eq_m256d(r, src);
11438 let r = _mm256_mask_expand_pd(src, 0b00000101, a);
11439 let e = _mm256_set_pd(200., 2., 200., 3.);
11440 assert_eq_m256d(r, e);
11441 }
11442
11443 #[simd_test(enable = "avx512f,avx512vl")]
11444 unsafe fn test_mm256_maskz_expand_pd() {
11445 let a = _mm256_set_pd(0., 1., 2., 3.);
11446 let r = _mm256_maskz_expand_pd(0, a);
11447 assert_eq_m256d(r, _mm256_setzero_pd());
11448 let r = _mm256_maskz_expand_pd(0b00000101, a);
11449 let e = _mm256_set_pd(0., 2., 0., 3.);
11450 assert_eq_m256d(r, e);
11451 }
11452
11453 #[simd_test(enable = "avx512f,avx512vl")]
11454 unsafe fn test_mm_mask_expand_pd() {
11455 let src = _mm_set1_pd(200.);
11456 let a = _mm_set_pd(0., 1.);
11457 let r = _mm_mask_expand_pd(src, 0, a);
11458 assert_eq_m128d(r, src);
11459 let r = _mm_mask_expand_pd(src, 0b00000001, a);
11460 let e = _mm_set_pd(200., 1.);
11461 assert_eq_m128d(r, e);
11462 }
11463
11464 #[simd_test(enable = "avx512f,avx512vl")]
11465 unsafe fn test_mm_maskz_expand_pd() {
11466 let a = _mm_set_pd(0., 1.);
11467 let r = _mm_maskz_expand_pd(0, a);
11468 assert_eq_m128d(r, _mm_setzero_pd());
11469 let r = _mm_maskz_expand_pd(0b00000001, a);
11470 let e = _mm_set_pd(0., 1.);
11471 assert_eq_m128d(r, e);
11472 }
11473
11474 #[simd_test(enable = "avx512f")]
11475 unsafe fn test_mm512_loadu_epi64() {
11476 let a = &[4, 3, 2, 5, -8, -9, -64, -50];
11477 let p = a.as_ptr();
11478 let r = _mm512_loadu_epi64(black_box(p));
11479 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
11480 assert_eq_m512i(r, e);
11481 }
11482
11483 #[simd_test(enable = "avx512f,avx512vl")]
11484 unsafe fn test_mm256_loadu_epi64() {
11485 let a = &[4, 3, 2, 5];
11486 let p = a.as_ptr();
11487 let r = _mm256_loadu_epi64(black_box(p));
11488 let e = _mm256_setr_epi64x(4, 3, 2, 5);
11489 assert_eq_m256i(r, e);
11490 }
11491
11492 #[simd_test(enable = "avx512f,avx512vl")]
11493 unsafe fn test_mm_loadu_epi64() {
11494 let a = &[4, 3];
11495 let p = a.as_ptr();
11496 let r = _mm_loadu_epi64(black_box(p));
11497 let e = _mm_setr_epi64x(4, 3);
11498 assert_eq_m128i(r, e);
11499 }
11500
11501 #[simd_test(enable = "avx512f")]
11502 unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
11503 let a = _mm512_set1_epi64(9);
11504 let mut r = _mm_undefined_si128();
11505 _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11506 let e = _mm_set1_epi16(9);
11507 assert_eq_m128i(r, e);
11508 }
11509
11510 #[simd_test(enable = "avx512f,avx512vl")]
11511 unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
11512 let a = _mm256_set1_epi64x(9);
11513 let mut r = _mm_set1_epi16(0);
11514 _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11515 let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
11516 assert_eq_m128i(r, e);
11517 }
11518
11519 #[simd_test(enable = "avx512f,avx512vl")]
11520 unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
11521 let a = _mm_set1_epi64x(9);
11522 let mut r = _mm_set1_epi16(0);
11523 _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11524 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
11525 assert_eq_m128i(r, e);
11526 }
11527
11528 #[simd_test(enable = "avx512f")]
11529 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
11530 let a = _mm512_set1_epi64(i64::MAX);
11531 let mut r = _mm_undefined_si128();
11532 _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11533 let e = _mm_set1_epi16(i16::MAX);
11534 assert_eq_m128i(r, e);
11535 }
11536
11537 #[simd_test(enable = "avx512f,avx512vl")]
11538 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
11539 let a = _mm256_set1_epi64x(i64::MAX);
11540 let mut r = _mm_set1_epi16(0);
11541 _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11542 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11543 assert_eq_m128i(r, e);
11544 }
11545
11546 #[simd_test(enable = "avx512f,avx512vl")]
11547 unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
11548 let a = _mm_set1_epi64x(i64::MAX);
11549 let mut r = _mm_set1_epi16(0);
11550 _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11551 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
11552 assert_eq_m128i(r, e);
11553 }
11554
11555 #[simd_test(enable = "avx512f")]
11556 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
11557 let a = _mm512_set1_epi64(i64::MAX);
11558 let mut r = _mm_undefined_si128();
11559 _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11560 let e = _mm_set1_epi16(u16::MAX as i16);
11561 assert_eq_m128i(r, e);
11562 }
11563
11564 #[simd_test(enable = "avx512f,avx512vl")]
11565 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
11566 let a = _mm256_set1_epi64x(i64::MAX);
11567 let mut r = _mm_set1_epi16(0);
11568 _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11569 let e = _mm_set_epi16(
11570 0,
11571 0,
11572 0,
11573 0,
11574 u16::MAX as i16,
11575 u16::MAX as i16,
11576 u16::MAX as i16,
11577 u16::MAX as i16,
11578 );
11579 assert_eq_m128i(r, e);
11580 }
11581
11582 #[simd_test(enable = "avx512f,avx512vl")]
11583 unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
11584 let a = _mm_set1_epi64x(i64::MAX);
11585 let mut r = _mm_set1_epi16(0);
11586 _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11587 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
11588 assert_eq_m128i(r, e);
11589 }
11590
11591 #[simd_test(enable = "avx512f")]
11592 unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
11593 let a = _mm512_set1_epi64(9);
11594 let mut r = _mm_set1_epi8(0);
11595 _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11596 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
11597 assert_eq_m128i(r, e);
11598 }
11599
11600 #[simd_test(enable = "avx512f,avx512vl")]
11601 unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
11602 let a = _mm256_set1_epi64x(9);
11603 let mut r = _mm_set1_epi8(0);
11604 _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11605 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
11606 assert_eq_m128i(r, e);
11607 }
11608
11609 #[simd_test(enable = "avx512f,avx512vl")]
11610 unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
11611 let a = _mm_set1_epi64x(9);
11612 let mut r = _mm_set1_epi8(0);
11613 _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11614 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
11615 assert_eq_m128i(r, e);
11616 }
11617
11618 #[simd_test(enable = "avx512f")]
11619 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
11620 let a = _mm512_set1_epi64(i64::MAX);
11621 let mut r = _mm_set1_epi8(0);
11622 _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11623 #[rustfmt::skip]
11624 let e = _mm_set_epi8(
11625 0, 0, 0, 0,
11626 0, 0, 0, 0,
11627 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
11628 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
11629 );
11630 assert_eq_m128i(r, e);
11631 }
11632
11633 #[simd_test(enable = "avx512f,avx512vl")]
11634 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
11635 let a = _mm256_set1_epi64x(i64::MAX);
11636 let mut r = _mm_set1_epi8(0);
11637 _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11638 #[rustfmt::skip]
11639 let e = _mm_set_epi8(
11640 0, 0, 0, 0,
11641 0, 0, 0, 0,
11642 0, 0, 0, 0,
11643 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
11644 );
11645 assert_eq_m128i(r, e);
11646 }
11647
11648 #[simd_test(enable = "avx512f,avx512vl")]
11649 unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
11650 let a = _mm_set1_epi64x(i64::MAX);
11651 let mut r = _mm_set1_epi8(0);
11652 _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11653 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
11654 assert_eq_m128i(r, e);
11655 }
11656
11657 #[simd_test(enable = "avx512f")]
11658 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
11659 let a = _mm512_set1_epi64(i64::MAX);
11660 let mut r = _mm_set1_epi8(0);
11661 _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11662 #[rustfmt::skip]
11663 let e = _mm_set_epi8(
11664 0, 0, 0, 0,
11665 0, 0, 0, 0,
11666 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
11667 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
11668 );
11669 assert_eq_m128i(r, e);
11670 }
11671
11672 #[simd_test(enable = "avx512f,avx512vl")]
11673 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
11674 let a = _mm256_set1_epi64x(i64::MAX);
11675 let mut r = _mm_set1_epi8(0);
11676 _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11677 #[rustfmt::skip]
11678 let e = _mm_set_epi8(
11679 0, 0, 0, 0,
11680 0, 0, 0, 0,
11681 0, 0, 0, 0,
11682 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
11683 );
11684 assert_eq_m128i(r, e);
11685 }
11686
11687 #[simd_test(enable = "avx512f,avx512vl")]
11688 unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
11689 let a = _mm_set1_epi64x(i64::MAX);
11690 let mut r = _mm_set1_epi8(0);
11691 _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11692 #[rustfmt::skip]
11693 let e = _mm_set_epi8(
11694 0, 0, 0, 0,
11695 0, 0, 0, 0,
11696 0, 0, 0, 0,
11697 0, 0, u8::MAX as i8, u8::MAX as i8,
11698 );
11699 assert_eq_m128i(r, e);
11700 }
11701
11702 #[simd_test(enable = "avx512f")]
11703 unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
11704 let a = _mm512_set1_epi64(9);
11705 let mut r = _mm256_undefined_si256();
11706 _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11707 let e = _mm256_set1_epi32(9);
11708 assert_eq_m256i(r, e);
11709 }
11710
11711 #[simd_test(enable = "avx512f,avx512vl")]
11712 unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
11713 let a = _mm256_set1_epi64x(9);
11714 let mut r = _mm_set1_epi32(0);
11715 _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11716 let e = _mm_set_epi32(9, 9, 9, 9);
11717 assert_eq_m128i(r, e);
11718 }
11719
11720 #[simd_test(enable = "avx512f,avx512vl")]
11721 unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
11722 let a = _mm_set1_epi64x(9);
11723 let mut r = _mm_set1_epi16(0);
11724 _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11725 let e = _mm_set_epi32(0, 0, 9, 9);
11726 assert_eq_m128i(r, e);
11727 }
11728
11729 #[simd_test(enable = "avx512f")]
11730 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
11731 let a = _mm512_set1_epi64(i64::MAX);
11732 let mut r = _mm256_undefined_si256();
11733 _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11734 let e = _mm256_set1_epi32(i32::MAX);
11735 assert_eq_m256i(r, e);
11736 }
11737
11738 #[simd_test(enable = "avx512f,avx512vl")]
11739 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
11740 let a = _mm256_set1_epi64x(i64::MAX);
11741 let mut r = _mm_set1_epi32(0);
11742 _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
11743 let e = _mm_set1_epi32(i32::MAX);
11744 assert_eq_m128i(r, e);
11745 }
11746
11747 #[simd_test(enable = "avx512f,avx512vl")]
11748 unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
11749 let a = _mm_set1_epi64x(i64::MAX);
11750 let mut r = _mm_set1_epi16(0);
11751 _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
11752 let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
11753 assert_eq_m128i(r, e);
11754 }
11755
11756 #[simd_test(enable = "avx512f")]
11757 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
11758 let a = _mm512_set1_epi64(i64::MAX);
11759 let mut r = _mm256_undefined_si256();
11760 _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11761 let e = _mm256_set1_epi32(u32::MAX as i32);
11762 assert_eq_m256i(r, e);
11763 }
11764
11765 #[simd_test(enable = "avx512f,avx512vl")]
11766 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
11767 let a = _mm256_set1_epi64x(i64::MAX);
11768 let mut r = _mm_set1_epi32(0);
11769 _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
11770 let e = _mm_set1_epi32(u32::MAX as i32);
11771 assert_eq_m128i(r, e);
11772 }
11773
11774 #[simd_test(enable = "avx512f,avx512vl")]
11775 unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
11776 let a = _mm_set1_epi64x(i64::MAX);
11777 let mut r = _mm_set1_epi16(0);
11778 _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
11779 let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
11780 assert_eq_m128i(r, e);
11781 }
11782
11783 #[simd_test(enable = "avx512f")]
11784 unsafe fn test_mm512_storeu_epi64() {
11785 let a = _mm512_set1_epi64(9);
11786 let mut r = _mm512_set1_epi64(0);
11787 _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
11788 assert_eq_m512i(r, a);
11789 }
11790
11791 #[simd_test(enable = "avx512f,avx512vl")]
11792 unsafe fn test_mm256_storeu_epi64() {
11793 let a = _mm256_set1_epi64x(9);
11794 let mut r = _mm256_set1_epi64x(0);
11795 _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
11796 assert_eq_m256i(r, a);
11797 }
11798
11799 #[simd_test(enable = "avx512f,avx512vl")]
11800 unsafe fn test_mm_storeu_epi64() {
11801 let a = _mm_set1_epi64x(9);
11802 let mut r = _mm_set1_epi64x(0);
11803 _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
11804 assert_eq_m128i(r, a);
11805 }
11806
11807 #[simd_test(enable = "avx512f")]
11808 unsafe fn test_mm512_load_epi64() {
11809 #[repr(align(64))]
11810 struct Align {
11811 data: [i64; 8], // 64 bytes
11812 }
11813 let a = Align {
11814 data: [4, 3, 2, 5, -8, -9, -64, -50],
11815 };
11816 let p = (a.data).as_ptr();
11817 let r = _mm512_load_epi64(black_box(p));
11818 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
11819 assert_eq_m512i(r, e);
11820 }
11821
11822 #[simd_test(enable = "avx512f,avx512vl")]
11823 unsafe fn test_mm256_load_epi64() {
11824 #[repr(align(64))]
11825 struct Align {
11826 data: [i64; 4],
11827 }
11828 let a = Align { data: [4, 3, 2, 5] };
11829 let p = (a.data).as_ptr();
11830 let r = _mm256_load_epi64(black_box(p));
11831 let e = _mm256_set_epi64x(5, 2, 3, 4);
11832 assert_eq_m256i(r, e);
11833 }
11834
11835 #[simd_test(enable = "avx512f,avx512vl")]
11836 unsafe fn test_mm_load_epi64() {
11837 #[repr(align(64))]
11838 struct Align {
11839 data: [i64; 2],
11840 }
11841 let a = Align { data: [4, 3] };
11842 let p = (a.data).as_ptr();
11843 let r = _mm_load_epi64(black_box(p));
11844 let e = _mm_set_epi64x(3, 4);
11845 assert_eq_m128i(r, e);
11846 }
11847
11848 #[simd_test(enable = "avx512f")]
11849 unsafe fn test_mm512_store_epi64() {
11850 let a = _mm512_set1_epi64(9);
11851 let mut r = _mm512_set1_epi64(0);
11852 _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
11853 assert_eq_m512i(r, a);
11854 }
11855
11856 #[simd_test(enable = "avx512f,avx512vl")]
11857 unsafe fn test_mm256_store_epi64() {
11858 let a = _mm256_set1_epi64x(9);
11859 let mut r = _mm256_set1_epi64x(0);
11860 _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
11861 assert_eq_m256i(r, a);
11862 }
11863
11864 #[simd_test(enable = "avx512f,avx512vl")]
11865 unsafe fn test_mm_store_epi64() {
11866 let a = _mm_set1_epi64x(9);
11867 let mut r = _mm_set1_epi64x(0);
11868 _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
11869 assert_eq_m128i(r, a);
11870 }
11871
11872 #[simd_test(enable = "avx512f")]
11873 unsafe fn test_mm512_load_pd() {
11874 #[repr(align(64))]
11875 struct Align {
11876 data: [f64; 8], // 64 bytes
11877 }
11878 let a = Align {
11879 data: [4., 3., 2., 5., -8., -9., -64., -50.],
11880 };
11881 let p = (a.data).as_ptr();
11882 let r = _mm512_load_pd(black_box(p));
11883 let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
11884 assert_eq_m512d(r, e);
11885 }
11886
11887 #[simd_test(enable = "avx512f")]
11888 unsafe fn test_mm512_store_pd() {
11889 let a = _mm512_set1_pd(9.);
11890 let mut r = _mm512_undefined_pd();
11891 _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
11892 assert_eq_m512d(r, a);
11893 }
11894
11895 #[simd_test(enable = "avx512f")]
11896 unsafe fn test_mm512_test_epi64_mask() {
11897 let a = _mm512_set1_epi64(1 << 0);
11898 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
11899 let r = _mm512_test_epi64_mask(a, b);
11900 let e: __mmask8 = 0b11111111;
11901 assert_eq!(r, e);
11902 }
11903
11904 #[simd_test(enable = "avx512f")]
11905 unsafe fn test_mm512_mask_test_epi64_mask() {
11906 let a = _mm512_set1_epi64(1 << 0);
11907 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
11908 let r = _mm512_mask_test_epi64_mask(0, a, b);
11909 assert_eq!(r, 0);
11910 let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
11911 let e: __mmask8 = 0b11111111;
11912 assert_eq!(r, e);
11913 }
11914
11915 #[simd_test(enable = "avx512f,avx512vl")]
11916 unsafe fn test_mm256_test_epi64_mask() {
11917 let a = _mm256_set1_epi64x(1 << 0);
11918 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
11919 let r = _mm256_test_epi64_mask(a, b);
11920 let e: __mmask8 = 0b00001111;
11921 assert_eq!(r, e);
11922 }
11923
11924 #[simd_test(enable = "avx512f,avx512vl")]
11925 unsafe fn test_mm256_mask_test_epi64_mask() {
11926 let a = _mm256_set1_epi64x(1 << 0);
11927 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
11928 let r = _mm256_mask_test_epi64_mask(0, a, b);
11929 assert_eq!(r, 0);
11930 let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
11931 let e: __mmask8 = 0b00001111;
11932 assert_eq!(r, e);
11933 }
11934
11935 #[simd_test(enable = "avx512f,avx512vl")]
11936 unsafe fn test_mm_test_epi64_mask() {
11937 let a = _mm_set1_epi64x(1 << 0);
11938 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
11939 let r = _mm_test_epi64_mask(a, b);
11940 let e: __mmask8 = 0b00000011;
11941 assert_eq!(r, e);
11942 }
11943
11944 #[simd_test(enable = "avx512f,avx512vl")]
11945 unsafe fn test_mm_mask_test_epi64_mask() {
11946 let a = _mm_set1_epi64x(1 << 0);
11947 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
11948 let r = _mm_mask_test_epi64_mask(0, a, b);
11949 assert_eq!(r, 0);
11950 let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
11951 let e: __mmask8 = 0b00000011;
11952 assert_eq!(r, e);
11953 }
11954
11955 #[simd_test(enable = "avx512f")]
11956 unsafe fn test_mm512_testn_epi64_mask() {
11957 let a = _mm512_set1_epi64(1 << 0);
11958 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
11959 let r = _mm512_testn_epi64_mask(a, b);
11960 let e: __mmask8 = 0b00000000;
11961 assert_eq!(r, e);
11962 }
11963
11964 #[simd_test(enable = "avx512f")]
11965 unsafe fn test_mm512_mask_testn_epi64_mask() {
11966 let a = _mm512_set1_epi64(1 << 0);
11967 let b = _mm512_set1_epi64(1 << 1);
11968 let r = _mm512_mask_testn_epi64_mask(0, a, b);
11969 assert_eq!(r, 0);
11970 let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
11971 let e: __mmask8 = 0b11111111;
11972 assert_eq!(r, e);
11973 }
11974
11975 #[simd_test(enable = "avx512f,avx512vl")]
11976 unsafe fn test_mm256_testn_epi64_mask() {
11977 let a = _mm256_set1_epi64x(1 << 0);
11978 let b = _mm256_set1_epi64x(1 << 1);
11979 let r = _mm256_testn_epi64_mask(a, b);
11980 let e: __mmask8 = 0b00001111;
11981 assert_eq!(r, e);
11982 }
11983
11984 #[simd_test(enable = "avx512f,avx512vl")]
11985 unsafe fn test_mm256_mask_testn_epi64_mask() {
11986 let a = _mm256_set1_epi64x(1 << 0);
11987 let b = _mm256_set1_epi64x(1 << 1);
11988 let r = _mm256_mask_testn_epi64_mask(0, a, b);
11989 assert_eq!(r, 0);
11990 let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
11991 let e: __mmask8 = 0b00001111;
11992 assert_eq!(r, e);
11993 }
11994
11995 #[simd_test(enable = "avx512f,avx512vl")]
11996 unsafe fn test_mm_testn_epi64_mask() {
11997 let a = _mm_set1_epi64x(1 << 0);
11998 let b = _mm_set1_epi64x(1 << 1);
11999 let r = _mm_testn_epi64_mask(a, b);
12000 let e: __mmask8 = 0b00000011;
12001 assert_eq!(r, e);
12002 }
12003
12004 #[simd_test(enable = "avx512f,avx512vl")]
12005 unsafe fn test_mm_mask_testn_epi64_mask() {
12006 let a = _mm_set1_epi64x(1 << 0);
12007 let b = _mm_set1_epi64x(1 << 1);
12008 let r = _mm_mask_testn_epi64_mask(0, a, b);
12009 assert_eq!(r, 0);
12010 let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12011 let e: __mmask8 = 0b00000011;
12012 assert_eq!(r, e);
12013 }
12014
12015 #[simd_test(enable = "avx512f")]
12016 unsafe fn test_mm512_stream_pd() {
12017 #[repr(align(64))]
12018 struct Memory {
12019 pub data: [f64; 8],
12020 }
12021 let a = _mm512_set1_pd(7.0);
12022 let mut mem = Memory { data: [-1.0; 8] };
12023
12024 _mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
12025 for i in 0..8 {
12026 assert_eq!(mem.data[i], get_m512d(a, i));
12027 }
12028 }
12029
12030 #[simd_test(enable = "avx512f")]
12031 unsafe fn test_mm512_stream_si512() {
12032 #[repr(align(64))]
12033 struct Memory {
12034 pub data: [i64; 8],
12035 }
12036 let a = _mm512_set1_epi64(7);
12037 let mut mem = Memory { data: [-1; 8] };
12038
12039 _mm512_stream_si512(&mut mem.data[0] as *mut i64, a);
12040 for i in 0..8 {
12041 assert_eq!(mem.data[i], get_m512i(a, i));
12042 }
12043 }
12044
12045 #[simd_test(enable = "avx512f")]
12046 unsafe fn test_mm512_mask_set1_epi64() {
12047 let src = _mm512_set1_epi64(2);
12048 let a: i64 = 11;
12049 let r = _mm512_mask_set1_epi64(src, 0, a);
12050 assert_eq_m512i(r, src);
12051 let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12052 let e = _mm512_set1_epi64(11);
12053 assert_eq_m512i(r, e);
12054 }
12055
12056 #[simd_test(enable = "avx512f")]
12057 unsafe fn test_mm512_maskz_set1_epi64() {
12058 let a: i64 = 11;
12059 let r = _mm512_maskz_set1_epi64(0, a);
12060 assert_eq_m512i(r, _mm512_setzero_si512());
12061 let r = _mm512_maskz_set1_epi64(0b11111111, a);
12062 let e = _mm512_set1_epi64(11);
12063 assert_eq_m512i(r, e);
12064 }
12065
12066 #[simd_test(enable = "avx512f,avx512vl")]
12067 unsafe fn test_mm256_mask_set1_epi64() {
12068 let src = _mm256_set1_epi64x(2);
12069 let a: i64 = 11;
12070 let r = _mm256_mask_set1_epi64(src, 0, a);
12071 assert_eq_m256i(r, src);
12072 let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12073 let e = _mm256_set1_epi64x(11);
12074 assert_eq_m256i(r, e);
12075 }
12076
12077 #[simd_test(enable = "avx512f,avx512vl")]
12078 unsafe fn test_mm256_maskz_set1_epi64() {
12079 let a: i64 = 11;
12080 let r = _mm256_maskz_set1_epi64(0, a);
12081 assert_eq_m256i(r, _mm256_setzero_si256());
12082 let r = _mm256_maskz_set1_epi64(0b00001111, a);
12083 let e = _mm256_set1_epi64x(11);
12084 assert_eq_m256i(r, e);
12085 }
12086
12087 #[simd_test(enable = "avx512f,avx512vl")]
12088 unsafe fn test_mm_mask_set1_epi64() {
12089 let src = _mm_set1_epi64x(2);
12090 let a: i64 = 11;
12091 let r = _mm_mask_set1_epi64(src, 0, a);
12092 assert_eq_m128i(r, src);
12093 let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12094 let e = _mm_set1_epi64x(11);
12095 assert_eq_m128i(r, e);
12096 }
12097
12098 #[simd_test(enable = "avx512f,avx512vl")]
12099 unsafe fn test_mm_maskz_set1_epi64() {
12100 let a: i64 = 11;
12101 let r = _mm_maskz_set1_epi64(0, a);
12102 assert_eq_m128i(r, _mm_setzero_si128());
12103 let r = _mm_maskz_set1_epi64(0b00000011, a);
12104 let e = _mm_set1_epi64x(11);
12105 assert_eq_m128i(r, e);
12106 }
12107
12108 #[simd_test(enable = "avx512f")]
12109 unsafe fn test_mm_cvtsd_i64() {
12110 let a = _mm_set_pd(1., -1.5);
12111 let r = _mm_cvtsd_i64(a);
12112 let e: i64 = -2;
12113 assert_eq!(r, e);
12114 }
12115
12116 #[simd_test(enable = "avx512f")]
12117 unsafe fn test_mm_cvtss_i64() {
12118 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12119 let r = _mm_cvtss_i64(a);
12120 let e: i64 = -2;
12121 assert_eq!(r, e);
12122 }
12123
12124 #[simd_test(enable = "avx512f")]
12125 unsafe fn test_mm_cvt_roundi64_ss() {
12126 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12127 let b: i64 = 9;
12128 let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12129 let e = _mm_set_ps(0., -0.5, 1., 9.);
12130 assert_eq_m128(r, e);
12131 }
12132
12133 #[simd_test(enable = "avx512f")]
12134 unsafe fn test_mm_cvt_roundsi64_ss() {
12135 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12136 let b: i64 = 9;
12137 let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12138 let e = _mm_set_ps(0., -0.5, 1., 9.);
12139 assert_eq_m128(r, e);
12140 }
12141
12142 #[simd_test(enable = "avx512f")]
12143 unsafe fn test_mm_cvti64_ss() {
12144 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12145 let b: i64 = 9;
12146 let r = _mm_cvti64_ss(a, b);
12147 let e = _mm_set_ps(0., -0.5, 1., 9.);
12148 assert_eq_m128(r, e);
12149 }
12150
12151 #[simd_test(enable = "avx512f")]
12152 unsafe fn test_mm_cvti64_sd() {
12153 let a = _mm_set_pd(1., -1.5);
12154 let b: i64 = 9;
12155 let r = _mm_cvti64_sd(a, b);
12156 let e = _mm_set_pd(1., 9.);
12157 assert_eq_m128d(r, e);
12158 }
12159
12160 #[simd_test(enable = "avx512f")]
12161 unsafe fn test_mm_cvt_roundsd_si64() {
12162 let a = _mm_set_pd(1., -1.5);
12163 let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12164 let e: i64 = -1;
12165 assert_eq!(r, e);
12166 }
12167
12168 #[simd_test(enable = "avx512f")]
12169 unsafe fn test_mm_cvt_roundsd_i64() {
12170 let a = _mm_set_pd(1., -1.5);
12171 let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12172 let e: i64 = -1;
12173 assert_eq!(r, e);
12174 }
12175
12176 #[simd_test(enable = "avx512f")]
12177 unsafe fn test_mm_cvt_roundsd_u64() {
12178 let a = _mm_set_pd(1., f64::MAX);
12179 let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12180 let e: u64 = u64::MAX;
12181 assert_eq!(r, e);
12182 }
12183
12184 #[simd_test(enable = "avx512f")]
12185 unsafe fn test_mm_cvtsd_u64() {
12186 let a = _mm_set_pd(1., -1.5);
12187 let r = _mm_cvtsd_u64(a);
12188 let e: u64 = u64::MAX;
12189 assert_eq!(r, e);
12190 }
12191
12192 #[simd_test(enable = "avx512f")]
12193 unsafe fn test_mm_cvt_roundss_i64() {
12194 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12195 let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12196 let e: i64 = -1;
12197 assert_eq!(r, e);
12198 }
12199
12200 #[simd_test(enable = "avx512f")]
12201 unsafe fn test_mm_cvt_roundss_si64() {
12202 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12203 let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12204 let e: i64 = -1;
12205 assert_eq!(r, e);
12206 }
12207
12208 #[simd_test(enable = "avx512f")]
12209 unsafe fn test_mm_cvt_roundss_u64() {
12210 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12211 let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12212 let e: u64 = u64::MAX;
12213 assert_eq!(r, e);
12214 }
12215
12216 #[simd_test(enable = "avx512f")]
12217 unsafe fn test_mm_cvtss_u64() {
12218 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12219 let r = _mm_cvtss_u64(a);
12220 let e: u64 = u64::MAX;
12221 assert_eq!(r, e);
12222 }
12223
12224 #[simd_test(enable = "avx512f")]
12225 unsafe fn test_mm_cvttsd_i64() {
12226 let a = _mm_set_pd(1., -1.5);
12227 let r = _mm_cvttsd_i64(a);
12228 let e: i64 = -2;
12229 assert_eq!(r, e);
12230 }
12231
12232 #[simd_test(enable = "avx512f")]
12233 unsafe fn test_mm_cvtt_roundsd_i64() {
12234 let a = _mm_set_pd(1., -1.5);
12235 let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_CUR_DIRECTION>(a);
12236 let e: i64 = -2;
12237 assert_eq!(r, e);
12238 }
12239
12240 #[simd_test(enable = "avx512f")]
12241 unsafe fn test_mm_cvtt_roundsd_si64() {
12242 let a = _mm_set_pd(1., -1.5);
12243 let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_CUR_DIRECTION>(a);
12244 let e: i64 = -2;
12245 assert_eq!(r, e);
12246 }
12247
12248 #[simd_test(enable = "avx512f")]
12249 unsafe fn test_mm_cvtt_roundsd_u64() {
12250 let a = _mm_set_pd(1., -1.5);
12251 let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_CUR_DIRECTION>(a);
12252 let e: u64 = u64::MAX;
12253 assert_eq!(r, e);
12254 }
12255
12256 #[simd_test(enable = "avx512f")]
12257 unsafe fn test_mm_cvttsd_u64() {
12258 let a = _mm_set_pd(1., -1.5);
12259 let r = _mm_cvttsd_u64(a);
12260 let e: u64 = u64::MAX;
12261 assert_eq!(r, e);
12262 }
12263
12264 #[simd_test(enable = "avx512f")]
12265 unsafe fn test_mm_cvttss_i64() {
12266 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12267 let r = _mm_cvttss_i64(a);
12268 let e: i64 = -2;
12269 assert_eq!(r, e);
12270 }
12271
12272 #[simd_test(enable = "avx512f")]
12273 unsafe fn test_mm_cvtt_roundss_i64() {
12274 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12275 let r = _mm_cvtt_roundss_i64::<_MM_FROUND_CUR_DIRECTION>(a);
12276 let e: i64 = -2;
12277 assert_eq!(r, e);
12278 }
12279
12280 #[simd_test(enable = "avx512f")]
12281 unsafe fn test_mm_cvtt_roundss_si64() {
12282 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12283 let r = _mm_cvtt_roundss_si64::<_MM_FROUND_CUR_DIRECTION>(a);
12284 let e: i64 = -2;
12285 assert_eq!(r, e);
12286 }
12287
12288 #[simd_test(enable = "avx512f")]
12289 unsafe fn test_mm_cvtt_roundss_u64() {
12290 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12291 let r = _mm_cvtt_roundss_u64::<_MM_FROUND_CUR_DIRECTION>(a);
12292 let e: u64 = u64::MAX;
12293 assert_eq!(r, e);
12294 }
12295
12296 #[simd_test(enable = "avx512f")]
12297 unsafe fn test_mm_cvttss_u64() {
12298 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12299 let r = _mm_cvttss_u64(a);
12300 let e: u64 = u64::MAX;
12301 assert_eq!(r, e);
12302 }
12303
12304 #[simd_test(enable = "avx512f")]
12305 unsafe fn test_mm_cvtu64_ss() {
12306 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12307 let b: u64 = 9;
12308 let r = _mm_cvtu64_ss(a, b);
12309 let e = _mm_set_ps(0., -0.5, 1., 9.);
12310 assert_eq_m128(r, e);
12311 }
12312
12313 #[simd_test(enable = "avx512f")]
12314 unsafe fn test_mm_cvtu64_sd() {
12315 let a = _mm_set_pd(1., -1.5);
12316 let b: u64 = 9;
12317 let r = _mm_cvtu64_sd(a, b);
12318 let e = _mm_set_pd(1., 9.);
12319 assert_eq_m128d(r, e);
12320 }
12321
12322 #[simd_test(enable = "avx512f")]
12323 unsafe fn test_mm_cvt_roundu64_ss() {
12324 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12325 let b: u64 = 9;
12326 let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12327 let e = _mm_set_ps(0., -0.5, 1., 9.);
12328 assert_eq_m128(r, e);
12329 }
12330
12331 #[simd_test(enable = "avx512f")]
12332 unsafe fn test_mm_cvt_roundu64_sd() {
12333 let a = _mm_set_pd(1., -1.5);
12334 let b: u64 = 9;
12335 let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12336 let e = _mm_set_pd(1., 9.);
12337 assert_eq_m128d(r, e);
12338 }
12339
12340 #[simd_test(enable = "avx512f")]
12341 unsafe fn test_mm_cvt_roundi64_sd() {
12342 let a = _mm_set_pd(1., -1.5);
12343 let b: i64 = 9;
12344 let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12345 let e = _mm_set_pd(1., 9.);
12346 assert_eq_m128d(r, e);
12347 }
12348
12349 #[simd_test(enable = "avx512f")]
12350 unsafe fn test_mm_cvt_roundsi64_sd() {
12351 let a = _mm_set_pd(1., -1.5);
12352 let b: i64 = 9;
12353 let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12354 let e = _mm_set_pd(1., 9.);
12355 assert_eq_m128d(r, e);
12356 }
12357}
12358