1use crate::{
2 core_arch::{simd::*, x86::*, x86_64::*},
3 mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
10///
11/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
12#[inline]
13#[target_feature(enable = "avx512f")]
14#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15#[cfg_attr(test, assert_instr(vcvtsd2si))]
16pub fn _mm_cvtsd_i64(a: __m128d) -> i64 {
17 _mm_cvtsd_si64(a)
18}
19
20/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
21///
22/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
23#[inline]
24#[target_feature(enable = "avx512f")]
25#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
26#[cfg_attr(test, assert_instr(vcvtss2si))]
27pub fn _mm_cvtss_i64(a: __m128) -> i64 {
28 _mm_cvtss_si64(a)
29}
30
31/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
32///
33/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
34#[inline]
35#[target_feature(enable = "avx512f")]
36#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
37#[cfg_attr(test, assert_instr(vcvtss2usi))]
38pub fn _mm_cvtss_u64(a: __m128) -> u64 {
39 unsafe { vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
40}
41
42/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
43///
44/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
45#[inline]
46#[target_feature(enable = "avx512f")]
47#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
48#[cfg_attr(test, assert_instr(vcvtsd2usi))]
49pub fn _mm_cvtsd_u64(a: __m128d) -> u64 {
50 unsafe { vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
51}
52
53/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
54///
55/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti64_ss&expand=1643)
56#[inline]
57#[target_feature(enable = "avx512f")]
58#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
59#[cfg_attr(test, assert_instr(vcvtsi2ss))]
60pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
61 unsafe {
62 let b: f32 = b as f32;
63 simd_insert!(a, 0, b)
64 }
65}
66
67/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
68///
69/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
70#[inline]
71#[target_feature(enable = "avx512f")]
72#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
73#[cfg_attr(test, assert_instr(vcvtsi2sd))]
74pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
75 unsafe {
76 let b: f64 = b as f64;
77 simd_insert!(a, 0, b)
78 }
79}
80
81/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
82///
83/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
84#[inline]
85#[target_feature(enable = "avx512f")]
86#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
87#[cfg_attr(test, assert_instr(vcvtusi2ss))]
88pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
89 unsafe {
90 let b: f32 = b as f32;
91 simd_insert!(a, 0, b)
92 }
93}
94
95/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
96///
97/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
98#[inline]
99#[target_feature(enable = "avx512f")]
100#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
101#[cfg_attr(test, assert_instr(vcvtusi2sd))]
102pub fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
103 unsafe {
104 let b: f64 = b as f64;
105 simd_insert!(a, 0, b)
106 }
107}
108
109/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
110///
111/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
112#[inline]
113#[target_feature(enable = "avx512f")]
114#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
115#[cfg_attr(test, assert_instr(vcvttsd2si))]
116pub fn _mm_cvttsd_i64(a: __m128d) -> i64 {
117 unsafe { vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
118}
119
120/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
121///
122/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
123#[inline]
124#[target_feature(enable = "avx512f")]
125#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
126#[cfg_attr(test, assert_instr(vcvttsd2usi))]
127pub fn _mm_cvttsd_u64(a: __m128d) -> u64 {
128 unsafe { vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
129}
130
131/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
132///
133/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
134#[inline]
135#[target_feature(enable = "avx512f")]
136#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
137#[cfg_attr(test, assert_instr(vcvttss2si))]
138pub fn _mm_cvttss_i64(a: __m128) -> i64 {
139 unsafe { vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
140}
141
142/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
143///
144/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
145#[inline]
146#[target_feature(enable = "avx512f")]
147#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
148#[cfg_attr(test, assert_instr(vcvttss2usi))]
149pub fn _mm_cvttss_u64(a: __m128) -> u64 {
150 unsafe { vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
151}
152
153/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
154/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
155/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
156/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
157/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
158/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
159/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
160///
161/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
162#[inline]
163#[target_feature(enable = "avx512f")]
164#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
165#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
166#[rustc_legacy_const_generics(2)]
167pub fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
168 unsafe {
169 static_assert_rounding!(ROUNDING);
170 let a: f64x2 = a.as_f64x2();
171 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
172 transmute(src:r)
173 }
174}
175
176/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
177/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
178/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
179/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
180/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
181/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
182/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
183///
184/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
185#[inline]
186#[target_feature(enable = "avx512f")]
187#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
188#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
189#[rustc_legacy_const_generics(2)]
190pub fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
191 unsafe {
192 static_assert_rounding!(ROUNDING);
193 let a: f64x2 = a.as_f64x2();
194 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
195 transmute(src:r)
196 }
197}
198
199/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
200/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
201/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
202/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
203/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
204/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
205/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
206///
207/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
208#[inline]
209#[target_feature(enable = "avx512f")]
210#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
211#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
212#[rustc_legacy_const_generics(2)]
213pub fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
214 unsafe {
215 static_assert_rounding!(ROUNDING);
216 let a: f32x4 = a.as_f32x4();
217 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
218 transmute(src:r)
219 }
220}
221
222/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
223/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
224/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
225/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
226/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
227/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
228/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
229///
230/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
231#[inline]
232#[target_feature(enable = "avx512f")]
233#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
234#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
235#[rustc_legacy_const_generics(2)]
236pub fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
237 unsafe {
238 static_assert_rounding!(ROUNDING);
239 let a: f64x2 = a.as_f64x2();
240 let r: f64x2 = vcvtusi2sd64(a, b, ROUNDING);
241 transmute(src:r)
242 }
243}
244
245/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
246/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
247/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
248/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
249/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
250/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
251/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
252///
253/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
254#[inline]
255#[target_feature(enable = "avx512f")]
256#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
257#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
258#[rustc_legacy_const_generics(2)]
259pub fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
260 unsafe {
261 static_assert_rounding!(ROUNDING);
262 let a: f32x4 = a.as_f32x4();
263 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
264 transmute(src:r)
265 }
266}
267
268/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
269/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
270/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
271/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
272/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
273/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
274/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
275///
276/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
277#[inline]
278#[target_feature(enable = "avx512f")]
279#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
280#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
281#[rustc_legacy_const_generics(2)]
282pub fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
283 unsafe {
284 static_assert_rounding!(ROUNDING);
285 let a: f32x4 = a.as_f32x4();
286 let r: f32x4 = vcvtusi2ss64(a, b, ROUNDING);
287 transmute(src:r)
288 }
289}
290
291/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
292/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
293/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
294/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
295/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
296/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
297/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
298///
299/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
300#[inline]
301#[target_feature(enable = "avx512f")]
302#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
303#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
304#[rustc_legacy_const_generics(1)]
305pub fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
306 unsafe {
307 static_assert_rounding!(ROUNDING);
308 let a: f64x2 = a.as_f64x2();
309 vcvtsd2si64(a, ROUNDING)
310 }
311}
312
313/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
314/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
315/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
316/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
317/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
318/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
319/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
320///
321/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
322#[inline]
323#[target_feature(enable = "avx512f")]
324#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
325#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
326#[rustc_legacy_const_generics(1)]
327pub fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
328 unsafe {
329 static_assert_rounding!(ROUNDING);
330 let a: f64x2 = a.as_f64x2();
331 vcvtsd2si64(a, ROUNDING)
332 }
333}
334
335/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
336/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
337/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
338/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
339/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
340/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
341/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
342///
343/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
344#[inline]
345#[target_feature(enable = "avx512f")]
346#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
347#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
348#[rustc_legacy_const_generics(1)]
349pub fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
350 unsafe {
351 static_assert_rounding!(ROUNDING);
352 let a: f64x2 = a.as_f64x2();
353 vcvtsd2usi64(a, ROUNDING)
354 }
355}
356
357/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
358/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
359/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
360/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
361/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
362/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
363/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
364///
365/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
366#[inline]
367#[target_feature(enable = "avx512f")]
368#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
369#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
370#[rustc_legacy_const_generics(1)]
371pub fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
372 unsafe {
373 static_assert_rounding!(ROUNDING);
374 let a: f32x4 = a.as_f32x4();
375 vcvtss2si64(a, ROUNDING)
376 }
377}
378
379/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
380/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
381/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
382/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
383/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
384/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
385/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
386///
387/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
388#[inline]
389#[target_feature(enable = "avx512f")]
390#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
391#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
392#[rustc_legacy_const_generics(1)]
393pub fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
394 unsafe {
395 static_assert_rounding!(ROUNDING);
396 let a: f32x4 = a.as_f32x4();
397 vcvtss2si64(a, ROUNDING)
398 }
399}
400
401/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
402/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
403/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
404/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
405/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
406/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
407/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
408///
409/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
410#[inline]
411#[target_feature(enable = "avx512f")]
412#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
413#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
414#[rustc_legacy_const_generics(1)]
415pub fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
416 unsafe {
417 static_assert_rounding!(ROUNDING);
418 let a: f32x4 = a.as_f32x4();
419 vcvtss2usi64(a, ROUNDING)
420 }
421}
422
423/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
424/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
425///
426/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
427#[inline]
428#[target_feature(enable = "avx512f")]
429#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
430#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
431#[rustc_legacy_const_generics(1)]
432pub fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
433 unsafe {
434 static_assert_sae!(SAE);
435 let a: f64x2 = a.as_f64x2();
436 vcvttsd2si64(a, SAE)
437 }
438}
439
440/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
441/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
442///
443/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
444#[inline]
445#[target_feature(enable = "avx512f")]
446#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
447#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
448#[rustc_legacy_const_generics(1)]
449pub fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
450 unsafe {
451 static_assert_sae!(SAE);
452 let a: f64x2 = a.as_f64x2();
453 vcvttsd2si64(a, SAE)
454 }
455}
456
457/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
458/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
459///
460/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
461#[inline]
462#[target_feature(enable = "avx512f")]
463#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
464#[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))]
465#[rustc_legacy_const_generics(1)]
466pub fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
467 unsafe {
468 static_assert_sae!(SAE);
469 let a: f64x2 = a.as_f64x2();
470 vcvttsd2usi64(a, SAE)
471 }
472}
473
474/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
475/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
476///
477/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
478#[inline]
479#[target_feature(enable = "avx512f")]
480#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
481#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
482#[rustc_legacy_const_generics(1)]
483pub fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
484 unsafe {
485 static_assert_sae!(SAE);
486 let a: f32x4 = a.as_f32x4();
487 vcvttss2si64(a, SAE)
488 }
489}
490
491/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
492/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
493///
494/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
495#[inline]
496#[target_feature(enable = "avx512f")]
497#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
498#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
499#[rustc_legacy_const_generics(1)]
500pub fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
501 unsafe {
502 static_assert_sae!(SAE);
503 let a: f32x4 = a.as_f32x4();
504 vcvttss2si64(a, SAE)
505 }
506}
507
508/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
509/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
510///
511/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
512#[inline]
513#[target_feature(enable = "avx512f")]
514#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
515#[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))]
516#[rustc_legacy_const_generics(1)]
517pub fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
518 unsafe {
519 static_assert_sae!(SAE);
520 let a: f32x4 = a.as_f32x4();
521 vcvttss2usi64(a, SAE)
522 }
523}
524
525#[allow(improper_ctypes)]
526unsafe extern "C" {
527 #[link_name = "llvm.x86.avx512.vcvtss2si64"]
528 unsafefn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
529 #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
530 unsafefn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
531 #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
532 unsafefn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
533 #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
534 unsafefn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
535
536 #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
537 unsafefn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
538 #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
539 unsafefn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
540 #[link_name = "llvm.x86.avx512.cvtusi642ss"]
541 unsafefn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
542 #[link_name = "llvm.x86.avx512.cvtusi642sd"]
543 unsafefn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
544
545 #[link_name = "llvm.x86.avx512.cvttss2si64"]
546 unsafefn vcvttss2si64(a: f32x4, rounding: i32) -> i64;
547 #[link_name = "llvm.x86.avx512.cvttss2usi64"]
548 unsafefn vcvttss2usi64(a: f32x4, rounding: i32) -> u64;
549 #[link_name = "llvm.x86.avx512.cvttsd2si64"]
550 unsafefn vcvttsd2si64(a: f64x2, rounding: i32) -> i64;
551 #[link_name = "llvm.x86.avx512.cvttsd2usi64"]
552 unsafefn vcvttsd2usi64(a: f64x2, rounding: i32) -> u64;
553}
554
555#[cfg(test)]
556mod tests {
557
558 use stdarch_test::simd_test;
559
560 use crate::core_arch::x86::*;
561 use crate::core_arch::x86_64::*;
562 use crate::hint::black_box;
563
564 #[simd_test(enable = "avx512f")]
565 unsafe fn test_mm512_abs_epi64() {
566 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
567 let r = _mm512_abs_epi64(a);
568 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
569 assert_eq_m512i(r, e);
570 }
571
572 #[simd_test(enable = "avx512f")]
573 unsafe fn test_mm512_mask_abs_epi64() {
574 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
575 let r = _mm512_mask_abs_epi64(a, 0, a);
576 assert_eq_m512i(r, a);
577 let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
578 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
579 assert_eq_m512i(r, e);
580 }
581
582 #[simd_test(enable = "avx512f")]
583 unsafe fn test_mm512_maskz_abs_epi64() {
584 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
585 let r = _mm512_maskz_abs_epi64(0, a);
586 assert_eq_m512i(r, _mm512_setzero_si512());
587 let r = _mm512_maskz_abs_epi64(0b11111111, a);
588 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
589 assert_eq_m512i(r, e);
590 }
591
592 #[simd_test(enable = "avx512f,avx512vl")]
593 unsafe fn test_mm256_abs_epi64() {
594 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
595 let r = _mm256_abs_epi64(a);
596 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
597 assert_eq_m256i(r, e);
598 }
599
600 #[simd_test(enable = "avx512f,avx512vl")]
601 unsafe fn test_mm256_mask_abs_epi64() {
602 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
603 let r = _mm256_mask_abs_epi64(a, 0, a);
604 assert_eq_m256i(r, a);
605 let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
606 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
607 assert_eq_m256i(r, e);
608 }
609
610 #[simd_test(enable = "avx512f,avx512vl")]
611 unsafe fn test_mm256_maskz_abs_epi64() {
612 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
613 let r = _mm256_maskz_abs_epi64(0, a);
614 assert_eq_m256i(r, _mm256_setzero_si256());
615 let r = _mm256_maskz_abs_epi64(0b00001111, a);
616 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
617 assert_eq_m256i(r, e);
618 }
619
620 #[simd_test(enable = "avx512f,avx512vl")]
621 unsafe fn test_mm_abs_epi64() {
622 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
623 let r = _mm_abs_epi64(a);
624 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
625 assert_eq_m128i(r, e);
626 let a = _mm_set_epi64x(100, -100);
627 let r = _mm_abs_epi64(a);
628 let e = _mm_set_epi64x(100, 100);
629 assert_eq_m128i(r, e);
630 }
631
632 #[simd_test(enable = "avx512f,avx512vl")]
633 unsafe fn test_mm_mask_abs_epi64() {
634 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
635 let r = _mm_mask_abs_epi64(a, 0, a);
636 assert_eq_m128i(r, a);
637 let r = _mm_mask_abs_epi64(a, 0b00000011, a);
638 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
639 assert_eq_m128i(r, e);
640 let a = _mm_set_epi64x(100, -100);
641 let r = _mm_mask_abs_epi64(a, 0b00000011, a);
642 let e = _mm_set_epi64x(100, 100);
643 assert_eq_m128i(r, e);
644 }
645
646 #[simd_test(enable = "avx512f,avx512vl")]
647 unsafe fn test_mm_maskz_abs_epi64() {
648 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
649 let r = _mm_maskz_abs_epi64(0, a);
650 assert_eq_m128i(r, _mm_setzero_si128());
651 let r = _mm_maskz_abs_epi64(0b00000011, a);
652 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
653 assert_eq_m128i(r, e);
654 let a = _mm_set_epi64x(100, -100);
655 let r = _mm_maskz_abs_epi64(0b00000011, a);
656 let e = _mm_set_epi64x(100, 100);
657 assert_eq_m128i(r, e);
658 }
659
660 #[simd_test(enable = "avx512f")]
661 unsafe fn test_mm512_abs_pd() {
662 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
663 let r = _mm512_abs_pd(a);
664 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
665 assert_eq_m512d(r, e);
666 }
667
668 #[simd_test(enable = "avx512f")]
669 unsafe fn test_mm512_mask_abs_pd() {
670 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
671 let r = _mm512_mask_abs_pd(a, 0, a);
672 assert_eq_m512d(r, a);
673 let r = _mm512_mask_abs_pd(a, 0b00001111, a);
674 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
675 assert_eq_m512d(r, e);
676 }
677
678 #[simd_test(enable = "avx512f")]
679 unsafe fn test_mm512_mask_mov_epi64() {
680 let src = _mm512_set1_epi64(1);
681 let a = _mm512_set1_epi64(2);
682 let r = _mm512_mask_mov_epi64(src, 0, a);
683 assert_eq_m512i(r, src);
684 let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
685 assert_eq_m512i(r, a);
686 }
687
688 #[simd_test(enable = "avx512f")]
689 unsafe fn test_mm512_maskz_mov_epi64() {
690 let a = _mm512_set1_epi64(2);
691 let r = _mm512_maskz_mov_epi64(0, a);
692 assert_eq_m512i(r, _mm512_setzero_si512());
693 let r = _mm512_maskz_mov_epi64(0b11111111, a);
694 assert_eq_m512i(r, a);
695 }
696
697 #[simd_test(enable = "avx512f,avx512vl")]
698 unsafe fn test_mm256_mask_mov_epi64() {
699 let src = _mm256_set1_epi64x(1);
700 let a = _mm256_set1_epi64x(2);
701 let r = _mm256_mask_mov_epi64(src, 0, a);
702 assert_eq_m256i(r, src);
703 let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
704 assert_eq_m256i(r, a);
705 }
706
707 #[simd_test(enable = "avx512f,avx512vl")]
708 unsafe fn test_mm256_maskz_mov_epi64() {
709 let a = _mm256_set1_epi64x(2);
710 let r = _mm256_maskz_mov_epi64(0, a);
711 assert_eq_m256i(r, _mm256_setzero_si256());
712 let r = _mm256_maskz_mov_epi64(0b00001111, a);
713 assert_eq_m256i(r, a);
714 }
715
716 #[simd_test(enable = "avx512f,avx512vl")]
717 unsafe fn test_mm_mask_mov_epi64() {
718 let src = _mm_set1_epi64x(1);
719 let a = _mm_set1_epi64x(2);
720 let r = _mm_mask_mov_epi64(src, 0, a);
721 assert_eq_m128i(r, src);
722 let r = _mm_mask_mov_epi64(src, 0b00000011, a);
723 assert_eq_m128i(r, a);
724 }
725
726 #[simd_test(enable = "avx512f,avx512vl")]
727 unsafe fn test_mm_maskz_mov_epi64() {
728 let a = _mm_set1_epi64x(2);
729 let r = _mm_maskz_mov_epi64(0, a);
730 assert_eq_m128i(r, _mm_setzero_si128());
731 let r = _mm_maskz_mov_epi64(0b00000011, a);
732 assert_eq_m128i(r, a);
733 }
734
735 #[simd_test(enable = "avx512f")]
736 unsafe fn test_mm512_mask_mov_pd() {
737 let src = _mm512_set1_pd(1.);
738 let a = _mm512_set1_pd(2.);
739 let r = _mm512_mask_mov_pd(src, 0, a);
740 assert_eq_m512d(r, src);
741 let r = _mm512_mask_mov_pd(src, 0b11111111, a);
742 assert_eq_m512d(r, a);
743 }
744
745 #[simd_test(enable = "avx512f")]
746 unsafe fn test_mm512_maskz_mov_pd() {
747 let a = _mm512_set1_pd(2.);
748 let r = _mm512_maskz_mov_pd(0, a);
749 assert_eq_m512d(r, _mm512_setzero_pd());
750 let r = _mm512_maskz_mov_pd(0b11111111, a);
751 assert_eq_m512d(r, a);
752 }
753
754 #[simd_test(enable = "avx512f,avx512vl")]
755 unsafe fn test_mm256_mask_mov_pd() {
756 let src = _mm256_set1_pd(1.);
757 let a = _mm256_set1_pd(2.);
758 let r = _mm256_mask_mov_pd(src, 0, a);
759 assert_eq_m256d(r, src);
760 let r = _mm256_mask_mov_pd(src, 0b00001111, a);
761 assert_eq_m256d(r, a);
762 }
763
764 #[simd_test(enable = "avx512f,avx512vl")]
765 unsafe fn test_mm256_maskz_mov_pd() {
766 let a = _mm256_set1_pd(2.);
767 let r = _mm256_maskz_mov_pd(0, a);
768 assert_eq_m256d(r, _mm256_setzero_pd());
769 let r = _mm256_maskz_mov_pd(0b00001111, a);
770 assert_eq_m256d(r, a);
771 }
772
773 #[simd_test(enable = "avx512f,avx512vl")]
774 unsafe fn test_mm_mask_mov_pd() {
775 let src = _mm_set1_pd(1.);
776 let a = _mm_set1_pd(2.);
777 let r = _mm_mask_mov_pd(src, 0, a);
778 assert_eq_m128d(r, src);
779 let r = _mm_mask_mov_pd(src, 0b00000011, a);
780 assert_eq_m128d(r, a);
781 }
782
783 #[simd_test(enable = "avx512f,avx512vl")]
784 unsafe fn test_mm_maskz_mov_pd() {
785 let a = _mm_set1_pd(2.);
786 let r = _mm_maskz_mov_pd(0, a);
787 assert_eq_m128d(r, _mm_setzero_pd());
788 let r = _mm_maskz_mov_pd(0b00000011, a);
789 assert_eq_m128d(r, a);
790 }
791
792 #[simd_test(enable = "avx512f")]
793 unsafe fn test_mm512_add_epi64() {
794 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
795 let b = _mm512_set1_epi64(1);
796 let r = _mm512_add_epi64(a, b);
797 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
798 assert_eq_m512i(r, e);
799 }
800
801 #[simd_test(enable = "avx512f")]
802 unsafe fn test_mm512_mask_add_epi64() {
803 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
804 let b = _mm512_set1_epi64(1);
805 let r = _mm512_mask_add_epi64(a, 0, a, b);
806 assert_eq_m512i(r, a);
807 let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
808 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
809 assert_eq_m512i(r, e);
810 }
811
812 #[simd_test(enable = "avx512f")]
813 unsafe fn test_mm512_maskz_add_epi64() {
814 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
815 let b = _mm512_set1_epi64(1);
816 let r = _mm512_maskz_add_epi64(0, a, b);
817 assert_eq_m512i(r, _mm512_setzero_si512());
818 let r = _mm512_maskz_add_epi64(0b00001111, a, b);
819 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
820 assert_eq_m512i(r, e);
821 }
822
823 #[simd_test(enable = "avx512f,avx512vl")]
824 unsafe fn test_mm256_mask_add_epi64() {
825 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
826 let b = _mm256_set1_epi64x(1);
827 let r = _mm256_mask_add_epi64(a, 0, a, b);
828 assert_eq_m256i(r, a);
829 let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
830 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
831 assert_eq_m256i(r, e);
832 }
833
834 #[simd_test(enable = "avx512f,avx512vl")]
835 unsafe fn test_mm256_maskz_add_epi64() {
836 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
837 let b = _mm256_set1_epi64x(1);
838 let r = _mm256_maskz_add_epi64(0, a, b);
839 assert_eq_m256i(r, _mm256_setzero_si256());
840 let r = _mm256_maskz_add_epi64(0b00001111, a, b);
841 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
842 assert_eq_m256i(r, e);
843 }
844
845 #[simd_test(enable = "avx512f,avx512vl")]
846 unsafe fn test_mm_mask_add_epi64() {
847 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
848 let b = _mm_set1_epi64x(1);
849 let r = _mm_mask_add_epi64(a, 0, a, b);
850 assert_eq_m128i(r, a);
851 let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
852 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
853 assert_eq_m128i(r, e);
854 }
855
856 #[simd_test(enable = "avx512f,avx512vl")]
857 unsafe fn test_mm_maskz_add_epi64() {
858 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
859 let b = _mm_set1_epi64x(1);
860 let r = _mm_maskz_add_epi64(0, a, b);
861 assert_eq_m128i(r, _mm_setzero_si128());
862 let r = _mm_maskz_add_epi64(0b00000011, a, b);
863 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
864 assert_eq_m128i(r, e);
865 }
866
867 #[simd_test(enable = "avx512f")]
868 unsafe fn test_mm512_add_pd() {
869 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
870 let b = _mm512_set1_pd(1.);
871 let r = _mm512_add_pd(a, b);
872 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
873 assert_eq_m512d(r, e);
874 }
875
876 #[simd_test(enable = "avx512f")]
877 unsafe fn test_mm512_mask_add_pd() {
878 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
879 let b = _mm512_set1_pd(1.);
880 let r = _mm512_mask_add_pd(a, 0, a, b);
881 assert_eq_m512d(r, a);
882 let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
883 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
884 assert_eq_m512d(r, e);
885 }
886
887 #[simd_test(enable = "avx512f")]
888 unsafe fn test_mm512_maskz_add_pd() {
889 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
890 let b = _mm512_set1_pd(1.);
891 let r = _mm512_maskz_add_pd(0, a, b);
892 assert_eq_m512d(r, _mm512_setzero_pd());
893 let r = _mm512_maskz_add_pd(0b00001111, a, b);
894 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
895 assert_eq_m512d(r, e);
896 }
897
898 #[simd_test(enable = "avx512f,avx512vl")]
899 unsafe fn test_mm256_mask_add_pd() {
900 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
901 let b = _mm256_set1_pd(1.);
902 let r = _mm256_mask_add_pd(a, 0, a, b);
903 assert_eq_m256d(r, a);
904 let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
905 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
906 assert_eq_m256d(r, e);
907 }
908
909 #[simd_test(enable = "avx512f,avx512vl")]
910 unsafe fn test_mm256_maskz_add_pd() {
911 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
912 let b = _mm256_set1_pd(1.);
913 let r = _mm256_maskz_add_pd(0, a, b);
914 assert_eq_m256d(r, _mm256_setzero_pd());
915 let r = _mm256_maskz_add_pd(0b00001111, a, b);
916 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
917 assert_eq_m256d(r, e);
918 }
919
920 #[simd_test(enable = "avx512f,avx512vl")]
921 unsafe fn test_mm_mask_add_pd() {
922 let a = _mm_set_pd(f64::MAX, f64::MIN);
923 let b = _mm_set1_pd(1.);
924 let r = _mm_mask_add_pd(a, 0, a, b);
925 assert_eq_m128d(r, a);
926 let r = _mm_mask_add_pd(a, 0b00000011, a, b);
927 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
928 assert_eq_m128d(r, e);
929 }
930
931 #[simd_test(enable = "avx512f,avx512vl")]
932 unsafe fn test_mm_maskz_add_pd() {
933 let a = _mm_set_pd(f64::MAX, f64::MIN);
934 let b = _mm_set1_pd(1.);
935 let r = _mm_maskz_add_pd(0, a, b);
936 assert_eq_m128d(r, _mm_setzero_pd());
937 let r = _mm_maskz_add_pd(0b00000011, a, b);
938 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
939 assert_eq_m128d(r, e);
940 }
941
942 #[simd_test(enable = "avx512f")]
943 unsafe fn test_mm512_sub_epi64() {
944 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
945 let b = _mm512_set1_epi64(1);
946 let r = _mm512_sub_epi64(a, b);
947 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
948 assert_eq_m512i(r, e);
949 }
950
951 #[simd_test(enable = "avx512f")]
952 unsafe fn test_mm512_mask_sub_epi64() {
953 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
954 let b = _mm512_set1_epi64(1);
955 let r = _mm512_mask_sub_epi64(a, 0, a, b);
956 assert_eq_m512i(r, a);
957 let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
958 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
959 assert_eq_m512i(r, e);
960 }
961
962 #[simd_test(enable = "avx512f")]
963 unsafe fn test_mm512_maskz_sub_epi64() {
964 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
965 let b = _mm512_set1_epi64(1);
966 let r = _mm512_maskz_sub_epi64(0, a, b);
967 assert_eq_m512i(r, _mm512_setzero_si512());
968 let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
969 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
970 assert_eq_m512i(r, e);
971 }
972
973 #[simd_test(enable = "avx512f,avx512vl")]
974 unsafe fn test_mm256_mask_sub_epi64() {
975 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
976 let b = _mm256_set1_epi64x(1);
977 let r = _mm256_mask_sub_epi64(a, 0, a, b);
978 assert_eq_m256i(r, a);
979 let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
980 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
981 assert_eq_m256i(r, e);
982 }
983
984 #[simd_test(enable = "avx512f,avx512vl")]
985 unsafe fn test_mm256_maskz_sub_epi64() {
986 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
987 let b = _mm256_set1_epi64x(1);
988 let r = _mm256_maskz_sub_epi64(0, a, b);
989 assert_eq_m256i(r, _mm256_setzero_si256());
990 let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
991 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
992 assert_eq_m256i(r, e);
993 }
994
995 #[simd_test(enable = "avx512f,avx512vl")]
996 unsafe fn test_mm_mask_sub_epi64() {
997 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
998 let b = _mm_set1_epi64x(1);
999 let r = _mm_mask_sub_epi64(a, 0, a, b);
1000 assert_eq_m128i(r, a);
1001 let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
1002 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1003 assert_eq_m128i(r, e);
1004 }
1005
1006 #[simd_test(enable = "avx512f,avx512vl")]
1007 unsafe fn test_mm_maskz_sub_epi64() {
1008 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1009 let b = _mm_set1_epi64x(1);
1010 let r = _mm_maskz_sub_epi64(0, a, b);
1011 assert_eq_m128i(r, _mm_setzero_si128());
1012 let r = _mm_maskz_sub_epi64(0b00000011, a, b);
1013 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1014 assert_eq_m128i(r, e);
1015 }
1016
1017 #[simd_test(enable = "avx512f")]
1018 unsafe fn test_mm512_sub_pd() {
1019 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1020 let b = _mm512_set1_pd(1.);
1021 let r = _mm512_sub_pd(a, b);
1022 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
1023 assert_eq_m512d(r, e);
1024 }
1025
1026 #[simd_test(enable = "avx512f")]
1027 unsafe fn test_mm512_mask_sub_pd() {
1028 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1029 let b = _mm512_set1_pd(1.);
1030 let r = _mm512_mask_sub_pd(a, 0, a, b);
1031 assert_eq_m512d(r, a);
1032 let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
1033 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
1034 assert_eq_m512d(r, e);
1035 }
1036
1037 #[simd_test(enable = "avx512f")]
1038 unsafe fn test_mm512_maskz_sub_pd() {
1039 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1040 let b = _mm512_set1_pd(1.);
1041 let r = _mm512_maskz_sub_pd(0, a, b);
1042 assert_eq_m512d(r, _mm512_setzero_pd());
1043 let r = _mm512_maskz_sub_pd(0b00001111, a, b);
1044 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
1045 assert_eq_m512d(r, e);
1046 }
1047
1048 #[simd_test(enable = "avx512f,avx512vl")]
1049 unsafe fn test_mm256_mask_sub_pd() {
1050 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1051 let b = _mm256_set1_pd(1.);
1052 let r = _mm256_mask_sub_pd(a, 0, a, b);
1053 assert_eq_m256d(r, a);
1054 let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
1055 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1056 assert_eq_m256d(r, e);
1057 }
1058
1059 #[simd_test(enable = "avx512f,avx512vl")]
1060 unsafe fn test_mm256_maskz_sub_pd() {
1061 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1062 let b = _mm256_set1_pd(1.);
1063 let r = _mm256_maskz_sub_pd(0, a, b);
1064 assert_eq_m256d(r, _mm256_setzero_pd());
1065 let r = _mm256_maskz_sub_pd(0b00001111, a, b);
1066 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1067 assert_eq_m256d(r, e);
1068 }
1069
1070 #[simd_test(enable = "avx512f,avx512vl")]
1071 unsafe fn test_mm_mask_sub_pd() {
1072 let a = _mm_set_pd(f64::MAX, f64::MIN);
1073 let b = _mm_set1_pd(1.);
1074 let r = _mm_mask_sub_pd(a, 0, a, b);
1075 assert_eq_m128d(r, a);
1076 let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
1077 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1078 assert_eq_m128d(r, e);
1079 }
1080
1081 #[simd_test(enable = "avx512f,avx512vl")]
1082 unsafe fn test_mm_maskz_sub_pd() {
1083 let a = _mm_set_pd(f64::MAX, f64::MIN);
1084 let b = _mm_set1_pd(1.);
1085 let r = _mm_maskz_sub_pd(0, a, b);
1086 assert_eq_m128d(r, _mm_setzero_pd());
1087 let r = _mm_maskz_sub_pd(0b00000011, a, b);
1088 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1089 assert_eq_m128d(r, e);
1090 }
1091
1092 #[simd_test(enable = "avx512f")]
1093 unsafe fn test_mm512_mul_epi32() {
1094 let a = _mm512_set1_epi32(1);
1095 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1096 let r = _mm512_mul_epi32(a, b);
1097 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1098 assert_eq_m512i(r, e);
1099 }
1100
1101 #[simd_test(enable = "avx512f")]
1102 unsafe fn test_mm512_mask_mul_epi32() {
1103 let a = _mm512_set1_epi32(1);
1104 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1105 let r = _mm512_mask_mul_epi32(a, 0, a, b);
1106 assert_eq_m512i(r, a);
1107 let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1108 #[rustfmt::skip]
1109 let e = _mm512_set_epi64(
1110 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1111 7, 5, 3, 1,
1112 );
1113 assert_eq_m512i(r, e);
1114 }
1115
1116 #[simd_test(enable = "avx512f")]
1117 unsafe fn test_mm512_maskz_mul_epi32() {
1118 let a = _mm512_set1_epi32(1);
1119 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1120 let r = _mm512_maskz_mul_epi32(0, a, b);
1121 assert_eq_m512i(r, _mm512_setzero_si512());
1122 let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1123 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1124 assert_eq_m512i(r, e);
1125 }
1126
1127 #[simd_test(enable = "avx512f,avx512vl")]
1128 unsafe fn test_mm256_mask_mul_epi32() {
1129 let a = _mm256_set1_epi32(1);
1130 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1131 let r = _mm256_mask_mul_epi32(a, 0, a, b);
1132 assert_eq_m256i(r, a);
1133 let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1134 let e = _mm256_set_epi64x(2, 4, 6, 8);
1135 assert_eq_m256i(r, e);
1136 }
1137
1138 #[simd_test(enable = "avx512f,avx512vl")]
1139 unsafe fn test_mm256_maskz_mul_epi32() {
1140 let a = _mm256_set1_epi32(1);
1141 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1142 let r = _mm256_maskz_mul_epi32(0, a, b);
1143 assert_eq_m256i(r, _mm256_setzero_si256());
1144 let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1145 let e = _mm256_set_epi64x(2, 4, 6, 8);
1146 assert_eq_m256i(r, e);
1147 }
1148
1149 #[simd_test(enable = "avx512f,avx512vl")]
1150 unsafe fn test_mm_mask_mul_epi32() {
1151 let a = _mm_set1_epi32(1);
1152 let b = _mm_set_epi32(1, 2, 3, 4);
1153 let r = _mm_mask_mul_epi32(a, 0, a, b);
1154 assert_eq_m128i(r, a);
1155 let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1156 let e = _mm_set_epi64x(2, 4);
1157 assert_eq_m128i(r, e);
1158 }
1159
1160 #[simd_test(enable = "avx512f,avx512vl")]
1161 unsafe fn test_mm_maskz_mul_epi32() {
1162 let a = _mm_set1_epi32(1);
1163 let b = _mm_set_epi32(1, 2, 3, 4);
1164 let r = _mm_maskz_mul_epi32(0, a, b);
1165 assert_eq_m128i(r, _mm_setzero_si128());
1166 let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1167 let e = _mm_set_epi64x(2, 4);
1168 assert_eq_m128i(r, e);
1169 }
1170
1171 #[simd_test(enable = "avx512f")]
1172 unsafe fn test_mm512_mul_epu32() {
1173 let a = _mm512_set1_epi32(1);
1174 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1175 let r = _mm512_mul_epu32(a, b);
1176 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1177 assert_eq_m512i(r, e);
1178 }
1179
1180 #[simd_test(enable = "avx512f")]
1181 unsafe fn test_mm512_mask_mul_epu32() {
1182 let a = _mm512_set1_epi32(1);
1183 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1184 let r = _mm512_mask_mul_epu32(a, 0, a, b);
1185 assert_eq_m512i(r, a);
1186 let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1187 #[rustfmt::skip]
1188 let e = _mm512_set_epi64(
1189 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1190 7, 5, 3, 1,
1191 );
1192 assert_eq_m512i(r, e);
1193 }
1194
1195 #[simd_test(enable = "avx512f")]
1196 unsafe fn test_mm512_maskz_mul_epu32() {
1197 let a = _mm512_set1_epi32(1);
1198 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1199 let r = _mm512_maskz_mul_epu32(0, a, b);
1200 assert_eq_m512i(r, _mm512_setzero_si512());
1201 let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1202 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1203 assert_eq_m512i(r, e);
1204 }
1205
1206 #[simd_test(enable = "avx512f,avx512vl")]
1207 unsafe fn test_mm256_mask_mul_epu32() {
1208 let a = _mm256_set1_epi32(1);
1209 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1210 let r = _mm256_mask_mul_epu32(a, 0, a, b);
1211 assert_eq_m256i(r, a);
1212 let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1213 let e = _mm256_set_epi64x(2, 4, 6, 8);
1214 assert_eq_m256i(r, e);
1215 }
1216
1217 #[simd_test(enable = "avx512f,avx512vl")]
1218 unsafe fn test_mm256_maskz_mul_epu32() {
1219 let a = _mm256_set1_epi32(1);
1220 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1221 let r = _mm256_maskz_mul_epu32(0, a, b);
1222 assert_eq_m256i(r, _mm256_setzero_si256());
1223 let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1224 let e = _mm256_set_epi64x(2, 4, 6, 8);
1225 assert_eq_m256i(r, e);
1226 }
1227
1228 #[simd_test(enable = "avx512f,avx512vl")]
1229 unsafe fn test_mm_mask_mul_epu32() {
1230 let a = _mm_set1_epi32(1);
1231 let b = _mm_set_epi32(1, 2, 3, 4);
1232 let r = _mm_mask_mul_epu32(a, 0, a, b);
1233 assert_eq_m128i(r, a);
1234 let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1235 let e = _mm_set_epi64x(2, 4);
1236 assert_eq_m128i(r, e);
1237 }
1238
1239 #[simd_test(enable = "avx512f,avx512vl")]
1240 unsafe fn test_mm_maskz_mul_epu32() {
1241 let a = _mm_set1_epi32(1);
1242 let b = _mm_set_epi32(1, 2, 3, 4);
1243 let r = _mm_maskz_mul_epu32(0, a, b);
1244 assert_eq_m128i(r, _mm_setzero_si128());
1245 let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1246 let e = _mm_set_epi64x(2, 4);
1247 assert_eq_m128i(r, e);
1248 }
1249
1250 #[simd_test(enable = "avx512f")]
1251 unsafe fn test_mm512_mullox_epi64() {
1252 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1253 let b = _mm512_set1_epi64(2);
1254 let r = _mm512_mullox_epi64(a, b);
1255 let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1256 assert_eq_m512i(r, e);
1257 }
1258
1259 #[simd_test(enable = "avx512f")]
1260 unsafe fn test_mm512_mask_mullox_epi64() {
1261 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1262 let b = _mm512_set1_epi64(2);
1263 let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1264 assert_eq_m512i(r, a);
1265 let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1266 let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1267 assert_eq_m512i(r, e);
1268 }
1269
1270 #[simd_test(enable = "avx512f")]
1271 unsafe fn test_mm512_mul_pd() {
1272 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1273 let b = _mm512_set1_pd(2.);
1274 let r = _mm512_mul_pd(a, b);
1275 #[rustfmt::skip]
1276 let e = _mm512_setr_pd(
1277 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1278 f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1279 );
1280 assert_eq_m512d(r, e);
1281 }
1282
1283 #[simd_test(enable = "avx512f")]
1284 unsafe fn test_mm512_mask_mul_pd() {
1285 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1286 let b = _mm512_set1_pd(2.);
1287 let r = _mm512_mask_mul_pd(a, 0, a, b);
1288 assert_eq_m512d(r, a);
1289 let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1290 #[rustfmt::skip]
1291 let e = _mm512_setr_pd(
1292 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1293 f64::MAX, f64::MIN, -100., -32.,
1294 );
1295 assert_eq_m512d(r, e);
1296 }
1297
1298 #[simd_test(enable = "avx512f")]
1299 unsafe fn test_mm512_maskz_mul_pd() {
1300 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1301 let b = _mm512_set1_pd(2.);
1302 let r = _mm512_maskz_mul_pd(0, a, b);
1303 assert_eq_m512d(r, _mm512_setzero_pd());
1304 let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1305 let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1306 assert_eq_m512d(r, e);
1307 }
1308
1309 #[simd_test(enable = "avx512f,avx512vl")]
1310 unsafe fn test_mm256_mask_mul_pd() {
1311 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1312 let b = _mm256_set1_pd(2.);
1313 let r = _mm256_mask_mul_pd(a, 0, a, b);
1314 assert_eq_m256d(r, a);
1315 let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1316 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1317 assert_eq_m256d(r, e);
1318 }
1319
1320 #[simd_test(enable = "avx512f,avx512vl")]
1321 unsafe fn test_mm256_maskz_mul_pd() {
1322 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1323 let b = _mm256_set1_pd(2.);
1324 let r = _mm256_maskz_mul_pd(0, a, b);
1325 assert_eq_m256d(r, _mm256_setzero_pd());
1326 let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1327 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1328 assert_eq_m256d(r, e);
1329 }
1330
1331 #[simd_test(enable = "avx512f,avx512vl")]
1332 unsafe fn test_mm_mask_mul_pd() {
1333 let a = _mm_set_pd(f64::MAX, f64::MIN);
1334 let b = _mm_set1_pd(2.);
1335 let r = _mm_mask_mul_pd(a, 0, a, b);
1336 assert_eq_m128d(r, a);
1337 let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1338 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1339 assert_eq_m128d(r, e);
1340 }
1341
1342 #[simd_test(enable = "avx512f,avx512vl")]
1343 unsafe fn test_mm_maskz_mul_pd() {
1344 let a = _mm_set_pd(f64::MAX, f64::MIN);
1345 let b = _mm_set1_pd(2.);
1346 let r = _mm_maskz_mul_pd(0, a, b);
1347 assert_eq_m128d(r, _mm_setzero_pd());
1348 let r = _mm_maskz_mul_pd(0b00000011, a, b);
1349 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1350 assert_eq_m128d(r, e);
1351 }
1352
1353 #[simd_test(enable = "avx512f")]
1354 unsafe fn test_mm512_div_pd() {
1355 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1356 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1357 let r = _mm512_div_pd(a, b);
1358 #[rustfmt::skip]
1359 let e = _mm512_setr_pd(
1360 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1361 f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1362 );
1363 assert_eq_m512d(r, e);
1364 }
1365
1366 #[simd_test(enable = "avx512f")]
1367 unsafe fn test_mm512_mask_div_pd() {
1368 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1369 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1370 let r = _mm512_mask_div_pd(a, 0, a, b);
1371 assert_eq_m512d(r, a);
1372 let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1373 #[rustfmt::skip]
1374 let e = _mm512_setr_pd(
1375 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1376 f64::MAX, f64::MIN, -100., -32.,
1377 );
1378 assert_eq_m512d(r, e);
1379 }
1380
1381 #[simd_test(enable = "avx512f")]
1382 unsafe fn test_mm512_maskz_div_pd() {
1383 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1384 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1385 let r = _mm512_maskz_div_pd(0, a, b);
1386 assert_eq_m512d(r, _mm512_setzero_pd());
1387 let r = _mm512_maskz_div_pd(0b00001111, a, b);
1388 let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1389 assert_eq_m512d(r, e);
1390 }
1391
1392 #[simd_test(enable = "avx512f,avx512vl")]
1393 unsafe fn test_mm256_mask_div_pd() {
1394 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1395 let b = _mm256_set_pd(2., 2., 0., 0.);
1396 let r = _mm256_mask_div_pd(a, 0, a, b);
1397 assert_eq_m256d(r, a);
1398 let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1399 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1400 assert_eq_m256d(r, e);
1401 }
1402
1403 #[simd_test(enable = "avx512f,avx512vl")]
1404 unsafe fn test_mm256_maskz_div_pd() {
1405 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1406 let b = _mm256_set_pd(2., 2., 0., 0.);
1407 let r = _mm256_maskz_div_pd(0, a, b);
1408 assert_eq_m256d(r, _mm256_setzero_pd());
1409 let r = _mm256_maskz_div_pd(0b00001111, a, b);
1410 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1411 assert_eq_m256d(r, e);
1412 }
1413
1414 #[simd_test(enable = "avx512f,avx512vl")]
1415 unsafe fn test_mm_mask_div_pd() {
1416 let a = _mm_set_pd(f64::MAX, f64::MIN);
1417 let b = _mm_set_pd(0., 0.);
1418 let r = _mm_mask_div_pd(a, 0, a, b);
1419 assert_eq_m128d(r, a);
1420 let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1421 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1422 assert_eq_m128d(r, e);
1423 }
1424
1425 #[simd_test(enable = "avx512f,avx512vl")]
1426 unsafe fn test_mm_maskz_div_pd() {
1427 let a = _mm_set_pd(f64::MAX, f64::MIN);
1428 let b = _mm_set_pd(0., 0.);
1429 let r = _mm_maskz_div_pd(0, a, b);
1430 assert_eq_m128d(r, _mm_setzero_pd());
1431 let r = _mm_maskz_div_pd(0b00000011, a, b);
1432 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1433 assert_eq_m128d(r, e);
1434 }
1435
1436 #[simd_test(enable = "avx512f")]
1437 unsafe fn test_mm512_max_epi64() {
1438 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1439 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1440 let r = _mm512_max_epi64(a, b);
1441 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1442 assert_eq_m512i(r, e);
1443 }
1444
1445 #[simd_test(enable = "avx512f")]
1446 unsafe fn test_mm512_mask_max_epi64() {
1447 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1448 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1449 let r = _mm512_mask_max_epi64(a, 0, a, b);
1450 assert_eq_m512i(r, a);
1451 let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1452 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1453 assert_eq_m512i(r, e);
1454 }
1455
1456 #[simd_test(enable = "avx512f")]
1457 unsafe fn test_mm512_maskz_max_epi64() {
1458 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1459 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1460 let r = _mm512_maskz_max_epi64(0, a, b);
1461 assert_eq_m512i(r, _mm512_setzero_si512());
1462 let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1463 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1464 assert_eq_m512i(r, e);
1465 }
1466
1467 #[simd_test(enable = "avx512f,avx512vl")]
1468 unsafe fn test_mm256_max_epi64() {
1469 let a = _mm256_set_epi64x(0, 1, 2, 3);
1470 let b = _mm256_set_epi64x(3, 2, 1, 0);
1471 let r = _mm256_max_epi64(a, b);
1472 let e = _mm256_set_epi64x(3, 2, 2, 3);
1473 assert_eq_m256i(r, e);
1474 }
1475
1476 #[simd_test(enable = "avx512f,avx512vl")]
1477 unsafe fn test_mm256_mask_max_epi64() {
1478 let a = _mm256_set_epi64x(0, 1, 2, 3);
1479 let b = _mm256_set_epi64x(3, 2, 1, 0);
1480 let r = _mm256_mask_max_epi64(a, 0, a, b);
1481 assert_eq_m256i(r, a);
1482 let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1483 let e = _mm256_set_epi64x(3, 2, 2, 3);
1484 assert_eq_m256i(r, e);
1485 }
1486
1487 #[simd_test(enable = "avx512f,avx512vl")]
1488 unsafe fn test_mm256_maskz_max_epi64() {
1489 let a = _mm256_set_epi64x(0, 1, 2, 3);
1490 let b = _mm256_set_epi64x(3, 2, 1, 0);
1491 let r = _mm256_maskz_max_epi64(0, a, b);
1492 assert_eq_m256i(r, _mm256_setzero_si256());
1493 let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1494 let e = _mm256_set_epi64x(3, 2, 2, 3);
1495 assert_eq_m256i(r, e);
1496 }
1497
1498 #[simd_test(enable = "avx512f,avx512vl")]
1499 unsafe fn test_mm_max_epi64() {
1500 let a = _mm_set_epi64x(2, 3);
1501 let b = _mm_set_epi64x(3, 2);
1502 let r = _mm_max_epi64(a, b);
1503 let e = _mm_set_epi64x(3, 3);
1504 assert_eq_m128i(r, e);
1505 }
1506
1507 #[simd_test(enable = "avx512f,avx512vl")]
1508 unsafe fn test_mm_mask_max_epi64() {
1509 let a = _mm_set_epi64x(2, 3);
1510 let b = _mm_set_epi64x(3, 2);
1511 let r = _mm_mask_max_epi64(a, 0, a, b);
1512 assert_eq_m128i(r, a);
1513 let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1514 let e = _mm_set_epi64x(3, 3);
1515 assert_eq_m128i(r, e);
1516 }
1517
1518 #[simd_test(enable = "avx512f,avx512vl")]
1519 unsafe fn test_mm_maskz_max_epi64() {
1520 let a = _mm_set_epi64x(2, 3);
1521 let b = _mm_set_epi64x(3, 2);
1522 let r = _mm_maskz_max_epi64(0, a, b);
1523 assert_eq_m128i(r, _mm_setzero_si128());
1524 let r = _mm_maskz_max_epi64(0b00000011, a, b);
1525 let e = _mm_set_epi64x(3, 3);
1526 assert_eq_m128i(r, e);
1527 }
1528
1529 #[simd_test(enable = "avx512f")]
1530 unsafe fn test_mm512_max_pd() {
1531 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1532 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1533 let r = _mm512_max_pd(a, b);
1534 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1535 assert_eq_m512d(r, e);
1536 }
1537
1538 #[simd_test(enable = "avx512f")]
1539 unsafe fn test_mm512_mask_max_pd() {
1540 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1541 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1542 let r = _mm512_mask_max_pd(a, 0, a, b);
1543 assert_eq_m512d(r, a);
1544 let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1545 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1546 assert_eq_m512d(r, e);
1547 }
1548
1549 #[simd_test(enable = "avx512f")]
1550 unsafe fn test_mm512_maskz_max_pd() {
1551 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1552 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1553 let r = _mm512_maskz_max_pd(0, a, b);
1554 assert_eq_m512d(r, _mm512_setzero_pd());
1555 let r = _mm512_maskz_max_pd(0b00001111, a, b);
1556 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1557 assert_eq_m512d(r, e);
1558 }
1559
1560 #[simd_test(enable = "avx512f,avx512vl")]
1561 unsafe fn test_mm256_mask_max_pd() {
1562 let a = _mm256_set_pd(0., 1., 2., 3.);
1563 let b = _mm256_set_pd(3., 2., 1., 0.);
1564 let r = _mm256_mask_max_pd(a, 0, a, b);
1565 assert_eq_m256d(r, a);
1566 let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1567 let e = _mm256_set_pd(3., 2., 2., 3.);
1568 assert_eq_m256d(r, e);
1569 }
1570
1571 #[simd_test(enable = "avx512f,avx512vl")]
1572 unsafe fn test_mm256_maskz_max_pd() {
1573 let a = _mm256_set_pd(0., 1., 2., 3.);
1574 let b = _mm256_set_pd(3., 2., 1., 0.);
1575 let r = _mm256_maskz_max_pd(0, a, b);
1576 assert_eq_m256d(r, _mm256_setzero_pd());
1577 let r = _mm256_maskz_max_pd(0b00001111, a, b);
1578 let e = _mm256_set_pd(3., 2., 2., 3.);
1579 assert_eq_m256d(r, e);
1580 }
1581
1582 #[simd_test(enable = "avx512f,avx512vl")]
1583 unsafe fn test_mm_mask_max_pd() {
1584 let a = _mm_set_pd(2., 3.);
1585 let b = _mm_set_pd(3., 2.);
1586 let r = _mm_mask_max_pd(a, 0, a, b);
1587 assert_eq_m128d(r, a);
1588 let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1589 let e = _mm_set_pd(3., 3.);
1590 assert_eq_m128d(r, e);
1591 }
1592
1593 #[simd_test(enable = "avx512f,avx512vl")]
1594 unsafe fn test_mm_maskz_max_pd() {
1595 let a = _mm_set_pd(2., 3.);
1596 let b = _mm_set_pd(3., 2.);
1597 let r = _mm_maskz_max_pd(0, a, b);
1598 assert_eq_m128d(r, _mm_setzero_pd());
1599 let r = _mm_maskz_max_pd(0b00000011, a, b);
1600 let e = _mm_set_pd(3., 3.);
1601 assert_eq_m128d(r, e);
1602 }
1603
1604 #[simd_test(enable = "avx512f")]
1605 unsafe fn test_mm512_max_epu64() {
1606 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1607 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1608 let r = _mm512_max_epu64(a, b);
1609 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1610 assert_eq_m512i(r, e);
1611 }
1612
1613 #[simd_test(enable = "avx512f")]
1614 unsafe fn test_mm512_mask_max_epu64() {
1615 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1616 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1617 let r = _mm512_mask_max_epu64(a, 0, a, b);
1618 assert_eq_m512i(r, a);
1619 let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1620 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1621 assert_eq_m512i(r, e);
1622 }
1623
1624 #[simd_test(enable = "avx512f")]
1625 unsafe fn test_mm512_maskz_max_epu64() {
1626 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1627 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1628 let r = _mm512_maskz_max_epu64(0, a, b);
1629 assert_eq_m512i(r, _mm512_setzero_si512());
1630 let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1631 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1632 assert_eq_m512i(r, e);
1633 }
1634
1635 #[simd_test(enable = "avx512f,avx512vl")]
1636 unsafe fn test_mm256_max_epu64() {
1637 let a = _mm256_set_epi64x(0, 1, 2, 3);
1638 let b = _mm256_set_epi64x(3, 2, 1, 0);
1639 let r = _mm256_max_epu64(a, b);
1640 let e = _mm256_set_epi64x(3, 2, 2, 3);
1641 assert_eq_m256i(r, e);
1642 }
1643
1644 #[simd_test(enable = "avx512f,avx512vl")]
1645 unsafe fn test_mm256_mask_max_epu64() {
1646 let a = _mm256_set_epi64x(0, 1, 2, 3);
1647 let b = _mm256_set_epi64x(3, 2, 1, 0);
1648 let r = _mm256_mask_max_epu64(a, 0, a, b);
1649 assert_eq_m256i(r, a);
1650 let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1651 let e = _mm256_set_epi64x(3, 2, 2, 3);
1652 assert_eq_m256i(r, e);
1653 }
1654
1655 #[simd_test(enable = "avx512f,avx512vl")]
1656 unsafe fn test_mm256_maskz_max_epu64() {
1657 let a = _mm256_set_epi64x(0, 1, 2, 3);
1658 let b = _mm256_set_epi64x(3, 2, 1, 0);
1659 let r = _mm256_maskz_max_epu64(0, a, b);
1660 assert_eq_m256i(r, _mm256_setzero_si256());
1661 let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1662 let e = _mm256_set_epi64x(3, 2, 2, 3);
1663 assert_eq_m256i(r, e);
1664 }
1665
1666 #[simd_test(enable = "avx512f,avx512vl")]
1667 unsafe fn test_mm_max_epu64() {
1668 let a = _mm_set_epi64x(2, 3);
1669 let b = _mm_set_epi64x(3, 2);
1670 let r = _mm_max_epu64(a, b);
1671 let e = _mm_set_epi64x(3, 3);
1672 assert_eq_m128i(r, e);
1673 }
1674
1675 #[simd_test(enable = "avx512f,avx512vl")]
1676 unsafe fn test_mm_mask_max_epu64() {
1677 let a = _mm_set_epi64x(2, 3);
1678 let b = _mm_set_epi64x(3, 2);
1679 let r = _mm_mask_max_epu64(a, 0, a, b);
1680 assert_eq_m128i(r, a);
1681 let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1682 let e = _mm_set_epi64x(3, 3);
1683 assert_eq_m128i(r, e);
1684 }
1685
1686 #[simd_test(enable = "avx512f,avx512vl")]
1687 unsafe fn test_mm_maskz_max_epu64() {
1688 let a = _mm_set_epi64x(2, 3);
1689 let b = _mm_set_epi64x(3, 2);
1690 let r = _mm_maskz_max_epu64(0, a, b);
1691 assert_eq_m128i(r, _mm_setzero_si128());
1692 let r = _mm_maskz_max_epu64(0b00000011, a, b);
1693 let e = _mm_set_epi64x(3, 3);
1694 assert_eq_m128i(r, e);
1695 }
1696
1697 #[simd_test(enable = "avx512f")]
1698 unsafe fn test_mm512_min_epi64() {
1699 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1700 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1701 let r = _mm512_min_epi64(a, b);
1702 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1703 assert_eq_m512i(r, e);
1704 }
1705
1706 #[simd_test(enable = "avx512f")]
1707 unsafe fn test_mm512_mask_min_epi64() {
1708 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1709 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1710 let r = _mm512_mask_min_epi64(a, 0, a, b);
1711 assert_eq_m512i(r, a);
1712 let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1713 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1714 assert_eq_m512i(r, e);
1715 }
1716
1717 #[simd_test(enable = "avx512f")]
1718 unsafe fn test_mm512_maskz_min_epi64() {
1719 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1720 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1721 let r = _mm512_maskz_min_epi64(0, a, b);
1722 assert_eq_m512i(r, _mm512_setzero_si512());
1723 let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1724 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1725 assert_eq_m512i(r, e);
1726 }
1727
1728 #[simd_test(enable = "avx512f,avx512vl")]
1729 unsafe fn test_mm256_min_epi64() {
1730 let a = _mm256_set_epi64x(0, 1, 2, 3);
1731 let b = _mm256_set_epi64x(3, 2, 1, 0);
1732 let r = _mm256_min_epi64(a, b);
1733 let e = _mm256_set_epi64x(0, 1, 1, 0);
1734 assert_eq_m256i(r, e);
1735 }
1736
1737 #[simd_test(enable = "avx512f,avx512vl")]
1738 unsafe fn test_mm256_mask_min_epi64() {
1739 let a = _mm256_set_epi64x(0, 1, 2, 3);
1740 let b = _mm256_set_epi64x(3, 2, 1, 0);
1741 let r = _mm256_mask_min_epi64(a, 0, a, b);
1742 assert_eq_m256i(r, a);
1743 let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1744 let e = _mm256_set_epi64x(0, 1, 1, 0);
1745 assert_eq_m256i(r, e);
1746 }
1747
1748 #[simd_test(enable = "avx512f,avx512vl")]
1749 unsafe fn test_mm256_maskz_min_epi64() {
1750 let a = _mm256_set_epi64x(0, 1, 2, 3);
1751 let b = _mm256_set_epi64x(3, 2, 1, 0);
1752 let r = _mm256_maskz_min_epi64(0, a, b);
1753 assert_eq_m256i(r, _mm256_setzero_si256());
1754 let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1755 let e = _mm256_set_epi64x(0, 1, 1, 0);
1756 assert_eq_m256i(r, e);
1757 }
1758
1759 #[simd_test(enable = "avx512f,avx512vl")]
1760 unsafe fn test_mm_min_epi64() {
1761 let a = _mm_set_epi64x(0, 1);
1762 let b = _mm_set_epi64x(3, 2);
1763 let r = _mm_min_epi64(a, b);
1764 let e = _mm_set_epi64x(0, 1);
1765 assert_eq_m128i(r, e);
1766 let a = _mm_set_epi64x(2, 3);
1767 let b = _mm_set_epi64x(1, 0);
1768 let r = _mm_min_epi64(a, b);
1769 let e = _mm_set_epi64x(1, 0);
1770 assert_eq_m128i(r, e);
1771 }
1772
1773 #[simd_test(enable = "avx512f,avx512vl")]
1774 unsafe fn test_mm_mask_min_epi64() {
1775 let a = _mm_set_epi64x(0, 1);
1776 let b = _mm_set_epi64x(3, 2);
1777 let r = _mm_mask_min_epi64(a, 0, a, b);
1778 assert_eq_m128i(r, a);
1779 let r = _mm_mask_min_epi64(a, 0b00000011, a, b);
1780 let e = _mm_set_epi64x(0, 1);
1781 assert_eq_m128i(r, e);
1782 }
1783
1784 #[simd_test(enable = "avx512f,avx512vl")]
1785 unsafe fn test_mm_maskz_min_epi64() {
1786 let a = _mm_set_epi64x(0, 1);
1787 let b = _mm_set_epi64x(3, 2);
1788 let r = _mm_maskz_min_epi64(0, a, b);
1789 assert_eq_m128i(r, _mm_setzero_si128());
1790 let r = _mm_maskz_min_epi64(0b00000011, a, b);
1791 let e = _mm_set_epi64x(0, 1);
1792 assert_eq_m128i(r, e);
1793 }
1794
1795 #[simd_test(enable = "avx512f")]
1796 unsafe fn test_mm512_min_pd() {
1797 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1798 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1799 let r = _mm512_min_pd(a, b);
1800 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1801 assert_eq_m512d(r, e);
1802 }
1803
1804 #[simd_test(enable = "avx512f")]
1805 unsafe fn test_mm512_mask_min_pd() {
1806 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1807 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1808 let r = _mm512_mask_min_pd(a, 0, a, b);
1809 assert_eq_m512d(r, a);
1810 let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1811 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1812 assert_eq_m512d(r, e);
1813 }
1814
1815 #[simd_test(enable = "avx512f")]
1816 unsafe fn test_mm512_maskz_min_pd() {
1817 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1818 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1819 let r = _mm512_maskz_min_pd(0, a, b);
1820 assert_eq_m512d(r, _mm512_setzero_pd());
1821 let r = _mm512_maskz_min_pd(0b00001111, a, b);
1822 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1823 assert_eq_m512d(r, e);
1824 }
1825
1826 #[simd_test(enable = "avx512f,avx512vl")]
1827 unsafe fn test_mm256_mask_min_pd() {
1828 let a = _mm256_set_pd(0., 1., 2., 3.);
1829 let b = _mm256_set_pd(3., 2., 1., 0.);
1830 let r = _mm256_mask_min_pd(a, 0, a, b);
1831 assert_eq_m256d(r, a);
1832 let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1833 let e = _mm256_set_pd(0., 1., 1., 0.);
1834 assert_eq_m256d(r, e);
1835 }
1836
1837 #[simd_test(enable = "avx512f,avx512vl")]
1838 unsafe fn test_mm256_maskz_min_pd() {
1839 let a = _mm256_set_pd(0., 1., 2., 3.);
1840 let b = _mm256_set_pd(3., 2., 1., 0.);
1841 let r = _mm256_maskz_min_pd(0, a, b);
1842 assert_eq_m256d(r, _mm256_setzero_pd());
1843 let r = _mm256_maskz_min_pd(0b00001111, a, b);
1844 let e = _mm256_set_pd(0., 1., 1., 0.);
1845 assert_eq_m256d(r, e);
1846 }
1847
1848 #[simd_test(enable = "avx512f,avx512vl")]
1849 unsafe fn test_mm_mask_min_pd() {
1850 let a = _mm_set_pd(0., 1.);
1851 let b = _mm_set_pd(1., 0.);
1852 let r = _mm_mask_min_pd(a, 0, a, b);
1853 assert_eq_m128d(r, a);
1854 let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1855 let e = _mm_set_pd(0., 0.);
1856 assert_eq_m128d(r, e);
1857 }
1858
1859 #[simd_test(enable = "avx512f,avx512vl")]
1860 unsafe fn test_mm_maskz_min_pd() {
1861 let a = _mm_set_pd(0., 1.);
1862 let b = _mm_set_pd(1., 0.);
1863 let r = _mm_maskz_min_pd(0, a, b);
1864 assert_eq_m128d(r, _mm_setzero_pd());
1865 let r = _mm_maskz_min_pd(0b00000011, a, b);
1866 let e = _mm_set_pd(0., 0.);
1867 assert_eq_m128d(r, e);
1868 }
1869
1870 #[simd_test(enable = "avx512f")]
1871 unsafe fn test_mm512_min_epu64() {
1872 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1873 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1874 let r = _mm512_min_epu64(a, b);
1875 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1876 assert_eq_m512i(r, e);
1877 }
1878
1879 #[simd_test(enable = "avx512f")]
1880 unsafe fn test_mm512_mask_min_epu64() {
1881 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1882 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1883 let r = _mm512_mask_min_epu64(a, 0, a, b);
1884 assert_eq_m512i(r, a);
1885 let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1886 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1887 assert_eq_m512i(r, e);
1888 }
1889
1890 #[simd_test(enable = "avx512f")]
1891 unsafe fn test_mm512_maskz_min_epu64() {
1892 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1893 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1894 let r = _mm512_maskz_min_epu64(0, a, b);
1895 assert_eq_m512i(r, _mm512_setzero_si512());
1896 let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1897 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1898 assert_eq_m512i(r, e);
1899 }
1900
1901 #[simd_test(enable = "avx512f,avx512vl")]
1902 unsafe fn test_mm256_min_epu64() {
1903 let a = _mm256_set_epi64x(0, 1, 2, 3);
1904 let b = _mm256_set_epi64x(3, 2, 1, 0);
1905 let r = _mm256_min_epu64(a, b);
1906 let e = _mm256_set_epi64x(0, 1, 1, 0);
1907 assert_eq_m256i(r, e);
1908 }
1909
1910 #[simd_test(enable = "avx512f,avx512vl")]
1911 unsafe fn test_mm256_mask_min_epu64() {
1912 let a = _mm256_set_epi64x(0, 1, 2, 3);
1913 let b = _mm256_set_epi64x(3, 2, 1, 0);
1914 let r = _mm256_mask_min_epu64(a, 0, a, b);
1915 assert_eq_m256i(r, a);
1916 let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1917 let e = _mm256_set_epi64x(0, 1, 1, 0);
1918 assert_eq_m256i(r, e);
1919 }
1920
1921 #[simd_test(enable = "avx512f,avx512vl")]
1922 unsafe fn test_mm256_maskz_min_epu64() {
1923 let a = _mm256_set_epi64x(0, 1, 2, 3);
1924 let b = _mm256_set_epi64x(3, 2, 1, 0);
1925 let r = _mm256_maskz_min_epu64(0, a, b);
1926 assert_eq_m256i(r, _mm256_setzero_si256());
1927 let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1928 let e = _mm256_set_epi64x(0, 1, 1, 0);
1929 assert_eq_m256i(r, e);
1930 }
1931
1932 #[simd_test(enable = "avx512f,avx512vl")]
1933 unsafe fn test_mm_min_epu64() {
1934 let a = _mm_set_epi64x(0, 1);
1935 let b = _mm_set_epi64x(1, 0);
1936 let r = _mm_min_epu64(a, b);
1937 let e = _mm_set_epi64x(0, 0);
1938 assert_eq_m128i(r, e);
1939 }
1940
1941 #[simd_test(enable = "avx512f,avx512vl")]
1942 unsafe fn test_mm_mask_min_epu64() {
1943 let a = _mm_set_epi64x(0, 1);
1944 let b = _mm_set_epi64x(1, 0);
1945 let r = _mm_mask_min_epu64(a, 0, a, b);
1946 assert_eq_m128i(r, a);
1947 let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1948 let e = _mm_set_epi64x(0, 0);
1949 assert_eq_m128i(r, e);
1950 }
1951
1952 #[simd_test(enable = "avx512f,avx512vl")]
1953 unsafe fn test_mm_maskz_min_epu64() {
1954 let a = _mm_set_epi64x(0, 1);
1955 let b = _mm_set_epi64x(1, 0);
1956 let r = _mm_maskz_min_epu64(0, a, b);
1957 assert_eq_m128i(r, _mm_setzero_si128());
1958 let r = _mm_maskz_min_epu64(0b00000011, a, b);
1959 let e = _mm_set_epi64x(0, 0);
1960 assert_eq_m128i(r, e);
1961 }
1962
1963 #[simd_test(enable = "avx512f")]
1964 unsafe fn test_mm512_sqrt_pd() {
1965 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1966 let r = _mm512_sqrt_pd(a);
1967 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1968 assert_eq_m512d(r, e);
1969 }
1970
1971 #[simd_test(enable = "avx512f")]
1972 unsafe fn test_mm512_mask_sqrt_pd() {
1973 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1974 let r = _mm512_mask_sqrt_pd(a, 0, a);
1975 assert_eq_m512d(r, a);
1976 let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1977 let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1978 assert_eq_m512d(r, e);
1979 }
1980
1981 #[simd_test(enable = "avx512f")]
1982 unsafe fn test_mm512_maskz_sqrt_pd() {
1983 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1984 let r = _mm512_maskz_sqrt_pd(0, a);
1985 assert_eq_m512d(r, _mm512_setzero_pd());
1986 let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1987 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1988 assert_eq_m512d(r, e);
1989 }
1990
1991 #[simd_test(enable = "avx512f,avx512vl")]
1992 unsafe fn test_mm256_mask_sqrt_pd() {
1993 let a = _mm256_set_pd(0., 1., 4., 9.);
1994 let r = _mm256_mask_sqrt_pd(a, 0, a);
1995 assert_eq_m256d(r, a);
1996 let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
1997 let e = _mm256_set_pd(0., 1., 2., 3.);
1998 assert_eq_m256d(r, e);
1999 }
2000
2001 #[simd_test(enable = "avx512f,avx512vl")]
2002 unsafe fn test_mm256_maskz_sqrt_pd() {
2003 let a = _mm256_set_pd(0., 1., 4., 9.);
2004 let r = _mm256_maskz_sqrt_pd(0, a);
2005 assert_eq_m256d(r, _mm256_setzero_pd());
2006 let r = _mm256_maskz_sqrt_pd(0b00001111, a);
2007 let e = _mm256_set_pd(0., 1., 2., 3.);
2008 assert_eq_m256d(r, e);
2009 }
2010
2011 #[simd_test(enable = "avx512f,avx512vl")]
2012 unsafe fn test_mm_mask_sqrt_pd() {
2013 let a = _mm_set_pd(0., 1.);
2014 let r = _mm_mask_sqrt_pd(a, 0, a);
2015 assert_eq_m128d(r, a);
2016 let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
2017 let e = _mm_set_pd(0., 1.);
2018 assert_eq_m128d(r, e);
2019 }
2020
2021 #[simd_test(enable = "avx512f,avx512vl")]
2022 unsafe fn test_mm_maskz_sqrt_pd() {
2023 let a = _mm_set_pd(0., 1.);
2024 let r = _mm_maskz_sqrt_pd(0, a);
2025 assert_eq_m128d(r, _mm_setzero_pd());
2026 let r = _mm_maskz_sqrt_pd(0b00000011, a);
2027 let e = _mm_set_pd(0., 1.);
2028 assert_eq_m128d(r, e);
2029 }
2030
2031 #[simd_test(enable = "avx512f")]
2032 unsafe fn test_mm512_fmadd_pd() {
2033 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2034 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2035 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2036 let r = _mm512_fmadd_pd(a, b, c);
2037 let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
2038 assert_eq_m512d(r, e);
2039 }
2040
2041 #[simd_test(enable = "avx512f")]
2042 unsafe fn test_mm512_mask_fmadd_pd() {
2043 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2044 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2045 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2046 let r = _mm512_mask_fmadd_pd(a, 0, b, c);
2047 assert_eq_m512d(r, a);
2048 let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
2049 let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
2050 assert_eq_m512d(r, e);
2051 }
2052
2053 #[simd_test(enable = "avx512f")]
2054 unsafe fn test_mm512_maskz_fmadd_pd() {
2055 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2056 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2057 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2058 let r = _mm512_maskz_fmadd_pd(0, a, b, c);
2059 assert_eq_m512d(r, _mm512_setzero_pd());
2060 let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
2061 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
2062 assert_eq_m512d(r, e);
2063 }
2064
2065 #[simd_test(enable = "avx512f")]
2066 unsafe fn test_mm512_mask3_fmadd_pd() {
2067 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2068 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2069 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2070 let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
2071 assert_eq_m512d(r, c);
2072 let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
2073 let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
2074 assert_eq_m512d(r, e);
2075 }
2076
2077 #[simd_test(enable = "avx512f,avx512vl")]
2078 unsafe fn test_mm256_mask_fmadd_pd() {
2079 let a = _mm256_set1_pd(1.);
2080 let b = _mm256_set_pd(0., 1., 2., 3.);
2081 let c = _mm256_set1_pd(1.);
2082 let r = _mm256_mask_fmadd_pd(a, 0, b, c);
2083 assert_eq_m256d(r, a);
2084 let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
2085 let e = _mm256_set_pd(1., 2., 3., 4.);
2086 assert_eq_m256d(r, e);
2087 }
2088
2089 #[simd_test(enable = "avx512f,avx512vl")]
2090 unsafe fn test_mm256_maskz_fmadd_pd() {
2091 let a = _mm256_set1_pd(1.);
2092 let b = _mm256_set_pd(0., 1., 2., 3.);
2093 let c = _mm256_set1_pd(1.);
2094 let r = _mm256_maskz_fmadd_pd(0, a, b, c);
2095 assert_eq_m256d(r, _mm256_setzero_pd());
2096 let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
2097 let e = _mm256_set_pd(1., 2., 3., 4.);
2098 assert_eq_m256d(r, e);
2099 }
2100
2101 #[simd_test(enable = "avx512f,avx512vl")]
2102 unsafe fn test_mm256_mask3_fmadd_pd() {
2103 let a = _mm256_set1_pd(1.);
2104 let b = _mm256_set_pd(0., 1., 2., 3.);
2105 let c = _mm256_set1_pd(1.);
2106 let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
2107 assert_eq_m256d(r, c);
2108 let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
2109 let e = _mm256_set_pd(1., 2., 3., 4.);
2110 assert_eq_m256d(r, e);
2111 }
2112
2113 #[simd_test(enable = "avx512f,avx512vl")]
2114 unsafe fn test_mm_mask_fmadd_pd() {
2115 let a = _mm_set1_pd(1.);
2116 let b = _mm_set_pd(0., 1.);
2117 let c = _mm_set1_pd(1.);
2118 let r = _mm_mask_fmadd_pd(a, 0, b, c);
2119 assert_eq_m128d(r, a);
2120 let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
2121 let e = _mm_set_pd(1., 2.);
2122 assert_eq_m128d(r, e);
2123 }
2124
2125 #[simd_test(enable = "avx512f,avx512vl")]
2126 unsafe fn test_mm_maskz_fmadd_pd() {
2127 let a = _mm_set1_pd(1.);
2128 let b = _mm_set_pd(0., 1.);
2129 let c = _mm_set1_pd(1.);
2130 let r = _mm_maskz_fmadd_pd(0, a, b, c);
2131 assert_eq_m128d(r, _mm_setzero_pd());
2132 let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2133 let e = _mm_set_pd(1., 2.);
2134 assert_eq_m128d(r, e);
2135 }
2136
2137 #[simd_test(enable = "avx512f,avx512vl")]
2138 unsafe fn test_mm_mask3_fmadd_pd() {
2139 let a = _mm_set1_pd(1.);
2140 let b = _mm_set_pd(0., 1.);
2141 let c = _mm_set1_pd(1.);
2142 let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2143 assert_eq_m128d(r, c);
2144 let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2145 let e = _mm_set_pd(1., 2.);
2146 assert_eq_m128d(r, e);
2147 }
2148
2149 #[simd_test(enable = "avx512f")]
2150 unsafe fn test_mm512_fmsub_pd() {
2151 let a = _mm512_set1_pd(1.);
2152 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2153 let c = _mm512_set1_pd(1.);
2154 let r = _mm512_fmsub_pd(a, b, c);
2155 let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2156 assert_eq_m512d(r, e);
2157 }
2158
2159 #[simd_test(enable = "avx512f")]
2160 unsafe fn test_mm512_mask_fmsub_pd() {
2161 let a = _mm512_set1_pd(1.);
2162 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2163 let c = _mm512_set1_pd(1.);
2164 let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2165 assert_eq_m512d(r, a);
2166 let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2167 let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2168 assert_eq_m512d(r, e);
2169 }
2170
2171 #[simd_test(enable = "avx512f")]
2172 unsafe fn test_mm512_maskz_fmsub_pd() {
2173 let a = _mm512_set1_pd(1.);
2174 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2175 let c = _mm512_set1_pd(1.);
2176 let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2177 assert_eq_m512d(r, _mm512_setzero_pd());
2178 let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2179 let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2180 assert_eq_m512d(r, e);
2181 }
2182
2183 #[simd_test(enable = "avx512f")]
2184 unsafe fn test_mm512_mask3_fmsub_pd() {
2185 let a = _mm512_set1_pd(1.);
2186 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2187 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2188 let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2189 assert_eq_m512d(r, c);
2190 let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2191 let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2192 assert_eq_m512d(r, e);
2193 }
2194
2195 #[simd_test(enable = "avx512f,avx512vl")]
2196 unsafe fn test_mm256_mask_fmsub_pd() {
2197 let a = _mm256_set1_pd(1.);
2198 let b = _mm256_set_pd(0., 1., 2., 3.);
2199 let c = _mm256_set1_pd(1.);
2200 let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2201 assert_eq_m256d(r, a);
2202 let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2203 let e = _mm256_set_pd(-1., 0., 1., 2.);
2204 assert_eq_m256d(r, e);
2205 }
2206
2207 #[simd_test(enable = "avx512f,avx512vl")]
2208 unsafe fn test_mm256_maskz_fmsub_pd() {
2209 let a = _mm256_set1_pd(1.);
2210 let b = _mm256_set_pd(0., 1., 2., 3.);
2211 let c = _mm256_set1_pd(1.);
2212 let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2213 assert_eq_m256d(r, _mm256_setzero_pd());
2214 let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2215 let e = _mm256_set_pd(-1., 0., 1., 2.);
2216 assert_eq_m256d(r, e);
2217 }
2218
2219 #[simd_test(enable = "avx512f,avx512vl")]
2220 unsafe fn test_mm256_mask3_fmsub_pd() {
2221 let a = _mm256_set1_pd(1.);
2222 let b = _mm256_set_pd(0., 1., 2., 3.);
2223 let c = _mm256_set1_pd(1.);
2224 let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2225 assert_eq_m256d(r, c);
2226 let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2227 let e = _mm256_set_pd(-1., 0., 1., 2.);
2228 assert_eq_m256d(r, e);
2229 }
2230
2231 #[simd_test(enable = "avx512f,avx512vl")]
2232 unsafe fn test_mm_mask_fmsub_pd() {
2233 let a = _mm_set1_pd(1.);
2234 let b = _mm_set_pd(0., 1.);
2235 let c = _mm_set1_pd(1.);
2236 let r = _mm_mask_fmsub_pd(a, 0, b, c);
2237 assert_eq_m128d(r, a);
2238 let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2239 let e = _mm_set_pd(-1., 0.);
2240 assert_eq_m128d(r, e);
2241 }
2242
2243 #[simd_test(enable = "avx512f,avx512vl")]
2244 unsafe fn test_mm_maskz_fmsub_pd() {
2245 let a = _mm_set1_pd(1.);
2246 let b = _mm_set_pd(0., 1.);
2247 let c = _mm_set1_pd(1.);
2248 let r = _mm_maskz_fmsub_pd(0, a, b, c);
2249 assert_eq_m128d(r, _mm_setzero_pd());
2250 let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2251 let e = _mm_set_pd(-1., 0.);
2252 assert_eq_m128d(r, e);
2253 }
2254
2255 #[simd_test(enable = "avx512f,avx512vl")]
2256 unsafe fn test_mm_mask3_fmsub_pd() {
2257 let a = _mm_set1_pd(1.);
2258 let b = _mm_set_pd(0., 1.);
2259 let c = _mm_set1_pd(1.);
2260 let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2261 assert_eq_m128d(r, c);
2262 let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2263 let e = _mm_set_pd(-1., 0.);
2264 assert_eq_m128d(r, e);
2265 }
2266
2267 #[simd_test(enable = "avx512f")]
2268 unsafe fn test_mm512_fmaddsub_pd() {
2269 let a = _mm512_set1_pd(1.);
2270 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2271 let c = _mm512_set1_pd(1.);
2272 let r = _mm512_fmaddsub_pd(a, b, c);
2273 let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2274 assert_eq_m512d(r, e);
2275 }
2276
2277 #[simd_test(enable = "avx512f")]
2278 unsafe fn test_mm512_mask_fmaddsub_pd() {
2279 let a = _mm512_set1_pd(1.);
2280 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2281 let c = _mm512_set1_pd(1.);
2282 let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2283 assert_eq_m512d(r, a);
2284 let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2285 let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2286 assert_eq_m512d(r, e);
2287 }
2288
2289 #[simd_test(enable = "avx512f")]
2290 unsafe fn test_mm512_maskz_fmaddsub_pd() {
2291 let a = _mm512_set1_pd(1.);
2292 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2293 let c = _mm512_set1_pd(1.);
2294 let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2295 assert_eq_m512d(r, _mm512_setzero_pd());
2296 let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2297 let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2298 assert_eq_m512d(r, e);
2299 }
2300
2301 #[simd_test(enable = "avx512f")]
2302 unsafe fn test_mm512_mask3_fmaddsub_pd() {
2303 let a = _mm512_set1_pd(1.);
2304 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2305 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2306 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2307 assert_eq_m512d(r, c);
2308 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2309 let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2310 assert_eq_m512d(r, e);
2311 }
2312
2313 #[simd_test(enable = "avx512f,avx512vl")]
2314 unsafe fn test_mm256_mask_fmaddsub_pd() {
2315 let a = _mm256_set1_pd(1.);
2316 let b = _mm256_set_pd(0., 1., 2., 3.);
2317 let c = _mm256_set1_pd(1.);
2318 let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2319 assert_eq_m256d(r, a);
2320 let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2321 let e = _mm256_set_pd(1., 0., 3., 2.);
2322 assert_eq_m256d(r, e);
2323 }
2324
2325 #[simd_test(enable = "avx512f,avx512vl")]
2326 unsafe fn test_mm256_maskz_fmaddsub_pd() {
2327 let a = _mm256_set1_pd(1.);
2328 let b = _mm256_set_pd(0., 1., 2., 3.);
2329 let c = _mm256_set1_pd(1.);
2330 let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2331 assert_eq_m256d(r, _mm256_setzero_pd());
2332 let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2333 let e = _mm256_set_pd(1., 0., 3., 2.);
2334 assert_eq_m256d(r, e);
2335 }
2336
2337 #[simd_test(enable = "avx512f,avx512vl")]
2338 unsafe fn test_mm256_mask3_fmaddsub_pd() {
2339 let a = _mm256_set1_pd(1.);
2340 let b = _mm256_set_pd(0., 1., 2., 3.);
2341 let c = _mm256_set1_pd(1.);
2342 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2343 assert_eq_m256d(r, c);
2344 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2345 let e = _mm256_set_pd(1., 0., 3., 2.);
2346 assert_eq_m256d(r, e);
2347 }
2348
2349 #[simd_test(enable = "avx512f,avx512vl")]
2350 unsafe fn test_mm_mask_fmaddsub_pd() {
2351 let a = _mm_set1_pd(1.);
2352 let b = _mm_set_pd(0., 1.);
2353 let c = _mm_set1_pd(1.);
2354 let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2355 assert_eq_m128d(r, a);
2356 let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2357 let e = _mm_set_pd(1., 0.);
2358 assert_eq_m128d(r, e);
2359 }
2360
2361 #[simd_test(enable = "avx512f,avx512vl")]
2362 unsafe fn test_mm_maskz_fmaddsub_pd() {
2363 let a = _mm_set1_pd(1.);
2364 let b = _mm_set_pd(0., 1.);
2365 let c = _mm_set1_pd(1.);
2366 let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2367 assert_eq_m128d(r, _mm_setzero_pd());
2368 let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2369 let e = _mm_set_pd(1., 0.);
2370 assert_eq_m128d(r, e);
2371 }
2372
2373 #[simd_test(enable = "avx512f,avx512vl")]
2374 unsafe fn test_mm_mask3_fmaddsub_pd() {
2375 let a = _mm_set1_pd(1.);
2376 let b = _mm_set_pd(0., 1.);
2377 let c = _mm_set1_pd(1.);
2378 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2379 assert_eq_m128d(r, c);
2380 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2381 let e = _mm_set_pd(1., 0.);
2382 assert_eq_m128d(r, e);
2383 }
2384
2385 #[simd_test(enable = "avx512f")]
2386 unsafe fn test_mm512_fmsubadd_pd() {
2387 let a = _mm512_set1_pd(1.);
2388 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2389 let c = _mm512_set1_pd(1.);
2390 let r = _mm512_fmsubadd_pd(a, b, c);
2391 let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2392 assert_eq_m512d(r, e);
2393 }
2394
2395 #[simd_test(enable = "avx512f")]
2396 unsafe fn test_mm512_mask_fmsubadd_pd() {
2397 let a = _mm512_set1_pd(1.);
2398 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2399 let c = _mm512_set1_pd(1.);
2400 let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2401 assert_eq_m512d(r, a);
2402 let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2403 let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2404 assert_eq_m512d(r, e);
2405 }
2406
2407 #[simd_test(enable = "avx512f")]
2408 unsafe fn test_mm512_maskz_fmsubadd_pd() {
2409 let a = _mm512_set1_pd(1.);
2410 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2411 let c = _mm512_set1_pd(1.);
2412 let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2413 assert_eq_m512d(r, _mm512_setzero_pd());
2414 let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2415 let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2416 assert_eq_m512d(r, e);
2417 }
2418
2419 #[simd_test(enable = "avx512f")]
2420 unsafe fn test_mm512_mask3_fmsubadd_pd() {
2421 let a = _mm512_set1_pd(1.);
2422 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2423 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2424 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2425 assert_eq_m512d(r, c);
2426 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2427 let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2428 assert_eq_m512d(r, e);
2429 }
2430
2431 #[simd_test(enable = "avx512f,avx512vl")]
2432 unsafe fn test_mm256_mask_fmsubadd_pd() {
2433 let a = _mm256_set1_pd(1.);
2434 let b = _mm256_set_pd(0., 1., 2., 3.);
2435 let c = _mm256_set1_pd(1.);
2436 let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2437 assert_eq_m256d(r, a);
2438 let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2439 let e = _mm256_set_pd(-1., 2., 1., 4.);
2440 assert_eq_m256d(r, e);
2441 }
2442
2443 #[simd_test(enable = "avx512f,avx512vl")]
2444 unsafe fn test_mm256_maskz_fmsubadd_pd() {
2445 let a = _mm256_set1_pd(1.);
2446 let b = _mm256_set_pd(0., 1., 2., 3.);
2447 let c = _mm256_set1_pd(1.);
2448 let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2449 assert_eq_m256d(r, _mm256_setzero_pd());
2450 let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2451 let e = _mm256_set_pd(-1., 2., 1., 4.);
2452 assert_eq_m256d(r, e);
2453 }
2454
2455 #[simd_test(enable = "avx512f,avx512vl")]
2456 unsafe fn test_mm256_mask3_fmsubadd_pd() {
2457 let a = _mm256_set1_pd(1.);
2458 let b = _mm256_set_pd(0., 1., 2., 3.);
2459 let c = _mm256_set1_pd(1.);
2460 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2461 assert_eq_m256d(r, c);
2462 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2463 let e = _mm256_set_pd(-1., 2., 1., 4.);
2464 assert_eq_m256d(r, e);
2465 }
2466
2467 #[simd_test(enable = "avx512f,avx512vl")]
2468 unsafe fn test_mm_mask_fmsubadd_pd() {
2469 let a = _mm_set1_pd(1.);
2470 let b = _mm_set_pd(0., 1.);
2471 let c = _mm_set1_pd(1.);
2472 let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2473 assert_eq_m128d(r, a);
2474 let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2475 let e = _mm_set_pd(-1., 2.);
2476 assert_eq_m128d(r, e);
2477 }
2478
2479 #[simd_test(enable = "avx512f,avx512vl")]
2480 unsafe fn test_mm_maskz_fmsubadd_pd() {
2481 let a = _mm_set1_pd(1.);
2482 let b = _mm_set_pd(0., 1.);
2483 let c = _mm_set1_pd(1.);
2484 let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2485 assert_eq_m128d(r, _mm_setzero_pd());
2486 let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2487 let e = _mm_set_pd(-1., 2.);
2488 assert_eq_m128d(r, e);
2489 }
2490
2491 #[simd_test(enable = "avx512f,avx512vl")]
2492 unsafe fn test_mm_mask3_fmsubadd_pd() {
2493 let a = _mm_set1_pd(1.);
2494 let b = _mm_set_pd(0., 1.);
2495 let c = _mm_set1_pd(1.);
2496 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2497 assert_eq_m128d(r, c);
2498 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2499 let e = _mm_set_pd(-1., 2.);
2500 assert_eq_m128d(r, e);
2501 }
2502
2503 #[simd_test(enable = "avx512f")]
2504 unsafe fn test_mm512_fnmadd_pd() {
2505 let a = _mm512_set1_pd(1.);
2506 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2507 let c = _mm512_set1_pd(1.);
2508 let r = _mm512_fnmadd_pd(a, b, c);
2509 let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2510 assert_eq_m512d(r, e);
2511 }
2512
2513 #[simd_test(enable = "avx512f")]
2514 unsafe fn test_mm512_mask_fnmadd_pd() {
2515 let a = _mm512_set1_pd(1.);
2516 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2517 let c = _mm512_set1_pd(1.);
2518 let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2519 assert_eq_m512d(r, a);
2520 let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2521 let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2522 assert_eq_m512d(r, e);
2523 }
2524
2525 #[simd_test(enable = "avx512f")]
2526 unsafe fn test_mm512_maskz_fnmadd_pd() {
2527 let a = _mm512_set1_pd(1.);
2528 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2529 let c = _mm512_set1_pd(1.);
2530 let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2531 assert_eq_m512d(r, _mm512_setzero_pd());
2532 let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2533 let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2534 assert_eq_m512d(r, e);
2535 }
2536
2537 #[simd_test(enable = "avx512f")]
2538 unsafe fn test_mm512_mask3_fnmadd_pd() {
2539 let a = _mm512_set1_pd(1.);
2540 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2541 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2542 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2543 assert_eq_m512d(r, c);
2544 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2545 let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2546 assert_eq_m512d(r, e);
2547 }
2548
2549 #[simd_test(enable = "avx512f,avx512vl")]
2550 unsafe fn test_mm256_mask_fnmadd_pd() {
2551 let a = _mm256_set1_pd(1.);
2552 let b = _mm256_set_pd(0., 1., 2., 3.);
2553 let c = _mm256_set1_pd(1.);
2554 let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2555 assert_eq_m256d(r, a);
2556 let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2557 let e = _mm256_set_pd(1., 0., -1., -2.);
2558 assert_eq_m256d(r, e);
2559 }
2560
2561 #[simd_test(enable = "avx512f,avx512vl")]
2562 unsafe fn test_mm256_maskz_fnmadd_pd() {
2563 let a = _mm256_set1_pd(1.);
2564 let b = _mm256_set_pd(0., 1., 2., 3.);
2565 let c = _mm256_set1_pd(1.);
2566 let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2567 assert_eq_m256d(r, _mm256_setzero_pd());
2568 let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2569 let e = _mm256_set_pd(1., 0., -1., -2.);
2570 assert_eq_m256d(r, e);
2571 }
2572
2573 #[simd_test(enable = "avx512f,avx512vl")]
2574 unsafe fn test_mm256_mask3_fnmadd_pd() {
2575 let a = _mm256_set1_pd(1.);
2576 let b = _mm256_set_pd(0., 1., 2., 3.);
2577 let c = _mm256_set1_pd(1.);
2578 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2579 assert_eq_m256d(r, c);
2580 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2581 let e = _mm256_set_pd(1., 0., -1., -2.);
2582 assert_eq_m256d(r, e);
2583 }
2584
2585 #[simd_test(enable = "avx512f,avx512vl")]
2586 unsafe fn test_mm_mask_fnmadd_pd() {
2587 let a = _mm_set1_pd(1.);
2588 let b = _mm_set_pd(0., 1.);
2589 let c = _mm_set1_pd(1.);
2590 let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2591 assert_eq_m128d(r, a);
2592 let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2593 let e = _mm_set_pd(1., 0.);
2594 assert_eq_m128d(r, e);
2595 }
2596
2597 #[simd_test(enable = "avx512f,avx512vl")]
2598 unsafe fn test_mm_maskz_fnmadd_pd() {
2599 let a = _mm_set1_pd(1.);
2600 let b = _mm_set_pd(0., 1.);
2601 let c = _mm_set1_pd(1.);
2602 let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2603 assert_eq_m128d(r, _mm_setzero_pd());
2604 let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2605 let e = _mm_set_pd(1., 0.);
2606 assert_eq_m128d(r, e);
2607 }
2608
2609 #[simd_test(enable = "avx512f,avx512vl")]
2610 unsafe fn test_mm_mask3_fnmadd_pd() {
2611 let a = _mm_set1_pd(1.);
2612 let b = _mm_set_pd(0., 1.);
2613 let c = _mm_set1_pd(1.);
2614 let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2615 assert_eq_m128d(r, c);
2616 let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2617 let e = _mm_set_pd(1., 0.);
2618 assert_eq_m128d(r, e);
2619 }
2620
2621 #[simd_test(enable = "avx512f")]
2622 unsafe fn test_mm512_fnmsub_pd() {
2623 let a = _mm512_set1_pd(1.);
2624 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2625 let c = _mm512_set1_pd(1.);
2626 let r = _mm512_fnmsub_pd(a, b, c);
2627 let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2628 assert_eq_m512d(r, e);
2629 }
2630
2631 #[simd_test(enable = "avx512f")]
2632 unsafe fn test_mm512_mask_fnmsub_pd() {
2633 let a = _mm512_set1_pd(1.);
2634 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2635 let c = _mm512_set1_pd(1.);
2636 let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2637 assert_eq_m512d(r, a);
2638 let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2639 let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2640 assert_eq_m512d(r, e);
2641 }
2642
2643 #[simd_test(enable = "avx512f")]
2644 unsafe fn test_mm512_maskz_fnmsub_pd() {
2645 let a = _mm512_set1_pd(1.);
2646 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2647 let c = _mm512_set1_pd(1.);
2648 let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2649 assert_eq_m512d(r, _mm512_setzero_pd());
2650 let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2651 let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2652 assert_eq_m512d(r, e);
2653 }
2654
2655 #[simd_test(enable = "avx512f")]
2656 unsafe fn test_mm512_mask3_fnmsub_pd() {
2657 let a = _mm512_set1_pd(1.);
2658 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2659 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2660 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2661 assert_eq_m512d(r, c);
2662 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2663 let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2664 assert_eq_m512d(r, e);
2665 }
2666
2667 #[simd_test(enable = "avx512f,avx512vl")]
2668 unsafe fn test_mm256_mask_fnmsub_pd() {
2669 let a = _mm256_set1_pd(1.);
2670 let b = _mm256_set_pd(0., 1., 2., 3.);
2671 let c = _mm256_set1_pd(1.);
2672 let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2673 assert_eq_m256d(r, a);
2674 let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2675 let e = _mm256_set_pd(-1., -2., -3., -4.);
2676 assert_eq_m256d(r, e);
2677 }
2678
2679 #[simd_test(enable = "avx512f,avx512vl")]
2680 unsafe fn test_mm256_maskz_fnmsub_pd() {
2681 let a = _mm256_set1_pd(1.);
2682 let b = _mm256_set_pd(0., 1., 2., 3.);
2683 let c = _mm256_set1_pd(1.);
2684 let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2685 assert_eq_m256d(r, _mm256_setzero_pd());
2686 let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2687 let e = _mm256_set_pd(-1., -2., -3., -4.);
2688 assert_eq_m256d(r, e);
2689 }
2690
2691 #[simd_test(enable = "avx512f,avx512vl")]
2692 unsafe fn test_mm256_mask3_fnmsub_pd() {
2693 let a = _mm256_set1_pd(1.);
2694 let b = _mm256_set_pd(0., 1., 2., 3.);
2695 let c = _mm256_set1_pd(1.);
2696 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2697 assert_eq_m256d(r, c);
2698 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2699 let e = _mm256_set_pd(-1., -2., -3., -4.);
2700 assert_eq_m256d(r, e);
2701 }
2702
2703 #[simd_test(enable = "avx512f,avx512vl")]
2704 unsafe fn test_mm_mask_fnmsub_pd() {
2705 let a = _mm_set1_pd(1.);
2706 let b = _mm_set_pd(0., 1.);
2707 let c = _mm_set1_pd(1.);
2708 let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2709 assert_eq_m128d(r, a);
2710 let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2711 let e = _mm_set_pd(-1., -2.);
2712 assert_eq_m128d(r, e);
2713 }
2714
2715 #[simd_test(enable = "avx512f,avx512vl")]
2716 unsafe fn test_mm_maskz_fnmsub_pd() {
2717 let a = _mm_set1_pd(1.);
2718 let b = _mm_set_pd(0., 1.);
2719 let c = _mm_set1_pd(1.);
2720 let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2721 assert_eq_m128d(r, _mm_setzero_pd());
2722 let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2723 let e = _mm_set_pd(-1., -2.);
2724 assert_eq_m128d(r, e);
2725 }
2726
2727 #[simd_test(enable = "avx512f,avx512vl")]
2728 unsafe fn test_mm_mask3_fnmsub_pd() {
2729 let a = _mm_set1_pd(1.);
2730 let b = _mm_set_pd(0., 1.);
2731 let c = _mm_set1_pd(1.);
2732 let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2733 assert_eq_m128d(r, c);
2734 let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2735 let e = _mm_set_pd(-1., -2.);
2736 assert_eq_m128d(r, e);
2737 }
2738
2739 #[simd_test(enable = "avx512f")]
2740 unsafe fn test_mm512_rcp14_pd() {
2741 let a = _mm512_set1_pd(3.);
2742 let r = _mm512_rcp14_pd(a);
2743 let e = _mm512_set1_pd(0.3333320617675781);
2744 assert_eq_m512d(r, e);
2745 }
2746
2747 #[simd_test(enable = "avx512f")]
2748 unsafe fn test_mm512_mask_rcp14_pd() {
2749 let a = _mm512_set1_pd(3.);
2750 let r = _mm512_mask_rcp14_pd(a, 0, a);
2751 assert_eq_m512d(r, a);
2752 let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2753 #[rustfmt::skip]
2754 let e = _mm512_setr_pd(
2755 3., 3., 3., 3.,
2756 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2757 );
2758 assert_eq_m512d(r, e);
2759 }
2760
2761 #[simd_test(enable = "avx512f")]
2762 unsafe fn test_mm512_maskz_rcp14_pd() {
2763 let a = _mm512_set1_pd(3.);
2764 let r = _mm512_maskz_rcp14_pd(0, a);
2765 assert_eq_m512d(r, _mm512_setzero_pd());
2766 let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2767 #[rustfmt::skip]
2768 let e = _mm512_setr_pd(
2769 0., 0., 0., 0.,
2770 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2771 );
2772 assert_eq_m512d(r, e);
2773 }
2774
2775 #[simd_test(enable = "avx512f,avx512vl")]
2776 unsafe fn test_mm256_rcp14_pd() {
2777 let a = _mm256_set1_pd(3.);
2778 let r = _mm256_rcp14_pd(a);
2779 let e = _mm256_set1_pd(0.3333320617675781);
2780 assert_eq_m256d(r, e);
2781 }
2782
2783 #[simd_test(enable = "avx512f,avx512vl")]
2784 unsafe fn test_mm256_mask_rcp14_pd() {
2785 let a = _mm256_set1_pd(3.);
2786 let r = _mm256_mask_rcp14_pd(a, 0, a);
2787 assert_eq_m256d(r, a);
2788 let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2789 let e = _mm256_set1_pd(0.3333320617675781);
2790 assert_eq_m256d(r, e);
2791 }
2792
2793 #[simd_test(enable = "avx512f,avx512vl")]
2794 unsafe fn test_mm256_maskz_rcp14_pd() {
2795 let a = _mm256_set1_pd(3.);
2796 let r = _mm256_maskz_rcp14_pd(0, a);
2797 assert_eq_m256d(r, _mm256_setzero_pd());
2798 let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2799 let e = _mm256_set1_pd(0.3333320617675781);
2800 assert_eq_m256d(r, e);
2801 }
2802
2803 #[simd_test(enable = "avx512f,avx512vl")]
2804 unsafe fn test_mm_rcp14_pd() {
2805 let a = _mm_set1_pd(3.);
2806 let r = _mm_rcp14_pd(a);
2807 let e = _mm_set1_pd(0.3333320617675781);
2808 assert_eq_m128d(r, e);
2809 }
2810
2811 #[simd_test(enable = "avx512f,avx512vl")]
2812 unsafe fn test_mm_mask_rcp14_pd() {
2813 let a = _mm_set1_pd(3.);
2814 let r = _mm_mask_rcp14_pd(a, 0, a);
2815 assert_eq_m128d(r, a);
2816 let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2817 let e = _mm_set1_pd(0.3333320617675781);
2818 assert_eq_m128d(r, e);
2819 }
2820
2821 #[simd_test(enable = "avx512f,avx512vl")]
2822 unsafe fn test_mm_maskz_rcp14_pd() {
2823 let a = _mm_set1_pd(3.);
2824 let r = _mm_maskz_rcp14_pd(0, a);
2825 assert_eq_m128d(r, _mm_setzero_pd());
2826 let r = _mm_maskz_rcp14_pd(0b00000011, a);
2827 let e = _mm_set1_pd(0.3333320617675781);
2828 assert_eq_m128d(r, e);
2829 }
2830
2831 #[simd_test(enable = "avx512f")]
2832 unsafe fn test_mm512_rsqrt14_pd() {
2833 let a = _mm512_set1_pd(3.);
2834 let r = _mm512_rsqrt14_pd(a);
2835 let e = _mm512_set1_pd(0.5773391723632813);
2836 assert_eq_m512d(r, e);
2837 }
2838
2839 #[simd_test(enable = "avx512f")]
2840 unsafe fn test_mm512_mask_rsqrt14_pd() {
2841 let a = _mm512_set1_pd(3.);
2842 let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2843 assert_eq_m512d(r, a);
2844 let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2845 #[rustfmt::skip]
2846 let e = _mm512_setr_pd(
2847 3., 3., 3., 3.,
2848 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2849 );
2850 assert_eq_m512d(r, e);
2851 }
2852
2853 #[simd_test(enable = "avx512f")]
2854 unsafe fn test_mm512_maskz_rsqrt14_pd() {
2855 let a = _mm512_set1_pd(3.);
2856 let r = _mm512_maskz_rsqrt14_pd(0, a);
2857 assert_eq_m512d(r, _mm512_setzero_pd());
2858 let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2859 #[rustfmt::skip]
2860 let e = _mm512_setr_pd(
2861 0., 0., 0., 0.,
2862 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2863 );
2864 assert_eq_m512d(r, e);
2865 }
2866
2867 #[simd_test(enable = "avx512f,avx512vl")]
2868 unsafe fn test_mm256_rsqrt14_pd() {
2869 let a = _mm256_set1_pd(3.);
2870 let r = _mm256_rsqrt14_pd(a);
2871 let e = _mm256_set1_pd(0.5773391723632813);
2872 assert_eq_m256d(r, e);
2873 }
2874
2875 #[simd_test(enable = "avx512f,avx512vl")]
2876 unsafe fn test_mm256_mask_rsqrt14_pd() {
2877 let a = _mm256_set1_pd(3.);
2878 let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2879 assert_eq_m256d(r, a);
2880 let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2881 let e = _mm256_set1_pd(0.5773391723632813);
2882 assert_eq_m256d(r, e);
2883 }
2884
2885 #[simd_test(enable = "avx512f,avx512vl")]
2886 unsafe fn test_mm256_maskz_rsqrt14_pd() {
2887 let a = _mm256_set1_pd(3.);
2888 let r = _mm256_maskz_rsqrt14_pd(0, a);
2889 assert_eq_m256d(r, _mm256_setzero_pd());
2890 let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2891 let e = _mm256_set1_pd(0.5773391723632813);
2892 assert_eq_m256d(r, e);
2893 }
2894
2895 #[simd_test(enable = "avx512f,avx512vl")]
2896 unsafe fn test_mm_rsqrt14_pd() {
2897 let a = _mm_set1_pd(3.);
2898 let r = _mm_rsqrt14_pd(a);
2899 let e = _mm_set1_pd(0.5773391723632813);
2900 assert_eq_m128d(r, e);
2901 }
2902
2903 #[simd_test(enable = "avx512f,avx512vl")]
2904 unsafe fn test_mm_mask_rsqrt14_pd() {
2905 let a = _mm_set1_pd(3.);
2906 let r = _mm_mask_rsqrt14_pd(a, 0, a);
2907 assert_eq_m128d(r, a);
2908 let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2909 let e = _mm_set1_pd(0.5773391723632813);
2910 assert_eq_m128d(r, e);
2911 }
2912
2913 #[simd_test(enable = "avx512f,avx512vl")]
2914 unsafe fn test_mm_maskz_rsqrt14_pd() {
2915 let a = _mm_set1_pd(3.);
2916 let r = _mm_maskz_rsqrt14_pd(0, a);
2917 assert_eq_m128d(r, _mm_setzero_pd());
2918 let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2919 let e = _mm_set1_pd(0.5773391723632813);
2920 assert_eq_m128d(r, e);
2921 }
2922
2923 #[simd_test(enable = "avx512f")]
2924 unsafe fn test_mm512_getexp_pd() {
2925 let a = _mm512_set1_pd(3.);
2926 let r = _mm512_getexp_pd(a);
2927 let e = _mm512_set1_pd(1.);
2928 assert_eq_m512d(r, e);
2929 }
2930
2931 #[simd_test(enable = "avx512f")]
2932 unsafe fn test_mm512_mask_getexp_pd() {
2933 let a = _mm512_set1_pd(3.);
2934 let r = _mm512_mask_getexp_pd(a, 0, a);
2935 assert_eq_m512d(r, a);
2936 let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2937 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2938 assert_eq_m512d(r, e);
2939 }
2940
2941 #[simd_test(enable = "avx512f")]
2942 unsafe fn test_mm512_maskz_getexp_pd() {
2943 let a = _mm512_set1_pd(3.);
2944 let r = _mm512_maskz_getexp_pd(0, a);
2945 assert_eq_m512d(r, _mm512_setzero_pd());
2946 let r = _mm512_maskz_getexp_pd(0b11110000, a);
2947 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2948 assert_eq_m512d(r, e);
2949 }
2950
2951 #[simd_test(enable = "avx512f,avx512vl")]
2952 unsafe fn test_mm256_getexp_pd() {
2953 let a = _mm256_set1_pd(3.);
2954 let r = _mm256_getexp_pd(a);
2955 let e = _mm256_set1_pd(1.);
2956 assert_eq_m256d(r, e);
2957 }
2958
2959 #[simd_test(enable = "avx512f,avx512vl")]
2960 unsafe fn test_mm256_mask_getexp_pd() {
2961 let a = _mm256_set1_pd(3.);
2962 let r = _mm256_mask_getexp_pd(a, 0, a);
2963 assert_eq_m256d(r, a);
2964 let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2965 let e = _mm256_set1_pd(1.);
2966 assert_eq_m256d(r, e);
2967 }
2968
2969 #[simd_test(enable = "avx512f,avx512vl")]
2970 unsafe fn test_mm256_maskz_getexp_pd() {
2971 let a = _mm256_set1_pd(3.);
2972 let r = _mm256_maskz_getexp_pd(0, a);
2973 assert_eq_m256d(r, _mm256_setzero_pd());
2974 let r = _mm256_maskz_getexp_pd(0b00001111, a);
2975 let e = _mm256_set1_pd(1.);
2976 assert_eq_m256d(r, e);
2977 }
2978
2979 #[simd_test(enable = "avx512f,avx512vl")]
2980 unsafe fn test_mm_getexp_pd() {
2981 let a = _mm_set1_pd(3.);
2982 let r = _mm_getexp_pd(a);
2983 let e = _mm_set1_pd(1.);
2984 assert_eq_m128d(r, e);
2985 }
2986
2987 #[simd_test(enable = "avx512f,avx512vl")]
2988 unsafe fn test_mm_mask_getexp_pd() {
2989 let a = _mm_set1_pd(3.);
2990 let r = _mm_mask_getexp_pd(a, 0, a);
2991 assert_eq_m128d(r, a);
2992 let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2993 let e = _mm_set1_pd(1.);
2994 assert_eq_m128d(r, e);
2995 }
2996
2997 #[simd_test(enable = "avx512f,avx512vl")]
2998 unsafe fn test_mm_maskz_getexp_pd() {
2999 let a = _mm_set1_pd(3.);
3000 let r = _mm_maskz_getexp_pd(0, a);
3001 assert_eq_m128d(r, _mm_setzero_pd());
3002 let r = _mm_maskz_getexp_pd(0b00000011, a);
3003 let e = _mm_set1_pd(1.);
3004 assert_eq_m128d(r, e);
3005 }
3006
3007 #[simd_test(enable = "avx512f")]
3008 unsafe fn test_mm512_roundscale_pd() {
3009 let a = _mm512_set1_pd(1.1);
3010 let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
3011 let e = _mm512_set1_pd(1.0);
3012 assert_eq_m512d(r, e);
3013 }
3014
3015 #[simd_test(enable = "avx512f")]
3016 unsafe fn test_mm512_mask_roundscale_pd() {
3017 let a = _mm512_set1_pd(1.1);
3018 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3019 let e = _mm512_set1_pd(1.1);
3020 assert_eq_m512d(r, e);
3021 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
3022 let e = _mm512_set1_pd(1.0);
3023 assert_eq_m512d(r, e);
3024 }
3025
3026 #[simd_test(enable = "avx512f")]
3027 unsafe fn test_mm512_maskz_roundscale_pd() {
3028 let a = _mm512_set1_pd(1.1);
3029 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3030 assert_eq_m512d(r, _mm512_setzero_pd());
3031 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
3032 let e = _mm512_set1_pd(1.0);
3033 assert_eq_m512d(r, e);
3034 }
3035
3036 #[simd_test(enable = "avx512f,avx512vl")]
3037 unsafe fn test_mm256_roundscale_pd() {
3038 let a = _mm256_set1_pd(1.1);
3039 let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
3040 let e = _mm256_set1_pd(1.0);
3041 assert_eq_m256d(r, e);
3042 }
3043
3044 #[simd_test(enable = "avx512f,avx512vl")]
3045 unsafe fn test_mm256_mask_roundscale_pd() {
3046 let a = _mm256_set1_pd(1.1);
3047 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3048 assert_eq_m256d(r, a);
3049 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
3050 let e = _mm256_set1_pd(1.0);
3051 assert_eq_m256d(r, e);
3052 }
3053
3054 #[simd_test(enable = "avx512f,avx512vl")]
3055 unsafe fn test_mm256_maskz_roundscale_pd() {
3056 let a = _mm256_set1_pd(1.1);
3057 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3058 assert_eq_m256d(r, _mm256_setzero_pd());
3059 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
3060 let e = _mm256_set1_pd(1.0);
3061 assert_eq_m256d(r, e);
3062 }
3063
3064 #[simd_test(enable = "avx512f,avx512vl")]
3065 unsafe fn test_mm_roundscale_pd() {
3066 let a = _mm_set1_pd(1.1);
3067 let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
3068 let e = _mm_set1_pd(1.0);
3069 assert_eq_m128d(r, e);
3070 }
3071
3072 #[simd_test(enable = "avx512f,avx512vl")]
3073 unsafe fn test_mm_mask_roundscale_pd() {
3074 let a = _mm_set1_pd(1.1);
3075 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3076 let e = _mm_set1_pd(1.1);
3077 assert_eq_m128d(r, e);
3078 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
3079 let e = _mm_set1_pd(1.0);
3080 assert_eq_m128d(r, e);
3081 }
3082
3083 #[simd_test(enable = "avx512f,avx512vl")]
3084 unsafe fn test_mm_maskz_roundscale_pd() {
3085 let a = _mm_set1_pd(1.1);
3086 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3087 assert_eq_m128d(r, _mm_setzero_pd());
3088 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
3089 let e = _mm_set1_pd(1.0);
3090 assert_eq_m128d(r, e);
3091 }
3092
3093 #[simd_test(enable = "avx512f")]
3094 unsafe fn test_mm512_scalef_pd() {
3095 let a = _mm512_set1_pd(1.);
3096 let b = _mm512_set1_pd(3.);
3097 let r = _mm512_scalef_pd(a, b);
3098 let e = _mm512_set1_pd(8.);
3099 assert_eq_m512d(r, e);
3100 }
3101
3102 #[simd_test(enable = "avx512f")]
3103 unsafe fn test_mm512_mask_scalef_pd() {
3104 let a = _mm512_set1_pd(1.);
3105 let b = _mm512_set1_pd(3.);
3106 let r = _mm512_mask_scalef_pd(a, 0, a, b);
3107 assert_eq_m512d(r, a);
3108 let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
3109 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
3110 assert_eq_m512d(r, e);
3111 }
3112
3113 #[simd_test(enable = "avx512f")]
3114 unsafe fn test_mm512_maskz_scalef_pd() {
3115 let a = _mm512_set1_pd(1.);
3116 let b = _mm512_set1_pd(3.);
3117 let r = _mm512_maskz_scalef_pd(0, a, b);
3118 assert_eq_m512d(r, _mm512_setzero_pd());
3119 let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
3120 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
3121 assert_eq_m512d(r, e);
3122 }
3123
3124 #[simd_test(enable = "avx512f,avx512vl")]
3125 unsafe fn test_mm256_scalef_pd() {
3126 let a = _mm256_set1_pd(1.);
3127 let b = _mm256_set1_pd(3.);
3128 let r = _mm256_scalef_pd(a, b);
3129 let e = _mm256_set1_pd(8.);
3130 assert_eq_m256d(r, e);
3131 }
3132
3133 #[simd_test(enable = "avx512f,avx512vl")]
3134 unsafe fn test_mm256_mask_scalef_pd() {
3135 let a = _mm256_set1_pd(1.);
3136 let b = _mm256_set1_pd(3.);
3137 let r = _mm256_mask_scalef_pd(a, 0, a, b);
3138 assert_eq_m256d(r, a);
3139 let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
3140 let e = _mm256_set1_pd(8.);
3141 assert_eq_m256d(r, e);
3142 }
3143
3144 #[simd_test(enable = "avx512f,avx512vl")]
3145 unsafe fn test_mm256_maskz_scalef_pd() {
3146 let a = _mm256_set1_pd(1.);
3147 let b = _mm256_set1_pd(3.);
3148 let r = _mm256_maskz_scalef_pd(0, a, b);
3149 assert_eq_m256d(r, _mm256_setzero_pd());
3150 let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3151 let e = _mm256_set1_pd(8.);
3152 assert_eq_m256d(r, e);
3153 }
3154
3155 #[simd_test(enable = "avx512f,avx512vl")]
3156 unsafe fn test_mm_scalef_pd() {
3157 let a = _mm_set1_pd(1.);
3158 let b = _mm_set1_pd(3.);
3159 let r = _mm_scalef_pd(a, b);
3160 let e = _mm_set1_pd(8.);
3161 assert_eq_m128d(r, e);
3162 }
3163
3164 #[simd_test(enable = "avx512f,avx512vl")]
3165 unsafe fn test_mm_mask_scalef_pd() {
3166 let a = _mm_set1_pd(1.);
3167 let b = _mm_set1_pd(3.);
3168 let r = _mm_mask_scalef_pd(a, 0, a, b);
3169 assert_eq_m128d(r, a);
3170 let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3171 let e = _mm_set1_pd(8.);
3172 assert_eq_m128d(r, e);
3173 }
3174
3175 #[simd_test(enable = "avx512f,avx512vl")]
3176 unsafe fn test_mm_maskz_scalef_pd() {
3177 let a = _mm_set1_pd(1.);
3178 let b = _mm_set1_pd(3.);
3179 let r = _mm_maskz_scalef_pd(0, a, b);
3180 assert_eq_m128d(r, _mm_setzero_pd());
3181 let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3182 let e = _mm_set1_pd(8.);
3183 assert_eq_m128d(r, e);
3184 }
3185
3186 #[simd_test(enable = "avx512f")]
3187 unsafe fn test_mm512_fixupimm_pd() {
3188 let a = _mm512_set1_pd(f64::NAN);
3189 let b = _mm512_set1_pd(f64::MAX);
3190 let c = _mm512_set1_epi64(i32::MAX as i64);
3191 let r = _mm512_fixupimm_pd::<5>(a, b, c);
3192 let e = _mm512_set1_pd(0.0);
3193 assert_eq_m512d(r, e);
3194 }
3195
3196 #[simd_test(enable = "avx512f")]
3197 unsafe fn test_mm512_mask_fixupimm_pd() {
3198 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3199 let b = _mm512_set1_pd(f64::MAX);
3200 let c = _mm512_set1_epi64(i32::MAX as i64);
3201 let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3202 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3203 assert_eq_m512d(r, e);
3204 }
3205
3206 #[simd_test(enable = "avx512f")]
3207 unsafe fn test_mm512_maskz_fixupimm_pd() {
3208 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3209 let b = _mm512_set1_pd(f64::MAX);
3210 let c = _mm512_set1_epi64(i32::MAX as i64);
3211 let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3212 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3213 assert_eq_m512d(r, e);
3214 }
3215
3216 #[simd_test(enable = "avx512f,avx512vl")]
3217 unsafe fn test_mm256_fixupimm_pd() {
3218 let a = _mm256_set1_pd(f64::NAN);
3219 let b = _mm256_set1_pd(f64::MAX);
3220 let c = _mm256_set1_epi64x(i32::MAX as i64);
3221 let r = _mm256_fixupimm_pd::<5>(a, b, c);
3222 let e = _mm256_set1_pd(0.0);
3223 assert_eq_m256d(r, e);
3224 }
3225
3226 #[simd_test(enable = "avx512f,avx512vl")]
3227 unsafe fn test_mm256_mask_fixupimm_pd() {
3228 let a = _mm256_set1_pd(f64::NAN);
3229 let b = _mm256_set1_pd(f64::MAX);
3230 let c = _mm256_set1_epi64x(i32::MAX as i64);
3231 let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3232 let e = _mm256_set1_pd(0.0);
3233 assert_eq_m256d(r, e);
3234 }
3235
3236 #[simd_test(enable = "avx512f,avx512vl")]
3237 unsafe fn test_mm256_maskz_fixupimm_pd() {
3238 let a = _mm256_set1_pd(f64::NAN);
3239 let b = _mm256_set1_pd(f64::MAX);
3240 let c = _mm256_set1_epi64x(i32::MAX as i64);
3241 let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3242 let e = _mm256_set1_pd(0.0);
3243 assert_eq_m256d(r, e);
3244 }
3245
3246 #[simd_test(enable = "avx512f,avx512vl")]
3247 unsafe fn test_mm_fixupimm_pd() {
3248 let a = _mm_set1_pd(f64::NAN);
3249 let b = _mm_set1_pd(f64::MAX);
3250 let c = _mm_set1_epi64x(i32::MAX as i64);
3251 let r = _mm_fixupimm_pd::<5>(a, b, c);
3252 let e = _mm_set1_pd(0.0);
3253 assert_eq_m128d(r, e);
3254 }
3255
3256 #[simd_test(enable = "avx512f,avx512vl")]
3257 unsafe fn test_mm_mask_fixupimm_pd() {
3258 let a = _mm_set1_pd(f64::NAN);
3259 let b = _mm_set1_pd(f64::MAX);
3260 let c = _mm_set1_epi64x(i32::MAX as i64);
3261 let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3262 let e = _mm_set1_pd(0.0);
3263 assert_eq_m128d(r, e);
3264 }
3265
3266 #[simd_test(enable = "avx512f,avx512vl")]
3267 unsafe fn test_mm_maskz_fixupimm_pd() {
3268 let a = _mm_set1_pd(f64::NAN);
3269 let b = _mm_set1_pd(f64::MAX);
3270 let c = _mm_set1_epi64x(i32::MAX as i64);
3271 let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3272 let e = _mm_set1_pd(0.0);
3273 assert_eq_m128d(r, e);
3274 }
3275
3276 #[simd_test(enable = "avx512f")]
3277 unsafe fn test_mm512_ternarylogic_epi64() {
3278 let a = _mm512_set1_epi64(1 << 2);
3279 let b = _mm512_set1_epi64(1 << 1);
3280 let c = _mm512_set1_epi64(1 << 0);
3281 let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3282 let e = _mm512_set1_epi64(0);
3283 assert_eq_m512i(r, e);
3284 }
3285
3286 #[simd_test(enable = "avx512f")]
3287 unsafe fn test_mm512_mask_ternarylogic_epi64() {
3288 let src = _mm512_set1_epi64(1 << 2);
3289 let a = _mm512_set1_epi64(1 << 1);
3290 let b = _mm512_set1_epi64(1 << 0);
3291 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3292 assert_eq_m512i(r, src);
3293 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3294 let e = _mm512_set1_epi64(0);
3295 assert_eq_m512i(r, e);
3296 }
3297
3298 #[simd_test(enable = "avx512f")]
3299 unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3300 let a = _mm512_set1_epi64(1 << 2);
3301 let b = _mm512_set1_epi64(1 << 1);
3302 let c = _mm512_set1_epi64(1 << 0);
3303 let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3304 assert_eq_m512i(r, _mm512_setzero_si512());
3305 let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3306 let e = _mm512_set1_epi64(0);
3307 assert_eq_m512i(r, e);
3308 }
3309
3310 #[simd_test(enable = "avx512f,avx512vl")]
3311 unsafe fn test_mm256_ternarylogic_epi64() {
3312 let a = _mm256_set1_epi64x(1 << 2);
3313 let b = _mm256_set1_epi64x(1 << 1);
3314 let c = _mm256_set1_epi64x(1 << 0);
3315 let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3316 let e = _mm256_set1_epi64x(0);
3317 assert_eq_m256i(r, e);
3318 }
3319
3320 #[simd_test(enable = "avx512f,avx512vl")]
3321 unsafe fn test_mm256_mask_ternarylogic_epi64() {
3322 let src = _mm256_set1_epi64x(1 << 2);
3323 let a = _mm256_set1_epi64x(1 << 1);
3324 let b = _mm256_set1_epi64x(1 << 0);
3325 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3326 assert_eq_m256i(r, src);
3327 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3328 let e = _mm256_set1_epi64x(0);
3329 assert_eq_m256i(r, e);
3330 }
3331
3332 #[simd_test(enable = "avx512f,avx512vl")]
3333 unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3334 let a = _mm256_set1_epi64x(1 << 2);
3335 let b = _mm256_set1_epi64x(1 << 1);
3336 let c = _mm256_set1_epi64x(1 << 0);
3337 let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3338 assert_eq_m256i(r, _mm256_setzero_si256());
3339 let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3340 let e = _mm256_set1_epi64x(0);
3341 assert_eq_m256i(r, e);
3342 }
3343
3344 #[simd_test(enable = "avx512f,avx512vl")]
3345 unsafe fn test_mm_ternarylogic_epi64() {
3346 let a = _mm_set1_epi64x(1 << 2);
3347 let b = _mm_set1_epi64x(1 << 1);
3348 let c = _mm_set1_epi64x(1 << 0);
3349 let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3350 let e = _mm_set1_epi64x(0);
3351 assert_eq_m128i(r, e);
3352 }
3353
3354 #[simd_test(enable = "avx512f,avx512vl")]
3355 unsafe fn test_mm_mask_ternarylogic_epi64() {
3356 let src = _mm_set1_epi64x(1 << 2);
3357 let a = _mm_set1_epi64x(1 << 1);
3358 let b = _mm_set1_epi64x(1 << 0);
3359 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3360 assert_eq_m128i(r, src);
3361 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3362 let e = _mm_set1_epi64x(0);
3363 assert_eq_m128i(r, e);
3364 }
3365
3366 #[simd_test(enable = "avx512f,avx512vl")]
3367 unsafe fn test_mm_maskz_ternarylogic_epi64() {
3368 let a = _mm_set1_epi64x(1 << 2);
3369 let b = _mm_set1_epi64x(1 << 1);
3370 let c = _mm_set1_epi64x(1 << 0);
3371 let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3372 assert_eq_m128i(r, _mm_setzero_si128());
3373 let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3374 let e = _mm_set1_epi64x(0);
3375 assert_eq_m128i(r, e);
3376 }
3377
3378 #[simd_test(enable = "avx512f")]
3379 unsafe fn test_mm512_getmant_pd() {
3380 let a = _mm512_set1_pd(10.);
3381 let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3382 let e = _mm512_set1_pd(1.25);
3383 assert_eq_m512d(r, e);
3384 }
3385
3386 #[simd_test(enable = "avx512f")]
3387 unsafe fn test_mm512_mask_getmant_pd() {
3388 let a = _mm512_set1_pd(10.);
3389 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3390 assert_eq_m512d(r, a);
3391 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3392 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3393 assert_eq_m512d(r, e);
3394 }
3395
3396 #[simd_test(enable = "avx512f")]
3397 unsafe fn test_mm512_maskz_getmant_pd() {
3398 let a = _mm512_set1_pd(10.);
3399 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3400 assert_eq_m512d(r, _mm512_setzero_pd());
3401 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3402 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3403 assert_eq_m512d(r, e);
3404 }
3405
3406 #[simd_test(enable = "avx512f,avx512vl")]
3407 unsafe fn test_mm256_getmant_pd() {
3408 let a = _mm256_set1_pd(10.);
3409 let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3410 let e = _mm256_set1_pd(1.25);
3411 assert_eq_m256d(r, e);
3412 }
3413
3414 #[simd_test(enable = "avx512f,avx512vl")]
3415 unsafe fn test_mm256_mask_getmant_pd() {
3416 let a = _mm256_set1_pd(10.);
3417 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3418 assert_eq_m256d(r, a);
3419 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3420 let e = _mm256_set1_pd(1.25);
3421 assert_eq_m256d(r, e);
3422 }
3423
3424 #[simd_test(enable = "avx512f,avx512vl")]
3425 unsafe fn test_mm256_maskz_getmant_pd() {
3426 let a = _mm256_set1_pd(10.);
3427 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3428 assert_eq_m256d(r, _mm256_setzero_pd());
3429 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3430 let e = _mm256_set1_pd(1.25);
3431 assert_eq_m256d(r, e);
3432 }
3433
3434 #[simd_test(enable = "avx512f,avx512vl")]
3435 unsafe fn test_mm_getmant_pd() {
3436 let a = _mm_set1_pd(10.);
3437 let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3438 let e = _mm_set1_pd(1.25);
3439 assert_eq_m128d(r, e);
3440 }
3441
3442 #[simd_test(enable = "avx512f,avx512vl")]
3443 unsafe fn test_mm_mask_getmant_pd() {
3444 let a = _mm_set1_pd(10.);
3445 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3446 assert_eq_m128d(r, a);
3447 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3448 let e = _mm_set1_pd(1.25);
3449 assert_eq_m128d(r, e);
3450 }
3451
3452 #[simd_test(enable = "avx512f,avx512vl")]
3453 unsafe fn test_mm_maskz_getmant_pd() {
3454 let a = _mm_set1_pd(10.);
3455 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3456 assert_eq_m128d(r, _mm_setzero_pd());
3457 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3458 let e = _mm_set1_pd(1.25);
3459 assert_eq_m128d(r, e);
3460 }
3461
3462 #[simd_test(enable = "avx512f")]
3463 unsafe fn test_mm512_cvtps_pd() {
3464 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3465 let r = _mm512_cvtps_pd(a);
3466 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3467 assert_eq_m512d(r, e);
3468 }
3469
3470 #[simd_test(enable = "avx512f")]
3471 unsafe fn test_mm512_mask_cvtps_pd() {
3472 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3473 let src = _mm512_set1_pd(0.);
3474 let r = _mm512_mask_cvtps_pd(src, 0, a);
3475 assert_eq_m512d(r, src);
3476 let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3477 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3478 assert_eq_m512d(r, e);
3479 }
3480
3481 #[simd_test(enable = "avx512f")]
3482 unsafe fn test_mm512_maskz_cvtps_pd() {
3483 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3484 let r = _mm512_maskz_cvtps_pd(0, a);
3485 assert_eq_m512d(r, _mm512_setzero_pd());
3486 let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3487 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3488 assert_eq_m512d(r, e);
3489 }
3490
3491 #[simd_test(enable = "avx512f")]
3492 unsafe fn test_mm512_cvtpslo_pd() {
3493 let v2 = _mm512_setr_ps(
3494 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3495 );
3496 let r = _mm512_cvtpslo_pd(v2);
3497 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3498 assert_eq_m512d(r, e);
3499 }
3500
3501 #[simd_test(enable = "avx512f")]
3502 unsafe fn test_mm512_mask_cvtpslo_pd() {
3503 let v2 = _mm512_setr_ps(
3504 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3505 );
3506 let src = _mm512_set1_pd(0.);
3507 let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3508 assert_eq_m512d(r, src);
3509 let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3510 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3511 assert_eq_m512d(r, e);
3512 }
3513
3514 #[simd_test(enable = "avx512f")]
3515 unsafe fn test_mm512_cvtpd_ps() {
3516 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3517 let r = _mm512_cvtpd_ps(a);
3518 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3519 assert_eq_m256(r, e);
3520 }
3521
3522 #[simd_test(enable = "avx512f")]
3523 unsafe fn test_mm512_mask_cvtpd_ps() {
3524 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3525 let src = _mm256_set1_ps(0.);
3526 let r = _mm512_mask_cvtpd_ps(src, 0, a);
3527 assert_eq_m256(r, src);
3528 let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3529 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3530 assert_eq_m256(r, e);
3531 }
3532
3533 #[simd_test(enable = "avx512f")]
3534 unsafe fn test_mm512_maskz_cvtpd_ps() {
3535 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3536 let r = _mm512_maskz_cvtpd_ps(0, a);
3537 assert_eq_m256(r, _mm256_setzero_ps());
3538 let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3539 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3540 assert_eq_m256(r, e);
3541 }
3542
3543 #[simd_test(enable = "avx512f,avx512vl")]
3544 unsafe fn test_mm256_mask_cvtpd_ps() {
3545 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3546 let src = _mm_set1_ps(0.);
3547 let r = _mm256_mask_cvtpd_ps(src, 0, a);
3548 assert_eq_m128(r, src);
3549 let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3550 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3551 assert_eq_m128(r, e);
3552 }
3553
3554 #[simd_test(enable = "avx512f,avx512vl")]
3555 unsafe fn test_mm256_maskz_cvtpd_ps() {
3556 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3557 let r = _mm256_maskz_cvtpd_ps(0, a);
3558 assert_eq_m128(r, _mm_setzero_ps());
3559 let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3560 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3561 assert_eq_m128(r, e);
3562 }
3563
3564 #[simd_test(enable = "avx512f,avx512vl")]
3565 unsafe fn test_mm_mask_cvtpd_ps() {
3566 let a = _mm_set_pd(6., -7.5);
3567 let src = _mm_set1_ps(0.);
3568 let r = _mm_mask_cvtpd_ps(src, 0, a);
3569 assert_eq_m128(r, src);
3570 let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3571 let e = _mm_set_ps(0., 0., 6., -7.5);
3572 assert_eq_m128(r, e);
3573 }
3574
3575 #[simd_test(enable = "avx512f,avx512vl")]
3576 unsafe fn test_mm_maskz_cvtpd_ps() {
3577 let a = _mm_set_pd(6., -7.5);
3578 let r = _mm_maskz_cvtpd_ps(0, a);
3579 assert_eq_m128(r, _mm_setzero_ps());
3580 let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3581 let e = _mm_set_ps(0., 0., 6., -7.5);
3582 assert_eq_m128(r, e);
3583 }
3584
3585 #[simd_test(enable = "avx512f")]
3586 unsafe fn test_mm512_cvtpd_epi32() {
3587 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3588 let r = _mm512_cvtpd_epi32(a);
3589 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3590 assert_eq_m256i(r, e);
3591 }
3592
3593 #[simd_test(enable = "avx512f")]
3594 unsafe fn test_mm512_mask_cvtpd_epi32() {
3595 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3596 let src = _mm256_set1_epi32(0);
3597 let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3598 assert_eq_m256i(r, src);
3599 let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3600 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3601 assert_eq_m256i(r, e);
3602 }
3603
3604 #[simd_test(enable = "avx512f")]
3605 unsafe fn test_mm512_maskz_cvtpd_epi32() {
3606 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3607 let r = _mm512_maskz_cvtpd_epi32(0, a);
3608 assert_eq_m256i(r, _mm256_setzero_si256());
3609 let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3610 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3611 assert_eq_m256i(r, e);
3612 }
3613
3614 #[simd_test(enable = "avx512f,avx512vl")]
3615 unsafe fn test_mm256_mask_cvtpd_epi32() {
3616 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3617 let src = _mm_set1_epi32(0);
3618 let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3619 assert_eq_m128i(r, src);
3620 let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3621 let e = _mm_set_epi32(4, -6, 6, -8);
3622 assert_eq_m128i(r, e);
3623 }
3624
3625 #[simd_test(enable = "avx512f,avx512vl")]
3626 unsafe fn test_mm256_maskz_cvtpd_epi32() {
3627 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3628 let r = _mm256_maskz_cvtpd_epi32(0, a);
3629 assert_eq_m128i(r, _mm_setzero_si128());
3630 let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3631 let e = _mm_set_epi32(4, -6, 6, -8);
3632 assert_eq_m128i(r, e);
3633 }
3634
3635 #[simd_test(enable = "avx512f,avx512vl")]
3636 unsafe fn test_mm_mask_cvtpd_epi32() {
3637 let a = _mm_set_pd(6., -7.5);
3638 let src = _mm_set1_epi32(0);
3639 let r = _mm_mask_cvtpd_epi32(src, 0, a);
3640 assert_eq_m128i(r, src);
3641 let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3642 let e = _mm_set_epi32(0, 0, 6, -8);
3643 assert_eq_m128i(r, e);
3644 }
3645
3646 #[simd_test(enable = "avx512f,avx512vl")]
3647 unsafe fn test_mm_maskz_cvtpd_epi32() {
3648 let a = _mm_set_pd(6., -7.5);
3649 let r = _mm_maskz_cvtpd_epi32(0, a);
3650 assert_eq_m128i(r, _mm_setzero_si128());
3651 let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3652 let e = _mm_set_epi32(0, 0, 6, -8);
3653 assert_eq_m128i(r, e);
3654 }
3655
3656 #[simd_test(enable = "avx512f")]
3657 unsafe fn test_mm512_cvtpd_epu32() {
3658 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3659 let r = _mm512_cvtpd_epu32(a);
3660 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3661 assert_eq_m256i(r, e);
3662 }
3663
3664 #[simd_test(enable = "avx512f")]
3665 unsafe fn test_mm512_mask_cvtpd_epu32() {
3666 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3667 let src = _mm256_set1_epi32(0);
3668 let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3669 assert_eq_m256i(r, src);
3670 let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3671 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3672 assert_eq_m256i(r, e);
3673 }
3674
3675 #[simd_test(enable = "avx512f")]
3676 unsafe fn test_mm512_maskz_cvtpd_epu32() {
3677 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3678 let r = _mm512_maskz_cvtpd_epu32(0, a);
3679 assert_eq_m256i(r, _mm256_setzero_si256());
3680 let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3681 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3682 assert_eq_m256i(r, e);
3683 }
3684
3685 #[simd_test(enable = "avx512f,avx512vl")]
3686 unsafe fn test_mm256_cvtpd_epu32() {
3687 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3688 let r = _mm256_cvtpd_epu32(a);
3689 let e = _mm_set_epi32(4, 6, 6, 8);
3690 assert_eq_m128i(r, e);
3691 }
3692
3693 #[simd_test(enable = "avx512f,avx512vl")]
3694 unsafe fn test_mm256_mask_cvtpd_epu32() {
3695 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3696 let src = _mm_set1_epi32(0);
3697 let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3698 assert_eq_m128i(r, src);
3699 let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3700 let e = _mm_set_epi32(4, 6, 6, 8);
3701 assert_eq_m128i(r, e);
3702 }
3703
3704 #[simd_test(enable = "avx512f,avx512vl")]
3705 unsafe fn test_mm256_maskz_cvtpd_epu32() {
3706 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3707 let r = _mm256_maskz_cvtpd_epu32(0, a);
3708 assert_eq_m128i(r, _mm_setzero_si128());
3709 let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3710 let e = _mm_set_epi32(4, 6, 6, 8);
3711 assert_eq_m128i(r, e);
3712 }
3713
3714 #[simd_test(enable = "avx512f,avx512vl")]
3715 unsafe fn test_mm_cvtpd_epu32() {
3716 let a = _mm_set_pd(6., 7.5);
3717 let r = _mm_cvtpd_epu32(a);
3718 let e = _mm_set_epi32(0, 0, 6, 8);
3719 assert_eq_m128i(r, e);
3720 }
3721
3722 #[simd_test(enable = "avx512f,avx512vl")]
3723 unsafe fn test_mm_mask_cvtpd_epu32() {
3724 let a = _mm_set_pd(6., 7.5);
3725 let src = _mm_set1_epi32(0);
3726 let r = _mm_mask_cvtpd_epu32(src, 0, a);
3727 assert_eq_m128i(r, src);
3728 let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3729 let e = _mm_set_epi32(0, 0, 6, 8);
3730 assert_eq_m128i(r, e);
3731 }
3732
3733 #[simd_test(enable = "avx512f,avx512vl")]
3734 unsafe fn test_mm_maskz_cvtpd_epu32() {
3735 let a = _mm_set_pd(6., 7.5);
3736 let r = _mm_maskz_cvtpd_epu32(0, a);
3737 assert_eq_m128i(r, _mm_setzero_si128());
3738 let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3739 let e = _mm_set_epi32(0, 0, 6, 8);
3740 assert_eq_m128i(r, e);
3741 }
3742
3743 #[simd_test(enable = "avx512f")]
3744 unsafe fn test_mm512_cvtpd_pslo() {
3745 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3746 let r = _mm512_cvtpd_pslo(v2);
3747 let e = _mm512_setr_ps(
3748 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3749 );
3750 assert_eq_m512(r, e);
3751 }
3752
3753 #[simd_test(enable = "avx512f")]
3754 unsafe fn test_mm512_mask_cvtpd_pslo() {
3755 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3756 let src = _mm512_set1_ps(0.);
3757 let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3758 assert_eq_m512(r, src);
3759 let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3760 let e = _mm512_setr_ps(
3761 0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3762 );
3763 assert_eq_m512(r, e);
3764 }
3765
3766 #[simd_test(enable = "avx512f")]
3767 unsafe fn test_mm512_cvtepi8_epi64() {
3768 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3769 let r = _mm512_cvtepi8_epi64(a);
3770 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3771 assert_eq_m512i(r, e);
3772 }
3773
3774 #[simd_test(enable = "avx512f")]
3775 unsafe fn test_mm512_mask_cvtepi8_epi64() {
3776 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3777 let src = _mm512_set1_epi64(-1);
3778 let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3779 assert_eq_m512i(r, src);
3780 let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3781 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3782 assert_eq_m512i(r, e);
3783 }
3784
3785 #[simd_test(enable = "avx512f")]
3786 unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3787 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3788 let r = _mm512_maskz_cvtepi8_epi64(0, a);
3789 assert_eq_m512i(r, _mm512_setzero_si512());
3790 let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3791 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3792 assert_eq_m512i(r, e);
3793 }
3794
3795 #[simd_test(enable = "avx512f,avx512vl")]
3796 unsafe fn test_mm256_mask_cvtepi8_epi64() {
3797 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3798 let src = _mm256_set1_epi64x(-1);
3799 let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3800 assert_eq_m256i(r, src);
3801 let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3802 let e = _mm256_set_epi64x(12, 13, 14, 15);
3803 assert_eq_m256i(r, e);
3804 }
3805
3806 #[simd_test(enable = "avx512f,avx512vl")]
3807 unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3808 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3809 let r = _mm256_maskz_cvtepi8_epi64(0, a);
3810 assert_eq_m256i(r, _mm256_setzero_si256());
3811 let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3812 let e = _mm256_set_epi64x(12, 13, 14, 15);
3813 assert_eq_m256i(r, e);
3814 }
3815
3816 #[simd_test(enable = "avx512f,avx512vl")]
3817 unsafe fn test_mm_mask_cvtepi8_epi64() {
3818 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3819 let src = _mm_set1_epi64x(-1);
3820 let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3821 assert_eq_m128i(r, src);
3822 let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3823 let e = _mm_set_epi64x(14, 15);
3824 assert_eq_m128i(r, e);
3825 }
3826
3827 #[simd_test(enable = "avx512f,avx512vl")]
3828 unsafe fn test_mm_maskz_cvtepi8_epi64() {
3829 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3830 let r = _mm_maskz_cvtepi8_epi64(0, a);
3831 assert_eq_m128i(r, _mm_setzero_si128());
3832 let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3833 let e = _mm_set_epi64x(14, 15);
3834 assert_eq_m128i(r, e);
3835 }
3836
3837 #[simd_test(enable = "avx512f")]
3838 unsafe fn test_mm512_cvtepu8_epi64() {
3839 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3840 let r = _mm512_cvtepu8_epi64(a);
3841 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3842 assert_eq_m512i(r, e);
3843 }
3844
3845 #[simd_test(enable = "avx512f")]
3846 unsafe fn test_mm512_mask_cvtepu8_epi64() {
3847 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3848 let src = _mm512_set1_epi64(-1);
3849 let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3850 assert_eq_m512i(r, src);
3851 let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3852 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3853 assert_eq_m512i(r, e);
3854 }
3855
3856 #[simd_test(enable = "avx512f")]
3857 unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3858 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3859 let r = _mm512_maskz_cvtepu8_epi64(0, a);
3860 assert_eq_m512i(r, _mm512_setzero_si512());
3861 let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3862 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3863 assert_eq_m512i(r, e);
3864 }
3865
3866 #[simd_test(enable = "avx512f,avx512vl")]
3867 unsafe fn test_mm256_mask_cvtepu8_epi64() {
3868 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3869 let src = _mm256_set1_epi64x(-1);
3870 let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3871 assert_eq_m256i(r, src);
3872 let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3873 let e = _mm256_set_epi64x(12, 13, 14, 15);
3874 assert_eq_m256i(r, e);
3875 }
3876
3877 #[simd_test(enable = "avx512f,avx512vl")]
3878 unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3879 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3880 let r = _mm256_maskz_cvtepu8_epi64(0, a);
3881 assert_eq_m256i(r, _mm256_setzero_si256());
3882 let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3883 let e = _mm256_set_epi64x(12, 13, 14, 15);
3884 assert_eq_m256i(r, e);
3885 }
3886
3887 #[simd_test(enable = "avx512f,avx512vl")]
3888 unsafe fn test_mm_mask_cvtepu8_epi64() {
3889 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3890 let src = _mm_set1_epi64x(-1);
3891 let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3892 assert_eq_m128i(r, src);
3893 let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3894 let e = _mm_set_epi64x(14, 15);
3895 assert_eq_m128i(r, e);
3896 }
3897
3898 #[simd_test(enable = "avx512f,avx512vl")]
3899 unsafe fn test_mm_maskz_cvtepu8_epi64() {
3900 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3901 let r = _mm_maskz_cvtepu8_epi64(0, a);
3902 assert_eq_m128i(r, _mm_setzero_si128());
3903 let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3904 let e = _mm_set_epi64x(14, 15);
3905 assert_eq_m128i(r, e);
3906 }
3907
3908 #[simd_test(enable = "avx512f")]
3909 unsafe fn test_mm512_cvtepi16_epi64() {
3910 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3911 let r = _mm512_cvtepi16_epi64(a);
3912 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3913 assert_eq_m512i(r, e);
3914 }
3915
3916 #[simd_test(enable = "avx512f")]
3917 unsafe fn test_mm512_mask_cvtepi16_epi64() {
3918 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3919 let src = _mm512_set1_epi64(-1);
3920 let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3921 assert_eq_m512i(r, src);
3922 let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3923 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3924 assert_eq_m512i(r, e);
3925 }
3926
3927 #[simd_test(enable = "avx512f")]
3928 unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3929 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3930 let r = _mm512_maskz_cvtepi16_epi64(0, a);
3931 assert_eq_m512i(r, _mm512_setzero_si512());
3932 let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3933 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3934 assert_eq_m512i(r, e);
3935 }
3936
3937 #[simd_test(enable = "avx512f,avx512vl")]
3938 unsafe fn test_mm256_mask_cvtepi16_epi64() {
3939 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3940 let src = _mm256_set1_epi64x(-1);
3941 let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3942 assert_eq_m256i(r, src);
3943 let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3944 let e = _mm256_set_epi64x(12, 13, 14, 15);
3945 assert_eq_m256i(r, e);
3946 }
3947
3948 #[simd_test(enable = "avx512f,avx512vl")]
3949 unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3950 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3951 let r = _mm256_maskz_cvtepi16_epi64(0, a);
3952 assert_eq_m256i(r, _mm256_setzero_si256());
3953 let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3954 let e = _mm256_set_epi64x(12, 13, 14, 15);
3955 assert_eq_m256i(r, e);
3956 }
3957
3958 #[simd_test(enable = "avx512f,avx512vl")]
3959 unsafe fn test_mm_mask_cvtepi16_epi64() {
3960 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3961 let src = _mm_set1_epi64x(-1);
3962 let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3963 assert_eq_m128i(r, src);
3964 let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3965 let e = _mm_set_epi64x(14, 15);
3966 assert_eq_m128i(r, e);
3967 }
3968
3969 #[simd_test(enable = "avx512f,avx512vl")]
3970 unsafe fn test_mm_maskz_cvtepi16_epi64() {
3971 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3972 let r = _mm_maskz_cvtepi16_epi64(0, a);
3973 assert_eq_m128i(r, _mm_setzero_si128());
3974 let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3975 let e = _mm_set_epi64x(14, 15);
3976 assert_eq_m128i(r, e);
3977 }
3978
3979 #[simd_test(enable = "avx512f")]
3980 unsafe fn test_mm512_cvtepu16_epi64() {
3981 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3982 let r = _mm512_cvtepu16_epi64(a);
3983 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3984 assert_eq_m512i(r, e);
3985 }
3986
3987 #[simd_test(enable = "avx512f")]
3988 unsafe fn test_mm512_mask_cvtepu16_epi64() {
3989 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3990 let src = _mm512_set1_epi64(-1);
3991 let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3992 assert_eq_m512i(r, src);
3993 let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3994 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3995 assert_eq_m512i(r, e);
3996 }
3997
3998 #[simd_test(enable = "avx512f")]
3999 unsafe fn test_mm512_maskz_cvtepu16_epi64() {
4000 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4001 let r = _mm512_maskz_cvtepu16_epi64(0, a);
4002 assert_eq_m512i(r, _mm512_setzero_si512());
4003 let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
4004 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4005 assert_eq_m512i(r, e);
4006 }
4007
4008 #[simd_test(enable = "avx512f,avx512vl")]
4009 unsafe fn test_mm256_mask_cvtepu16_epi64() {
4010 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4011 let src = _mm256_set1_epi64x(-1);
4012 let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
4013 assert_eq_m256i(r, src);
4014 let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
4015 let e = _mm256_set_epi64x(12, 13, 14, 15);
4016 assert_eq_m256i(r, e);
4017 }
4018
4019 #[simd_test(enable = "avx512f,avx512vl")]
4020 unsafe fn test_mm256_maskz_cvtepu16_epi64() {
4021 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4022 let r = _mm256_maskz_cvtepu16_epi64(0, a);
4023 assert_eq_m256i(r, _mm256_setzero_si256());
4024 let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
4025 let e = _mm256_set_epi64x(12, 13, 14, 15);
4026 assert_eq_m256i(r, e);
4027 }
4028
4029 #[simd_test(enable = "avx512f,avx512vl")]
4030 unsafe fn test_mm_mask_cvtepu16_epi64() {
4031 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4032 let src = _mm_set1_epi64x(-1);
4033 let r = _mm_mask_cvtepu16_epi64(src, 0, a);
4034 assert_eq_m128i(r, src);
4035 let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
4036 let e = _mm_set_epi64x(14, 15);
4037 assert_eq_m128i(r, e);
4038 }
4039
4040 #[simd_test(enable = "avx512f,avx512vl")]
4041 unsafe fn test_mm_maskz_cvtepu16_epi64() {
4042 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4043 let r = _mm_maskz_cvtepu16_epi64(0, a);
4044 assert_eq_m128i(r, _mm_setzero_si128());
4045 let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
4046 let e = _mm_set_epi64x(14, 15);
4047 assert_eq_m128i(r, e);
4048 }
4049
4050 #[simd_test(enable = "avx512f")]
4051 unsafe fn test_mm512_cvtepi32_epi64() {
4052 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4053 let r = _mm512_cvtepi32_epi64(a);
4054 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4055 assert_eq_m512i(r, e);
4056 }
4057
4058 #[simd_test(enable = "avx512f")]
4059 unsafe fn test_mm512_mask_cvtepi32_epi64() {
4060 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4061 let src = _mm512_set1_epi64(-1);
4062 let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
4063 assert_eq_m512i(r, src);
4064 let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
4065 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4066 assert_eq_m512i(r, e);
4067 }
4068
4069 #[simd_test(enable = "avx512f")]
4070 unsafe fn test_mm512_maskz_cvtepi32_epi64() {
4071 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4072 let r = _mm512_maskz_cvtepi32_epi64(0, a);
4073 assert_eq_m512i(r, _mm512_setzero_si512());
4074 let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
4075 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4076 assert_eq_m512i(r, e);
4077 }
4078
4079 #[simd_test(enable = "avx512f,avx512vl")]
4080 unsafe fn test_mm256_mask_cvtepi32_epi64() {
4081 let a = _mm_set_epi32(8, 9, 10, 11);
4082 let src = _mm256_set1_epi64x(-1);
4083 let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
4084 assert_eq_m256i(r, src);
4085 let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
4086 let e = _mm256_set_epi64x(8, 9, 10, 11);
4087 assert_eq_m256i(r, e);
4088 }
4089
4090 #[simd_test(enable = "avx512f,avx512vl")]
4091 unsafe fn test_mm256_maskz_cvtepi32_epi64() {
4092 let a = _mm_set_epi32(8, 9, 10, 11);
4093 let r = _mm256_maskz_cvtepi32_epi64(0, a);
4094 assert_eq_m256i(r, _mm256_setzero_si256());
4095 let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
4096 let e = _mm256_set_epi64x(8, 9, 10, 11);
4097 assert_eq_m256i(r, e);
4098 }
4099
4100 #[simd_test(enable = "avx512f,avx512vl")]
4101 unsafe fn test_mm_mask_cvtepi32_epi64() {
4102 let a = _mm_set_epi32(8, 9, 10, 11);
4103 let src = _mm_set1_epi64x(0);
4104 let r = _mm_mask_cvtepi32_epi64(src, 0, a);
4105 assert_eq_m128i(r, src);
4106 let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
4107 let e = _mm_set_epi64x(10, 11);
4108 assert_eq_m128i(r, e);
4109 }
4110
4111 #[simd_test(enable = "avx512f,avx512vl")]
4112 unsafe fn test_mm_maskz_cvtepi32_epi64() {
4113 let a = _mm_set_epi32(8, 9, 10, 11);
4114 let r = _mm_maskz_cvtepi32_epi64(0, a);
4115 assert_eq_m128i(r, _mm_setzero_si128());
4116 let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
4117 let e = _mm_set_epi64x(10, 11);
4118 assert_eq_m128i(r, e);
4119 }
4120
4121 #[simd_test(enable = "avx512f")]
4122 unsafe fn test_mm512_cvtepu32_epi64() {
4123 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4124 let r = _mm512_cvtepu32_epi64(a);
4125 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4126 assert_eq_m512i(r, e);
4127 }
4128
4129 #[simd_test(enable = "avx512f")]
4130 unsafe fn test_mm512_mask_cvtepu32_epi64() {
4131 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4132 let src = _mm512_set1_epi64(-1);
4133 let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
4134 assert_eq_m512i(r, src);
4135 let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
4136 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4137 assert_eq_m512i(r, e);
4138 }
4139
4140 #[simd_test(enable = "avx512f")]
4141 unsafe fn test_mm512_maskz_cvtepu32_epi64() {
4142 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4143 let r = _mm512_maskz_cvtepu32_epi64(0, a);
4144 assert_eq_m512i(r, _mm512_setzero_si512());
4145 let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4146 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4147 assert_eq_m512i(r, e);
4148 }
4149
4150 #[simd_test(enable = "avx512f,avx512vl")]
4151 unsafe fn test_mm256_mask_cvtepu32_epi64() {
4152 let a = _mm_set_epi32(12, 13, 14, 15);
4153 let src = _mm256_set1_epi64x(-1);
4154 let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4155 assert_eq_m256i(r, src);
4156 let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4157 let e = _mm256_set_epi64x(12, 13, 14, 15);
4158 assert_eq_m256i(r, e);
4159 }
4160
4161 #[simd_test(enable = "avx512f,avx512vl")]
4162 unsafe fn test_mm256_maskz_cvtepu32_epi64() {
4163 let a = _mm_set_epi32(12, 13, 14, 15);
4164 let r = _mm256_maskz_cvtepu32_epi64(0, a);
4165 assert_eq_m256i(r, _mm256_setzero_si256());
4166 let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4167 let e = _mm256_set_epi64x(12, 13, 14, 15);
4168 assert_eq_m256i(r, e);
4169 }
4170
4171 #[simd_test(enable = "avx512f,avx512vl")]
4172 unsafe fn test_mm_mask_cvtepu32_epi64() {
4173 let a = _mm_set_epi32(12, 13, 14, 15);
4174 let src = _mm_set1_epi64x(-1);
4175 let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4176 assert_eq_m128i(r, src);
4177 let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4178 let e = _mm_set_epi64x(14, 15);
4179 assert_eq_m128i(r, e);
4180 }
4181
4182 #[simd_test(enable = "avx512f,avx512vl")]
4183 unsafe fn test_mm_maskz_cvtepu32_epi64() {
4184 let a = _mm_set_epi32(12, 13, 14, 15);
4185 let r = _mm_maskz_cvtepu32_epi64(0, a);
4186 assert_eq_m128i(r, _mm_setzero_si128());
4187 let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4188 let e = _mm_set_epi64x(14, 15);
4189 assert_eq_m128i(r, e);
4190 }
4191
4192 #[simd_test(enable = "avx512f")]
4193 unsafe fn test_mm512_cvtepi32_pd() {
4194 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4195 let r = _mm512_cvtepi32_pd(a);
4196 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4197 assert_eq_m512d(r, e);
4198 }
4199
4200 #[simd_test(enable = "avx512f")]
4201 unsafe fn test_mm512_mask_cvtepi32_pd() {
4202 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4203 let src = _mm512_set1_pd(-1.);
4204 let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4205 assert_eq_m512d(r, src);
4206 let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4207 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4208 assert_eq_m512d(r, e);
4209 }
4210
4211 #[simd_test(enable = "avx512f")]
4212 unsafe fn test_mm512_maskz_cvtepi32_pd() {
4213 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4214 let r = _mm512_maskz_cvtepi32_pd(0, a);
4215 assert_eq_m512d(r, _mm512_setzero_pd());
4216 let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4217 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4218 assert_eq_m512d(r, e);
4219 }
4220
4221 #[simd_test(enable = "avx512f,avx512vl")]
4222 unsafe fn test_mm256_mask_cvtepi32_pd() {
4223 let a = _mm_set_epi32(12, 13, 14, 15);
4224 let src = _mm256_set1_pd(-1.);
4225 let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4226 assert_eq_m256d(r, src);
4227 let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4228 let e = _mm256_set_pd(12., 13., 14., 15.);
4229 assert_eq_m256d(r, e);
4230 }
4231
4232 #[simd_test(enable = "avx512f,avx512vl")]
4233 unsafe fn test_mm256_maskz_cvtepi32_pd() {
4234 let a = _mm_set_epi32(12, 13, 14, 15);
4235 let r = _mm256_maskz_cvtepi32_pd(0, a);
4236 assert_eq_m256d(r, _mm256_setzero_pd());
4237 let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4238 let e = _mm256_set_pd(12., 13., 14., 15.);
4239 assert_eq_m256d(r, e);
4240 }
4241
4242 #[simd_test(enable = "avx512f,avx512vl")]
4243 unsafe fn test_mm_mask_cvtepi32_pd() {
4244 let a = _mm_set_epi32(12, 13, 14, 15);
4245 let src = _mm_set1_pd(-1.);
4246 let r = _mm_mask_cvtepi32_pd(src, 0, a);
4247 assert_eq_m128d(r, src);
4248 let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4249 let e = _mm_set_pd(14., 15.);
4250 assert_eq_m128d(r, e);
4251 }
4252
4253 #[simd_test(enable = "avx512f,avx512vl")]
4254 unsafe fn test_mm_maskz_cvtepi32_pd() {
4255 let a = _mm_set_epi32(12, 13, 14, 15);
4256 let r = _mm_maskz_cvtepi32_pd(0, a);
4257 assert_eq_m128d(r, _mm_setzero_pd());
4258 let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4259 let e = _mm_set_pd(14., 15.);
4260 assert_eq_m128d(r, e);
4261 }
4262
4263 #[simd_test(enable = "avx512f")]
4264 unsafe fn test_mm512_cvtepu32_pd() {
4265 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4266 let r = _mm512_cvtepu32_pd(a);
4267 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4268 assert_eq_m512d(r, e);
4269 }
4270
4271 #[simd_test(enable = "avx512f")]
4272 unsafe fn test_mm512_mask_cvtepu32_pd() {
4273 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4274 let src = _mm512_set1_pd(-1.);
4275 let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4276 assert_eq_m512d(r, src);
4277 let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4278 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4279 assert_eq_m512d(r, e);
4280 }
4281
4282 #[simd_test(enable = "avx512f")]
4283 unsafe fn test_mm512_maskz_cvtepu32_pd() {
4284 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4285 let r = _mm512_maskz_cvtepu32_pd(0, a);
4286 assert_eq_m512d(r, _mm512_setzero_pd());
4287 let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4288 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4289 assert_eq_m512d(r, e);
4290 }
4291
4292 #[simd_test(enable = "avx512f,avx512vl")]
4293 unsafe fn test_mm256_cvtepu32_pd() {
4294 let a = _mm_set_epi32(12, 13, 14, 15);
4295 let r = _mm256_cvtepu32_pd(a);
4296 let e = _mm256_set_pd(12., 13., 14., 15.);
4297 assert_eq_m256d(r, e);
4298 }
4299
4300 #[simd_test(enable = "avx512f,avx512vl")]
4301 unsafe fn test_mm256_mask_cvtepu32_pd() {
4302 let a = _mm_set_epi32(12, 13, 14, 15);
4303 let src = _mm256_set1_pd(-1.);
4304 let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4305 assert_eq_m256d(r, src);
4306 let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4307 let e = _mm256_set_pd(12., 13., 14., 15.);
4308 assert_eq_m256d(r, e);
4309 }
4310
4311 #[simd_test(enable = "avx512f,avx512vl")]
4312 unsafe fn test_mm256_maskz_cvtepu32_pd() {
4313 let a = _mm_set_epi32(12, 13, 14, 15);
4314 let r = _mm256_maskz_cvtepu32_pd(0, a);
4315 assert_eq_m256d(r, _mm256_setzero_pd());
4316 let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4317 let e = _mm256_set_pd(12., 13., 14., 15.);
4318 assert_eq_m256d(r, e);
4319 }
4320
4321 #[simd_test(enable = "avx512f,avx512vl")]
4322 unsafe fn test_mm_cvtepu32_pd() {
4323 let a = _mm_set_epi32(12, 13, 14, 15);
4324 let r = _mm_cvtepu32_pd(a);
4325 let e = _mm_set_pd(14., 15.);
4326 assert_eq_m128d(r, e);
4327 }
4328
4329 #[simd_test(enable = "avx512f,avx512vl")]
4330 unsafe fn test_mm_mask_cvtepu32_pd() {
4331 let a = _mm_set_epi32(12, 13, 14, 15);
4332 let src = _mm_set1_pd(-1.);
4333 let r = _mm_mask_cvtepu32_pd(src, 0, a);
4334 assert_eq_m128d(r, src);
4335 let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4336 let e = _mm_set_pd(14., 15.);
4337 assert_eq_m128d(r, e);
4338 }
4339
4340 #[simd_test(enable = "avx512f,avx512vl")]
4341 unsafe fn test_mm_maskz_cvtepu32_pd() {
4342 let a = _mm_set_epi32(12, 13, 14, 15);
4343 let r = _mm_maskz_cvtepu32_pd(0, a);
4344 assert_eq_m128d(r, _mm_setzero_pd());
4345 let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4346 let e = _mm_set_pd(14., 15.);
4347 assert_eq_m128d(r, e);
4348 }
4349
4350 #[simd_test(enable = "avx512f")]
4351 unsafe fn test_mm512_cvtepi32lo_pd() {
4352 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4353 let r = _mm512_cvtepi32lo_pd(a);
4354 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4355 assert_eq_m512d(r, e);
4356 }
4357
4358 #[simd_test(enable = "avx512f")]
4359 unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4360 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4361 let src = _mm512_set1_pd(-1.);
4362 let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4363 assert_eq_m512d(r, src);
4364 let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4365 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4366 assert_eq_m512d(r, e);
4367 }
4368
4369 #[simd_test(enable = "avx512f")]
4370 unsafe fn test_mm512_cvtepu32lo_pd() {
4371 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4372 let r = _mm512_cvtepu32lo_pd(a);
4373 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4374 assert_eq_m512d(r, e);
4375 }
4376
4377 #[simd_test(enable = "avx512f")]
4378 unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4379 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4380 let src = _mm512_set1_pd(-1.);
4381 let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4382 assert_eq_m512d(r, src);
4383 let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4384 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4385 assert_eq_m512d(r, e);
4386 }
4387
4388 #[simd_test(enable = "avx512f")]
4389 unsafe fn test_mm512_cvtepi64_epi32() {
4390 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4391 let r = _mm512_cvtepi64_epi32(a);
4392 let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4393 assert_eq_m256i(r, e);
4394 }
4395
4396 #[simd_test(enable = "avx512f")]
4397 unsafe fn test_mm512_mask_cvtepi64_epi32() {
4398 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4399 let src = _mm256_set1_epi32(-1);
4400 let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4401 assert_eq_m256i(r, src);
4402 let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4403 let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4404 assert_eq_m256i(r, e);
4405 }
4406
4407 #[simd_test(enable = "avx512f")]
4408 unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4409 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4410 let r = _mm512_maskz_cvtepi64_epi32(0, a);
4411 assert_eq_m256i(r, _mm256_setzero_si256());
4412 let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4413 let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4414 assert_eq_m256i(r, e);
4415 }
4416
4417 #[simd_test(enable = "avx512f,avx512vl")]
4418 unsafe fn test_mm256_cvtepi64_epi32() {
4419 let a = _mm256_set_epi64x(1, 2, 3, 4);
4420 let r = _mm256_cvtepi64_epi32(a);
4421 let e = _mm_set_epi32(1, 2, 3, 4);
4422 assert_eq_m128i(r, e);
4423 }
4424
4425 #[simd_test(enable = "avx512f,avx512vl")]
4426 unsafe fn test_mm256_mask_cvtepi64_epi32() {
4427 let a = _mm256_set_epi64x(1, 2, 3, 4);
4428 let src = _mm_set1_epi32(0);
4429 let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4430 assert_eq_m128i(r, src);
4431 let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4432 let e = _mm_set_epi32(1, 2, 3, 4);
4433 assert_eq_m128i(r, e);
4434 }
4435
4436 #[simd_test(enable = "avx512f,avx512vl")]
4437 unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4438 let a = _mm256_set_epi64x(1, 2, 3, 4);
4439 let r = _mm256_maskz_cvtepi64_epi32(0, a);
4440 assert_eq_m128i(r, _mm_setzero_si128());
4441 let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4442 let e = _mm_set_epi32(1, 2, 3, 4);
4443 assert_eq_m128i(r, e);
4444 }
4445
4446 #[simd_test(enable = "avx512f,avx512vl")]
4447 unsafe fn test_mm_cvtepi64_epi32() {
4448 let a = _mm_set_epi64x(3, 4);
4449 let r = _mm_cvtepi64_epi32(a);
4450 let e = _mm_set_epi32(0, 0, 3, 4);
4451 assert_eq_m128i(r, e);
4452 }
4453
4454 #[simd_test(enable = "avx512f,avx512vl")]
4455 unsafe fn test_mm_mask_cvtepi64_epi32() {
4456 let a = _mm_set_epi64x(3, 4);
4457 let src = _mm_set1_epi32(0);
4458 let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4459 assert_eq_m128i(r, src);
4460 let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4461 let e = _mm_set_epi32(0, 0, 3, 4);
4462 assert_eq_m128i(r, e);
4463 }
4464
4465 #[simd_test(enable = "avx512f,avx512vl")]
4466 unsafe fn test_mm_maskz_cvtepi64_epi32() {
4467 let a = _mm_set_epi64x(3, 4);
4468 let r = _mm_maskz_cvtepi64_epi32(0, a);
4469 assert_eq_m128i(r, _mm_setzero_si128());
4470 let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4471 let e = _mm_set_epi32(0, 0, 3, 4);
4472 assert_eq_m128i(r, e);
4473 }
4474
4475 #[simd_test(enable = "avx512f")]
4476 unsafe fn test_mm512_cvtepi64_epi16() {
4477 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4478 let r = _mm512_cvtepi64_epi16(a);
4479 let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4480 assert_eq_m128i(r, e);
4481 }
4482
4483 #[simd_test(enable = "avx512f")]
4484 unsafe fn test_mm512_mask_cvtepi64_epi16() {
4485 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4486 let src = _mm_set1_epi16(-1);
4487 let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4488 assert_eq_m128i(r, src);
4489 let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4490 let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4491 assert_eq_m128i(r, e);
4492 }
4493
4494 #[simd_test(enable = "avx512f")]
4495 unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4496 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4497 let r = _mm512_maskz_cvtepi64_epi16(0, a);
4498 assert_eq_m128i(r, _mm_setzero_si128());
4499 let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4500 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4501 assert_eq_m128i(r, e);
4502 }
4503
4504 #[simd_test(enable = "avx512f,avx512vl")]
4505 unsafe fn test_mm256_cvtepi64_epi16() {
4506 let a = _mm256_set_epi64x(12, 13, 14, 15);
4507 let r = _mm256_cvtepi64_epi16(a);
4508 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4509 assert_eq_m128i(r, e);
4510 }
4511
4512 #[simd_test(enable = "avx512f,avx512vl")]
4513 unsafe fn test_mm256_mask_cvtepi64_epi16() {
4514 let a = _mm256_set_epi64x(12, 13, 14, 15);
4515 let src = _mm_set1_epi16(0);
4516 let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4517 assert_eq_m128i(r, src);
4518 let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4519 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4520 assert_eq_m128i(r, e);
4521 }
4522
4523 #[simd_test(enable = "avx512f,avx512vl")]
4524 unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4525 let a = _mm256_set_epi64x(12, 13, 14, 15);
4526 let r = _mm256_maskz_cvtepi64_epi16(0, a);
4527 assert_eq_m128i(r, _mm_setzero_si128());
4528 let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4529 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4530 assert_eq_m128i(r, e);
4531 }
4532
4533 #[simd_test(enable = "avx512f,avx512vl")]
4534 unsafe fn test_mm_cvtepi64_epi16() {
4535 let a = _mm_set_epi64x(14, 15);
4536 let r = _mm_cvtepi64_epi16(a);
4537 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4538 assert_eq_m128i(r, e);
4539 }
4540
4541 #[simd_test(enable = "avx512f,avx512vl")]
4542 unsafe fn test_mm_mask_cvtepi64_epi16() {
4543 let a = _mm_set_epi64x(14, 15);
4544 let src = _mm_set1_epi16(0);
4545 let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4546 assert_eq_m128i(r, src);
4547 let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4548 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4549 assert_eq_m128i(r, e);
4550 }
4551
4552 #[simd_test(enable = "avx512f,avx512vl")]
4553 unsafe fn test_mm_maskz_cvtepi64_epi16() {
4554 let a = _mm_set_epi64x(14, 15);
4555 let r = _mm_maskz_cvtepi64_epi16(0, a);
4556 assert_eq_m128i(r, _mm_setzero_si128());
4557 let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4558 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4559 assert_eq_m128i(r, e);
4560 }
4561
4562 #[simd_test(enable = "avx512f")]
4563 unsafe fn test_mm512_cvtepi64_epi8() {
4564 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4565 let r = _mm512_cvtepi64_epi8(a);
4566 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4567 assert_eq_m128i(r, e);
4568 }
4569
4570 #[simd_test(enable = "avx512f")]
4571 unsafe fn test_mm512_mask_cvtepi64_epi8() {
4572 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4573 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4574 let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4575 assert_eq_m128i(r, src);
4576 let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4577 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4578 assert_eq_m128i(r, e);
4579 }
4580
4581 #[simd_test(enable = "avx512f")]
4582 unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4583 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4584 let r = _mm512_maskz_cvtepi64_epi8(0, a);
4585 assert_eq_m128i(r, _mm_setzero_si128());
4586 let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4587 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4588 assert_eq_m128i(r, e);
4589 }
4590
4591 #[simd_test(enable = "avx512f,avx512vl")]
4592 unsafe fn test_mm256_cvtepi64_epi8() {
4593 let a = _mm256_set_epi64x(12, 13, 14, 15);
4594 let r = _mm256_cvtepi64_epi8(a);
4595 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4596 assert_eq_m128i(r, e);
4597 }
4598
4599 #[simd_test(enable = "avx512f,avx512vl")]
4600 unsafe fn test_mm256_mask_cvtepi64_epi8() {
4601 let a = _mm256_set_epi64x(12, 13, 14, 15);
4602 let src = _mm_set1_epi8(0);
4603 let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4604 assert_eq_m128i(r, src);
4605 let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4606 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4607 assert_eq_m128i(r, e);
4608 }
4609
4610 #[simd_test(enable = "avx512f,avx512vl")]
4611 unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4612 let a = _mm256_set_epi64x(12, 13, 14, 15);
4613 let r = _mm256_maskz_cvtepi64_epi8(0, a);
4614 assert_eq_m128i(r, _mm_setzero_si128());
4615 let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4616 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4617 assert_eq_m128i(r, e);
4618 }
4619
4620 #[simd_test(enable = "avx512f,avx512vl")]
4621 unsafe fn test_mm_cvtepi64_epi8() {
4622 let a = _mm_set_epi64x(14, 15);
4623 let r = _mm_cvtepi64_epi8(a);
4624 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4625 assert_eq_m128i(r, e);
4626 }
4627
4628 #[simd_test(enable = "avx512f,avx512vl")]
4629 unsafe fn test_mm_mask_cvtepi64_epi8() {
4630 let a = _mm_set_epi64x(14, 15);
4631 let src = _mm_set1_epi8(0);
4632 let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4633 assert_eq_m128i(r, src);
4634 let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4635 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4636 assert_eq_m128i(r, e);
4637 }
4638
4639 #[simd_test(enable = "avx512f,avx512vl")]
4640 unsafe fn test_mm_maskz_cvtepi64_epi8() {
4641 let a = _mm_set_epi64x(14, 15);
4642 let r = _mm_maskz_cvtepi64_epi8(0, a);
4643 assert_eq_m128i(r, _mm_setzero_si128());
4644 let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4645 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4646 assert_eq_m128i(r, e);
4647 }
4648
4649 #[simd_test(enable = "avx512f")]
4650 unsafe fn test_mm512_cvtsepi64_epi32() {
4651 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4652 let r = _mm512_cvtsepi64_epi32(a);
4653 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4654 assert_eq_m256i(r, e);
4655 }
4656
4657 #[simd_test(enable = "avx512f")]
4658 unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4659 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4660 let src = _mm256_set1_epi32(-1);
4661 let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4662 assert_eq_m256i(r, src);
4663 let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4664 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4665 assert_eq_m256i(r, e);
4666 }
4667
4668 #[simd_test(enable = "avx512f")]
4669 unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4670 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4671 let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4672 assert_eq_m256i(r, _mm256_setzero_si256());
4673 let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4674 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4675 assert_eq_m256i(r, e);
4676 }
4677
4678 #[simd_test(enable = "avx512f,avx512vl")]
4679 unsafe fn test_mm256_cvtsepi64_epi32() {
4680 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4681 let r = _mm256_cvtsepi64_epi32(a);
4682 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4683 assert_eq_m128i(r, e);
4684 }
4685
4686 #[simd_test(enable = "avx512f,avx512vl")]
4687 unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4688 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4689 let src = _mm_set1_epi32(-1);
4690 let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4691 assert_eq_m128i(r, src);
4692 let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4693 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4694 assert_eq_m128i(r, e);
4695 }
4696
4697 #[simd_test(enable = "avx512f,avx512vl")]
4698 unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4699 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4700 let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4701 assert_eq_m128i(r, _mm_setzero_si128());
4702 let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4703 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4704 assert_eq_m128i(r, e);
4705 }
4706
4707 #[simd_test(enable = "avx512f,avx512vl")]
4708 unsafe fn test_mm_cvtsepi64_epi32() {
4709 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4710 let r = _mm_cvtsepi64_epi32(a);
4711 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4712 assert_eq_m128i(r, e);
4713 }
4714
4715 #[simd_test(enable = "avx512f,avx512vl")]
4716 unsafe fn test_mm_mask_cvtsepi64_epi32() {
4717 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4718 let src = _mm_set1_epi32(0);
4719 let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4720 assert_eq_m128i(r, src);
4721 let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4722 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4723 assert_eq_m128i(r, e);
4724 }
4725
4726 #[simd_test(enable = "avx512f,avx512vl")]
4727 unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4728 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4729 let r = _mm_maskz_cvtsepi64_epi32(0, a);
4730 assert_eq_m128i(r, _mm_setzero_si128());
4731 let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4732 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4733 assert_eq_m128i(r, e);
4734 }
4735
4736 #[simd_test(enable = "avx512f")]
4737 unsafe fn test_mm512_cvtsepi64_epi16() {
4738 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4739 let r = _mm512_cvtsepi64_epi16(a);
4740 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4741 assert_eq_m128i(r, e);
4742 }
4743
4744 #[simd_test(enable = "avx512f")]
4745 unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4746 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4747 let src = _mm_set1_epi16(-1);
4748 let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4749 assert_eq_m128i(r, src);
4750 let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4751 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4752 assert_eq_m128i(r, e);
4753 }
4754
4755 #[simd_test(enable = "avx512f")]
4756 unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4757 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4758 let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4759 assert_eq_m128i(r, _mm_setzero_si128());
4760 let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4761 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4762 assert_eq_m128i(r, e);
4763 }
4764
4765 #[simd_test(enable = "avx512f,avx512vl")]
4766 unsafe fn test_mm256_cvtsepi64_epi16() {
4767 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4768 let r = _mm256_cvtsepi64_epi16(a);
4769 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4770 assert_eq_m128i(r, e);
4771 }
4772
4773 #[simd_test(enable = "avx512f,avx512vl")]
4774 unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4775 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4776 let src = _mm_set1_epi16(0);
4777 let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4778 assert_eq_m128i(r, src);
4779 let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4780 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4781 assert_eq_m128i(r, e);
4782 }
4783
4784 #[simd_test(enable = "avx512f,avx512vl")]
4785 unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4786 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4787 let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4788 assert_eq_m128i(r, _mm_setzero_si128());
4789 let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4790 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4791 assert_eq_m128i(r, e);
4792 }
4793
4794 #[simd_test(enable = "avx512f,avx512vl")]
4795 unsafe fn test_mm_cvtsepi64_epi16() {
4796 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4797 let r = _mm_cvtsepi64_epi16(a);
4798 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4799 assert_eq_m128i(r, e);
4800 }
4801
4802 #[simd_test(enable = "avx512f,avx512vl")]
4803 unsafe fn test_mm_mask_cvtsepi64_epi16() {
4804 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4805 let src = _mm_set1_epi16(0);
4806 let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4807 assert_eq_m128i(r, src);
4808 let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4809 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4810 assert_eq_m128i(r, e);
4811 }
4812
4813 #[simd_test(enable = "avx512f,avx512vl")]
4814 unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4815 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4816 let r = _mm_maskz_cvtsepi64_epi16(0, a);
4817 assert_eq_m128i(r, _mm_setzero_si128());
4818 let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4819 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4820 assert_eq_m128i(r, e);
4821 }
4822
4823 #[simd_test(enable = "avx512f")]
4824 unsafe fn test_mm512_cvtsepi64_epi8() {
4825 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4826 let r = _mm512_cvtsepi64_epi8(a);
4827 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4828 assert_eq_m128i(r, e);
4829 }
4830
4831 #[simd_test(enable = "avx512f")]
4832 unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4833 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4834 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4835 let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4836 assert_eq_m128i(r, src);
4837 let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4838 #[rustfmt::skip]
4839 let e = _mm_set_epi8(
4840 0, 0, 0, 0,
4841 0, 0, 0, 0,
4842 -1, -1, -1, -1,
4843 4, 5, i8::MIN, i8::MAX,
4844 );
4845 assert_eq_m128i(r, e);
4846 }
4847
4848 #[simd_test(enable = "avx512f")]
4849 unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4850 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4851 let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4852 assert_eq_m128i(r, _mm_setzero_si128());
4853 let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4854 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4855 assert_eq_m128i(r, e);
4856 }
4857
4858 #[simd_test(enable = "avx512f,avx512vl")]
4859 unsafe fn test_mm256_cvtsepi64_epi8() {
4860 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4861 let r = _mm256_cvtsepi64_epi8(a);
4862 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4863 assert_eq_m128i(r, e);
4864 }
4865
4866 #[simd_test(enable = "avx512f,avx512vl")]
4867 unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4868 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4869 let src = _mm_set1_epi8(0);
4870 let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4871 assert_eq_m128i(r, src);
4872 let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4873 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4874 assert_eq_m128i(r, e);
4875 }
4876
4877 #[simd_test(enable = "avx512f,avx512vl")]
4878 unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4879 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4880 let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4881 assert_eq_m128i(r, _mm_setzero_si128());
4882 let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4883 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4884 assert_eq_m128i(r, e);
4885 }
4886
4887 #[simd_test(enable = "avx512f,avx512vl")]
4888 unsafe fn test_mm_cvtsepi64_epi8() {
4889 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4890 let r = _mm_cvtsepi64_epi8(a);
4891 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4892 assert_eq_m128i(r, e);
4893 }
4894
4895 #[simd_test(enable = "avx512f,avx512vl")]
4896 unsafe fn test_mm_mask_cvtsepi64_epi8() {
4897 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4898 let src = _mm_set1_epi8(0);
4899 let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4900 assert_eq_m128i(r, src);
4901 let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4902 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4903 assert_eq_m128i(r, e);
4904 }
4905
4906 #[simd_test(enable = "avx512f,avx512vl")]
4907 unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4908 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4909 let r = _mm_maskz_cvtsepi64_epi8(0, a);
4910 assert_eq_m128i(r, _mm_setzero_si128());
4911 let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4912 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4913 assert_eq_m128i(r, e);
4914 }
4915
4916 #[simd_test(enable = "avx512f")]
4917 unsafe fn test_mm512_cvtusepi64_epi32() {
4918 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4919 let r = _mm512_cvtusepi64_epi32(a);
4920 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4921 assert_eq_m256i(r, e);
4922 }
4923
4924 #[simd_test(enable = "avx512f")]
4925 unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4926 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4927 let src = _mm256_set1_epi32(-1);
4928 let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4929 assert_eq_m256i(r, src);
4930 let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4931 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4932 assert_eq_m256i(r, e);
4933 }
4934
4935 #[simd_test(enable = "avx512f")]
4936 unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4937 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4938 let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4939 assert_eq_m256i(r, _mm256_setzero_si256());
4940 let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4941 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4942 assert_eq_m256i(r, e);
4943 }
4944
4945 #[simd_test(enable = "avx512f,avx512vl")]
4946 unsafe fn test_mm256_cvtusepi64_epi32() {
4947 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4948 let r = _mm256_cvtusepi64_epi32(a);
4949 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4950 assert_eq_m128i(r, e);
4951 }
4952
4953 #[simd_test(enable = "avx512f,avx512vl")]
4954 unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4955 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4956 let src = _mm_set1_epi32(0);
4957 let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4958 assert_eq_m128i(r, src);
4959 let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4960 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4961 assert_eq_m128i(r, e);
4962 }
4963
4964 #[simd_test(enable = "avx512f,avx512vl")]
4965 unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4966 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4967 let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4968 assert_eq_m128i(r, _mm_setzero_si128());
4969 let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4970 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4971 assert_eq_m128i(r, e);
4972 }
4973
4974 #[simd_test(enable = "avx512f,avx512vl")]
4975 unsafe fn test_mm_cvtusepi64_epi32() {
4976 let a = _mm_set_epi64x(6, i64::MAX);
4977 let r = _mm_cvtusepi64_epi32(a);
4978 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4979 assert_eq_m128i(r, e);
4980 }
4981
4982 #[simd_test(enable = "avx512f,avx512vl")]
4983 unsafe fn test_mm_mask_cvtusepi64_epi32() {
4984 let a = _mm_set_epi64x(6, i64::MAX);
4985 let src = _mm_set1_epi32(0);
4986 let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4987 assert_eq_m128i(r, src);
4988 let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4989 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4990 assert_eq_m128i(r, e);
4991 }
4992
4993 #[simd_test(enable = "avx512f,avx512vl")]
4994 unsafe fn test_mm_maskz_cvtusepi64_epi32() {
4995 let a = _mm_set_epi64x(6, i64::MAX);
4996 let r = _mm_maskz_cvtusepi64_epi32(0, a);
4997 assert_eq_m128i(r, _mm_setzero_si128());
4998 let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
4999 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
5000 assert_eq_m128i(r, e);
5001 }
5002
5003 #[simd_test(enable = "avx512f")]
5004 unsafe fn test_mm512_cvtusepi64_epi16() {
5005 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5006 let r = _mm512_cvtusepi64_epi16(a);
5007 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
5008 assert_eq_m128i(r, e);
5009 }
5010
5011 #[simd_test(enable = "avx512f")]
5012 unsafe fn test_mm512_mask_cvtusepi64_epi16() {
5013 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5014 let src = _mm_set1_epi16(-1);
5015 let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
5016 assert_eq_m128i(r, src);
5017 let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
5018 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
5019 assert_eq_m128i(r, e);
5020 }
5021
5022 #[simd_test(enable = "avx512f")]
5023 unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
5024 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5025 let r = _mm512_maskz_cvtusepi64_epi16(0, a);
5026 assert_eq_m128i(r, _mm_setzero_si128());
5027 let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
5028 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
5029 assert_eq_m128i(r, e);
5030 }
5031
5032 #[simd_test(enable = "avx512f,avx512vl")]
5033 unsafe fn test_mm256_cvtusepi64_epi16() {
5034 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5035 let r = _mm256_cvtusepi64_epi16(a);
5036 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5037 assert_eq_m128i(r, e);
5038 }
5039
5040 #[simd_test(enable = "avx512f,avx512vl")]
5041 unsafe fn test_mm256_mask_cvtusepi64_epi16() {
5042 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5043 let src = _mm_set1_epi16(0);
5044 let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
5045 assert_eq_m128i(r, src);
5046 let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
5047 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5048 assert_eq_m128i(r, e);
5049 }
5050
5051 #[simd_test(enable = "avx512f,avx512vl")]
5052 unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
5053 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5054 let r = _mm256_maskz_cvtusepi64_epi16(0, a);
5055 assert_eq_m128i(r, _mm_setzero_si128());
5056 let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
5057 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5058 assert_eq_m128i(r, e);
5059 }
5060
5061 #[simd_test(enable = "avx512f,avx512vl")]
5062 unsafe fn test_mm_cvtusepi64_epi16() {
5063 let a = _mm_set_epi64x(6, i64::MAX);
5064 let r = _mm_cvtusepi64_epi16(a);
5065 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5066 assert_eq_m128i(r, e);
5067 }
5068
5069 #[simd_test(enable = "avx512f,avx512vl")]
5070 unsafe fn test_mm_mask_cvtusepi64_epi16() {
5071 let a = _mm_set_epi64x(6, i64::MAX);
5072 let src = _mm_set1_epi16(0);
5073 let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
5074 assert_eq_m128i(r, src);
5075 let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
5076 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5077 assert_eq_m128i(r, e);
5078 }
5079
5080 #[simd_test(enable = "avx512f,avx512vl")]
5081 unsafe fn test_mm_maskz_cvtusepi64_epi16() {
5082 let a = _mm_set_epi64x(6, i64::MAX);
5083 let r = _mm_maskz_cvtusepi64_epi16(0, a);
5084 assert_eq_m128i(r, _mm_setzero_si128());
5085 let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
5086 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5087 assert_eq_m128i(r, e);
5088 }
5089
5090 #[simd_test(enable = "avx512f")]
5091 unsafe fn test_mm512_cvtusepi64_epi8() {
5092 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5093 let r = _mm512_cvtusepi64_epi8(a);
5094 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
5095 assert_eq_m128i(r, e);
5096 }
5097
5098 #[simd_test(enable = "avx512f")]
5099 unsafe fn test_mm512_mask_cvtusepi64_epi8() {
5100 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5101 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
5102 let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
5103 assert_eq_m128i(r, src);
5104 let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
5105 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
5106 assert_eq_m128i(r, e);
5107 }
5108
5109 #[simd_test(enable = "avx512f")]
5110 unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
5111 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5112 let r = _mm512_maskz_cvtusepi64_epi8(0, a);
5113 assert_eq_m128i(r, _mm_setzero_si128());
5114 let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
5115 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
5116 assert_eq_m128i(r, e);
5117 }
5118
5119 #[simd_test(enable = "avx512f,avx512vl")]
5120 unsafe fn test_mm256_cvtusepi64_epi8() {
5121 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5122 let r = _mm256_cvtusepi64_epi8(a);
5123 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5124 assert_eq_m128i(r, e);
5125 }
5126
5127 #[simd_test(enable = "avx512f,avx512vl")]
5128 unsafe fn test_mm256_mask_cvtusepi64_epi8() {
5129 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5130 let src = _mm_set1_epi8(0);
5131 let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
5132 assert_eq_m128i(r, src);
5133 let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
5134 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5135 assert_eq_m128i(r, e);
5136 }
5137
5138 #[simd_test(enable = "avx512f,avx512vl")]
5139 unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
5140 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5141 let r = _mm256_maskz_cvtusepi64_epi8(0, a);
5142 assert_eq_m128i(r, _mm_setzero_si128());
5143 let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5144 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5145 assert_eq_m128i(r, e);
5146 }
5147
5148 #[simd_test(enable = "avx512f,avx512vl")]
5149 unsafe fn test_mm_cvtusepi64_epi8() {
5150 let a = _mm_set_epi64x(6, i64::MAX);
5151 let r = _mm_cvtusepi64_epi8(a);
5152 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5153 assert_eq_m128i(r, e);
5154 }
5155
5156 #[simd_test(enable = "avx512f,avx512vl")]
5157 unsafe fn test_mm_mask_cvtusepi64_epi8() {
5158 let a = _mm_set_epi64x(6, i64::MAX);
5159 let src = _mm_set1_epi8(0);
5160 let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5161 assert_eq_m128i(r, src);
5162 let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5163 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5164 assert_eq_m128i(r, e);
5165 }
5166
5167 #[simd_test(enable = "avx512f,avx512vl")]
5168 unsafe fn test_mm_maskz_cvtusepi64_epi8() {
5169 let a = _mm_set_epi64x(6, i64::MAX);
5170 let r = _mm_maskz_cvtusepi64_epi8(0, a);
5171 assert_eq_m128i(r, _mm_setzero_si128());
5172 let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5173 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5174 assert_eq_m128i(r, e);
5175 }
5176
5177 #[simd_test(enable = "avx512f")]
5178 unsafe fn test_mm512_cvtt_roundpd_epi32() {
5179 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5180 let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5181 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5182 assert_eq_m256i(r, e);
5183 }
5184
5185 #[simd_test(enable = "avx512f")]
5186 unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5187 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5188 let src = _mm256_set1_epi32(0);
5189 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5190 assert_eq_m256i(r, src);
5191 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5192 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5193 assert_eq_m256i(r, e);
5194 }
5195
5196 #[simd_test(enable = "avx512f")]
5197 unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5198 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5199 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5200 assert_eq_m256i(r, _mm256_setzero_si256());
5201 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5202 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5203 assert_eq_m256i(r, e);
5204 }
5205
5206 #[simd_test(enable = "avx512f")]
5207 unsafe fn test_mm512_cvtt_roundpd_epu32() {
5208 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5209 let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5210 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5211 assert_eq_m256i(r, e);
5212 }
5213
5214 #[simd_test(enable = "avx512f")]
5215 unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5216 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5217 let src = _mm256_set1_epi32(0);
5218 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5219 assert_eq_m256i(r, src);
5220 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5221 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5222 assert_eq_m256i(r, e);
5223 }
5224
5225 #[simd_test(enable = "avx512f")]
5226 unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5227 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5228 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5229 assert_eq_m256i(r, _mm256_setzero_si256());
5230 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5231 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5232 assert_eq_m256i(r, e);
5233 }
5234
5235 #[simd_test(enable = "avx512f")]
5236 unsafe fn test_mm512_cvttpd_epi32() {
5237 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5238 let r = _mm512_cvttpd_epi32(a);
5239 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5240 assert_eq_m256i(r, e);
5241 }
5242
5243 #[simd_test(enable = "avx512f")]
5244 unsafe fn test_mm512_mask_cvttpd_epi32() {
5245 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5246 let src = _mm256_set1_epi32(0);
5247 let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5248 assert_eq_m256i(r, src);
5249 let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5250 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5251 assert_eq_m256i(r, e);
5252 }
5253
5254 #[simd_test(enable = "avx512f")]
5255 unsafe fn test_mm512_maskz_cvttpd_epi32() {
5256 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5257 let r = _mm512_maskz_cvttpd_epi32(0, a);
5258 assert_eq_m256i(r, _mm256_setzero_si256());
5259 let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5260 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5261 assert_eq_m256i(r, e);
5262 }
5263
5264 #[simd_test(enable = "avx512f,avx512vl")]
5265 unsafe fn test_mm256_mask_cvttpd_epi32() {
5266 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5267 let src = _mm_set1_epi32(0);
5268 let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5269 assert_eq_m128i(r, src);
5270 let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5271 let e = _mm_setr_epi32(4, -5, 6, -7);
5272 assert_eq_m128i(r, e);
5273 }
5274
5275 #[simd_test(enable = "avx512f,avx512vl")]
5276 unsafe fn test_mm256_maskz_cvttpd_epi32() {
5277 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5278 let r = _mm256_maskz_cvttpd_epi32(0, a);
5279 assert_eq_m128i(r, _mm_setzero_si128());
5280 let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5281 let e = _mm_setr_epi32(4, -5, 6, -7);
5282 assert_eq_m128i(r, e);
5283 }
5284
5285 #[simd_test(enable = "avx512f,avx512vl")]
5286 unsafe fn test_mm_mask_cvttpd_epi32() {
5287 let a = _mm_set_pd(6., -7.5);
5288 let src = _mm_set1_epi32(0);
5289 let r = _mm_mask_cvttpd_epi32(src, 0, a);
5290 assert_eq_m128i(r, src);
5291 let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5292 let e = _mm_set_epi32(0, 0, 6, -7);
5293 assert_eq_m128i(r, e);
5294 }
5295
5296 #[simd_test(enable = "avx512f,avx512vl")]
5297 unsafe fn test_mm_maskz_cvttpd_epi32() {
5298 let a = _mm_set_pd(6., -7.5);
5299 let r = _mm_maskz_cvttpd_epi32(0, a);
5300 assert_eq_m128i(r, _mm_setzero_si128());
5301 let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5302 let e = _mm_set_epi32(0, 0, 6, -7);
5303 assert_eq_m128i(r, e);
5304 }
5305
5306 #[simd_test(enable = "avx512f")]
5307 unsafe fn test_mm512_cvttpd_epu32() {
5308 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5309 let r = _mm512_cvttpd_epu32(a);
5310 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5311 assert_eq_m256i(r, e);
5312 }
5313
5314 #[simd_test(enable = "avx512f")]
5315 unsafe fn test_mm512_mask_cvttpd_epu32() {
5316 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5317 let src = _mm256_set1_epi32(0);
5318 let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5319 assert_eq_m256i(r, src);
5320 let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5321 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5322 assert_eq_m256i(r, e);
5323 }
5324
5325 #[simd_test(enable = "avx512f")]
5326 unsafe fn test_mm512_maskz_cvttpd_epu32() {
5327 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5328 let r = _mm512_maskz_cvttpd_epu32(0, a);
5329 assert_eq_m256i(r, _mm256_setzero_si256());
5330 let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5331 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5332 assert_eq_m256i(r, e);
5333 }
5334
5335 #[simd_test(enable = "avx512f,avx512vl")]
5336 unsafe fn test_mm256_cvttpd_epu32() {
5337 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5338 let r = _mm256_cvttpd_epu32(a);
5339 let e = _mm_set_epi32(4, 5, 6, 7);
5340 assert_eq_m128i(r, e);
5341 }
5342
5343 #[simd_test(enable = "avx512f,avx512vl")]
5344 unsafe fn test_mm256_mask_cvttpd_epu32() {
5345 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5346 let src = _mm_set1_epi32(0);
5347 let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5348 assert_eq_m128i(r, src);
5349 let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5350 let e = _mm_set_epi32(4, 5, 6, 7);
5351 assert_eq_m128i(r, e);
5352 }
5353
5354 #[simd_test(enable = "avx512f,avx512vl")]
5355 unsafe fn test_mm256_maskz_cvttpd_epu32() {
5356 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5357 let r = _mm256_maskz_cvttpd_epu32(0, a);
5358 assert_eq_m128i(r, _mm_setzero_si128());
5359 let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5360 let e = _mm_set_epi32(4, 5, 6, 7);
5361 assert_eq_m128i(r, e);
5362 }
5363
5364 #[simd_test(enable = "avx512f,avx512vl")]
5365 unsafe fn test_mm_cvttpd_epu32() {
5366 let a = _mm_set_pd(6., 7.5);
5367 let r = _mm_cvttpd_epu32(a);
5368 let e = _mm_set_epi32(0, 0, 6, 7);
5369 assert_eq_m128i(r, e);
5370 }
5371
5372 #[simd_test(enable = "avx512f,avx512vl")]
5373 unsafe fn test_mm_mask_cvttpd_epu32() {
5374 let a = _mm_set_pd(6., 7.5);
5375 let src = _mm_set1_epi32(0);
5376 let r = _mm_mask_cvttpd_epu32(src, 0, a);
5377 assert_eq_m128i(r, src);
5378 let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5379 let e = _mm_set_epi32(0, 0, 6, 7);
5380 assert_eq_m128i(r, e);
5381 }
5382
5383 #[simd_test(enable = "avx512f,avx512vl")]
5384 unsafe fn test_mm_maskz_cvttpd_epu32() {
5385 let a = _mm_set_pd(6., 7.5);
5386 let r = _mm_maskz_cvttpd_epu32(0, a);
5387 assert_eq_m128i(r, _mm_setzero_si128());
5388 let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5389 let e = _mm_set_epi32(0, 0, 6, 7);
5390 assert_eq_m128i(r, e);
5391 }
5392
5393 #[simd_test(enable = "avx512f")]
5394 unsafe fn test_mm512_add_round_pd() {
5395 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5396 let b = _mm512_set1_pd(-1.);
5397 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5398 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5399 assert_eq_m512d(r, e);
5400 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5401 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5402 assert_eq_m512d(r, e);
5403 }
5404
5405 #[simd_test(enable = "avx512f")]
5406 unsafe fn test_mm512_mask_add_round_pd() {
5407 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5408 let b = _mm512_set1_pd(-1.);
5409 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5410 a, 0, a, b,
5411 );
5412 assert_eq_m512d(r, a);
5413 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5414 a, 0b11110000, a, b,
5415 );
5416 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5417 assert_eq_m512d(r, e);
5418 }
5419
5420 #[simd_test(enable = "avx512f")]
5421 unsafe fn test_mm512_maskz_add_round_pd() {
5422 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5423 let b = _mm512_set1_pd(-1.);
5424 let r =
5425 _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5426 assert_eq_m512d(r, _mm512_setzero_pd());
5427 let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5428 0b11110000, a, b,
5429 );
5430 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5431 assert_eq_m512d(r, e);
5432 }
5433
5434 #[simd_test(enable = "avx512f")]
5435 unsafe fn test_mm512_sub_round_pd() {
5436 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5437 let b = _mm512_set1_pd(1.);
5438 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5439 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5440 assert_eq_m512d(r, e);
5441 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5442 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5443 assert_eq_m512d(r, e);
5444 }
5445
5446 #[simd_test(enable = "avx512f")]
5447 unsafe fn test_mm512_mask_sub_round_pd() {
5448 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5449 let b = _mm512_set1_pd(1.);
5450 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5451 a, 0, a, b,
5452 );
5453 assert_eq_m512d(r, a);
5454 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5455 a, 0b11110000, a, b,
5456 );
5457 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5458 assert_eq_m512d(r, e);
5459 }
5460
5461 #[simd_test(enable = "avx512f")]
5462 unsafe fn test_mm512_maskz_sub_round_pd() {
5463 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5464 let b = _mm512_set1_pd(1.);
5465 let r =
5466 _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5467 assert_eq_m512d(r, _mm512_setzero_pd());
5468 let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5469 0b11110000, a, b,
5470 );
5471 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5472 assert_eq_m512d(r, e);
5473 }
5474
5475 #[simd_test(enable = "avx512f")]
5476 unsafe fn test_mm512_mul_round_pd() {
5477 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5478 let b = _mm512_set1_pd(0.1);
5479 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5480 let e = _mm512_setr_pd(
5481 0.8,
5482 0.9500000000000001,
5483 1.,
5484 1.1500000000000001,
5485 1.2000000000000002,
5486 1.35,
5487 1.4000000000000001,
5488 0.,
5489 );
5490 assert_eq_m512d(r, e);
5491 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5492 let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5493 assert_eq_m512d(r, e);
5494 }
5495
5496 #[simd_test(enable = "avx512f")]
5497 unsafe fn test_mm512_mask_mul_round_pd() {
5498 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5499 let b = _mm512_set1_pd(0.1);
5500 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5501 a, 0, a, b,
5502 );
5503 assert_eq_m512d(r, a);
5504 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5505 a, 0b11110000, a, b,
5506 );
5507 let e = _mm512_setr_pd(
5508 8.,
5509 9.5,
5510 10.,
5511 11.5,
5512 1.2000000000000002,
5513 1.35,
5514 1.4000000000000001,
5515 0.,
5516 );
5517 assert_eq_m512d(r, e);
5518 }
5519
5520 #[simd_test(enable = "avx512f")]
5521 unsafe fn test_mm512_maskz_mul_round_pd() {
5522 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5523 let b = _mm512_set1_pd(0.1);
5524 let r =
5525 _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5526 assert_eq_m512d(r, _mm512_setzero_pd());
5527 let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5528 0b11110000, a, b,
5529 );
5530 let e = _mm512_setr_pd(
5531 0.,
5532 0.,
5533 0.,
5534 0.,
5535 1.2000000000000002,
5536 1.35,
5537 1.4000000000000001,
5538 0.,
5539 );
5540 assert_eq_m512d(r, e);
5541 }
5542
5543 #[simd_test(enable = "avx512f")]
5544 unsafe fn test_mm512_div_round_pd() {
5545 let a = _mm512_set1_pd(1.);
5546 let b = _mm512_set1_pd(3.);
5547 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5548 let e = _mm512_set1_pd(0.3333333333333333);
5549 assert_eq_m512d(r, e);
5550 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5551 let e = _mm512_set1_pd(0.3333333333333333);
5552 assert_eq_m512d(r, e);
5553 }
5554
5555 #[simd_test(enable = "avx512f")]
5556 unsafe fn test_mm512_mask_div_round_pd() {
5557 let a = _mm512_set1_pd(1.);
5558 let b = _mm512_set1_pd(3.);
5559 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5560 a, 0, a, b,
5561 );
5562 assert_eq_m512d(r, a);
5563 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5564 a, 0b11110000, a, b,
5565 );
5566 let e = _mm512_setr_pd(
5567 1.,
5568 1.,
5569 1.,
5570 1.,
5571 0.3333333333333333,
5572 0.3333333333333333,
5573 0.3333333333333333,
5574 0.3333333333333333,
5575 );
5576 assert_eq_m512d(r, e);
5577 }
5578
5579 #[simd_test(enable = "avx512f")]
5580 unsafe fn test_mm512_maskz_div_round_pd() {
5581 let a = _mm512_set1_pd(1.);
5582 let b = _mm512_set1_pd(3.);
5583 let r =
5584 _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5585 assert_eq_m512d(r, _mm512_setzero_pd());
5586 let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5587 0b11110000, a, b,
5588 );
5589 let e = _mm512_setr_pd(
5590 0.,
5591 0.,
5592 0.,
5593 0.,
5594 0.3333333333333333,
5595 0.3333333333333333,
5596 0.3333333333333333,
5597 0.3333333333333333,
5598 );
5599 assert_eq_m512d(r, e);
5600 }
5601
5602 #[simd_test(enable = "avx512f")]
5603 unsafe fn test_mm512_sqrt_round_pd() {
5604 let a = _mm512_set1_pd(3.);
5605 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5606 let e = _mm512_set1_pd(1.7320508075688772);
5607 assert_eq_m512d(r, e);
5608 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5609 let e = _mm512_set1_pd(1.7320508075688774);
5610 assert_eq_m512d(r, e);
5611 }
5612
5613 #[simd_test(enable = "avx512f")]
5614 unsafe fn test_mm512_mask_sqrt_round_pd() {
5615 let a = _mm512_set1_pd(3.);
5616 let r =
5617 _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5618 assert_eq_m512d(r, a);
5619 let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5620 a, 0b11110000, a,
5621 );
5622 let e = _mm512_setr_pd(
5623 3.,
5624 3.,
5625 3.,
5626 3.,
5627 1.7320508075688772,
5628 1.7320508075688772,
5629 1.7320508075688772,
5630 1.7320508075688772,
5631 );
5632 assert_eq_m512d(r, e);
5633 }
5634
5635 #[simd_test(enable = "avx512f")]
5636 unsafe fn test_mm512_maskz_sqrt_round_pd() {
5637 let a = _mm512_set1_pd(3.);
5638 let r =
5639 _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5640 assert_eq_m512d(r, _mm512_setzero_pd());
5641 let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5642 0b11110000, a,
5643 );
5644 let e = _mm512_setr_pd(
5645 0.,
5646 0.,
5647 0.,
5648 0.,
5649 1.7320508075688772,
5650 1.7320508075688772,
5651 1.7320508075688772,
5652 1.7320508075688772,
5653 );
5654 assert_eq_m512d(r, e);
5655 }
5656
5657 #[simd_test(enable = "avx512f")]
5658 unsafe fn test_mm512_fmadd_round_pd() {
5659 let a = _mm512_set1_pd(0.000000000000000007);
5660 let b = _mm512_set1_pd(1.);
5661 let c = _mm512_set1_pd(-1.);
5662 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5663 let e = _mm512_set1_pd(-1.);
5664 assert_eq_m512d(r, e);
5665 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5666 let e = _mm512_set1_pd(-0.9999999999999999);
5667 assert_eq_m512d(r, e);
5668 }
5669
5670 #[simd_test(enable = "avx512f")]
5671 unsafe fn test_mm512_mask_fmadd_round_pd() {
5672 let a = _mm512_set1_pd(0.000000000000000007);
5673 let b = _mm512_set1_pd(1.);
5674 let c = _mm512_set1_pd(-1.);
5675 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5676 a, 0, b, c,
5677 );
5678 assert_eq_m512d(r, a);
5679 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5680 a, 0b00001111, b, c,
5681 );
5682 let e = _mm512_setr_pd(
5683 -1.,
5684 -1.,
5685 -1.,
5686 -1.,
5687 0.000000000000000007,
5688 0.000000000000000007,
5689 0.000000000000000007,
5690 0.000000000000000007,
5691 );
5692 assert_eq_m512d(r, e);
5693 }
5694
5695 #[simd_test(enable = "avx512f")]
5696 unsafe fn test_mm512_maskz_fmadd_round_pd() {
5697 let a = _mm512_set1_pd(0.000000000000000007);
5698 let b = _mm512_set1_pd(1.);
5699 let c = _mm512_set1_pd(-1.);
5700 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5701 0, a, b, c,
5702 );
5703 assert_eq_m512d(r, _mm512_setzero_pd());
5704 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5705 0b00001111, a, b, c,
5706 );
5707 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5708 assert_eq_m512d(r, e);
5709 }
5710
5711 #[simd_test(enable = "avx512f")]
5712 unsafe fn test_mm512_mask3_fmadd_round_pd() {
5713 let a = _mm512_set1_pd(0.000000000000000007);
5714 let b = _mm512_set1_pd(1.);
5715 let c = _mm512_set1_pd(-1.);
5716 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5717 a, b, c, 0,
5718 );
5719 assert_eq_m512d(r, c);
5720 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5721 a, b, c, 0b00001111,
5722 );
5723 let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5724 assert_eq_m512d(r, e);
5725 }
5726
5727 #[simd_test(enable = "avx512f")]
5728 unsafe fn test_mm512_fmsub_round_pd() {
5729 let a = _mm512_set1_pd(0.000000000000000007);
5730 let b = _mm512_set1_pd(1.);
5731 let c = _mm512_set1_pd(1.);
5732 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5733 let e = _mm512_set1_pd(-1.);
5734 assert_eq_m512d(r, e);
5735 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5736 let e = _mm512_set1_pd(-0.9999999999999999);
5737 assert_eq_m512d(r, e);
5738 }
5739
5740 #[simd_test(enable = "avx512f")]
5741 unsafe fn test_mm512_mask_fmsub_round_pd() {
5742 let a = _mm512_set1_pd(0.000000000000000007);
5743 let b = _mm512_set1_pd(1.);
5744 let c = _mm512_set1_pd(1.);
5745 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5746 a, 0, b, c,
5747 );
5748 assert_eq_m512d(r, a);
5749 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5750 a, 0b00001111, b, c,
5751 );
5752 let e = _mm512_setr_pd(
5753 -1.,
5754 -1.,
5755 -1.,
5756 -1.,
5757 0.000000000000000007,
5758 0.000000000000000007,
5759 0.000000000000000007,
5760 0.000000000000000007,
5761 );
5762 assert_eq_m512d(r, e);
5763 }
5764
5765 #[simd_test(enable = "avx512f")]
5766 unsafe fn test_mm512_maskz_fmsub_round_pd() {
5767 let a = _mm512_set1_pd(0.000000000000000007);
5768 let b = _mm512_set1_pd(1.);
5769 let c = _mm512_set1_pd(1.);
5770 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5771 0, a, b, c,
5772 );
5773 assert_eq_m512d(r, _mm512_setzero_pd());
5774 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5775 0b00001111, a, b, c,
5776 );
5777 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5778 assert_eq_m512d(r, e);
5779 }
5780
5781 #[simd_test(enable = "avx512f")]
5782 unsafe fn test_mm512_mask3_fmsub_round_pd() {
5783 let a = _mm512_set1_pd(0.000000000000000007);
5784 let b = _mm512_set1_pd(1.);
5785 let c = _mm512_set1_pd(1.);
5786 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5787 a, b, c, 0,
5788 );
5789 assert_eq_m512d(r, c);
5790 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5791 a, b, c, 0b00001111,
5792 );
5793 let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5794 assert_eq_m512d(r, e);
5795 }
5796
5797 #[simd_test(enable = "avx512f")]
5798 unsafe fn test_mm512_fmaddsub_round_pd() {
5799 let a = _mm512_set1_pd(0.000000000000000007);
5800 let b = _mm512_set1_pd(1.);
5801 let c = _mm512_set1_pd(-1.);
5802 let r =
5803 _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5804 let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5805 assert_eq_m512d(r, e);
5806 let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5807 let e = _mm512_setr_pd(
5808 1.,
5809 -0.9999999999999999,
5810 1.,
5811 -0.9999999999999999,
5812 1.,
5813 -0.9999999999999999,
5814 1.,
5815 -0.9999999999999999,
5816 );
5817 assert_eq_m512d(r, e);
5818 }
5819
5820 #[simd_test(enable = "avx512f")]
5821 unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5822 let a = _mm512_set1_pd(0.000000000000000007);
5823 let b = _mm512_set1_pd(1.);
5824 let c = _mm512_set1_pd(-1.);
5825 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5826 a, 0, b, c,
5827 );
5828 assert_eq_m512d(r, a);
5829 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5830 a, 0b00001111, b, c,
5831 );
5832 let e = _mm512_setr_pd(
5833 1.,
5834 -1.,
5835 1.,
5836 -1.,
5837 0.000000000000000007,
5838 0.000000000000000007,
5839 0.000000000000000007,
5840 0.000000000000000007,
5841 );
5842 assert_eq_m512d(r, e);
5843 }
5844
5845 #[simd_test(enable = "avx512f")]
5846 unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5847 let a = _mm512_set1_pd(0.000000000000000007);
5848 let b = _mm512_set1_pd(1.);
5849 let c = _mm512_set1_pd(-1.);
5850 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5851 0, a, b, c,
5852 );
5853 assert_eq_m512d(r, _mm512_setzero_pd());
5854 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5855 0b00001111, a, b, c,
5856 );
5857 let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5858 assert_eq_m512d(r, e);
5859 }
5860
5861 #[simd_test(enable = "avx512f")]
5862 unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5863 let a = _mm512_set1_pd(0.000000000000000007);
5864 let b = _mm512_set1_pd(1.);
5865 let c = _mm512_set1_pd(-1.);
5866 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5867 a, b, c, 0,
5868 );
5869 assert_eq_m512d(r, c);
5870 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5871 a, b, c, 0b00001111,
5872 );
5873 let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5874 assert_eq_m512d(r, e);
5875 }
5876
5877 #[simd_test(enable = "avx512f")]
5878 unsafe fn test_mm512_fmsubadd_round_pd() {
5879 let a = _mm512_set1_pd(0.000000000000000007);
5880 let b = _mm512_set1_pd(1.);
5881 let c = _mm512_set1_pd(-1.);
5882 let r =
5883 _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5884 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5885 assert_eq_m512d(r, e);
5886 let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5887 let e = _mm512_setr_pd(
5888 -0.9999999999999999,
5889 1.,
5890 -0.9999999999999999,
5891 1.,
5892 -0.9999999999999999,
5893 1.,
5894 -0.9999999999999999,
5895 1.,
5896 );
5897 assert_eq_m512d(r, e);
5898 }
5899
5900 #[simd_test(enable = "avx512f")]
5901 unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5902 let a = _mm512_set1_pd(0.000000000000000007);
5903 let b = _mm512_set1_pd(1.);
5904 let c = _mm512_set1_pd(-1.);
5905 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5906 a, 0, b, c,
5907 );
5908 assert_eq_m512d(r, a);
5909 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5910 a, 0b00001111, b, c,
5911 );
5912 let e = _mm512_setr_pd(
5913 -1.,
5914 1.,
5915 -1.,
5916 1.,
5917 0.000000000000000007,
5918 0.000000000000000007,
5919 0.000000000000000007,
5920 0.000000000000000007,
5921 );
5922 assert_eq_m512d(r, e);
5923 }
5924
5925 #[simd_test(enable = "avx512f")]
5926 unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5927 let a = _mm512_set1_pd(0.000000000000000007);
5928 let b = _mm512_set1_pd(1.);
5929 let c = _mm512_set1_pd(-1.);
5930 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5931 0, a, b, c,
5932 );
5933 assert_eq_m512d(r, _mm512_setzero_pd());
5934 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5935 0b00001111, a, b, c,
5936 );
5937 let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5938 assert_eq_m512d(r, e);
5939 }
5940
5941 #[simd_test(enable = "avx512f")]
5942 unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5943 let a = _mm512_set1_pd(0.000000000000000007);
5944 let b = _mm512_set1_pd(1.);
5945 let c = _mm512_set1_pd(-1.);
5946 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5947 a, b, c, 0,
5948 );
5949 assert_eq_m512d(r, c);
5950 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5951 a, b, c, 0b00001111,
5952 );
5953 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5954 assert_eq_m512d(r, e);
5955 }
5956
5957 #[simd_test(enable = "avx512f")]
5958 unsafe fn test_mm512_fnmadd_round_pd() {
5959 let a = _mm512_set1_pd(0.000000000000000007);
5960 let b = _mm512_set1_pd(1.);
5961 let c = _mm512_set1_pd(1.);
5962 let r =
5963 _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5964 let e = _mm512_set1_pd(1.);
5965 assert_eq_m512d(r, e);
5966 let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5967 let e = _mm512_set1_pd(0.9999999999999999);
5968 assert_eq_m512d(r, e);
5969 }
5970
5971 #[simd_test(enable = "avx512f")]
5972 unsafe fn test_mm512_mask_fnmadd_round_pd() {
5973 let a = _mm512_set1_pd(0.000000000000000007);
5974 let b = _mm512_set1_pd(1.);
5975 let c = _mm512_set1_pd(1.);
5976 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5977 a, 0, b, c,
5978 );
5979 assert_eq_m512d(r, a);
5980 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5981 a, 0b00001111, b, c,
5982 );
5983 let e = _mm512_setr_pd(
5984 1.,
5985 1.,
5986 1.,
5987 1.,
5988 0.000000000000000007,
5989 0.000000000000000007,
5990 0.000000000000000007,
5991 0.000000000000000007,
5992 );
5993 assert_eq_m512d(r, e);
5994 }
5995
5996 #[simd_test(enable = "avx512f")]
5997 unsafe fn test_mm512_maskz_fnmadd_round_pd() {
5998 let a = _mm512_set1_pd(0.000000000000000007);
5999 let b = _mm512_set1_pd(1.);
6000 let c = _mm512_set1_pd(1.);
6001 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6002 0, a, b, c,
6003 );
6004 assert_eq_m512d(r, _mm512_setzero_pd());
6005 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6006 0b00001111, a, b, c,
6007 );
6008 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6009 assert_eq_m512d(r, e);
6010 }
6011
6012 #[simd_test(enable = "avx512f")]
6013 unsafe fn test_mm512_mask3_fnmadd_round_pd() {
6014 let a = _mm512_set1_pd(0.000000000000000007);
6015 let b = _mm512_set1_pd(1.);
6016 let c = _mm512_set1_pd(1.);
6017 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6018 a, b, c, 0,
6019 );
6020 assert_eq_m512d(r, c);
6021 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6022 a, b, c, 0b00001111,
6023 );
6024 let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
6025 assert_eq_m512d(r, e);
6026 }
6027
6028 #[simd_test(enable = "avx512f")]
6029 unsafe fn test_mm512_fnmsub_round_pd() {
6030 let a = _mm512_set1_pd(0.000000000000000007);
6031 let b = _mm512_set1_pd(1.);
6032 let c = _mm512_set1_pd(-1.);
6033 let r =
6034 _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
6035 let e = _mm512_set1_pd(1.);
6036 assert_eq_m512d(r, e);
6037 let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
6038 let e = _mm512_set1_pd(0.9999999999999999);
6039 assert_eq_m512d(r, e);
6040 }
6041
6042 #[simd_test(enable = "avx512f")]
6043 unsafe fn test_mm512_mask_fnmsub_round_pd() {
6044 let a = _mm512_set1_pd(0.000000000000000007);
6045 let b = _mm512_set1_pd(1.);
6046 let c = _mm512_set1_pd(-1.);
6047 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6048 a, 0, b, c,
6049 );
6050 assert_eq_m512d(r, a);
6051 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6052 a, 0b00001111, b, c,
6053 );
6054 let e = _mm512_setr_pd(
6055 1.,
6056 1.,
6057 1.,
6058 1.,
6059 0.000000000000000007,
6060 0.000000000000000007,
6061 0.000000000000000007,
6062 0.000000000000000007,
6063 );
6064 assert_eq_m512d(r, e);
6065 }
6066
6067 #[simd_test(enable = "avx512f")]
6068 unsafe fn test_mm512_maskz_fnmsub_round_pd() {
6069 let a = _mm512_set1_pd(0.000000000000000007);
6070 let b = _mm512_set1_pd(1.);
6071 let c = _mm512_set1_pd(-1.);
6072 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6073 0, a, b, c,
6074 );
6075 assert_eq_m512d(r, _mm512_setzero_pd());
6076 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6077 0b00001111, a, b, c,
6078 );
6079 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6080 assert_eq_m512d(r, e);
6081 }
6082
6083 #[simd_test(enable = "avx512f")]
6084 unsafe fn test_mm512_mask3_fnmsub_round_pd() {
6085 let a = _mm512_set1_pd(0.000000000000000007);
6086 let b = _mm512_set1_pd(1.);
6087 let c = _mm512_set1_pd(-1.);
6088 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6089 a, b, c, 0,
6090 );
6091 assert_eq_m512d(r, c);
6092 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6093 a, b, c, 0b00001111,
6094 );
6095 let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
6096 assert_eq_m512d(r, e);
6097 }
6098
6099 #[simd_test(enable = "avx512f")]
6100 unsafe fn test_mm512_max_round_pd() {
6101 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6102 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6103 let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6104 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6105 assert_eq_m512d(r, e);
6106 }
6107
6108 #[simd_test(enable = "avx512f")]
6109 unsafe fn test_mm512_mask_max_round_pd() {
6110 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6111 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6112 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6113 assert_eq_m512d(r, a);
6114 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6115 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6116 assert_eq_m512d(r, e);
6117 }
6118
6119 #[simd_test(enable = "avx512f")]
6120 unsafe fn test_mm512_maskz_max_round_pd() {
6121 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6122 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6123 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6124 assert_eq_m512d(r, _mm512_setzero_pd());
6125 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6126 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
6127 assert_eq_m512d(r, e);
6128 }
6129
6130 #[simd_test(enable = "avx512f")]
6131 unsafe fn test_mm512_min_round_pd() {
6132 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6133 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6134 let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6135 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
6136 assert_eq_m512d(r, e);
6137 }
6138
6139 #[simd_test(enable = "avx512f")]
6140 unsafe fn test_mm512_mask_min_round_pd() {
6141 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6142 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6143 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6144 assert_eq_m512d(r, a);
6145 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6146 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6147 assert_eq_m512d(r, e);
6148 }
6149
6150 #[simd_test(enable = "avx512f")]
6151 unsafe fn test_mm512_maskz_min_round_pd() {
6152 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6153 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6154 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6155 assert_eq_m512d(r, _mm512_setzero_pd());
6156 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6157 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6158 assert_eq_m512d(r, e);
6159 }
6160
6161 #[simd_test(enable = "avx512f")]
6162 unsafe fn test_mm512_getexp_round_pd() {
6163 let a = _mm512_set1_pd(3.);
6164 let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6165 let e = _mm512_set1_pd(1.);
6166 assert_eq_m512d(r, e);
6167 }
6168
6169 #[simd_test(enable = "avx512f")]
6170 unsafe fn test_mm512_mask_getexp_round_pd() {
6171 let a = _mm512_set1_pd(3.);
6172 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6173 assert_eq_m512d(r, a);
6174 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6175 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6176 assert_eq_m512d(r, e);
6177 }
6178
6179 #[simd_test(enable = "avx512f")]
6180 unsafe fn test_mm512_maskz_getexp_round_pd() {
6181 let a = _mm512_set1_pd(3.);
6182 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6183 assert_eq_m512d(r, _mm512_setzero_pd());
6184 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6185 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6186 assert_eq_m512d(r, e);
6187 }
6188
6189 #[simd_test(enable = "avx512f")]
6190 unsafe fn test_mm512_roundscale_round_pd() {
6191 let a = _mm512_set1_pd(1.1);
6192 let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6193 let e = _mm512_set1_pd(1.0);
6194 assert_eq_m512d(r, e);
6195 }
6196
6197 #[simd_test(enable = "avx512f")]
6198 unsafe fn test_mm512_mask_roundscale_round_pd() {
6199 let a = _mm512_set1_pd(1.1);
6200 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6201 let e = _mm512_set1_pd(1.1);
6202 assert_eq_m512d(r, e);
6203 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6204 let e = _mm512_set1_pd(1.0);
6205 assert_eq_m512d(r, e);
6206 }
6207
6208 #[simd_test(enable = "avx512f")]
6209 unsafe fn test_mm512_maskz_roundscale_round_pd() {
6210 let a = _mm512_set1_pd(1.1);
6211 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6212 assert_eq_m512d(r, _mm512_setzero_pd());
6213 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6214 let e = _mm512_set1_pd(1.0);
6215 assert_eq_m512d(r, e);
6216 }
6217
6218 #[simd_test(enable = "avx512f")]
6219 unsafe fn test_mm512_scalef_round_pd() {
6220 let a = _mm512_set1_pd(1.);
6221 let b = _mm512_set1_pd(3.);
6222 let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6223 let e = _mm512_set1_pd(8.);
6224 assert_eq_m512d(r, e);
6225 }
6226
6227 #[simd_test(enable = "avx512f")]
6228 unsafe fn test_mm512_mask_scalef_round_pd() {
6229 let a = _mm512_set1_pd(1.);
6230 let b = _mm512_set1_pd(3.);
6231 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6232 a, 0, a, b,
6233 );
6234 assert_eq_m512d(r, a);
6235 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6236 a, 0b11110000, a, b,
6237 );
6238 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6239 assert_eq_m512d(r, e);
6240 }
6241
6242 #[simd_test(enable = "avx512f")]
6243 unsafe fn test_mm512_maskz_scalef_round_pd() {
6244 let a = _mm512_set1_pd(1.);
6245 let b = _mm512_set1_pd(3.);
6246 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6247 0, a, b,
6248 );
6249 assert_eq_m512d(r, _mm512_setzero_pd());
6250 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6251 0b11110000, a, b,
6252 );
6253 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6254 assert_eq_m512d(r, e);
6255 }
6256
6257 #[simd_test(enable = "avx512f")]
6258 unsafe fn test_mm512_fixupimm_round_pd() {
6259 let a = _mm512_set1_pd(f64::NAN);
6260 let b = _mm512_set1_pd(f64::MAX);
6261 let c = _mm512_set1_epi64(i32::MAX as i64);
6262 let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6263 let e = _mm512_set1_pd(0.0);
6264 assert_eq_m512d(r, e);
6265 }
6266
6267 #[simd_test(enable = "avx512f")]
6268 unsafe fn test_mm512_mask_fixupimm_round_pd() {
6269 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6270 let b = _mm512_set1_pd(f64::MAX);
6271 let c = _mm512_set1_epi64(i32::MAX as i64);
6272 let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6273 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6274 assert_eq_m512d(r, e);
6275 }
6276
6277 #[simd_test(enable = "avx512f")]
6278 unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6279 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6280 let b = _mm512_set1_pd(f64::MAX);
6281 let c = _mm512_set1_epi64(i32::MAX as i64);
6282 let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6283 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6284 assert_eq_m512d(r, e);
6285 }
6286
6287 #[simd_test(enable = "avx512f")]
6288 unsafe fn test_mm512_getmant_round_pd() {
6289 let a = _mm512_set1_pd(10.);
6290 let r = _mm512_getmant_round_pd::<
6291 _MM_MANT_NORM_1_2,
6292 _MM_MANT_SIGN_SRC,
6293 _MM_FROUND_CUR_DIRECTION,
6294 >(a);
6295 let e = _mm512_set1_pd(1.25);
6296 assert_eq_m512d(r, e);
6297 }
6298
6299 #[simd_test(enable = "avx512f")]
6300 unsafe fn test_mm512_mask_getmant_round_pd() {
6301 let a = _mm512_set1_pd(10.);
6302 let r = _mm512_mask_getmant_round_pd::<
6303 _MM_MANT_NORM_1_2,
6304 _MM_MANT_SIGN_SRC,
6305 _MM_FROUND_CUR_DIRECTION,
6306 >(a, 0, a);
6307 assert_eq_m512d(r, a);
6308 let r = _mm512_mask_getmant_round_pd::<
6309 _MM_MANT_NORM_1_2,
6310 _MM_MANT_SIGN_SRC,
6311 _MM_FROUND_CUR_DIRECTION,
6312 >(a, 0b11110000, a);
6313 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6314 assert_eq_m512d(r, e);
6315 }
6316
6317 #[simd_test(enable = "avx512f")]
6318 unsafe fn test_mm512_maskz_getmant_round_pd() {
6319 let a = _mm512_set1_pd(10.);
6320 let r = _mm512_maskz_getmant_round_pd::<
6321 _MM_MANT_NORM_1_2,
6322 _MM_MANT_SIGN_SRC,
6323 _MM_FROUND_CUR_DIRECTION,
6324 >(0, a);
6325 assert_eq_m512d(r, _mm512_setzero_pd());
6326 let r = _mm512_maskz_getmant_round_pd::<
6327 _MM_MANT_NORM_1_2,
6328 _MM_MANT_SIGN_SRC,
6329 _MM_FROUND_CUR_DIRECTION,
6330 >(0b11110000, a);
6331 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6332 assert_eq_m512d(r, e);
6333 }
6334
6335 #[simd_test(enable = "avx512f")]
6336 unsafe fn test_mm512_cvt_roundps_pd() {
6337 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6338 let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6339 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6340 assert_eq_m512d(r, e);
6341 }
6342
6343 #[simd_test(enable = "avx512f")]
6344 unsafe fn test_mm512_mask_cvt_roundps_pd() {
6345 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6346 let src = _mm512_set1_pd(0.);
6347 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6348 assert_eq_m512d(r, src);
6349 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6350 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6351 assert_eq_m512d(r, e);
6352 }
6353
6354 #[simd_test(enable = "avx512f")]
6355 unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6356 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6357 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6358 assert_eq_m512d(r, _mm512_setzero_pd());
6359 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6360 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6361 assert_eq_m512d(r, e);
6362 }
6363
6364 #[simd_test(enable = "avx512f")]
6365 unsafe fn test_mm512_cvt_roundpd_ps() {
6366 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6367 let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6368 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6369 assert_eq_m256(r, e);
6370 }
6371
6372 #[simd_test(enable = "avx512f")]
6373 unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6374 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6375 let src = _mm256_set1_ps(0.);
6376 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6377 assert_eq_m256(r, src);
6378 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6379 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6380 assert_eq_m256(r, e);
6381 }
6382
6383 #[simd_test(enable = "avx512f")]
6384 unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6385 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6386 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6387 assert_eq_m256(r, _mm256_setzero_ps());
6388 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6389 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6390 assert_eq_m256(r, e);
6391 }
6392
6393 #[simd_test(enable = "avx512f")]
6394 unsafe fn test_mm512_cvt_roundpd_epi32() {
6395 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6396 let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6397 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6398 assert_eq_m256i(r, e);
6399 }
6400
6401 #[simd_test(enable = "avx512f")]
6402 unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6403 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6404 let src = _mm256_set1_epi32(0);
6405 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6406 assert_eq_m256i(r, src);
6407 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6408 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6409 assert_eq_m256i(r, e);
6410 }
6411
6412 #[simd_test(enable = "avx512f")]
6413 unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6414 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6415 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6416 assert_eq_m256i(r, _mm256_setzero_si256());
6417 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6418 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6419 assert_eq_m256i(r, e);
6420 }
6421
6422 #[simd_test(enable = "avx512f")]
6423 unsafe fn test_mm512_cvt_roundpd_epu32() {
6424 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6425 let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6426 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6427 assert_eq_m256i(r, e);
6428 }
6429
6430 #[simd_test(enable = "avx512f")]
6431 unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6432 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6433 let src = _mm256_set1_epi32(0);
6434 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6435 assert_eq_m256i(r, src);
6436 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6437 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6438 assert_eq_m256i(r, e);
6439 }
6440
6441 #[simd_test(enable = "avx512f")]
6442 unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6443 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6444 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6445 assert_eq_m256i(r, _mm256_setzero_si256());
6446 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6447 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6448 assert_eq_m256i(r, e);
6449 }
6450
6451 #[simd_test(enable = "avx512f")]
6452 unsafe fn test_mm512_setzero_pd() {
6453 assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6454 }
6455
6456 unsafe fn test_mm512_set1_epi64() {
6457 let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6458 assert_eq_m512i(r, _mm512_set1_epi64(2));
6459 }
6460
6461 #[simd_test(enable = "avx512f")]
6462 unsafe fn test_mm512_set1_pd() {
6463 let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6464 assert_eq_m512d(expected, _mm512_set1_pd(2.));
6465 }
6466
6467 unsafe fn test_mm512_set4_epi64() {
6468 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6469 assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6470 }
6471
6472 #[simd_test(enable = "avx512f")]
6473 unsafe fn test_mm512_set4_pd() {
6474 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6475 assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6476 }
6477
6478 unsafe fn test_mm512_setr4_epi64() {
6479 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6480 assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6481 }
6482
6483 #[simd_test(enable = "avx512f")]
6484 unsafe fn test_mm512_setr4_pd() {
6485 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6486 assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6487 }
6488
6489 #[simd_test(enable = "avx512f")]
6490 unsafe fn test_mm512_cmplt_pd_mask() {
6491 #[rustfmt::skip]
6492 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6493 let b = _mm512_set1_pd(-1.);
6494 let m = _mm512_cmplt_pd_mask(a, b);
6495 assert_eq!(m, 0b00000101);
6496 }
6497
6498 #[simd_test(enable = "avx512f")]
6499 unsafe fn test_mm512_mask_cmplt_pd_mask() {
6500 #[rustfmt::skip]
6501 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6502 let b = _mm512_set1_pd(-1.);
6503 let mask = 0b01100110;
6504 let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6505 assert_eq!(r, 0b00000100);
6506 }
6507
6508 #[simd_test(enable = "avx512f")]
6509 unsafe fn test_mm512_cmpnlt_pd_mask() {
6510 #[rustfmt::skip]
6511 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6512 let b = _mm512_set1_pd(-1.);
6513 assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6514 }
6515
6516 #[simd_test(enable = "avx512f")]
6517 unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6518 #[rustfmt::skip]
6519 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6520 let b = _mm512_set1_pd(-1.);
6521 let mask = 0b01111010;
6522 assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6523 }
6524
6525 #[simd_test(enable = "avx512f")]
6526 unsafe fn test_mm512_cmple_pd_mask() {
6527 #[rustfmt::skip]
6528 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6529 let b = _mm512_set1_pd(-1.);
6530 assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6531 }
6532
6533 #[simd_test(enable = "avx512f")]
6534 unsafe fn test_mm512_mask_cmple_pd_mask() {
6535 #[rustfmt::skip]
6536 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6537 let b = _mm512_set1_pd(-1.);
6538 let mask = 0b01111010;
6539 assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6540 }
6541
6542 #[simd_test(enable = "avx512f")]
6543 unsafe fn test_mm512_cmpnle_pd_mask() {
6544 #[rustfmt::skip]
6545 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6546 let b = _mm512_set1_pd(-1.);
6547 let m = _mm512_cmpnle_pd_mask(b, a);
6548 assert_eq!(m, 0b00001101);
6549 }
6550
6551 #[simd_test(enable = "avx512f")]
6552 unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6553 #[rustfmt::skip]
6554 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6555 let b = _mm512_set1_pd(-1.);
6556 let mask = 0b01100110;
6557 let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6558 assert_eq!(r, 0b00000100);
6559 }
6560
6561 #[simd_test(enable = "avx512f")]
6562 unsafe fn test_mm512_cmpeq_pd_mask() {
6563 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6564 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6565 let m = _mm512_cmpeq_pd_mask(b, a);
6566 assert_eq!(m, 0b11001101);
6567 }
6568
6569 #[simd_test(enable = "avx512f")]
6570 unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6571 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6572 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6573 let mask = 0b01111010;
6574 let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6575 assert_eq!(r, 0b01001000);
6576 }
6577
6578 #[simd_test(enable = "avx512f")]
6579 unsafe fn test_mm512_cmpneq_pd_mask() {
6580 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6581 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6582 let m = _mm512_cmpneq_pd_mask(b, a);
6583 assert_eq!(m, 0b00110010);
6584 }
6585
6586 #[simd_test(enable = "avx512f")]
6587 unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6588 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6589 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6590 let mask = 0b01111010;
6591 let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6592 assert_eq!(r, 0b00110010)
6593 }
6594
6595 #[simd_test(enable = "avx512f")]
6596 unsafe fn test_mm512_cmp_pd_mask() {
6597 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6598 let b = _mm512_set1_pd(-1.);
6599 let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6600 assert_eq!(m, 0b00000101);
6601 }
6602
6603 #[simd_test(enable = "avx512f")]
6604 unsafe fn test_mm512_mask_cmp_pd_mask() {
6605 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6606 let b = _mm512_set1_pd(-1.);
6607 let mask = 0b01100110;
6608 let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6609 assert_eq!(r, 0b00000100);
6610 }
6611
6612 #[simd_test(enable = "avx512f,avx512vl")]
6613 unsafe fn test_mm256_cmp_pd_mask() {
6614 let a = _mm256_set_pd(0., 1., -1., 13.);
6615 let b = _mm256_set1_pd(1.);
6616 let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6617 assert_eq!(m, 0b00001010);
6618 }
6619
6620 #[simd_test(enable = "avx512f,avx512vl")]
6621 unsafe fn test_mm256_mask_cmp_pd_mask() {
6622 let a = _mm256_set_pd(0., 1., -1., 13.);
6623 let b = _mm256_set1_pd(1.);
6624 let mask = 0b11111111;
6625 let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6626 assert_eq!(r, 0b00001010);
6627 }
6628
6629 #[simd_test(enable = "avx512f,avx512vl")]
6630 unsafe fn test_mm_cmp_pd_mask() {
6631 let a = _mm_set_pd(0., 1.);
6632 let b = _mm_set1_pd(1.);
6633 let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6634 assert_eq!(m, 0b00000010);
6635 }
6636
6637 #[simd_test(enable = "avx512f,avx512vl")]
6638 unsafe fn test_mm_mask_cmp_pd_mask() {
6639 let a = _mm_set_pd(0., 1.);
6640 let b = _mm_set1_pd(1.);
6641 let mask = 0b11111111;
6642 let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6643 assert_eq!(r, 0b00000010);
6644 }
6645
6646 #[simd_test(enable = "avx512f")]
6647 unsafe fn test_mm512_cmp_round_pd_mask() {
6648 #[rustfmt::skip]
6649 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6650 let b = _mm512_set1_pd(-1.);
6651 let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6652 assert_eq!(m, 0b00000101);
6653 }
6654
6655 #[simd_test(enable = "avx512f")]
6656 unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6657 #[rustfmt::skip]
6658 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6659 let b = _mm512_set1_pd(-1.);
6660 let mask = 0b01100110;
6661 let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6662 assert_eq!(r, 0b00000100);
6663 }
6664
6665 #[simd_test(enable = "avx512f")]
6666 unsafe fn test_mm512_cmpord_pd_mask() {
6667 #[rustfmt::skip]
6668 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6669 #[rustfmt::skip]
6670 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6671 let m = _mm512_cmpord_pd_mask(a, b);
6672 assert_eq!(m, 0b00000101);
6673 }
6674
6675 #[simd_test(enable = "avx512f")]
6676 unsafe fn test_mm512_mask_cmpord_pd_mask() {
6677 #[rustfmt::skip]
6678 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6679 #[rustfmt::skip]
6680 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6681 let mask = 0b11000011;
6682 let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6683 assert_eq!(m, 0b00000001);
6684 }
6685
6686 #[simd_test(enable = "avx512f")]
6687 unsafe fn test_mm512_cmpunord_pd_mask() {
6688 #[rustfmt::skip]
6689 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6690 #[rustfmt::skip]
6691 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6692 let m = _mm512_cmpunord_pd_mask(a, b);
6693
6694 assert_eq!(m, 0b11111010);
6695 }
6696
6697 #[simd_test(enable = "avx512f")]
6698 unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6699 #[rustfmt::skip]
6700 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6701 #[rustfmt::skip]
6702 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6703 let mask = 0b00001111;
6704 let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6705 assert_eq!(m, 0b000001010);
6706 }
6707
6708 #[simd_test(enable = "avx512f")]
6709 unsafe fn test_mm512_cmplt_epu64_mask() {
6710 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6711 let b = _mm512_set1_epi64(-1);
6712 let m = _mm512_cmplt_epu64_mask(a, b);
6713 assert_eq!(m, 0b11001111);
6714 }
6715
6716 #[simd_test(enable = "avx512f")]
6717 unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6718 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6719 let b = _mm512_set1_epi64(-1);
6720 let mask = 0b01111010;
6721 let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6722 assert_eq!(r, 0b01001010);
6723 }
6724
6725 #[simd_test(enable = "avx512f,avx512vl")]
6726 unsafe fn test_mm256_cmplt_epu64_mask() {
6727 let a = _mm256_set_epi64x(0, 1, 2, 100);
6728 let b = _mm256_set1_epi64x(2);
6729 let r = _mm256_cmplt_epu64_mask(a, b);
6730 assert_eq!(r, 0b00001100);
6731 }
6732
6733 #[simd_test(enable = "avx512f,avx512vl")]
6734 unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6735 let a = _mm256_set_epi64x(0, 1, 2, 100);
6736 let b = _mm256_set1_epi64x(2);
6737 let mask = 0b11111111;
6738 let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6739 assert_eq!(r, 0b00001100);
6740 }
6741
6742 #[simd_test(enable = "avx512f,avx512vl")]
6743 unsafe fn test_mm_cmplt_epu64_mask() {
6744 let a = _mm_set_epi64x(0, 1);
6745 let b = _mm_set1_epi64x(2);
6746 let r = _mm_cmplt_epu64_mask(a, b);
6747 assert_eq!(r, 0b00000011);
6748 }
6749
6750 #[simd_test(enable = "avx512f,avx512vl")]
6751 unsafe fn test_mm_mask_cmplt_epu64_mask() {
6752 let a = _mm_set_epi64x(0, 1);
6753 let b = _mm_set1_epi64x(2);
6754 let mask = 0b11111111;
6755 let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6756 assert_eq!(r, 0b00000011);
6757 }
6758
6759 #[simd_test(enable = "avx512f")]
6760 unsafe fn test_mm512_cmpgt_epu64_mask() {
6761 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6762 let b = _mm512_set1_epi64(-1);
6763 let m = _mm512_cmpgt_epu64_mask(b, a);
6764 assert_eq!(m, 0b11001111);
6765 }
6766
6767 #[simd_test(enable = "avx512f")]
6768 unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6769 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6770 let b = _mm512_set1_epi64(-1);
6771 let mask = 0b01111010;
6772 let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6773 assert_eq!(r, 0b01001010);
6774 }
6775
6776 #[simd_test(enable = "avx512f,avx512vl")]
6777 unsafe fn test_mm256_cmpgt_epu64_mask() {
6778 let a = _mm256_set_epi64x(0, 1, 2, 3);
6779 let b = _mm256_set1_epi64x(1);
6780 let r = _mm256_cmpgt_epu64_mask(a, b);
6781 assert_eq!(r, 0b00000011);
6782 }
6783
6784 #[simd_test(enable = "avx512f,avx512vl")]
6785 unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6786 let a = _mm256_set_epi64x(0, 1, 2, 3);
6787 let b = _mm256_set1_epi64x(1);
6788 let mask = 0b11111111;
6789 let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6790 assert_eq!(r, 0b00000011);
6791 }
6792
6793 #[simd_test(enable = "avx512f,avx512vl")]
6794 unsafe fn test_mm_cmpgt_epu64_mask() {
6795 let a = _mm_set_epi64x(1, 2);
6796 let b = _mm_set1_epi64x(1);
6797 let r = _mm_cmpgt_epu64_mask(a, b);
6798 assert_eq!(r, 0b00000001);
6799 }
6800
6801 #[simd_test(enable = "avx512f,avx512vl")]
6802 unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6803 let a = _mm_set_epi64x(1, 2);
6804 let b = _mm_set1_epi64x(1);
6805 let mask = 0b11111111;
6806 let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6807 assert_eq!(r, 0b00000001);
6808 }
6809
6810 #[simd_test(enable = "avx512f")]
6811 unsafe fn test_mm512_cmple_epu64_mask() {
6812 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6813 let b = _mm512_set1_epi64(-1);
6814 assert_eq!(
6815 _mm512_cmple_epu64_mask(a, b),
6816 !_mm512_cmpgt_epu64_mask(a, b)
6817 )
6818 }
6819
6820 #[simd_test(enable = "avx512f")]
6821 unsafe fn test_mm512_mask_cmple_epu64_mask() {
6822 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6823 let b = _mm512_set1_epi64(-1);
6824 let mask = 0b01111010;
6825 assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6826 }
6827
6828 #[simd_test(enable = "avx512f,avx512vl")]
6829 unsafe fn test_mm256_cmple_epu64_mask() {
6830 let a = _mm256_set_epi64x(0, 1, 2, 1);
6831 let b = _mm256_set1_epi64x(1);
6832 let r = _mm256_cmple_epu64_mask(a, b);
6833 assert_eq!(r, 0b00001101)
6834 }
6835
6836 #[simd_test(enable = "avx512f,avx512vl")]
6837 unsafe fn test_mm256_mask_cmple_epu64_mask() {
6838 let a = _mm256_set_epi64x(0, 1, 2, 1);
6839 let b = _mm256_set1_epi64x(1);
6840 let mask = 0b11111111;
6841 let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6842 assert_eq!(r, 0b00001101)
6843 }
6844
6845 #[simd_test(enable = "avx512f,avx512vl")]
6846 unsafe fn test_mm_cmple_epu64_mask() {
6847 let a = _mm_set_epi64x(0, 1);
6848 let b = _mm_set1_epi64x(1);
6849 let r = _mm_cmple_epu64_mask(a, b);
6850 assert_eq!(r, 0b00000011)
6851 }
6852
6853 #[simd_test(enable = "avx512f,avx512vl")]
6854 unsafe fn test_mm_mask_cmple_epu64_mask() {
6855 let a = _mm_set_epi64x(0, 1);
6856 let b = _mm_set1_epi64x(1);
6857 let mask = 0b11111111;
6858 let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6859 assert_eq!(r, 0b00000011)
6860 }
6861
6862 #[simd_test(enable = "avx512f")]
6863 unsafe fn test_mm512_cmpge_epu64_mask() {
6864 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6865 let b = _mm512_set1_epi64(-1);
6866 assert_eq!(
6867 _mm512_cmpge_epu64_mask(a, b),
6868 !_mm512_cmplt_epu64_mask(a, b)
6869 );
6870 }
6871
6872 #[simd_test(enable = "avx512f")]
6873 unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6874 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6875 let b = _mm512_set1_epi64(-1);
6876 let mask = 0b11111111;
6877 let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6878 assert_eq!(r, 0b00110000);
6879 }
6880
6881 #[simd_test(enable = "avx512f,avx512vl")]
6882 unsafe fn test_mm256_cmpge_epu64_mask() {
6883 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6884 let b = _mm256_set1_epi64x(1);
6885 let r = _mm256_cmpge_epu64_mask(a, b);
6886 assert_eq!(r, 0b00000111);
6887 }
6888
6889 #[simd_test(enable = "avx512f,avx512vl")]
6890 unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6891 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6892 let b = _mm256_set1_epi64x(1);
6893 let mask = 0b11111111;
6894 let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6895 assert_eq!(r, 0b00000111);
6896 }
6897
6898 #[simd_test(enable = "avx512f,avx512vl")]
6899 unsafe fn test_mm_cmpge_epu64_mask() {
6900 let a = _mm_set_epi64x(0, 1);
6901 let b = _mm_set1_epi64x(1);
6902 let r = _mm_cmpge_epu64_mask(a, b);
6903 assert_eq!(r, 0b00000001);
6904 }
6905
6906 #[simd_test(enable = "avx512f,avx512vl")]
6907 unsafe fn test_mm_mask_cmpge_epu64_mask() {
6908 let a = _mm_set_epi64x(0, 1);
6909 let b = _mm_set1_epi64x(1);
6910 let mask = 0b11111111;
6911 let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6912 assert_eq!(r, 0b00000001);
6913 }
6914
6915 #[simd_test(enable = "avx512f")]
6916 unsafe fn test_mm512_cmpeq_epu64_mask() {
6917 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6918 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6919 let m = _mm512_cmpeq_epu64_mask(b, a);
6920 assert_eq!(m, 0b11001111);
6921 }
6922
6923 #[simd_test(enable = "avx512f")]
6924 unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6925 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6926 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6927 let mask = 0b01111010;
6928 let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6929 assert_eq!(r, 0b01001010);
6930 }
6931
6932 #[simd_test(enable = "avx512f,avx512vl")]
6933 unsafe fn test_mm256_cmpeq_epu64_mask() {
6934 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6935 let b = _mm256_set_epi64x(0, 1, 13, 42);
6936 let m = _mm256_cmpeq_epu64_mask(b, a);
6937 assert_eq!(m, 0b00001100);
6938 }
6939
6940 #[simd_test(enable = "avx512f,avx512vl")]
6941 unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6942 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6943 let b = _mm256_set_epi64x(0, 1, 13, 42);
6944 let mask = 0b11111111;
6945 let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6946 assert_eq!(r, 0b00001100);
6947 }
6948
6949 #[simd_test(enable = "avx512f,avx512vl")]
6950 unsafe fn test_mm_cmpeq_epu64_mask() {
6951 let a = _mm_set_epi64x(0, 1);
6952 let b = _mm_set_epi64x(0, 1);
6953 let m = _mm_cmpeq_epu64_mask(b, a);
6954 assert_eq!(m, 0b00000011);
6955 }
6956
6957 #[simd_test(enable = "avx512f,avx512vl")]
6958 unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6959 let a = _mm_set_epi64x(0, 1);
6960 let b = _mm_set_epi64x(0, 1);
6961 let mask = 0b11111111;
6962 let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6963 assert_eq!(r, 0b00000011);
6964 }
6965
6966 #[simd_test(enable = "avx512f")]
6967 unsafe fn test_mm512_cmpneq_epu64_mask() {
6968 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6969 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6970 let m = _mm512_cmpneq_epu64_mask(b, a);
6971 assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6972 }
6973
6974 #[simd_test(enable = "avx512f")]
6975 unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6976 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6977 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6978 let mask = 0b01111010;
6979 let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6980 assert_eq!(r, 0b00110010);
6981 }
6982
6983 #[simd_test(enable = "avx512f,avx512vl")]
6984 unsafe fn test_mm256_cmpneq_epu64_mask() {
6985 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6986 let b = _mm256_set_epi64x(0, 1, 13, 42);
6987 let r = _mm256_cmpneq_epu64_mask(b, a);
6988 assert_eq!(r, 0b00000011);
6989 }
6990
6991 #[simd_test(enable = "avx512f,avx512vl")]
6992 unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
6993 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6994 let b = _mm256_set_epi64x(0, 1, 13, 42);
6995 let mask = 0b11111111;
6996 let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
6997 assert_eq!(r, 0b00000011);
6998 }
6999
7000 #[simd_test(enable = "avx512f,avx512vl")]
7001 unsafe fn test_mm_cmpneq_epu64_mask() {
7002 let a = _mm_set_epi64x(-1, u64::MAX as i64);
7003 let b = _mm_set_epi64x(13, 42);
7004 let r = _mm_cmpneq_epu64_mask(b, a);
7005 assert_eq!(r, 0b00000011);
7006 }
7007
7008 #[simd_test(enable = "avx512f,avx512vl")]
7009 unsafe fn test_mm_mask_cmpneq_epu64_mask() {
7010 let a = _mm_set_epi64x(-1, u64::MAX as i64);
7011 let b = _mm_set_epi64x(13, 42);
7012 let mask = 0b11111111;
7013 let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
7014 assert_eq!(r, 0b00000011);
7015 }
7016
7017 #[simd_test(enable = "avx512f")]
7018 unsafe fn test_mm512_cmp_epu64_mask() {
7019 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7020 let b = _mm512_set1_epi64(-1);
7021 let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7022 assert_eq!(m, 0b11001111);
7023 }
7024
7025 #[simd_test(enable = "avx512f")]
7026 unsafe fn test_mm512_mask_cmp_epu64_mask() {
7027 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7028 let b = _mm512_set1_epi64(-1);
7029 let mask = 0b01111010;
7030 let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7031 assert_eq!(r, 0b01001010);
7032 }
7033
7034 #[simd_test(enable = "avx512f,avx512vl")]
7035 unsafe fn test_mm256_cmp_epu64_mask() {
7036 let a = _mm256_set_epi64x(0, 1, -1, 100);
7037 let b = _mm256_set1_epi64x(1);
7038 let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7039 assert_eq!(m, 0b00001000);
7040 }
7041
7042 #[simd_test(enable = "avx512f,avx512vl")]
7043 unsafe fn test_mm256_mask_cmp_epu64_mask() {
7044 let a = _mm256_set_epi64x(0, 1, -1, 100);
7045 let b = _mm256_set1_epi64x(1);
7046 let mask = 0b11111111;
7047 let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7048 assert_eq!(r, 0b00001000);
7049 }
7050
7051 #[simd_test(enable = "avx512f,avx512vl")]
7052 unsafe fn test_mm_cmp_epu64_mask() {
7053 let a = _mm_set_epi64x(0, 1);
7054 let b = _mm_set1_epi64x(1);
7055 let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7056 assert_eq!(m, 0b00000010);
7057 }
7058
7059 #[simd_test(enable = "avx512f,avx512vl")]
7060 unsafe fn test_mm_mask_cmp_epu64_mask() {
7061 let a = _mm_set_epi64x(0, 1);
7062 let b = _mm_set1_epi64x(1);
7063 let mask = 0b11111111;
7064 let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7065 assert_eq!(r, 0b00000010);
7066 }
7067
7068 #[simd_test(enable = "avx512f")]
7069 unsafe fn test_mm512_cmplt_epi64_mask() {
7070 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7071 let b = _mm512_set1_epi64(-1);
7072 let m = _mm512_cmplt_epi64_mask(a, b);
7073 assert_eq!(m, 0b00000101);
7074 }
7075
7076 #[simd_test(enable = "avx512f")]
7077 unsafe fn test_mm512_mask_cmplt_epi64_mask() {
7078 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7079 let b = _mm512_set1_epi64(-1);
7080 let mask = 0b01100110;
7081 let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
7082 assert_eq!(r, 0b00000100);
7083 }
7084
7085 #[simd_test(enable = "avx512f,avx512vl")]
7086 unsafe fn test_mm256_cmplt_epi64_mask() {
7087 let a = _mm256_set_epi64x(0, 1, -1, -13);
7088 let b = _mm256_set1_epi64x(-1);
7089 let r = _mm256_cmplt_epi64_mask(a, b);
7090 assert_eq!(r, 0b00000001);
7091 }
7092
7093 #[simd_test(enable = "avx512f,avx512vl")]
7094 unsafe fn test_mm256_mask_cmplt_epi64_mask() {
7095 let a = _mm256_set_epi64x(0, 1, -1, -13);
7096 let b = _mm256_set1_epi64x(-1);
7097 let mask = 0b11111111;
7098 let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
7099 assert_eq!(r, 0b00000001);
7100 }
7101
7102 #[simd_test(enable = "avx512f,avx512vl")]
7103 unsafe fn test_mm_cmplt_epi64_mask() {
7104 let a = _mm_set_epi64x(-1, -13);
7105 let b = _mm_set1_epi64x(-1);
7106 let r = _mm_cmplt_epi64_mask(a, b);
7107 assert_eq!(r, 0b00000001);
7108 }
7109
7110 #[simd_test(enable = "avx512f,avx512vl")]
7111 unsafe fn test_mm_mask_cmplt_epi64_mask() {
7112 let a = _mm_set_epi64x(-1, -13);
7113 let b = _mm_set1_epi64x(-1);
7114 let mask = 0b11111111;
7115 let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
7116 assert_eq!(r, 0b00000001);
7117 }
7118
7119 #[simd_test(enable = "avx512f")]
7120 unsafe fn test_mm512_cmpgt_epi64_mask() {
7121 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7122 let b = _mm512_set1_epi64(-1);
7123 let m = _mm512_cmpgt_epi64_mask(b, a);
7124 assert_eq!(m, 0b00000101);
7125 }
7126
7127 #[simd_test(enable = "avx512f")]
7128 unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
7129 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7130 let b = _mm512_set1_epi64(-1);
7131 let mask = 0b01100110;
7132 let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
7133 assert_eq!(r, 0b00000100);
7134 }
7135
7136 #[simd_test(enable = "avx512f,avx512vl")]
7137 unsafe fn test_mm256_cmpgt_epi64_mask() {
7138 let a = _mm256_set_epi64x(0, 1, -1, 13);
7139 let b = _mm256_set1_epi64x(-1);
7140 let r = _mm256_cmpgt_epi64_mask(a, b);
7141 assert_eq!(r, 0b00001101);
7142 }
7143
7144 #[simd_test(enable = "avx512f,avx512vl")]
7145 unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
7146 let a = _mm256_set_epi64x(0, 1, -1, 13);
7147 let b = _mm256_set1_epi64x(-1);
7148 let mask = 0b11111111;
7149 let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7150 assert_eq!(r, 0b00001101);
7151 }
7152
7153 #[simd_test(enable = "avx512f,avx512vl")]
7154 unsafe fn test_mm_cmpgt_epi64_mask() {
7155 let a = _mm_set_epi64x(0, -1);
7156 let b = _mm_set1_epi64x(-1);
7157 let r = _mm_cmpgt_epi64_mask(a, b);
7158 assert_eq!(r, 0b00000010);
7159 }
7160
7161 #[simd_test(enable = "avx512f,avx512vl")]
7162 unsafe fn test_mm_mask_cmpgt_epi64_mask() {
7163 let a = _mm_set_epi64x(0, -1);
7164 let b = _mm_set1_epi64x(-1);
7165 let mask = 0b11111111;
7166 let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7167 assert_eq!(r, 0b00000010);
7168 }
7169
7170 #[simd_test(enable = "avx512f")]
7171 unsafe fn test_mm512_cmple_epi64_mask() {
7172 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7173 let b = _mm512_set1_epi64(-1);
7174 assert_eq!(
7175 _mm512_cmple_epi64_mask(a, b),
7176 !_mm512_cmpgt_epi64_mask(a, b)
7177 )
7178 }
7179
7180 #[simd_test(enable = "avx512f")]
7181 unsafe fn test_mm512_mask_cmple_epi64_mask() {
7182 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7183 let b = _mm512_set1_epi64(-1);
7184 let mask = 0b01111010;
7185 assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7186 }
7187
7188 #[simd_test(enable = "avx512f,avx512vl")]
7189 unsafe fn test_mm256_cmple_epi64_mask() {
7190 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7191 let b = _mm256_set1_epi64x(-1);
7192 let r = _mm256_cmple_epi64_mask(a, b);
7193 assert_eq!(r, 0b00000010)
7194 }
7195
7196 #[simd_test(enable = "avx512f,avx512vl")]
7197 unsafe fn test_mm256_mask_cmple_epi64_mask() {
7198 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7199 let b = _mm256_set1_epi64x(-1);
7200 let mask = 0b11111111;
7201 let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7202 assert_eq!(r, 0b00000010)
7203 }
7204
7205 #[simd_test(enable = "avx512f,avx512vl")]
7206 unsafe fn test_mm_cmple_epi64_mask() {
7207 let a = _mm_set_epi64x(0, 1);
7208 let b = _mm_set1_epi64x(1);
7209 let r = _mm_cmple_epi64_mask(a, b);
7210 assert_eq!(r, 0b00000011)
7211 }
7212
7213 #[simd_test(enable = "avx512f,avx512vl")]
7214 unsafe fn test_mm_mask_cmple_epi64_mask() {
7215 let a = _mm_set_epi64x(0, 1);
7216 let b = _mm_set1_epi64x(1);
7217 let mask = 0b11111111;
7218 let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7219 assert_eq!(r, 0b00000011)
7220 }
7221
7222 #[simd_test(enable = "avx512f")]
7223 unsafe fn test_mm512_cmpge_epi64_mask() {
7224 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7225 let b = _mm512_set1_epi64(-1);
7226 assert_eq!(
7227 _mm512_cmpge_epi64_mask(a, b),
7228 !_mm512_cmplt_epi64_mask(a, b)
7229 )
7230 }
7231
7232 #[simd_test(enable = "avx512f")]
7233 unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7234 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7235 let b = _mm512_set1_epi64(-1);
7236 let mask = 0b11111111;
7237 let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7238 assert_eq!(r, 0b11111010);
7239 }
7240
7241 #[simd_test(enable = "avx512f,avx512vl")]
7242 unsafe fn test_mm256_cmpge_epi64_mask() {
7243 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7244 let b = _mm256_set1_epi64x(-1);
7245 let r = _mm256_cmpge_epi64_mask(a, b);
7246 assert_eq!(r, 0b00001111);
7247 }
7248
7249 #[simd_test(enable = "avx512f,avx512vl")]
7250 unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7251 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7252 let b = _mm256_set1_epi64x(-1);
7253 let mask = 0b11111111;
7254 let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7255 assert_eq!(r, 0b00001111);
7256 }
7257
7258 #[simd_test(enable = "avx512f,avx512vl")]
7259 unsafe fn test_mm_cmpge_epi64_mask() {
7260 let a = _mm_set_epi64x(0, 1);
7261 let b = _mm_set1_epi64x(-1);
7262 let r = _mm_cmpge_epi64_mask(a, b);
7263 assert_eq!(r, 0b00000011);
7264 }
7265
7266 #[simd_test(enable = "avx512f,avx512vl")]
7267 unsafe fn test_mm_mask_cmpge_epi64_mask() {
7268 let a = _mm_set_epi64x(0, 1);
7269 let b = _mm_set1_epi64x(-1);
7270 let mask = 0b11111111;
7271 let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7272 assert_eq!(r, 0b00000011);
7273 }
7274
7275 #[simd_test(enable = "avx512f")]
7276 unsafe fn test_mm512_cmpeq_epi64_mask() {
7277 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7278 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7279 let m = _mm512_cmpeq_epi64_mask(b, a);
7280 assert_eq!(m, 0b11001111);
7281 }
7282
7283 #[simd_test(enable = "avx512f")]
7284 unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7285 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7286 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7287 let mask = 0b01111010;
7288 let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7289 assert_eq!(r, 0b01001010);
7290 }
7291
7292 #[simd_test(enable = "avx512f,avx512vl")]
7293 unsafe fn test_mm256_cmpeq_epi64_mask() {
7294 let a = _mm256_set_epi64x(0, 1, -1, 13);
7295 let b = _mm256_set_epi64x(0, 1, 13, 42);
7296 let m = _mm256_cmpeq_epi64_mask(b, a);
7297 assert_eq!(m, 0b00001100);
7298 }
7299
7300 #[simd_test(enable = "avx512f,avx512vl")]
7301 unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7302 let a = _mm256_set_epi64x(0, 1, -1, 13);
7303 let b = _mm256_set_epi64x(0, 1, 13, 42);
7304 let mask = 0b11111111;
7305 let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7306 assert_eq!(r, 0b00001100);
7307 }
7308
7309 #[simd_test(enable = "avx512f,avx512vl")]
7310 unsafe fn test_mm_cmpeq_epi64_mask() {
7311 let a = _mm_set_epi64x(0, 1);
7312 let b = _mm_set_epi64x(0, 1);
7313 let m = _mm_cmpeq_epi64_mask(b, a);
7314 assert_eq!(m, 0b00000011);
7315 }
7316
7317 #[simd_test(enable = "avx512f,avx512vl")]
7318 unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7319 let a = _mm_set_epi64x(0, 1);
7320 let b = _mm_set_epi64x(0, 1);
7321 let mask = 0b11111111;
7322 let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7323 assert_eq!(r, 0b00000011);
7324 }
7325
7326 #[simd_test(enable = "avx512f")]
7327 unsafe fn test_mm512_set_epi64() {
7328 let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7329 assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7330 }
7331
7332 #[simd_test(enable = "avx512f")]
7333 unsafe fn test_mm512_setr_epi64() {
7334 let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7335 assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7336 }
7337
7338 unsafe fn test_mm512_cmpneq_epi64_mask() {
7339 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7340 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7341 let m = _mm512_cmpneq_epi64_mask(b, a);
7342 assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7343 }
7344
7345 #[simd_test(enable = "avx512f")]
7346 unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7347 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7348 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7349 let mask = 0b01111010;
7350 let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7351 assert_eq!(r, 0b00110010)
7352 }
7353
7354 #[simd_test(enable = "avx512f,avx512vl")]
7355 unsafe fn test_mm256_cmpneq_epi64_mask() {
7356 let a = _mm256_set_epi64x(0, 1, -1, 13);
7357 let b = _mm256_set_epi64x(0, 1, 13, 42);
7358 let r = _mm256_cmpneq_epi64_mask(b, a);
7359 assert_eq!(r, 0b00000011)
7360 }
7361
7362 #[simd_test(enable = "avx512f,avx512vl")]
7363 unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7364 let a = _mm256_set_epi64x(0, 1, -1, 13);
7365 let b = _mm256_set_epi64x(0, 1, 13, 42);
7366 let mask = 0b11111111;
7367 let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7368 assert_eq!(r, 0b00000011)
7369 }
7370
7371 #[simd_test(enable = "avx512f,avx512vl")]
7372 unsafe fn test_mm_cmpneq_epi64_mask() {
7373 let a = _mm_set_epi64x(-1, 13);
7374 let b = _mm_set_epi64x(13, 42);
7375 let r = _mm_cmpneq_epi64_mask(b, a);
7376 assert_eq!(r, 0b00000011)
7377 }
7378
7379 #[simd_test(enable = "avx512f,avx512vl")]
7380 unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7381 let a = _mm_set_epi64x(-1, 13);
7382 let b = _mm_set_epi64x(13, 42);
7383 let mask = 0b11111111;
7384 let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7385 assert_eq!(r, 0b00000011)
7386 }
7387
7388 #[simd_test(enable = "avx512f")]
7389 unsafe fn test_mm512_cmp_epi64_mask() {
7390 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7391 let b = _mm512_set1_epi64(-1);
7392 let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7393 assert_eq!(m, 0b00000101);
7394 }
7395
7396 #[simd_test(enable = "avx512f")]
7397 unsafe fn test_mm512_mask_cmp_epi64_mask() {
7398 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7399 let b = _mm512_set1_epi64(-1);
7400 let mask = 0b01100110;
7401 let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7402 assert_eq!(r, 0b00000100);
7403 }
7404
7405 #[simd_test(enable = "avx512f,avx512vl")]
7406 unsafe fn test_mm256_cmp_epi64_mask() {
7407 let a = _mm256_set_epi64x(0, 1, -1, 13);
7408 let b = _mm256_set1_epi64x(1);
7409 let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7410 assert_eq!(m, 0b00001010);
7411 }
7412
7413 #[simd_test(enable = "avx512f,avx512vl")]
7414 unsafe fn test_mm256_mask_cmp_epi64_mask() {
7415 let a = _mm256_set_epi64x(0, 1, -1, 13);
7416 let b = _mm256_set1_epi64x(1);
7417 let mask = 0b11111111;
7418 let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7419 assert_eq!(r, 0b00001010);
7420 }
7421
7422 #[simd_test(enable = "avx512f,avx512vl")]
7423 unsafe fn test_mm_cmp_epi64_mask() {
7424 let a = _mm_set_epi64x(0, 1);
7425 let b = _mm_set1_epi64x(1);
7426 let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7427 assert_eq!(m, 0b00000010);
7428 }
7429
7430 #[simd_test(enable = "avx512f,avx512vl")]
7431 unsafe fn test_mm_mask_cmp_epi64_mask() {
7432 let a = _mm_set_epi64x(0, 1);
7433 let b = _mm_set1_epi64x(1);
7434 let mask = 0b11111111;
7435 let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7436 assert_eq!(r, 0b00000010);
7437 }
7438
7439 #[simd_test(enable = "avx512f")]
7440 unsafe fn test_mm512_i32gather_pd() {
7441 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7442 // A multiplier of 8 is word-addressing
7443 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7444 let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr());
7445 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7446 }
7447
7448 #[simd_test(enable = "avx512f")]
7449 unsafe fn test_mm512_mask_i32gather_pd() {
7450 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7451 let src = _mm512_set1_pd(2.);
7452 let mask = 0b10101010;
7453 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7454 // A multiplier of 8 is word-addressing
7455 let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr());
7456 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7457 }
7458
7459 #[simd_test(enable = "avx512f")]
7460 unsafe fn test_mm512_i64gather_pd() {
7461 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7462 // A multiplier of 8 is word-addressing
7463 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7464 let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr());
7465 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7466 }
7467
7468 #[simd_test(enable = "avx512f")]
7469 unsafe fn test_mm512_mask_i64gather_pd() {
7470 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7471 let src = _mm512_set1_pd(2.);
7472 let mask = 0b10101010;
7473 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7474 // A multiplier of 8 is word-addressing
7475 let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr());
7476 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7477 }
7478
7479 #[simd_test(enable = "avx512f")]
7480 unsafe fn test_mm512_i64gather_ps() {
7481 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7482 // A multiplier of 4 is word-addressing
7483 #[rustfmt::skip]
7484 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7485 let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr());
7486 assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7487 }
7488
7489 #[simd_test(enable = "avx512f")]
7490 unsafe fn test_mm512_mask_i64gather_ps() {
7491 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7492 let src = _mm256_set1_ps(2.);
7493 let mask = 0b10101010;
7494 #[rustfmt::skip]
7495 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7496 // A multiplier of 4 is word-addressing
7497 let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr());
7498 assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7499 }
7500
7501 #[simd_test(enable = "avx512f")]
7502 unsafe fn test_mm512_i32gather_epi64() {
7503 let mut arr = [0i64; 128];
7504 for i in 0..128i64 {
7505 arr[i as usize] = i;
7506 }
7507 // A multiplier of 8 is word-addressing
7508 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7509 let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr());
7510 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7511 }
7512
7513 #[simd_test(enable = "avx512f")]
7514 unsafe fn test_mm512_mask_i32gather_epi64() {
7515 let mut arr = [0i64; 128];
7516 for i in 0..128i64 {
7517 arr[i as usize] = i;
7518 }
7519 let src = _mm512_set1_epi64(2);
7520 let mask = 0b10101010;
7521 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7522 // A multiplier of 8 is word-addressing
7523 let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr());
7524 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7525 }
7526
7527 #[simd_test(enable = "avx512f")]
7528 unsafe fn test_mm512_i64gather_epi64() {
7529 let mut arr = [0i64; 128];
7530 for i in 0..128i64 {
7531 arr[i as usize] = i;
7532 }
7533 // A multiplier of 8 is word-addressing
7534 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7535 let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr());
7536 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7537 }
7538
7539 #[simd_test(enable = "avx512f")]
7540 unsafe fn test_mm512_mask_i64gather_epi64() {
7541 let mut arr = [0i64; 128];
7542 for i in 0..128i64 {
7543 arr[i as usize] = i;
7544 }
7545 let src = _mm512_set1_epi64(2);
7546 let mask = 0b10101010;
7547 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7548 // A multiplier of 8 is word-addressing
7549 let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr());
7550 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7551 }
7552
7553 #[simd_test(enable = "avx512f")]
7554 unsafe fn test_mm512_i64gather_epi32() {
7555 let mut arr = [0i64; 128];
7556 for i in 0..128i64 {
7557 arr[i as usize] = i;
7558 }
7559 // A multiplier of 8 is word-addressing
7560 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7561 let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32);
7562 assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7563 }
7564
7565 #[simd_test(enable = "avx512f")]
7566 unsafe fn test_mm512_mask_i64gather_epi32() {
7567 let mut arr = [0i64; 128];
7568 for i in 0..128i64 {
7569 arr[i as usize] = i;
7570 }
7571 let src = _mm256_set1_epi32(2);
7572 let mask = 0b10101010;
7573 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7574 // A multiplier of 8 is word-addressing
7575 let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32);
7576 assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7577 }
7578
7579 #[simd_test(enable = "avx512f")]
7580 unsafe fn test_mm512_i32scatter_pd() {
7581 let mut arr = [0f64; 128];
7582 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7583 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7584 // A multiplier of 8 is word-addressing
7585 _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7586 let mut expected = [0f64; 128];
7587 for i in 0..8 {
7588 expected[i * 16] = (i + 1) as f64;
7589 }
7590 assert_eq!(&arr[..], &expected[..],);
7591 }
7592
7593 #[simd_test(enable = "avx512f")]
7594 unsafe fn test_mm512_mask_i32scatter_pd() {
7595 let mut arr = [0f64; 128];
7596 let mask = 0b10101010;
7597 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7598 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7599 // A multiplier of 8 is word-addressing
7600 _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7601 let mut expected = [0f64; 128];
7602 for i in 0..4 {
7603 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7604 }
7605 assert_eq!(&arr[..], &expected[..],);
7606 }
7607
7608 #[simd_test(enable = "avx512f")]
7609 unsafe fn test_mm512_i64scatter_pd() {
7610 let mut arr = [0f64; 128];
7611 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7612 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7613 // A multiplier of 8 is word-addressing
7614 _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7615 let mut expected = [0f64; 128];
7616 for i in 0..8 {
7617 expected[i * 16] = (i + 1) as f64;
7618 }
7619 assert_eq!(&arr[..], &expected[..],);
7620 }
7621
7622 #[simd_test(enable = "avx512f")]
7623 unsafe fn test_mm512_mask_i64scatter_pd() {
7624 let mut arr = [0f64; 128];
7625 let mask = 0b10101010;
7626 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7627 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7628 // A multiplier of 8 is word-addressing
7629 _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7630 let mut expected = [0f64; 128];
7631 for i in 0..4 {
7632 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7633 }
7634 assert_eq!(&arr[..], &expected[..],);
7635 }
7636
7637 #[simd_test(enable = "avx512f")]
7638 unsafe fn test_mm512_i64scatter_ps() {
7639 let mut arr = [0f32; 128];
7640 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7641 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7642 // A multiplier of 4 is word-addressing
7643 _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
7644 let mut expected = [0f32; 128];
7645 for i in 0..8 {
7646 expected[i * 16] = (i + 1) as f32;
7647 }
7648 assert_eq!(&arr[..], &expected[..],);
7649 }
7650
7651 #[simd_test(enable = "avx512f")]
7652 unsafe fn test_mm512_mask_i64scatter_ps() {
7653 let mut arr = [0f32; 128];
7654 let mask = 0b10101010;
7655 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7656 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7657 // A multiplier of 4 is word-addressing
7658 _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
7659 let mut expected = [0f32; 128];
7660 for i in 0..4 {
7661 expected[i * 32 + 16] = 2. * (i + 1) as f32;
7662 }
7663 assert_eq!(&arr[..], &expected[..],);
7664 }
7665
7666 #[simd_test(enable = "avx512f")]
7667 unsafe fn test_mm512_i32scatter_epi64() {
7668 let mut arr = [0i64; 128];
7669 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7670 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7671 // A multiplier of 8 is word-addressing
7672 _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7673 let mut expected = [0i64; 128];
7674 for i in 0..8 {
7675 expected[i * 16] = (i + 1) as i64;
7676 }
7677 assert_eq!(&arr[..], &expected[..],);
7678 }
7679
7680 #[simd_test(enable = "avx512f")]
7681 unsafe fn test_mm512_mask_i32scatter_epi64() {
7682 let mut arr = [0i64; 128];
7683 let mask = 0b10101010;
7684 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7685 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7686 // A multiplier of 8 is word-addressing
7687 _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7688 let mut expected = [0i64; 128];
7689 for i in 0..4 {
7690 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7691 }
7692 assert_eq!(&arr[..], &expected[..],);
7693 }
7694
7695 #[simd_test(enable = "avx512f")]
7696 unsafe fn test_mm512_i64scatter_epi64() {
7697 let mut arr = [0i64; 128];
7698 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7699 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7700 // A multiplier of 8 is word-addressing
7701 _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7702 let mut expected = [0i64; 128];
7703 for i in 0..8 {
7704 expected[i * 16] = (i + 1) as i64;
7705 }
7706 assert_eq!(&arr[..], &expected[..],);
7707 }
7708
7709 #[simd_test(enable = "avx512f")]
7710 unsafe fn test_mm512_mask_i64scatter_epi64() {
7711 let mut arr = [0i64; 128];
7712 let mask = 0b10101010;
7713 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7714 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7715 // A multiplier of 8 is word-addressing
7716 _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7717 let mut expected = [0i64; 128];
7718 for i in 0..4 {
7719 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7720 }
7721 assert_eq!(&arr[..], &expected[..],);
7722 }
7723
7724 #[simd_test(enable = "avx512f")]
7725 unsafe fn test_mm512_i64scatter_epi32() {
7726 let mut arr = [0i32; 128];
7727 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7728 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7729 // A multiplier of 4 is word-addressing
7730 _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
7731 let mut expected = [0i32; 128];
7732 for i in 0..8 {
7733 expected[i * 16] = (i + 1) as i32;
7734 }
7735 assert_eq!(&arr[..], &expected[..],);
7736 }
7737
7738 #[simd_test(enable = "avx512f")]
7739 unsafe fn test_mm512_mask_i64scatter_epi32() {
7740 let mut arr = [0i32; 128];
7741 let mask = 0b10101010;
7742 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7743 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7744 // A multiplier of 4 is word-addressing
7745 _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
7746 let mut expected = [0i32; 128];
7747 for i in 0..4 {
7748 expected[i * 32 + 16] = 2 * (i + 1) as i32;
7749 }
7750 assert_eq!(&arr[..], &expected[..],);
7751 }
7752
7753 #[simd_test(enable = "avx512f")]
7754 unsafe fn test_mm512_i32logather_epi64() {
7755 let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7756 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7757 let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr());
7758 let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7759 assert_eq_m512i(expected, r);
7760 }
7761
7762 #[simd_test(enable = "avx512f")]
7763 unsafe fn test_mm512_mask_i32logather_epi64() {
7764 let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7765 let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
7766 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7767 let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
7768 let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
7769 assert_eq_m512i(expected, r);
7770 }
7771
7772 #[simd_test(enable = "avx512f")]
7773 unsafe fn test_mm512_i32logather_pd() {
7774 let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7775 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7776 let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr());
7777 let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7778 assert_eq_m512d(expected, r);
7779 }
7780
7781 #[simd_test(enable = "avx512f")]
7782 unsafe fn test_mm512_mask_i32logather_pd() {
7783 let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7784 let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
7785 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7786 let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
7787 let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
7788 assert_eq_m512d(expected, r);
7789 }
7790
7791 #[simd_test(enable = "avx512f")]
7792 unsafe fn test_mm512_i32loscatter_epi64() {
7793 let mut base_addr: [i64; 8] = [0; 8];
7794 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7795 let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7796 _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
7797 let expected = [1, 2, 3, 4, 5, 6, 7, 8];
7798 assert_eq!(expected, base_addr);
7799 }
7800
7801 #[simd_test(enable = "avx512f")]
7802 unsafe fn test_mm512_mask_i32loscatter_epi64() {
7803 let mut base_addr: [i64; 8] = [0; 8];
7804 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7805 let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7806 _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7807 let expected = [0, 2, 0, 4, 0, 6, 0, 8];
7808 assert_eq!(expected, base_addr);
7809 }
7810
7811 #[simd_test(enable = "avx512f")]
7812 unsafe fn test_mm512_i32loscatter_pd() {
7813 let mut base_addr: [f64; 8] = [0.; 8];
7814 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7815 let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7816 _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
7817 let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
7818 assert_eq!(expected, base_addr);
7819 }
7820
7821 #[simd_test(enable = "avx512f")]
7822 unsafe fn test_mm512_mask_i32loscatter_pd() {
7823 let mut base_addr: [f64; 8] = [0.; 8];
7824 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7825 let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7826 _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7827 let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
7828 assert_eq!(expected, base_addr);
7829 }
7830
7831 #[simd_test(enable = "avx512f,avx512vl")]
7832 unsafe fn test_mm_mmask_i32gather_epi32() {
7833 let base_addr: [i32; 4] = [1, 2, 3, 4];
7834 let src = _mm_setr_epi32(5, 6, 7, 8);
7835 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7836 let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7837 let expected = _mm_setr_epi32(2, 6, 4, 8);
7838 assert_eq_m128i(expected, r);
7839 }
7840
7841 #[simd_test(enable = "avx512f,avx512vl")]
7842 unsafe fn test_mm_mmask_i32gather_epi64() {
7843 let base_addr: [i64; 2] = [1, 2];
7844 let src = _mm_setr_epi64x(5, 6);
7845 let vindex = _mm_setr_epi32(1, 0, -1, -1);
7846 let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
7847 let expected = _mm_setr_epi64x(2, 6);
7848 assert_eq_m128i(expected, r);
7849 }
7850
7851 #[simd_test(enable = "avx512f,avx512vl")]
7852 unsafe fn test_mm_mmask_i32gather_pd() {
7853 let base_addr: [f64; 2] = [1., 2.];
7854 let src = _mm_setr_pd(5., 6.);
7855 let vindex = _mm_setr_epi32(1, 0, -1, -1);
7856 let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
7857 let expected = _mm_setr_pd(2., 6.);
7858 assert_eq_m128d(expected, r);
7859 }
7860
7861 #[simd_test(enable = "avx512f,avx512vl")]
7862 unsafe fn test_mm_mmask_i32gather_ps() {
7863 let base_addr: [f32; 4] = [1., 2., 3., 4.];
7864 let src = _mm_setr_ps(5., 6., 7., 8.);
7865 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7866 let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7867 let expected = _mm_setr_ps(2., 6., 4., 8.);
7868 assert_eq_m128(expected, r);
7869 }
7870
7871 #[simd_test(enable = "avx512f,avx512vl")]
7872 unsafe fn test_mm_mmask_i64gather_epi32() {
7873 let base_addr: [i32; 2] = [1, 2];
7874 let src = _mm_setr_epi32(5, 6, 7, 8);
7875 let vindex = _mm_setr_epi64x(1, 0);
7876 let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr());
7877 let expected = _mm_setr_epi32(2, 6, 0, 0);
7878 assert_eq_m128i(expected, r);
7879 }
7880
7881 #[simd_test(enable = "avx512f,avx512vl")]
7882 unsafe fn test_mm_mmask_i64gather_epi64() {
7883 let base_addr: [i64; 2] = [1, 2];
7884 let src = _mm_setr_epi64x(5, 6);
7885 let vindex = _mm_setr_epi64x(1, 0);
7886 let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
7887 let expected = _mm_setr_epi64x(2, 6);
7888 assert_eq_m128i(expected, r);
7889 }
7890
7891 #[simd_test(enable = "avx512f,avx512vl")]
7892 unsafe fn test_mm_mmask_i64gather_pd() {
7893 let base_addr: [f64; 2] = [1., 2.];
7894 let src = _mm_setr_pd(5., 6.);
7895 let vindex = _mm_setr_epi64x(1, 0);
7896 let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
7897 let expected = _mm_setr_pd(2., 6.);
7898 assert_eq_m128d(expected, r);
7899 }
7900
7901 #[simd_test(enable = "avx512f,avx512vl")]
7902 unsafe fn test_mm_mmask_i64gather_ps() {
7903 let base_addr: [f32; 2] = [1., 2.];
7904 let src = _mm_setr_ps(5., 6., 7., 8.);
7905 let vindex = _mm_setr_epi64x(1, 0);
7906 let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr());
7907 let expected = _mm_setr_ps(2., 6., 0., 0.);
7908 assert_eq_m128(expected, r);
7909 }
7910
7911 #[simd_test(enable = "avx512f,avx512vl")]
7912 unsafe fn test_mm256_mmask_i32gather_epi32() {
7913 let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7914 let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
7915 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7916 let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
7917 let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
7918 assert_eq_m256i(expected, r);
7919 }
7920
7921 #[simd_test(enable = "avx512f,avx512vl")]
7922 unsafe fn test_mm256_mmask_i32gather_epi64() {
7923 let base_addr: [i64; 4] = [1, 2, 3, 4];
7924 let src = _mm256_setr_epi64x(9, 10, 11, 12);
7925 let vindex = _mm_setr_epi32(1, 2, 3, 4);
7926 let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7927 let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7928 assert_eq_m256i(expected, r);
7929 }
7930
7931 #[simd_test(enable = "avx512f,avx512vl")]
7932 unsafe fn test_mm256_mmask_i32gather_pd() {
7933 let base_addr: [f64; 4] = [1., 2., 3., 4.];
7934 let src = _mm256_setr_pd(9., 10., 11., 12.);
7935 let vindex = _mm_setr_epi32(1, 2, 3, 4);
7936 let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7937 let expected = _mm256_setr_pd(2., 10., 4., 12.);
7938 assert_eq_m256d(expected, r);
7939 }
7940
7941 #[simd_test(enable = "avx512f,avx512vl")]
7942 unsafe fn test_mm256_mmask_i32gather_ps() {
7943 let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7944 let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
7945 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7946 let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
7947 let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
7948 assert_eq_m256(expected, r);
7949 }
7950
7951 #[simd_test(enable = "avx512f,avx512vl")]
7952 unsafe fn test_mm256_mmask_i64gather_epi32() {
7953 let base_addr: [i32; 4] = [1, 2, 3, 4];
7954 let src = _mm_setr_epi32(9, 10, 11, 12);
7955 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7956 let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7957 let expected = _mm_setr_epi32(2, 10, 4, 12);
7958 assert_eq_m128i(expected, r);
7959 }
7960
7961 #[simd_test(enable = "avx512f,avx512vl")]
7962 unsafe fn test_mm256_mmask_i64gather_epi64() {
7963 let base_addr: [i64; 4] = [1, 2, 3, 4];
7964 let src = _mm256_setr_epi64x(9, 10, 11, 12);
7965 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7966 let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7967 let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7968 assert_eq_m256i(expected, r);
7969 }
7970
7971 #[simd_test(enable = "avx512f,avx512vl")]
7972 unsafe fn test_mm256_mmask_i64gather_pd() {
7973 let base_addr: [f64; 4] = [1., 2., 3., 4.];
7974 let src = _mm256_setr_pd(9., 10., 11., 12.);
7975 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7976 let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7977 let expected = _mm256_setr_pd(2., 10., 4., 12.);
7978 assert_eq_m256d(expected, r);
7979 }
7980
7981 #[simd_test(enable = "avx512f,avx512vl")]
7982 unsafe fn test_mm256_mmask_i64gather_ps() {
7983 let base_addr: [f32; 4] = [1., 2., 3., 4.];
7984 let src = _mm_setr_ps(9., 10., 11., 12.);
7985 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7986 let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7987 let expected = _mm_setr_ps(2., 10., 4., 12.);
7988 assert_eq_m128(expected, r);
7989 }
7990
7991 #[simd_test(enable = "avx512f,avx512vl")]
7992 unsafe fn test_mm_i32scatter_epi32() {
7993 let mut base_addr: [i32; 4] = [0; 4];
7994 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7995 let src = _mm_setr_epi32(2, 3, 4, 1);
7996 _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
7997 let expected = [1, 2, 3, 4];
7998 assert_eq!(expected, base_addr);
7999 }
8000
8001 #[simd_test(enable = "avx512f,avx512vl")]
8002 unsafe fn test_mm_mask_i32scatter_epi32() {
8003 let mut base_addr: [i32; 4] = [0; 4];
8004 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8005 let src = _mm_setr_epi32(2, 3, 4, 1);
8006 _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8007 let expected = [0, 2, 0, 4];
8008 assert_eq!(expected, base_addr);
8009 }
8010
8011 #[simd_test(enable = "avx512f,avx512vl")]
8012 unsafe fn test_mm_i32scatter_epi64() {
8013 let mut base_addr: [i64; 2] = [0; 2];
8014 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8015 let src = _mm_setr_epi64x(2, 1);
8016 _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8017 let expected = [1, 2];
8018 assert_eq!(expected, base_addr);
8019 }
8020
8021 #[simd_test(enable = "avx512f,avx512vl")]
8022 unsafe fn test_mm_mask_i32scatter_epi64() {
8023 let mut base_addr: [i64; 2] = [0; 2];
8024 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8025 let src = _mm_setr_epi64x(2, 1);
8026 _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8027 let expected = [0, 2];
8028 assert_eq!(expected, base_addr);
8029 }
8030
8031 #[simd_test(enable = "avx512f,avx512vl")]
8032 unsafe fn test_mm_i32scatter_pd() {
8033 let mut base_addr: [f64; 2] = [0.; 2];
8034 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8035 let src = _mm_setr_pd(2., 1.);
8036 _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8037 let expected = [1., 2.];
8038 assert_eq!(expected, base_addr);
8039 }
8040
8041 #[simd_test(enable = "avx512f,avx512vl")]
8042 unsafe fn test_mm_mask_i32scatter_pd() {
8043 let mut base_addr: [f64; 2] = [0.; 2];
8044 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8045 let src = _mm_setr_pd(2., 1.);
8046 _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8047 let expected = [0., 2.];
8048 assert_eq!(expected, base_addr);
8049 }
8050
8051 #[simd_test(enable = "avx512f,avx512vl")]
8052 unsafe fn test_mm_i32scatter_ps() {
8053 let mut base_addr: [f32; 4] = [0.; 4];
8054 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8055 let src = _mm_setr_ps(2., 3., 4., 1.);
8056 _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8057 let expected = [1., 2., 3., 4.];
8058 assert_eq!(expected, base_addr);
8059 }
8060
8061 #[simd_test(enable = "avx512f,avx512vl")]
8062 unsafe fn test_mm_mask_i32scatter_ps() {
8063 let mut base_addr: [f32; 4] = [0.; 4];
8064 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8065 let src = _mm_setr_ps(2., 3., 4., 1.);
8066 _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8067 let expected = [0., 2., 0., 4.];
8068 assert_eq!(expected, base_addr);
8069 }
8070
8071 #[simd_test(enable = "avx512f,avx512vl")]
8072 unsafe fn test_mm_i64scatter_epi32() {
8073 let mut base_addr: [i32; 2] = [0; 2];
8074 let vindex = _mm_setr_epi64x(1, 0);
8075 let src = _mm_setr_epi32(2, 1, -1, -1);
8076 _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8077 let expected = [1, 2];
8078 assert_eq!(expected, base_addr);
8079 }
8080
8081 #[simd_test(enable = "avx512f,avx512vl")]
8082 unsafe fn test_mm_mask_i64scatter_epi32() {
8083 let mut base_addr: [i32; 2] = [0; 2];
8084 let vindex = _mm_setr_epi64x(1, 0);
8085 let src = _mm_setr_epi32(2, 1, -1, -1);
8086 _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8087 let expected = [0, 2];
8088 assert_eq!(expected, base_addr);
8089 }
8090
8091 #[simd_test(enable = "avx512f,avx512vl")]
8092 unsafe fn test_mm_i64scatter_epi64() {
8093 let mut base_addr: [i64; 2] = [0; 2];
8094 let vindex = _mm_setr_epi64x(1, 0);
8095 let src = _mm_setr_epi64x(2, 1);
8096 _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8097 let expected = [1, 2];
8098 assert_eq!(expected, base_addr);
8099 }
8100
8101 #[simd_test(enable = "avx512f,avx512vl")]
8102 unsafe fn test_mm_mask_i64scatter_epi64() {
8103 let mut base_addr: [i64; 2] = [0; 2];
8104 let vindex = _mm_setr_epi64x(1, 0);
8105 let src = _mm_setr_epi64x(2, 1);
8106 _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8107 let expected = [0, 2];
8108 assert_eq!(expected, base_addr);
8109 }
8110
8111 #[simd_test(enable = "avx512f,avx512vl")]
8112 unsafe fn test_mm_i64scatter_pd() {
8113 let mut base_addr: [f64; 2] = [0.; 2];
8114 let vindex = _mm_setr_epi64x(1, 0);
8115 let src = _mm_setr_pd(2., 1.);
8116 _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8117 let expected = [1., 2.];
8118 assert_eq!(expected, base_addr);
8119 }
8120
8121 #[simd_test(enable = "avx512f,avx512vl")]
8122 unsafe fn test_mm_mask_i64scatter_pd() {
8123 let mut base_addr: [f64; 2] = [0.; 2];
8124 let vindex = _mm_setr_epi64x(1, 0);
8125 let src = _mm_setr_pd(2., 1.);
8126 _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8127 let expected = [0., 2.];
8128 assert_eq!(expected, base_addr);
8129 }
8130
8131 #[simd_test(enable = "avx512f,avx512vl")]
8132 unsafe fn test_mm_i64scatter_ps() {
8133 let mut base_addr: [f32; 2] = [0.; 2];
8134 let vindex = _mm_setr_epi64x(1, 0);
8135 let src = _mm_setr_ps(2., 1., -1., -1.);
8136 _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8137 let expected = [1., 2.];
8138 assert_eq!(expected, base_addr);
8139 }
8140
8141 #[simd_test(enable = "avx512f,avx512vl")]
8142 unsafe fn test_mm_mask_i64scatter_ps() {
8143 let mut base_addr: [f32; 2] = [0.; 2];
8144 let vindex = _mm_setr_epi64x(1, 0);
8145 let src = _mm_setr_ps(2., 1., -1., -1.);
8146 _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8147 let expected = [0., 2.];
8148 assert_eq!(expected, base_addr);
8149 }
8150
8151 #[simd_test(enable = "avx512f,avx512vl")]
8152 unsafe fn test_mm256_i32scatter_epi32() {
8153 let mut base_addr: [i32; 8] = [0; 8];
8154 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8155 let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8156 _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8157 let expected = [1, 2, 3, 4, 5, 6, 7, 8];
8158 assert_eq!(expected, base_addr);
8159 }
8160
8161 #[simd_test(enable = "avx512f,avx512vl")]
8162 unsafe fn test_mm256_mask_i32scatter_epi32() {
8163 let mut base_addr: [i32; 8] = [0; 8];
8164 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8165 let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8166 _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8167 let expected = [0, 2, 0, 4, 0, 6, 0, 8];
8168 assert_eq!(expected, base_addr);
8169 }
8170
8171 #[simd_test(enable = "avx512f,avx512vl")]
8172 unsafe fn test_mm256_i32scatter_epi64() {
8173 let mut base_addr: [i64; 4] = [0; 4];
8174 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8175 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8176 _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8177 let expected = [1, 2, 3, 4];
8178 assert_eq!(expected, base_addr);
8179 }
8180
8181 #[simd_test(enable = "avx512f,avx512vl")]
8182 unsafe fn test_mm256_mask_i32scatter_epi64() {
8183 let mut base_addr: [i64; 4] = [0; 4];
8184 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8185 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8186 _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8187 let expected = [0, 2, 0, 4];
8188 assert_eq!(expected, base_addr);
8189 }
8190
8191 #[simd_test(enable = "avx512f,avx512vl")]
8192 unsafe fn test_mm256_i32scatter_pd() {
8193 let mut base_addr: [f64; 4] = [0.; 4];
8194 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8195 let src = _mm256_setr_pd(2., 3., 4., 1.);
8196 _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8197 let expected = [1., 2., 3., 4.];
8198 assert_eq!(expected, base_addr);
8199 }
8200
8201 #[simd_test(enable = "avx512f,avx512vl")]
8202 unsafe fn test_mm256_mask_i32scatter_pd() {
8203 let mut base_addr: [f64; 4] = [0.; 4];
8204 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8205 let src = _mm256_setr_pd(2., 3., 4., 1.);
8206 _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8207 let expected = [0., 2., 0., 4.];
8208 assert_eq!(expected, base_addr);
8209 }
8210
8211 #[simd_test(enable = "avx512f,avx512vl")]
8212 unsafe fn test_mm256_i32scatter_ps() {
8213 let mut base_addr: [f32; 8] = [0.; 8];
8214 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8215 let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8216 _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8217 let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
8218 assert_eq!(expected, base_addr);
8219 }
8220
8221 #[simd_test(enable = "avx512f,avx512vl")]
8222 unsafe fn test_mm256_mask_i32scatter_ps() {
8223 let mut base_addr: [f32; 8] = [0.; 8];
8224 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8225 let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8226 _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8227 let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
8228 assert_eq!(expected, base_addr);
8229 }
8230
8231 #[simd_test(enable = "avx512f,avx512vl")]
8232 unsafe fn test_mm256_i64scatter_epi32() {
8233 let mut base_addr: [i32; 4] = [0; 4];
8234 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8235 let src = _mm_setr_epi32(2, 3, 4, 1);
8236 _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8237 let expected = [1, 2, 3, 4];
8238 assert_eq!(expected, base_addr);
8239 }
8240
8241 #[simd_test(enable = "avx512f,avx512vl")]
8242 unsafe fn test_mm256_mask_i64scatter_epi32() {
8243 let mut base_addr: [i32; 4] = [0; 4];
8244 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8245 let src = _mm_setr_epi32(2, 3, 4, 1);
8246 _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8247 let expected = [0, 2, 0, 4];
8248 assert_eq!(expected, base_addr);
8249 }
8250
8251 #[simd_test(enable = "avx512f,avx512vl")]
8252 unsafe fn test_mm256_i64scatter_epi64() {
8253 let mut base_addr: [i64; 4] = [0; 4];
8254 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8255 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8256 _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8257 let expected = [1, 2, 3, 4];
8258 assert_eq!(expected, base_addr);
8259 }
8260
8261 #[simd_test(enable = "avx512f,avx512vl")]
8262 unsafe fn test_mm256_mask_i64scatter_epi64() {
8263 let mut base_addr: [i64; 4] = [0; 4];
8264 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8265 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8266 _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8267 let expected = [0, 2, 0, 4];
8268 assert_eq!(expected, base_addr);
8269 }
8270
8271 #[simd_test(enable = "avx512f,avx512vl")]
8272 unsafe fn test_mm256_i64scatter_pd() {
8273 let mut base_addr: [f64; 4] = [0.; 4];
8274 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8275 let src = _mm256_setr_pd(2., 3., 4., 1.);
8276 _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8277 let expected = [1., 2., 3., 4.];
8278 assert_eq!(expected, base_addr);
8279 }
8280
8281 #[simd_test(enable = "avx512f,avx512vl")]
8282 unsafe fn test_mm256_mask_i64scatter_pd() {
8283 let mut base_addr: [f64; 4] = [0.; 4];
8284 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8285 let src = _mm256_setr_pd(2., 3., 4., 1.);
8286 _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8287 let expected = [0., 2., 0., 4.];
8288 assert_eq!(expected, base_addr);
8289 }
8290
8291 #[simd_test(enable = "avx512f,avx512vl")]
8292 unsafe fn test_mm256_i64scatter_ps() {
8293 let mut base_addr: [f32; 4] = [0.; 4];
8294 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8295 let src = _mm_setr_ps(2., 3., 4., 1.);
8296 _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8297 let expected = [1., 2., 3., 4.];
8298 assert_eq!(expected, base_addr);
8299 }
8300
8301 #[simd_test(enable = "avx512f,avx512vl")]
8302 unsafe fn test_mm256_mask_i64scatter_ps() {
8303 let mut base_addr: [f32; 4] = [0.; 4];
8304 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8305 let src = _mm_setr_ps(2., 3., 4., 1.);
8306 _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8307 let expected = [0., 2., 0., 4.];
8308 assert_eq!(expected, base_addr);
8309 }
8310
8311 #[simd_test(enable = "avx512f")]
8312 unsafe fn test_mm512_rol_epi64() {
8313 #[rustfmt::skip]
8314 let a = _mm512_set_epi64(
8315 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8316 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8317 );
8318 let r = _mm512_rol_epi64::<1>(a);
8319 #[rustfmt::skip]
8320 let e = _mm512_set_epi64(
8321 1 << 0, 1 << 33, 1 << 33, 1 << 33,
8322 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8323 );
8324 assert_eq_m512i(r, e);
8325 }
8326
8327 #[simd_test(enable = "avx512f")]
8328 unsafe fn test_mm512_mask_rol_epi64() {
8329 #[rustfmt::skip]
8330 let a = _mm512_set_epi64(
8331 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8332 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8333 );
8334 let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
8335 assert_eq_m512i(r, a);
8336 let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
8337 #[rustfmt::skip]
8338 let e = _mm512_set_epi64(
8339 1 << 0, 1 << 33, 1 << 33, 1 << 33,
8340 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8341 );
8342 assert_eq_m512i(r, e);
8343 }
8344
8345 #[simd_test(enable = "avx512f")]
8346 unsafe fn test_mm512_maskz_rol_epi64() {
8347 #[rustfmt::skip]
8348 let a = _mm512_set_epi64(
8349 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8350 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8351 );
8352 let r = _mm512_maskz_rol_epi64::<1>(0, a);
8353 assert_eq_m512i(r, _mm512_setzero_si512());
8354 let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
8355 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
8356 assert_eq_m512i(r, e);
8357 }
8358
8359 #[simd_test(enable = "avx512f,avx512vl")]
8360 unsafe fn test_mm256_rol_epi64() {
8361 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8362 let r = _mm256_rol_epi64::<1>(a);
8363 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8364 assert_eq_m256i(r, e);
8365 }
8366
8367 #[simd_test(enable = "avx512f,avx512vl")]
8368 unsafe fn test_mm256_mask_rol_epi64() {
8369 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8370 let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
8371 assert_eq_m256i(r, a);
8372 let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
8373 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8374 assert_eq_m256i(r, e);
8375 }
8376
8377 #[simd_test(enable = "avx512f,avx512vl")]
8378 unsafe fn test_mm256_maskz_rol_epi64() {
8379 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8380 let r = _mm256_maskz_rol_epi64::<1>(0, a);
8381 assert_eq_m256i(r, _mm256_setzero_si256());
8382 let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
8383 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8384 assert_eq_m256i(r, e);
8385 }
8386
8387 #[simd_test(enable = "avx512f,avx512vl")]
8388 unsafe fn test_mm_rol_epi64() {
8389 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8390 let r = _mm_rol_epi64::<1>(a);
8391 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8392 assert_eq_m128i(r, e);
8393 }
8394
8395 #[simd_test(enable = "avx512f,avx512vl")]
8396 unsafe fn test_mm_mask_rol_epi64() {
8397 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8398 let r = _mm_mask_rol_epi64::<1>(a, 0, a);
8399 assert_eq_m128i(r, a);
8400 let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
8401 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8402 assert_eq_m128i(r, e);
8403 }
8404
8405 #[simd_test(enable = "avx512f,avx512vl")]
8406 unsafe fn test_mm_maskz_rol_epi64() {
8407 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8408 let r = _mm_maskz_rol_epi64::<1>(0, a);
8409 assert_eq_m128i(r, _mm_setzero_si128());
8410 let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
8411 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8412 assert_eq_m128i(r, e);
8413 }
8414
8415 #[simd_test(enable = "avx512f")]
8416 unsafe fn test_mm512_ror_epi64() {
8417 #[rustfmt::skip]
8418 let a = _mm512_set_epi64(
8419 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8420 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8421 );
8422 let r = _mm512_ror_epi64::<1>(a);
8423 #[rustfmt::skip]
8424 let e = _mm512_set_epi64(
8425 1 << 63, 1 << 31, 1 << 31, 1 << 31,
8426 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8427 );
8428 assert_eq_m512i(r, e);
8429 }
8430
8431 #[simd_test(enable = "avx512f")]
8432 unsafe fn test_mm512_mask_ror_epi64() {
8433 #[rustfmt::skip]
8434 let a = _mm512_set_epi64(
8435 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8436 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8437 );
8438 let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
8439 assert_eq_m512i(r, a);
8440 let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
8441 #[rustfmt::skip]
8442 let e = _mm512_set_epi64(
8443 1 << 63, 1 << 31, 1 << 31, 1 << 31,
8444 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8445 );
8446 assert_eq_m512i(r, e);
8447 }
8448
8449 #[simd_test(enable = "avx512f")]
8450 unsafe fn test_mm512_maskz_ror_epi64() {
8451 #[rustfmt::skip]
8452 let a = _mm512_set_epi64(
8453 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8454 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8455 );
8456 let r = _mm512_maskz_ror_epi64::<1>(0, a);
8457 assert_eq_m512i(r, _mm512_setzero_si512());
8458 let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
8459 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
8460 assert_eq_m512i(r, e);
8461 }
8462
8463 #[simd_test(enable = "avx512f,avx512vl")]
8464 unsafe fn test_mm256_ror_epi64() {
8465 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8466 let r = _mm256_ror_epi64::<1>(a);
8467 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8468 assert_eq_m256i(r, e);
8469 }
8470
8471 #[simd_test(enable = "avx512f,avx512vl")]
8472 unsafe fn test_mm256_mask_ror_epi64() {
8473 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8474 let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
8475 assert_eq_m256i(r, a);
8476 let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
8477 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8478 assert_eq_m256i(r, e);
8479 }
8480
8481 #[simd_test(enable = "avx512f,avx512vl")]
8482 unsafe fn test_mm256_maskz_ror_epi64() {
8483 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8484 let r = _mm256_maskz_ror_epi64::<1>(0, a);
8485 assert_eq_m256i(r, _mm256_setzero_si256());
8486 let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
8487 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8488 assert_eq_m256i(r, e);
8489 }
8490
8491 #[simd_test(enable = "avx512f,avx512vl")]
8492 unsafe fn test_mm_ror_epi64() {
8493 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8494 let r = _mm_ror_epi64::<1>(a);
8495 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8496 assert_eq_m128i(r, e);
8497 }
8498
8499 #[simd_test(enable = "avx512f,avx512vl")]
8500 unsafe fn test_mm_mask_ror_epi64() {
8501 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8502 let r = _mm_mask_ror_epi64::<1>(a, 0, a);
8503 assert_eq_m128i(r, a);
8504 let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
8505 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8506 assert_eq_m128i(r, e);
8507 }
8508
8509 #[simd_test(enable = "avx512f,avx512vl")]
8510 unsafe fn test_mm_maskz_ror_epi64() {
8511 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8512 let r = _mm_maskz_ror_epi64::<1>(0, a);
8513 assert_eq_m128i(r, _mm_setzero_si128());
8514 let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
8515 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8516 assert_eq_m128i(r, e);
8517 }
8518
8519 #[simd_test(enable = "avx512f")]
8520 unsafe fn test_mm512_slli_epi64() {
8521 #[rustfmt::skip]
8522 let a = _mm512_set_epi64(
8523 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8524 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8525 );
8526 let r = _mm512_slli_epi64::<1>(a);
8527 #[rustfmt::skip]
8528 let e = _mm512_set_epi64(
8529 0, 1 << 33, 1 << 33, 1 << 33,
8530 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8531 );
8532 assert_eq_m512i(r, e);
8533 }
8534
8535 #[simd_test(enable = "avx512f")]
8536 unsafe fn test_mm512_mask_slli_epi64() {
8537 #[rustfmt::skip]
8538 let a = _mm512_set_epi64(
8539 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8540 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8541 );
8542 let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
8543 assert_eq_m512i(r, a);
8544 let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
8545 #[rustfmt::skip]
8546 let e = _mm512_set_epi64(
8547 0, 1 << 33, 1 << 33, 1 << 33,
8548 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8549 );
8550 assert_eq_m512i(r, e);
8551 }
8552
8553 #[simd_test(enable = "avx512f")]
8554 unsafe fn test_mm512_maskz_slli_epi64() {
8555 #[rustfmt::skip]
8556 let a = _mm512_set_epi64(
8557 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8558 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8559 );
8560 let r = _mm512_maskz_slli_epi64::<1>(0, a);
8561 assert_eq_m512i(r, _mm512_setzero_si512());
8562 let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
8563 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8564 assert_eq_m512i(r, e);
8565 }
8566
8567 #[simd_test(enable = "avx512f,avx512vl")]
8568 unsafe fn test_mm256_mask_slli_epi64() {
8569 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8570 let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
8571 assert_eq_m256i(r, a);
8572 let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
8573 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8574 assert_eq_m256i(r, e);
8575 }
8576
8577 #[simd_test(enable = "avx512f,avx512vl")]
8578 unsafe fn test_mm256_maskz_slli_epi64() {
8579 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8580 let r = _mm256_maskz_slli_epi64::<1>(0, a);
8581 assert_eq_m256i(r, _mm256_setzero_si256());
8582 let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
8583 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8584 assert_eq_m256i(r, e);
8585 }
8586
8587 #[simd_test(enable = "avx512f,avx512vl")]
8588 unsafe fn test_mm_mask_slli_epi64() {
8589 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8590 let r = _mm_mask_slli_epi64::<1>(a, 0, a);
8591 assert_eq_m128i(r, a);
8592 let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
8593 let e = _mm_set_epi64x(0, 1 << 33);
8594 assert_eq_m128i(r, e);
8595 }
8596
8597 #[simd_test(enable = "avx512f,avx512vl")]
8598 unsafe fn test_mm_maskz_slli_epi64() {
8599 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8600 let r = _mm_maskz_slli_epi64::<1>(0, a);
8601 assert_eq_m128i(r, _mm_setzero_si128());
8602 let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
8603 let e = _mm_set_epi64x(0, 1 << 33);
8604 assert_eq_m128i(r, e);
8605 }
8606
8607 #[simd_test(enable = "avx512f")]
8608 unsafe fn test_mm512_srli_epi64() {
8609 #[rustfmt::skip]
8610 let a = _mm512_set_epi64(
8611 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8612 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8613 );
8614 let r = _mm512_srli_epi64::<1>(a);
8615 #[rustfmt::skip]
8616 let e = _mm512_set_epi64(
8617 0, 1 << 31, 1 << 31, 1 << 31,
8618 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8619 );
8620 assert_eq_m512i(r, e);
8621 }
8622
8623 #[simd_test(enable = "avx512f")]
8624 unsafe fn test_mm512_mask_srli_epi64() {
8625 #[rustfmt::skip]
8626 let a = _mm512_set_epi64(
8627 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8628 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8629 );
8630 let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
8631 assert_eq_m512i(r, a);
8632 let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
8633 #[rustfmt::skip]
8634 let e = _mm512_set_epi64(
8635 0, 1 << 31, 1 << 31, 1 << 31,
8636 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8637 );
8638 assert_eq_m512i(r, e);
8639 }
8640
8641 #[simd_test(enable = "avx512f")]
8642 unsafe fn test_mm512_maskz_srli_epi64() {
8643 #[rustfmt::skip]
8644 let a = _mm512_set_epi64(
8645 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8646 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8647 );
8648 let r = _mm512_maskz_srli_epi64::<1>(0, a);
8649 assert_eq_m512i(r, _mm512_setzero_si512());
8650 let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
8651 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8652 assert_eq_m512i(r, e);
8653 }
8654
8655 #[simd_test(enable = "avx512f,avx512vl")]
8656 unsafe fn test_mm256_mask_srli_epi64() {
8657 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8658 let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
8659 assert_eq_m256i(r, a);
8660 let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
8661 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8662 assert_eq_m256i(r, e);
8663 }
8664
8665 #[simd_test(enable = "avx512f,avx512vl")]
8666 unsafe fn test_mm256_maskz_srli_epi64() {
8667 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8668 let r = _mm256_maskz_srli_epi64::<1>(0, a);
8669 assert_eq_m256i(r, _mm256_setzero_si256());
8670 let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
8671 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8672 assert_eq_m256i(r, e);
8673 }
8674
8675 #[simd_test(enable = "avx512f,avx512vl")]
8676 unsafe fn test_mm_mask_srli_epi64() {
8677 let a = _mm_set_epi64x(1 << 5, 0);
8678 let r = _mm_mask_srli_epi64::<1>(a, 0, a);
8679 assert_eq_m128i(r, a);
8680 let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
8681 let e = _mm_set_epi64x(1 << 4, 0);
8682 assert_eq_m128i(r, e);
8683 }
8684
8685 #[simd_test(enable = "avx512f,avx512vl")]
8686 unsafe fn test_mm_maskz_srli_epi64() {
8687 let a = _mm_set_epi64x(1 << 5, 0);
8688 let r = _mm_maskz_srli_epi64::<1>(0, a);
8689 assert_eq_m128i(r, _mm_setzero_si128());
8690 let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8691 let e = _mm_set_epi64x(1 << 4, 0);
8692 assert_eq_m128i(r, e);
8693 }
8694
8695 #[simd_test(enable = "avx512f")]
8696 unsafe fn test_mm512_rolv_epi64() {
8697 #[rustfmt::skip]
8698 let a = _mm512_set_epi64(
8699 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8700 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8701 );
8702 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8703 let r = _mm512_rolv_epi64(a, b);
8704 #[rustfmt::skip]
8705 let e = _mm512_set_epi64(
8706 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8707 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8708 );
8709 assert_eq_m512i(r, e);
8710 }
8711
8712 #[simd_test(enable = "avx512f")]
8713 unsafe fn test_mm512_mask_rolv_epi64() {
8714 #[rustfmt::skip]
8715 let a = _mm512_set_epi64(
8716 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8717 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8718 );
8719 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8720 let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8721 assert_eq_m512i(r, a);
8722 let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8723 #[rustfmt::skip]
8724 let e = _mm512_set_epi64(
8725 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8726 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8727 );
8728 assert_eq_m512i(r, e);
8729 }
8730
8731 #[simd_test(enable = "avx512f")]
8732 unsafe fn test_mm512_maskz_rolv_epi64() {
8733 #[rustfmt::skip]
8734 let a = _mm512_set_epi64(
8735 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8736 1 << 32, 1 << 32, 1 << 32, 1 << 62,
8737 );
8738 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8739 let r = _mm512_maskz_rolv_epi64(0, a, b);
8740 assert_eq_m512i(r, _mm512_setzero_si512());
8741 let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8742 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8743 assert_eq_m512i(r, e);
8744 }
8745
8746 #[simd_test(enable = "avx512f,avx512vl")]
8747 unsafe fn test_mm256_rolv_epi64() {
8748 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8749 let b = _mm256_set_epi64x(0, 1, 2, 3);
8750 let r = _mm256_rolv_epi64(a, b);
8751 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8752 assert_eq_m256i(r, e);
8753 }
8754
8755 #[simd_test(enable = "avx512f,avx512vl")]
8756 unsafe fn test_mm256_mask_rolv_epi64() {
8757 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8758 let b = _mm256_set_epi64x(0, 1, 2, 3);
8759 let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8760 assert_eq_m256i(r, a);
8761 let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8762 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8763 assert_eq_m256i(r, e);
8764 }
8765
8766 #[simd_test(enable = "avx512f,avx512vl")]
8767 unsafe fn test_mm256_maskz_rolv_epi64() {
8768 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8769 let b = _mm256_set_epi64x(0, 1, 2, 3);
8770 let r = _mm256_maskz_rolv_epi64(0, a, b);
8771 assert_eq_m256i(r, _mm256_setzero_si256());
8772 let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8773 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8774 assert_eq_m256i(r, e);
8775 }
8776
8777 #[simd_test(enable = "avx512f,avx512vl")]
8778 unsafe fn test_mm_rolv_epi64() {
8779 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8780 let b = _mm_set_epi64x(0, 1);
8781 let r = _mm_rolv_epi64(a, b);
8782 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8783 assert_eq_m128i(r, e);
8784 }
8785
8786 #[simd_test(enable = "avx512f,avx512vl")]
8787 unsafe fn test_mm_mask_rolv_epi64() {
8788 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8789 let b = _mm_set_epi64x(0, 1);
8790 let r = _mm_mask_rolv_epi64(a, 0, a, b);
8791 assert_eq_m128i(r, a);
8792 let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8793 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8794 assert_eq_m128i(r, e);
8795 }
8796
8797 #[simd_test(enable = "avx512f,avx512vl")]
8798 unsafe fn test_mm_maskz_rolv_epi64() {
8799 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8800 let b = _mm_set_epi64x(0, 1);
8801 let r = _mm_maskz_rolv_epi64(0, a, b);
8802 assert_eq_m128i(r, _mm_setzero_si128());
8803 let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8804 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8805 assert_eq_m128i(r, e);
8806 }
8807
8808 #[simd_test(enable = "avx512f")]
8809 unsafe fn test_mm512_rorv_epi64() {
8810 #[rustfmt::skip]
8811 let a = _mm512_set_epi64(
8812 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8813 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8814 );
8815 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8816 let r = _mm512_rorv_epi64(a, b);
8817 #[rustfmt::skip]
8818 let e = _mm512_set_epi64(
8819 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8820 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8821 );
8822 assert_eq_m512i(r, e);
8823 }
8824
8825 #[simd_test(enable = "avx512f")]
8826 unsafe fn test_mm512_mask_rorv_epi64() {
8827 #[rustfmt::skip]
8828 let a = _mm512_set_epi64(
8829 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8830 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8831 );
8832 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8833 let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8834 assert_eq_m512i(r, a);
8835 let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8836 #[rustfmt::skip]
8837 let e = _mm512_set_epi64(
8838 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8839 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8840 );
8841 assert_eq_m512i(r, e);
8842 }
8843
8844 #[simd_test(enable = "avx512f")]
8845 unsafe fn test_mm512_maskz_rorv_epi64() {
8846 #[rustfmt::skip]
8847 let a = _mm512_set_epi64(
8848 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8849 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8850 );
8851 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8852 let r = _mm512_maskz_rorv_epi64(0, a, b);
8853 assert_eq_m512i(r, _mm512_setzero_si512());
8854 let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8855 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8856 assert_eq_m512i(r, e);
8857 }
8858
8859 #[simd_test(enable = "avx512f,avx512vl")]
8860 unsafe fn test_mm256_rorv_epi64() {
8861 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8862 let b = _mm256_set_epi64x(0, 1, 2, 3);
8863 let r = _mm256_rorv_epi64(a, b);
8864 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8865 assert_eq_m256i(r, e);
8866 }
8867
8868 #[simd_test(enable = "avx512f,avx512vl")]
8869 unsafe fn test_mm256_mask_rorv_epi64() {
8870 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8871 let b = _mm256_set_epi64x(0, 1, 2, 3);
8872 let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8873 assert_eq_m256i(r, a);
8874 let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8875 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8876 assert_eq_m256i(r, e);
8877 }
8878
8879 #[simd_test(enable = "avx512f,avx512vl")]
8880 unsafe fn test_mm256_maskz_rorv_epi64() {
8881 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8882 let b = _mm256_set_epi64x(0, 1, 2, 3);
8883 let r = _mm256_maskz_rorv_epi64(0, a, b);
8884 assert_eq_m256i(r, _mm256_setzero_si256());
8885 let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8886 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8887 assert_eq_m256i(r, e);
8888 }
8889
8890 #[simd_test(enable = "avx512f,avx512vl")]
8891 unsafe fn test_mm_rorv_epi64() {
8892 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8893 let b = _mm_set_epi64x(0, 1);
8894 let r = _mm_rorv_epi64(a, b);
8895 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8896 assert_eq_m128i(r, e);
8897 }
8898
8899 #[simd_test(enable = "avx512f,avx512vl")]
8900 unsafe fn test_mm_mask_rorv_epi64() {
8901 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8902 let b = _mm_set_epi64x(0, 1);
8903 let r = _mm_mask_rorv_epi64(a, 0, a, b);
8904 assert_eq_m128i(r, a);
8905 let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8906 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8907 assert_eq_m128i(r, e);
8908 }
8909
8910 #[simd_test(enable = "avx512f,avx512vl")]
8911 unsafe fn test_mm_maskz_rorv_epi64() {
8912 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8913 let b = _mm_set_epi64x(0, 1);
8914 let r = _mm_maskz_rorv_epi64(0, a, b);
8915 assert_eq_m128i(r, _mm_setzero_si128());
8916 let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8917 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8918 assert_eq_m128i(r, e);
8919 }
8920
8921 #[simd_test(enable = "avx512f")]
8922 unsafe fn test_mm512_sllv_epi64() {
8923 #[rustfmt::skip]
8924 let a = _mm512_set_epi64(
8925 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8926 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8927 );
8928 let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8929 let r = _mm512_sllv_epi64(a, count);
8930 #[rustfmt::skip]
8931 let e = _mm512_set_epi64(
8932 1 << 32, 0, 1 << 34, 1 << 35,
8933 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8934 );
8935 assert_eq_m512i(r, e);
8936 }
8937
8938 #[simd_test(enable = "avx512f")]
8939 unsafe fn test_mm512_mask_sllv_epi64() {
8940 #[rustfmt::skip]
8941 let a = _mm512_set_epi64(
8942 1 << 32, 1 << 32, 1 << 63, 1 << 32,
8943 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8944 );
8945 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8946 let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8947 assert_eq_m512i(r, a);
8948 let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8949 #[rustfmt::skip]
8950 let e = _mm512_set_epi64(
8951 1 << 32, 1 << 33, 0, 1 << 35,
8952 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8953 );
8954 assert_eq_m512i(r, e);
8955 }
8956
8957 #[simd_test(enable = "avx512f")]
8958 unsafe fn test_mm512_maskz_sllv_epi64() {
8959 #[rustfmt::skip]
8960 let a = _mm512_set_epi64(
8961 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8962 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8963 );
8964 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8965 let r = _mm512_maskz_sllv_epi64(0, a, count);
8966 assert_eq_m512i(r, _mm512_setzero_si512());
8967 let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8968 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8969 assert_eq_m512i(r, e);
8970 }
8971
8972 #[simd_test(enable = "avx512f,avx512vl")]
8973 unsafe fn test_mm256_mask_sllv_epi64() {
8974 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8975 let count = _mm256_set_epi64x(0, 1, 2, 3);
8976 let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8977 assert_eq_m256i(r, a);
8978 let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8979 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8980 assert_eq_m256i(r, e);
8981 }
8982
8983 #[simd_test(enable = "avx512f,avx512vl")]
8984 unsafe fn test_mm256_maskz_sllv_epi64() {
8985 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8986 let count = _mm256_set_epi64x(0, 1, 2, 3);
8987 let r = _mm256_maskz_sllv_epi64(0, a, count);
8988 assert_eq_m256i(r, _mm256_setzero_si256());
8989 let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8990 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8991 assert_eq_m256i(r, e);
8992 }
8993
8994 #[simd_test(enable = "avx512f,avx512vl")]
8995 unsafe fn test_mm_mask_sllv_epi64() {
8996 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8997 let count = _mm_set_epi64x(2, 3);
8998 let r = _mm_mask_sllv_epi64(a, 0, a, count);
8999 assert_eq_m128i(r, a);
9000 let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
9001 let e = _mm_set_epi64x(0, 1 << 35);
9002 assert_eq_m128i(r, e);
9003 }
9004
9005 #[simd_test(enable = "avx512f,avx512vl")]
9006 unsafe fn test_mm_maskz_sllv_epi64() {
9007 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9008 let count = _mm_set_epi64x(2, 3);
9009 let r = _mm_maskz_sllv_epi64(0, a, count);
9010 assert_eq_m128i(r, _mm_setzero_si128());
9011 let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
9012 let e = _mm_set_epi64x(0, 1 << 35);
9013 assert_eq_m128i(r, e);
9014 }
9015
9016 #[simd_test(enable = "avx512f")]
9017 unsafe fn test_mm512_srlv_epi64() {
9018 #[rustfmt::skip]
9019 let a = _mm512_set_epi64(
9020 1 << 32, 1 << 0, 1 << 32, 1 << 32,
9021 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9022 );
9023 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9024 let r = _mm512_srlv_epi64(a, count);
9025 #[rustfmt::skip]
9026 let e = _mm512_set_epi64(
9027 1 << 32, 0, 1 << 30, 1 << 29,
9028 1 << 28, 1 << 27, 1 << 26, 1 << 25,
9029 );
9030 assert_eq_m512i(r, e);
9031 }
9032
9033 #[simd_test(enable = "avx512f")]
9034 unsafe fn test_mm512_mask_srlv_epi64() {
9035 #[rustfmt::skip]
9036 let a = _mm512_set_epi64(
9037 1 << 32, 1 << 0, 1 << 32, 1 << 32,
9038 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9039 );
9040 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9041 let r = _mm512_mask_srlv_epi64(a, 0, a, count);
9042 assert_eq_m512i(r, a);
9043 let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
9044 #[rustfmt::skip]
9045 let e = _mm512_set_epi64(
9046 1 << 32, 0, 1 << 30, 1 << 29,
9047 1 << 28, 1 << 27, 1 << 26, 1 << 25,
9048 );
9049 assert_eq_m512i(r, e);
9050 }
9051
9052 #[simd_test(enable = "avx512f")]
9053 unsafe fn test_mm512_maskz_srlv_epi64() {
9054 #[rustfmt::skip]
9055 let a = _mm512_set_epi64(
9056 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9057 1 << 32, 1 << 32, 1 << 32, 1 << 0,
9058 );
9059 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9060 let r = _mm512_maskz_srlv_epi64(0, a, count);
9061 assert_eq_m512i(r, _mm512_setzero_si512());
9062 let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
9063 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
9064 assert_eq_m512i(r, e);
9065 }
9066
9067 #[simd_test(enable = "avx512f,avx512vl")]
9068 unsafe fn test_mm256_mask_srlv_epi64() {
9069 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9070 let count = _mm256_set1_epi64x(1);
9071 let r = _mm256_mask_srlv_epi64(a, 0, a, count);
9072 assert_eq_m256i(r, a);
9073 let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
9074 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9075 assert_eq_m256i(r, e);
9076 }
9077
9078 #[simd_test(enable = "avx512f,avx512vl")]
9079 unsafe fn test_mm256_maskz_srlv_epi64() {
9080 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9081 let count = _mm256_set1_epi64x(1);
9082 let r = _mm256_maskz_srlv_epi64(0, a, count);
9083 assert_eq_m256i(r, _mm256_setzero_si256());
9084 let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
9085 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9086 assert_eq_m256i(r, e);
9087 }
9088
9089 #[simd_test(enable = "avx512f,avx512vl")]
9090 unsafe fn test_mm_mask_srlv_epi64() {
9091 let a = _mm_set_epi64x(1 << 5, 0);
9092 let count = _mm_set1_epi64x(1);
9093 let r = _mm_mask_srlv_epi64(a, 0, a, count);
9094 assert_eq_m128i(r, a);
9095 let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
9096 let e = _mm_set_epi64x(1 << 4, 0);
9097 assert_eq_m128i(r, e);
9098 }
9099
9100 #[simd_test(enable = "avx512f,avx512vl")]
9101 unsafe fn test_mm_maskz_srlv_epi64() {
9102 let a = _mm_set_epi64x(1 << 5, 0);
9103 let count = _mm_set1_epi64x(1);
9104 let r = _mm_maskz_srlv_epi64(0, a, count);
9105 assert_eq_m128i(r, _mm_setzero_si128());
9106 let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
9107 let e = _mm_set_epi64x(1 << 4, 0);
9108 assert_eq_m128i(r, e);
9109 }
9110
9111 #[simd_test(enable = "avx512f")]
9112 unsafe fn test_mm512_sll_epi64() {
9113 #[rustfmt::skip]
9114 let a = _mm512_set_epi64(
9115 1 << 63, 1 << 32, 1 << 32, 1 << 32,
9116 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9117 );
9118 let count = _mm_set_epi64x(0, 1);
9119 let r = _mm512_sll_epi64(a, count);
9120 #[rustfmt::skip]
9121 let e = _mm512_set_epi64(
9122 0, 1 << 33, 1 << 33, 1 << 33,
9123 1 << 33, 1 << 33, 1 << 33, 1 << 33,
9124 );
9125 assert_eq_m512i(r, e);
9126 let count = _mm_set_epi64x(1, 0);
9127 let r = _mm512_sll_epi64(a, count);
9128 assert_eq_m512i(r, a);
9129 }
9130
9131 #[simd_test(enable = "avx512f")]
9132 unsafe fn test_mm512_mask_sll_epi64() {
9133 #[rustfmt::skip]
9134 let a = _mm512_set_epi64(
9135 1 << 63, 1 << 32, 1 << 32, 1 << 32,
9136 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9137 );
9138 let count = _mm_set_epi64x(0, 1);
9139 let r = _mm512_mask_sll_epi64(a, 0, a, count);
9140 assert_eq_m512i(r, a);
9141 let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
9142 #[rustfmt::skip]
9143 let e = _mm512_set_epi64(
9144 0, 1 << 33, 1 << 33, 1 << 33,
9145 1 << 33, 1 << 33, 1 << 33, 1 << 33,
9146 );
9147 assert_eq_m512i(r, e);
9148 }
9149
9150 #[simd_test(enable = "avx512f")]
9151 unsafe fn test_mm512_maskz_sll_epi64() {
9152 #[rustfmt::skip]
9153 let a = _mm512_set_epi64(
9154 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9155 1 << 32, 1 << 32, 1 << 32, 1 << 63,
9156 );
9157 let count = _mm_set_epi64x(0, 1);
9158 let r = _mm512_maskz_sll_epi64(0, a, count);
9159 assert_eq_m512i(r, _mm512_setzero_si512());
9160 let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
9161 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
9162 assert_eq_m512i(r, e);
9163 }
9164
9165 #[simd_test(enable = "avx512f,avx512vl")]
9166 unsafe fn test_mm256_mask_sll_epi64() {
9167 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9168 let count = _mm_set_epi64x(0, 1);
9169 let r = _mm256_mask_sll_epi64(a, 0, a, count);
9170 assert_eq_m256i(r, a);
9171 let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
9172 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9173 assert_eq_m256i(r, e);
9174 }
9175
9176 #[simd_test(enable = "avx512f,avx512vl")]
9177 unsafe fn test_mm256_maskz_sll_epi64() {
9178 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9179 let count = _mm_set_epi64x(0, 1);
9180 let r = _mm256_maskz_sll_epi64(0, a, count);
9181 assert_eq_m256i(r, _mm256_setzero_si256());
9182 let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
9183 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9184 assert_eq_m256i(r, e);
9185 }
9186
9187 #[simd_test(enable = "avx512f,avx512vl")]
9188 unsafe fn test_mm_mask_sll_epi64() {
9189 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9190 let count = _mm_set_epi64x(0, 1);
9191 let r = _mm_mask_sll_epi64(a, 0, a, count);
9192 assert_eq_m128i(r, a);
9193 let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
9194 let e = _mm_set_epi64x(0, 1 << 33);
9195 assert_eq_m128i(r, e);
9196 }
9197
9198 #[simd_test(enable = "avx512f,avx512vl")]
9199 unsafe fn test_mm_maskz_sll_epi64() {
9200 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9201 let count = _mm_set_epi64x(0, 1);
9202 let r = _mm_maskz_sll_epi64(0, a, count);
9203 assert_eq_m128i(r, _mm_setzero_si128());
9204 let r = _mm_maskz_sll_epi64(0b00000011, a, count);
9205 let e = _mm_set_epi64x(0, 1 << 33);
9206 assert_eq_m128i(r, e);
9207 }
9208
9209 #[simd_test(enable = "avx512f")]
9210 unsafe fn test_mm512_srl_epi64() {
9211 #[rustfmt::skip]
9212 let a = _mm512_set_epi64(
9213 1 << 0, 1 << 32, 1 << 32, 1 << 32,
9214 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9215 );
9216 let count = _mm_set_epi64x(0, 1);
9217 let r = _mm512_srl_epi64(a, count);
9218 #[rustfmt::skip]
9219 let e = _mm512_set_epi64(
9220 0, 1 << 31, 1 << 31, 1 << 31,
9221 1 << 31, 1 << 31, 1 << 31, 1 << 31,
9222 );
9223 assert_eq_m512i(r, e);
9224 }
9225
9226 #[simd_test(enable = "avx512f")]
9227 unsafe fn test_mm512_mask_srl_epi64() {
9228 #[rustfmt::skip]
9229 let a = _mm512_set_epi64(
9230 1 << 0, 1 << 32, 1 << 32, 1 << 32,
9231 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9232 );
9233 let count = _mm_set_epi64x(0, 1);
9234 let r = _mm512_mask_srl_epi64(a, 0, a, count);
9235 assert_eq_m512i(r, a);
9236 let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
9237 #[rustfmt::skip]
9238 let e = _mm512_set_epi64(
9239 0, 1 << 31, 1 << 31, 1 << 31,
9240 1 << 31, 1 << 31, 1 << 31, 1 << 31,
9241 );
9242 assert_eq_m512i(r, e);
9243 }
9244
9245 #[simd_test(enable = "avx512f")]
9246 unsafe fn test_mm512_maskz_srl_epi64() {
9247 #[rustfmt::skip]
9248 let a = _mm512_set_epi64(
9249 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9250 1 << 32, 1 << 32, 1 << 32, 1 << 0,
9251 );
9252 let count = _mm_set_epi64x(0, 1);
9253 let r = _mm512_maskz_srl_epi64(0, a, count);
9254 assert_eq_m512i(r, _mm512_setzero_si512());
9255 let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
9256 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
9257 assert_eq_m512i(r, e);
9258 }
9259
9260 #[simd_test(enable = "avx512f,avx512vl")]
9261 unsafe fn test_mm256_mask_srl_epi64() {
9262 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9263 let count = _mm_set_epi64x(0, 1);
9264 let r = _mm256_mask_srl_epi64(a, 0, a, count);
9265 assert_eq_m256i(r, a);
9266 let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
9267 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9268 assert_eq_m256i(r, e);
9269 }
9270
9271 #[simd_test(enable = "avx512f,avx512vl")]
9272 unsafe fn test_mm256_maskz_srl_epi64() {
9273 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9274 let count = _mm_set_epi64x(0, 1);
9275 let r = _mm256_maskz_srl_epi64(0, a, count);
9276 assert_eq_m256i(r, _mm256_setzero_si256());
9277 let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
9278 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9279 assert_eq_m256i(r, e);
9280 }
9281
9282 #[simd_test(enable = "avx512f,avx512vl")]
9283 unsafe fn test_mm_mask_srl_epi64() {
9284 let a = _mm_set_epi64x(1 << 5, 0);
9285 let count = _mm_set_epi64x(0, 1);
9286 let r = _mm_mask_srl_epi64(a, 0, a, count);
9287 assert_eq_m128i(r, a);
9288 let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
9289 let e = _mm_set_epi64x(1 << 4, 0);
9290 assert_eq_m128i(r, e);
9291 }
9292
9293 #[simd_test(enable = "avx512f,avx512vl")]
9294 unsafe fn test_mm_maskz_srl_epi64() {
9295 let a = _mm_set_epi64x(1 << 5, 0);
9296 let count = _mm_set_epi64x(0, 1);
9297 let r = _mm_maskz_srl_epi64(0, a, count);
9298 assert_eq_m128i(r, _mm_setzero_si128());
9299 let r = _mm_maskz_srl_epi64(0b00000011, a, count);
9300 let e = _mm_set_epi64x(1 << 4, 0);
9301 assert_eq_m128i(r, e);
9302 }
9303
9304 #[simd_test(enable = "avx512f")]
9305 unsafe fn test_mm512_sra_epi64() {
9306 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9307 let count = _mm_set_epi64x(0, 2);
9308 let r = _mm512_sra_epi64(a, count);
9309 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9310 assert_eq_m512i(r, e);
9311 }
9312
9313 #[simd_test(enable = "avx512f")]
9314 unsafe fn test_mm512_mask_sra_epi64() {
9315 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9316 let count = _mm_set_epi64x(0, 2);
9317 let r = _mm512_mask_sra_epi64(a, 0, a, count);
9318 assert_eq_m512i(r, a);
9319 let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
9320 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9321 assert_eq_m512i(r, e);
9322 }
9323
9324 #[simd_test(enable = "avx512f")]
9325 unsafe fn test_mm512_maskz_sra_epi64() {
9326 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9327 let count = _mm_set_epi64x(0, 2);
9328 let r = _mm512_maskz_sra_epi64(0, a, count);
9329 assert_eq_m512i(r, _mm512_setzero_si512());
9330 let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
9331 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
9332 assert_eq_m512i(r, e);
9333 }
9334
9335 #[simd_test(enable = "avx512f,avx512vl")]
9336 unsafe fn test_mm256_sra_epi64() {
9337 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9338 let count = _mm_set_epi64x(0, 1);
9339 let r = _mm256_sra_epi64(a, count);
9340 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9341 assert_eq_m256i(r, e);
9342 }
9343
9344 #[simd_test(enable = "avx512f,avx512vl")]
9345 unsafe fn test_mm256_mask_sra_epi64() {
9346 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9347 let count = _mm_set_epi64x(0, 1);
9348 let r = _mm256_mask_sra_epi64(a, 0, a, count);
9349 assert_eq_m256i(r, a);
9350 let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
9351 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9352 assert_eq_m256i(r, e);
9353 }
9354
9355 #[simd_test(enable = "avx512f,avx512vl")]
9356 unsafe fn test_mm256_maskz_sra_epi64() {
9357 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9358 let count = _mm_set_epi64x(0, 1);
9359 let r = _mm256_maskz_sra_epi64(0, a, count);
9360 assert_eq_m256i(r, _mm256_setzero_si256());
9361 let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
9362 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9363 assert_eq_m256i(r, e);
9364 }
9365
9366 #[simd_test(enable = "avx512f,avx512vl")]
9367 unsafe fn test_mm_sra_epi64() {
9368 let a = _mm_set_epi64x(1 << 5, 0);
9369 let count = _mm_set_epi64x(0, 1);
9370 let r = _mm_sra_epi64(a, count);
9371 let e = _mm_set_epi64x(1 << 4, 0);
9372 assert_eq_m128i(r, e);
9373 }
9374
9375 #[simd_test(enable = "avx512f,avx512vl")]
9376 unsafe fn test_mm_mask_sra_epi64() {
9377 let a = _mm_set_epi64x(1 << 5, 0);
9378 let count = _mm_set_epi64x(0, 1);
9379 let r = _mm_mask_sra_epi64(a, 0, a, count);
9380 assert_eq_m128i(r, a);
9381 let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
9382 let e = _mm_set_epi64x(1 << 4, 0);
9383 assert_eq_m128i(r, e);
9384 }
9385
9386 #[simd_test(enable = "avx512f,avx512vl")]
9387 unsafe fn test_mm_maskz_sra_epi64() {
9388 let a = _mm_set_epi64x(1 << 5, 0);
9389 let count = _mm_set_epi64x(0, 1);
9390 let r = _mm_maskz_sra_epi64(0, a, count);
9391 assert_eq_m128i(r, _mm_setzero_si128());
9392 let r = _mm_maskz_sra_epi64(0b00000011, a, count);
9393 let e = _mm_set_epi64x(1 << 4, 0);
9394 assert_eq_m128i(r, e);
9395 }
9396
9397 #[simd_test(enable = "avx512f")]
9398 unsafe fn test_mm512_srav_epi64() {
9399 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9400 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9401 let r = _mm512_srav_epi64(a, count);
9402 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9403 assert_eq_m512i(r, e);
9404 }
9405
9406 #[simd_test(enable = "avx512f")]
9407 unsafe fn test_mm512_mask_srav_epi64() {
9408 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9409 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9410 let r = _mm512_mask_srav_epi64(a, 0, a, count);
9411 assert_eq_m512i(r, a);
9412 let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
9413 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9414 assert_eq_m512i(r, e);
9415 }
9416
9417 #[simd_test(enable = "avx512f")]
9418 unsafe fn test_mm512_maskz_srav_epi64() {
9419 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9420 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9421 let r = _mm512_maskz_srav_epi64(0, a, count);
9422 assert_eq_m512i(r, _mm512_setzero_si512());
9423 let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
9424 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
9425 assert_eq_m512i(r, e);
9426 }
9427
9428 #[simd_test(enable = "avx512f,avx512vl")]
9429 unsafe fn test_mm256_srav_epi64() {
9430 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9431 let count = _mm256_set1_epi64x(1);
9432 let r = _mm256_srav_epi64(a, count);
9433 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9434 assert_eq_m256i(r, e);
9435 }
9436
9437 #[simd_test(enable = "avx512f,avx512vl")]
9438 unsafe fn test_mm256_mask_srav_epi64() {
9439 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9440 let count = _mm256_set1_epi64x(1);
9441 let r = _mm256_mask_srav_epi64(a, 0, a, count);
9442 assert_eq_m256i(r, a);
9443 let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
9444 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9445 assert_eq_m256i(r, e);
9446 }
9447
9448 #[simd_test(enable = "avx512f,avx512vl")]
9449 unsafe fn test_mm256_maskz_srav_epi64() {
9450 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9451 let count = _mm256_set1_epi64x(1);
9452 let r = _mm256_maskz_srav_epi64(0, a, count);
9453 assert_eq_m256i(r, _mm256_setzero_si256());
9454 let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
9455 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9456 assert_eq_m256i(r, e);
9457 }
9458
9459 #[simd_test(enable = "avx512f,avx512vl")]
9460 unsafe fn test_mm_srav_epi64() {
9461 let a = _mm_set_epi64x(1 << 5, 0);
9462 let count = _mm_set1_epi64x(1);
9463 let r = _mm_srav_epi64(a, count);
9464 let e = _mm_set_epi64x(1 << 4, 0);
9465 assert_eq_m128i(r, e);
9466 }
9467
9468 #[simd_test(enable = "avx512f,avx512vl")]
9469 unsafe fn test_mm_mask_srav_epi64() {
9470 let a = _mm_set_epi64x(1 << 5, 0);
9471 let count = _mm_set1_epi64x(1);
9472 let r = _mm_mask_srav_epi64(a, 0, a, count);
9473 assert_eq_m128i(r, a);
9474 let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
9475 let e = _mm_set_epi64x(1 << 4, 0);
9476 assert_eq_m128i(r, e);
9477 }
9478
9479 #[simd_test(enable = "avx512f,avx512vl")]
9480 unsafe fn test_mm_maskz_srav_epi64() {
9481 let a = _mm_set_epi64x(1 << 5, 0);
9482 let count = _mm_set1_epi64x(1);
9483 let r = _mm_maskz_srav_epi64(0, a, count);
9484 assert_eq_m128i(r, _mm_setzero_si128());
9485 let r = _mm_maskz_srav_epi64(0b00000011, a, count);
9486 let e = _mm_set_epi64x(1 << 4, 0);
9487 assert_eq_m128i(r, e);
9488 }
9489
9490 #[simd_test(enable = "avx512f")]
9491 unsafe fn test_mm512_srai_epi64() {
9492 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9493 let r = _mm512_srai_epi64::<2>(a);
9494 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9495 assert_eq_m512i(r, e);
9496 }
9497
9498 #[simd_test(enable = "avx512f")]
9499 unsafe fn test_mm512_mask_srai_epi64() {
9500 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9501 let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
9502 assert_eq_m512i(r, a);
9503 let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
9504 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9505 assert_eq_m512i(r, e);
9506 }
9507
9508 #[simd_test(enable = "avx512f")]
9509 unsafe fn test_mm512_maskz_srai_epi64() {
9510 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9511 let r = _mm512_maskz_srai_epi64::<2>(0, a);
9512 assert_eq_m512i(r, _mm512_setzero_si512());
9513 let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
9514 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
9515 assert_eq_m512i(r, e);
9516 }
9517
9518 #[simd_test(enable = "avx512f,avx512vl")]
9519 unsafe fn test_mm256_srai_epi64() {
9520 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9521 let r = _mm256_srai_epi64::<1>(a);
9522 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9523 assert_eq_m256i(r, e);
9524 }
9525
9526 #[simd_test(enable = "avx512f,avx512vl")]
9527 unsafe fn test_mm256_mask_srai_epi64() {
9528 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9529 let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
9530 assert_eq_m256i(r, a);
9531 let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
9532 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9533 assert_eq_m256i(r, e);
9534 }
9535
9536 #[simd_test(enable = "avx512f,avx512vl")]
9537 unsafe fn test_mm256_maskz_srai_epi64() {
9538 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9539 let r = _mm256_maskz_srai_epi64::<1>(0, a);
9540 assert_eq_m256i(r, _mm256_setzero_si256());
9541 let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
9542 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9543 assert_eq_m256i(r, e);
9544 }
9545
9546 #[simd_test(enable = "avx512f,avx512vl")]
9547 unsafe fn test_mm_srai_epi64() {
9548 let a = _mm_set_epi64x(1 << 5, 0);
9549 let r = _mm_srai_epi64::<1>(a);
9550 let e = _mm_set_epi64x(1 << 4, 0);
9551 assert_eq_m128i(r, e);
9552 }
9553
9554 #[simd_test(enable = "avx512f,avx512vl")]
9555 unsafe fn test_mm_mask_srai_epi64() {
9556 let a = _mm_set_epi64x(1 << 5, 0);
9557 let r = _mm_mask_srai_epi64::<1>(a, 0, a);
9558 assert_eq_m128i(r, a);
9559 let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
9560 let e = _mm_set_epi64x(1 << 4, 0);
9561 assert_eq_m128i(r, e);
9562 }
9563
9564 #[simd_test(enable = "avx512f,avx512vl")]
9565 unsafe fn test_mm_maskz_srai_epi64() {
9566 let a = _mm_set_epi64x(1 << 5, 0);
9567 let r = _mm_maskz_srai_epi64::<1>(0, a);
9568 assert_eq_m128i(r, _mm_setzero_si128());
9569 let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
9570 let e = _mm_set_epi64x(1 << 4, 0);
9571 assert_eq_m128i(r, e);
9572 }
9573
9574 #[simd_test(enable = "avx512f")]
9575 unsafe fn test_mm512_permute_pd() {
9576 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9577 let r = _mm512_permute_pd::<0b11_11_11_11>(a);
9578 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9579 assert_eq_m512d(r, e);
9580 }
9581
9582 #[simd_test(enable = "avx512f")]
9583 unsafe fn test_mm512_mask_permute_pd() {
9584 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9585 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
9586 assert_eq_m512d(r, a);
9587 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
9588 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9589 assert_eq_m512d(r, e);
9590 }
9591
9592 #[simd_test(enable = "avx512f")]
9593 unsafe fn test_mm512_maskz_permute_pd() {
9594 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9595 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
9596 assert_eq_m512d(r, _mm512_setzero_pd());
9597 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
9598 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9599 assert_eq_m512d(r, e);
9600 }
9601
9602 #[simd_test(enable = "avx512f,avx512vl")]
9603 unsafe fn test_mm256_mask_permute_pd() {
9604 let a = _mm256_set_pd(3., 2., 1., 0.);
9605 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
9606 assert_eq_m256d(r, a);
9607 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
9608 let e = _mm256_set_pd(3., 3., 1., 1.);
9609 assert_eq_m256d(r, e);
9610 }
9611
9612 #[simd_test(enable = "avx512f,avx512vl")]
9613 unsafe fn test_mm256_maskz_permute_pd() {
9614 let a = _mm256_set_pd(3., 2., 1., 0.);
9615 let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
9616 assert_eq_m256d(r, _mm256_setzero_pd());
9617 let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
9618 let e = _mm256_set_pd(3., 3., 1., 1.);
9619 assert_eq_m256d(r, e);
9620 }
9621
9622 #[simd_test(enable = "avx512f,avx512vl")]
9623 unsafe fn test_mm_mask_permute_pd() {
9624 let a = _mm_set_pd(1., 0.);
9625 let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
9626 assert_eq_m128d(r, a);
9627 let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
9628 let e = _mm_set_pd(1., 1.);
9629 assert_eq_m128d(r, e);
9630 }
9631
9632 #[simd_test(enable = "avx512f,avx512vl")]
9633 unsafe fn test_mm_maskz_permute_pd() {
9634 let a = _mm_set_pd(1., 0.);
9635 let r = _mm_maskz_permute_pd::<0b11>(0, a);
9636 assert_eq_m128d(r, _mm_setzero_pd());
9637 let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
9638 let e = _mm_set_pd(1., 1.);
9639 assert_eq_m128d(r, e);
9640 }
9641
9642 #[simd_test(enable = "avx512f")]
9643 unsafe fn test_mm512_permutex_epi64() {
9644 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9645 let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
9646 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9647 assert_eq_m512i(r, e);
9648 }
9649
9650 #[simd_test(enable = "avx512f")]
9651 unsafe fn test_mm512_mask_permutex_epi64() {
9652 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9653 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9654 assert_eq_m512i(r, a);
9655 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
9656 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9657 assert_eq_m512i(r, e);
9658 }
9659
9660 #[simd_test(enable = "avx512f")]
9661 unsafe fn test_mm512_maskz_permutex_epi64() {
9662 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9663 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9664 assert_eq_m512i(r, _mm512_setzero_si512());
9665 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
9666 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9667 assert_eq_m512i(r, e);
9668 }
9669
9670 #[simd_test(enable = "avx512f,avx512vl")]
9671 unsafe fn test_mm256_permutex_epi64() {
9672 let a = _mm256_set_epi64x(3, 2, 1, 0);
9673 let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
9674 let e = _mm256_set_epi64x(3, 3, 3, 3);
9675 assert_eq_m256i(r, e);
9676 }
9677
9678 #[simd_test(enable = "avx512f,avx512vl")]
9679 unsafe fn test_mm256_mask_permutex_epi64() {
9680 let a = _mm256_set_epi64x(3, 2, 1, 0);
9681 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9682 assert_eq_m256i(r, a);
9683 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
9684 let e = _mm256_set_epi64x(3, 3, 3, 3);
9685 assert_eq_m256i(r, e);
9686 }
9687
9688 #[simd_test(enable = "avx512f")]
9689 unsafe fn test_mm256_maskz_permutex_epi64() {
9690 let a = _mm256_set_epi64x(3, 2, 1, 0);
9691 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9692 assert_eq_m256i(r, _mm256_setzero_si256());
9693 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9694 let e = _mm256_set_epi64x(3, 3, 3, 3);
9695 assert_eq_m256i(r, e);
9696 }
9697
9698 #[simd_test(enable = "avx512f")]
9699 unsafe fn test_mm512_permutex_pd() {
9700 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9701 let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9702 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9703 assert_eq_m512d(r, e);
9704 }
9705
9706 #[simd_test(enable = "avx512f")]
9707 unsafe fn test_mm512_mask_permutex_pd() {
9708 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9709 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9710 assert_eq_m512d(r, a);
9711 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9712 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9713 assert_eq_m512d(r, e);
9714 }
9715
9716 #[simd_test(enable = "avx512f")]
9717 unsafe fn test_mm512_maskz_permutex_pd() {
9718 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9719 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9720 assert_eq_m512d(r, _mm512_setzero_pd());
9721 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9722 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9723 assert_eq_m512d(r, e);
9724 }
9725
9726 #[simd_test(enable = "avx512f,avx512vl")]
9727 unsafe fn test_mm256_permutex_pd() {
9728 let a = _mm256_set_pd(0., 1., 2., 3.);
9729 let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9730 let e = _mm256_set_pd(0., 0., 0., 0.);
9731 assert_eq_m256d(r, e);
9732 }
9733
9734 #[simd_test(enable = "avx512f,avx512vl")]
9735 unsafe fn test_mm256_mask_permutex_pd() {
9736 let a = _mm256_set_pd(0., 1., 2., 3.);
9737 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9738 assert_eq_m256d(r, a);
9739 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9740 let e = _mm256_set_pd(0., 0., 0., 0.);
9741 assert_eq_m256d(r, e);
9742 }
9743
9744 #[simd_test(enable = "avx512f,avx512vl")]
9745 unsafe fn test_mm256_maskz_permutex_pd() {
9746 let a = _mm256_set_pd(0., 1., 2., 3.);
9747 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9748 assert_eq_m256d(r, _mm256_setzero_pd());
9749 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9750 let e = _mm256_set_pd(0., 0., 0., 0.);
9751 assert_eq_m256d(r, e);
9752 }
9753
9754 #[simd_test(enable = "avx512f")]
9755 unsafe fn test_mm512_permutevar_pd() {
9756 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9757 let b = _mm512_set1_epi64(0b1);
9758 let r = _mm512_permutevar_pd(a, b);
9759 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9760 assert_eq_m512d(r, e);
9761 }
9762
9763 #[simd_test(enable = "avx512f")]
9764 unsafe fn test_mm512_mask_permutevar_pd() {
9765 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9766 let b = _mm512_set1_epi64(0b1);
9767 let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9768 assert_eq_m512d(r, a);
9769 let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9770 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9771 assert_eq_m512d(r, e);
9772 }
9773
9774 #[simd_test(enable = "avx512f")]
9775 unsafe fn test_mm512_maskz_permutevar_pd() {
9776 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9777 let b = _mm512_set1_epi64(0b1);
9778 let r = _mm512_maskz_permutevar_pd(0, a, b);
9779 assert_eq_m512d(r, _mm512_setzero_pd());
9780 let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9781 let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9782 assert_eq_m512d(r, e);
9783 }
9784
9785 #[simd_test(enable = "avx512f,avx512vl")]
9786 unsafe fn test_mm256_mask_permutevar_pd() {
9787 let a = _mm256_set_pd(0., 1., 2., 3.);
9788 let b = _mm256_set1_epi64x(0b1);
9789 let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9790 assert_eq_m256d(r, a);
9791 let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9792 let e = _mm256_set_pd(1., 1., 3., 3.);
9793 assert_eq_m256d(r, e);
9794 }
9795
9796 #[simd_test(enable = "avx512f,avx512vl")]
9797 unsafe fn test_mm256_maskz_permutevar_pd() {
9798 let a = _mm256_set_pd(0., 1., 2., 3.);
9799 let b = _mm256_set1_epi64x(0b1);
9800 let r = _mm256_maskz_permutevar_pd(0, a, b);
9801 assert_eq_m256d(r, _mm256_setzero_pd());
9802 let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9803 let e = _mm256_set_pd(1., 1., 3., 3.);
9804 assert_eq_m256d(r, e);
9805 }
9806
9807 #[simd_test(enable = "avx512f,avx512vl")]
9808 unsafe fn test_mm_mask_permutevar_pd() {
9809 let a = _mm_set_pd(0., 1.);
9810 let b = _mm_set1_epi64x(0b1);
9811 let r = _mm_mask_permutevar_pd(a, 0, a, b);
9812 assert_eq_m128d(r, a);
9813 let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9814 let e = _mm_set_pd(1., 1.);
9815 assert_eq_m128d(r, e);
9816 }
9817
9818 #[simd_test(enable = "avx512f,avx512vl")]
9819 unsafe fn test_mm_maskz_permutevar_pd() {
9820 let a = _mm_set_pd(0., 1.);
9821 let b = _mm_set1_epi64x(0b1);
9822 let r = _mm_maskz_permutevar_pd(0, a, b);
9823 assert_eq_m128d(r, _mm_setzero_pd());
9824 let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9825 let e = _mm_set_pd(1., 1.);
9826 assert_eq_m128d(r, e);
9827 }
9828
9829 #[simd_test(enable = "avx512f")]
9830 unsafe fn test_mm512_permutexvar_epi64() {
9831 let idx = _mm512_set1_epi64(1);
9832 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9833 let r = _mm512_permutexvar_epi64(idx, a);
9834 let e = _mm512_set1_epi64(6);
9835 assert_eq_m512i(r, e);
9836 }
9837
9838 #[simd_test(enable = "avx512f")]
9839 unsafe fn test_mm512_mask_permutexvar_epi64() {
9840 let idx = _mm512_set1_epi64(1);
9841 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9842 let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9843 assert_eq_m512i(r, a);
9844 let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9845 let e = _mm512_set1_epi64(6);
9846 assert_eq_m512i(r, e);
9847 }
9848
9849 #[simd_test(enable = "avx512f")]
9850 unsafe fn test_mm512_maskz_permutexvar_epi64() {
9851 let idx = _mm512_set1_epi64(1);
9852 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9853 let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9854 assert_eq_m512i(r, _mm512_setzero_si512());
9855 let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9856 let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9857 assert_eq_m512i(r, e);
9858 }
9859
9860 #[simd_test(enable = "avx512f,avx512vl")]
9861 unsafe fn test_mm256_permutexvar_epi64() {
9862 let idx = _mm256_set1_epi64x(1);
9863 let a = _mm256_set_epi64x(0, 1, 2, 3);
9864 let r = _mm256_permutexvar_epi64(idx, a);
9865 let e = _mm256_set1_epi64x(2);
9866 assert_eq_m256i(r, e);
9867 }
9868
9869 #[simd_test(enable = "avx512f,avx512vl")]
9870 unsafe fn test_mm256_mask_permutexvar_epi64() {
9871 let idx = _mm256_set1_epi64x(1);
9872 let a = _mm256_set_epi64x(0, 1, 2, 3);
9873 let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9874 assert_eq_m256i(r, a);
9875 let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9876 let e = _mm256_set1_epi64x(2);
9877 assert_eq_m256i(r, e);
9878 }
9879
9880 #[simd_test(enable = "avx512f,avx512vl")]
9881 unsafe fn test_mm256_maskz_permutexvar_epi64() {
9882 let idx = _mm256_set1_epi64x(1);
9883 let a = _mm256_set_epi64x(0, 1, 2, 3);
9884 let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9885 assert_eq_m256i(r, _mm256_setzero_si256());
9886 let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9887 let e = _mm256_set1_epi64x(2);
9888 assert_eq_m256i(r, e);
9889 }
9890
9891 #[simd_test(enable = "avx512f")]
9892 unsafe fn test_mm512_permutexvar_pd() {
9893 let idx = _mm512_set1_epi64(1);
9894 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9895 let r = _mm512_permutexvar_pd(idx, a);
9896 let e = _mm512_set1_pd(6.);
9897 assert_eq_m512d(r, e);
9898 }
9899
9900 #[simd_test(enable = "avx512f")]
9901 unsafe fn test_mm512_mask_permutexvar_pd() {
9902 let idx = _mm512_set1_epi64(1);
9903 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9904 let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9905 assert_eq_m512d(r, a);
9906 let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9907 let e = _mm512_set1_pd(6.);
9908 assert_eq_m512d(r, e);
9909 }
9910
9911 #[simd_test(enable = "avx512f")]
9912 unsafe fn test_mm512_maskz_permutexvar_pd() {
9913 let idx = _mm512_set1_epi64(1);
9914 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9915 let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9916 assert_eq_m512d(r, _mm512_setzero_pd());
9917 let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9918 let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9919 assert_eq_m512d(r, e);
9920 }
9921
9922 #[simd_test(enable = "avx512f,avx512vl")]
9923 unsafe fn test_mm256_permutexvar_pd() {
9924 let idx = _mm256_set1_epi64x(1);
9925 let a = _mm256_set_pd(0., 1., 2., 3.);
9926 let r = _mm256_permutexvar_pd(idx, a);
9927 let e = _mm256_set1_pd(2.);
9928 assert_eq_m256d(r, e);
9929 }
9930
9931 #[simd_test(enable = "avx512f,avx512vl")]
9932 unsafe fn test_mm256_mask_permutexvar_pd() {
9933 let idx = _mm256_set1_epi64x(1);
9934 let a = _mm256_set_pd(0., 1., 2., 3.);
9935 let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9936 assert_eq_m256d(r, a);
9937 let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9938 let e = _mm256_set1_pd(2.);
9939 assert_eq_m256d(r, e);
9940 }
9941
9942 #[simd_test(enable = "avx512f,avx512vl")]
9943 unsafe fn test_mm256_maskz_permutexvar_pd() {
9944 let idx = _mm256_set1_epi64x(1);
9945 let a = _mm256_set_pd(0., 1., 2., 3.);
9946 let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9947 assert_eq_m256d(r, _mm256_setzero_pd());
9948 let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9949 let e = _mm256_set1_pd(2.);
9950 assert_eq_m256d(r, e);
9951 }
9952
9953 #[simd_test(enable = "avx512f")]
9954 unsafe fn test_mm512_permutex2var_epi64() {
9955 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9956 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9957 let b = _mm512_set1_epi64(100);
9958 let r = _mm512_permutex2var_epi64(a, idx, b);
9959 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9960 assert_eq_m512i(r, e);
9961 }
9962
9963 #[simd_test(enable = "avx512f")]
9964 unsafe fn test_mm512_mask_permutex2var_epi64() {
9965 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9966 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9967 let b = _mm512_set1_epi64(100);
9968 let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9969 assert_eq_m512i(r, a);
9970 let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9971 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9972 assert_eq_m512i(r, e);
9973 }
9974
9975 #[simd_test(enable = "avx512f")]
9976 unsafe fn test_mm512_maskz_permutex2var_epi64() {
9977 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9978 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9979 let b = _mm512_set1_epi64(100);
9980 let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9981 assert_eq_m512i(r, _mm512_setzero_si512());
9982 let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9983 let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9984 assert_eq_m512i(r, e);
9985 }
9986
9987 #[simd_test(enable = "avx512f")]
9988 unsafe fn test_mm512_mask2_permutex2var_epi64() {
9989 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9990 let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9991 let b = _mm512_set1_epi64(100);
9992 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
9993 assert_eq_m512i(r, idx);
9994 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9995 let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
9996 assert_eq_m512i(r, e);
9997 }
9998
9999 #[simd_test(enable = "avx512f,avx512vl")]
10000 unsafe fn test_mm256_permutex2var_epi64() {
10001 let a = _mm256_set_epi64x(0, 1, 2, 3);
10002 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10003 let b = _mm256_set1_epi64x(100);
10004 let r = _mm256_permutex2var_epi64(a, idx, b);
10005 let e = _mm256_set_epi64x(2, 100, 1, 100);
10006 assert_eq_m256i(r, e);
10007 }
10008
10009 #[simd_test(enable = "avx512f,avx512vl")]
10010 unsafe fn test_mm256_mask_permutex2var_epi64() {
10011 let a = _mm256_set_epi64x(0, 1, 2, 3);
10012 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10013 let b = _mm256_set1_epi64x(100);
10014 let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
10015 assert_eq_m256i(r, a);
10016 let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
10017 let e = _mm256_set_epi64x(2, 100, 1, 100);
10018 assert_eq_m256i(r, e);
10019 }
10020
10021 #[simd_test(enable = "avx512f,avx512vl")]
10022 unsafe fn test_mm256_maskz_permutex2var_epi64() {
10023 let a = _mm256_set_epi64x(0, 1, 2, 3);
10024 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10025 let b = _mm256_set1_epi64x(100);
10026 let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
10027 assert_eq_m256i(r, _mm256_setzero_si256());
10028 let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
10029 let e = _mm256_set_epi64x(2, 100, 1, 100);
10030 assert_eq_m256i(r, e);
10031 }
10032
10033 #[simd_test(enable = "avx512f,avx512vl")]
10034 unsafe fn test_mm256_mask2_permutex2var_epi64() {
10035 let a = _mm256_set_epi64x(0, 1, 2, 3);
10036 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10037 let b = _mm256_set1_epi64x(100);
10038 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
10039 assert_eq_m256i(r, idx);
10040 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10041 let e = _mm256_set_epi64x(2, 100, 1, 100);
10042 assert_eq_m256i(r, e);
10043 }
10044
10045 #[simd_test(enable = "avx512f,avx512vl")]
10046 unsafe fn test_mm_permutex2var_epi64() {
10047 let a = _mm_set_epi64x(0, 1);
10048 let idx = _mm_set_epi64x(1, 1 << 1);
10049 let b = _mm_set1_epi64x(100);
10050 let r = _mm_permutex2var_epi64(a, idx, b);
10051 let e = _mm_set_epi64x(0, 100);
10052 assert_eq_m128i(r, e);
10053 }
10054
10055 #[simd_test(enable = "avx512f,avx512vl")]
10056 unsafe fn test_mm_mask_permutex2var_epi64() {
10057 let a = _mm_set_epi64x(0, 1);
10058 let idx = _mm_set_epi64x(1, 1 << 1);
10059 let b = _mm_set1_epi64x(100);
10060 let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
10061 assert_eq_m128i(r, a);
10062 let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
10063 let e = _mm_set_epi64x(0, 100);
10064 assert_eq_m128i(r, e);
10065 }
10066
10067 #[simd_test(enable = "avx512f,avx512vl")]
10068 unsafe fn test_mm_maskz_permutex2var_epi64() {
10069 let a = _mm_set_epi64x(0, 1);
10070 let idx = _mm_set_epi64x(1, 1 << 1);
10071 let b = _mm_set1_epi64x(100);
10072 let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
10073 assert_eq_m128i(r, _mm_setzero_si128());
10074 let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
10075 let e = _mm_set_epi64x(0, 100);
10076 assert_eq_m128i(r, e);
10077 }
10078
10079 #[simd_test(enable = "avx512f,avx512vl")]
10080 unsafe fn test_mm_mask2_permutex2var_epi64() {
10081 let a = _mm_set_epi64x(0, 1);
10082 let idx = _mm_set_epi64x(1, 1 << 1);
10083 let b = _mm_set1_epi64x(100);
10084 let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
10085 assert_eq_m128i(r, idx);
10086 let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
10087 let e = _mm_set_epi64x(0, 100);
10088 assert_eq_m128i(r, e);
10089 }
10090
10091 #[simd_test(enable = "avx512f")]
10092 unsafe fn test_mm512_permutex2var_pd() {
10093 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10094 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10095 let b = _mm512_set1_pd(100.);
10096 let r = _mm512_permutex2var_pd(a, idx, b);
10097 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10098 assert_eq_m512d(r, e);
10099 }
10100
10101 #[simd_test(enable = "avx512f")]
10102 unsafe fn test_mm512_mask_permutex2var_pd() {
10103 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10104 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10105 let b = _mm512_set1_pd(100.);
10106 let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
10107 assert_eq_m512d(r, a);
10108 let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
10109 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10110 assert_eq_m512d(r, e);
10111 }
10112
10113 #[simd_test(enable = "avx512f")]
10114 unsafe fn test_mm512_maskz_permutex2var_pd() {
10115 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10116 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10117 let b = _mm512_set1_pd(100.);
10118 let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
10119 assert_eq_m512d(r, _mm512_setzero_pd());
10120 let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
10121 let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
10122 assert_eq_m512d(r, e);
10123 }
10124
10125 #[simd_test(enable = "avx512f")]
10126 unsafe fn test_mm512_mask2_permutex2var_pd() {
10127 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10128 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10129 let b = _mm512_set1_pd(100.);
10130 let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
10131 assert_eq_m512d(r, _mm512_castsi512_pd(idx));
10132 let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
10133 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10134 assert_eq_m512d(r, e);
10135 }
10136
10137 #[simd_test(enable = "avx512f,avx512vl")]
10138 unsafe fn test_mm256_permutex2var_pd() {
10139 let a = _mm256_set_pd(0., 1., 2., 3.);
10140 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10141 let b = _mm256_set1_pd(100.);
10142 let r = _mm256_permutex2var_pd(a, idx, b);
10143 let e = _mm256_set_pd(2., 100., 1., 100.);
10144 assert_eq_m256d(r, e);
10145 }
10146
10147 #[simd_test(enable = "avx512f,avx512vl")]
10148 unsafe fn test_mm256_mask_permutex2var_pd() {
10149 let a = _mm256_set_pd(0., 1., 2., 3.);
10150 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10151 let b = _mm256_set1_pd(100.);
10152 let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
10153 assert_eq_m256d(r, a);
10154 let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
10155 let e = _mm256_set_pd(2., 100., 1., 100.);
10156 assert_eq_m256d(r, e);
10157 }
10158
10159 #[simd_test(enable = "avx512f,avx512vl")]
10160 unsafe fn test_mm256_maskz_permutex2var_pd() {
10161 let a = _mm256_set_pd(0., 1., 2., 3.);
10162 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10163 let b = _mm256_set1_pd(100.);
10164 let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
10165 assert_eq_m256d(r, _mm256_setzero_pd());
10166 let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
10167 let e = _mm256_set_pd(2., 100., 1., 100.);
10168 assert_eq_m256d(r, e);
10169 }
10170
10171 #[simd_test(enable = "avx512f,avx512vl")]
10172 unsafe fn test_mm256_mask2_permutex2var_pd() {
10173 let a = _mm256_set_pd(0., 1., 2., 3.);
10174 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10175 let b = _mm256_set1_pd(100.);
10176 let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
10177 assert_eq_m256d(r, _mm256_castsi256_pd(idx));
10178 let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
10179 let e = _mm256_set_pd(2., 100., 1., 100.);
10180 assert_eq_m256d(r, e);
10181 }
10182
10183 #[simd_test(enable = "avx512f,avx512vl")]
10184 unsafe fn test_mm_permutex2var_pd() {
10185 let a = _mm_set_pd(0., 1.);
10186 let idx = _mm_set_epi64x(1, 1 << 1);
10187 let b = _mm_set1_pd(100.);
10188 let r = _mm_permutex2var_pd(a, idx, b);
10189 let e = _mm_set_pd(0., 100.);
10190 assert_eq_m128d(r, e);
10191 }
10192
10193 #[simd_test(enable = "avx512f,avx512vl")]
10194 unsafe fn test_mm_mask_permutex2var_pd() {
10195 let a = _mm_set_pd(0., 1.);
10196 let idx = _mm_set_epi64x(1, 1 << 1);
10197 let b = _mm_set1_pd(100.);
10198 let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
10199 assert_eq_m128d(r, a);
10200 let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
10201 let e = _mm_set_pd(0., 100.);
10202 assert_eq_m128d(r, e);
10203 }
10204
10205 #[simd_test(enable = "avx512f,avx512vl")]
10206 unsafe fn test_mm_maskz_permutex2var_pd() {
10207 let a = _mm_set_pd(0., 1.);
10208 let idx = _mm_set_epi64x(1, 1 << 1);
10209 let b = _mm_set1_pd(100.);
10210 let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
10211 assert_eq_m128d(r, _mm_setzero_pd());
10212 let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
10213 let e = _mm_set_pd(0., 100.);
10214 assert_eq_m128d(r, e);
10215 }
10216
10217 #[simd_test(enable = "avx512f,avx512vl")]
10218 unsafe fn test_mm_mask2_permutex2var_pd() {
10219 let a = _mm_set_pd(0., 1.);
10220 let idx = _mm_set_epi64x(1, 1 << 1);
10221 let b = _mm_set1_pd(100.);
10222 let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
10223 assert_eq_m128d(r, _mm_castsi128_pd(idx));
10224 let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
10225 let e = _mm_set_pd(0., 100.);
10226 assert_eq_m128d(r, e);
10227 }
10228
10229 #[simd_test(enable = "avx512f,avx512vl")]
10230 unsafe fn test_mm256_mask_shuffle_pd() {
10231 let a = _mm256_set_pd(1., 4., 5., 8.);
10232 let b = _mm256_set_pd(2., 3., 6., 7.);
10233 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10234 assert_eq_m256d(r, a);
10235 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
10236 let e = _mm256_set_pd(2., 1., 6., 5.);
10237 assert_eq_m256d(r, e);
10238 }
10239
10240 #[simd_test(enable = "avx512f,avx512vl")]
10241 unsafe fn test_mm256_maskz_shuffle_pd() {
10242 let a = _mm256_set_pd(1., 4., 5., 8.);
10243 let b = _mm256_set_pd(2., 3., 6., 7.);
10244 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10245 assert_eq_m256d(r, _mm256_setzero_pd());
10246 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
10247 let e = _mm256_set_pd(2., 1., 6., 5.);
10248 assert_eq_m256d(r, e);
10249 }
10250
10251 #[simd_test(enable = "avx512f,avx512vl")]
10252 unsafe fn test_mm_mask_shuffle_pd() {
10253 let a = _mm_set_pd(1., 4.);
10254 let b = _mm_set_pd(2., 3.);
10255 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10256 assert_eq_m128d(r, a);
10257 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
10258 let e = _mm_set_pd(2., 1.);
10259 assert_eq_m128d(r, e);
10260 }
10261
10262 #[simd_test(enable = "avx512f,avx512vl")]
10263 unsafe fn test_mm_maskz_shuffle_pd() {
10264 let a = _mm_set_pd(1., 4.);
10265 let b = _mm_set_pd(2., 3.);
10266 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10267 assert_eq_m128d(r, _mm_setzero_pd());
10268 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
10269 let e = _mm_set_pd(2., 1.);
10270 assert_eq_m128d(r, e);
10271 }
10272
10273 #[simd_test(enable = "avx512f")]
10274 unsafe fn test_mm512_shuffle_i64x2() {
10275 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10276 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10277 let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
10278 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10279 assert_eq_m512i(r, e);
10280 }
10281
10282 #[simd_test(enable = "avx512f")]
10283 unsafe fn test_mm512_mask_shuffle_i64x2() {
10284 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10285 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10286 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
10287 assert_eq_m512i(r, a);
10288 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10289 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10290 assert_eq_m512i(r, e);
10291 }
10292
10293 #[simd_test(enable = "avx512f")]
10294 unsafe fn test_mm512_maskz_shuffle_i64x2() {
10295 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10296 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10297 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
10298 assert_eq_m512i(r, _mm512_setzero_si512());
10299 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
10300 let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
10301 assert_eq_m512i(r, e);
10302 }
10303
10304 #[simd_test(enable = "avx512f,avx512vl")]
10305 unsafe fn test_mm256_shuffle_i64x2() {
10306 let a = _mm256_set_epi64x(1, 4, 5, 8);
10307 let b = _mm256_set_epi64x(2, 3, 6, 7);
10308 let r = _mm256_shuffle_i64x2::<0b00>(a, b);
10309 let e = _mm256_set_epi64x(6, 7, 5, 8);
10310 assert_eq_m256i(r, e);
10311 }
10312
10313 #[simd_test(enable = "avx512f,avx512vl")]
10314 unsafe fn test_mm256_mask_shuffle_i64x2() {
10315 let a = _mm256_set_epi64x(1, 4, 5, 8);
10316 let b = _mm256_set_epi64x(2, 3, 6, 7);
10317 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
10318 assert_eq_m256i(r, a);
10319 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
10320 let e = _mm256_set_epi64x(6, 7, 5, 8);
10321 assert_eq_m256i(r, e);
10322 }
10323
10324 #[simd_test(enable = "avx512f,avx512vl")]
10325 unsafe fn test_mm256_maskz_shuffle_i64x2() {
10326 let a = _mm256_set_epi64x(1, 4, 5, 8);
10327 let b = _mm256_set_epi64x(2, 3, 6, 7);
10328 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
10329 assert_eq_m256i(r, _mm256_setzero_si256());
10330 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
10331 let e = _mm256_set_epi64x(6, 7, 5, 8);
10332 assert_eq_m256i(r, e);
10333 }
10334
10335 #[simd_test(enable = "avx512f")]
10336 unsafe fn test_mm512_shuffle_f64x2() {
10337 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10338 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10339 let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
10340 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10341 assert_eq_m512d(r, e);
10342 }
10343
10344 #[simd_test(enable = "avx512f")]
10345 unsafe fn test_mm512_mask_shuffle_f64x2() {
10346 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10347 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10348 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
10349 assert_eq_m512d(r, a);
10350 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10351 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10352 assert_eq_m512d(r, e);
10353 }
10354
10355 #[simd_test(enable = "avx512f")]
10356 unsafe fn test_mm512_maskz_shuffle_f64x2() {
10357 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10358 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10359 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
10360 assert_eq_m512d(r, _mm512_setzero_pd());
10361 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
10362 let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
10363 assert_eq_m512d(r, e);
10364 }
10365
10366 #[simd_test(enable = "avx512f,avx512vl")]
10367 unsafe fn test_mm256_shuffle_f64x2() {
10368 let a = _mm256_set_pd(1., 4., 5., 8.);
10369 let b = _mm256_set_pd(2., 3., 6., 7.);
10370 let r = _mm256_shuffle_f64x2::<0b00>(a, b);
10371 let e = _mm256_set_pd(6., 7., 5., 8.);
10372 assert_eq_m256d(r, e);
10373 }
10374
10375 #[simd_test(enable = "avx512f,avx512vl")]
10376 unsafe fn test_mm256_mask_shuffle_f64x2() {
10377 let a = _mm256_set_pd(1., 4., 5., 8.);
10378 let b = _mm256_set_pd(2., 3., 6., 7.);
10379 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
10380 assert_eq_m256d(r, a);
10381 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
10382 let e = _mm256_set_pd(6., 7., 5., 8.);
10383 assert_eq_m256d(r, e);
10384 }
10385
10386 #[simd_test(enable = "avx512f,avx512vl")]
10387 unsafe fn test_mm256_maskz_shuffle_f64x2() {
10388 let a = _mm256_set_pd(1., 4., 5., 8.);
10389 let b = _mm256_set_pd(2., 3., 6., 7.);
10390 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
10391 assert_eq_m256d(r, _mm256_setzero_pd());
10392 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
10393 let e = _mm256_set_pd(6., 7., 5., 8.);
10394 assert_eq_m256d(r, e);
10395 }
10396
10397 #[simd_test(enable = "avx512f")]
10398 unsafe fn test_mm512_movedup_pd() {
10399 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10400 let r = _mm512_movedup_pd(a);
10401 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10402 assert_eq_m512d(r, e);
10403 }
10404
10405 #[simd_test(enable = "avx512f")]
10406 unsafe fn test_mm512_mask_movedup_pd() {
10407 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10408 let r = _mm512_mask_movedup_pd(a, 0, a);
10409 assert_eq_m512d(r, a);
10410 let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
10411 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10412 assert_eq_m512d(r, e);
10413 }
10414
10415 #[simd_test(enable = "avx512f")]
10416 unsafe fn test_mm512_maskz_movedup_pd() {
10417 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10418 let r = _mm512_maskz_movedup_pd(0, a);
10419 assert_eq_m512d(r, _mm512_setzero_pd());
10420 let r = _mm512_maskz_movedup_pd(0b00001111, a);
10421 let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
10422 assert_eq_m512d(r, e);
10423 }
10424
10425 #[simd_test(enable = "avx512f,avx512vl")]
10426 unsafe fn test_mm256_mask_movedup_pd() {
10427 let a = _mm256_set_pd(1., 2., 3., 4.);
10428 let r = _mm256_mask_movedup_pd(a, 0, a);
10429 assert_eq_m256d(r, a);
10430 let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
10431 let e = _mm256_set_pd(2., 2., 4., 4.);
10432 assert_eq_m256d(r, e);
10433 }
10434
10435 #[simd_test(enable = "avx512f,avx512vl")]
10436 unsafe fn test_mm256_maskz_movedup_pd() {
10437 let a = _mm256_set_pd(1., 2., 3., 4.);
10438 let r = _mm256_maskz_movedup_pd(0, a);
10439 assert_eq_m256d(r, _mm256_setzero_pd());
10440 let r = _mm256_maskz_movedup_pd(0b00001111, a);
10441 let e = _mm256_set_pd(2., 2., 4., 4.);
10442 assert_eq_m256d(r, e);
10443 }
10444
10445 #[simd_test(enable = "avx512f,avx512vl")]
10446 unsafe fn test_mm_mask_movedup_pd() {
10447 let a = _mm_set_pd(1., 2.);
10448 let r = _mm_mask_movedup_pd(a, 0, a);
10449 assert_eq_m128d(r, a);
10450 let r = _mm_mask_movedup_pd(a, 0b00000011, a);
10451 let e = _mm_set_pd(2., 2.);
10452 assert_eq_m128d(r, e);
10453 }
10454
10455 #[simd_test(enable = "avx512f,avx512vl")]
10456 unsafe fn test_mm_maskz_movedup_pd() {
10457 let a = _mm_set_pd(1., 2.);
10458 let r = _mm_maskz_movedup_pd(0, a);
10459 assert_eq_m128d(r, _mm_setzero_pd());
10460 let r = _mm_maskz_movedup_pd(0b00000011, a);
10461 let e = _mm_set_pd(2., 2.);
10462 assert_eq_m128d(r, e);
10463 }
10464
10465 #[simd_test(enable = "avx512f")]
10466 unsafe fn test_mm512_inserti64x4() {
10467 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10468 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10469 let r = _mm512_inserti64x4::<1>(a, b);
10470 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10471 assert_eq_m512i(r, e);
10472 }
10473
10474 #[simd_test(enable = "avx512f")]
10475 unsafe fn test_mm512_mask_inserti64x4() {
10476 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10477 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10478 let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
10479 assert_eq_m512i(r, a);
10480 let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
10481 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10482 assert_eq_m512i(r, e);
10483 }
10484
10485 #[simd_test(enable = "avx512f")]
10486 unsafe fn test_mm512_maskz_inserti64x4() {
10487 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10488 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10489 let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
10490 assert_eq_m512i(r, _mm512_setzero_si512());
10491 let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
10492 let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
10493 assert_eq_m512i(r, e);
10494 }
10495
10496 #[simd_test(enable = "avx512f")]
10497 unsafe fn test_mm512_insertf64x4() {
10498 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10499 let b = _mm256_setr_pd(17., 18., 19., 20.);
10500 let r = _mm512_insertf64x4::<1>(a, b);
10501 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10502 assert_eq_m512d(r, e);
10503 }
10504
10505 #[simd_test(enable = "avx512f")]
10506 unsafe fn test_mm512_mask_insertf64x4() {
10507 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10508 let b = _mm256_setr_pd(17., 18., 19., 20.);
10509 let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
10510 assert_eq_m512d(r, a);
10511 let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
10512 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10513 assert_eq_m512d(r, e);
10514 }
10515
10516 #[simd_test(enable = "avx512f")]
10517 unsafe fn test_mm512_maskz_insertf64x4() {
10518 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10519 let b = _mm256_setr_pd(17., 18., 19., 20.);
10520 let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
10521 assert_eq_m512d(r, _mm512_setzero_pd());
10522 let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
10523 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
10524 assert_eq_m512d(r, e);
10525 }
10526
10527 #[simd_test(enable = "avx512f")]
10528 unsafe fn test_mm512_castpd128_pd512() {
10529 let a = _mm_setr_pd(17., 18.);
10530 let r = _mm512_castpd128_pd512(a);
10531 assert_eq_m128d(_mm512_castpd512_pd128(r), a);
10532 }
10533
10534 #[simd_test(enable = "avx512f")]
10535 unsafe fn test_mm512_castpd256_pd512() {
10536 let a = _mm256_setr_pd(17., 18., 19., 20.);
10537 let r = _mm512_castpd256_pd512(a);
10538 assert_eq_m256d(_mm512_castpd512_pd256(r), a);
10539 }
10540
10541 #[simd_test(enable = "avx512f")]
10542 unsafe fn test_mm512_zextpd128_pd512() {
10543 let a = _mm_setr_pd(17., 18.);
10544 let r = _mm512_zextpd128_pd512(a);
10545 let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
10546 assert_eq_m512d(r, e);
10547 }
10548
10549 #[simd_test(enable = "avx512f")]
10550 unsafe fn test_mm512_zextpd256_pd512() {
10551 let a = _mm256_setr_pd(17., 18., 19., 20.);
10552 let r = _mm512_zextpd256_pd512(a);
10553 let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
10554 assert_eq_m512d(r, e);
10555 }
10556
10557 #[simd_test(enable = "avx512f")]
10558 unsafe fn test_mm512_castpd512_pd128() {
10559 let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
10560 let r = _mm512_castpd512_pd128(a);
10561 let e = _mm_setr_pd(17., 18.);
10562 assert_eq_m128d(r, e);
10563 }
10564
10565 #[simd_test(enable = "avx512f")]
10566 unsafe fn test_mm512_castpd512_pd256() {
10567 let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
10568 let r = _mm512_castpd512_pd256(a);
10569 let e = _mm256_setr_pd(17., 18., 19., 20.);
10570 assert_eq_m256d(r, e);
10571 }
10572
10573 #[simd_test(enable = "avx512f")]
10574 unsafe fn test_mm512_castpd_ps() {
10575 let a = _mm512_set1_pd(1.);
10576 let r = _mm512_castpd_ps(a);
10577 let e = _mm512_set_ps(
10578 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
10579 1.875, 0.0,
10580 );
10581 assert_eq_m512(r, e);
10582 }
10583
10584 #[simd_test(enable = "avx512f")]
10585 unsafe fn test_mm512_castpd_si512() {
10586 let a = _mm512_set1_pd(1.);
10587 let r = _mm512_castpd_si512(a);
10588 let e = _mm512_set_epi32(
10589 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
10590 0, 1072693248, 0, 1072693248, 0,
10591 );
10592 assert_eq_m512i(r, e);
10593 }
10594
10595 #[simd_test(enable = "avx512f")]
10596 unsafe fn test_mm512_castsi128_si512() {
10597 let a = _mm_setr_epi64x(17, 18);
10598 let r = _mm512_castsi128_si512(a);
10599 assert_eq_m128i(_mm512_castsi512_si128(r), a);
10600 }
10601
10602 #[simd_test(enable = "avx512f")]
10603 unsafe fn test_mm512_castsi256_si512() {
10604 let a = _mm256_setr_epi64x(17, 18, 19, 20);
10605 let r = _mm512_castsi256_si512(a);
10606 assert_eq_m256i(_mm512_castsi512_si256(r), a);
10607 }
10608
10609 #[simd_test(enable = "avx512f")]
10610 unsafe fn test_mm512_zextsi128_si512() {
10611 let a = _mm_setr_epi64x(17, 18);
10612 let r = _mm512_zextsi128_si512(a);
10613 let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
10614 assert_eq_m512i(r, e);
10615 }
10616
10617 #[simd_test(enable = "avx512f")]
10618 unsafe fn test_mm512_zextsi256_si512() {
10619 let a = _mm256_setr_epi64x(17, 18, 19, 20);
10620 let r = _mm512_zextsi256_si512(a);
10621 let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
10622 assert_eq_m512i(r, e);
10623 }
10624
10625 #[simd_test(enable = "avx512f")]
10626 unsafe fn test_mm512_castsi512_si128() {
10627 let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
10628 let r = _mm512_castsi512_si128(a);
10629 let e = _mm_setr_epi64x(17, 18);
10630 assert_eq_m128i(r, e);
10631 }
10632
10633 #[simd_test(enable = "avx512f")]
10634 unsafe fn test_mm512_castsi512_si256() {
10635 let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
10636 let r = _mm512_castsi512_si256(a);
10637 let e = _mm256_setr_epi64x(17, 18, 19, 20);
10638 assert_eq_m256i(r, e);
10639 }
10640
10641 #[simd_test(enable = "avx512f")]
10642 unsafe fn test_mm512_castsi512_ps() {
10643 let a = _mm512_set1_epi64(1 << 62);
10644 let r = _mm512_castsi512_ps(a);
10645 let e = _mm512_set_ps(
10646 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
10647 );
10648 assert_eq_m512(r, e);
10649 }
10650
10651 #[simd_test(enable = "avx512f")]
10652 unsafe fn test_mm512_castsi512_pd() {
10653 let a = _mm512_set1_epi64(1 << 62);
10654 let r = _mm512_castsi512_pd(a);
10655 let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
10656 assert_eq_m512d(r, e);
10657 }
10658
10659 #[simd_test(enable = "avx512f")]
10660 unsafe fn test_mm512_broadcastq_epi64() {
10661 let a = _mm_setr_epi64x(17, 18);
10662 let r = _mm512_broadcastq_epi64(a);
10663 let e = _mm512_set1_epi64(17);
10664 assert_eq_m512i(r, e);
10665 }
10666
10667 #[simd_test(enable = "avx512f")]
10668 unsafe fn test_mm512_mask_broadcastq_epi64() {
10669 let src = _mm512_set1_epi64(18);
10670 let a = _mm_setr_epi64x(17, 18);
10671 let r = _mm512_mask_broadcastq_epi64(src, 0, a);
10672 assert_eq_m512i(r, src);
10673 let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
10674 let e = _mm512_set1_epi64(17);
10675 assert_eq_m512i(r, e);
10676 }
10677
10678 #[simd_test(enable = "avx512f")]
10679 unsafe fn test_mm512_maskz_broadcastq_epi64() {
10680 let a = _mm_setr_epi64x(17, 18);
10681 let r = _mm512_maskz_broadcastq_epi64(0, a);
10682 assert_eq_m512i(r, _mm512_setzero_si512());
10683 let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10684 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10685 assert_eq_m512i(r, e);
10686 }
10687
10688 #[simd_test(enable = "avx512f,avx512vl")]
10689 unsafe fn test_mm256_mask_broadcastq_epi64() {
10690 let src = _mm256_set1_epi64x(18);
10691 let a = _mm_set_epi64x(17, 18);
10692 let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10693 assert_eq_m256i(r, src);
10694 let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10695 let e = _mm256_set1_epi64x(18);
10696 assert_eq_m256i(r, e);
10697 }
10698
10699 #[simd_test(enable = "avx512f,avx512vl")]
10700 unsafe fn test_mm256_maskz_broadcastq_epi64() {
10701 let a = _mm_set_epi64x(17, 18);
10702 let r = _mm256_maskz_broadcastq_epi64(0, a);
10703 assert_eq_m256i(r, _mm256_setzero_si256());
10704 let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10705 let e = _mm256_set1_epi64x(18);
10706 assert_eq_m256i(r, e);
10707 }
10708
10709 #[simd_test(enable = "avx512f,avx512vl")]
10710 unsafe fn test_mm_mask_broadcastq_epi64() {
10711 let src = _mm_set1_epi64x(18);
10712 let a = _mm_set_epi64x(17, 18);
10713 let r = _mm_mask_broadcastq_epi64(src, 0, a);
10714 assert_eq_m128i(r, src);
10715 let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10716 let e = _mm_set1_epi64x(18);
10717 assert_eq_m128i(r, e);
10718 }
10719
10720 #[simd_test(enable = "avx512f,avx512vl")]
10721 unsafe fn test_mm_maskz_broadcastq_epi64() {
10722 let a = _mm_set_epi64x(17, 18);
10723 let r = _mm_maskz_broadcastq_epi64(0, a);
10724 assert_eq_m128i(r, _mm_setzero_si128());
10725 let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10726 let e = _mm_set1_epi64x(18);
10727 assert_eq_m128i(r, e);
10728 }
10729
10730 #[simd_test(enable = "avx512f")]
10731 unsafe fn test_mm512_broadcastsd_pd() {
10732 let a = _mm_set_pd(17., 18.);
10733 let r = _mm512_broadcastsd_pd(a);
10734 let e = _mm512_set1_pd(18.);
10735 assert_eq_m512d(r, e);
10736 }
10737
10738 #[simd_test(enable = "avx512f")]
10739 unsafe fn test_mm512_mask_broadcastsd_pd() {
10740 let src = _mm512_set1_pd(18.);
10741 let a = _mm_set_pd(17., 18.);
10742 let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10743 assert_eq_m512d(r, src);
10744 let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10745 let e = _mm512_set1_pd(18.);
10746 assert_eq_m512d(r, e);
10747 }
10748
10749 #[simd_test(enable = "avx512f")]
10750 unsafe fn test_mm512_maskz_broadcastsd_pd() {
10751 let a = _mm_set_pd(17., 18.);
10752 let r = _mm512_maskz_broadcastsd_pd(0, a);
10753 assert_eq_m512d(r, _mm512_setzero_pd());
10754 let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10755 let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10756 assert_eq_m512d(r, e);
10757 }
10758
10759 #[simd_test(enable = "avx512f,avx512vl")]
10760 unsafe fn test_mm256_mask_broadcastsd_pd() {
10761 let src = _mm256_set1_pd(18.);
10762 let a = _mm_set_pd(17., 18.);
10763 let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10764 assert_eq_m256d(r, src);
10765 let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10766 let e = _mm256_set1_pd(18.);
10767 assert_eq_m256d(r, e);
10768 }
10769
10770 #[simd_test(enable = "avx512f,avx512vl")]
10771 unsafe fn test_mm256_maskz_broadcastsd_pd() {
10772 let a = _mm_set_pd(17., 18.);
10773 let r = _mm256_maskz_broadcastsd_pd(0, a);
10774 assert_eq_m256d(r, _mm256_setzero_pd());
10775 let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10776 let e = _mm256_set1_pd(18.);
10777 assert_eq_m256d(r, e);
10778 }
10779
10780 #[simd_test(enable = "avx512f")]
10781 unsafe fn test_mm512_broadcast_i64x4() {
10782 let a = _mm256_set_epi64x(17, 18, 19, 20);
10783 let r = _mm512_broadcast_i64x4(a);
10784 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10785 assert_eq_m512i(r, e);
10786 }
10787
10788 #[simd_test(enable = "avx512f")]
10789 unsafe fn test_mm512_mask_broadcast_i64x4() {
10790 let src = _mm512_set1_epi64(18);
10791 let a = _mm256_set_epi64x(17, 18, 19, 20);
10792 let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10793 assert_eq_m512i(r, src);
10794 let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10795 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10796 assert_eq_m512i(r, e);
10797 }
10798
10799 #[simd_test(enable = "avx512f")]
10800 unsafe fn test_mm512_maskz_broadcast_i64x4() {
10801 let a = _mm256_set_epi64x(17, 18, 19, 20);
10802 let r = _mm512_maskz_broadcast_i64x4(0, a);
10803 assert_eq_m512i(r, _mm512_setzero_si512());
10804 let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10805 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10806 assert_eq_m512i(r, e);
10807 }
10808
10809 #[simd_test(enable = "avx512f")]
10810 unsafe fn test_mm512_broadcast_f64x4() {
10811 let a = _mm256_set_pd(17., 18., 19., 20.);
10812 let r = _mm512_broadcast_f64x4(a);
10813 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10814 assert_eq_m512d(r, e);
10815 }
10816
10817 #[simd_test(enable = "avx512f")]
10818 unsafe fn test_mm512_mask_broadcast_f64x4() {
10819 let src = _mm512_set1_pd(18.);
10820 let a = _mm256_set_pd(17., 18., 19., 20.);
10821 let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10822 assert_eq_m512d(r, src);
10823 let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10824 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10825 assert_eq_m512d(r, e);
10826 }
10827
10828 #[simd_test(enable = "avx512f")]
10829 unsafe fn test_mm512_maskz_broadcast_f64x4() {
10830 let a = _mm256_set_pd(17., 18., 19., 20.);
10831 let r = _mm512_maskz_broadcast_f64x4(0, a);
10832 assert_eq_m512d(r, _mm512_setzero_pd());
10833 let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10834 let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10835 assert_eq_m512d(r, e);
10836 }
10837
10838 #[simd_test(enable = "avx512f")]
10839 unsafe fn test_mm512_mask_blend_epi64() {
10840 let a = _mm512_set1_epi64(1);
10841 let b = _mm512_set1_epi64(2);
10842 let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10843 let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10844 assert_eq_m512i(r, e);
10845 }
10846
10847 #[simd_test(enable = "avx512f,avx512vl")]
10848 unsafe fn test_mm256_mask_blend_epi64() {
10849 let a = _mm256_set1_epi64x(1);
10850 let b = _mm256_set1_epi64x(2);
10851 let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10852 let e = _mm256_set1_epi64x(2);
10853 assert_eq_m256i(r, e);
10854 }
10855
10856 #[simd_test(enable = "avx512f,avx512vl")]
10857 unsafe fn test_mm_mask_blend_epi64() {
10858 let a = _mm_set1_epi64x(1);
10859 let b = _mm_set1_epi64x(2);
10860 let r = _mm_mask_blend_epi64(0b00000011, a, b);
10861 let e = _mm_set1_epi64x(2);
10862 assert_eq_m128i(r, e);
10863 }
10864
10865 #[simd_test(enable = "avx512f")]
10866 unsafe fn test_mm512_mask_blend_pd() {
10867 let a = _mm512_set1_pd(1.);
10868 let b = _mm512_set1_pd(2.);
10869 let r = _mm512_mask_blend_pd(0b11110000, a, b);
10870 let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10871 assert_eq_m512d(r, e);
10872 }
10873
10874 #[simd_test(enable = "avx512f,avx512vl")]
10875 unsafe fn test_mm256_mask_blend_pd() {
10876 let a = _mm256_set1_pd(1.);
10877 let b = _mm256_set1_pd(2.);
10878 let r = _mm256_mask_blend_pd(0b00001111, a, b);
10879 let e = _mm256_set1_pd(2.);
10880 assert_eq_m256d(r, e);
10881 }
10882
10883 #[simd_test(enable = "avx512f,avx512vl")]
10884 unsafe fn test_mm_mask_blend_pd() {
10885 let a = _mm_set1_pd(1.);
10886 let b = _mm_set1_pd(2.);
10887 let r = _mm_mask_blend_pd(0b00000011, a, b);
10888 let e = _mm_set1_pd(2.);
10889 assert_eq_m128d(r, e);
10890 }
10891
10892 #[simd_test(enable = "avx512f")]
10893 unsafe fn test_mm512_unpackhi_epi64() {
10894 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10895 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10896 let r = _mm512_unpackhi_epi64(a, b);
10897 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10898 assert_eq_m512i(r, e);
10899 }
10900
10901 #[simd_test(enable = "avx512f")]
10902 unsafe fn test_mm512_mask_unpackhi_epi64() {
10903 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10904 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10905 let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10906 assert_eq_m512i(r, a);
10907 let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10908 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10909 assert_eq_m512i(r, e);
10910 }
10911
10912 #[simd_test(enable = "avx512f")]
10913 unsafe fn test_mm512_maskz_unpackhi_epi64() {
10914 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10915 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10916 let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10917 assert_eq_m512i(r, _mm512_setzero_si512());
10918 let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10919 let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10920 assert_eq_m512i(r, e);
10921 }
10922
10923 #[simd_test(enable = "avx512f,avx512vl")]
10924 unsafe fn test_mm256_mask_unpackhi_epi64() {
10925 let a = _mm256_set_epi64x(1, 2, 3, 4);
10926 let b = _mm256_set_epi64x(17, 18, 19, 20);
10927 let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10928 assert_eq_m256i(r, a);
10929 let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10930 let e = _mm256_set_epi64x(17, 1, 19, 3);
10931 assert_eq_m256i(r, e);
10932 }
10933
10934 #[simd_test(enable = "avx512f,avx512vl")]
10935 unsafe fn test_mm256_maskz_unpackhi_epi64() {
10936 let a = _mm256_set_epi64x(1, 2, 3, 4);
10937 let b = _mm256_set_epi64x(17, 18, 19, 20);
10938 let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10939 assert_eq_m256i(r, _mm256_setzero_si256());
10940 let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10941 let e = _mm256_set_epi64x(17, 1, 19, 3);
10942 assert_eq_m256i(r, e);
10943 }
10944
10945 #[simd_test(enable = "avx512f,avx512vl")]
10946 unsafe fn test_mm_mask_unpackhi_epi64() {
10947 let a = _mm_set_epi64x(1, 2);
10948 let b = _mm_set_epi64x(17, 18);
10949 let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10950 assert_eq_m128i(r, a);
10951 let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10952 let e = _mm_set_epi64x(17, 1);
10953 assert_eq_m128i(r, e);
10954 }
10955
10956 #[simd_test(enable = "avx512f,avx512vl")]
10957 unsafe fn test_mm_maskz_unpackhi_epi64() {
10958 let a = _mm_set_epi64x(1, 2);
10959 let b = _mm_set_epi64x(17, 18);
10960 let r = _mm_maskz_unpackhi_epi64(0, a, b);
10961 assert_eq_m128i(r, _mm_setzero_si128());
10962 let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10963 let e = _mm_set_epi64x(17, 1);
10964 assert_eq_m128i(r, e);
10965 }
10966
10967 #[simd_test(enable = "avx512f")]
10968 unsafe fn test_mm512_unpackhi_pd() {
10969 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10970 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10971 let r = _mm512_unpackhi_pd(a, b);
10972 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10973 assert_eq_m512d(r, e);
10974 }
10975
10976 #[simd_test(enable = "avx512f")]
10977 unsafe fn test_mm512_mask_unpackhi_pd() {
10978 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10979 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10980 let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10981 assert_eq_m512d(r, a);
10982 let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10983 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10984 assert_eq_m512d(r, e);
10985 }
10986
10987 #[simd_test(enable = "avx512f")]
10988 unsafe fn test_mm512_maskz_unpackhi_pd() {
10989 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10990 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10991 let r = _mm512_maskz_unpackhi_pd(0, a, b);
10992 assert_eq_m512d(r, _mm512_setzero_pd());
10993 let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
10994 let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
10995 assert_eq_m512d(r, e);
10996 }
10997
10998 #[simd_test(enable = "avx512f,avx512vl")]
10999 unsafe fn test_mm256_mask_unpackhi_pd() {
11000 let a = _mm256_set_pd(1., 2., 3., 4.);
11001 let b = _mm256_set_pd(17., 18., 19., 20.);
11002 let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
11003 assert_eq_m256d(r, a);
11004 let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
11005 let e = _mm256_set_pd(17., 1., 19., 3.);
11006 assert_eq_m256d(r, e);
11007 }
11008
11009 #[simd_test(enable = "avx512f,avx512vl")]
11010 unsafe fn test_mm256_maskz_unpackhi_pd() {
11011 let a = _mm256_set_pd(1., 2., 3., 4.);
11012 let b = _mm256_set_pd(17., 18., 19., 20.);
11013 let r = _mm256_maskz_unpackhi_pd(0, a, b);
11014 assert_eq_m256d(r, _mm256_setzero_pd());
11015 let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
11016 let e = _mm256_set_pd(17., 1., 19., 3.);
11017 assert_eq_m256d(r, e);
11018 }
11019
11020 #[simd_test(enable = "avx512f,avx512vl")]
11021 unsafe fn test_mm_mask_unpackhi_pd() {
11022 let a = _mm_set_pd(1., 2.);
11023 let b = _mm_set_pd(17., 18.);
11024 let r = _mm_mask_unpackhi_pd(a, 0, a, b);
11025 assert_eq_m128d(r, a);
11026 let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
11027 let e = _mm_set_pd(17., 1.);
11028 assert_eq_m128d(r, e);
11029 }
11030
11031 #[simd_test(enable = "avx512f,avx512vl")]
11032 unsafe fn test_mm_maskz_unpackhi_pd() {
11033 let a = _mm_set_pd(1., 2.);
11034 let b = _mm_set_pd(17., 18.);
11035 let r = _mm_maskz_unpackhi_pd(0, a, b);
11036 assert_eq_m128d(r, _mm_setzero_pd());
11037 let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
11038 let e = _mm_set_pd(17., 1.);
11039 assert_eq_m128d(r, e);
11040 }
11041
11042 #[simd_test(enable = "avx512f")]
11043 unsafe fn test_mm512_unpacklo_epi64() {
11044 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11045 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11046 let r = _mm512_unpacklo_epi64(a, b);
11047 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11048 assert_eq_m512i(r, e);
11049 }
11050
11051 #[simd_test(enable = "avx512f")]
11052 unsafe fn test_mm512_mask_unpacklo_epi64() {
11053 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11054 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11055 let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
11056 assert_eq_m512i(r, a);
11057 let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
11058 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11059 assert_eq_m512i(r, e);
11060 }
11061
11062 #[simd_test(enable = "avx512f")]
11063 unsafe fn test_mm512_maskz_unpacklo_epi64() {
11064 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11065 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11066 let r = _mm512_maskz_unpacklo_epi64(0, a, b);
11067 assert_eq_m512i(r, _mm512_setzero_si512());
11068 let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
11069 let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
11070 assert_eq_m512i(r, e);
11071 }
11072
11073 #[simd_test(enable = "avx512f,avx512vl")]
11074 unsafe fn test_mm256_mask_unpacklo_epi64() {
11075 let a = _mm256_set_epi64x(1, 2, 3, 4);
11076 let b = _mm256_set_epi64x(17, 18, 19, 20);
11077 let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
11078 assert_eq_m256i(r, a);
11079 let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
11080 let e = _mm256_set_epi64x(18, 2, 20, 4);
11081 assert_eq_m256i(r, e);
11082 }
11083
11084 #[simd_test(enable = "avx512f,avx512vl")]
11085 unsafe fn test_mm256_maskz_unpacklo_epi64() {
11086 let a = _mm256_set_epi64x(1, 2, 3, 4);
11087 let b = _mm256_set_epi64x(17, 18, 19, 20);
11088 let r = _mm256_maskz_unpacklo_epi64(0, a, b);
11089 assert_eq_m256i(r, _mm256_setzero_si256());
11090 let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
11091 let e = _mm256_set_epi64x(18, 2, 20, 4);
11092 assert_eq_m256i(r, e);
11093 }
11094
11095 #[simd_test(enable = "avx512f,avx512vl")]
11096 unsafe fn test_mm_mask_unpacklo_epi64() {
11097 let a = _mm_set_epi64x(1, 2);
11098 let b = _mm_set_epi64x(17, 18);
11099 let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
11100 assert_eq_m128i(r, a);
11101 let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
11102 let e = _mm_set_epi64x(18, 2);
11103 assert_eq_m128i(r, e);
11104 }
11105
11106 #[simd_test(enable = "avx512f,avx512vl")]
11107 unsafe fn test_mm_maskz_unpacklo_epi64() {
11108 let a = _mm_set_epi64x(1, 2);
11109 let b = _mm_set_epi64x(17, 18);
11110 let r = _mm_maskz_unpacklo_epi64(0, a, b);
11111 assert_eq_m128i(r, _mm_setzero_si128());
11112 let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
11113 let e = _mm_set_epi64x(18, 2);
11114 assert_eq_m128i(r, e);
11115 }
11116
11117 #[simd_test(enable = "avx512f")]
11118 unsafe fn test_mm512_unpacklo_pd() {
11119 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11120 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11121 let r = _mm512_unpacklo_pd(a, b);
11122 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11123 assert_eq_m512d(r, e);
11124 }
11125
11126 #[simd_test(enable = "avx512f")]
11127 unsafe fn test_mm512_mask_unpacklo_pd() {
11128 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11129 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11130 let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
11131 assert_eq_m512d(r, a);
11132 let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
11133 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11134 assert_eq_m512d(r, e);
11135 }
11136
11137 #[simd_test(enable = "avx512f")]
11138 unsafe fn test_mm512_maskz_unpacklo_pd() {
11139 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11140 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11141 let r = _mm512_maskz_unpacklo_pd(0, a, b);
11142 assert_eq_m512d(r, _mm512_setzero_pd());
11143 let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
11144 let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
11145 assert_eq_m512d(r, e);
11146 }
11147
11148 #[simd_test(enable = "avx512f,avx512vl")]
11149 unsafe fn test_mm256_mask_unpacklo_pd() {
11150 let a = _mm256_set_pd(1., 2., 3., 4.);
11151 let b = _mm256_set_pd(17., 18., 19., 20.);
11152 let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
11153 assert_eq_m256d(r, a);
11154 let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
11155 let e = _mm256_set_pd(18., 2., 20., 4.);
11156 assert_eq_m256d(r, e);
11157 }
11158
11159 #[simd_test(enable = "avx512f,avx512vl")]
11160 unsafe fn test_mm256_maskz_unpacklo_pd() {
11161 let a = _mm256_set_pd(1., 2., 3., 4.);
11162 let b = _mm256_set_pd(17., 18., 19., 20.);
11163 let r = _mm256_maskz_unpacklo_pd(0, a, b);
11164 assert_eq_m256d(r, _mm256_setzero_pd());
11165 let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
11166 let e = _mm256_set_pd(18., 2., 20., 4.);
11167 assert_eq_m256d(r, e);
11168 }
11169
11170 #[simd_test(enable = "avx512f,avx512vl")]
11171 unsafe fn test_mm_mask_unpacklo_pd() {
11172 let a = _mm_set_pd(1., 2.);
11173 let b = _mm_set_pd(17., 18.);
11174 let r = _mm_mask_unpacklo_pd(a, 0, a, b);
11175 assert_eq_m128d(r, a);
11176 let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
11177 let e = _mm_set_pd(18., 2.);
11178 assert_eq_m128d(r, e);
11179 }
11180
11181 #[simd_test(enable = "avx512f,avx512vl")]
11182 unsafe fn test_mm_maskz_unpacklo_pd() {
11183 let a = _mm_set_pd(1., 2.);
11184 let b = _mm_set_pd(17., 18.);
11185 let r = _mm_maskz_unpacklo_pd(0, a, b);
11186 assert_eq_m128d(r, _mm_setzero_pd());
11187 let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
11188 let e = _mm_set_pd(18., 2.);
11189 assert_eq_m128d(r, e);
11190 }
11191
11192 #[simd_test(enable = "avx512f")]
11193 unsafe fn test_mm512_alignr_epi64() {
11194 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11195 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11196 let r = _mm512_alignr_epi64::<0>(a, b);
11197 assert_eq_m512i(r, b);
11198 let r = _mm512_alignr_epi64::<8>(a, b);
11199 assert_eq_m512i(r, b);
11200 let r = _mm512_alignr_epi64::<1>(a, b);
11201 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11202 assert_eq_m512i(r, e);
11203 }
11204
11205 #[simd_test(enable = "avx512f")]
11206 unsafe fn test_mm512_mask_alignr_epi64() {
11207 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11208 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11209 let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
11210 assert_eq_m512i(r, a);
11211 let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
11212 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11213 assert_eq_m512i(r, e);
11214 }
11215
11216 #[simd_test(enable = "avx512f")]
11217 unsafe fn test_mm512_maskz_alignr_epi64() {
11218 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11219 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11220 let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
11221 assert_eq_m512i(r, _mm512_setzero_si512());
11222 let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
11223 let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
11224 assert_eq_m512i(r, e);
11225 }
11226
11227 #[simd_test(enable = "avx512f,avx512vl")]
11228 unsafe fn test_mm256_alignr_epi64() {
11229 let a = _mm256_set_epi64x(4, 3, 2, 1);
11230 let b = _mm256_set_epi64x(8, 7, 6, 5);
11231 let r = _mm256_alignr_epi64::<0>(a, b);
11232 let e = _mm256_set_epi64x(8, 7, 6, 5);
11233 assert_eq_m256i(r, e);
11234 let r = _mm256_alignr_epi64::<1>(a, b);
11235 let e = _mm256_set_epi64x(1, 8, 7, 6);
11236 assert_eq_m256i(r, e);
11237 let r = _mm256_alignr_epi64::<6>(a, b);
11238 let e = _mm256_set_epi64x(2, 1, 8, 7);
11239 assert_eq_m256i(r, e);
11240 }
11241
11242 #[simd_test(enable = "avx512f,avx512vl")]
11243 unsafe fn test_mm256_mask_alignr_epi64() {
11244 let a = _mm256_set_epi64x(4, 3, 2, 1);
11245 let b = _mm256_set_epi64x(8, 7, 6, 5);
11246 let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
11247 assert_eq_m256i(r, a);
11248 let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
11249 let e = _mm256_set_epi64x(8, 7, 6, 5);
11250 assert_eq_m256i(r, e);
11251 }
11252
11253 #[simd_test(enable = "avx512f,avx512vl")]
11254 unsafe fn test_mm256_maskz_alignr_epi64() {
11255 let a = _mm256_set_epi64x(4, 3, 2, 1);
11256 let b = _mm256_set_epi64x(8, 7, 6, 5);
11257 let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
11258 assert_eq_m256i(r, _mm256_setzero_si256());
11259 let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
11260 let e = _mm256_set_epi64x(8, 7, 6, 5);
11261 assert_eq_m256i(r, e);
11262 }
11263
11264 #[simd_test(enable = "avx512f,avx512vl")]
11265 unsafe fn test_mm_alignr_epi64() {
11266 let a = _mm_set_epi64x(2, 1);
11267 let b = _mm_set_epi64x(4, 3);
11268 let r = _mm_alignr_epi64::<0>(a, b);
11269 let e = _mm_set_epi64x(4, 3);
11270 assert_eq_m128i(r, e);
11271 }
11272
11273 #[simd_test(enable = "avx512f,avx512vl")]
11274 unsafe fn test_mm_mask_alignr_epi64() {
11275 let a = _mm_set_epi64x(2, 1);
11276 let b = _mm_set_epi64x(4, 3);
11277 let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
11278 assert_eq_m128i(r, a);
11279 let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
11280 let e = _mm_set_epi64x(4, 3);
11281 assert_eq_m128i(r, e);
11282 }
11283
11284 #[simd_test(enable = "avx512f,avx512vl")]
11285 unsafe fn test_mm_maskz_alignr_epi64() {
11286 let a = _mm_set_epi64x(2, 1);
11287 let b = _mm_set_epi64x(4, 3);
11288 let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
11289 assert_eq_m128i(r, _mm_setzero_si128());
11290 let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
11291 let e = _mm_set_epi64x(4, 3);
11292 assert_eq_m128i(r, e);
11293 }
11294
11295 #[simd_test(enable = "avx512f")]
11296 unsafe fn test_mm512_and_epi64() {
11297 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11298 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11299 let r = _mm512_and_epi64(a, b);
11300 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11301 assert_eq_m512i(r, e);
11302 }
11303
11304 #[simd_test(enable = "avx512f")]
11305 unsafe fn test_mm512_mask_and_epi64() {
11306 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11307 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11308 let r = _mm512_mask_and_epi64(a, 0, a, b);
11309 assert_eq_m512i(r, a);
11310 let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
11311 let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11312 assert_eq_m512i(r, e);
11313 }
11314
11315 #[simd_test(enable = "avx512f")]
11316 unsafe fn test_mm512_maskz_and_epi64() {
11317 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11318 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11319 let r = _mm512_maskz_and_epi64(0, a, b);
11320 assert_eq_m512i(r, _mm512_setzero_si512());
11321 let r = _mm512_maskz_and_epi64(0b00001111, a, b);
11322 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11323 assert_eq_m512i(r, e);
11324 }
11325
11326 #[simd_test(enable = "avx512f,avx512vl")]
11327 unsafe fn test_mm256_mask_and_epi64() {
11328 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11329 let b = _mm256_set1_epi64x(1 << 0);
11330 let r = _mm256_mask_and_epi64(a, 0, a, b);
11331 assert_eq_m256i(r, a);
11332 let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
11333 let e = _mm256_set1_epi64x(1 << 0);
11334 assert_eq_m256i(r, e);
11335 }
11336
11337 #[simd_test(enable = "avx512f,avx512vl")]
11338 unsafe fn test_mm256_maskz_and_epi64() {
11339 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11340 let b = _mm256_set1_epi64x(1 << 0);
11341 let r = _mm256_maskz_and_epi64(0, a, b);
11342 assert_eq_m256i(r, _mm256_setzero_si256());
11343 let r = _mm256_maskz_and_epi64(0b00001111, a, b);
11344 let e = _mm256_set1_epi64x(1 << 0);
11345 assert_eq_m256i(r, e);
11346 }
11347
11348 #[simd_test(enable = "avx512f,avx512vl")]
11349 unsafe fn test_mm_mask_and_epi64() {
11350 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11351 let b = _mm_set1_epi64x(1 << 0);
11352 let r = _mm_mask_and_epi64(a, 0, a, b);
11353 assert_eq_m128i(r, a);
11354 let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
11355 let e = _mm_set1_epi64x(1 << 0);
11356 assert_eq_m128i(r, e);
11357 }
11358
11359 #[simd_test(enable = "avx512f,avx512vl")]
11360 unsafe fn test_mm_maskz_and_epi64() {
11361 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11362 let b = _mm_set1_epi64x(1 << 0);
11363 let r = _mm_maskz_and_epi64(0, a, b);
11364 assert_eq_m128i(r, _mm_setzero_si128());
11365 let r = _mm_maskz_and_epi64(0b00000011, a, b);
11366 let e = _mm_set1_epi64x(1 << 0);
11367 assert_eq_m128i(r, e);
11368 }
11369
11370 #[simd_test(enable = "avx512f")]
11371 unsafe fn test_mm512_and_si512() {
11372 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11373 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11374 let r = _mm512_and_epi64(a, b);
11375 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11376 assert_eq_m512i(r, e);
11377 }
11378
11379 #[simd_test(enable = "avx512f")]
11380 unsafe fn test_mm512_or_epi64() {
11381 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11382 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11383 let r = _mm512_or_epi64(a, b);
11384 #[rustfmt::skip]
11385 let e = _mm512_set_epi64(
11386 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11387 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11388 );
11389 assert_eq_m512i(r, e);
11390 }
11391
11392 #[simd_test(enable = "avx512f")]
11393 unsafe fn test_mm512_mask_or_epi64() {
11394 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11395 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11396 let r = _mm512_mask_or_epi64(a, 0, a, b);
11397 assert_eq_m512i(r, a);
11398 let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
11399 #[rustfmt::skip]
11400 let e = _mm512_set_epi64(
11401 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11402 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11403 );
11404 assert_eq_m512i(r, e);
11405 }
11406
11407 #[simd_test(enable = "avx512f")]
11408 unsafe fn test_mm512_maskz_or_epi64() {
11409 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11410 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11411 let r = _mm512_maskz_or_epi64(0, a, b);
11412 assert_eq_m512i(r, _mm512_setzero_si512());
11413 let r = _mm512_maskz_or_epi64(0b00001111, a, b);
11414 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11415 assert_eq_m512i(r, e);
11416 }
11417
11418 #[simd_test(enable = "avx512f,avx512vl")]
11419 unsafe fn test_mm256_or_epi64() {
11420 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11421 let b = _mm256_set1_epi64x(1 << 13);
11422 let r = _mm256_or_epi64(a, b);
11423 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11424 assert_eq_m256i(r, e);
11425 }
11426
11427 #[simd_test(enable = "avx512f,avx512vl")]
11428 unsafe fn test_mm256_mask_or_epi64() {
11429 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11430 let b = _mm256_set1_epi64x(1 << 13);
11431 let r = _mm256_mask_or_epi64(a, 0, a, b);
11432 assert_eq_m256i(r, a);
11433 let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
11434 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11435 assert_eq_m256i(r, e);
11436 }
11437
11438 #[simd_test(enable = "avx512f,avx512vl")]
11439 unsafe fn test_mm256_maskz_or_epi64() {
11440 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11441 let b = _mm256_set1_epi64x(1 << 13);
11442 let r = _mm256_maskz_or_epi64(0, a, b);
11443 assert_eq_m256i(r, _mm256_setzero_si256());
11444 let r = _mm256_maskz_or_epi64(0b00001111, a, b);
11445 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11446 assert_eq_m256i(r, e);
11447 }
11448
11449 #[simd_test(enable = "avx512f,avx512vl")]
11450 unsafe fn test_mm_or_epi64() {
11451 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11452 let b = _mm_set1_epi64x(1 << 13);
11453 let r = _mm_or_epi64(a, b);
11454 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11455 assert_eq_m128i(r, e);
11456 }
11457
11458 #[simd_test(enable = "avx512f,avx512vl")]
11459 unsafe fn test_mm_mask_or_epi64() {
11460 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11461 let b = _mm_set1_epi64x(1 << 13);
11462 let r = _mm_mask_or_epi64(a, 0, a, b);
11463 assert_eq_m128i(r, a);
11464 let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
11465 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11466 assert_eq_m128i(r, e);
11467 }
11468
11469 #[simd_test(enable = "avx512f,avx512vl")]
11470 unsafe fn test_mm_maskz_or_epi64() {
11471 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11472 let b = _mm_set1_epi64x(1 << 13);
11473 let r = _mm_maskz_or_epi64(0, a, b);
11474 assert_eq_m128i(r, _mm_setzero_si128());
11475 let r = _mm_maskz_or_epi64(0b00000011, a, b);
11476 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11477 assert_eq_m128i(r, e);
11478 }
11479
11480 #[simd_test(enable = "avx512f")]
11481 unsafe fn test_mm512_or_si512() {
11482 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11483 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11484 let r = _mm512_or_epi64(a, b);
11485 #[rustfmt::skip]
11486 let e = _mm512_set_epi64(
11487 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11488 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11489 );
11490 assert_eq_m512i(r, e);
11491 }
11492
11493 #[simd_test(enable = "avx512f")]
11494 unsafe fn test_mm512_xor_epi64() {
11495 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11496 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11497 let r = _mm512_xor_epi64(a, b);
11498 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11499 assert_eq_m512i(r, e);
11500 }
11501
11502 #[simd_test(enable = "avx512f")]
11503 unsafe fn test_mm512_mask_xor_epi64() {
11504 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11505 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11506 let r = _mm512_mask_xor_epi64(a, 0, a, b);
11507 assert_eq_m512i(r, a);
11508 let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
11509 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11510 assert_eq_m512i(r, e);
11511 }
11512
11513 #[simd_test(enable = "avx512f")]
11514 unsafe fn test_mm512_maskz_xor_epi64() {
11515 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11516 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11517 let r = _mm512_maskz_xor_epi64(0, a, b);
11518 assert_eq_m512i(r, _mm512_setzero_si512());
11519 let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
11520 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
11521 assert_eq_m512i(r, e);
11522 }
11523
11524 #[simd_test(enable = "avx512f,avx512vl")]
11525 unsafe fn test_mm256_xor_epi64() {
11526 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11527 let b = _mm256_set1_epi64x(1 << 13);
11528 let r = _mm256_xor_epi64(a, b);
11529 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11530 assert_eq_m256i(r, e);
11531 }
11532
11533 #[simd_test(enable = "avx512f,avx512vl")]
11534 unsafe fn test_mm256_mask_xor_epi64() {
11535 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11536 let b = _mm256_set1_epi64x(1 << 13);
11537 let r = _mm256_mask_xor_epi64(a, 0, a, b);
11538 assert_eq_m256i(r, a);
11539 let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
11540 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11541 assert_eq_m256i(r, e);
11542 }
11543
11544 #[simd_test(enable = "avx512f,avx512vl")]
11545 unsafe fn test_mm256_maskz_xor_epi64() {
11546 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11547 let b = _mm256_set1_epi64x(1 << 13);
11548 let r = _mm256_maskz_xor_epi64(0, a, b);
11549 assert_eq_m256i(r, _mm256_setzero_si256());
11550 let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
11551 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11552 assert_eq_m256i(r, e);
11553 }
11554
11555 #[simd_test(enable = "avx512f,avx512vl")]
11556 unsafe fn test_mm_xor_epi64() {
11557 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11558 let b = _mm_set1_epi64x(1 << 13);
11559 let r = _mm_xor_epi64(a, b);
11560 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11561 assert_eq_m128i(r, e);
11562 }
11563
11564 #[simd_test(enable = "avx512f,avx512vl")]
11565 unsafe fn test_mm_mask_xor_epi64() {
11566 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11567 let b = _mm_set1_epi64x(1 << 13);
11568 let r = _mm_mask_xor_epi64(a, 0, a, b);
11569 assert_eq_m128i(r, a);
11570 let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
11571 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11572 assert_eq_m128i(r, e);
11573 }
11574
11575 #[simd_test(enable = "avx512f,avx512vl")]
11576 unsafe fn test_mm_maskz_xor_epi64() {
11577 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11578 let b = _mm_set1_epi64x(1 << 13);
11579 let r = _mm_maskz_xor_epi64(0, a, b);
11580 assert_eq_m128i(r, _mm_setzero_si128());
11581 let r = _mm_maskz_xor_epi64(0b00000011, a, b);
11582 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11583 assert_eq_m128i(r, e);
11584 }
11585
11586 #[simd_test(enable = "avx512f")]
11587 unsafe fn test_mm512_xor_si512() {
11588 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11589 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11590 let r = _mm512_xor_epi64(a, b);
11591 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11592 assert_eq_m512i(r, e);
11593 }
11594
11595 #[simd_test(enable = "avx512f")]
11596 unsafe fn test_mm512_andnot_epi64() {
11597 let a = _mm512_set1_epi64(0);
11598 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11599 let r = _mm512_andnot_epi64(a, b);
11600 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11601 assert_eq_m512i(r, e);
11602 }
11603
11604 #[simd_test(enable = "avx512f")]
11605 unsafe fn test_mm512_mask_andnot_epi64() {
11606 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11607 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11608 let r = _mm512_mask_andnot_epi64(a, 0, a, b);
11609 assert_eq_m512i(r, a);
11610 let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
11611 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11612 assert_eq_m512i(r, e);
11613 }
11614
11615 #[simd_test(enable = "avx512f")]
11616 unsafe fn test_mm512_maskz_andnot_epi64() {
11617 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11618 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11619 let r = _mm512_maskz_andnot_epi64(0, a, b);
11620 assert_eq_m512i(r, _mm512_setzero_si512());
11621 let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
11622 #[rustfmt::skip]
11623 let e = _mm512_set_epi64(
11624 0, 0, 0, 0,
11625 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
11626 );
11627 assert_eq_m512i(r, e);
11628 }
11629
11630 #[simd_test(enable = "avx512f,avx512vl")]
11631 unsafe fn test_mm256_mask_andnot_epi64() {
11632 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11633 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11634 let r = _mm256_mask_andnot_epi64(a, 0, a, b);
11635 assert_eq_m256i(r, a);
11636 let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
11637 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11638 assert_eq_m256i(r, e);
11639 }
11640
11641 #[simd_test(enable = "avx512f,avx512vl")]
11642 unsafe fn test_mm256_maskz_andnot_epi64() {
11643 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11644 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11645 let r = _mm256_maskz_andnot_epi64(0, a, b);
11646 assert_eq_m256i(r, _mm256_setzero_si256());
11647 let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
11648 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11649 assert_eq_m256i(r, e);
11650 }
11651
11652 #[simd_test(enable = "avx512f,avx512vl")]
11653 unsafe fn test_mm_mask_andnot_epi64() {
11654 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11655 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11656 let r = _mm_mask_andnot_epi64(a, 0, a, b);
11657 assert_eq_m128i(r, a);
11658 let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
11659 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11660 assert_eq_m128i(r, e);
11661 }
11662
11663 #[simd_test(enable = "avx512f,avx512vl")]
11664 unsafe fn test_mm_maskz_andnot_epi64() {
11665 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11666 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11667 let r = _mm_maskz_andnot_epi64(0, a, b);
11668 assert_eq_m128i(r, _mm_setzero_si128());
11669 let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
11670 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11671 assert_eq_m128i(r, e);
11672 }
11673
11674 #[simd_test(enable = "avx512f")]
11675 unsafe fn test_mm512_andnot_si512() {
11676 let a = _mm512_set1_epi64(0);
11677 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11678 let r = _mm512_andnot_si512(a, b);
11679 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11680 assert_eq_m512i(r, e);
11681 }
11682
11683 #[simd_test(enable = "avx512f")]
11684 unsafe fn test_mm512_reduce_add_epi64() {
11685 let a = _mm512_set1_epi64(1);
11686 let e: i64 = _mm512_reduce_add_epi64(a);
11687 assert_eq!(8, e);
11688 }
11689
11690 #[simd_test(enable = "avx512f")]
11691 unsafe fn test_mm512_mask_reduce_add_epi64() {
11692 let a = _mm512_set1_epi64(1);
11693 let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11694 assert_eq!(4, e);
11695 }
11696
11697 #[simd_test(enable = "avx512f")]
11698 unsafe fn test_mm512_reduce_add_pd() {
11699 let a = _mm512_set1_pd(1.);
11700 let e: f64 = _mm512_reduce_add_pd(a);
11701 assert_eq!(8., e);
11702 }
11703
11704 #[simd_test(enable = "avx512f")]
11705 unsafe fn test_mm512_mask_reduce_add_pd() {
11706 let a = _mm512_set1_pd(1.);
11707 let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11708 assert_eq!(4., e);
11709 }
11710
11711 #[simd_test(enable = "avx512f")]
11712 unsafe fn test_mm512_reduce_mul_epi64() {
11713 let a = _mm512_set1_epi64(2);
11714 let e: i64 = _mm512_reduce_mul_epi64(a);
11715 assert_eq!(256, e);
11716 }
11717
11718 #[simd_test(enable = "avx512f")]
11719 unsafe fn test_mm512_mask_reduce_mul_epi64() {
11720 let a = _mm512_set1_epi64(2);
11721 let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11722 assert_eq!(16, e);
11723 }
11724
11725 #[simd_test(enable = "avx512f")]
11726 unsafe fn test_mm512_reduce_mul_pd() {
11727 let a = _mm512_set1_pd(2.);
11728 let e: f64 = _mm512_reduce_mul_pd(a);
11729 assert_eq!(256., e);
11730 }
11731
11732 #[simd_test(enable = "avx512f")]
11733 unsafe fn test_mm512_mask_reduce_mul_pd() {
11734 let a = _mm512_set1_pd(2.);
11735 let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11736 assert_eq!(16., e);
11737 }
11738
11739 #[simd_test(enable = "avx512f")]
11740 unsafe fn test_mm512_reduce_max_epi64() {
11741 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11742 let e: i64 = _mm512_reduce_max_epi64(a);
11743 assert_eq!(7, e);
11744 }
11745
11746 #[simd_test(enable = "avx512f")]
11747 unsafe fn test_mm512_mask_reduce_max_epi64() {
11748 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11749 let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11750 assert_eq!(3, e);
11751 }
11752
11753 #[simd_test(enable = "avx512f")]
11754 unsafe fn test_mm512_reduce_max_epu64() {
11755 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11756 let e: u64 = _mm512_reduce_max_epu64(a);
11757 assert_eq!(7, e);
11758 }
11759
11760 #[simd_test(enable = "avx512f")]
11761 unsafe fn test_mm512_mask_reduce_max_epu64() {
11762 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11763 let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11764 assert_eq!(3, e);
11765 }
11766
11767 #[simd_test(enable = "avx512f")]
11768 unsafe fn test_mm512_reduce_max_pd() {
11769 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11770 let e: f64 = _mm512_reduce_max_pd(a);
11771 assert_eq!(7., e);
11772 }
11773
11774 #[simd_test(enable = "avx512f")]
11775 unsafe fn test_mm512_mask_reduce_max_pd() {
11776 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11777 let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11778 assert_eq!(3., e);
11779 }
11780
11781 #[simd_test(enable = "avx512f")]
11782 unsafe fn test_mm512_reduce_min_epi64() {
11783 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11784 let e: i64 = _mm512_reduce_min_epi64(a);
11785 assert_eq!(0, e);
11786 }
11787
11788 #[simd_test(enable = "avx512f")]
11789 unsafe fn test_mm512_mask_reduce_min_epi64() {
11790 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11791 let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11792 assert_eq!(0, e);
11793 }
11794
11795 #[simd_test(enable = "avx512f")]
11796 unsafe fn test_mm512_reduce_min_epu64() {
11797 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11798 let e: u64 = _mm512_reduce_min_epu64(a);
11799 assert_eq!(0, e);
11800 }
11801
11802 #[simd_test(enable = "avx512f")]
11803 unsafe fn test_mm512_mask_reduce_min_epu64() {
11804 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11805 let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11806 assert_eq!(0, e);
11807 }
11808
11809 #[simd_test(enable = "avx512f")]
11810 unsafe fn test_mm512_reduce_min_pd() {
11811 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11812 let e: f64 = _mm512_reduce_min_pd(a);
11813 assert_eq!(0., e);
11814 }
11815
11816 #[simd_test(enable = "avx512f")]
11817 unsafe fn test_mm512_mask_reduce_min_pd() {
11818 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11819 let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11820 assert_eq!(0., e);
11821 }
11822
11823 #[simd_test(enable = "avx512f")]
11824 unsafe fn test_mm512_reduce_and_epi64() {
11825 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11826 let e: i64 = _mm512_reduce_and_epi64(a);
11827 assert_eq!(0, e);
11828 }
11829
11830 #[simd_test(enable = "avx512f")]
11831 unsafe fn test_mm512_mask_reduce_and_epi64() {
11832 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11833 let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11834 assert_eq!(1, e);
11835 }
11836
11837 #[simd_test(enable = "avx512f")]
11838 unsafe fn test_mm512_reduce_or_epi64() {
11839 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11840 let e: i64 = _mm512_reduce_or_epi64(a);
11841 assert_eq!(3, e);
11842 }
11843
11844 #[simd_test(enable = "avx512f")]
11845 unsafe fn test_mm512_mask_reduce_or_epi64() {
11846 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11847 let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11848 assert_eq!(1, e);
11849 }
11850
11851 #[simd_test(enable = "avx512f")]
11852 unsafe fn test_mm512_extractf64x4_pd() {
11853 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11854 let r = _mm512_extractf64x4_pd::<1>(a);
11855 let e = _mm256_setr_pd(5., 6., 7., 8.);
11856 assert_eq_m256d(r, e);
11857 }
11858
11859 #[simd_test(enable = "avx512f")]
11860 unsafe fn test_mm512_mask_extractf64x4_pd() {
11861 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11862 let src = _mm256_set1_pd(100.);
11863 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11864 assert_eq_m256d(r, src);
11865 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11866 let e = _mm256_setr_pd(5., 6., 7., 8.);
11867 assert_eq_m256d(r, e);
11868 }
11869
11870 #[simd_test(enable = "avx512f")]
11871 unsafe fn test_mm512_maskz_extractf64x4_pd() {
11872 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11873 let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11874 assert_eq_m256d(r, _mm256_setzero_pd());
11875 let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11876 let e = _mm256_setr_pd(5., 0., 0., 0.);
11877 assert_eq_m256d(r, e);
11878 }
11879
11880 #[simd_test(enable = "avx512f")]
11881 unsafe fn test_mm512_extracti64x4_epi64() {
11882 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11883 let r = _mm512_extracti64x4_epi64::<0x1>(a);
11884 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11885 assert_eq_m256i(r, e);
11886 }
11887
11888 #[simd_test(enable = "avx512f")]
11889 unsafe fn test_mm512_mask_extracti64x4_epi64() {
11890 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11891 let src = _mm256_set1_epi64x(100);
11892 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11893 assert_eq_m256i(r, src);
11894 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11895 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11896 assert_eq_m256i(r, e);
11897 }
11898
11899 #[simd_test(enable = "avx512f")]
11900 unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11901 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11902 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11903 assert_eq_m256i(r, _mm256_setzero_si256());
11904 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11905 let e = _mm256_setr_epi64x(5, 0, 0, 0);
11906 assert_eq_m256i(r, e);
11907 }
11908
11909 #[simd_test(enable = "avx512f")]
11910 unsafe fn test_mm512_mask_compress_epi64() {
11911 let src = _mm512_set1_epi64(200);
11912 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11913 let r = _mm512_mask_compress_epi64(src, 0, a);
11914 assert_eq_m512i(r, src);
11915 let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11916 let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11917 assert_eq_m512i(r, e);
11918 }
11919
11920 #[simd_test(enable = "avx512f")]
11921 unsafe fn test_mm512_maskz_compress_epi64() {
11922 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11923 let r = _mm512_maskz_compress_epi64(0, a);
11924 assert_eq_m512i(r, _mm512_setzero_si512());
11925 let r = _mm512_maskz_compress_epi64(0b01010101, a);
11926 let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11927 assert_eq_m512i(r, e);
11928 }
11929
11930 #[simd_test(enable = "avx512f,avx512vl")]
11931 unsafe fn test_mm256_mask_compress_epi64() {
11932 let src = _mm256_set1_epi64x(200);
11933 let a = _mm256_set_epi64x(0, 1, 2, 3);
11934 let r = _mm256_mask_compress_epi64(src, 0, a);
11935 assert_eq_m256i(r, src);
11936 let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11937 let e = _mm256_set_epi64x(200, 200, 1, 3);
11938 assert_eq_m256i(r, e);
11939 }
11940
11941 #[simd_test(enable = "avx512f,avx512vl")]
11942 unsafe fn test_mm256_maskz_compress_epi64() {
11943 let a = _mm256_set_epi64x(0, 1, 2, 3);
11944 let r = _mm256_maskz_compress_epi64(0, a);
11945 assert_eq_m256i(r, _mm256_setzero_si256());
11946 let r = _mm256_maskz_compress_epi64(0b00000101, a);
11947 let e = _mm256_set_epi64x(0, 0, 1, 3);
11948 assert_eq_m256i(r, e);
11949 }
11950
11951 #[simd_test(enable = "avx512f,avx512vl")]
11952 unsafe fn test_mm_mask_compress_epi64() {
11953 let src = _mm_set1_epi64x(200);
11954 let a = _mm_set_epi64x(0, 1);
11955 let r = _mm_mask_compress_epi64(src, 0, a);
11956 assert_eq_m128i(r, src);
11957 let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11958 let e = _mm_set_epi64x(200, 1);
11959 assert_eq_m128i(r, e);
11960 }
11961
11962 #[simd_test(enable = "avx512f,avx512vl")]
11963 unsafe fn test_mm_maskz_compress_epi64() {
11964 let a = _mm_set_epi64x(0, 1);
11965 let r = _mm_maskz_compress_epi64(0, a);
11966 assert_eq_m128i(r, _mm_setzero_si128());
11967 let r = _mm_maskz_compress_epi64(0b00000001, a);
11968 let e = _mm_set_epi64x(0, 1);
11969 assert_eq_m128i(r, e);
11970 }
11971
11972 #[simd_test(enable = "avx512f")]
11973 unsafe fn test_mm512_mask_compress_pd() {
11974 let src = _mm512_set1_pd(200.);
11975 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11976 let r = _mm512_mask_compress_pd(src, 0, a);
11977 assert_eq_m512d(r, src);
11978 let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11979 let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11980 assert_eq_m512d(r, e);
11981 }
11982
11983 #[simd_test(enable = "avx512f")]
11984 unsafe fn test_mm512_maskz_compress_pd() {
11985 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11986 let r = _mm512_maskz_compress_pd(0, a);
11987 assert_eq_m512d(r, _mm512_setzero_pd());
11988 let r = _mm512_maskz_compress_pd(0b01010101, a);
11989 let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11990 assert_eq_m512d(r, e);
11991 }
11992
11993 #[simd_test(enable = "avx512f,avx512vl")]
11994 unsafe fn test_mm256_mask_compress_pd() {
11995 let src = _mm256_set1_pd(200.);
11996 let a = _mm256_set_pd(0., 1., 2., 3.);
11997 let r = _mm256_mask_compress_pd(src, 0, a);
11998 assert_eq_m256d(r, src);
11999 let r = _mm256_mask_compress_pd(src, 0b00000101, a);
12000 let e = _mm256_set_pd(200., 200., 1., 3.);
12001 assert_eq_m256d(r, e);
12002 }
12003
12004 #[simd_test(enable = "avx512f,avx512vl")]
12005 unsafe fn test_mm256_maskz_compress_pd() {
12006 let a = _mm256_set_pd(0., 1., 2., 3.);
12007 let r = _mm256_maskz_compress_pd(0, a);
12008 assert_eq_m256d(r, _mm256_setzero_pd());
12009 let r = _mm256_maskz_compress_pd(0b00000101, a);
12010 let e = _mm256_set_pd(0., 0., 1., 3.);
12011 assert_eq_m256d(r, e);
12012 }
12013
12014 #[simd_test(enable = "avx512f,avx512vl")]
12015 unsafe fn test_mm_mask_compress_pd() {
12016 let src = _mm_set1_pd(200.);
12017 let a = _mm_set_pd(0., 1.);
12018 let r = _mm_mask_compress_pd(src, 0, a);
12019 assert_eq_m128d(r, src);
12020 let r = _mm_mask_compress_pd(src, 0b00000001, a);
12021 let e = _mm_set_pd(200., 1.);
12022 assert_eq_m128d(r, e);
12023 }
12024
12025 #[simd_test(enable = "avx512f,avx512vl")]
12026 unsafe fn test_mm_maskz_compress_pd() {
12027 let a = _mm_set_pd(0., 1.);
12028 let r = _mm_maskz_compress_pd(0, a);
12029 assert_eq_m128d(r, _mm_setzero_pd());
12030 let r = _mm_maskz_compress_pd(0b00000001, a);
12031 let e = _mm_set_pd(0., 1.);
12032 assert_eq_m128d(r, e);
12033 }
12034
12035 #[simd_test(enable = "avx512f")]
12036 unsafe fn test_mm512_mask_expand_epi64() {
12037 let src = _mm512_set1_epi64(200);
12038 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12039 let r = _mm512_mask_expand_epi64(src, 0, a);
12040 assert_eq_m512i(r, src);
12041 let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
12042 let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
12043 assert_eq_m512i(r, e);
12044 }
12045
12046 #[simd_test(enable = "avx512f")]
12047 unsafe fn test_mm512_maskz_expand_epi64() {
12048 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12049 let r = _mm512_maskz_expand_epi64(0, a);
12050 assert_eq_m512i(r, _mm512_setzero_si512());
12051 let r = _mm512_maskz_expand_epi64(0b01010101, a);
12052 let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
12053 assert_eq_m512i(r, e);
12054 }
12055
12056 #[simd_test(enable = "avx512f,avx512vl")]
12057 unsafe fn test_mm256_mask_expand_epi64() {
12058 let src = _mm256_set1_epi64x(200);
12059 let a = _mm256_set_epi64x(0, 1, 2, 3);
12060 let r = _mm256_mask_expand_epi64(src, 0, a);
12061 assert_eq_m256i(r, src);
12062 let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
12063 let e = _mm256_set_epi64x(200, 2, 200, 3);
12064 assert_eq_m256i(r, e);
12065 }
12066
12067 #[simd_test(enable = "avx512f,avx512vl")]
12068 unsafe fn test_mm256_maskz_expand_epi64() {
12069 let a = _mm256_set_epi64x(0, 1, 2, 3);
12070 let r = _mm256_maskz_expand_epi64(0, a);
12071 assert_eq_m256i(r, _mm256_setzero_si256());
12072 let r = _mm256_maskz_expand_epi64(0b00000101, a);
12073 let e = _mm256_set_epi64x(0, 2, 0, 3);
12074 assert_eq_m256i(r, e);
12075 }
12076
12077 #[simd_test(enable = "avx512f,avx512vl")]
12078 unsafe fn test_mm_mask_expand_epi64() {
12079 let src = _mm_set1_epi64x(200);
12080 let a = _mm_set_epi64x(0, 1);
12081 let r = _mm_mask_expand_epi64(src, 0, a);
12082 assert_eq_m128i(r, src);
12083 let r = _mm_mask_expand_epi64(src, 0b00000001, a);
12084 let e = _mm_set_epi64x(200, 1);
12085 assert_eq_m128i(r, e);
12086 }
12087
12088 #[simd_test(enable = "avx512f,avx512vl")]
12089 unsafe fn test_mm_maskz_expand_epi64() {
12090 let a = _mm_set_epi64x(0, 1);
12091 let r = _mm_maskz_expand_epi64(0, a);
12092 assert_eq_m128i(r, _mm_setzero_si128());
12093 let r = _mm_maskz_expand_epi64(0b00000001, a);
12094 let e = _mm_set_epi64x(0, 1);
12095 assert_eq_m128i(r, e);
12096 }
12097
12098 #[simd_test(enable = "avx512f")]
12099 unsafe fn test_mm512_mask_expand_pd() {
12100 let src = _mm512_set1_pd(200.);
12101 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12102 let r = _mm512_mask_expand_pd(src, 0, a);
12103 assert_eq_m512d(r, src);
12104 let r = _mm512_mask_expand_pd(src, 0b01010101, a);
12105 let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
12106 assert_eq_m512d(r, e);
12107 }
12108
12109 #[simd_test(enable = "avx512f")]
12110 unsafe fn test_mm512_maskz_expand_pd() {
12111 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12112 let r = _mm512_maskz_expand_pd(0, a);
12113 assert_eq_m512d(r, _mm512_setzero_pd());
12114 let r = _mm512_maskz_expand_pd(0b01010101, a);
12115 let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
12116 assert_eq_m512d(r, e);
12117 }
12118
12119 #[simd_test(enable = "avx512f,avx512vl")]
12120 unsafe fn test_mm256_mask_expand_pd() {
12121 let src = _mm256_set1_pd(200.);
12122 let a = _mm256_set_pd(0., 1., 2., 3.);
12123 let r = _mm256_mask_expand_pd(src, 0, a);
12124 assert_eq_m256d(r, src);
12125 let r = _mm256_mask_expand_pd(src, 0b00000101, a);
12126 let e = _mm256_set_pd(200., 2., 200., 3.);
12127 assert_eq_m256d(r, e);
12128 }
12129
12130 #[simd_test(enable = "avx512f,avx512vl")]
12131 unsafe fn test_mm256_maskz_expand_pd() {
12132 let a = _mm256_set_pd(0., 1., 2., 3.);
12133 let r = _mm256_maskz_expand_pd(0, a);
12134 assert_eq_m256d(r, _mm256_setzero_pd());
12135 let r = _mm256_maskz_expand_pd(0b00000101, a);
12136 let e = _mm256_set_pd(0., 2., 0., 3.);
12137 assert_eq_m256d(r, e);
12138 }
12139
12140 #[simd_test(enable = "avx512f,avx512vl")]
12141 unsafe fn test_mm_mask_expand_pd() {
12142 let src = _mm_set1_pd(200.);
12143 let a = _mm_set_pd(0., 1.);
12144 let r = _mm_mask_expand_pd(src, 0, a);
12145 assert_eq_m128d(r, src);
12146 let r = _mm_mask_expand_pd(src, 0b00000001, a);
12147 let e = _mm_set_pd(200., 1.);
12148 assert_eq_m128d(r, e);
12149 }
12150
12151 #[simd_test(enable = "avx512f,avx512vl")]
12152 unsafe fn test_mm_maskz_expand_pd() {
12153 let a = _mm_set_pd(0., 1.);
12154 let r = _mm_maskz_expand_pd(0, a);
12155 assert_eq_m128d(r, _mm_setzero_pd());
12156 let r = _mm_maskz_expand_pd(0b00000001, a);
12157 let e = _mm_set_pd(0., 1.);
12158 assert_eq_m128d(r, e);
12159 }
12160
12161 #[simd_test(enable = "avx512f")]
12162 unsafe fn test_mm512_loadu_epi64() {
12163 let a = &[4, 3, 2, 5, -8, -9, -64, -50];
12164 let p = a.as_ptr();
12165 let r = _mm512_loadu_epi64(black_box(p));
12166 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12167 assert_eq_m512i(r, e);
12168 }
12169
12170 #[simd_test(enable = "avx512f,avx512vl")]
12171 unsafe fn test_mm256_loadu_epi64() {
12172 let a = &[4, 3, 2, 5];
12173 let p = a.as_ptr();
12174 let r = _mm256_loadu_epi64(black_box(p));
12175 let e = _mm256_setr_epi64x(4, 3, 2, 5);
12176 assert_eq_m256i(r, e);
12177 }
12178
12179 #[simd_test(enable = "avx512f,avx512vl")]
12180 unsafe fn test_mm_loadu_epi64() {
12181 let a = &[4, 3];
12182 let p = a.as_ptr();
12183 let r = _mm_loadu_epi64(black_box(p));
12184 let e = _mm_setr_epi64x(4, 3);
12185 assert_eq_m128i(r, e);
12186 }
12187
12188 #[simd_test(enable = "avx512f")]
12189 unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
12190 let a = _mm512_set1_epi64(9);
12191 let mut r = _mm_undefined_si128();
12192 _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12193 let e = _mm_set1_epi16(9);
12194 assert_eq_m128i(r, e);
12195 }
12196
12197 #[simd_test(enable = "avx512f,avx512vl")]
12198 unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
12199 let a = _mm256_set1_epi64x(9);
12200 let mut r = _mm_set1_epi16(0);
12201 _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12202 let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
12203 assert_eq_m128i(r, e);
12204 }
12205
12206 #[simd_test(enable = "avx512f,avx512vl")]
12207 unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
12208 let a = _mm_set1_epi64x(9);
12209 let mut r = _mm_set1_epi16(0);
12210 _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12211 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
12212 assert_eq_m128i(r, e);
12213 }
12214
12215 #[simd_test(enable = "avx512f")]
12216 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
12217 let a = _mm512_set1_epi64(i64::MAX);
12218 let mut r = _mm_undefined_si128();
12219 _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12220 let e = _mm_set1_epi16(i16::MAX);
12221 assert_eq_m128i(r, e);
12222 }
12223
12224 #[simd_test(enable = "avx512f,avx512vl")]
12225 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
12226 let a = _mm256_set1_epi64x(i64::MAX);
12227 let mut r = _mm_set1_epi16(0);
12228 _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12229 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
12230 assert_eq_m128i(r, e);
12231 }
12232
12233 #[simd_test(enable = "avx512f,avx512vl")]
12234 unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
12235 let a = _mm_set1_epi64x(i64::MAX);
12236 let mut r = _mm_set1_epi16(0);
12237 _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12238 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
12239 assert_eq_m128i(r, e);
12240 }
12241
12242 #[simd_test(enable = "avx512f")]
12243 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
12244 let a = _mm512_set1_epi64(i64::MAX);
12245 let mut r = _mm_undefined_si128();
12246 _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12247 let e = _mm_set1_epi16(u16::MAX as i16);
12248 assert_eq_m128i(r, e);
12249 }
12250
12251 #[simd_test(enable = "avx512f,avx512vl")]
12252 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
12253 let a = _mm256_set1_epi64x(i64::MAX);
12254 let mut r = _mm_set1_epi16(0);
12255 _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12256 let e = _mm_set_epi16(
12257 0,
12258 0,
12259 0,
12260 0,
12261 u16::MAX as i16,
12262 u16::MAX as i16,
12263 u16::MAX as i16,
12264 u16::MAX as i16,
12265 );
12266 assert_eq_m128i(r, e);
12267 }
12268
12269 #[simd_test(enable = "avx512f,avx512vl")]
12270 unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
12271 let a = _mm_set1_epi64x(i64::MAX);
12272 let mut r = _mm_set1_epi16(0);
12273 _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12274 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
12275 assert_eq_m128i(r, e);
12276 }
12277
12278 #[simd_test(enable = "avx512f")]
12279 unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
12280 let a = _mm512_set1_epi64(9);
12281 let mut r = _mm_set1_epi8(0);
12282 _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12283 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
12284 assert_eq_m128i(r, e);
12285 }
12286
12287 #[simd_test(enable = "avx512f,avx512vl")]
12288 unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
12289 let a = _mm256_set1_epi64x(9);
12290 let mut r = _mm_set1_epi8(0);
12291 _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12292 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
12293 assert_eq_m128i(r, e);
12294 }
12295
12296 #[simd_test(enable = "avx512f,avx512vl")]
12297 unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
12298 let a = _mm_set1_epi64x(9);
12299 let mut r = _mm_set1_epi8(0);
12300 _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12301 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
12302 assert_eq_m128i(r, e);
12303 }
12304
12305 #[simd_test(enable = "avx512f")]
12306 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
12307 let a = _mm512_set1_epi64(i64::MAX);
12308 let mut r = _mm_set1_epi8(0);
12309 _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12310 #[rustfmt::skip]
12311 let e = _mm_set_epi8(
12312 0, 0, 0, 0,
12313 0, 0, 0, 0,
12314 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12315 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12316 );
12317 assert_eq_m128i(r, e);
12318 }
12319
12320 #[simd_test(enable = "avx512f,avx512vl")]
12321 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
12322 let a = _mm256_set1_epi64x(i64::MAX);
12323 let mut r = _mm_set1_epi8(0);
12324 _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12325 #[rustfmt::skip]
12326 let e = _mm_set_epi8(
12327 0, 0, 0, 0,
12328 0, 0, 0, 0,
12329 0, 0, 0, 0,
12330 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12331 );
12332 assert_eq_m128i(r, e);
12333 }
12334
12335 #[simd_test(enable = "avx512f,avx512vl")]
12336 unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
12337 let a = _mm_set1_epi64x(i64::MAX);
12338 let mut r = _mm_set1_epi8(0);
12339 _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12340 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
12341 assert_eq_m128i(r, e);
12342 }
12343
12344 #[simd_test(enable = "avx512f")]
12345 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
12346 let a = _mm512_set1_epi64(i64::MAX);
12347 let mut r = _mm_set1_epi8(0);
12348 _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12349 #[rustfmt::skip]
12350 let e = _mm_set_epi8(
12351 0, 0, 0, 0,
12352 0, 0, 0, 0,
12353 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12354 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12355 );
12356 assert_eq_m128i(r, e);
12357 }
12358
12359 #[simd_test(enable = "avx512f,avx512vl")]
12360 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
12361 let a = _mm256_set1_epi64x(i64::MAX);
12362 let mut r = _mm_set1_epi8(0);
12363 _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12364 #[rustfmt::skip]
12365 let e = _mm_set_epi8(
12366 0, 0, 0, 0,
12367 0, 0, 0, 0,
12368 0, 0, 0, 0,
12369 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12370 );
12371 assert_eq_m128i(r, e);
12372 }
12373
12374 #[simd_test(enable = "avx512f,avx512vl")]
12375 unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
12376 let a = _mm_set1_epi64x(i64::MAX);
12377 let mut r = _mm_set1_epi8(0);
12378 _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12379 #[rustfmt::skip]
12380 let e = _mm_set_epi8(
12381 0, 0, 0, 0,
12382 0, 0, 0, 0,
12383 0, 0, 0, 0,
12384 0, 0, u8::MAX as i8, u8::MAX as i8,
12385 );
12386 assert_eq_m128i(r, e);
12387 }
12388
12389 #[simd_test(enable = "avx512f")]
12390 unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
12391 let a = _mm512_set1_epi64(9);
12392 let mut r = _mm256_undefined_si256();
12393 _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12394 let e = _mm256_set1_epi32(9);
12395 assert_eq_m256i(r, e);
12396 }
12397
12398 #[simd_test(enable = "avx512f,avx512vl")]
12399 unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
12400 let a = _mm256_set1_epi64x(9);
12401 let mut r = _mm_set1_epi32(0);
12402 _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12403 let e = _mm_set_epi32(9, 9, 9, 9);
12404 assert_eq_m128i(r, e);
12405 }
12406
12407 #[simd_test(enable = "avx512f,avx512vl")]
12408 unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
12409 let a = _mm_set1_epi64x(9);
12410 let mut r = _mm_set1_epi16(0);
12411 _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12412 let e = _mm_set_epi32(0, 0, 9, 9);
12413 assert_eq_m128i(r, e);
12414 }
12415
12416 #[simd_test(enable = "avx512f")]
12417 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
12418 let a = _mm512_set1_epi64(i64::MAX);
12419 let mut r = _mm256_undefined_si256();
12420 _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12421 let e = _mm256_set1_epi32(i32::MAX);
12422 assert_eq_m256i(r, e);
12423 }
12424
12425 #[simd_test(enable = "avx512f,avx512vl")]
12426 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
12427 let a = _mm256_set1_epi64x(i64::MAX);
12428 let mut r = _mm_set1_epi32(0);
12429 _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12430 let e = _mm_set1_epi32(i32::MAX);
12431 assert_eq_m128i(r, e);
12432 }
12433
12434 #[simd_test(enable = "avx512f,avx512vl")]
12435 unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
12436 let a = _mm_set1_epi64x(i64::MAX);
12437 let mut r = _mm_set1_epi16(0);
12438 _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12439 let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
12440 assert_eq_m128i(r, e);
12441 }
12442
12443 #[simd_test(enable = "avx512f")]
12444 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
12445 let a = _mm512_set1_epi64(i64::MAX);
12446 let mut r = _mm256_undefined_si256();
12447 _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12448 let e = _mm256_set1_epi32(u32::MAX as i32);
12449 assert_eq_m256i(r, e);
12450 }
12451
12452 #[simd_test(enable = "avx512f,avx512vl")]
12453 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
12454 let a = _mm256_set1_epi64x(i64::MAX);
12455 let mut r = _mm_set1_epi32(0);
12456 _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12457 let e = _mm_set1_epi32(u32::MAX as i32);
12458 assert_eq_m128i(r, e);
12459 }
12460
12461 #[simd_test(enable = "avx512f,avx512vl")]
12462 unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
12463 let a = _mm_set1_epi64x(i64::MAX);
12464 let mut r = _mm_set1_epi16(0);
12465 _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12466 let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
12467 assert_eq_m128i(r, e);
12468 }
12469
12470 #[simd_test(enable = "avx512f")]
12471 unsafe fn test_mm512_storeu_epi64() {
12472 let a = _mm512_set1_epi64(9);
12473 let mut r = _mm512_set1_epi64(0);
12474 _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12475 assert_eq_m512i(r, a);
12476 }
12477
12478 #[simd_test(enable = "avx512f,avx512vl")]
12479 unsafe fn test_mm256_storeu_epi64() {
12480 let a = _mm256_set1_epi64x(9);
12481 let mut r = _mm256_set1_epi64x(0);
12482 _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12483 assert_eq_m256i(r, a);
12484 }
12485
12486 #[simd_test(enable = "avx512f,avx512vl")]
12487 unsafe fn test_mm_storeu_epi64() {
12488 let a = _mm_set1_epi64x(9);
12489 let mut r = _mm_set1_epi64x(0);
12490 _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12491 assert_eq_m128i(r, a);
12492 }
12493
12494 #[simd_test(enable = "avx512f")]
12495 unsafe fn test_mm512_load_epi64() {
12496 #[repr(align(64))]
12497 struct Align {
12498 data: [i64; 8], // 64 bytes
12499 }
12500 let a = Align {
12501 data: [4, 3, 2, 5, -8, -9, -64, -50],
12502 };
12503 let p = (a.data).as_ptr();
12504 let r = _mm512_load_epi64(black_box(p));
12505 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12506 assert_eq_m512i(r, e);
12507 }
12508
12509 #[simd_test(enable = "avx512f,avx512vl")]
12510 unsafe fn test_mm256_load_epi64() {
12511 #[repr(align(64))]
12512 struct Align {
12513 data: [i64; 4],
12514 }
12515 let a = Align { data: [4, 3, 2, 5] };
12516 let p = (a.data).as_ptr();
12517 let r = _mm256_load_epi64(black_box(p));
12518 let e = _mm256_set_epi64x(5, 2, 3, 4);
12519 assert_eq_m256i(r, e);
12520 }
12521
12522 #[simd_test(enable = "avx512f,avx512vl")]
12523 unsafe fn test_mm_load_epi64() {
12524 #[repr(align(64))]
12525 struct Align {
12526 data: [i64; 2],
12527 }
12528 let a = Align { data: [4, 3] };
12529 let p = (a.data).as_ptr();
12530 let r = _mm_load_epi64(black_box(p));
12531 let e = _mm_set_epi64x(3, 4);
12532 assert_eq_m128i(r, e);
12533 }
12534
12535 #[simd_test(enable = "avx512f")]
12536 unsafe fn test_mm512_store_epi64() {
12537 let a = _mm512_set1_epi64(9);
12538 let mut r = _mm512_set1_epi64(0);
12539 _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
12540 assert_eq_m512i(r, a);
12541 }
12542
12543 #[simd_test(enable = "avx512f,avx512vl")]
12544 unsafe fn test_mm256_store_epi64() {
12545 let a = _mm256_set1_epi64x(9);
12546 let mut r = _mm256_set1_epi64x(0);
12547 _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
12548 assert_eq_m256i(r, a);
12549 }
12550
12551 #[simd_test(enable = "avx512f,avx512vl")]
12552 unsafe fn test_mm_store_epi64() {
12553 let a = _mm_set1_epi64x(9);
12554 let mut r = _mm_set1_epi64x(0);
12555 _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
12556 assert_eq_m128i(r, a);
12557 }
12558
12559 #[simd_test(enable = "avx512f")]
12560 unsafe fn test_mm512_load_pd() {
12561 #[repr(align(64))]
12562 struct Align {
12563 data: [f64; 8], // 64 bytes
12564 }
12565 let a = Align {
12566 data: [4., 3., 2., 5., -8., -9., -64., -50.],
12567 };
12568 let p = (a.data).as_ptr();
12569 let r = _mm512_load_pd(black_box(p));
12570 let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
12571 assert_eq_m512d(r, e);
12572 }
12573
12574 #[simd_test(enable = "avx512f")]
12575 unsafe fn test_mm512_store_pd() {
12576 let a = _mm512_set1_pd(9.);
12577 let mut r = _mm512_undefined_pd();
12578 _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
12579 assert_eq_m512d(r, a);
12580 }
12581
12582 #[simd_test(enable = "avx512f")]
12583 unsafe fn test_mm512_test_epi64_mask() {
12584 let a = _mm512_set1_epi64(1 << 0);
12585 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12586 let r = _mm512_test_epi64_mask(a, b);
12587 let e: __mmask8 = 0b11111111;
12588 assert_eq!(r, e);
12589 }
12590
12591 #[simd_test(enable = "avx512f")]
12592 unsafe fn test_mm512_mask_test_epi64_mask() {
12593 let a = _mm512_set1_epi64(1 << 0);
12594 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12595 let r = _mm512_mask_test_epi64_mask(0, a, b);
12596 assert_eq!(r, 0);
12597 let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
12598 let e: __mmask8 = 0b11111111;
12599 assert_eq!(r, e);
12600 }
12601
12602 #[simd_test(enable = "avx512f,avx512vl")]
12603 unsafe fn test_mm256_test_epi64_mask() {
12604 let a = _mm256_set1_epi64x(1 << 0);
12605 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12606 let r = _mm256_test_epi64_mask(a, b);
12607 let e: __mmask8 = 0b00001111;
12608 assert_eq!(r, e);
12609 }
12610
12611 #[simd_test(enable = "avx512f,avx512vl")]
12612 unsafe fn test_mm256_mask_test_epi64_mask() {
12613 let a = _mm256_set1_epi64x(1 << 0);
12614 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12615 let r = _mm256_mask_test_epi64_mask(0, a, b);
12616 assert_eq!(r, 0);
12617 let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
12618 let e: __mmask8 = 0b00001111;
12619 assert_eq!(r, e);
12620 }
12621
12622 #[simd_test(enable = "avx512f,avx512vl")]
12623 unsafe fn test_mm_test_epi64_mask() {
12624 let a = _mm_set1_epi64x(1 << 0);
12625 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12626 let r = _mm_test_epi64_mask(a, b);
12627 let e: __mmask8 = 0b00000011;
12628 assert_eq!(r, e);
12629 }
12630
12631 #[simd_test(enable = "avx512f,avx512vl")]
12632 unsafe fn test_mm_mask_test_epi64_mask() {
12633 let a = _mm_set1_epi64x(1 << 0);
12634 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12635 let r = _mm_mask_test_epi64_mask(0, a, b);
12636 assert_eq!(r, 0);
12637 let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
12638 let e: __mmask8 = 0b00000011;
12639 assert_eq!(r, e);
12640 }
12641
12642 #[simd_test(enable = "avx512f")]
12643 unsafe fn test_mm512_testn_epi64_mask() {
12644 let a = _mm512_set1_epi64(1 << 0);
12645 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12646 let r = _mm512_testn_epi64_mask(a, b);
12647 let e: __mmask8 = 0b00000000;
12648 assert_eq!(r, e);
12649 }
12650
12651 #[simd_test(enable = "avx512f")]
12652 unsafe fn test_mm512_mask_testn_epi64_mask() {
12653 let a = _mm512_set1_epi64(1 << 0);
12654 let b = _mm512_set1_epi64(1 << 1);
12655 let r = _mm512_mask_testn_epi64_mask(0, a, b);
12656 assert_eq!(r, 0);
12657 let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
12658 let e: __mmask8 = 0b11111111;
12659 assert_eq!(r, e);
12660 }
12661
12662 #[simd_test(enable = "avx512f,avx512vl")]
12663 unsafe fn test_mm256_testn_epi64_mask() {
12664 let a = _mm256_set1_epi64x(1 << 0);
12665 let b = _mm256_set1_epi64x(1 << 1);
12666 let r = _mm256_testn_epi64_mask(a, b);
12667 let e: __mmask8 = 0b00001111;
12668 assert_eq!(r, e);
12669 }
12670
12671 #[simd_test(enable = "avx512f,avx512vl")]
12672 unsafe fn test_mm256_mask_testn_epi64_mask() {
12673 let a = _mm256_set1_epi64x(1 << 0);
12674 let b = _mm256_set1_epi64x(1 << 1);
12675 let r = _mm256_mask_testn_epi64_mask(0, a, b);
12676 assert_eq!(r, 0);
12677 let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
12678 let e: __mmask8 = 0b00001111;
12679 assert_eq!(r, e);
12680 }
12681
12682 #[simd_test(enable = "avx512f,avx512vl")]
12683 unsafe fn test_mm_testn_epi64_mask() {
12684 let a = _mm_set1_epi64x(1 << 0);
12685 let b = _mm_set1_epi64x(1 << 1);
12686 let r = _mm_testn_epi64_mask(a, b);
12687 let e: __mmask8 = 0b00000011;
12688 assert_eq!(r, e);
12689 }
12690
12691 #[simd_test(enable = "avx512f,avx512vl")]
12692 unsafe fn test_mm_mask_testn_epi64_mask() {
12693 let a = _mm_set1_epi64x(1 << 0);
12694 let b = _mm_set1_epi64x(1 << 1);
12695 let r = _mm_mask_testn_epi64_mask(0, a, b);
12696 assert_eq!(r, 0);
12697 let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12698 let e: __mmask8 = 0b00000011;
12699 assert_eq!(r, e);
12700 }
12701
12702 #[simd_test(enable = "avx512f")]
12703 unsafe fn test_mm512_mask_set1_epi64() {
12704 let src = _mm512_set1_epi64(2);
12705 let a: i64 = 11;
12706 let r = _mm512_mask_set1_epi64(src, 0, a);
12707 assert_eq_m512i(r, src);
12708 let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12709 let e = _mm512_set1_epi64(11);
12710 assert_eq_m512i(r, e);
12711 }
12712
12713 #[simd_test(enable = "avx512f")]
12714 unsafe fn test_mm512_maskz_set1_epi64() {
12715 let a: i64 = 11;
12716 let r = _mm512_maskz_set1_epi64(0, a);
12717 assert_eq_m512i(r, _mm512_setzero_si512());
12718 let r = _mm512_maskz_set1_epi64(0b11111111, a);
12719 let e = _mm512_set1_epi64(11);
12720 assert_eq_m512i(r, e);
12721 }
12722
12723 #[simd_test(enable = "avx512f,avx512vl")]
12724 unsafe fn test_mm256_mask_set1_epi64() {
12725 let src = _mm256_set1_epi64x(2);
12726 let a: i64 = 11;
12727 let r = _mm256_mask_set1_epi64(src, 0, a);
12728 assert_eq_m256i(r, src);
12729 let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12730 let e = _mm256_set1_epi64x(11);
12731 assert_eq_m256i(r, e);
12732 }
12733
12734 #[simd_test(enable = "avx512f,avx512vl")]
12735 unsafe fn test_mm256_maskz_set1_epi64() {
12736 let a: i64 = 11;
12737 let r = _mm256_maskz_set1_epi64(0, a);
12738 assert_eq_m256i(r, _mm256_setzero_si256());
12739 let r = _mm256_maskz_set1_epi64(0b00001111, a);
12740 let e = _mm256_set1_epi64x(11);
12741 assert_eq_m256i(r, e);
12742 }
12743
12744 #[simd_test(enable = "avx512f,avx512vl")]
12745 unsafe fn test_mm_mask_set1_epi64() {
12746 let src = _mm_set1_epi64x(2);
12747 let a: i64 = 11;
12748 let r = _mm_mask_set1_epi64(src, 0, a);
12749 assert_eq_m128i(r, src);
12750 let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12751 let e = _mm_set1_epi64x(11);
12752 assert_eq_m128i(r, e);
12753 }
12754
12755 #[simd_test(enable = "avx512f,avx512vl")]
12756 unsafe fn test_mm_maskz_set1_epi64() {
12757 let a: i64 = 11;
12758 let r = _mm_maskz_set1_epi64(0, a);
12759 assert_eq_m128i(r, _mm_setzero_si128());
12760 let r = _mm_maskz_set1_epi64(0b00000011, a);
12761 let e = _mm_set1_epi64x(11);
12762 assert_eq_m128i(r, e);
12763 }
12764
12765 #[simd_test(enable = "avx512f")]
12766 unsafe fn test_mm_cvtsd_i64() {
12767 let a = _mm_set_pd(1., -1.5);
12768 let r = _mm_cvtsd_i64(a);
12769 let e: i64 = -2;
12770 assert_eq!(r, e);
12771 }
12772
12773 #[simd_test(enable = "avx512f")]
12774 unsafe fn test_mm_cvtss_i64() {
12775 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12776 let r = _mm_cvtss_i64(a);
12777 let e: i64 = -2;
12778 assert_eq!(r, e);
12779 }
12780
12781 #[simd_test(enable = "avx512f")]
12782 unsafe fn test_mm_cvt_roundi64_ss() {
12783 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12784 let b: i64 = 9;
12785 let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12786 let e = _mm_set_ps(0., -0.5, 1., 9.);
12787 assert_eq_m128(r, e);
12788 }
12789
12790 #[simd_test(enable = "avx512f")]
12791 unsafe fn test_mm_cvt_roundsi64_ss() {
12792 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12793 let b: i64 = 9;
12794 let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12795 let e = _mm_set_ps(0., -0.5, 1., 9.);
12796 assert_eq_m128(r, e);
12797 }
12798
12799 #[simd_test(enable = "avx512f")]
12800 unsafe fn test_mm_cvti64_ss() {
12801 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12802 let b: i64 = 9;
12803 let r = _mm_cvti64_ss(a, b);
12804 let e = _mm_set_ps(0., -0.5, 1., 9.);
12805 assert_eq_m128(r, e);
12806 }
12807
12808 #[simd_test(enable = "avx512f")]
12809 unsafe fn test_mm_cvti64_sd() {
12810 let a = _mm_set_pd(1., -1.5);
12811 let b: i64 = 9;
12812 let r = _mm_cvti64_sd(a, b);
12813 let e = _mm_set_pd(1., 9.);
12814 assert_eq_m128d(r, e);
12815 }
12816
12817 #[simd_test(enable = "avx512f")]
12818 unsafe fn test_mm_cvt_roundsd_si64() {
12819 let a = _mm_set_pd(1., -1.5);
12820 let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12821 let e: i64 = -1;
12822 assert_eq!(r, e);
12823 }
12824
12825 #[simd_test(enable = "avx512f")]
12826 unsafe fn test_mm_cvt_roundsd_i64() {
12827 let a = _mm_set_pd(1., -1.5);
12828 let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12829 let e: i64 = -1;
12830 assert_eq!(r, e);
12831 }
12832
12833 #[simd_test(enable = "avx512f")]
12834 unsafe fn test_mm_cvt_roundsd_u64() {
12835 let a = _mm_set_pd(1., f64::MAX);
12836 let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12837 let e: u64 = u64::MAX;
12838 assert_eq!(r, e);
12839 }
12840
12841 #[simd_test(enable = "avx512f")]
12842 unsafe fn test_mm_cvtsd_u64() {
12843 let a = _mm_set_pd(1., -1.5);
12844 let r = _mm_cvtsd_u64(a);
12845 let e: u64 = u64::MAX;
12846 assert_eq!(r, e);
12847 }
12848
12849 #[simd_test(enable = "avx512f")]
12850 unsafe fn test_mm_cvt_roundss_i64() {
12851 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12852 let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12853 let e: i64 = -1;
12854 assert_eq!(r, e);
12855 }
12856
12857 #[simd_test(enable = "avx512f")]
12858 unsafe fn test_mm_cvt_roundss_si64() {
12859 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12860 let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12861 let e: i64 = -1;
12862 assert_eq!(r, e);
12863 }
12864
12865 #[simd_test(enable = "avx512f")]
12866 unsafe fn test_mm_cvt_roundss_u64() {
12867 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12868 let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12869 let e: u64 = u64::MAX;
12870 assert_eq!(r, e);
12871 }
12872
12873 #[simd_test(enable = "avx512f")]
12874 unsafe fn test_mm_cvtss_u64() {
12875 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12876 let r = _mm_cvtss_u64(a);
12877 let e: u64 = u64::MAX;
12878 assert_eq!(r, e);
12879 }
12880
12881 #[simd_test(enable = "avx512f")]
12882 unsafe fn test_mm_cvttsd_i64() {
12883 let a = _mm_set_pd(1., -1.5);
12884 let r = _mm_cvttsd_i64(a);
12885 let e: i64 = -1;
12886 assert_eq!(r, e);
12887 }
12888
12889 #[simd_test(enable = "avx512f")]
12890 unsafe fn test_mm_cvtt_roundsd_i64() {
12891 let a = _mm_set_pd(1., -1.5);
12892 let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
12893 let e: i64 = -1;
12894 assert_eq!(r, e);
12895 }
12896
12897 #[simd_test(enable = "avx512f")]
12898 unsafe fn test_mm_cvtt_roundsd_si64() {
12899 let a = _mm_set_pd(1., -1.5);
12900 let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
12901 let e: i64 = -1;
12902 assert_eq!(r, e);
12903 }
12904
12905 #[simd_test(enable = "avx512f")]
12906 unsafe fn test_mm_cvtt_roundsd_u64() {
12907 let a = _mm_set_pd(1., -1.5);
12908 let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
12909 let e: u64 = u64::MAX;
12910 assert_eq!(r, e);
12911 }
12912
12913 #[simd_test(enable = "avx512f")]
12914 unsafe fn test_mm_cvttsd_u64() {
12915 let a = _mm_set_pd(1., -1.5);
12916 let r = _mm_cvttsd_u64(a);
12917 let e: u64 = u64::MAX;
12918 assert_eq!(r, e);
12919 }
12920
12921 #[simd_test(enable = "avx512f")]
12922 unsafe fn test_mm_cvttss_i64() {
12923 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12924 let r = _mm_cvttss_i64(a);
12925 let e: i64 = -1;
12926 assert_eq!(r, e);
12927 }
12928
12929 #[simd_test(enable = "avx512f")]
12930 unsafe fn test_mm_cvtt_roundss_i64() {
12931 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12932 let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
12933 let e: i64 = -1;
12934 assert_eq!(r, e);
12935 }
12936
12937 #[simd_test(enable = "avx512f")]
12938 unsafe fn test_mm_cvtt_roundss_si64() {
12939 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12940 let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
12941 let e: i64 = -1;
12942 assert_eq!(r, e);
12943 }
12944
12945 #[simd_test(enable = "avx512f")]
12946 unsafe fn test_mm_cvtt_roundss_u64() {
12947 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12948 let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
12949 let e: u64 = u64::MAX;
12950 assert_eq!(r, e);
12951 }
12952
12953 #[simd_test(enable = "avx512f")]
12954 unsafe fn test_mm_cvttss_u64() {
12955 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12956 let r = _mm_cvttss_u64(a);
12957 let e: u64 = u64::MAX;
12958 assert_eq!(r, e);
12959 }
12960
12961 #[simd_test(enable = "avx512f")]
12962 unsafe fn test_mm_cvtu64_ss() {
12963 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12964 let b: u64 = 9;
12965 let r = _mm_cvtu64_ss(a, b);
12966 let e = _mm_set_ps(0., -0.5, 1., 9.);
12967 assert_eq_m128(r, e);
12968 }
12969
12970 #[simd_test(enable = "avx512f")]
12971 unsafe fn test_mm_cvtu64_sd() {
12972 let a = _mm_set_pd(1., -1.5);
12973 let b: u64 = 9;
12974 let r = _mm_cvtu64_sd(a, b);
12975 let e = _mm_set_pd(1., 9.);
12976 assert_eq_m128d(r, e);
12977 }
12978
12979 #[simd_test(enable = "avx512f")]
12980 unsafe fn test_mm_cvt_roundu64_ss() {
12981 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12982 let b: u64 = 9;
12983 let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12984 let e = _mm_set_ps(0., -0.5, 1., 9.);
12985 assert_eq_m128(r, e);
12986 }
12987
12988 #[simd_test(enable = "avx512f")]
12989 unsafe fn test_mm_cvt_roundu64_sd() {
12990 let a = _mm_set_pd(1., -1.5);
12991 let b: u64 = 9;
12992 let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12993 let e = _mm_set_pd(1., 9.);
12994 assert_eq_m128d(r, e);
12995 }
12996
12997 #[simd_test(enable = "avx512f")]
12998 unsafe fn test_mm_cvt_roundi64_sd() {
12999 let a = _mm_set_pd(1., -1.5);
13000 let b: i64 = 9;
13001 let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13002 let e = _mm_set_pd(1., 9.);
13003 assert_eq_m128d(r, e);
13004 }
13005
13006 #[simd_test(enable = "avx512f")]
13007 unsafe fn test_mm_cvt_roundsi64_sd() {
13008 let a = _mm_set_pd(1., -1.5);
13009 let b: i64 = 9;
13010 let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13011 let e = _mm_set_pd(1., 9.);
13012 assert_eq_m128d(r, e);
13013 }
13014}
13015