1use crate::{
2 core_arch::{simd::*, simd_llvm::*, x86::*, x86_64::*},
3 mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
10///
11/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
12#[inline]
13#[target_feature(enable = "avx512f")]
14#[cfg_attr(test, assert_instr(vcvtsd2si))]
15pub unsafe fn _mm_cvtsd_i64(a: __m128d) -> i64 {
16 _mm_cvtsd_si64(a)
17}
18
19/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
20///
21/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
22#[inline]
23#[target_feature(enable = "avx512f")]
24#[cfg_attr(test, assert_instr(vcvtss2si))]
25pub unsafe fn _mm_cvtss_i64(a: __m128) -> i64 {
26 _mm_cvtss_si64(a)
27}
28
29/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
30///
31/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
32#[inline]
33#[target_feature(enable = "avx512f")]
34#[cfg_attr(test, assert_instr(vcvtss2usi))]
35pub unsafe fn _mm_cvtss_u64(a: __m128) -> u64 {
36 vcvtss2usi64(a:a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
37}
38
39/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
40///
41/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
42#[inline]
43#[target_feature(enable = "avx512f")]
44#[cfg_attr(test, assert_instr(vcvtsd2usi))]
45pub unsafe fn _mm_cvtsd_u64(a: __m128d) -> u64 {
46 vcvtsd2usi64(a:a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
47}
48
49/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
50///
51/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti32_ss&expand=1643)
52#[inline]
53#[target_feature(enable = "avx512f")]
54#[cfg_attr(test, assert_instr(vcvtsi2ss))]
55pub unsafe fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
56 let b: f32 = b as f32;
57 simd_insert(x:a, idx:0, val:b)
58}
59
60/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
61///
62/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
63#[inline]
64#[target_feature(enable = "avx512f")]
65#[cfg_attr(test, assert_instr(vcvtsi2sd))]
66pub unsafe fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
67 let b: f64 = b as f64;
68 simd_insert(x:a, idx:0, val:b)
69}
70
71/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
72///
73/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
74#[inline]
75#[target_feature(enable = "avx512f")]
76#[cfg_attr(test, assert_instr(vcvtusi2ss))]
77pub unsafe fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
78 let b: f32 = b as f32;
79 simd_insert(x:a, idx:0, val:b)
80}
81
82/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
83///
84/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
85#[inline]
86#[target_feature(enable = "avx512f")]
87#[cfg_attr(test, assert_instr(vcvtusi2sd))]
88pub unsafe fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
89 let b: f64 = b as f64;
90 simd_insert(x:a, idx:0, val:b)
91}
92
93/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
94///
95/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
96#[inline]
97#[target_feature(enable = "avx512f")]
98#[cfg_attr(test, assert_instr(vcvtsd2si))]
99pub unsafe fn _mm_cvttsd_i64(a: __m128d) -> i64 {
100 vcvtsd2si64(a:a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
101}
102
103/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
104///
105/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
106#[inline]
107#[target_feature(enable = "avx512f")]
108#[cfg_attr(test, assert_instr(vcvtsd2usi))]
109pub unsafe fn _mm_cvttsd_u64(a: __m128d) -> u64 {
110 vcvtsd2usi64(a:a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
111}
112
113/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
114///
115/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
116#[inline]
117#[target_feature(enable = "avx512f")]
118#[cfg_attr(test, assert_instr(vcvtss2si))]
119pub unsafe fn _mm_cvttss_i64(a: __m128) -> i64 {
120 vcvtss2si64(a:a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
121}
122
123/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
124///
125/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
126#[inline]
127#[target_feature(enable = "avx512f")]
128#[cfg_attr(test, assert_instr(vcvtss2usi))]
129pub unsafe fn _mm_cvttss_u64(a: __m128) -> u64 {
130 vcvtss2usi64(a:a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
131}
132
133/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
134/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
135/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
136/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
137/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
138/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
139/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
140///
141/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
142#[inline]
143#[target_feature(enable = "avx512f")]
144#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
145#[rustc_legacy_const_generics(2)]
146pub unsafe fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
147 static_assert_rounding!(ROUNDING);
148 let a: f64x2 = a.as_f64x2();
149 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
150 transmute(src:r)
151}
152
153/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
154/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
155/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
156/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
157/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
158/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
159/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
160///
161/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
162#[inline]
163#[target_feature(enable = "avx512f")]
164#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
165#[rustc_legacy_const_generics(2)]
166pub unsafe fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
167 static_assert_rounding!(ROUNDING);
168 let a: f64x2 = a.as_f64x2();
169 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
170 transmute(src:r)
171}
172
173/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
174/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
175/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
176/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
177/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
178/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
179/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
180///
181/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
182#[inline]
183#[target_feature(enable = "avx512f")]
184#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
185#[rustc_legacy_const_generics(2)]
186pub unsafe fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
187 static_assert_rounding!(ROUNDING);
188 let a: f32x4 = a.as_f32x4();
189 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
190 transmute(src:r)
191}
192
193/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
194/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
195/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
196/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
197/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
198/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
199/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
200///
201/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
202#[inline]
203#[target_feature(enable = "avx512f")]
204#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
205#[rustc_legacy_const_generics(2)]
206pub unsafe fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
207 static_assert_rounding!(ROUNDING);
208 let a: f64x2 = a.as_f64x2();
209 let r: f64x2 = vcvtusi2sd64(a, b, ROUNDING);
210 transmute(src:r)
211}
212
213/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
214/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
215/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
216/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
217/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
218/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
219/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
220///
221/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
222#[inline]
223#[target_feature(enable = "avx512f")]
224#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
225#[rustc_legacy_const_generics(2)]
226pub unsafe fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
227 static_assert_rounding!(ROUNDING);
228 let a: f32x4 = a.as_f32x4();
229 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
230 transmute(src:r)
231}
232
233/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
234/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
235/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
236/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
237/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
238/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
239/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
240///
241/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
242#[inline]
243#[target_feature(enable = "avx512f")]
244#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
245#[rustc_legacy_const_generics(2)]
246pub unsafe fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
247 static_assert_rounding!(ROUNDING);
248 let a: f32x4 = a.as_f32x4();
249 let r: f32x4 = vcvtusi2ss64(a, b, ROUNDING);
250 transmute(src:r)
251}
252
253/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
254/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
255/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
256/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
257/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
258/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
259/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
260///
261/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
262#[inline]
263#[target_feature(enable = "avx512f")]
264#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
265#[rustc_legacy_const_generics(1)]
266pub unsafe fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
267 static_assert_rounding!(ROUNDING);
268 let a: f64x2 = a.as_f64x2();
269 vcvtsd2si64(a, ROUNDING)
270}
271
272/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
273/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
274/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
275/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
276/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
277/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
278/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
279///
280/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
281#[inline]
282#[target_feature(enable = "avx512f")]
283#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
284#[rustc_legacy_const_generics(1)]
285pub unsafe fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
286 static_assert_rounding!(ROUNDING);
287 let a: f64x2 = a.as_f64x2();
288 vcvtsd2si64(a, ROUNDING)
289}
290
291/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
292/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
293/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
294/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
295/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
296/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
297/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
298///
299/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
300#[inline]
301#[target_feature(enable = "avx512f")]
302#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
303#[rustc_legacy_const_generics(1)]
304pub unsafe fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
305 static_assert_rounding!(ROUNDING);
306 let a: f64x2 = a.as_f64x2();
307 vcvtsd2usi64(a, ROUNDING)
308}
309
310/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
311/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
312/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
313/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
314/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
315/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
316/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
317///
318/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
319#[inline]
320#[target_feature(enable = "avx512f")]
321#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
322#[rustc_legacy_const_generics(1)]
323pub unsafe fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
324 static_assert_rounding!(ROUNDING);
325 let a: f32x4 = a.as_f32x4();
326 vcvtss2si64(a, ROUNDING)
327}
328
329/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
330/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
331/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
332/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
333/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
334/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
335/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
336///
337/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
338#[inline]
339#[target_feature(enable = "avx512f")]
340#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
341#[rustc_legacy_const_generics(1)]
342pub unsafe fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
343 static_assert_rounding!(ROUNDING);
344 let a: f32x4 = a.as_f32x4();
345 vcvtss2si64(a, ROUNDING)
346}
347
348/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
349/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
350/// (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\
351/// (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\
352/// (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\
353/// (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\
354/// _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
355///
356/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
357#[inline]
358#[target_feature(enable = "avx512f")]
359#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
360#[rustc_legacy_const_generics(1)]
361pub unsafe fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
362 static_assert_rounding!(ROUNDING);
363 let a: f32x4 = a.as_f32x4();
364 vcvtss2usi64(a, ROUNDING)
365}
366
367/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
368/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
369///
370/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
371#[inline]
372#[target_feature(enable = "avx512f")]
373#[cfg_attr(test, assert_instr(vcvtsd2si, SAE = 8))]
374#[rustc_legacy_const_generics(1)]
375pub unsafe fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
376 static_assert_sae!(SAE);
377 let a: f64x2 = a.as_f64x2();
378 vcvtsd2si64(a, SAE)
379}
380
381/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
382/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
383///
384/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
385#[inline]
386#[target_feature(enable = "avx512f")]
387#[cfg_attr(test, assert_instr(vcvtsd2si, SAE = 8))]
388#[rustc_legacy_const_generics(1)]
389pub unsafe fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
390 static_assert_sae!(SAE);
391 let a: f64x2 = a.as_f64x2();
392 vcvtsd2si64(a, SAE)
393}
394
395/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
396/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
397///
398/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
399#[inline]
400#[target_feature(enable = "avx512f")]
401#[cfg_attr(test, assert_instr(vcvtsd2usi, SAE = 8))]
402#[rustc_legacy_const_generics(1)]
403pub unsafe fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
404 static_assert_sae!(SAE);
405 let a: f64x2 = a.as_f64x2();
406 vcvtsd2usi64(a, SAE)
407}
408
409/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
410/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
411///
412/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
413#[inline]
414#[target_feature(enable = "avx512f")]
415#[cfg_attr(test, assert_instr(vcvtss2si, SAE = 8))]
416#[rustc_legacy_const_generics(1)]
417pub unsafe fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
418 static_assert_sae!(SAE);
419 let a: f32x4 = a.as_f32x4();
420 vcvtss2si64(a, SAE)
421}
422
423/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
424/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
425///
426/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
427#[inline]
428#[target_feature(enable = "avx512f")]
429#[cfg_attr(test, assert_instr(vcvtss2si, SAE = 8))]
430#[rustc_legacy_const_generics(1)]
431pub unsafe fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
432 static_assert_sae!(SAE);
433 let a: f32x4 = a.as_f32x4();
434 vcvtss2si64(a, SAE)
435}
436
437/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
438/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
439///
440/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
441#[inline]
442#[target_feature(enable = "avx512f")]
443#[cfg_attr(test, assert_instr(vcvtss2usi, SAE = 8))]
444#[rustc_legacy_const_generics(1)]
445pub unsafe fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
446 static_assert_sae!(SAE);
447 let a: f32x4 = a.as_f32x4();
448 vcvtss2usi64(a, SAE)
449}
450
451#[allow(improper_ctypes)]
452extern "C" {
453 #[link_name = "llvm.x86.avx512.vcvtss2si64"]
454 fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
455 #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
456 fn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
457 #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
458 fn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
459 #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
460 fn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
461
462 #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
463 fn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
464 #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
465 fn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
466 #[link_name = "llvm.x86.avx512.cvtusi642ss"]
467 fn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
468 #[link_name = "llvm.x86.avx512.cvtusi642sd"]
469 fn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
470}
471
472#[cfg(test)]
473mod tests {
474
475 use stdarch_test::simd_test;
476
477 use crate::core_arch::x86::*;
478 use crate::core_arch::x86_64::*;
479 use crate::hint::black_box;
480
481 #[simd_test(enable = "avx512f")]
482 unsafe fn test_mm512_abs_epi64() {
483 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
484 let r = _mm512_abs_epi64(a);
485 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
486 assert_eq_m512i(r, e);
487 }
488
489 #[simd_test(enable = "avx512f")]
490 unsafe fn test_mm512_mask_abs_epi64() {
491 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
492 let r = _mm512_mask_abs_epi64(a, 0, a);
493 assert_eq_m512i(r, a);
494 let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
495 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
496 assert_eq_m512i(r, e);
497 }
498
499 #[simd_test(enable = "avx512f")]
500 unsafe fn test_mm512_maskz_abs_epi64() {
501 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
502 let r = _mm512_maskz_abs_epi64(0, a);
503 assert_eq_m512i(r, _mm512_setzero_si512());
504 let r = _mm512_maskz_abs_epi64(0b11111111, a);
505 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
506 assert_eq_m512i(r, e);
507 }
508
509 #[simd_test(enable = "avx512f,avx512vl")]
510 unsafe fn test_mm256_abs_epi64() {
511 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
512 let r = _mm256_abs_epi64(a);
513 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
514 assert_eq_m256i(r, e);
515 }
516
517 #[simd_test(enable = "avx512f,avx512vl")]
518 unsafe fn test_mm256_mask_abs_epi64() {
519 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
520 let r = _mm256_mask_abs_epi64(a, 0, a);
521 assert_eq_m256i(r, a);
522 let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
523 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
524 assert_eq_m256i(r, e);
525 }
526
527 #[simd_test(enable = "avx512f,avx512vl")]
528 unsafe fn test_mm256_maskz_abs_epi64() {
529 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
530 let r = _mm256_maskz_abs_epi64(0, a);
531 assert_eq_m256i(r, _mm256_setzero_si256());
532 let r = _mm256_maskz_abs_epi64(0b00001111, a);
533 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
534 assert_eq_m256i(r, e);
535 }
536
537 #[simd_test(enable = "avx512f")]
538 unsafe fn test_mm512_abs_pd() {
539 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
540 let r = _mm512_abs_pd(a);
541 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
542 assert_eq_m512d(r, e);
543 }
544
545 #[simd_test(enable = "avx512f")]
546 unsafe fn test_mm512_mask_abs_pd() {
547 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
548 let r = _mm512_mask_abs_pd(a, 0, a);
549 assert_eq_m512d(r, a);
550 let r = _mm512_mask_abs_pd(a, 0b00001111, a);
551 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
552 assert_eq_m512d(r, e);
553 }
554
555 #[simd_test(enable = "avx512f")]
556 unsafe fn test_mm512_mask_mov_epi64() {
557 let src = _mm512_set1_epi64(1);
558 let a = _mm512_set1_epi64(2);
559 let r = _mm512_mask_mov_epi64(src, 0, a);
560 assert_eq_m512i(r, src);
561 let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
562 assert_eq_m512i(r, a);
563 }
564
565 #[simd_test(enable = "avx512f")]
566 unsafe fn test_mm512_maskz_mov_epi64() {
567 let a = _mm512_set1_epi64(2);
568 let r = _mm512_maskz_mov_epi64(0, a);
569 assert_eq_m512i(r, _mm512_setzero_si512());
570 let r = _mm512_maskz_mov_epi64(0b11111111, a);
571 assert_eq_m512i(r, a);
572 }
573
574 #[simd_test(enable = "avx512f,avx512vl")]
575 unsafe fn test_mm256_mask_mov_epi64() {
576 let src = _mm256_set1_epi64x(1);
577 let a = _mm256_set1_epi64x(2);
578 let r = _mm256_mask_mov_epi64(src, 0, a);
579 assert_eq_m256i(r, src);
580 let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
581 assert_eq_m256i(r, a);
582 }
583
584 #[simd_test(enable = "avx512f,avx512vl")]
585 unsafe fn test_mm256_maskz_mov_epi64() {
586 let a = _mm256_set1_epi64x(2);
587 let r = _mm256_maskz_mov_epi64(0, a);
588 assert_eq_m256i(r, _mm256_setzero_si256());
589 let r = _mm256_maskz_mov_epi64(0b00001111, a);
590 assert_eq_m256i(r, a);
591 }
592
593 #[simd_test(enable = "avx512f,avx512vl")]
594 unsafe fn test_mm_mask_mov_epi64() {
595 let src = _mm_set1_epi64x(1);
596 let a = _mm_set1_epi64x(2);
597 let r = _mm_mask_mov_epi64(src, 0, a);
598 assert_eq_m128i(r, src);
599 let r = _mm_mask_mov_epi64(src, 0b00000011, a);
600 assert_eq_m128i(r, a);
601 }
602
603 #[simd_test(enable = "avx512f,avx512vl")]
604 unsafe fn test_mm_maskz_mov_epi64() {
605 let a = _mm_set1_epi64x(2);
606 let r = _mm_maskz_mov_epi64(0, a);
607 assert_eq_m128i(r, _mm_setzero_si128());
608 let r = _mm_maskz_mov_epi64(0b00000011, a);
609 assert_eq_m128i(r, a);
610 }
611
612 #[simd_test(enable = "avx512f")]
613 unsafe fn test_mm512_mask_mov_pd() {
614 let src = _mm512_set1_pd(1.);
615 let a = _mm512_set1_pd(2.);
616 let r = _mm512_mask_mov_pd(src, 0, a);
617 assert_eq_m512d(r, src);
618 let r = _mm512_mask_mov_pd(src, 0b11111111, a);
619 assert_eq_m512d(r, a);
620 }
621
622 #[simd_test(enable = "avx512f")]
623 unsafe fn test_mm512_maskz_mov_pd() {
624 let a = _mm512_set1_pd(2.);
625 let r = _mm512_maskz_mov_pd(0, a);
626 assert_eq_m512d(r, _mm512_setzero_pd());
627 let r = _mm512_maskz_mov_pd(0b11111111, a);
628 assert_eq_m512d(r, a);
629 }
630
631 #[simd_test(enable = "avx512f,avx512vl")]
632 unsafe fn test_mm256_mask_mov_pd() {
633 let src = _mm256_set1_pd(1.);
634 let a = _mm256_set1_pd(2.);
635 let r = _mm256_mask_mov_pd(src, 0, a);
636 assert_eq_m256d(r, src);
637 let r = _mm256_mask_mov_pd(src, 0b00001111, a);
638 assert_eq_m256d(r, a);
639 }
640
641 #[simd_test(enable = "avx512f,avx512vl")]
642 unsafe fn test_mm256_maskz_mov_pd() {
643 let a = _mm256_set1_pd(2.);
644 let r = _mm256_maskz_mov_pd(0, a);
645 assert_eq_m256d(r, _mm256_setzero_pd());
646 let r = _mm256_maskz_mov_pd(0b00001111, a);
647 assert_eq_m256d(r, a);
648 }
649
650 #[simd_test(enable = "avx512f,avx512vl")]
651 unsafe fn test_mm_mask_mov_pd() {
652 let src = _mm_set1_pd(1.);
653 let a = _mm_set1_pd(2.);
654 let r = _mm_mask_mov_pd(src, 0, a);
655 assert_eq_m128d(r, src);
656 let r = _mm_mask_mov_pd(src, 0b00000011, a);
657 assert_eq_m128d(r, a);
658 }
659
660 #[simd_test(enable = "avx512f,avx512vl")]
661 unsafe fn test_mm_maskz_mov_pd() {
662 let a = _mm_set1_pd(2.);
663 let r = _mm_maskz_mov_pd(0, a);
664 assert_eq_m128d(r, _mm_setzero_pd());
665 let r = _mm_maskz_mov_pd(0b00000011, a);
666 assert_eq_m128d(r, a);
667 }
668
669 #[simd_test(enable = "avx512f")]
670 unsafe fn test_mm512_add_epi64() {
671 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
672 let b = _mm512_set1_epi64(1);
673 let r = _mm512_add_epi64(a, b);
674 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
675 assert_eq_m512i(r, e);
676 }
677
678 #[simd_test(enable = "avx512f")]
679 unsafe fn test_mm512_mask_add_epi64() {
680 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
681 let b = _mm512_set1_epi64(1);
682 let r = _mm512_mask_add_epi64(a, 0, a, b);
683 assert_eq_m512i(r, a);
684 let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
685 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
686 assert_eq_m512i(r, e);
687 }
688
689 #[simd_test(enable = "avx512f")]
690 unsafe fn test_mm512_maskz_add_epi64() {
691 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
692 let b = _mm512_set1_epi64(1);
693 let r = _mm512_maskz_add_epi64(0, a, b);
694 assert_eq_m512i(r, _mm512_setzero_si512());
695 let r = _mm512_maskz_add_epi64(0b00001111, a, b);
696 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
697 assert_eq_m512i(r, e);
698 }
699
700 #[simd_test(enable = "avx512f,avx512vl")]
701 unsafe fn test_mm256_mask_add_epi64() {
702 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
703 let b = _mm256_set1_epi64x(1);
704 let r = _mm256_mask_add_epi64(a, 0, a, b);
705 assert_eq_m256i(r, a);
706 let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
707 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
708 assert_eq_m256i(r, e);
709 }
710
711 #[simd_test(enable = "avx512f,avx512vl")]
712 unsafe fn test_mm256_maskz_add_epi64() {
713 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
714 let b = _mm256_set1_epi64x(1);
715 let r = _mm256_maskz_add_epi64(0, a, b);
716 assert_eq_m256i(r, _mm256_setzero_si256());
717 let r = _mm256_maskz_add_epi64(0b00001111, a, b);
718 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
719 assert_eq_m256i(r, e);
720 }
721
722 #[simd_test(enable = "avx512f,avx512vl")]
723 unsafe fn test_mm_mask_add_epi64() {
724 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
725 let b = _mm_set1_epi64x(1);
726 let r = _mm_mask_add_epi64(a, 0, a, b);
727 assert_eq_m128i(r, a);
728 let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
729 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
730 assert_eq_m128i(r, e);
731 }
732
733 #[simd_test(enable = "avx512f,avx512vl")]
734 unsafe fn test_mm_maskz_add_epi64() {
735 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
736 let b = _mm_set1_epi64x(1);
737 let r = _mm_maskz_add_epi64(0, a, b);
738 assert_eq_m128i(r, _mm_setzero_si128());
739 let r = _mm_maskz_add_epi64(0b00000011, a, b);
740 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
741 assert_eq_m128i(r, e);
742 }
743
744 #[simd_test(enable = "avx512f")]
745 unsafe fn test_mm512_add_pd() {
746 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
747 let b = _mm512_set1_pd(1.);
748 let r = _mm512_add_pd(a, b);
749 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
750 assert_eq_m512d(r, e);
751 }
752
753 #[simd_test(enable = "avx512f")]
754 unsafe fn test_mm512_mask_add_pd() {
755 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
756 let b = _mm512_set1_pd(1.);
757 let r = _mm512_mask_add_pd(a, 0, a, b);
758 assert_eq_m512d(r, a);
759 let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
760 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
761 assert_eq_m512d(r, e);
762 }
763
764 #[simd_test(enable = "avx512f")]
765 unsafe fn test_mm512_maskz_add_pd() {
766 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
767 let b = _mm512_set1_pd(1.);
768 let r = _mm512_maskz_add_pd(0, a, b);
769 assert_eq_m512d(r, _mm512_setzero_pd());
770 let r = _mm512_maskz_add_pd(0b00001111, a, b);
771 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
772 assert_eq_m512d(r, e);
773 }
774
775 #[simd_test(enable = "avx512f,avx512vl")]
776 unsafe fn test_mm256_mask_add_pd() {
777 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
778 let b = _mm256_set1_pd(1.);
779 let r = _mm256_mask_add_pd(a, 0, a, b);
780 assert_eq_m256d(r, a);
781 let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
782 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
783 assert_eq_m256d(r, e);
784 }
785
786 #[simd_test(enable = "avx512f,avx512vl")]
787 unsafe fn test_mm256_maskz_add_pd() {
788 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
789 let b = _mm256_set1_pd(1.);
790 let r = _mm256_maskz_add_pd(0, a, b);
791 assert_eq_m256d(r, _mm256_setzero_pd());
792 let r = _mm256_maskz_add_pd(0b00001111, a, b);
793 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
794 assert_eq_m256d(r, e);
795 }
796
797 #[simd_test(enable = "avx512f,avx512vl")]
798 unsafe fn test_mm_mask_add_pd() {
799 let a = _mm_set_pd(f64::MAX, f64::MIN);
800 let b = _mm_set1_pd(1.);
801 let r = _mm_mask_add_pd(a, 0, a, b);
802 assert_eq_m128d(r, a);
803 let r = _mm_mask_add_pd(a, 0b00000011, a, b);
804 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
805 assert_eq_m128d(r, e);
806 }
807
808 #[simd_test(enable = "avx512f,avx512vl")]
809 unsafe fn test_mm_maskz_add_pd() {
810 let a = _mm_set_pd(f64::MAX, f64::MIN);
811 let b = _mm_set1_pd(1.);
812 let r = _mm_maskz_add_pd(0, a, b);
813 assert_eq_m128d(r, _mm_setzero_pd());
814 let r = _mm_maskz_add_pd(0b00000011, a, b);
815 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
816 assert_eq_m128d(r, e);
817 }
818
819 #[simd_test(enable = "avx512f")]
820 unsafe fn test_mm512_sub_epi64() {
821 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
822 let b = _mm512_set1_epi64(1);
823 let r = _mm512_sub_epi64(a, b);
824 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
825 assert_eq_m512i(r, e);
826 }
827
828 #[simd_test(enable = "avx512f")]
829 unsafe fn test_mm512_mask_sub_epi64() {
830 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
831 let b = _mm512_set1_epi64(1);
832 let r = _mm512_mask_sub_epi64(a, 0, a, b);
833 assert_eq_m512i(r, a);
834 let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
835 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
836 assert_eq_m512i(r, e);
837 }
838
839 #[simd_test(enable = "avx512f")]
840 unsafe fn test_mm512_maskz_sub_epi64() {
841 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
842 let b = _mm512_set1_epi64(1);
843 let r = _mm512_maskz_sub_epi64(0, a, b);
844 assert_eq_m512i(r, _mm512_setzero_si512());
845 let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
846 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
847 assert_eq_m512i(r, e);
848 }
849
850 #[simd_test(enable = "avx512f,avx512vl")]
851 unsafe fn test_mm256_mask_sub_epi64() {
852 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
853 let b = _mm256_set1_epi64x(1);
854 let r = _mm256_mask_sub_epi64(a, 0, a, b);
855 assert_eq_m256i(r, a);
856 let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
857 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
858 assert_eq_m256i(r, e);
859 }
860
861 #[simd_test(enable = "avx512f,avx512vl")]
862 unsafe fn test_mm256_maskz_sub_epi64() {
863 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
864 let b = _mm256_set1_epi64x(1);
865 let r = _mm256_maskz_sub_epi64(0, a, b);
866 assert_eq_m256i(r, _mm256_setzero_si256());
867 let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
868 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
869 assert_eq_m256i(r, e);
870 }
871
872 #[simd_test(enable = "avx512f,avx512vl")]
873 unsafe fn test_mm_mask_sub_epi64() {
874 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
875 let b = _mm_set1_epi64x(1);
876 let r = _mm_mask_sub_epi64(a, 0, a, b);
877 assert_eq_m128i(r, a);
878 let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
879 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
880 assert_eq_m128i(r, e);
881 }
882
883 #[simd_test(enable = "avx512f,avx512vl")]
884 unsafe fn test_mm_maskz_sub_epi64() {
885 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
886 let b = _mm_set1_epi64x(1);
887 let r = _mm_maskz_sub_epi64(0, a, b);
888 assert_eq_m128i(r, _mm_setzero_si128());
889 let r = _mm_maskz_sub_epi64(0b00000011, a, b);
890 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
891 assert_eq_m128i(r, e);
892 }
893
894 #[simd_test(enable = "avx512f")]
895 unsafe fn test_mm512_sub_pd() {
896 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
897 let b = _mm512_set1_pd(1.);
898 let r = _mm512_sub_pd(a, b);
899 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
900 assert_eq_m512d(r, e);
901 }
902
903 #[simd_test(enable = "avx512f")]
904 unsafe fn test_mm512_mask_sub_pd() {
905 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
906 let b = _mm512_set1_pd(1.);
907 let r = _mm512_mask_sub_pd(a, 0, a, b);
908 assert_eq_m512d(r, a);
909 let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
910 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
911 assert_eq_m512d(r, e);
912 }
913
914 #[simd_test(enable = "avx512f")]
915 unsafe fn test_mm512_maskz_sub_pd() {
916 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
917 let b = _mm512_set1_pd(1.);
918 let r = _mm512_maskz_sub_pd(0, a, b);
919 assert_eq_m512d(r, _mm512_setzero_pd());
920 let r = _mm512_maskz_sub_pd(0b00001111, a, b);
921 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
922 assert_eq_m512d(r, e);
923 }
924
925 #[simd_test(enable = "avx512f,avx512vl")]
926 unsafe fn test_mm256_mask_sub_pd() {
927 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
928 let b = _mm256_set1_pd(1.);
929 let r = _mm256_mask_sub_pd(a, 0, a, b);
930 assert_eq_m256d(r, a);
931 let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
932 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
933 assert_eq_m256d(r, e);
934 }
935
936 #[simd_test(enable = "avx512f,avx512vl")]
937 unsafe fn test_mm256_maskz_sub_pd() {
938 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
939 let b = _mm256_set1_pd(1.);
940 let r = _mm256_maskz_sub_pd(0, a, b);
941 assert_eq_m256d(r, _mm256_setzero_pd());
942 let r = _mm256_maskz_sub_pd(0b00001111, a, b);
943 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
944 assert_eq_m256d(r, e);
945 }
946
947 #[simd_test(enable = "avx512f,avx512vl")]
948 unsafe fn test_mm_mask_sub_pd() {
949 let a = _mm_set_pd(f64::MAX, f64::MIN);
950 let b = _mm_set1_pd(1.);
951 let r = _mm_mask_sub_pd(a, 0, a, b);
952 assert_eq_m128d(r, a);
953 let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
954 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
955 assert_eq_m128d(r, e);
956 }
957
958 #[simd_test(enable = "avx512f,avx512vl")]
959 unsafe fn test_mm_maskz_sub_pd() {
960 let a = _mm_set_pd(f64::MAX, f64::MIN);
961 let b = _mm_set1_pd(1.);
962 let r = _mm_maskz_sub_pd(0, a, b);
963 assert_eq_m128d(r, _mm_setzero_pd());
964 let r = _mm_maskz_sub_pd(0b00000011, a, b);
965 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
966 assert_eq_m128d(r, e);
967 }
968
969 #[simd_test(enable = "avx512f")]
970 unsafe fn test_mm512_mul_epi32() {
971 let a = _mm512_set1_epi32(1);
972 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
973 let r = _mm512_mul_epi32(a, b);
974 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
975 assert_eq_m512i(r, e);
976 }
977
978 #[simd_test(enable = "avx512f")]
979 unsafe fn test_mm512_mask_mul_epi32() {
980 let a = _mm512_set1_epi32(1);
981 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
982 let r = _mm512_mask_mul_epi32(a, 0, a, b);
983 assert_eq_m512i(r, a);
984 let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
985 #[rustfmt::skip]
986 let e = _mm512_set_epi64(
987 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
988 7, 5, 3, 1,
989 );
990 assert_eq_m512i(r, e);
991 }
992
993 #[simd_test(enable = "avx512f")]
994 unsafe fn test_mm512_maskz_mul_epi32() {
995 let a = _mm512_set1_epi32(1);
996 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
997 let r = _mm512_maskz_mul_epi32(0, a, b);
998 assert_eq_m512i(r, _mm512_setzero_si512());
999 let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1000 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1001 assert_eq_m512i(r, e);
1002 }
1003
1004 #[simd_test(enable = "avx512f,avx512vl")]
1005 unsafe fn test_mm256_mask_mul_epi32() {
1006 let a = _mm256_set1_epi32(1);
1007 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1008 let r = _mm256_mask_mul_epi32(a, 0, a, b);
1009 assert_eq_m256i(r, a);
1010 let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1011 let e = _mm256_set_epi64x(2, 4, 6, 8);
1012 assert_eq_m256i(r, e);
1013 }
1014
1015 #[simd_test(enable = "avx512f,avx512vl")]
1016 unsafe fn test_mm256_maskz_mul_epi32() {
1017 let a = _mm256_set1_epi32(1);
1018 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1019 let r = _mm256_maskz_mul_epi32(0, a, b);
1020 assert_eq_m256i(r, _mm256_setzero_si256());
1021 let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1022 let e = _mm256_set_epi64x(2, 4, 6, 8);
1023 assert_eq_m256i(r, e);
1024 }
1025
1026 #[simd_test(enable = "avx512f,avx512vl")]
1027 unsafe fn test_mm_mask_mul_epi32() {
1028 let a = _mm_set1_epi32(1);
1029 let b = _mm_set_epi32(1, 2, 3, 4);
1030 let r = _mm_mask_mul_epi32(a, 0, a, b);
1031 assert_eq_m128i(r, a);
1032 let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1033 let e = _mm_set_epi64x(2, 4);
1034 assert_eq_m128i(r, e);
1035 }
1036
1037 #[simd_test(enable = "avx512f,avx512vl")]
1038 unsafe fn test_mm_maskz_mul_epi32() {
1039 let a = _mm_set1_epi32(1);
1040 let b = _mm_set_epi32(1, 2, 3, 4);
1041 let r = _mm_maskz_mul_epi32(0, a, b);
1042 assert_eq_m128i(r, _mm_setzero_si128());
1043 let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1044 let e = _mm_set_epi64x(2, 4);
1045 assert_eq_m128i(r, e);
1046 }
1047
1048 #[simd_test(enable = "avx512f")]
1049 unsafe fn test_mm512_mul_epu32() {
1050 let a = _mm512_set1_epi32(1);
1051 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1052 let r = _mm512_mul_epu32(a, b);
1053 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1054 assert_eq_m512i(r, e);
1055 }
1056
1057 #[simd_test(enable = "avx512f")]
1058 unsafe fn test_mm512_mask_mul_epu32() {
1059 let a = _mm512_set1_epi32(1);
1060 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1061 let r = _mm512_mask_mul_epu32(a, 0, a, b);
1062 assert_eq_m512i(r, a);
1063 let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1064 #[rustfmt::skip]
1065 let e = _mm512_set_epi64(
1066 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1067 7, 5, 3, 1,
1068 );
1069 assert_eq_m512i(r, e);
1070 }
1071
1072 #[simd_test(enable = "avx512f")]
1073 unsafe fn test_mm512_maskz_mul_epu32() {
1074 let a = _mm512_set1_epi32(1);
1075 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1076 let r = _mm512_maskz_mul_epu32(0, a, b);
1077 assert_eq_m512i(r, _mm512_setzero_si512());
1078 let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1079 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1080 assert_eq_m512i(r, e);
1081 }
1082
1083 #[simd_test(enable = "avx512f,avx512vl")]
1084 unsafe fn test_mm256_mask_mul_epu32() {
1085 let a = _mm256_set1_epi32(1);
1086 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1087 let r = _mm256_mask_mul_epu32(a, 0, a, b);
1088 assert_eq_m256i(r, a);
1089 let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1090 let e = _mm256_set_epi64x(2, 4, 6, 8);
1091 assert_eq_m256i(r, e);
1092 }
1093
1094 #[simd_test(enable = "avx512f,avx512vl")]
1095 unsafe fn test_mm256_maskz_mul_epu32() {
1096 let a = _mm256_set1_epi32(1);
1097 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1098 let r = _mm256_maskz_mul_epu32(0, a, b);
1099 assert_eq_m256i(r, _mm256_setzero_si256());
1100 let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1101 let e = _mm256_set_epi64x(2, 4, 6, 8);
1102 assert_eq_m256i(r, e);
1103 }
1104
1105 #[simd_test(enable = "avx512f,avx512vl")]
1106 unsafe fn test_mm_mask_mul_epu32() {
1107 let a = _mm_set1_epi32(1);
1108 let b = _mm_set_epi32(1, 2, 3, 4);
1109 let r = _mm_mask_mul_epu32(a, 0, a, b);
1110 assert_eq_m128i(r, a);
1111 let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1112 let e = _mm_set_epi64x(2, 4);
1113 assert_eq_m128i(r, e);
1114 }
1115
1116 #[simd_test(enable = "avx512f,avx512vl")]
1117 unsafe fn test_mm_maskz_mul_epu32() {
1118 let a = _mm_set1_epi32(1);
1119 let b = _mm_set_epi32(1, 2, 3, 4);
1120 let r = _mm_maskz_mul_epu32(0, a, b);
1121 assert_eq_m128i(r, _mm_setzero_si128());
1122 let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1123 let e = _mm_set_epi64x(2, 4);
1124 assert_eq_m128i(r, e);
1125 }
1126
1127 #[simd_test(enable = "avx512f")]
1128 unsafe fn test_mm512_mullox_epi64() {
1129 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1130 let b = _mm512_set1_epi64(2);
1131 let r = _mm512_mullox_epi64(a, b);
1132 let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1133 assert_eq_m512i(r, e);
1134 }
1135
1136 #[simd_test(enable = "avx512f")]
1137 unsafe fn test_mm512_mask_mullox_epi64() {
1138 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1139 let b = _mm512_set1_epi64(2);
1140 let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1141 assert_eq_m512i(r, a);
1142 let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1143 let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1144 assert_eq_m512i(r, e);
1145 }
1146
1147 #[simd_test(enable = "avx512f")]
1148 unsafe fn test_mm512_mul_pd() {
1149 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1150 let b = _mm512_set1_pd(2.);
1151 let r = _mm512_mul_pd(a, b);
1152 #[rustfmt::skip]
1153 let e = _mm512_setr_pd(
1154 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1155 f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1156 );
1157 assert_eq_m512d(r, e);
1158 }
1159
1160 #[simd_test(enable = "avx512f")]
1161 unsafe fn test_mm512_mask_mul_pd() {
1162 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1163 let b = _mm512_set1_pd(2.);
1164 let r = _mm512_mask_mul_pd(a, 0, a, b);
1165 assert_eq_m512d(r, a);
1166 let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1167 #[rustfmt::skip]
1168 let e = _mm512_setr_pd(
1169 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1170 f64::MAX, f64::MIN, -100., -32.,
1171 );
1172 assert_eq_m512d(r, e);
1173 }
1174
1175 #[simd_test(enable = "avx512f")]
1176 unsafe fn test_mm512_maskz_mul_pd() {
1177 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1178 let b = _mm512_set1_pd(2.);
1179 let r = _mm512_maskz_mul_pd(0, a, b);
1180 assert_eq_m512d(r, _mm512_setzero_pd());
1181 let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1182 let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1183 assert_eq_m512d(r, e);
1184 }
1185
1186 #[simd_test(enable = "avx512f,avx512vl")]
1187 unsafe fn test_mm256_mask_mul_pd() {
1188 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1189 let b = _mm256_set1_pd(2.);
1190 let r = _mm256_mask_mul_pd(a, 0, a, b);
1191 assert_eq_m256d(r, a);
1192 let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1193 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1194 assert_eq_m256d(r, e);
1195 }
1196
1197 #[simd_test(enable = "avx512f,avx512vl")]
1198 unsafe fn test_mm256_maskz_mul_pd() {
1199 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1200 let b = _mm256_set1_pd(2.);
1201 let r = _mm256_maskz_mul_pd(0, a, b);
1202 assert_eq_m256d(r, _mm256_setzero_pd());
1203 let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1204 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1205 assert_eq_m256d(r, e);
1206 }
1207
1208 #[simd_test(enable = "avx512f,avx512vl")]
1209 unsafe fn test_mm_mask_mul_pd() {
1210 let a = _mm_set_pd(f64::MAX, f64::MIN);
1211 let b = _mm_set1_pd(2.);
1212 let r = _mm_mask_mul_pd(a, 0, a, b);
1213 assert_eq_m128d(r, a);
1214 let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1215 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1216 assert_eq_m128d(r, e);
1217 }
1218
1219 #[simd_test(enable = "avx512f,avx512vl")]
1220 unsafe fn test_mm_maskz_mul_pd() {
1221 let a = _mm_set_pd(f64::MAX, f64::MIN);
1222 let b = _mm_set1_pd(2.);
1223 let r = _mm_maskz_mul_pd(0, a, b);
1224 assert_eq_m128d(r, _mm_setzero_pd());
1225 let r = _mm_maskz_mul_pd(0b00000011, a, b);
1226 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1227 assert_eq_m128d(r, e);
1228 }
1229
1230 #[simd_test(enable = "avx512f")]
1231 unsafe fn test_mm512_div_pd() {
1232 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1233 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1234 let r = _mm512_div_pd(a, b);
1235 #[rustfmt::skip]
1236 let e = _mm512_setr_pd(
1237 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1238 f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1239 );
1240 assert_eq_m512d(r, e);
1241 }
1242
1243 #[simd_test(enable = "avx512f")]
1244 unsafe fn test_mm512_mask_div_pd() {
1245 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1246 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1247 let r = _mm512_mask_div_pd(a, 0, a, b);
1248 assert_eq_m512d(r, a);
1249 let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1250 #[rustfmt::skip]
1251 let e = _mm512_setr_pd(
1252 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1253 f64::MAX, f64::MIN, -100., -32.,
1254 );
1255 assert_eq_m512d(r, e);
1256 }
1257
1258 #[simd_test(enable = "avx512f")]
1259 unsafe fn test_mm512_maskz_div_pd() {
1260 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1261 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1262 let r = _mm512_maskz_div_pd(0, a, b);
1263 assert_eq_m512d(r, _mm512_setzero_pd());
1264 let r = _mm512_maskz_div_pd(0b00001111, a, b);
1265 let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1266 assert_eq_m512d(r, e);
1267 }
1268
1269 #[simd_test(enable = "avx512f,avx512vl")]
1270 unsafe fn test_mm256_mask_div_pd() {
1271 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1272 let b = _mm256_set_pd(2., 2., 0., 0.);
1273 let r = _mm256_mask_div_pd(a, 0, a, b);
1274 assert_eq_m256d(r, a);
1275 let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1276 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1277 assert_eq_m256d(r, e);
1278 }
1279
1280 #[simd_test(enable = "avx512f,avx512vl")]
1281 unsafe fn test_mm256_maskz_div_pd() {
1282 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1283 let b = _mm256_set_pd(2., 2., 0., 0.);
1284 let r = _mm256_maskz_div_pd(0, a, b);
1285 assert_eq_m256d(r, _mm256_setzero_pd());
1286 let r = _mm256_maskz_div_pd(0b00001111, a, b);
1287 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1288 assert_eq_m256d(r, e);
1289 }
1290
1291 #[simd_test(enable = "avx512f,avx512vl")]
1292 unsafe fn test_mm_mask_div_pd() {
1293 let a = _mm_set_pd(f64::MAX, f64::MIN);
1294 let b = _mm_set_pd(0., 0.);
1295 let r = _mm_mask_div_pd(a, 0, a, b);
1296 assert_eq_m128d(r, a);
1297 let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1298 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1299 assert_eq_m128d(r, e);
1300 }
1301
1302 #[simd_test(enable = "avx512f,avx512vl")]
1303 unsafe fn test_mm_maskz_div_pd() {
1304 let a = _mm_set_pd(f64::MAX, f64::MIN);
1305 let b = _mm_set_pd(0., 0.);
1306 let r = _mm_maskz_div_pd(0, a, b);
1307 assert_eq_m128d(r, _mm_setzero_pd());
1308 let r = _mm_maskz_div_pd(0b00000011, a, b);
1309 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1310 assert_eq_m128d(r, e);
1311 }
1312
1313 #[simd_test(enable = "avx512f")]
1314 unsafe fn test_mm512_max_epi64() {
1315 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1316 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1317 let r = _mm512_max_epi64(a, b);
1318 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1319 assert_eq_m512i(r, e);
1320 }
1321
1322 #[simd_test(enable = "avx512f")]
1323 unsafe fn test_mm512_mask_max_epi64() {
1324 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1325 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1326 let r = _mm512_mask_max_epi64(a, 0, a, b);
1327 assert_eq_m512i(r, a);
1328 let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1329 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1330 assert_eq_m512i(r, e);
1331 }
1332
1333 #[simd_test(enable = "avx512f")]
1334 unsafe fn test_mm512_maskz_max_epi64() {
1335 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1336 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1337 let r = _mm512_maskz_max_epi64(0, a, b);
1338 assert_eq_m512i(r, _mm512_setzero_si512());
1339 let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1340 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1341 assert_eq_m512i(r, e);
1342 }
1343
1344 #[simd_test(enable = "avx512f,avx512vl")]
1345 unsafe fn test_mm256_max_epi64() {
1346 let a = _mm256_set_epi64x(0, 1, 2, 3);
1347 let b = _mm256_set_epi64x(3, 2, 1, 0);
1348 let r = _mm256_max_epi64(a, b);
1349 let e = _mm256_set_epi64x(3, 2, 2, 3);
1350 assert_eq_m256i(r, e);
1351 }
1352
1353 #[simd_test(enable = "avx512f,avx512vl")]
1354 unsafe fn test_mm256_mask_max_epi64() {
1355 let a = _mm256_set_epi64x(0, 1, 2, 3);
1356 let b = _mm256_set_epi64x(3, 2, 1, 0);
1357 let r = _mm256_mask_max_epi64(a, 0, a, b);
1358 assert_eq_m256i(r, a);
1359 let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1360 let e = _mm256_set_epi64x(3, 2, 2, 3);
1361 assert_eq_m256i(r, e);
1362 }
1363
1364 #[simd_test(enable = "avx512f,avx512vl")]
1365 unsafe fn test_mm256_maskz_max_epi64() {
1366 let a = _mm256_set_epi64x(0, 1, 2, 3);
1367 let b = _mm256_set_epi64x(3, 2, 1, 0);
1368 let r = _mm256_maskz_max_epi64(0, a, b);
1369 assert_eq_m256i(r, _mm256_setzero_si256());
1370 let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1371 let e = _mm256_set_epi64x(3, 2, 2, 3);
1372 assert_eq_m256i(r, e);
1373 }
1374
1375 #[simd_test(enable = "avx512f,avx512vl")]
1376 unsafe fn test_mm_max_epi64() {
1377 let a = _mm_set_epi64x(2, 3);
1378 let b = _mm_set_epi64x(3, 2);
1379 let r = _mm_max_epi64(a, b);
1380 let e = _mm_set_epi64x(3, 3);
1381 assert_eq_m128i(r, e);
1382 }
1383
1384 #[simd_test(enable = "avx512f,avx512vl")]
1385 unsafe fn test_mm_mask_max_epi64() {
1386 let a = _mm_set_epi64x(2, 3);
1387 let b = _mm_set_epi64x(3, 2);
1388 let r = _mm_mask_max_epi64(a, 0, a, b);
1389 assert_eq_m128i(r, a);
1390 let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1391 let e = _mm_set_epi64x(3, 3);
1392 assert_eq_m128i(r, e);
1393 }
1394
1395 #[simd_test(enable = "avx512f,avx512vl")]
1396 unsafe fn test_mm_maskz_max_epi64() {
1397 let a = _mm_set_epi64x(2, 3);
1398 let b = _mm_set_epi64x(3, 2);
1399 let r = _mm_maskz_max_epi64(0, a, b);
1400 assert_eq_m128i(r, _mm_setzero_si128());
1401 let r = _mm_maskz_max_epi64(0b00000011, a, b);
1402 let e = _mm_set_epi64x(3, 3);
1403 assert_eq_m128i(r, e);
1404 }
1405
1406 #[simd_test(enable = "avx512f")]
1407 unsafe fn test_mm512_max_pd() {
1408 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1409 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1410 let r = _mm512_max_pd(a, b);
1411 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1412 assert_eq_m512d(r, e);
1413 }
1414
1415 #[simd_test(enable = "avx512f")]
1416 unsafe fn test_mm512_mask_max_pd() {
1417 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1418 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1419 let r = _mm512_mask_max_pd(a, 0, a, b);
1420 assert_eq_m512d(r, a);
1421 let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1422 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1423 assert_eq_m512d(r, e);
1424 }
1425
1426 #[simd_test(enable = "avx512f")]
1427 unsafe fn test_mm512_maskz_max_pd() {
1428 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1429 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1430 let r = _mm512_maskz_max_pd(0, a, b);
1431 assert_eq_m512d(r, _mm512_setzero_pd());
1432 let r = _mm512_maskz_max_pd(0b00001111, a, b);
1433 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1434 assert_eq_m512d(r, e);
1435 }
1436
1437 #[simd_test(enable = "avx512f,avx512vl")]
1438 unsafe fn test_mm256_mask_max_pd() {
1439 let a = _mm256_set_pd(0., 1., 2., 3.);
1440 let b = _mm256_set_pd(3., 2., 1., 0.);
1441 let r = _mm256_mask_max_pd(a, 0, a, b);
1442 assert_eq_m256d(r, a);
1443 let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1444 let e = _mm256_set_pd(3., 2., 2., 3.);
1445 assert_eq_m256d(r, e);
1446 }
1447
1448 #[simd_test(enable = "avx512f,avx512vl")]
1449 unsafe fn test_mm256_maskz_max_pd() {
1450 let a = _mm256_set_pd(0., 1., 2., 3.);
1451 let b = _mm256_set_pd(3., 2., 1., 0.);
1452 let r = _mm256_maskz_max_pd(0, a, b);
1453 assert_eq_m256d(r, _mm256_setzero_pd());
1454 let r = _mm256_maskz_max_pd(0b00001111, a, b);
1455 let e = _mm256_set_pd(3., 2., 2., 3.);
1456 assert_eq_m256d(r, e);
1457 }
1458
1459 #[simd_test(enable = "avx512f,avx512vl")]
1460 unsafe fn test_mm_mask_max_pd() {
1461 let a = _mm_set_pd(2., 3.);
1462 let b = _mm_set_pd(3., 2.);
1463 let r = _mm_mask_max_pd(a, 0, a, b);
1464 assert_eq_m128d(r, a);
1465 let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1466 let e = _mm_set_pd(3., 3.);
1467 assert_eq_m128d(r, e);
1468 }
1469
1470 #[simd_test(enable = "avx512f,avx512vl")]
1471 unsafe fn test_mm_maskz_max_pd() {
1472 let a = _mm_set_pd(2., 3.);
1473 let b = _mm_set_pd(3., 2.);
1474 let r = _mm_maskz_max_pd(0, a, b);
1475 assert_eq_m128d(r, _mm_setzero_pd());
1476 let r = _mm_maskz_max_pd(0b00000011, a, b);
1477 let e = _mm_set_pd(3., 3.);
1478 assert_eq_m128d(r, e);
1479 }
1480
1481 #[simd_test(enable = "avx512f")]
1482 unsafe fn test_mm512_max_epu64() {
1483 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1484 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1485 let r = _mm512_max_epu64(a, b);
1486 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1487 assert_eq_m512i(r, e);
1488 }
1489
1490 #[simd_test(enable = "avx512f")]
1491 unsafe fn test_mm512_mask_max_epu64() {
1492 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1493 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1494 let r = _mm512_mask_max_epu64(a, 0, a, b);
1495 assert_eq_m512i(r, a);
1496 let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1497 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1498 assert_eq_m512i(r, e);
1499 }
1500
1501 #[simd_test(enable = "avx512f")]
1502 unsafe fn test_mm512_maskz_max_epu64() {
1503 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1504 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1505 let r = _mm512_maskz_max_epu64(0, a, b);
1506 assert_eq_m512i(r, _mm512_setzero_si512());
1507 let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1508 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1509 assert_eq_m512i(r, e);
1510 }
1511
1512 #[simd_test(enable = "avx512f,avx512vl")]
1513 unsafe fn test_mm256_max_epu64() {
1514 let a = _mm256_set_epi64x(0, 1, 2, 3);
1515 let b = _mm256_set_epi64x(3, 2, 1, 0);
1516 let r = _mm256_max_epu64(a, b);
1517 let e = _mm256_set_epi64x(3, 2, 2, 3);
1518 assert_eq_m256i(r, e);
1519 }
1520
1521 #[simd_test(enable = "avx512f,avx512vl")]
1522 unsafe fn test_mm256_mask_max_epu64() {
1523 let a = _mm256_set_epi64x(0, 1, 2, 3);
1524 let b = _mm256_set_epi64x(3, 2, 1, 0);
1525 let r = _mm256_mask_max_epu64(a, 0, a, b);
1526 assert_eq_m256i(r, a);
1527 let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1528 let e = _mm256_set_epi64x(3, 2, 2, 3);
1529 assert_eq_m256i(r, e);
1530 }
1531
1532 #[simd_test(enable = "avx512f,avx512vl")]
1533 unsafe fn test_mm256_maskz_max_epu64() {
1534 let a = _mm256_set_epi64x(0, 1, 2, 3);
1535 let b = _mm256_set_epi64x(3, 2, 1, 0);
1536 let r = _mm256_maskz_max_epu64(0, a, b);
1537 assert_eq_m256i(r, _mm256_setzero_si256());
1538 let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1539 let e = _mm256_set_epi64x(3, 2, 2, 3);
1540 assert_eq_m256i(r, e);
1541 }
1542
1543 #[simd_test(enable = "avx512f,avx512vl")]
1544 unsafe fn test_mm_max_epu64() {
1545 let a = _mm_set_epi64x(2, 3);
1546 let b = _mm_set_epi64x(3, 2);
1547 let r = _mm_max_epu64(a, b);
1548 let e = _mm_set_epi64x(3, 3);
1549 assert_eq_m128i(r, e);
1550 }
1551
1552 #[simd_test(enable = "avx512f,avx512vl")]
1553 unsafe fn test_mm_mask_max_epu64() {
1554 let a = _mm_set_epi64x(2, 3);
1555 let b = _mm_set_epi64x(3, 2);
1556 let r = _mm_mask_max_epu64(a, 0, a, b);
1557 assert_eq_m128i(r, a);
1558 let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1559 let e = _mm_set_epi64x(3, 3);
1560 assert_eq_m128i(r, e);
1561 }
1562
1563 #[simd_test(enable = "avx512f,avx512vl")]
1564 unsafe fn test_mm_maskz_max_epu64() {
1565 let a = _mm_set_epi64x(2, 3);
1566 let b = _mm_set_epi64x(3, 2);
1567 let r = _mm_maskz_max_epu64(0, a, b);
1568 assert_eq_m128i(r, _mm_setzero_si128());
1569 let r = _mm_maskz_max_epu64(0b00000011, a, b);
1570 let e = _mm_set_epi64x(3, 3);
1571 assert_eq_m128i(r, e);
1572 }
1573
1574 #[simd_test(enable = "avx512f")]
1575 unsafe fn test_mm512_min_epi64() {
1576 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1577 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1578 let r = _mm512_min_epi64(a, b);
1579 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1580 assert_eq_m512i(r, e);
1581 }
1582
1583 #[simd_test(enable = "avx512f")]
1584 unsafe fn test_mm512_mask_min_epi64() {
1585 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1586 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1587 let r = _mm512_mask_min_epi64(a, 0, a, b);
1588 assert_eq_m512i(r, a);
1589 let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1590 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1591 assert_eq_m512i(r, e);
1592 }
1593
1594 #[simd_test(enable = "avx512f")]
1595 unsafe fn test_mm512_maskz_min_epi64() {
1596 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1597 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1598 let r = _mm512_maskz_min_epi64(0, a, b);
1599 assert_eq_m512i(r, _mm512_setzero_si512());
1600 let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1601 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1602 assert_eq_m512i(r, e);
1603 }
1604
1605 #[simd_test(enable = "avx512f,avx512vl")]
1606 unsafe fn test_mm256_min_epi64() {
1607 let a = _mm256_set_epi64x(0, 1, 2, 3);
1608 let b = _mm256_set_epi64x(3, 2, 1, 0);
1609 let r = _mm256_min_epi64(a, b);
1610 let e = _mm256_set_epi64x(0, 1, 1, 0);
1611 assert_eq_m256i(r, e);
1612 }
1613
1614 #[simd_test(enable = "avx512f,avx512vl")]
1615 unsafe fn test_mm256_mask_min_epi64() {
1616 let a = _mm256_set_epi64x(0, 1, 2, 3);
1617 let b = _mm256_set_epi64x(3, 2, 1, 0);
1618 let r = _mm256_mask_min_epi64(a, 0, a, b);
1619 assert_eq_m256i(r, a);
1620 let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1621 let e = _mm256_set_epi64x(0, 1, 1, 0);
1622 assert_eq_m256i(r, e);
1623 }
1624
1625 #[simd_test(enable = "avx512f,avx512vl")]
1626 unsafe fn test_mm256_maskz_min_epi64() {
1627 let a = _mm256_set_epi64x(0, 1, 2, 3);
1628 let b = _mm256_set_epi64x(3, 2, 1, 0);
1629 let r = _mm256_maskz_min_epi64(0, a, b);
1630 assert_eq_m256i(r, _mm256_setzero_si256());
1631 let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1632 let e = _mm256_set_epi64x(0, 1, 1, 0);
1633 assert_eq_m256i(r, e);
1634 }
1635
1636 #[simd_test(enable = "avx512f")]
1637 unsafe fn test_mm512_min_pd() {
1638 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1639 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1640 let r = _mm512_min_pd(a, b);
1641 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1642 assert_eq_m512d(r, e);
1643 }
1644
1645 #[simd_test(enable = "avx512f")]
1646 unsafe fn test_mm512_mask_min_pd() {
1647 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1648 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1649 let r = _mm512_mask_min_pd(a, 0, a, b);
1650 assert_eq_m512d(r, a);
1651 let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1652 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1653 assert_eq_m512d(r, e);
1654 }
1655
1656 #[simd_test(enable = "avx512f")]
1657 unsafe fn test_mm512_maskz_min_pd() {
1658 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1659 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1660 let r = _mm512_maskz_min_pd(0, a, b);
1661 assert_eq_m512d(r, _mm512_setzero_pd());
1662 let r = _mm512_maskz_min_pd(0b00001111, a, b);
1663 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1664 assert_eq_m512d(r, e);
1665 }
1666
1667 #[simd_test(enable = "avx512f,avx512vl")]
1668 unsafe fn test_mm256_mask_min_pd() {
1669 let a = _mm256_set_pd(0., 1., 2., 3.);
1670 let b = _mm256_set_pd(3., 2., 1., 0.);
1671 let r = _mm256_mask_min_pd(a, 0, a, b);
1672 assert_eq_m256d(r, a);
1673 let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1674 let e = _mm256_set_pd(0., 1., 1., 0.);
1675 assert_eq_m256d(r, e);
1676 }
1677
1678 #[simd_test(enable = "avx512f,avx512vl")]
1679 unsafe fn test_mm256_maskz_min_pd() {
1680 let a = _mm256_set_pd(0., 1., 2., 3.);
1681 let b = _mm256_set_pd(3., 2., 1., 0.);
1682 let r = _mm256_maskz_min_pd(0, a, b);
1683 assert_eq_m256d(r, _mm256_setzero_pd());
1684 let r = _mm256_maskz_min_pd(0b00001111, a, b);
1685 let e = _mm256_set_pd(0., 1., 1., 0.);
1686 assert_eq_m256d(r, e);
1687 }
1688
1689 #[simd_test(enable = "avx512f,avx512vl")]
1690 unsafe fn test_mm_mask_min_pd() {
1691 let a = _mm_set_pd(0., 1.);
1692 let b = _mm_set_pd(1., 0.);
1693 let r = _mm_mask_min_pd(a, 0, a, b);
1694 assert_eq_m128d(r, a);
1695 let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1696 let e = _mm_set_pd(0., 0.);
1697 assert_eq_m128d(r, e);
1698 }
1699
1700 #[simd_test(enable = "avx512f,avx512vl")]
1701 unsafe fn test_mm_maskz_min_pd() {
1702 let a = _mm_set_pd(0., 1.);
1703 let b = _mm_set_pd(1., 0.);
1704 let r = _mm_maskz_min_pd(0, a, b);
1705 assert_eq_m128d(r, _mm_setzero_pd());
1706 let r = _mm_maskz_min_pd(0b00000011, a, b);
1707 let e = _mm_set_pd(0., 0.);
1708 assert_eq_m128d(r, e);
1709 }
1710
1711 #[simd_test(enable = "avx512f")]
1712 unsafe fn test_mm512_min_epu64() {
1713 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1714 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1715 let r = _mm512_min_epu64(a, b);
1716 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1717 assert_eq_m512i(r, e);
1718 }
1719
1720 #[simd_test(enable = "avx512f")]
1721 unsafe fn test_mm512_mask_min_epu64() {
1722 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1723 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1724 let r = _mm512_mask_min_epu64(a, 0, a, b);
1725 assert_eq_m512i(r, a);
1726 let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1727 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1728 assert_eq_m512i(r, e);
1729 }
1730
1731 #[simd_test(enable = "avx512f")]
1732 unsafe fn test_mm512_maskz_min_epu64() {
1733 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1734 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1735 let r = _mm512_maskz_min_epu64(0, a, b);
1736 assert_eq_m512i(r, _mm512_setzero_si512());
1737 let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1738 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1739 assert_eq_m512i(r, e);
1740 }
1741
1742 #[simd_test(enable = "avx512f,avx512vl")]
1743 unsafe fn test_mm256_min_epu64() {
1744 let a = _mm256_set_epi64x(0, 1, 2, 3);
1745 let b = _mm256_set_epi64x(3, 2, 1, 0);
1746 let r = _mm256_min_epu64(a, b);
1747 let e = _mm256_set_epi64x(0, 1, 1, 0);
1748 assert_eq_m256i(r, e);
1749 }
1750
1751 #[simd_test(enable = "avx512f,avx512vl")]
1752 unsafe fn test_mm256_mask_min_epu64() {
1753 let a = _mm256_set_epi64x(0, 1, 2, 3);
1754 let b = _mm256_set_epi64x(3, 2, 1, 0);
1755 let r = _mm256_mask_min_epu64(a, 0, a, b);
1756 assert_eq_m256i(r, a);
1757 let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1758 let e = _mm256_set_epi64x(0, 1, 1, 0);
1759 assert_eq_m256i(r, e);
1760 }
1761
1762 #[simd_test(enable = "avx512f,avx512vl")]
1763 unsafe fn test_mm256_maskz_min_epu64() {
1764 let a = _mm256_set_epi64x(0, 1, 2, 3);
1765 let b = _mm256_set_epi64x(3, 2, 1, 0);
1766 let r = _mm256_maskz_min_epu64(0, a, b);
1767 assert_eq_m256i(r, _mm256_setzero_si256());
1768 let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1769 let e = _mm256_set_epi64x(0, 1, 1, 0);
1770 assert_eq_m256i(r, e);
1771 }
1772
1773 #[simd_test(enable = "avx512f,avx512vl")]
1774 unsafe fn test_mm_min_epu64() {
1775 let a = _mm_set_epi64x(0, 1);
1776 let b = _mm_set_epi64x(1, 0);
1777 let r = _mm_min_epu64(a, b);
1778 let e = _mm_set_epi64x(0, 0);
1779 assert_eq_m128i(r, e);
1780 }
1781
1782 #[simd_test(enable = "avx512f,avx512vl")]
1783 unsafe fn test_mm_mask_min_epu64() {
1784 let a = _mm_set_epi64x(0, 1);
1785 let b = _mm_set_epi64x(1, 0);
1786 let r = _mm_mask_min_epu64(a, 0, a, b);
1787 assert_eq_m128i(r, a);
1788 let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1789 let e = _mm_set_epi64x(0, 0);
1790 assert_eq_m128i(r, e);
1791 }
1792
1793 #[simd_test(enable = "avx512f,avx512vl")]
1794 unsafe fn test_mm_maskz_min_epu64() {
1795 let a = _mm_set_epi64x(0, 1);
1796 let b = _mm_set_epi64x(1, 0);
1797 let r = _mm_maskz_min_epu64(0, a, b);
1798 assert_eq_m128i(r, _mm_setzero_si128());
1799 let r = _mm_maskz_min_epu64(0b00000011, a, b);
1800 let e = _mm_set_epi64x(0, 0);
1801 assert_eq_m128i(r, e);
1802 }
1803
1804 #[simd_test(enable = "avx512f")]
1805 unsafe fn test_mm512_sqrt_pd() {
1806 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1807 let r = _mm512_sqrt_pd(a);
1808 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1809 assert_eq_m512d(r, e);
1810 }
1811
1812 #[simd_test(enable = "avx512f")]
1813 unsafe fn test_mm512_mask_sqrt_pd() {
1814 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1815 let r = _mm512_mask_sqrt_pd(a, 0, a);
1816 assert_eq_m512d(r, a);
1817 let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1818 let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1819 assert_eq_m512d(r, e);
1820 }
1821
1822 #[simd_test(enable = "avx512f")]
1823 unsafe fn test_mm512_maskz_sqrt_pd() {
1824 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1825 let r = _mm512_maskz_sqrt_pd(0, a);
1826 assert_eq_m512d(r, _mm512_setzero_pd());
1827 let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1828 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1829 assert_eq_m512d(r, e);
1830 }
1831
1832 #[simd_test(enable = "avx512f,avx512vl")]
1833 unsafe fn test_mm256_mask_sqrt_pd() {
1834 let a = _mm256_set_pd(0., 1., 4., 9.);
1835 let r = _mm256_mask_sqrt_pd(a, 0, a);
1836 assert_eq_m256d(r, a);
1837 let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
1838 let e = _mm256_set_pd(0., 1., 2., 3.);
1839 assert_eq_m256d(r, e);
1840 }
1841
1842 #[simd_test(enable = "avx512f,avx512vl")]
1843 unsafe fn test_mm256_maskz_sqrt_pd() {
1844 let a = _mm256_set_pd(0., 1., 4., 9.);
1845 let r = _mm256_maskz_sqrt_pd(0, a);
1846 assert_eq_m256d(r, _mm256_setzero_pd());
1847 let r = _mm256_maskz_sqrt_pd(0b00001111, a);
1848 let e = _mm256_set_pd(0., 1., 2., 3.);
1849 assert_eq_m256d(r, e);
1850 }
1851
1852 #[simd_test(enable = "avx512f,avx512vl")]
1853 unsafe fn test_mm_mask_sqrt_pd() {
1854 let a = _mm_set_pd(0., 1.);
1855 let r = _mm_mask_sqrt_pd(a, 0, a);
1856 assert_eq_m128d(r, a);
1857 let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
1858 let e = _mm_set_pd(0., 1.);
1859 assert_eq_m128d(r, e);
1860 }
1861
1862 #[simd_test(enable = "avx512f,avx512vl")]
1863 unsafe fn test_mm_maskz_sqrt_pd() {
1864 let a = _mm_set_pd(0., 1.);
1865 let r = _mm_maskz_sqrt_pd(0, a);
1866 assert_eq_m128d(r, _mm_setzero_pd());
1867 let r = _mm_maskz_sqrt_pd(0b00000011, a);
1868 let e = _mm_set_pd(0., 1.);
1869 assert_eq_m128d(r, e);
1870 }
1871
1872 #[simd_test(enable = "avx512f")]
1873 unsafe fn test_mm512_fmadd_pd() {
1874 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1875 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1876 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1877 let r = _mm512_fmadd_pd(a, b, c);
1878 let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
1879 assert_eq_m512d(r, e);
1880 }
1881
1882 #[simd_test(enable = "avx512f")]
1883 unsafe fn test_mm512_mask_fmadd_pd() {
1884 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1885 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1886 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1887 let r = _mm512_mask_fmadd_pd(a, 0, b, c);
1888 assert_eq_m512d(r, a);
1889 let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
1890 let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
1891 assert_eq_m512d(r, e);
1892 }
1893
1894 #[simd_test(enable = "avx512f")]
1895 unsafe fn test_mm512_maskz_fmadd_pd() {
1896 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1897 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1898 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1899 let r = _mm512_maskz_fmadd_pd(0, a, b, c);
1900 assert_eq_m512d(r, _mm512_setzero_pd());
1901 let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
1902 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
1903 assert_eq_m512d(r, e);
1904 }
1905
1906 #[simd_test(enable = "avx512f")]
1907 unsafe fn test_mm512_mask3_fmadd_pd() {
1908 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1909 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1910 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
1911 let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
1912 assert_eq_m512d(r, c);
1913 let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
1914 let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
1915 assert_eq_m512d(r, e);
1916 }
1917
1918 #[simd_test(enable = "avx512f,avx512vl")]
1919 unsafe fn test_mm256_mask_fmadd_pd() {
1920 let a = _mm256_set1_pd(1.);
1921 let b = _mm256_set_pd(0., 1., 2., 3.);
1922 let c = _mm256_set1_pd(1.);
1923 let r = _mm256_mask_fmadd_pd(a, 0, b, c);
1924 assert_eq_m256d(r, a);
1925 let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
1926 let e = _mm256_set_pd(1., 2., 3., 4.);
1927 assert_eq_m256d(r, e);
1928 }
1929
1930 #[simd_test(enable = "avx512f,avx512vl")]
1931 unsafe fn test_mm256_maskz_fmadd_pd() {
1932 let a = _mm256_set1_pd(1.);
1933 let b = _mm256_set_pd(0., 1., 2., 3.);
1934 let c = _mm256_set1_pd(1.);
1935 let r = _mm256_maskz_fmadd_pd(0, a, b, c);
1936 assert_eq_m256d(r, _mm256_setzero_pd());
1937 let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
1938 let e = _mm256_set_pd(1., 2., 3., 4.);
1939 assert_eq_m256d(r, e);
1940 }
1941
1942 #[simd_test(enable = "avx512f,avx512vl")]
1943 unsafe fn test_mm256_mask3_fmadd_pd() {
1944 let a = _mm256_set1_pd(1.);
1945 let b = _mm256_set_pd(0., 1., 2., 3.);
1946 let c = _mm256_set1_pd(1.);
1947 let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
1948 assert_eq_m256d(r, c);
1949 let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
1950 let e = _mm256_set_pd(1., 2., 3., 4.);
1951 assert_eq_m256d(r, e);
1952 }
1953
1954 #[simd_test(enable = "avx512f,avx512vl")]
1955 unsafe fn test_mm_mask_fmadd_pd() {
1956 let a = _mm_set1_pd(1.);
1957 let b = _mm_set_pd(0., 1.);
1958 let c = _mm_set1_pd(1.);
1959 let r = _mm_mask_fmadd_pd(a, 0, b, c);
1960 assert_eq_m128d(r, a);
1961 let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
1962 let e = _mm_set_pd(1., 2.);
1963 assert_eq_m128d(r, e);
1964 }
1965
1966 #[simd_test(enable = "avx512f,avx512vl")]
1967 unsafe fn test_mm_maskz_fmadd_pd() {
1968 let a = _mm_set1_pd(1.);
1969 let b = _mm_set_pd(0., 1.);
1970 let c = _mm_set1_pd(1.);
1971 let r = _mm_maskz_fmadd_pd(0, a, b, c);
1972 assert_eq_m128d(r, _mm_setzero_pd());
1973 let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
1974 let e = _mm_set_pd(1., 2.);
1975 assert_eq_m128d(r, e);
1976 }
1977
1978 #[simd_test(enable = "avx512f,avx512vl")]
1979 unsafe fn test_mm_mask3_fmadd_pd() {
1980 let a = _mm_set1_pd(1.);
1981 let b = _mm_set_pd(0., 1.);
1982 let c = _mm_set1_pd(1.);
1983 let r = _mm_mask3_fmadd_pd(a, b, c, 0);
1984 assert_eq_m128d(r, c);
1985 let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
1986 let e = _mm_set_pd(1., 2.);
1987 assert_eq_m128d(r, e);
1988 }
1989
1990 #[simd_test(enable = "avx512f")]
1991 unsafe fn test_mm512_fmsub_pd() {
1992 let a = _mm512_set1_pd(1.);
1993 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1994 let c = _mm512_set1_pd(1.);
1995 let r = _mm512_fmsub_pd(a, b, c);
1996 let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
1997 assert_eq_m512d(r, e);
1998 }
1999
2000 #[simd_test(enable = "avx512f")]
2001 unsafe fn test_mm512_mask_fmsub_pd() {
2002 let a = _mm512_set1_pd(1.);
2003 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2004 let c = _mm512_set1_pd(1.);
2005 let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2006 assert_eq_m512d(r, a);
2007 let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2008 let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2009 assert_eq_m512d(r, e);
2010 }
2011
2012 #[simd_test(enable = "avx512f")]
2013 unsafe fn test_mm512_maskz_fmsub_pd() {
2014 let a = _mm512_set1_pd(1.);
2015 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2016 let c = _mm512_set1_pd(1.);
2017 let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2018 assert_eq_m512d(r, _mm512_setzero_pd());
2019 let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2020 let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2021 assert_eq_m512d(r, e);
2022 }
2023
2024 #[simd_test(enable = "avx512f")]
2025 unsafe fn test_mm512_mask3_fmsub_pd() {
2026 let a = _mm512_set1_pd(1.);
2027 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2028 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2029 let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2030 assert_eq_m512d(r, c);
2031 let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2032 let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2033 assert_eq_m512d(r, e);
2034 }
2035
2036 #[simd_test(enable = "avx512f,avx512vl")]
2037 unsafe fn test_mm256_mask_fmsub_pd() {
2038 let a = _mm256_set1_pd(1.);
2039 let b = _mm256_set_pd(0., 1., 2., 3.);
2040 let c = _mm256_set1_pd(1.);
2041 let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2042 assert_eq_m256d(r, a);
2043 let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2044 let e = _mm256_set_pd(-1., 0., 1., 2.);
2045 assert_eq_m256d(r, e);
2046 }
2047
2048 #[simd_test(enable = "avx512f,avx512vl")]
2049 unsafe fn test_mm256_maskz_fmsub_pd() {
2050 let a = _mm256_set1_pd(1.);
2051 let b = _mm256_set_pd(0., 1., 2., 3.);
2052 let c = _mm256_set1_pd(1.);
2053 let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2054 assert_eq_m256d(r, _mm256_setzero_pd());
2055 let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2056 let e = _mm256_set_pd(-1., 0., 1., 2.);
2057 assert_eq_m256d(r, e);
2058 }
2059
2060 #[simd_test(enable = "avx512f,avx512vl")]
2061 unsafe fn test_mm256_mask3_fmsub_pd() {
2062 let a = _mm256_set1_pd(1.);
2063 let b = _mm256_set_pd(0., 1., 2., 3.);
2064 let c = _mm256_set1_pd(1.);
2065 let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2066 assert_eq_m256d(r, c);
2067 let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2068 let e = _mm256_set_pd(-1., 0., 1., 2.);
2069 assert_eq_m256d(r, e);
2070 }
2071
2072 #[simd_test(enable = "avx512f,avx512vl")]
2073 unsafe fn test_mm_mask_fmsub_pd() {
2074 let a = _mm_set1_pd(1.);
2075 let b = _mm_set_pd(0., 1.);
2076 let c = _mm_set1_pd(1.);
2077 let r = _mm_mask_fmsub_pd(a, 0, b, c);
2078 assert_eq_m128d(r, a);
2079 let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2080 let e = _mm_set_pd(-1., 0.);
2081 assert_eq_m128d(r, e);
2082 }
2083
2084 #[simd_test(enable = "avx512f,avx512vl")]
2085 unsafe fn test_mm_maskz_fmsub_pd() {
2086 let a = _mm_set1_pd(1.);
2087 let b = _mm_set_pd(0., 1.);
2088 let c = _mm_set1_pd(1.);
2089 let r = _mm_maskz_fmsub_pd(0, a, b, c);
2090 assert_eq_m128d(r, _mm_setzero_pd());
2091 let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2092 let e = _mm_set_pd(-1., 0.);
2093 assert_eq_m128d(r, e);
2094 }
2095
2096 #[simd_test(enable = "avx512f,avx512vl")]
2097 unsafe fn test_mm_mask3_fmsub_pd() {
2098 let a = _mm_set1_pd(1.);
2099 let b = _mm_set_pd(0., 1.);
2100 let c = _mm_set1_pd(1.);
2101 let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2102 assert_eq_m128d(r, c);
2103 let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2104 let e = _mm_set_pd(-1., 0.);
2105 assert_eq_m128d(r, e);
2106 }
2107
2108 #[simd_test(enable = "avx512f")]
2109 unsafe fn test_mm512_fmaddsub_pd() {
2110 let a = _mm512_set1_pd(1.);
2111 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2112 let c = _mm512_set1_pd(1.);
2113 let r = _mm512_fmaddsub_pd(a, b, c);
2114 let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2115 assert_eq_m512d(r, e);
2116 }
2117
2118 #[simd_test(enable = "avx512f")]
2119 unsafe fn test_mm512_mask_fmaddsub_pd() {
2120 let a = _mm512_set1_pd(1.);
2121 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2122 let c = _mm512_set1_pd(1.);
2123 let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2124 assert_eq_m512d(r, a);
2125 let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2126 let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2127 assert_eq_m512d(r, e);
2128 }
2129
2130 #[simd_test(enable = "avx512f")]
2131 unsafe fn test_mm512_maskz_fmaddsub_pd() {
2132 let a = _mm512_set1_pd(1.);
2133 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2134 let c = _mm512_set1_pd(1.);
2135 let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2136 assert_eq_m512d(r, _mm512_setzero_pd());
2137 let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2138 let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2139 assert_eq_m512d(r, e);
2140 }
2141
2142 #[simd_test(enable = "avx512f")]
2143 unsafe fn test_mm512_mask3_fmaddsub_pd() {
2144 let a = _mm512_set1_pd(1.);
2145 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2146 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2147 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2148 assert_eq_m512d(r, c);
2149 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2150 let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2151 assert_eq_m512d(r, e);
2152 }
2153
2154 #[simd_test(enable = "avx512f,avx512vl")]
2155 unsafe fn test_mm256_mask_fmaddsub_pd() {
2156 let a = _mm256_set1_pd(1.);
2157 let b = _mm256_set_pd(0., 1., 2., 3.);
2158 let c = _mm256_set1_pd(1.);
2159 let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2160 assert_eq_m256d(r, a);
2161 let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2162 let e = _mm256_set_pd(1., 0., 3., 2.);
2163 assert_eq_m256d(r, e);
2164 }
2165
2166 #[simd_test(enable = "avx512f,avx512vl")]
2167 unsafe fn test_mm256_maskz_fmaddsub_pd() {
2168 let a = _mm256_set1_pd(1.);
2169 let b = _mm256_set_pd(0., 1., 2., 3.);
2170 let c = _mm256_set1_pd(1.);
2171 let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2172 assert_eq_m256d(r, _mm256_setzero_pd());
2173 let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2174 let e = _mm256_set_pd(1., 0., 3., 2.);
2175 assert_eq_m256d(r, e);
2176 }
2177
2178 #[simd_test(enable = "avx512f,avx512vl")]
2179 unsafe fn test_mm256_mask3_fmaddsub_pd() {
2180 let a = _mm256_set1_pd(1.);
2181 let b = _mm256_set_pd(0., 1., 2., 3.);
2182 let c = _mm256_set1_pd(1.);
2183 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2184 assert_eq_m256d(r, c);
2185 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2186 let e = _mm256_set_pd(1., 0., 3., 2.);
2187 assert_eq_m256d(r, e);
2188 }
2189
2190 #[simd_test(enable = "avx512f,avx512vl")]
2191 unsafe fn test_mm_mask_fmaddsub_pd() {
2192 let a = _mm_set1_pd(1.);
2193 let b = _mm_set_pd(0., 1.);
2194 let c = _mm_set1_pd(1.);
2195 let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2196 assert_eq_m128d(r, a);
2197 let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2198 let e = _mm_set_pd(1., 0.);
2199 assert_eq_m128d(r, e);
2200 }
2201
2202 #[simd_test(enable = "avx512f,avx512vl")]
2203 unsafe fn test_mm_maskz_fmaddsub_pd() {
2204 let a = _mm_set1_pd(1.);
2205 let b = _mm_set_pd(0., 1.);
2206 let c = _mm_set1_pd(1.);
2207 let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2208 assert_eq_m128d(r, _mm_setzero_pd());
2209 let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2210 let e = _mm_set_pd(1., 0.);
2211 assert_eq_m128d(r, e);
2212 }
2213
2214 #[simd_test(enable = "avx512f,avx512vl")]
2215 unsafe fn test_mm_mask3_fmaddsub_pd() {
2216 let a = _mm_set1_pd(1.);
2217 let b = _mm_set_pd(0., 1.);
2218 let c = _mm_set1_pd(1.);
2219 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2220 assert_eq_m128d(r, c);
2221 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2222 let e = _mm_set_pd(1., 0.);
2223 assert_eq_m128d(r, e);
2224 }
2225
2226 #[simd_test(enable = "avx512f")]
2227 unsafe fn test_mm512_fmsubadd_pd() {
2228 let a = _mm512_set1_pd(1.);
2229 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2230 let c = _mm512_set1_pd(1.);
2231 let r = _mm512_fmsubadd_pd(a, b, c);
2232 let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2233 assert_eq_m512d(r, e);
2234 }
2235
2236 #[simd_test(enable = "avx512f")]
2237 unsafe fn test_mm512_mask_fmsubadd_pd() {
2238 let a = _mm512_set1_pd(1.);
2239 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2240 let c = _mm512_set1_pd(1.);
2241 let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2242 assert_eq_m512d(r, a);
2243 let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2244 let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2245 assert_eq_m512d(r, e);
2246 }
2247
2248 #[simd_test(enable = "avx512f")]
2249 unsafe fn test_mm512_maskz_fmsubadd_pd() {
2250 let a = _mm512_set1_pd(1.);
2251 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2252 let c = _mm512_set1_pd(1.);
2253 let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2254 assert_eq_m512d(r, _mm512_setzero_pd());
2255 let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2256 let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2257 assert_eq_m512d(r, e);
2258 }
2259
2260 #[simd_test(enable = "avx512f")]
2261 unsafe fn test_mm512_mask3_fmsubadd_pd() {
2262 let a = _mm512_set1_pd(1.);
2263 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2264 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2265 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2266 assert_eq_m512d(r, c);
2267 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2268 let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2269 assert_eq_m512d(r, e);
2270 }
2271
2272 #[simd_test(enable = "avx512f,avx512vl")]
2273 unsafe fn test_mm256_mask_fmsubadd_pd() {
2274 let a = _mm256_set1_pd(1.);
2275 let b = _mm256_set_pd(0., 1., 2., 3.);
2276 let c = _mm256_set1_pd(1.);
2277 let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2278 assert_eq_m256d(r, a);
2279 let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2280 let e = _mm256_set_pd(-1., 2., 1., 4.);
2281 assert_eq_m256d(r, e);
2282 }
2283
2284 #[simd_test(enable = "avx512f,avx512vl")]
2285 unsafe fn test_mm256_maskz_fmsubadd_pd() {
2286 let a = _mm256_set1_pd(1.);
2287 let b = _mm256_set_pd(0., 1., 2., 3.);
2288 let c = _mm256_set1_pd(1.);
2289 let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2290 assert_eq_m256d(r, _mm256_setzero_pd());
2291 let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2292 let e = _mm256_set_pd(-1., 2., 1., 4.);
2293 assert_eq_m256d(r, e);
2294 }
2295
2296 #[simd_test(enable = "avx512f,avx512vl")]
2297 unsafe fn test_mm256_mask3_fmsubadd_pd() {
2298 let a = _mm256_set1_pd(1.);
2299 let b = _mm256_set_pd(0., 1., 2., 3.);
2300 let c = _mm256_set1_pd(1.);
2301 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2302 assert_eq_m256d(r, c);
2303 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2304 let e = _mm256_set_pd(-1., 2., 1., 4.);
2305 assert_eq_m256d(r, e);
2306 }
2307
2308 #[simd_test(enable = "avx512f,avx512vl")]
2309 unsafe fn test_mm_mask_fmsubadd_pd() {
2310 let a = _mm_set1_pd(1.);
2311 let b = _mm_set_pd(0., 1.);
2312 let c = _mm_set1_pd(1.);
2313 let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2314 assert_eq_m128d(r, a);
2315 let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2316 let e = _mm_set_pd(-1., 2.);
2317 assert_eq_m128d(r, e);
2318 }
2319
2320 #[simd_test(enable = "avx512f,avx512vl")]
2321 unsafe fn test_mm_maskz_fmsubadd_pd() {
2322 let a = _mm_set1_pd(1.);
2323 let b = _mm_set_pd(0., 1.);
2324 let c = _mm_set1_pd(1.);
2325 let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2326 assert_eq_m128d(r, _mm_setzero_pd());
2327 let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2328 let e = _mm_set_pd(-1., 2.);
2329 assert_eq_m128d(r, e);
2330 }
2331
2332 #[simd_test(enable = "avx512f,avx512vl")]
2333 unsafe fn test_mm_mask3_fmsubadd_pd() {
2334 let a = _mm_set1_pd(1.);
2335 let b = _mm_set_pd(0., 1.);
2336 let c = _mm_set1_pd(1.);
2337 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2338 assert_eq_m128d(r, c);
2339 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2340 let e = _mm_set_pd(-1., 2.);
2341 assert_eq_m128d(r, e);
2342 }
2343
2344 #[simd_test(enable = "avx512f")]
2345 unsafe fn test_mm512_fnmadd_pd() {
2346 let a = _mm512_set1_pd(1.);
2347 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2348 let c = _mm512_set1_pd(1.);
2349 let r = _mm512_fnmadd_pd(a, b, c);
2350 let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2351 assert_eq_m512d(r, e);
2352 }
2353
2354 #[simd_test(enable = "avx512f")]
2355 unsafe fn test_mm512_mask_fnmadd_pd() {
2356 let a = _mm512_set1_pd(1.);
2357 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2358 let c = _mm512_set1_pd(1.);
2359 let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2360 assert_eq_m512d(r, a);
2361 let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2362 let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2363 assert_eq_m512d(r, e);
2364 }
2365
2366 #[simd_test(enable = "avx512f")]
2367 unsafe fn test_mm512_maskz_fnmadd_pd() {
2368 let a = _mm512_set1_pd(1.);
2369 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2370 let c = _mm512_set1_pd(1.);
2371 let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2372 assert_eq_m512d(r, _mm512_setzero_pd());
2373 let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2374 let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2375 assert_eq_m512d(r, e);
2376 }
2377
2378 #[simd_test(enable = "avx512f")]
2379 unsafe fn test_mm512_mask3_fnmadd_pd() {
2380 let a = _mm512_set1_pd(1.);
2381 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2382 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2383 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2384 assert_eq_m512d(r, c);
2385 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2386 let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2387 assert_eq_m512d(r, e);
2388 }
2389
2390 #[simd_test(enable = "avx512f,avx512vl")]
2391 unsafe fn test_mm256_mask_fnmadd_pd() {
2392 let a = _mm256_set1_pd(1.);
2393 let b = _mm256_set_pd(0., 1., 2., 3.);
2394 let c = _mm256_set1_pd(1.);
2395 let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2396 assert_eq_m256d(r, a);
2397 let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2398 let e = _mm256_set_pd(1., 0., -1., -2.);
2399 assert_eq_m256d(r, e);
2400 }
2401
2402 #[simd_test(enable = "avx512f,avx512vl")]
2403 unsafe fn test_mm256_maskz_fnmadd_pd() {
2404 let a = _mm256_set1_pd(1.);
2405 let b = _mm256_set_pd(0., 1., 2., 3.);
2406 let c = _mm256_set1_pd(1.);
2407 let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2408 assert_eq_m256d(r, _mm256_setzero_pd());
2409 let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2410 let e = _mm256_set_pd(1., 0., -1., -2.);
2411 assert_eq_m256d(r, e);
2412 }
2413
2414 #[simd_test(enable = "avx512f,avx512vl")]
2415 unsafe fn test_mm256_mask3_fnmadd_pd() {
2416 let a = _mm256_set1_pd(1.);
2417 let b = _mm256_set_pd(0., 1., 2., 3.);
2418 let c = _mm256_set1_pd(1.);
2419 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2420 assert_eq_m256d(r, c);
2421 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2422 let e = _mm256_set_pd(1., 0., -1., -2.);
2423 assert_eq_m256d(r, e);
2424 }
2425
2426 #[simd_test(enable = "avx512f,avx512vl")]
2427 unsafe fn test_mm_mask_fnmadd_pd() {
2428 let a = _mm_set1_pd(1.);
2429 let b = _mm_set_pd(0., 1.);
2430 let c = _mm_set1_pd(1.);
2431 let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2432 assert_eq_m128d(r, a);
2433 let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2434 let e = _mm_set_pd(1., 0.);
2435 assert_eq_m128d(r, e);
2436 }
2437
2438 #[simd_test(enable = "avx512f,avx512vl")]
2439 unsafe fn test_mm_maskz_fnmadd_pd() {
2440 let a = _mm_set1_pd(1.);
2441 let b = _mm_set_pd(0., 1.);
2442 let c = _mm_set1_pd(1.);
2443 let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2444 assert_eq_m128d(r, _mm_setzero_pd());
2445 let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2446 let e = _mm_set_pd(1., 0.);
2447 assert_eq_m128d(r, e);
2448 }
2449
2450 #[simd_test(enable = "avx512f,avx512vl")]
2451 unsafe fn test_mm_mask3_fnmadd_pd() {
2452 let a = _mm_set1_pd(1.);
2453 let b = _mm_set_pd(0., 1.);
2454 let c = _mm_set1_pd(1.);
2455 let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2456 assert_eq_m128d(r, c);
2457 let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2458 let e = _mm_set_pd(1., 0.);
2459 assert_eq_m128d(r, e);
2460 }
2461
2462 #[simd_test(enable = "avx512f")]
2463 unsafe fn test_mm512_fnmsub_pd() {
2464 let a = _mm512_set1_pd(1.);
2465 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2466 let c = _mm512_set1_pd(1.);
2467 let r = _mm512_fnmsub_pd(a, b, c);
2468 let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2469 assert_eq_m512d(r, e);
2470 }
2471
2472 #[simd_test(enable = "avx512f")]
2473 unsafe fn test_mm512_mask_fnmsub_pd() {
2474 let a = _mm512_set1_pd(1.);
2475 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2476 let c = _mm512_set1_pd(1.);
2477 let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2478 assert_eq_m512d(r, a);
2479 let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2480 let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2481 assert_eq_m512d(r, e);
2482 }
2483
2484 #[simd_test(enable = "avx512f")]
2485 unsafe fn test_mm512_maskz_fnmsub_pd() {
2486 let a = _mm512_set1_pd(1.);
2487 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2488 let c = _mm512_set1_pd(1.);
2489 let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2490 assert_eq_m512d(r, _mm512_setzero_pd());
2491 let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2492 let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2493 assert_eq_m512d(r, e);
2494 }
2495
2496 #[simd_test(enable = "avx512f")]
2497 unsafe fn test_mm512_mask3_fnmsub_pd() {
2498 let a = _mm512_set1_pd(1.);
2499 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2500 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2501 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2502 assert_eq_m512d(r, c);
2503 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2504 let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2505 assert_eq_m512d(r, e);
2506 }
2507
2508 #[simd_test(enable = "avx512f,avx512vl")]
2509 unsafe fn test_mm256_mask_fnmsub_pd() {
2510 let a = _mm256_set1_pd(1.);
2511 let b = _mm256_set_pd(0., 1., 2., 3.);
2512 let c = _mm256_set1_pd(1.);
2513 let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2514 assert_eq_m256d(r, a);
2515 let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2516 let e = _mm256_set_pd(-1., -2., -3., -4.);
2517 assert_eq_m256d(r, e);
2518 }
2519
2520 #[simd_test(enable = "avx512f,avx512vl")]
2521 unsafe fn test_mm256_maskz_fnmsub_pd() {
2522 let a = _mm256_set1_pd(1.);
2523 let b = _mm256_set_pd(0., 1., 2., 3.);
2524 let c = _mm256_set1_pd(1.);
2525 let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2526 assert_eq_m256d(r, _mm256_setzero_pd());
2527 let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2528 let e = _mm256_set_pd(-1., -2., -3., -4.);
2529 assert_eq_m256d(r, e);
2530 }
2531
2532 #[simd_test(enable = "avx512f,avx512vl")]
2533 unsafe fn test_mm256_mask3_fnmsub_pd() {
2534 let a = _mm256_set1_pd(1.);
2535 let b = _mm256_set_pd(0., 1., 2., 3.);
2536 let c = _mm256_set1_pd(1.);
2537 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2538 assert_eq_m256d(r, c);
2539 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2540 let e = _mm256_set_pd(-1., -2., -3., -4.);
2541 assert_eq_m256d(r, e);
2542 }
2543
2544 #[simd_test(enable = "avx512f,avx512vl")]
2545 unsafe fn test_mm_mask_fnmsub_pd() {
2546 let a = _mm_set1_pd(1.);
2547 let b = _mm_set_pd(0., 1.);
2548 let c = _mm_set1_pd(1.);
2549 let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2550 assert_eq_m128d(r, a);
2551 let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2552 let e = _mm_set_pd(-1., -2.);
2553 assert_eq_m128d(r, e);
2554 }
2555
2556 #[simd_test(enable = "avx512f,avx512vl")]
2557 unsafe fn test_mm_maskz_fnmsub_pd() {
2558 let a = _mm_set1_pd(1.);
2559 let b = _mm_set_pd(0., 1.);
2560 let c = _mm_set1_pd(1.);
2561 let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2562 assert_eq_m128d(r, _mm_setzero_pd());
2563 let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2564 let e = _mm_set_pd(-1., -2.);
2565 assert_eq_m128d(r, e);
2566 }
2567
2568 #[simd_test(enable = "avx512f,avx512vl")]
2569 unsafe fn test_mm_mask3_fnmsub_pd() {
2570 let a = _mm_set1_pd(1.);
2571 let b = _mm_set_pd(0., 1.);
2572 let c = _mm_set1_pd(1.);
2573 let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2574 assert_eq_m128d(r, c);
2575 let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2576 let e = _mm_set_pd(-1., -2.);
2577 assert_eq_m128d(r, e);
2578 }
2579
2580 #[simd_test(enable = "avx512f")]
2581 unsafe fn test_mm512_rcp14_pd() {
2582 let a = _mm512_set1_pd(3.);
2583 let r = _mm512_rcp14_pd(a);
2584 let e = _mm512_set1_pd(0.3333320617675781);
2585 assert_eq_m512d(r, e);
2586 }
2587
2588 #[simd_test(enable = "avx512f")]
2589 unsafe fn test_mm512_mask_rcp14_pd() {
2590 let a = _mm512_set1_pd(3.);
2591 let r = _mm512_mask_rcp14_pd(a, 0, a);
2592 assert_eq_m512d(r, a);
2593 let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2594 #[rustfmt::skip]
2595 let e = _mm512_setr_pd(
2596 3., 3., 3., 3.,
2597 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2598 );
2599 assert_eq_m512d(r, e);
2600 }
2601
2602 #[simd_test(enable = "avx512f")]
2603 unsafe fn test_mm512_maskz_rcp14_pd() {
2604 let a = _mm512_set1_pd(3.);
2605 let r = _mm512_maskz_rcp14_pd(0, a);
2606 assert_eq_m512d(r, _mm512_setzero_pd());
2607 let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2608 #[rustfmt::skip]
2609 let e = _mm512_setr_pd(
2610 0., 0., 0., 0.,
2611 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2612 );
2613 assert_eq_m512d(r, e);
2614 }
2615
2616 #[simd_test(enable = "avx512f,avx512vl")]
2617 unsafe fn test_mm256_rcp14_pd() {
2618 let a = _mm256_set1_pd(3.);
2619 let r = _mm256_rcp14_pd(a);
2620 let e = _mm256_set1_pd(0.3333320617675781);
2621 assert_eq_m256d(r, e);
2622 }
2623
2624 #[simd_test(enable = "avx512f,avx512vl")]
2625 unsafe fn test_mm256_mask_rcp14_pd() {
2626 let a = _mm256_set1_pd(3.);
2627 let r = _mm256_mask_rcp14_pd(a, 0, a);
2628 assert_eq_m256d(r, a);
2629 let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2630 let e = _mm256_set1_pd(0.3333320617675781);
2631 assert_eq_m256d(r, e);
2632 }
2633
2634 #[simd_test(enable = "avx512f,avx512vl")]
2635 unsafe fn test_mm256_maskz_rcp14_pd() {
2636 let a = _mm256_set1_pd(3.);
2637 let r = _mm256_maskz_rcp14_pd(0, a);
2638 assert_eq_m256d(r, _mm256_setzero_pd());
2639 let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2640 let e = _mm256_set1_pd(0.3333320617675781);
2641 assert_eq_m256d(r, e);
2642 }
2643
2644 #[simd_test(enable = "avx512f,avx512vl")]
2645 unsafe fn test_mm_rcp14_pd() {
2646 let a = _mm_set1_pd(3.);
2647 let r = _mm_rcp14_pd(a);
2648 let e = _mm_set1_pd(0.3333320617675781);
2649 assert_eq_m128d(r, e);
2650 }
2651
2652 #[simd_test(enable = "avx512f,avx512vl")]
2653 unsafe fn test_mm_mask_rcp14_pd() {
2654 let a = _mm_set1_pd(3.);
2655 let r = _mm_mask_rcp14_pd(a, 0, a);
2656 assert_eq_m128d(r, a);
2657 let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2658 let e = _mm_set1_pd(0.3333320617675781);
2659 assert_eq_m128d(r, e);
2660 }
2661
2662 #[simd_test(enable = "avx512f,avx512vl")]
2663 unsafe fn test_mm_maskz_rcp14_pd() {
2664 let a = _mm_set1_pd(3.);
2665 let r = _mm_maskz_rcp14_pd(0, a);
2666 assert_eq_m128d(r, _mm_setzero_pd());
2667 let r = _mm_maskz_rcp14_pd(0b00000011, a);
2668 let e = _mm_set1_pd(0.3333320617675781);
2669 assert_eq_m128d(r, e);
2670 }
2671
2672 #[simd_test(enable = "avx512f")]
2673 unsafe fn test_mm512_rsqrt14_pd() {
2674 let a = _mm512_set1_pd(3.);
2675 let r = _mm512_rsqrt14_pd(a);
2676 let e = _mm512_set1_pd(0.5773391723632813);
2677 assert_eq_m512d(r, e);
2678 }
2679
2680 #[simd_test(enable = "avx512f")]
2681 unsafe fn test_mm512_mask_rsqrt14_pd() {
2682 let a = _mm512_set1_pd(3.);
2683 let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2684 assert_eq_m512d(r, a);
2685 let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2686 #[rustfmt::skip]
2687 let e = _mm512_setr_pd(
2688 3., 3., 3., 3.,
2689 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2690 );
2691 assert_eq_m512d(r, e);
2692 }
2693
2694 #[simd_test(enable = "avx512f")]
2695 unsafe fn test_mm512_maskz_rsqrt14_pd() {
2696 let a = _mm512_set1_pd(3.);
2697 let r = _mm512_maskz_rsqrt14_pd(0, a);
2698 assert_eq_m512d(r, _mm512_setzero_pd());
2699 let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2700 #[rustfmt::skip]
2701 let e = _mm512_setr_pd(
2702 0., 0., 0., 0.,
2703 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2704 );
2705 assert_eq_m512d(r, e);
2706 }
2707
2708 #[simd_test(enable = "avx512f,avx512vl")]
2709 unsafe fn test_mm256_mask_rsqrt14_pd() {
2710 let a = _mm256_set1_pd(3.);
2711 let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2712 assert_eq_m256d(r, a);
2713 let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2714 let e = _mm256_set1_pd(0.5773391723632813);
2715 assert_eq_m256d(r, e);
2716 }
2717
2718 #[simd_test(enable = "avx512f,avx512vl")]
2719 unsafe fn test_mm256_maskz_rsqrt14_pd() {
2720 let a = _mm256_set1_pd(3.);
2721 let r = _mm256_maskz_rsqrt14_pd(0, a);
2722 assert_eq_m256d(r, _mm256_setzero_pd());
2723 let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2724 let e = _mm256_set1_pd(0.5773391723632813);
2725 assert_eq_m256d(r, e);
2726 }
2727
2728 #[simd_test(enable = "avx512f,avx512vl")]
2729 unsafe fn test_mm_mask_rsqrt14_pd() {
2730 let a = _mm_set1_pd(3.);
2731 let r = _mm_mask_rsqrt14_pd(a, 0, a);
2732 assert_eq_m128d(r, a);
2733 let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2734 let e = _mm_set1_pd(0.5773391723632813);
2735 assert_eq_m128d(r, e);
2736 }
2737
2738 #[simd_test(enable = "avx512f,avx512vl")]
2739 unsafe fn test_mm_maskz_rsqrt14_pd() {
2740 let a = _mm_set1_pd(3.);
2741 let r = _mm_maskz_rsqrt14_pd(0, a);
2742 assert_eq_m128d(r, _mm_setzero_pd());
2743 let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2744 let e = _mm_set1_pd(0.5773391723632813);
2745 assert_eq_m128d(r, e);
2746 }
2747
2748 #[simd_test(enable = "avx512f")]
2749 unsafe fn test_mm512_getexp_pd() {
2750 let a = _mm512_set1_pd(3.);
2751 let r = _mm512_getexp_pd(a);
2752 let e = _mm512_set1_pd(1.);
2753 assert_eq_m512d(r, e);
2754 }
2755
2756 #[simd_test(enable = "avx512f")]
2757 unsafe fn test_mm512_mask_getexp_pd() {
2758 let a = _mm512_set1_pd(3.);
2759 let r = _mm512_mask_getexp_pd(a, 0, a);
2760 assert_eq_m512d(r, a);
2761 let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2762 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2763 assert_eq_m512d(r, e);
2764 }
2765
2766 #[simd_test(enable = "avx512f")]
2767 unsafe fn test_mm512_maskz_getexp_pd() {
2768 let a = _mm512_set1_pd(3.);
2769 let r = _mm512_maskz_getexp_pd(0, a);
2770 assert_eq_m512d(r, _mm512_setzero_pd());
2771 let r = _mm512_maskz_getexp_pd(0b11110000, a);
2772 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2773 assert_eq_m512d(r, e);
2774 }
2775
2776 #[simd_test(enable = "avx512f,avx512vl")]
2777 unsafe fn test_mm256_getexp_pd() {
2778 let a = _mm256_set1_pd(3.);
2779 let r = _mm256_getexp_pd(a);
2780 let e = _mm256_set1_pd(1.);
2781 assert_eq_m256d(r, e);
2782 }
2783
2784 #[simd_test(enable = "avx512f,avx512vl")]
2785 unsafe fn test_mm256_mask_getexp_pd() {
2786 let a = _mm256_set1_pd(3.);
2787 let r = _mm256_mask_getexp_pd(a, 0, a);
2788 assert_eq_m256d(r, a);
2789 let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2790 let e = _mm256_set1_pd(1.);
2791 assert_eq_m256d(r, e);
2792 }
2793
2794 #[simd_test(enable = "avx512f,avx512vl")]
2795 unsafe fn test_mm256_maskz_getexp_pd() {
2796 let a = _mm256_set1_pd(3.);
2797 let r = _mm256_maskz_getexp_pd(0, a);
2798 assert_eq_m256d(r, _mm256_setzero_pd());
2799 let r = _mm256_maskz_getexp_pd(0b00001111, a);
2800 let e = _mm256_set1_pd(1.);
2801 assert_eq_m256d(r, e);
2802 }
2803
2804 #[simd_test(enable = "avx512f,avx512vl")]
2805 unsafe fn test_mm_getexp_pd() {
2806 let a = _mm_set1_pd(3.);
2807 let r = _mm_getexp_pd(a);
2808 let e = _mm_set1_pd(1.);
2809 assert_eq_m128d(r, e);
2810 }
2811
2812 #[simd_test(enable = "avx512f,avx512vl")]
2813 unsafe fn test_mm_mask_getexp_pd() {
2814 let a = _mm_set1_pd(3.);
2815 let r = _mm_mask_getexp_pd(a, 0, a);
2816 assert_eq_m128d(r, a);
2817 let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2818 let e = _mm_set1_pd(1.);
2819 assert_eq_m128d(r, e);
2820 }
2821
2822 #[simd_test(enable = "avx512f,avx512vl")]
2823 unsafe fn test_mm_maskz_getexp_pd() {
2824 let a = _mm_set1_pd(3.);
2825 let r = _mm_maskz_getexp_pd(0, a);
2826 assert_eq_m128d(r, _mm_setzero_pd());
2827 let r = _mm_maskz_getexp_pd(0b00000011, a);
2828 let e = _mm_set1_pd(1.);
2829 assert_eq_m128d(r, e);
2830 }
2831
2832 #[simd_test(enable = "avx512f")]
2833 unsafe fn test_mm512_roundscale_pd() {
2834 let a = _mm512_set1_pd(1.1);
2835 let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
2836 let e = _mm512_set1_pd(1.0);
2837 assert_eq_m512d(r, e);
2838 }
2839
2840 #[simd_test(enable = "avx512f")]
2841 unsafe fn test_mm512_mask_roundscale_pd() {
2842 let a = _mm512_set1_pd(1.1);
2843 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2844 let e = _mm512_set1_pd(1.1);
2845 assert_eq_m512d(r, e);
2846 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
2847 let e = _mm512_set1_pd(1.0);
2848 assert_eq_m512d(r, e);
2849 }
2850
2851 #[simd_test(enable = "avx512f")]
2852 unsafe fn test_mm512_maskz_roundscale_pd() {
2853 let a = _mm512_set1_pd(1.1);
2854 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2855 assert_eq_m512d(r, _mm512_setzero_pd());
2856 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
2857 let e = _mm512_set1_pd(1.0);
2858 assert_eq_m512d(r, e);
2859 }
2860
2861 #[simd_test(enable = "avx512f,avx512vl")]
2862 unsafe fn test_mm256_roundscale_pd() {
2863 let a = _mm256_set1_pd(1.1);
2864 let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
2865 let e = _mm256_set1_pd(1.0);
2866 assert_eq_m256d(r, e);
2867 }
2868
2869 #[simd_test(enable = "avx512f,avx512vl")]
2870 unsafe fn test_mm256_mask_roundscale_pd() {
2871 let a = _mm256_set1_pd(1.1);
2872 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2873 assert_eq_m256d(r, a);
2874 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
2875 let e = _mm256_set1_pd(1.0);
2876 assert_eq_m256d(r, e);
2877 }
2878
2879 #[simd_test(enable = "avx512f,avx512vl")]
2880 unsafe fn test_mm256_maskz_roundscale_pd() {
2881 let a = _mm256_set1_pd(1.1);
2882 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2883 assert_eq_m256d(r, _mm256_setzero_pd());
2884 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
2885 let e = _mm256_set1_pd(1.0);
2886 assert_eq_m256d(r, e);
2887 }
2888
2889 #[simd_test(enable = "avx512f,avx512vl")]
2890 unsafe fn test_mm_roundscale_pd() {
2891 let a = _mm_set1_pd(1.1);
2892 let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
2893 let e = _mm_set1_pd(1.0);
2894 assert_eq_m128d(r, e);
2895 }
2896
2897 #[simd_test(enable = "avx512f,avx512vl")]
2898 unsafe fn test_mm_mask_roundscale_pd() {
2899 let a = _mm_set1_pd(1.1);
2900 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2901 let e = _mm_set1_pd(1.1);
2902 assert_eq_m128d(r, e);
2903 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
2904 let e = _mm_set1_pd(1.0);
2905 assert_eq_m128d(r, e);
2906 }
2907
2908 #[simd_test(enable = "avx512f,avx512vl")]
2909 unsafe fn test_mm_maskz_roundscale_pd() {
2910 let a = _mm_set1_pd(1.1);
2911 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2912 assert_eq_m128d(r, _mm_setzero_pd());
2913 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
2914 let e = _mm_set1_pd(1.0);
2915 assert_eq_m128d(r, e);
2916 }
2917
2918 #[simd_test(enable = "avx512f")]
2919 unsafe fn test_mm512_scalef_pd() {
2920 let a = _mm512_set1_pd(1.);
2921 let b = _mm512_set1_pd(3.);
2922 let r = _mm512_scalef_pd(a, b);
2923 let e = _mm512_set1_pd(8.);
2924 assert_eq_m512d(r, e);
2925 }
2926
2927 #[simd_test(enable = "avx512f")]
2928 unsafe fn test_mm512_mask_scalef_pd() {
2929 let a = _mm512_set1_pd(1.);
2930 let b = _mm512_set1_pd(3.);
2931 let r = _mm512_mask_scalef_pd(a, 0, a, b);
2932 assert_eq_m512d(r, a);
2933 let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
2934 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
2935 assert_eq_m512d(r, e);
2936 }
2937
2938 #[simd_test(enable = "avx512f")]
2939 unsafe fn test_mm512_maskz_scalef_pd() {
2940 let a = _mm512_set1_pd(1.);
2941 let b = _mm512_set1_pd(3.);
2942 let r = _mm512_maskz_scalef_pd(0, a, b);
2943 assert_eq_m512d(r, _mm512_setzero_pd());
2944 let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
2945 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
2946 assert_eq_m512d(r, e);
2947 }
2948
2949 #[simd_test(enable = "avx512f,avx512vl")]
2950 unsafe fn test_mm256_scalef_pd() {
2951 let a = _mm256_set1_pd(1.);
2952 let b = _mm256_set1_pd(3.);
2953 let r = _mm256_scalef_pd(a, b);
2954 let e = _mm256_set1_pd(8.);
2955 assert_eq_m256d(r, e);
2956 }
2957
2958 #[simd_test(enable = "avx512f,avx512vl")]
2959 unsafe fn test_mm256_mask_scalef_pd() {
2960 let a = _mm256_set1_pd(1.);
2961 let b = _mm256_set1_pd(3.);
2962 let r = _mm256_mask_scalef_pd(a, 0, a, b);
2963 assert_eq_m256d(r, a);
2964 let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
2965 let e = _mm256_set1_pd(8.);
2966 assert_eq_m256d(r, e);
2967 }
2968
2969 #[simd_test(enable = "avx512f,avx512vl")]
2970 unsafe fn test_mm256_maskz_scalef_pd() {
2971 let a = _mm256_set1_pd(1.);
2972 let b = _mm256_set1_pd(3.);
2973 let r = _mm256_maskz_scalef_pd(0, a, b);
2974 assert_eq_m256d(r, _mm256_setzero_pd());
2975 let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
2976 let e = _mm256_set1_pd(8.);
2977 assert_eq_m256d(r, e);
2978 }
2979
2980 #[simd_test(enable = "avx512f,avx512vl")]
2981 unsafe fn test_mm_scalef_pd() {
2982 let a = _mm_set1_pd(1.);
2983 let b = _mm_set1_pd(3.);
2984 let r = _mm_scalef_pd(a, b);
2985 let e = _mm_set1_pd(8.);
2986 assert_eq_m128d(r, e);
2987 }
2988
2989 #[simd_test(enable = "avx512f,avx512vl")]
2990 unsafe fn test_mm_mask_scalef_pd() {
2991 let a = _mm_set1_pd(1.);
2992 let b = _mm_set1_pd(3.);
2993 let r = _mm_mask_scalef_pd(a, 0, a, b);
2994 assert_eq_m128d(r, a);
2995 let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
2996 let e = _mm_set1_pd(8.);
2997 assert_eq_m128d(r, e);
2998 }
2999
3000 #[simd_test(enable = "avx512f,avx512vl")]
3001 unsafe fn test_mm_maskz_scalef_pd() {
3002 let a = _mm_set1_pd(1.);
3003 let b = _mm_set1_pd(3.);
3004 let r = _mm_maskz_scalef_pd(0, a, b);
3005 assert_eq_m128d(r, _mm_setzero_pd());
3006 let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3007 let e = _mm_set1_pd(8.);
3008 assert_eq_m128d(r, e);
3009 }
3010
3011 #[simd_test(enable = "avx512f")]
3012 unsafe fn test_mm512_fixupimm_pd() {
3013 let a = _mm512_set1_pd(f64::NAN);
3014 let b = _mm512_set1_pd(f64::MAX);
3015 let c = _mm512_set1_epi64(i32::MAX as i64);
3016 let r = _mm512_fixupimm_pd::<5>(a, b, c);
3017 let e = _mm512_set1_pd(0.0);
3018 assert_eq_m512d(r, e);
3019 }
3020
3021 #[simd_test(enable = "avx512f")]
3022 unsafe fn test_mm512_mask_fixupimm_pd() {
3023 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3024 let b = _mm512_set1_pd(f64::MAX);
3025 let c = _mm512_set1_epi64(i32::MAX as i64);
3026 let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3027 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3028 assert_eq_m512d(r, e);
3029 }
3030
3031 #[simd_test(enable = "avx512f")]
3032 unsafe fn test_mm512_maskz_fixupimm_pd() {
3033 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3034 let b = _mm512_set1_pd(f64::MAX);
3035 let c = _mm512_set1_epi64(i32::MAX as i64);
3036 let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3037 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3038 assert_eq_m512d(r, e);
3039 }
3040
3041 #[simd_test(enable = "avx512f,avx512vl")]
3042 unsafe fn test_mm256_fixupimm_pd() {
3043 let a = _mm256_set1_pd(f64::NAN);
3044 let b = _mm256_set1_pd(f64::MAX);
3045 let c = _mm256_set1_epi64x(i32::MAX as i64);
3046 let r = _mm256_fixupimm_pd::<5>(a, b, c);
3047 let e = _mm256_set1_pd(0.0);
3048 assert_eq_m256d(r, e);
3049 }
3050
3051 #[simd_test(enable = "avx512f,avx512vl")]
3052 unsafe fn test_mm256_mask_fixupimm_pd() {
3053 let a = _mm256_set1_pd(f64::NAN);
3054 let b = _mm256_set1_pd(f64::MAX);
3055 let c = _mm256_set1_epi64x(i32::MAX as i64);
3056 let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3057 let e = _mm256_set1_pd(0.0);
3058 assert_eq_m256d(r, e);
3059 }
3060
3061 #[simd_test(enable = "avx512f,avx512vl")]
3062 unsafe fn test_mm256_maskz_fixupimm_pd() {
3063 let a = _mm256_set1_pd(f64::NAN);
3064 let b = _mm256_set1_pd(f64::MAX);
3065 let c = _mm256_set1_epi64x(i32::MAX as i64);
3066 let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3067 let e = _mm256_set1_pd(0.0);
3068 assert_eq_m256d(r, e);
3069 }
3070
3071 #[simd_test(enable = "avx512f,avx512vl")]
3072 unsafe fn test_mm_fixupimm_pd() {
3073 let a = _mm_set1_pd(f64::NAN);
3074 let b = _mm_set1_pd(f64::MAX);
3075 let c = _mm_set1_epi64x(i32::MAX as i64);
3076 let r = _mm_fixupimm_pd::<5>(a, b, c);
3077 let e = _mm_set1_pd(0.0);
3078 assert_eq_m128d(r, e);
3079 }
3080
3081 #[simd_test(enable = "avx512f,avx512vl")]
3082 unsafe fn test_mm_mask_fixupimm_pd() {
3083 let a = _mm_set1_pd(f64::NAN);
3084 let b = _mm_set1_pd(f64::MAX);
3085 let c = _mm_set1_epi64x(i32::MAX as i64);
3086 let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3087 let e = _mm_set1_pd(0.0);
3088 assert_eq_m128d(r, e);
3089 }
3090
3091 #[simd_test(enable = "avx512f,avx512vl")]
3092 unsafe fn test_mm_maskz_fixupimm_pd() {
3093 let a = _mm_set1_pd(f64::NAN);
3094 let b = _mm_set1_pd(f64::MAX);
3095 let c = _mm_set1_epi64x(i32::MAX as i64);
3096 let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3097 let e = _mm_set1_pd(0.0);
3098 assert_eq_m128d(r, e);
3099 }
3100
3101 #[simd_test(enable = "avx512f")]
3102 unsafe fn test_mm512_ternarylogic_epi64() {
3103 let a = _mm512_set1_epi64(1 << 2);
3104 let b = _mm512_set1_epi64(1 << 1);
3105 let c = _mm512_set1_epi64(1 << 0);
3106 let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3107 let e = _mm512_set1_epi64(0);
3108 assert_eq_m512i(r, e);
3109 }
3110
3111 #[simd_test(enable = "avx512f")]
3112 unsafe fn test_mm512_mask_ternarylogic_epi64() {
3113 let src = _mm512_set1_epi64(1 << 2);
3114 let a = _mm512_set1_epi64(1 << 1);
3115 let b = _mm512_set1_epi64(1 << 0);
3116 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3117 assert_eq_m512i(r, src);
3118 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3119 let e = _mm512_set1_epi64(0);
3120 assert_eq_m512i(r, e);
3121 }
3122
3123 #[simd_test(enable = "avx512f")]
3124 unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3125 let a = _mm512_set1_epi64(1 << 2);
3126 let b = _mm512_set1_epi64(1 << 1);
3127 let c = _mm512_set1_epi64(1 << 0);
3128 let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3129 assert_eq_m512i(r, _mm512_setzero_si512());
3130 let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3131 let e = _mm512_set1_epi64(0);
3132 assert_eq_m512i(r, e);
3133 }
3134
3135 #[simd_test(enable = "avx512f,avx512vl")]
3136 unsafe fn test_mm256_ternarylogic_epi64() {
3137 let a = _mm256_set1_epi64x(1 << 2);
3138 let b = _mm256_set1_epi64x(1 << 1);
3139 let c = _mm256_set1_epi64x(1 << 0);
3140 let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3141 let e = _mm256_set1_epi64x(0);
3142 assert_eq_m256i(r, e);
3143 }
3144
3145 #[simd_test(enable = "avx512f,avx512vl")]
3146 unsafe fn test_mm256_mask_ternarylogic_epi64() {
3147 let src = _mm256_set1_epi64x(1 << 2);
3148 let a = _mm256_set1_epi64x(1 << 1);
3149 let b = _mm256_set1_epi64x(1 << 0);
3150 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3151 assert_eq_m256i(r, src);
3152 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3153 let e = _mm256_set1_epi64x(0);
3154 assert_eq_m256i(r, e);
3155 }
3156
3157 #[simd_test(enable = "avx512f,avx512vl")]
3158 unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3159 let a = _mm256_set1_epi64x(1 << 2);
3160 let b = _mm256_set1_epi64x(1 << 1);
3161 let c = _mm256_set1_epi64x(1 << 0);
3162 let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3163 assert_eq_m256i(r, _mm256_setzero_si256());
3164 let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3165 let e = _mm256_set1_epi64x(0);
3166 assert_eq_m256i(r, e);
3167 }
3168
3169 #[simd_test(enable = "avx512f,avx512vl")]
3170 unsafe fn test_mm_ternarylogic_epi64() {
3171 let a = _mm_set1_epi64x(1 << 2);
3172 let b = _mm_set1_epi64x(1 << 1);
3173 let c = _mm_set1_epi64x(1 << 0);
3174 let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3175 let e = _mm_set1_epi64x(0);
3176 assert_eq_m128i(r, e);
3177 }
3178
3179 #[simd_test(enable = "avx512f,avx512vl")]
3180 unsafe fn test_mm_mask_ternarylogic_epi64() {
3181 let src = _mm_set1_epi64x(1 << 2);
3182 let a = _mm_set1_epi64x(1 << 1);
3183 let b = _mm_set1_epi64x(1 << 0);
3184 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3185 assert_eq_m128i(r, src);
3186 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3187 let e = _mm_set1_epi64x(0);
3188 assert_eq_m128i(r, e);
3189 }
3190
3191 #[simd_test(enable = "avx512f,avx512vl")]
3192 unsafe fn test_mm_maskz_ternarylogic_epi64() {
3193 let a = _mm_set1_epi64x(1 << 2);
3194 let b = _mm_set1_epi64x(1 << 1);
3195 let c = _mm_set1_epi64x(1 << 0);
3196 let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3197 assert_eq_m128i(r, _mm_setzero_si128());
3198 let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3199 let e = _mm_set1_epi64x(0);
3200 assert_eq_m128i(r, e);
3201 }
3202
3203 #[simd_test(enable = "avx512f")]
3204 unsafe fn test_mm512_getmant_pd() {
3205 let a = _mm512_set1_pd(10.);
3206 let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3207 let e = _mm512_set1_pd(1.25);
3208 assert_eq_m512d(r, e);
3209 }
3210
3211 #[simd_test(enable = "avx512f")]
3212 unsafe fn test_mm512_mask_getmant_pd() {
3213 let a = _mm512_set1_pd(10.);
3214 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3215 assert_eq_m512d(r, a);
3216 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3217 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3218 assert_eq_m512d(r, e);
3219 }
3220
3221 #[simd_test(enable = "avx512f")]
3222 unsafe fn test_mm512_maskz_getmant_pd() {
3223 let a = _mm512_set1_pd(10.);
3224 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3225 assert_eq_m512d(r, _mm512_setzero_pd());
3226 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3227 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3228 assert_eq_m512d(r, e);
3229 }
3230
3231 #[simd_test(enable = "avx512f,avx512vl")]
3232 unsafe fn test_mm256_getmant_pd() {
3233 let a = _mm256_set1_pd(10.);
3234 let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3235 let e = _mm256_set1_pd(1.25);
3236 assert_eq_m256d(r, e);
3237 }
3238
3239 #[simd_test(enable = "avx512f,avx512vl")]
3240 unsafe fn test_mm256_mask_getmant_pd() {
3241 let a = _mm256_set1_pd(10.);
3242 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3243 assert_eq_m256d(r, a);
3244 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3245 let e = _mm256_set1_pd(1.25);
3246 assert_eq_m256d(r, e);
3247 }
3248
3249 #[simd_test(enable = "avx512f,avx512vl")]
3250 unsafe fn test_mm256_maskz_getmant_pd() {
3251 let a = _mm256_set1_pd(10.);
3252 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3253 assert_eq_m256d(r, _mm256_setzero_pd());
3254 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3255 let e = _mm256_set1_pd(1.25);
3256 assert_eq_m256d(r, e);
3257 }
3258
3259 #[simd_test(enable = "avx512f,avx512vl")]
3260 unsafe fn test_mm_getmant_pd() {
3261 let a = _mm_set1_pd(10.);
3262 let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3263 let e = _mm_set1_pd(1.25);
3264 assert_eq_m128d(r, e);
3265 }
3266
3267 #[simd_test(enable = "avx512f,avx512vl")]
3268 unsafe fn test_mm_mask_getmant_pd() {
3269 let a = _mm_set1_pd(10.);
3270 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3271 assert_eq_m128d(r, a);
3272 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3273 let e = _mm_set1_pd(1.25);
3274 assert_eq_m128d(r, e);
3275 }
3276
3277 #[simd_test(enable = "avx512f,avx512vl")]
3278 unsafe fn test_mm_maskz_getmant_pd() {
3279 let a = _mm_set1_pd(10.);
3280 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3281 assert_eq_m128d(r, _mm_setzero_pd());
3282 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3283 let e = _mm_set1_pd(1.25);
3284 assert_eq_m128d(r, e);
3285 }
3286
3287 #[simd_test(enable = "avx512f")]
3288 unsafe fn test_mm512_cvtps_pd() {
3289 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3290 let r = _mm512_cvtps_pd(a);
3291 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3292 assert_eq_m512d(r, e);
3293 }
3294
3295 #[simd_test(enable = "avx512f")]
3296 unsafe fn test_mm512_mask_cvtps_pd() {
3297 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3298 let src = _mm512_set1_pd(0.);
3299 let r = _mm512_mask_cvtps_pd(src, 0, a);
3300 assert_eq_m512d(r, src);
3301 let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3302 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3303 assert_eq_m512d(r, e);
3304 }
3305
3306 #[simd_test(enable = "avx512f")]
3307 unsafe fn test_mm512_maskz_cvtps_pd() {
3308 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3309 let r = _mm512_maskz_cvtps_pd(0, a);
3310 assert_eq_m512d(r, _mm512_setzero_pd());
3311 let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3312 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3313 assert_eq_m512d(r, e);
3314 }
3315
3316 #[simd_test(enable = "avx512f")]
3317 unsafe fn test_mm512_cvtpslo_pd() {
3318 let v2 = _mm512_setr_ps(
3319 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3320 );
3321 let r = _mm512_cvtpslo_pd(v2);
3322 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3323 assert_eq_m512d(r, e);
3324 }
3325
3326 #[simd_test(enable = "avx512f")]
3327 unsafe fn test_mm512_mask_cvtpslo_pd() {
3328 let v2 = _mm512_setr_ps(
3329 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3330 );
3331 let src = _mm512_set1_pd(0.);
3332 let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3333 assert_eq_m512d(r, src);
3334 let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3335 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3336 assert_eq_m512d(r, e);
3337 }
3338
3339 #[simd_test(enable = "avx512f")]
3340 unsafe fn test_mm512_cvtpd_ps() {
3341 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3342 let r = _mm512_cvtpd_ps(a);
3343 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3344 assert_eq_m256(r, e);
3345 }
3346
3347 #[simd_test(enable = "avx512f")]
3348 unsafe fn test_mm512_mask_cvtpd_ps() {
3349 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3350 let src = _mm256_set1_ps(0.);
3351 let r = _mm512_mask_cvtpd_ps(src, 0, a);
3352 assert_eq_m256(r, src);
3353 let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3354 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3355 assert_eq_m256(r, e);
3356 }
3357
3358 #[simd_test(enable = "avx512f")]
3359 unsafe fn test_mm512_maskz_cvtpd_ps() {
3360 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3361 let r = _mm512_maskz_cvtpd_ps(0, a);
3362 assert_eq_m256(r, _mm256_setzero_ps());
3363 let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3364 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3365 assert_eq_m256(r, e);
3366 }
3367
3368 #[simd_test(enable = "avx512f,avx512vl")]
3369 unsafe fn test_mm256_mask_cvtpd_ps() {
3370 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3371 let src = _mm_set1_ps(0.);
3372 let r = _mm256_mask_cvtpd_ps(src, 0, a);
3373 assert_eq_m128(r, src);
3374 let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3375 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3376 assert_eq_m128(r, e);
3377 }
3378
3379 #[simd_test(enable = "avx512f,avx512vl")]
3380 unsafe fn test_mm256_maskz_cvtpd_ps() {
3381 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3382 let r = _mm256_maskz_cvtpd_ps(0, a);
3383 assert_eq_m128(r, _mm_setzero_ps());
3384 let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3385 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3386 assert_eq_m128(r, e);
3387 }
3388
3389 #[simd_test(enable = "avx512f,avx512vl")]
3390 unsafe fn test_mm_mask_cvtpd_ps() {
3391 let a = _mm_set_pd(6., -7.5);
3392 let src = _mm_set1_ps(0.);
3393 let r = _mm_mask_cvtpd_ps(src, 0, a);
3394 assert_eq_m128(r, src);
3395 let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3396 let e = _mm_set_ps(0., 0., 6., -7.5);
3397 assert_eq_m128(r, e);
3398 }
3399
3400 #[simd_test(enable = "avx512f,avx512vl")]
3401 unsafe fn test_mm_maskz_cvtpd_ps() {
3402 let a = _mm_set_pd(6., -7.5);
3403 let r = _mm_maskz_cvtpd_ps(0, a);
3404 assert_eq_m128(r, _mm_setzero_ps());
3405 let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3406 let e = _mm_set_ps(0., 0., 6., -7.5);
3407 assert_eq_m128(r, e);
3408 }
3409
3410 #[simd_test(enable = "avx512f")]
3411 unsafe fn test_mm512_cvtpd_epi32() {
3412 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3413 let r = _mm512_cvtpd_epi32(a);
3414 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3415 assert_eq_m256i(r, e);
3416 }
3417
3418 #[simd_test(enable = "avx512f")]
3419 unsafe fn test_mm512_mask_cvtpd_epi32() {
3420 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3421 let src = _mm256_set1_epi32(0);
3422 let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3423 assert_eq_m256i(r, src);
3424 let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3425 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3426 assert_eq_m256i(r, e);
3427 }
3428
3429 #[simd_test(enable = "avx512f")]
3430 unsafe fn test_mm512_maskz_cvtpd_epi32() {
3431 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3432 let r = _mm512_maskz_cvtpd_epi32(0, a);
3433 assert_eq_m256i(r, _mm256_setzero_si256());
3434 let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3435 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3436 assert_eq_m256i(r, e);
3437 }
3438
3439 #[simd_test(enable = "avx512f,avx512vl")]
3440 unsafe fn test_mm256_mask_cvtpd_epi32() {
3441 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3442 let src = _mm_set1_epi32(0);
3443 let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3444 assert_eq_m128i(r, src);
3445 let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3446 let e = _mm_set_epi32(4, -6, 6, -8);
3447 assert_eq_m128i(r, e);
3448 }
3449
3450 #[simd_test(enable = "avx512f,avx512vl")]
3451 unsafe fn test_mm256_maskz_cvtpd_epi32() {
3452 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3453 let r = _mm256_maskz_cvtpd_epi32(0, a);
3454 assert_eq_m128i(r, _mm_setzero_si128());
3455 let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3456 let e = _mm_set_epi32(4, -6, 6, -8);
3457 assert_eq_m128i(r, e);
3458 }
3459
3460 #[simd_test(enable = "avx512f,avx512vl")]
3461 unsafe fn test_mm_mask_cvtpd_epi32() {
3462 let a = _mm_set_pd(6., -7.5);
3463 let src = _mm_set1_epi32(0);
3464 let r = _mm_mask_cvtpd_epi32(src, 0, a);
3465 assert_eq_m128i(r, src);
3466 let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3467 let e = _mm_set_epi32(0, 0, 6, -8);
3468 assert_eq_m128i(r, e);
3469 }
3470
3471 #[simd_test(enable = "avx512f,avx512vl")]
3472 unsafe fn test_mm_maskz_cvtpd_epi32() {
3473 let a = _mm_set_pd(6., -7.5);
3474 let r = _mm_maskz_cvtpd_epi32(0, a);
3475 assert_eq_m128i(r, _mm_setzero_si128());
3476 let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3477 let e = _mm_set_epi32(0, 0, 6, -8);
3478 assert_eq_m128i(r, e);
3479 }
3480
3481 #[simd_test(enable = "avx512f")]
3482 unsafe fn test_mm512_cvtpd_epu32() {
3483 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3484 let r = _mm512_cvtpd_epu32(a);
3485 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3486 assert_eq_m256i(r, e);
3487 }
3488
3489 #[simd_test(enable = "avx512f")]
3490 unsafe fn test_mm512_mask_cvtpd_epu32() {
3491 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3492 let src = _mm256_set1_epi32(0);
3493 let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3494 assert_eq_m256i(r, src);
3495 let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3496 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3497 assert_eq_m256i(r, e);
3498 }
3499
3500 #[simd_test(enable = "avx512f")]
3501 unsafe fn test_mm512_maskz_cvtpd_epu32() {
3502 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3503 let r = _mm512_maskz_cvtpd_epu32(0, a);
3504 assert_eq_m256i(r, _mm256_setzero_si256());
3505 let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3506 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3507 assert_eq_m256i(r, e);
3508 }
3509
3510 #[simd_test(enable = "avx512f,avx512vl")]
3511 unsafe fn test_mm256_cvtpd_epu32() {
3512 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3513 let r = _mm256_cvtpd_epu32(a);
3514 let e = _mm_set_epi32(4, 6, 6, 8);
3515 assert_eq_m128i(r, e);
3516 }
3517
3518 #[simd_test(enable = "avx512f,avx512vl")]
3519 unsafe fn test_mm256_mask_cvtpd_epu32() {
3520 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3521 let src = _mm_set1_epi32(0);
3522 let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3523 assert_eq_m128i(r, src);
3524 let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3525 let e = _mm_set_epi32(4, 6, 6, 8);
3526 assert_eq_m128i(r, e);
3527 }
3528
3529 #[simd_test(enable = "avx512f,avx512vl")]
3530 unsafe fn test_mm256_maskz_cvtpd_epu32() {
3531 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3532 let r = _mm256_maskz_cvtpd_epu32(0, a);
3533 assert_eq_m128i(r, _mm_setzero_si128());
3534 let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3535 let e = _mm_set_epi32(4, 6, 6, 8);
3536 assert_eq_m128i(r, e);
3537 }
3538
3539 #[simd_test(enable = "avx512f,avx512vl")]
3540 unsafe fn test_mm_cvtpd_epu32() {
3541 let a = _mm_set_pd(6., 7.5);
3542 let r = _mm_cvtpd_epu32(a);
3543 let e = _mm_set_epi32(0, 0, 6, 8);
3544 assert_eq_m128i(r, e);
3545 }
3546
3547 #[simd_test(enable = "avx512f,avx512vl")]
3548 unsafe fn test_mm_mask_cvtpd_epu32() {
3549 let a = _mm_set_pd(6., 7.5);
3550 let src = _mm_set1_epi32(0);
3551 let r = _mm_mask_cvtpd_epu32(src, 0, a);
3552 assert_eq_m128i(r, src);
3553 let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3554 let e = _mm_set_epi32(0, 0, 6, 8);
3555 assert_eq_m128i(r, e);
3556 }
3557
3558 #[simd_test(enable = "avx512f,avx512vl")]
3559 unsafe fn test_mm_maskz_cvtpd_epu32() {
3560 let a = _mm_set_pd(6., 7.5);
3561 let r = _mm_maskz_cvtpd_epu32(0, a);
3562 assert_eq_m128i(r, _mm_setzero_si128());
3563 let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3564 let e = _mm_set_epi32(0, 0, 6, 8);
3565 assert_eq_m128i(r, e);
3566 }
3567
3568 #[simd_test(enable = "avx512f")]
3569 unsafe fn test_mm512_cvtpd_pslo() {
3570 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3571 let r = _mm512_cvtpd_pslo(v2);
3572 let e = _mm512_setr_ps(
3573 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3574 );
3575 assert_eq_m512(r, e);
3576 }
3577
3578 #[simd_test(enable = "avx512f")]
3579 unsafe fn test_mm512_mask_cvtpd_pslo() {
3580 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3581 let src = _mm512_set1_ps(0.);
3582 let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3583 assert_eq_m512(r, src);
3584 let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3585 let e = _mm512_setr_ps(
3586 0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3587 );
3588 assert_eq_m512(r, e);
3589 }
3590
3591 #[simd_test(enable = "avx512f")]
3592 unsafe fn test_mm512_cvtepi8_epi64() {
3593 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3594 let r = _mm512_cvtepi8_epi64(a);
3595 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3596 assert_eq_m512i(r, e);
3597 }
3598
3599 #[simd_test(enable = "avx512f")]
3600 unsafe fn test_mm512_mask_cvtepi8_epi64() {
3601 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3602 let src = _mm512_set1_epi64(-1);
3603 let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3604 assert_eq_m512i(r, src);
3605 let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3606 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3607 assert_eq_m512i(r, e);
3608 }
3609
3610 #[simd_test(enable = "avx512f")]
3611 unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3612 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3613 let r = _mm512_maskz_cvtepi8_epi64(0, a);
3614 assert_eq_m512i(r, _mm512_setzero_si512());
3615 let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3616 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3617 assert_eq_m512i(r, e);
3618 }
3619
3620 #[simd_test(enable = "avx512f,avx512vl")]
3621 unsafe fn test_mm256_mask_cvtepi8_epi64() {
3622 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3623 let src = _mm256_set1_epi64x(-1);
3624 let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3625 assert_eq_m256i(r, src);
3626 let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3627 let e = _mm256_set_epi64x(12, 13, 14, 15);
3628 assert_eq_m256i(r, e);
3629 }
3630
3631 #[simd_test(enable = "avx512f,avx512vl")]
3632 unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3633 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3634 let r = _mm256_maskz_cvtepi8_epi64(0, a);
3635 assert_eq_m256i(r, _mm256_setzero_si256());
3636 let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3637 let e = _mm256_set_epi64x(12, 13, 14, 15);
3638 assert_eq_m256i(r, e);
3639 }
3640
3641 #[simd_test(enable = "avx512f,avx512vl")]
3642 unsafe fn test_mm_mask_cvtepi8_epi64() {
3643 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3644 let src = _mm_set1_epi64x(-1);
3645 let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3646 assert_eq_m128i(r, src);
3647 let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3648 let e = _mm_set_epi64x(14, 15);
3649 assert_eq_m128i(r, e);
3650 }
3651
3652 #[simd_test(enable = "avx512f,avx512vl")]
3653 unsafe fn test_mm_maskz_cvtepi8_epi64() {
3654 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3655 let r = _mm_maskz_cvtepi8_epi64(0, a);
3656 assert_eq_m128i(r, _mm_setzero_si128());
3657 let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3658 let e = _mm_set_epi64x(14, 15);
3659 assert_eq_m128i(r, e);
3660 }
3661
3662 #[simd_test(enable = "avx512f")]
3663 unsafe fn test_mm512_cvtepu8_epi64() {
3664 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3665 let r = _mm512_cvtepu8_epi64(a);
3666 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3667 assert_eq_m512i(r, e);
3668 }
3669
3670 #[simd_test(enable = "avx512f")]
3671 unsafe fn test_mm512_mask_cvtepu8_epi64() {
3672 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3673 let src = _mm512_set1_epi64(-1);
3674 let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3675 assert_eq_m512i(r, src);
3676 let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3677 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3678 assert_eq_m512i(r, e);
3679 }
3680
3681 #[simd_test(enable = "avx512f")]
3682 unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3683 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3684 let r = _mm512_maskz_cvtepu8_epi64(0, a);
3685 assert_eq_m512i(r, _mm512_setzero_si512());
3686 let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3687 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3688 assert_eq_m512i(r, e);
3689 }
3690
3691 #[simd_test(enable = "avx512f,avx512vl")]
3692 unsafe fn test_mm256_mask_cvtepu8_epi64() {
3693 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3694 let src = _mm256_set1_epi64x(-1);
3695 let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3696 assert_eq_m256i(r, src);
3697 let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3698 let e = _mm256_set_epi64x(12, 13, 14, 15);
3699 assert_eq_m256i(r, e);
3700 }
3701
3702 #[simd_test(enable = "avx512f,avx512vl")]
3703 unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3704 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3705 let r = _mm256_maskz_cvtepu8_epi64(0, a);
3706 assert_eq_m256i(r, _mm256_setzero_si256());
3707 let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3708 let e = _mm256_set_epi64x(12, 13, 14, 15);
3709 assert_eq_m256i(r, e);
3710 }
3711
3712 #[simd_test(enable = "avx512f,avx512vl")]
3713 unsafe fn test_mm_mask_cvtepu8_epi64() {
3714 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3715 let src = _mm_set1_epi64x(-1);
3716 let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3717 assert_eq_m128i(r, src);
3718 let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3719 let e = _mm_set_epi64x(14, 15);
3720 assert_eq_m128i(r, e);
3721 }
3722
3723 #[simd_test(enable = "avx512f,avx512vl")]
3724 unsafe fn test_mm_maskz_cvtepu8_epi64() {
3725 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3726 let r = _mm_maskz_cvtepu8_epi64(0, a);
3727 assert_eq_m128i(r, _mm_setzero_si128());
3728 let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3729 let e = _mm_set_epi64x(14, 15);
3730 assert_eq_m128i(r, e);
3731 }
3732
3733 #[simd_test(enable = "avx512f")]
3734 unsafe fn test_mm512_cvtepi16_epi64() {
3735 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3736 let r = _mm512_cvtepi16_epi64(a);
3737 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3738 assert_eq_m512i(r, e);
3739 }
3740
3741 #[simd_test(enable = "avx512f")]
3742 unsafe fn test_mm512_mask_cvtepi16_epi64() {
3743 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3744 let src = _mm512_set1_epi64(-1);
3745 let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3746 assert_eq_m512i(r, src);
3747 let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3748 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3749 assert_eq_m512i(r, e);
3750 }
3751
3752 #[simd_test(enable = "avx512f")]
3753 unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3754 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3755 let r = _mm512_maskz_cvtepi16_epi64(0, a);
3756 assert_eq_m512i(r, _mm512_setzero_si512());
3757 let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3758 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3759 assert_eq_m512i(r, e);
3760 }
3761
3762 #[simd_test(enable = "avx512f,avx512vl")]
3763 unsafe fn test_mm256_mask_cvtepi16_epi64() {
3764 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3765 let src = _mm256_set1_epi64x(-1);
3766 let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3767 assert_eq_m256i(r, src);
3768 let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3769 let e = _mm256_set_epi64x(12, 13, 14, 15);
3770 assert_eq_m256i(r, e);
3771 }
3772
3773 #[simd_test(enable = "avx512f,avx512vl")]
3774 unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3775 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3776 let r = _mm256_maskz_cvtepi16_epi64(0, a);
3777 assert_eq_m256i(r, _mm256_setzero_si256());
3778 let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3779 let e = _mm256_set_epi64x(12, 13, 14, 15);
3780 assert_eq_m256i(r, e);
3781 }
3782
3783 #[simd_test(enable = "avx512f,avx512vl")]
3784 unsafe fn test_mm_mask_cvtepi16_epi64() {
3785 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3786 let src = _mm_set1_epi64x(-1);
3787 let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3788 assert_eq_m128i(r, src);
3789 let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3790 let e = _mm_set_epi64x(14, 15);
3791 assert_eq_m128i(r, e);
3792 }
3793
3794 #[simd_test(enable = "avx512f,avx512vl")]
3795 unsafe fn test_mm_maskz_cvtepi16_epi64() {
3796 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3797 let r = _mm_maskz_cvtepi16_epi64(0, a);
3798 assert_eq_m128i(r, _mm_setzero_si128());
3799 let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3800 let e = _mm_set_epi64x(14, 15);
3801 assert_eq_m128i(r, e);
3802 }
3803
3804 #[simd_test(enable = "avx512f")]
3805 unsafe fn test_mm512_cvtepu16_epi64() {
3806 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3807 let r = _mm512_cvtepu16_epi64(a);
3808 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3809 assert_eq_m512i(r, e);
3810 }
3811
3812 #[simd_test(enable = "avx512f")]
3813 unsafe fn test_mm512_mask_cvtepu16_epi64() {
3814 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3815 let src = _mm512_set1_epi64(-1);
3816 let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3817 assert_eq_m512i(r, src);
3818 let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3819 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3820 assert_eq_m512i(r, e);
3821 }
3822
3823 #[simd_test(enable = "avx512f")]
3824 unsafe fn test_mm512_maskz_cvtepu16_epi64() {
3825 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3826 let r = _mm512_maskz_cvtepu16_epi64(0, a);
3827 assert_eq_m512i(r, _mm512_setzero_si512());
3828 let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
3829 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3830 assert_eq_m512i(r, e);
3831 }
3832
3833 #[simd_test(enable = "avx512f,avx512vl")]
3834 unsafe fn test_mm256_mask_cvtepu16_epi64() {
3835 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3836 let src = _mm256_set1_epi64x(-1);
3837 let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
3838 assert_eq_m256i(r, src);
3839 let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
3840 let e = _mm256_set_epi64x(12, 13, 14, 15);
3841 assert_eq_m256i(r, e);
3842 }
3843
3844 #[simd_test(enable = "avx512f,avx512vl")]
3845 unsafe fn test_mm256_maskz_cvtepu16_epi64() {
3846 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3847 let r = _mm256_maskz_cvtepu16_epi64(0, a);
3848 assert_eq_m256i(r, _mm256_setzero_si256());
3849 let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
3850 let e = _mm256_set_epi64x(12, 13, 14, 15);
3851 assert_eq_m256i(r, e);
3852 }
3853
3854 #[simd_test(enable = "avx512f,avx512vl")]
3855 unsafe fn test_mm_mask_cvtepu16_epi64() {
3856 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3857 let src = _mm_set1_epi64x(-1);
3858 let r = _mm_mask_cvtepu16_epi64(src, 0, a);
3859 assert_eq_m128i(r, src);
3860 let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
3861 let e = _mm_set_epi64x(14, 15);
3862 assert_eq_m128i(r, e);
3863 }
3864
3865 #[simd_test(enable = "avx512f,avx512vl")]
3866 unsafe fn test_mm_maskz_cvtepu16_epi64() {
3867 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3868 let r = _mm_maskz_cvtepu16_epi64(0, a);
3869 assert_eq_m128i(r, _mm_setzero_si128());
3870 let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
3871 let e = _mm_set_epi64x(14, 15);
3872 assert_eq_m128i(r, e);
3873 }
3874
3875 #[simd_test(enable = "avx512f")]
3876 unsafe fn test_mm512_cvtepi32_epi64() {
3877 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3878 let r = _mm512_cvtepi32_epi64(a);
3879 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3880 assert_eq_m512i(r, e);
3881 }
3882
3883 #[simd_test(enable = "avx512f")]
3884 unsafe fn test_mm512_mask_cvtepi32_epi64() {
3885 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3886 let src = _mm512_set1_epi64(-1);
3887 let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
3888 assert_eq_m512i(r, src);
3889 let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
3890 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3891 assert_eq_m512i(r, e);
3892 }
3893
3894 #[simd_test(enable = "avx512f")]
3895 unsafe fn test_mm512_maskz_cvtepi32_epi64() {
3896 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3897 let r = _mm512_maskz_cvtepi32_epi64(0, a);
3898 assert_eq_m512i(r, _mm512_setzero_si512());
3899 let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
3900 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3901 assert_eq_m512i(r, e);
3902 }
3903
3904 #[simd_test(enable = "avx512f,avx512vl")]
3905 unsafe fn test_mm256_mask_cvtepi32_epi64() {
3906 let a = _mm_set_epi32(8, 9, 10, 11);
3907 let src = _mm256_set1_epi64x(-1);
3908 let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
3909 assert_eq_m256i(r, src);
3910 let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
3911 let e = _mm256_set_epi64x(8, 9, 10, 11);
3912 assert_eq_m256i(r, e);
3913 }
3914
3915 #[simd_test(enable = "avx512f,avx512vl")]
3916 unsafe fn test_mm256_maskz_cvtepi32_epi64() {
3917 let a = _mm_set_epi32(8, 9, 10, 11);
3918 let r = _mm256_maskz_cvtepi32_epi64(0, a);
3919 assert_eq_m256i(r, _mm256_setzero_si256());
3920 let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
3921 let e = _mm256_set_epi64x(8, 9, 10, 11);
3922 assert_eq_m256i(r, e);
3923 }
3924
3925 #[simd_test(enable = "avx512f,avx512vl")]
3926 unsafe fn test_mm_mask_cvtepi32_epi64() {
3927 let a = _mm_set_epi32(8, 9, 10, 11);
3928 let src = _mm_set1_epi64x(0);
3929 let r = _mm_mask_cvtepi32_epi64(src, 0, a);
3930 assert_eq_m128i(r, src);
3931 let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
3932 let e = _mm_set_epi64x(10, 11);
3933 assert_eq_m128i(r, e);
3934 }
3935
3936 #[simd_test(enable = "avx512f,avx512vl")]
3937 unsafe fn test_mm_maskz_cvtepi32_epi64() {
3938 let a = _mm_set_epi32(8, 9, 10, 11);
3939 let r = _mm_maskz_cvtepi32_epi64(0, a);
3940 assert_eq_m128i(r, _mm_setzero_si128());
3941 let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
3942 let e = _mm_set_epi64x(10, 11);
3943 assert_eq_m128i(r, e);
3944 }
3945
3946 #[simd_test(enable = "avx512f")]
3947 unsafe fn test_mm512_cvtepu32_epi64() {
3948 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3949 let r = _mm512_cvtepu32_epi64(a);
3950 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3951 assert_eq_m512i(r, e);
3952 }
3953
3954 #[simd_test(enable = "avx512f")]
3955 unsafe fn test_mm512_mask_cvtepu32_epi64() {
3956 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3957 let src = _mm512_set1_epi64(-1);
3958 let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
3959 assert_eq_m512i(r, src);
3960 let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
3961 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3962 assert_eq_m512i(r, e);
3963 }
3964
3965 #[simd_test(enable = "avx512f")]
3966 unsafe fn test_mm512_maskz_cvtepu32_epi64() {
3967 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
3968 let r = _mm512_maskz_cvtepu32_epi64(0, a);
3969 assert_eq_m512i(r, _mm512_setzero_si512());
3970 let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
3971 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3972 assert_eq_m512i(r, e);
3973 }
3974
3975 #[simd_test(enable = "avx512f,avx512vl")]
3976 unsafe fn test_mm256_mask_cvtepu32_epi64() {
3977 let a = _mm_set_epi32(12, 13, 14, 15);
3978 let src = _mm256_set1_epi64x(-1);
3979 let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
3980 assert_eq_m256i(r, src);
3981 let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
3982 let e = _mm256_set_epi64x(12, 13, 14, 15);
3983 assert_eq_m256i(r, e);
3984 }
3985
3986 #[simd_test(enable = "avx512f,avx512vl")]
3987 unsafe fn test_mm256_maskz_cvtepu32_epi64() {
3988 let a = _mm_set_epi32(12, 13, 14, 15);
3989 let r = _mm256_maskz_cvtepu32_epi64(0, a);
3990 assert_eq_m256i(r, _mm256_setzero_si256());
3991 let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
3992 let e = _mm256_set_epi64x(12, 13, 14, 15);
3993 assert_eq_m256i(r, e);
3994 }
3995
3996 #[simd_test(enable = "avx512f,avx512vl")]
3997 unsafe fn test_mm_mask_cvtepu32_epi64() {
3998 let a = _mm_set_epi32(12, 13, 14, 15);
3999 let src = _mm_set1_epi64x(-1);
4000 let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4001 assert_eq_m128i(r, src);
4002 let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4003 let e = _mm_set_epi64x(14, 15);
4004 assert_eq_m128i(r, e);
4005 }
4006
4007 #[simd_test(enable = "avx512f,avx512vl")]
4008 unsafe fn test_mm_maskz_cvtepu32_epi64() {
4009 let a = _mm_set_epi32(12, 13, 14, 15);
4010 let r = _mm_maskz_cvtepu32_epi64(0, a);
4011 assert_eq_m128i(r, _mm_setzero_si128());
4012 let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4013 let e = _mm_set_epi64x(14, 15);
4014 assert_eq_m128i(r, e);
4015 }
4016
4017 #[simd_test(enable = "avx512f")]
4018 unsafe fn test_mm512_cvtepi32_pd() {
4019 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4020 let r = _mm512_cvtepi32_pd(a);
4021 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4022 assert_eq_m512d(r, e);
4023 }
4024
4025 #[simd_test(enable = "avx512f")]
4026 unsafe fn test_mm512_mask_cvtepi32_pd() {
4027 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4028 let src = _mm512_set1_pd(-1.);
4029 let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4030 assert_eq_m512d(r, src);
4031 let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4032 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4033 assert_eq_m512d(r, e);
4034 }
4035
4036 #[simd_test(enable = "avx512f")]
4037 unsafe fn test_mm512_maskz_cvtepi32_pd() {
4038 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4039 let r = _mm512_maskz_cvtepi32_pd(0, a);
4040 assert_eq_m512d(r, _mm512_setzero_pd());
4041 let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4042 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4043 assert_eq_m512d(r, e);
4044 }
4045
4046 #[simd_test(enable = "avx512f,avx512vl")]
4047 unsafe fn test_mm256_mask_cvtepi32_pd() {
4048 let a = _mm_set_epi32(12, 13, 14, 15);
4049 let src = _mm256_set1_pd(-1.);
4050 let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4051 assert_eq_m256d(r, src);
4052 let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4053 let e = _mm256_set_pd(12., 13., 14., 15.);
4054 assert_eq_m256d(r, e);
4055 }
4056
4057 #[simd_test(enable = "avx512f,avx512vl")]
4058 unsafe fn test_mm256_maskz_cvtepi32_pd() {
4059 let a = _mm_set_epi32(12, 13, 14, 15);
4060 let r = _mm256_maskz_cvtepi32_pd(0, a);
4061 assert_eq_m256d(r, _mm256_setzero_pd());
4062 let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4063 let e = _mm256_set_pd(12., 13., 14., 15.);
4064 assert_eq_m256d(r, e);
4065 }
4066
4067 #[simd_test(enable = "avx512f,avx512vl")]
4068 unsafe fn test_mm_mask_cvtepi32_pd() {
4069 let a = _mm_set_epi32(12, 13, 14, 15);
4070 let src = _mm_set1_pd(-1.);
4071 let r = _mm_mask_cvtepi32_pd(src, 0, a);
4072 assert_eq_m128d(r, src);
4073 let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4074 let e = _mm_set_pd(14., 15.);
4075 assert_eq_m128d(r, e);
4076 }
4077
4078 #[simd_test(enable = "avx512f,avx512vl")]
4079 unsafe fn test_mm_maskz_cvtepi32_pd() {
4080 let a = _mm_set_epi32(12, 13, 14, 15);
4081 let r = _mm_maskz_cvtepi32_pd(0, a);
4082 assert_eq_m128d(r, _mm_setzero_pd());
4083 let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4084 let e = _mm_set_pd(14., 15.);
4085 assert_eq_m128d(r, e);
4086 }
4087
4088 #[simd_test(enable = "avx512f")]
4089 unsafe fn test_mm512_cvtepu32_pd() {
4090 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4091 let r = _mm512_cvtepu32_pd(a);
4092 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4093 assert_eq_m512d(r, e);
4094 }
4095
4096 #[simd_test(enable = "avx512f")]
4097 unsafe fn test_mm512_mask_cvtepu32_pd() {
4098 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4099 let src = _mm512_set1_pd(-1.);
4100 let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4101 assert_eq_m512d(r, src);
4102 let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4103 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4104 assert_eq_m512d(r, e);
4105 }
4106
4107 #[simd_test(enable = "avx512f")]
4108 unsafe fn test_mm512_maskz_cvtepu32_pd() {
4109 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4110 let r = _mm512_maskz_cvtepu32_pd(0, a);
4111 assert_eq_m512d(r, _mm512_setzero_pd());
4112 let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4113 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4114 assert_eq_m512d(r, e);
4115 }
4116
4117 #[simd_test(enable = "avx512f,avx512vl")]
4118 unsafe fn test_mm256_cvtepu32_pd() {
4119 let a = _mm_set_epi32(12, 13, 14, 15);
4120 let r = _mm256_cvtepu32_pd(a);
4121 let e = _mm256_set_pd(12., 13., 14., 15.);
4122 assert_eq_m256d(r, e);
4123 }
4124
4125 #[simd_test(enable = "avx512f,avx512vl")]
4126 unsafe fn test_mm256_mask_cvtepu32_pd() {
4127 let a = _mm_set_epi32(12, 13, 14, 15);
4128 let src = _mm256_set1_pd(-1.);
4129 let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4130 assert_eq_m256d(r, src);
4131 let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4132 let e = _mm256_set_pd(12., 13., 14., 15.);
4133 assert_eq_m256d(r, e);
4134 }
4135
4136 #[simd_test(enable = "avx512f,avx512vl")]
4137 unsafe fn test_mm256_maskz_cvtepu32_pd() {
4138 let a = _mm_set_epi32(12, 13, 14, 15);
4139 let r = _mm256_maskz_cvtepu32_pd(0, a);
4140 assert_eq_m256d(r, _mm256_setzero_pd());
4141 let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4142 let e = _mm256_set_pd(12., 13., 14., 15.);
4143 assert_eq_m256d(r, e);
4144 }
4145
4146 #[simd_test(enable = "avx512f,avx512vl")]
4147 unsafe fn test_mm_cvtepu32_pd() {
4148 let a = _mm_set_epi32(12, 13, 14, 15);
4149 let r = _mm_cvtepu32_pd(a);
4150 let e = _mm_set_pd(14., 15.);
4151 assert_eq_m128d(r, e);
4152 }
4153
4154 #[simd_test(enable = "avx512f,avx512vl")]
4155 unsafe fn test_mm_mask_cvtepu32_pd() {
4156 let a = _mm_set_epi32(12, 13, 14, 15);
4157 let src = _mm_set1_pd(-1.);
4158 let r = _mm_mask_cvtepu32_pd(src, 0, a);
4159 assert_eq_m128d(r, src);
4160 let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4161 let e = _mm_set_pd(14., 15.);
4162 assert_eq_m128d(r, e);
4163 }
4164
4165 #[simd_test(enable = "avx512f,avx512vl")]
4166 unsafe fn test_mm_maskz_cvtepu32_pd() {
4167 let a = _mm_set_epi32(12, 13, 14, 15);
4168 let r = _mm_maskz_cvtepu32_pd(0, a);
4169 assert_eq_m128d(r, _mm_setzero_pd());
4170 let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4171 let e = _mm_set_pd(14., 15.);
4172 assert_eq_m128d(r, e);
4173 }
4174
4175 #[simd_test(enable = "avx512f")]
4176 unsafe fn test_mm512_cvtepi32lo_pd() {
4177 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4178 let r = _mm512_cvtepi32lo_pd(a);
4179 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4180 assert_eq_m512d(r, e);
4181 }
4182
4183 #[simd_test(enable = "avx512f")]
4184 unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4185 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4186 let src = _mm512_set1_pd(-1.);
4187 let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4188 assert_eq_m512d(r, src);
4189 let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4190 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4191 assert_eq_m512d(r, e);
4192 }
4193
4194 #[simd_test(enable = "avx512f")]
4195 unsafe fn test_mm512_cvtepu32lo_pd() {
4196 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4197 let r = _mm512_cvtepu32lo_pd(a);
4198 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4199 assert_eq_m512d(r, e);
4200 }
4201
4202 #[simd_test(enable = "avx512f")]
4203 unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4204 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4205 let src = _mm512_set1_pd(-1.);
4206 let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4207 assert_eq_m512d(r, src);
4208 let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4209 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4210 assert_eq_m512d(r, e);
4211 }
4212
4213 #[simd_test(enable = "avx512f")]
4214 unsafe fn test_mm512_cvtepi64_epi32() {
4215 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4216 let r = _mm512_cvtepi64_epi32(a);
4217 let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4218 assert_eq_m256i(r, e);
4219 }
4220
4221 #[simd_test(enable = "avx512f")]
4222 unsafe fn test_mm512_mask_cvtepi64_epi32() {
4223 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4224 let src = _mm256_set1_epi32(-1);
4225 let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4226 assert_eq_m256i(r, src);
4227 let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4228 let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4229 assert_eq_m256i(r, e);
4230 }
4231
4232 #[simd_test(enable = "avx512f")]
4233 unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4234 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4235 let r = _mm512_maskz_cvtepi64_epi32(0, a);
4236 assert_eq_m256i(r, _mm256_setzero_si256());
4237 let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4238 let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4239 assert_eq_m256i(r, e);
4240 }
4241
4242 #[simd_test(enable = "avx512f,avx512vl")]
4243 unsafe fn test_mm256_cvtepi64_epi32() {
4244 let a = _mm256_set_epi64x(1, 2, 3, 4);
4245 let r = _mm256_cvtepi64_epi32(a);
4246 let e = _mm_set_epi32(1, 2, 3, 4);
4247 assert_eq_m128i(r, e);
4248 }
4249
4250 #[simd_test(enable = "avx512f,avx512vl")]
4251 unsafe fn test_mm256_mask_cvtepi64_epi32() {
4252 let a = _mm256_set_epi64x(1, 2, 3, 4);
4253 let src = _mm_set1_epi32(0);
4254 let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4255 assert_eq_m128i(r, src);
4256 let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4257 let e = _mm_set_epi32(1, 2, 3, 4);
4258 assert_eq_m128i(r, e);
4259 }
4260
4261 #[simd_test(enable = "avx512f,avx512vl")]
4262 unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4263 let a = _mm256_set_epi64x(1, 2, 3, 4);
4264 let r = _mm256_maskz_cvtepi64_epi32(0, a);
4265 assert_eq_m128i(r, _mm_setzero_si128());
4266 let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4267 let e = _mm_set_epi32(1, 2, 3, 4);
4268 assert_eq_m128i(r, e);
4269 }
4270
4271 #[simd_test(enable = "avx512f,avx512vl")]
4272 unsafe fn test_mm_cvtepi64_epi32() {
4273 let a = _mm_set_epi64x(3, 4);
4274 let r = _mm_cvtepi64_epi32(a);
4275 let e = _mm_set_epi32(0, 0, 3, 4);
4276 assert_eq_m128i(r, e);
4277 }
4278
4279 #[simd_test(enable = "avx512f,avx512vl")]
4280 unsafe fn test_mm_mask_cvtepi64_epi32() {
4281 let a = _mm_set_epi64x(3, 4);
4282 let src = _mm_set1_epi32(0);
4283 let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4284 assert_eq_m128i(r, src);
4285 let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4286 let e = _mm_set_epi32(0, 0, 3, 4);
4287 assert_eq_m128i(r, e);
4288 }
4289
4290 #[simd_test(enable = "avx512f,avx512vl")]
4291 unsafe fn test_mm_maskz_cvtepi64_epi32() {
4292 let a = _mm_set_epi64x(3, 4);
4293 let r = _mm_maskz_cvtepi64_epi32(0, a);
4294 assert_eq_m128i(r, _mm_setzero_si128());
4295 let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4296 let e = _mm_set_epi32(0, 0, 3, 4);
4297 assert_eq_m128i(r, e);
4298 }
4299
4300 #[simd_test(enable = "avx512f")]
4301 unsafe fn test_mm512_cvtepi64_epi16() {
4302 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4303 let r = _mm512_cvtepi64_epi16(a);
4304 let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4305 assert_eq_m128i(r, e);
4306 }
4307
4308 #[simd_test(enable = "avx512f")]
4309 unsafe fn test_mm512_mask_cvtepi64_epi16() {
4310 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4311 let src = _mm_set1_epi16(-1);
4312 let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4313 assert_eq_m128i(r, src);
4314 let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4315 let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4316 assert_eq_m128i(r, e);
4317 }
4318
4319 #[simd_test(enable = "avx512f")]
4320 unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4321 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4322 let r = _mm512_maskz_cvtepi64_epi16(0, a);
4323 assert_eq_m128i(r, _mm_setzero_si128());
4324 let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4325 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4326 assert_eq_m128i(r, e);
4327 }
4328
4329 #[simd_test(enable = "avx512f,avx512vl")]
4330 unsafe fn test_mm256_cvtepi64_epi16() {
4331 let a = _mm256_set_epi64x(12, 13, 14, 15);
4332 let r = _mm256_cvtepi64_epi16(a);
4333 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4334 assert_eq_m128i(r, e);
4335 }
4336
4337 #[simd_test(enable = "avx512f,avx512vl")]
4338 unsafe fn test_mm256_mask_cvtepi64_epi16() {
4339 let a = _mm256_set_epi64x(12, 13, 14, 15);
4340 let src = _mm_set1_epi16(0);
4341 let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4342 assert_eq_m128i(r, src);
4343 let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4344 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4345 assert_eq_m128i(r, e);
4346 }
4347
4348 #[simd_test(enable = "avx512f,avx512vl")]
4349 unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4350 let a = _mm256_set_epi64x(12, 13, 14, 15);
4351 let r = _mm256_maskz_cvtepi64_epi16(0, a);
4352 assert_eq_m128i(r, _mm_setzero_si128());
4353 let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4354 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4355 assert_eq_m128i(r, e);
4356 }
4357
4358 #[simd_test(enable = "avx512f,avx512vl")]
4359 unsafe fn test_mm_cvtepi64_epi16() {
4360 let a = _mm_set_epi64x(14, 15);
4361 let r = _mm_cvtepi64_epi16(a);
4362 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4363 assert_eq_m128i(r, e);
4364 }
4365
4366 #[simd_test(enable = "avx512f,avx512vl")]
4367 unsafe fn test_mm_mask_cvtepi64_epi16() {
4368 let a = _mm_set_epi64x(14, 15);
4369 let src = _mm_set1_epi16(0);
4370 let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4371 assert_eq_m128i(r, src);
4372 let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4373 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4374 assert_eq_m128i(r, e);
4375 }
4376
4377 #[simd_test(enable = "avx512f,avx512vl")]
4378 unsafe fn test_mm_maskz_cvtepi64_epi16() {
4379 let a = _mm_set_epi64x(14, 15);
4380 let r = _mm_maskz_cvtepi64_epi16(0, a);
4381 assert_eq_m128i(r, _mm_setzero_si128());
4382 let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4383 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4384 assert_eq_m128i(r, e);
4385 }
4386
4387 #[simd_test(enable = "avx512f")]
4388 unsafe fn test_mm512_cvtepi64_epi8() {
4389 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4390 let r = _mm512_cvtepi64_epi8(a);
4391 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4392 assert_eq_m128i(r, e);
4393 }
4394
4395 #[simd_test(enable = "avx512f")]
4396 unsafe fn test_mm512_mask_cvtepi64_epi8() {
4397 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4398 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4399 let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4400 assert_eq_m128i(r, src);
4401 let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4402 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4403 assert_eq_m128i(r, e);
4404 }
4405
4406 #[simd_test(enable = "avx512f")]
4407 unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4408 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4409 let r = _mm512_maskz_cvtepi64_epi8(0, a);
4410 assert_eq_m128i(r, _mm_setzero_si128());
4411 let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4412 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4413 assert_eq_m128i(r, e);
4414 }
4415
4416 #[simd_test(enable = "avx512f,avx512vl")]
4417 unsafe fn test_mm256_cvtepi64_epi8() {
4418 let a = _mm256_set_epi64x(12, 13, 14, 15);
4419 let r = _mm256_cvtepi64_epi8(a);
4420 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4421 assert_eq_m128i(r, e);
4422 }
4423
4424 #[simd_test(enable = "avx512f,avx512vl")]
4425 unsafe fn test_mm256_mask_cvtepi64_epi8() {
4426 let a = _mm256_set_epi64x(12, 13, 14, 15);
4427 let src = _mm_set1_epi8(0);
4428 let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4429 assert_eq_m128i(r, src);
4430 let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4431 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4432 assert_eq_m128i(r, e);
4433 }
4434
4435 #[simd_test(enable = "avx512f,avx512vl")]
4436 unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4437 let a = _mm256_set_epi64x(12, 13, 14, 15);
4438 let r = _mm256_maskz_cvtepi64_epi8(0, a);
4439 assert_eq_m128i(r, _mm_setzero_si128());
4440 let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4441 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4442 assert_eq_m128i(r, e);
4443 }
4444
4445 #[simd_test(enable = "avx512f,avx512vl")]
4446 unsafe fn test_mm_cvtepi64_epi8() {
4447 let a = _mm_set_epi64x(14, 15);
4448 let r = _mm_cvtepi64_epi8(a);
4449 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4450 assert_eq_m128i(r, e);
4451 }
4452
4453 #[simd_test(enable = "avx512f,avx512vl")]
4454 unsafe fn test_mm_mask_cvtepi64_epi8() {
4455 let a = _mm_set_epi64x(14, 15);
4456 let src = _mm_set1_epi8(0);
4457 let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4458 assert_eq_m128i(r, src);
4459 let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4460 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4461 assert_eq_m128i(r, e);
4462 }
4463
4464 #[simd_test(enable = "avx512f,avx512vl")]
4465 unsafe fn test_mm_maskz_cvtepi64_epi8() {
4466 let a = _mm_set_epi64x(14, 15);
4467 let r = _mm_maskz_cvtepi64_epi8(0, a);
4468 assert_eq_m128i(r, _mm_setzero_si128());
4469 let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4470 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4471 assert_eq_m128i(r, e);
4472 }
4473
4474 #[simd_test(enable = "avx512f")]
4475 unsafe fn test_mm512_cvtsepi64_epi32() {
4476 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4477 let r = _mm512_cvtsepi64_epi32(a);
4478 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4479 assert_eq_m256i(r, e);
4480 }
4481
4482 #[simd_test(enable = "avx512f")]
4483 unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4484 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4485 let src = _mm256_set1_epi32(-1);
4486 let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4487 assert_eq_m256i(r, src);
4488 let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4489 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4490 assert_eq_m256i(r, e);
4491 }
4492
4493 #[simd_test(enable = "avx512f")]
4494 unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4495 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4496 let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4497 assert_eq_m256i(r, _mm256_setzero_si256());
4498 let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4499 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4500 assert_eq_m256i(r, e);
4501 }
4502
4503 #[simd_test(enable = "avx512f,avx512vl")]
4504 unsafe fn test_mm256_cvtsepi64_epi32() {
4505 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4506 let r = _mm256_cvtsepi64_epi32(a);
4507 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4508 assert_eq_m128i(r, e);
4509 }
4510
4511 #[simd_test(enable = "avx512f,avx512vl")]
4512 unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4513 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4514 let src = _mm_set1_epi32(-1);
4515 let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4516 assert_eq_m128i(r, src);
4517 let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4518 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4519 assert_eq_m128i(r, e);
4520 }
4521
4522 #[simd_test(enable = "avx512f,avx512vl")]
4523 unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4524 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4525 let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4526 assert_eq_m128i(r, _mm_setzero_si128());
4527 let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4528 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4529 assert_eq_m128i(r, e);
4530 }
4531
4532 #[simd_test(enable = "avx512f,avx512vl")]
4533 unsafe fn test_mm_cvtsepi64_epi32() {
4534 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4535 let r = _mm_cvtsepi64_epi32(a);
4536 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4537 assert_eq_m128i(r, e);
4538 }
4539
4540 #[simd_test(enable = "avx512f,avx512vl")]
4541 unsafe fn test_mm_mask_cvtsepi64_epi32() {
4542 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4543 let src = _mm_set1_epi32(0);
4544 let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4545 assert_eq_m128i(r, src);
4546 let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4547 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4548 assert_eq_m128i(r, e);
4549 }
4550
4551 #[simd_test(enable = "avx512f,avx512vl")]
4552 unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4553 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4554 let r = _mm_maskz_cvtsepi64_epi32(0, a);
4555 assert_eq_m128i(r, _mm_setzero_si128());
4556 let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4557 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4558 assert_eq_m128i(r, e);
4559 }
4560
4561 #[simd_test(enable = "avx512f")]
4562 unsafe fn test_mm512_cvtsepi64_epi16() {
4563 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4564 let r = _mm512_cvtsepi64_epi16(a);
4565 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4566 assert_eq_m128i(r, e);
4567 }
4568
4569 #[simd_test(enable = "avx512f")]
4570 unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4571 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4572 let src = _mm_set1_epi16(-1);
4573 let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4574 assert_eq_m128i(r, src);
4575 let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4576 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4577 assert_eq_m128i(r, e);
4578 }
4579
4580 #[simd_test(enable = "avx512f")]
4581 unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4582 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4583 let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4584 assert_eq_m128i(r, _mm_setzero_si128());
4585 let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4586 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4587 assert_eq_m128i(r, e);
4588 }
4589
4590 #[simd_test(enable = "avx512f,avx512vl")]
4591 unsafe fn test_mm256_cvtsepi64_epi16() {
4592 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4593 let r = _mm256_cvtsepi64_epi16(a);
4594 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4595 assert_eq_m128i(r, e);
4596 }
4597
4598 #[simd_test(enable = "avx512f,avx512vl")]
4599 unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4600 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4601 let src = _mm_set1_epi16(0);
4602 let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4603 assert_eq_m128i(r, src);
4604 let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4605 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4606 assert_eq_m128i(r, e);
4607 }
4608
4609 #[simd_test(enable = "avx512f,avx512vl")]
4610 unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4611 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4612 let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4613 assert_eq_m128i(r, _mm_setzero_si128());
4614 let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4615 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4616 assert_eq_m128i(r, e);
4617 }
4618
4619 #[simd_test(enable = "avx512f,avx512vl")]
4620 unsafe fn test_mm_cvtsepi64_epi16() {
4621 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4622 let r = _mm_cvtsepi64_epi16(a);
4623 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4624 assert_eq_m128i(r, e);
4625 }
4626
4627 #[simd_test(enable = "avx512f,avx512vl")]
4628 unsafe fn test_mm_mask_cvtsepi64_epi16() {
4629 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4630 let src = _mm_set1_epi16(0);
4631 let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4632 assert_eq_m128i(r, src);
4633 let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4634 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4635 assert_eq_m128i(r, e);
4636 }
4637
4638 #[simd_test(enable = "avx512f,avx512vl")]
4639 unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4640 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4641 let r = _mm_maskz_cvtsepi64_epi16(0, a);
4642 assert_eq_m128i(r, _mm_setzero_si128());
4643 let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4644 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4645 assert_eq_m128i(r, e);
4646 }
4647
4648 #[simd_test(enable = "avx512f")]
4649 unsafe fn test_mm512_cvtsepi64_epi8() {
4650 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4651 let r = _mm512_cvtsepi64_epi8(a);
4652 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4653 assert_eq_m128i(r, e);
4654 }
4655
4656 #[simd_test(enable = "avx512f")]
4657 unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4658 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4659 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4660 let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4661 assert_eq_m128i(r, src);
4662 let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4663 #[rustfmt::skip]
4664 let e = _mm_set_epi8(
4665 0, 0, 0, 0,
4666 0, 0, 0, 0,
4667 -1, -1, -1, -1,
4668 4, 5, i8::MIN, i8::MAX,
4669 );
4670 assert_eq_m128i(r, e);
4671 }
4672
4673 #[simd_test(enable = "avx512f")]
4674 unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4675 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4676 let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4677 assert_eq_m128i(r, _mm_setzero_si128());
4678 let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4679 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4680 assert_eq_m128i(r, e);
4681 }
4682
4683 #[simd_test(enable = "avx512f,avx512vl")]
4684 unsafe fn test_mm256_cvtsepi64_epi8() {
4685 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4686 let r = _mm256_cvtsepi64_epi8(a);
4687 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4688 assert_eq_m128i(r, e);
4689 }
4690
4691 #[simd_test(enable = "avx512f,avx512vl")]
4692 unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4693 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4694 let src = _mm_set1_epi8(0);
4695 let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4696 assert_eq_m128i(r, src);
4697 let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4698 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4699 assert_eq_m128i(r, e);
4700 }
4701
4702 #[simd_test(enable = "avx512f,avx512vl")]
4703 unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4704 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4705 let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4706 assert_eq_m128i(r, _mm_setzero_si128());
4707 let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4708 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4709 assert_eq_m128i(r, e);
4710 }
4711
4712 #[simd_test(enable = "avx512f,avx512vl")]
4713 unsafe fn test_mm_cvtsepi64_epi8() {
4714 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4715 let r = _mm_cvtsepi64_epi8(a);
4716 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4717 assert_eq_m128i(r, e);
4718 }
4719
4720 #[simd_test(enable = "avx512f,avx512vl")]
4721 unsafe fn test_mm_mask_cvtsepi64_epi8() {
4722 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4723 let src = _mm_set1_epi8(0);
4724 let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4725 assert_eq_m128i(r, src);
4726 let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4727 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4728 assert_eq_m128i(r, e);
4729 }
4730
4731 #[simd_test(enable = "avx512f,avx512vl")]
4732 unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4733 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4734 let r = _mm_maskz_cvtsepi64_epi8(0, a);
4735 assert_eq_m128i(r, _mm_setzero_si128());
4736 let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4737 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4738 assert_eq_m128i(r, e);
4739 }
4740
4741 #[simd_test(enable = "avx512f")]
4742 unsafe fn test_mm512_cvtusepi64_epi32() {
4743 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4744 let r = _mm512_cvtusepi64_epi32(a);
4745 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4746 assert_eq_m256i(r, e);
4747 }
4748
4749 #[simd_test(enable = "avx512f")]
4750 unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4751 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4752 let src = _mm256_set1_epi32(-1);
4753 let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4754 assert_eq_m256i(r, src);
4755 let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4756 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4757 assert_eq_m256i(r, e);
4758 }
4759
4760 #[simd_test(enable = "avx512f")]
4761 unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4762 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4763 let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4764 assert_eq_m256i(r, _mm256_setzero_si256());
4765 let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4766 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4767 assert_eq_m256i(r, e);
4768 }
4769
4770 #[simd_test(enable = "avx512f,avx512vl")]
4771 unsafe fn test_mm256_cvtusepi64_epi32() {
4772 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4773 let r = _mm256_cvtusepi64_epi32(a);
4774 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4775 assert_eq_m128i(r, e);
4776 }
4777
4778 #[simd_test(enable = "avx512f,avx512vl")]
4779 unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4780 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4781 let src = _mm_set1_epi32(0);
4782 let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4783 assert_eq_m128i(r, src);
4784 let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4785 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4786 assert_eq_m128i(r, e);
4787 }
4788
4789 #[simd_test(enable = "avx512f,avx512vl")]
4790 unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4791 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4792 let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4793 assert_eq_m128i(r, _mm_setzero_si128());
4794 let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4795 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4796 assert_eq_m128i(r, e);
4797 }
4798
4799 #[simd_test(enable = "avx512f,avx512vl")]
4800 unsafe fn test_mm_cvtusepi64_epi32() {
4801 let a = _mm_set_epi64x(6, i64::MAX);
4802 let r = _mm_cvtusepi64_epi32(a);
4803 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4804 assert_eq_m128i(r, e);
4805 }
4806
4807 #[simd_test(enable = "avx512f,avx512vl")]
4808 unsafe fn test_mm_mask_cvtusepi64_epi32() {
4809 let a = _mm_set_epi64x(6, i64::MAX);
4810 let src = _mm_set1_epi32(0);
4811 let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4812 assert_eq_m128i(r, src);
4813 let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4814 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4815 assert_eq_m128i(r, e);
4816 }
4817
4818 #[simd_test(enable = "avx512f,avx512vl")]
4819 unsafe fn test_mm_maskz_cvtusepi64_epi32() {
4820 let a = _mm_set_epi64x(6, i64::MAX);
4821 let r = _mm_maskz_cvtusepi64_epi32(0, a);
4822 assert_eq_m128i(r, _mm_setzero_si128());
4823 let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
4824 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4825 assert_eq_m128i(r, e);
4826 }
4827
4828 #[simd_test(enable = "avx512f")]
4829 unsafe fn test_mm512_cvtusepi64_epi16() {
4830 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4831 let r = _mm512_cvtusepi64_epi16(a);
4832 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
4833 assert_eq_m128i(r, e);
4834 }
4835
4836 #[simd_test(enable = "avx512f")]
4837 unsafe fn test_mm512_mask_cvtusepi64_epi16() {
4838 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4839 let src = _mm_set1_epi16(-1);
4840 let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
4841 assert_eq_m128i(r, src);
4842 let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
4843 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
4844 assert_eq_m128i(r, e);
4845 }
4846
4847 #[simd_test(enable = "avx512f")]
4848 unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
4849 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4850 let r = _mm512_maskz_cvtusepi64_epi16(0, a);
4851 assert_eq_m128i(r, _mm_setzero_si128());
4852 let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
4853 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
4854 assert_eq_m128i(r, e);
4855 }
4856
4857 #[simd_test(enable = "avx512f,avx512vl")]
4858 unsafe fn test_mm256_cvtusepi64_epi16() {
4859 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4860 let r = _mm256_cvtusepi64_epi16(a);
4861 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4862 assert_eq_m128i(r, e);
4863 }
4864
4865 #[simd_test(enable = "avx512f,avx512vl")]
4866 unsafe fn test_mm256_mask_cvtusepi64_epi16() {
4867 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4868 let src = _mm_set1_epi16(0);
4869 let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
4870 assert_eq_m128i(r, src);
4871 let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
4872 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4873 assert_eq_m128i(r, e);
4874 }
4875
4876 #[simd_test(enable = "avx512f,avx512vl")]
4877 unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
4878 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4879 let r = _mm256_maskz_cvtusepi64_epi16(0, a);
4880 assert_eq_m128i(r, _mm_setzero_si128());
4881 let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
4882 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4883 assert_eq_m128i(r, e);
4884 }
4885
4886 #[simd_test(enable = "avx512f,avx512vl")]
4887 unsafe fn test_mm_cvtusepi64_epi16() {
4888 let a = _mm_set_epi64x(6, i64::MAX);
4889 let r = _mm_cvtusepi64_epi16(a);
4890 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
4891 assert_eq_m128i(r, e);
4892 }
4893
4894 #[simd_test(enable = "avx512f,avx512vl")]
4895 unsafe fn test_mm_mask_cvtusepi64_epi16() {
4896 let a = _mm_set_epi64x(6, i64::MAX);
4897 let src = _mm_set1_epi16(0);
4898 let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
4899 assert_eq_m128i(r, src);
4900 let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
4901 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
4902 assert_eq_m128i(r, e);
4903 }
4904
4905 #[simd_test(enable = "avx512f,avx512vl")]
4906 unsafe fn test_mm_maskz_cvtusepi64_epi16() {
4907 let a = _mm_set_epi64x(6, i64::MAX);
4908 let r = _mm_maskz_cvtusepi64_epi16(0, a);
4909 assert_eq_m128i(r, _mm_setzero_si128());
4910 let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
4911 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
4912 assert_eq_m128i(r, e);
4913 }
4914
4915 #[simd_test(enable = "avx512f")]
4916 unsafe fn test_mm512_cvtusepi64_epi8() {
4917 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4918 let r = _mm512_cvtusepi64_epi8(a);
4919 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
4920 assert_eq_m128i(r, e);
4921 }
4922
4923 #[simd_test(enable = "avx512f")]
4924 unsafe fn test_mm512_mask_cvtusepi64_epi8() {
4925 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4926 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4927 let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
4928 assert_eq_m128i(r, src);
4929 let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
4930 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
4931 assert_eq_m128i(r, e);
4932 }
4933
4934 #[simd_test(enable = "avx512f")]
4935 unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
4936 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4937 let r = _mm512_maskz_cvtusepi64_epi8(0, a);
4938 assert_eq_m128i(r, _mm_setzero_si128());
4939 let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
4940 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
4941 assert_eq_m128i(r, e);
4942 }
4943
4944 #[simd_test(enable = "avx512f,avx512vl")]
4945 unsafe fn test_mm256_cvtusepi64_epi8() {
4946 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4947 let r = _mm256_cvtusepi64_epi8(a);
4948 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
4949 assert_eq_m128i(r, e);
4950 }
4951
4952 #[simd_test(enable = "avx512f,avx512vl")]
4953 unsafe fn test_mm256_mask_cvtusepi64_epi8() {
4954 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4955 let src = _mm_set1_epi8(0);
4956 let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
4957 assert_eq_m128i(r, src);
4958 let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
4959 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
4960 assert_eq_m128i(r, e);
4961 }
4962
4963 #[simd_test(enable = "avx512f,avx512vl")]
4964 unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
4965 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4966 let r = _mm256_maskz_cvtusepi64_epi8(0, a);
4967 assert_eq_m128i(r, _mm_setzero_si128());
4968 let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
4969 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
4970 assert_eq_m128i(r, e);
4971 }
4972
4973 #[simd_test(enable = "avx512f,avx512vl")]
4974 unsafe fn test_mm_cvtusepi64_epi8() {
4975 let a = _mm_set_epi64x(6, i64::MAX);
4976 let r = _mm_cvtusepi64_epi8(a);
4977 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
4978 assert_eq_m128i(r, e);
4979 }
4980
4981 #[simd_test(enable = "avx512f,avx512vl")]
4982 unsafe fn test_mm_mask_cvtusepi64_epi8() {
4983 let a = _mm_set_epi64x(6, i64::MAX);
4984 let src = _mm_set1_epi8(0);
4985 let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
4986 assert_eq_m128i(r, src);
4987 let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
4988 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
4989 assert_eq_m128i(r, e);
4990 }
4991
4992 #[simd_test(enable = "avx512f,avx512vl")]
4993 unsafe fn test_mm_maskz_cvtusepi64_epi8() {
4994 let a = _mm_set_epi64x(6, i64::MAX);
4995 let r = _mm_maskz_cvtusepi64_epi8(0, a);
4996 assert_eq_m128i(r, _mm_setzero_si128());
4997 let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
4998 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
4999 assert_eq_m128i(r, e);
5000 }
5001
5002 #[simd_test(enable = "avx512f")]
5003 unsafe fn test_mm512_cvtt_roundpd_epi32() {
5004 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5005 let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5006 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5007 assert_eq_m256i(r, e);
5008 }
5009
5010 #[simd_test(enable = "avx512f")]
5011 unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5012 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5013 let src = _mm256_set1_epi32(0);
5014 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5015 assert_eq_m256i(r, src);
5016 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5017 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5018 assert_eq_m256i(r, e);
5019 }
5020
5021 #[simd_test(enable = "avx512f")]
5022 unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5023 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5024 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5025 assert_eq_m256i(r, _mm256_setzero_si256());
5026 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5027 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5028 assert_eq_m256i(r, e);
5029 }
5030
5031 #[simd_test(enable = "avx512f")]
5032 unsafe fn test_mm512_cvtt_roundpd_epu32() {
5033 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5034 let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5035 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5036 assert_eq_m256i(r, e);
5037 }
5038
5039 #[simd_test(enable = "avx512f")]
5040 unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5041 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5042 let src = _mm256_set1_epi32(0);
5043 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5044 assert_eq_m256i(r, src);
5045 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5046 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5047 assert_eq_m256i(r, e);
5048 }
5049
5050 #[simd_test(enable = "avx512f")]
5051 unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5052 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5053 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5054 assert_eq_m256i(r, _mm256_setzero_si256());
5055 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5056 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5057 assert_eq_m256i(r, e);
5058 }
5059
5060 #[simd_test(enable = "avx512f")]
5061 unsafe fn test_mm512_cvttpd_epi32() {
5062 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5063 let r = _mm512_cvttpd_epi32(a);
5064 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5065 assert_eq_m256i(r, e);
5066 }
5067
5068 #[simd_test(enable = "avx512f")]
5069 unsafe fn test_mm512_mask_cvttpd_epi32() {
5070 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5071 let src = _mm256_set1_epi32(0);
5072 let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5073 assert_eq_m256i(r, src);
5074 let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5075 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5076 assert_eq_m256i(r, e);
5077 }
5078
5079 #[simd_test(enable = "avx512f")]
5080 unsafe fn test_mm512_maskz_cvttpd_epi32() {
5081 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5082 let r = _mm512_maskz_cvttpd_epi32(0, a);
5083 assert_eq_m256i(r, _mm256_setzero_si256());
5084 let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5085 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5086 assert_eq_m256i(r, e);
5087 }
5088
5089 #[simd_test(enable = "avx512f,avx512vl")]
5090 unsafe fn test_mm256_mask_cvttpd_epi32() {
5091 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5092 let src = _mm_set1_epi32(0);
5093 let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5094 assert_eq_m128i(r, src);
5095 let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5096 let e = _mm_setr_epi32(4, -5, 6, -7);
5097 assert_eq_m128i(r, e);
5098 }
5099
5100 #[simd_test(enable = "avx512f,avx512vl")]
5101 unsafe fn test_mm256_maskz_cvttpd_epi32() {
5102 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5103 let r = _mm256_maskz_cvttpd_epi32(0, a);
5104 assert_eq_m128i(r, _mm_setzero_si128());
5105 let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5106 let e = _mm_setr_epi32(4, -5, 6, -7);
5107 assert_eq_m128i(r, e);
5108 }
5109
5110 #[simd_test(enable = "avx512f,avx512vl")]
5111 unsafe fn test_mm_mask_cvttpd_epi32() {
5112 let a = _mm_set_pd(6., -7.5);
5113 let src = _mm_set1_epi32(0);
5114 let r = _mm_mask_cvttpd_epi32(src, 0, a);
5115 assert_eq_m128i(r, src);
5116 let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5117 let e = _mm_set_epi32(0, 0, 6, -7);
5118 assert_eq_m128i(r, e);
5119 }
5120
5121 #[simd_test(enable = "avx512f,avx512vl")]
5122 unsafe fn test_mm_maskz_cvttpd_epi32() {
5123 let a = _mm_set_pd(6., -7.5);
5124 let r = _mm_maskz_cvttpd_epi32(0, a);
5125 assert_eq_m128i(r, _mm_setzero_si128());
5126 let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5127 let e = _mm_set_epi32(0, 0, 6, -7);
5128 assert_eq_m128i(r, e);
5129 }
5130
5131 #[simd_test(enable = "avx512f")]
5132 unsafe fn test_mm512_cvttpd_epu32() {
5133 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5134 let r = _mm512_cvttpd_epu32(a);
5135 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5136 assert_eq_m256i(r, e);
5137 }
5138
5139 #[simd_test(enable = "avx512f")]
5140 unsafe fn test_mm512_mask_cvttpd_epu32() {
5141 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5142 let src = _mm256_set1_epi32(0);
5143 let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5144 assert_eq_m256i(r, src);
5145 let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5146 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5147 assert_eq_m256i(r, e);
5148 }
5149
5150 #[simd_test(enable = "avx512f")]
5151 unsafe fn test_mm512_maskz_cvttpd_epu32() {
5152 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5153 let r = _mm512_maskz_cvttpd_epu32(0, a);
5154 assert_eq_m256i(r, _mm256_setzero_si256());
5155 let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5156 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5157 assert_eq_m256i(r, e);
5158 }
5159
5160 #[simd_test(enable = "avx512f,avx512vl")]
5161 unsafe fn test_mm256_cvttpd_epu32() {
5162 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5163 let r = _mm256_cvttpd_epu32(a);
5164 let e = _mm_set_epi32(4, 5, 6, 7);
5165 assert_eq_m128i(r, e);
5166 }
5167
5168 #[simd_test(enable = "avx512f,avx512vl")]
5169 unsafe fn test_mm256_mask_cvttpd_epu32() {
5170 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5171 let src = _mm_set1_epi32(0);
5172 let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5173 assert_eq_m128i(r, src);
5174 let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5175 let e = _mm_set_epi32(4, 5, 6, 7);
5176 assert_eq_m128i(r, e);
5177 }
5178
5179 #[simd_test(enable = "avx512f,avx512vl")]
5180 unsafe fn test_mm256_maskz_cvttpd_epu32() {
5181 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5182 let r = _mm256_maskz_cvttpd_epu32(0, a);
5183 assert_eq_m128i(r, _mm_setzero_si128());
5184 let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5185 let e = _mm_set_epi32(4, 5, 6, 7);
5186 assert_eq_m128i(r, e);
5187 }
5188
5189 #[simd_test(enable = "avx512f,avx512vl")]
5190 unsafe fn test_mm_cvttpd_epu32() {
5191 let a = _mm_set_pd(6., 7.5);
5192 let r = _mm_cvttpd_epu32(a);
5193 let e = _mm_set_epi32(0, 0, 6, 7);
5194 assert_eq_m128i(r, e);
5195 }
5196
5197 #[simd_test(enable = "avx512f,avx512vl")]
5198 unsafe fn test_mm_mask_cvttpd_epu32() {
5199 let a = _mm_set_pd(6., 7.5);
5200 let src = _mm_set1_epi32(0);
5201 let r = _mm_mask_cvttpd_epu32(src, 0, a);
5202 assert_eq_m128i(r, src);
5203 let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5204 let e = _mm_set_epi32(0, 0, 6, 7);
5205 assert_eq_m128i(r, e);
5206 }
5207
5208 #[simd_test(enable = "avx512f,avx512vl")]
5209 unsafe fn test_mm_maskz_cvttpd_epu32() {
5210 let a = _mm_set_pd(6., 7.5);
5211 let r = _mm_maskz_cvttpd_epu32(0, a);
5212 assert_eq_m128i(r, _mm_setzero_si128());
5213 let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5214 let e = _mm_set_epi32(0, 0, 6, 7);
5215 assert_eq_m128i(r, e);
5216 }
5217
5218 #[simd_test(enable = "avx512f")]
5219 unsafe fn test_mm512_add_round_pd() {
5220 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5221 let b = _mm512_set1_pd(-1.);
5222 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5223 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5224 assert_eq_m512d(r, e);
5225 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5226 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5227 assert_eq_m512d(r, e);
5228 }
5229
5230 #[simd_test(enable = "avx512f")]
5231 unsafe fn test_mm512_mask_add_round_pd() {
5232 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5233 let b = _mm512_set1_pd(-1.);
5234 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5235 a, 0, a, b,
5236 );
5237 assert_eq_m512d(r, a);
5238 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5239 a, 0b11110000, a, b,
5240 );
5241 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5242 assert_eq_m512d(r, e);
5243 }
5244
5245 #[simd_test(enable = "avx512f")]
5246 unsafe fn test_mm512_maskz_add_round_pd() {
5247 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5248 let b = _mm512_set1_pd(-1.);
5249 let r =
5250 _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5251 assert_eq_m512d(r, _mm512_setzero_pd());
5252 let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5253 0b11110000, a, b,
5254 );
5255 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5256 assert_eq_m512d(r, e);
5257 }
5258
5259 #[simd_test(enable = "avx512f")]
5260 unsafe fn test_mm512_sub_round_pd() {
5261 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5262 let b = _mm512_set1_pd(1.);
5263 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5264 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5265 assert_eq_m512d(r, e);
5266 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5267 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5268 assert_eq_m512d(r, e);
5269 }
5270
5271 #[simd_test(enable = "avx512f")]
5272 unsafe fn test_mm512_mask_sub_round_pd() {
5273 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5274 let b = _mm512_set1_pd(1.);
5275 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5276 a, 0, a, b,
5277 );
5278 assert_eq_m512d(r, a);
5279 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5280 a, 0b11110000, a, b,
5281 );
5282 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5283 assert_eq_m512d(r, e);
5284 }
5285
5286 #[simd_test(enable = "avx512f")]
5287 unsafe fn test_mm512_maskz_sub_round_pd() {
5288 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5289 let b = _mm512_set1_pd(1.);
5290 let r =
5291 _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5292 assert_eq_m512d(r, _mm512_setzero_pd());
5293 let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5294 0b11110000, a, b,
5295 );
5296 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5297 assert_eq_m512d(r, e);
5298 }
5299
5300 #[simd_test(enable = "avx512f")]
5301 unsafe fn test_mm512_mul_round_pd() {
5302 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5303 let b = _mm512_set1_pd(0.1);
5304 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5305 let e = _mm512_setr_pd(
5306 0.8,
5307 0.9500000000000001,
5308 1.,
5309 1.1500000000000001,
5310 1.2000000000000002,
5311 1.35,
5312 1.4000000000000001,
5313 0.,
5314 );
5315 assert_eq_m512d(r, e);
5316 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5317 let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5318 assert_eq_m512d(r, e);
5319 }
5320
5321 #[simd_test(enable = "avx512f")]
5322 unsafe fn test_mm512_mask_mul_round_pd() {
5323 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5324 let b = _mm512_set1_pd(0.1);
5325 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5326 a, 0, a, b,
5327 );
5328 assert_eq_m512d(r, a);
5329 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5330 a, 0b11110000, a, b,
5331 );
5332 let e = _mm512_setr_pd(
5333 8.,
5334 9.5,
5335 10.,
5336 11.5,
5337 1.2000000000000002,
5338 1.35,
5339 1.4000000000000001,
5340 0.,
5341 );
5342 assert_eq_m512d(r, e);
5343 }
5344
5345 #[simd_test(enable = "avx512f")]
5346 unsafe fn test_mm512_maskz_mul_round_pd() {
5347 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5348 let b = _mm512_set1_pd(0.1);
5349 let r =
5350 _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5351 assert_eq_m512d(r, _mm512_setzero_pd());
5352 let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5353 0b11110000, a, b,
5354 );
5355 let e = _mm512_setr_pd(
5356 0.,
5357 0.,
5358 0.,
5359 0.,
5360 1.2000000000000002,
5361 1.35,
5362 1.4000000000000001,
5363 0.,
5364 );
5365 assert_eq_m512d(r, e);
5366 }
5367
5368 #[simd_test(enable = "avx512f")]
5369 unsafe fn test_mm512_div_round_pd() {
5370 let a = _mm512_set1_pd(1.);
5371 let b = _mm512_set1_pd(3.);
5372 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5373 let e = _mm512_set1_pd(0.3333333333333333);
5374 assert_eq_m512d(r, e);
5375 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5376 let e = _mm512_set1_pd(0.3333333333333333);
5377 assert_eq_m512d(r, e);
5378 }
5379
5380 #[simd_test(enable = "avx512f")]
5381 unsafe fn test_mm512_mask_div_round_pd() {
5382 let a = _mm512_set1_pd(1.);
5383 let b = _mm512_set1_pd(3.);
5384 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5385 a, 0, a, b,
5386 );
5387 assert_eq_m512d(r, a);
5388 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5389 a, 0b11110000, a, b,
5390 );
5391 let e = _mm512_setr_pd(
5392 1.,
5393 1.,
5394 1.,
5395 1.,
5396 0.3333333333333333,
5397 0.3333333333333333,
5398 0.3333333333333333,
5399 0.3333333333333333,
5400 );
5401 assert_eq_m512d(r, e);
5402 }
5403
5404 #[simd_test(enable = "avx512f")]
5405 unsafe fn test_mm512_maskz_div_round_pd() {
5406 let a = _mm512_set1_pd(1.);
5407 let b = _mm512_set1_pd(3.);
5408 let r =
5409 _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5410 assert_eq_m512d(r, _mm512_setzero_pd());
5411 let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5412 0b11110000, a, b,
5413 );
5414 let e = _mm512_setr_pd(
5415 0.,
5416 0.,
5417 0.,
5418 0.,
5419 0.3333333333333333,
5420 0.3333333333333333,
5421 0.3333333333333333,
5422 0.3333333333333333,
5423 );
5424 assert_eq_m512d(r, e);
5425 }
5426
5427 #[simd_test(enable = "avx512f")]
5428 unsafe fn test_mm512_sqrt_round_pd() {
5429 let a = _mm512_set1_pd(3.);
5430 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5431 let e = _mm512_set1_pd(1.7320508075688772);
5432 assert_eq_m512d(r, e);
5433 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5434 let e = _mm512_set1_pd(1.7320508075688774);
5435 assert_eq_m512d(r, e);
5436 }
5437
5438 #[simd_test(enable = "avx512f")]
5439 unsafe fn test_mm512_mask_sqrt_round_pd() {
5440 let a = _mm512_set1_pd(3.);
5441 let r =
5442 _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5443 assert_eq_m512d(r, a);
5444 let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5445 a, 0b11110000, a,
5446 );
5447 let e = _mm512_setr_pd(
5448 3.,
5449 3.,
5450 3.,
5451 3.,
5452 1.7320508075688772,
5453 1.7320508075688772,
5454 1.7320508075688772,
5455 1.7320508075688772,
5456 );
5457 assert_eq_m512d(r, e);
5458 }
5459
5460 #[simd_test(enable = "avx512f")]
5461 unsafe fn test_mm512_maskz_sqrt_round_pd() {
5462 let a = _mm512_set1_pd(3.);
5463 let r =
5464 _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5465 assert_eq_m512d(r, _mm512_setzero_pd());
5466 let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5467 0b11110000, a,
5468 );
5469 let e = _mm512_setr_pd(
5470 0.,
5471 0.,
5472 0.,
5473 0.,
5474 1.7320508075688772,
5475 1.7320508075688772,
5476 1.7320508075688772,
5477 1.7320508075688772,
5478 );
5479 assert_eq_m512d(r, e);
5480 }
5481
5482 #[simd_test(enable = "avx512f")]
5483 unsafe fn test_mm512_fmadd_round_pd() {
5484 let a = _mm512_set1_pd(0.000000000000000007);
5485 let b = _mm512_set1_pd(1.);
5486 let c = _mm512_set1_pd(-1.);
5487 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5488 let e = _mm512_set1_pd(-1.);
5489 assert_eq_m512d(r, e);
5490 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5491 let e = _mm512_set1_pd(-0.9999999999999999);
5492 assert_eq_m512d(r, e);
5493 }
5494
5495 #[simd_test(enable = "avx512f")]
5496 unsafe fn test_mm512_mask_fmadd_round_pd() {
5497 let a = _mm512_set1_pd(0.000000000000000007);
5498 let b = _mm512_set1_pd(1.);
5499 let c = _mm512_set1_pd(-1.);
5500 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5501 a, 0, b, c,
5502 );
5503 assert_eq_m512d(r, a);
5504 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5505 a, 0b00001111, b, c,
5506 );
5507 let e = _mm512_setr_pd(
5508 -1.,
5509 -1.,
5510 -1.,
5511 -1.,
5512 0.000000000000000007,
5513 0.000000000000000007,
5514 0.000000000000000007,
5515 0.000000000000000007,
5516 );
5517 assert_eq_m512d(r, e);
5518 }
5519
5520 #[simd_test(enable = "avx512f")]
5521 unsafe fn test_mm512_maskz_fmadd_round_pd() {
5522 let a = _mm512_set1_pd(0.000000000000000007);
5523 let b = _mm512_set1_pd(1.);
5524 let c = _mm512_set1_pd(-1.);
5525 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5526 0, a, b, c,
5527 );
5528 assert_eq_m512d(r, _mm512_setzero_pd());
5529 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5530 0b00001111, a, b, c,
5531 );
5532 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5533 assert_eq_m512d(r, e);
5534 }
5535
5536 #[simd_test(enable = "avx512f")]
5537 unsafe fn test_mm512_mask3_fmadd_round_pd() {
5538 let a = _mm512_set1_pd(0.000000000000000007);
5539 let b = _mm512_set1_pd(1.);
5540 let c = _mm512_set1_pd(-1.);
5541 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5542 a, b, c, 0,
5543 );
5544 assert_eq_m512d(r, c);
5545 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5546 a, b, c, 0b00001111,
5547 );
5548 let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5549 assert_eq_m512d(r, e);
5550 }
5551
5552 #[simd_test(enable = "avx512f")]
5553 unsafe fn test_mm512_fmsub_round_pd() {
5554 let a = _mm512_set1_pd(0.000000000000000007);
5555 let b = _mm512_set1_pd(1.);
5556 let c = _mm512_set1_pd(1.);
5557 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5558 let e = _mm512_set1_pd(-1.);
5559 assert_eq_m512d(r, e);
5560 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5561 let e = _mm512_set1_pd(-0.9999999999999999);
5562 assert_eq_m512d(r, e);
5563 }
5564
5565 #[simd_test(enable = "avx512f")]
5566 unsafe fn test_mm512_mask_fmsub_round_pd() {
5567 let a = _mm512_set1_pd(0.000000000000000007);
5568 let b = _mm512_set1_pd(1.);
5569 let c = _mm512_set1_pd(1.);
5570 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5571 a, 0, b, c,
5572 );
5573 assert_eq_m512d(r, a);
5574 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5575 a, 0b00001111, b, c,
5576 );
5577 let e = _mm512_setr_pd(
5578 -1.,
5579 -1.,
5580 -1.,
5581 -1.,
5582 0.000000000000000007,
5583 0.000000000000000007,
5584 0.000000000000000007,
5585 0.000000000000000007,
5586 );
5587 assert_eq_m512d(r, e);
5588 }
5589
5590 #[simd_test(enable = "avx512f")]
5591 unsafe fn test_mm512_maskz_fmsub_round_pd() {
5592 let a = _mm512_set1_pd(0.000000000000000007);
5593 let b = _mm512_set1_pd(1.);
5594 let c = _mm512_set1_pd(1.);
5595 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5596 0, a, b, c,
5597 );
5598 assert_eq_m512d(r, _mm512_setzero_pd());
5599 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5600 0b00001111, a, b, c,
5601 );
5602 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5603 assert_eq_m512d(r, e);
5604 }
5605
5606 #[simd_test(enable = "avx512f")]
5607 unsafe fn test_mm512_mask3_fmsub_round_pd() {
5608 let a = _mm512_set1_pd(0.000000000000000007);
5609 let b = _mm512_set1_pd(1.);
5610 let c = _mm512_set1_pd(1.);
5611 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5612 a, b, c, 0,
5613 );
5614 assert_eq_m512d(r, c);
5615 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5616 a, b, c, 0b00001111,
5617 );
5618 let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5619 assert_eq_m512d(r, e);
5620 }
5621
5622 #[simd_test(enable = "avx512f")]
5623 unsafe fn test_mm512_fmaddsub_round_pd() {
5624 let a = _mm512_set1_pd(0.000000000000000007);
5625 let b = _mm512_set1_pd(1.);
5626 let c = _mm512_set1_pd(-1.);
5627 let r =
5628 _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5629 let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5630 assert_eq_m512d(r, e);
5631 let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5632 let e = _mm512_setr_pd(
5633 1.,
5634 -0.9999999999999999,
5635 1.,
5636 -0.9999999999999999,
5637 1.,
5638 -0.9999999999999999,
5639 1.,
5640 -0.9999999999999999,
5641 );
5642 assert_eq_m512d(r, e);
5643 }
5644
5645 #[simd_test(enable = "avx512f")]
5646 unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5647 let a = _mm512_set1_pd(0.000000000000000007);
5648 let b = _mm512_set1_pd(1.);
5649 let c = _mm512_set1_pd(-1.);
5650 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5651 a, 0, b, c,
5652 );
5653 assert_eq_m512d(r, a);
5654 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5655 a, 0b00001111, b, c,
5656 );
5657 let e = _mm512_setr_pd(
5658 1.,
5659 -1.,
5660 1.,
5661 -1.,
5662 0.000000000000000007,
5663 0.000000000000000007,
5664 0.000000000000000007,
5665 0.000000000000000007,
5666 );
5667 assert_eq_m512d(r, e);
5668 }
5669
5670 #[simd_test(enable = "avx512f")]
5671 unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5672 let a = _mm512_set1_pd(0.000000000000000007);
5673 let b = _mm512_set1_pd(1.);
5674 let c = _mm512_set1_pd(-1.);
5675 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5676 0, a, b, c,
5677 );
5678 assert_eq_m512d(r, _mm512_setzero_pd());
5679 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5680 0b00001111, a, b, c,
5681 );
5682 let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5683 assert_eq_m512d(r, e);
5684 }
5685
5686 #[simd_test(enable = "avx512f")]
5687 unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5688 let a = _mm512_set1_pd(0.000000000000000007);
5689 let b = _mm512_set1_pd(1.);
5690 let c = _mm512_set1_pd(-1.);
5691 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5692 a, b, c, 0,
5693 );
5694 assert_eq_m512d(r, c);
5695 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5696 a, b, c, 0b00001111,
5697 );
5698 let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5699 assert_eq_m512d(r, e);
5700 }
5701
5702 #[simd_test(enable = "avx512f")]
5703 unsafe fn test_mm512_fmsubadd_round_pd() {
5704 let a = _mm512_set1_pd(0.000000000000000007);
5705 let b = _mm512_set1_pd(1.);
5706 let c = _mm512_set1_pd(-1.);
5707 let r =
5708 _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5709 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5710 assert_eq_m512d(r, e);
5711 let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5712 let e = _mm512_setr_pd(
5713 -0.9999999999999999,
5714 1.,
5715 -0.9999999999999999,
5716 1.,
5717 -0.9999999999999999,
5718 1.,
5719 -0.9999999999999999,
5720 1.,
5721 );
5722 assert_eq_m512d(r, e);
5723 }
5724
5725 #[simd_test(enable = "avx512f")]
5726 unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5727 let a = _mm512_set1_pd(0.000000000000000007);
5728 let b = _mm512_set1_pd(1.);
5729 let c = _mm512_set1_pd(-1.);
5730 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5731 a, 0, b, c,
5732 );
5733 assert_eq_m512d(r, a);
5734 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5735 a, 0b00001111, b, c,
5736 );
5737 let e = _mm512_setr_pd(
5738 -1.,
5739 1.,
5740 -1.,
5741 1.,
5742 0.000000000000000007,
5743 0.000000000000000007,
5744 0.000000000000000007,
5745 0.000000000000000007,
5746 );
5747 assert_eq_m512d(r, e);
5748 }
5749
5750 #[simd_test(enable = "avx512f")]
5751 unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5752 let a = _mm512_set1_pd(0.000000000000000007);
5753 let b = _mm512_set1_pd(1.);
5754 let c = _mm512_set1_pd(-1.);
5755 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5756 0, a, b, c,
5757 );
5758 assert_eq_m512d(r, _mm512_setzero_pd());
5759 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5760 0b00001111, a, b, c,
5761 );
5762 let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5763 assert_eq_m512d(r, e);
5764 }
5765
5766 #[simd_test(enable = "avx512f")]
5767 unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5768 let a = _mm512_set1_pd(0.000000000000000007);
5769 let b = _mm512_set1_pd(1.);
5770 let c = _mm512_set1_pd(-1.);
5771 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5772 a, b, c, 0,
5773 );
5774 assert_eq_m512d(r, c);
5775 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5776 a, b, c, 0b00001111,
5777 );
5778 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5779 assert_eq_m512d(r, e);
5780 }
5781
5782 #[simd_test(enable = "avx512f")]
5783 unsafe fn test_mm512_fnmadd_round_pd() {
5784 let a = _mm512_set1_pd(0.000000000000000007);
5785 let b = _mm512_set1_pd(1.);
5786 let c = _mm512_set1_pd(1.);
5787 let r =
5788 _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5789 let e = _mm512_set1_pd(1.);
5790 assert_eq_m512d(r, e);
5791 let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5792 let e = _mm512_set1_pd(0.9999999999999999);
5793 assert_eq_m512d(r, e);
5794 }
5795
5796 #[simd_test(enable = "avx512f")]
5797 unsafe fn test_mm512_mask_fnmadd_round_pd() {
5798 let a = _mm512_set1_pd(0.000000000000000007);
5799 let b = _mm512_set1_pd(1.);
5800 let c = _mm512_set1_pd(1.);
5801 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5802 a, 0, b, c,
5803 );
5804 assert_eq_m512d(r, a);
5805 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5806 a, 0b00001111, b, c,
5807 );
5808 let e = _mm512_setr_pd(
5809 1.,
5810 1.,
5811 1.,
5812 1.,
5813 0.000000000000000007,
5814 0.000000000000000007,
5815 0.000000000000000007,
5816 0.000000000000000007,
5817 );
5818 assert_eq_m512d(r, e);
5819 }
5820
5821 #[simd_test(enable = "avx512f")]
5822 unsafe fn test_mm512_maskz_fnmadd_round_pd() {
5823 let a = _mm512_set1_pd(0.000000000000000007);
5824 let b = _mm512_set1_pd(1.);
5825 let c = _mm512_set1_pd(1.);
5826 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5827 0, a, b, c,
5828 );
5829 assert_eq_m512d(r, _mm512_setzero_pd());
5830 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5831 0b00001111, a, b, c,
5832 );
5833 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
5834 assert_eq_m512d(r, e);
5835 }
5836
5837 #[simd_test(enable = "avx512f")]
5838 unsafe fn test_mm512_mask3_fnmadd_round_pd() {
5839 let a = _mm512_set1_pd(0.000000000000000007);
5840 let b = _mm512_set1_pd(1.);
5841 let c = _mm512_set1_pd(1.);
5842 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5843 a, b, c, 0,
5844 );
5845 assert_eq_m512d(r, c);
5846 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5847 a, b, c, 0b00001111,
5848 );
5849 let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
5850 assert_eq_m512d(r, e);
5851 }
5852
5853 #[simd_test(enable = "avx512f")]
5854 unsafe fn test_mm512_fnmsub_round_pd() {
5855 let a = _mm512_set1_pd(0.000000000000000007);
5856 let b = _mm512_set1_pd(1.);
5857 let c = _mm512_set1_pd(-1.);
5858 let r =
5859 _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5860 let e = _mm512_set1_pd(1.);
5861 assert_eq_m512d(r, e);
5862 let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5863 let e = _mm512_set1_pd(0.9999999999999999);
5864 assert_eq_m512d(r, e);
5865 }
5866
5867 #[simd_test(enable = "avx512f")]
5868 unsafe fn test_mm512_mask_fnmsub_round_pd() {
5869 let a = _mm512_set1_pd(0.000000000000000007);
5870 let b = _mm512_set1_pd(1.);
5871 let c = _mm512_set1_pd(-1.);
5872 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5873 a, 0, b, c,
5874 );
5875 assert_eq_m512d(r, a);
5876 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5877 a, 0b00001111, b, c,
5878 );
5879 let e = _mm512_setr_pd(
5880 1.,
5881 1.,
5882 1.,
5883 1.,
5884 0.000000000000000007,
5885 0.000000000000000007,
5886 0.000000000000000007,
5887 0.000000000000000007,
5888 );
5889 assert_eq_m512d(r, e);
5890 }
5891
5892 #[simd_test(enable = "avx512f")]
5893 unsafe fn test_mm512_maskz_fnmsub_round_pd() {
5894 let a = _mm512_set1_pd(0.000000000000000007);
5895 let b = _mm512_set1_pd(1.);
5896 let c = _mm512_set1_pd(-1.);
5897 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5898 0, a, b, c,
5899 );
5900 assert_eq_m512d(r, _mm512_setzero_pd());
5901 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5902 0b00001111, a, b, c,
5903 );
5904 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
5905 assert_eq_m512d(r, e);
5906 }
5907
5908 #[simd_test(enable = "avx512f")]
5909 unsafe fn test_mm512_mask3_fnmsub_round_pd() {
5910 let a = _mm512_set1_pd(0.000000000000000007);
5911 let b = _mm512_set1_pd(1.);
5912 let c = _mm512_set1_pd(-1.);
5913 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5914 a, b, c, 0,
5915 );
5916 assert_eq_m512d(r, c);
5917 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5918 a, b, c, 0b00001111,
5919 );
5920 let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
5921 assert_eq_m512d(r, e);
5922 }
5923
5924 #[simd_test(enable = "avx512f")]
5925 unsafe fn test_mm512_max_round_pd() {
5926 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5927 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5928 let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
5929 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
5930 assert_eq_m512d(r, e);
5931 }
5932
5933 #[simd_test(enable = "avx512f")]
5934 unsafe fn test_mm512_mask_max_round_pd() {
5935 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5936 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5937 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
5938 assert_eq_m512d(r, a);
5939 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
5940 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
5941 assert_eq_m512d(r, e);
5942 }
5943
5944 #[simd_test(enable = "avx512f")]
5945 unsafe fn test_mm512_maskz_max_round_pd() {
5946 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5947 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5948 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
5949 assert_eq_m512d(r, _mm512_setzero_pd());
5950 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
5951 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
5952 assert_eq_m512d(r, e);
5953 }
5954
5955 #[simd_test(enable = "avx512f")]
5956 unsafe fn test_mm512_min_round_pd() {
5957 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5958 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5959 let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
5960 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
5961 assert_eq_m512d(r, e);
5962 }
5963
5964 #[simd_test(enable = "avx512f")]
5965 unsafe fn test_mm512_mask_min_round_pd() {
5966 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5967 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5968 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
5969 assert_eq_m512d(r, a);
5970 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
5971 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5972 assert_eq_m512d(r, e);
5973 }
5974
5975 #[simd_test(enable = "avx512f")]
5976 unsafe fn test_mm512_maskz_min_round_pd() {
5977 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
5978 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
5979 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
5980 assert_eq_m512d(r, _mm512_setzero_pd());
5981 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
5982 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
5983 assert_eq_m512d(r, e);
5984 }
5985
5986 #[simd_test(enable = "avx512f")]
5987 unsafe fn test_mm512_getexp_round_pd() {
5988 let a = _mm512_set1_pd(3.);
5989 let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
5990 let e = _mm512_set1_pd(1.);
5991 assert_eq_m512d(r, e);
5992 }
5993
5994 #[simd_test(enable = "avx512f")]
5995 unsafe fn test_mm512_mask_getexp_round_pd() {
5996 let a = _mm512_set1_pd(3.);
5997 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
5998 assert_eq_m512d(r, a);
5999 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6000 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6001 assert_eq_m512d(r, e);
6002 }
6003
6004 #[simd_test(enable = "avx512f")]
6005 unsafe fn test_mm512_maskz_getexp_round_pd() {
6006 let a = _mm512_set1_pd(3.);
6007 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6008 assert_eq_m512d(r, _mm512_setzero_pd());
6009 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6010 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6011 assert_eq_m512d(r, e);
6012 }
6013
6014 #[simd_test(enable = "avx512f")]
6015 unsafe fn test_mm512_roundscale_round_pd() {
6016 let a = _mm512_set1_pd(1.1);
6017 let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6018 let e = _mm512_set1_pd(1.0);
6019 assert_eq_m512d(r, e);
6020 }
6021
6022 #[simd_test(enable = "avx512f")]
6023 unsafe fn test_mm512_mask_roundscale_round_pd() {
6024 let a = _mm512_set1_pd(1.1);
6025 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6026 let e = _mm512_set1_pd(1.1);
6027 assert_eq_m512d(r, e);
6028 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6029 let e = _mm512_set1_pd(1.0);
6030 assert_eq_m512d(r, e);
6031 }
6032
6033 #[simd_test(enable = "avx512f")]
6034 unsafe fn test_mm512_maskz_roundscale_round_pd() {
6035 let a = _mm512_set1_pd(1.1);
6036 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6037 assert_eq_m512d(r, _mm512_setzero_pd());
6038 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6039 let e = _mm512_set1_pd(1.0);
6040 assert_eq_m512d(r, e);
6041 }
6042
6043 #[simd_test(enable = "avx512f")]
6044 unsafe fn test_mm512_scalef_round_pd() {
6045 let a = _mm512_set1_pd(1.);
6046 let b = _mm512_set1_pd(3.);
6047 let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6048 let e = _mm512_set1_pd(8.);
6049 assert_eq_m512d(r, e);
6050 }
6051
6052 #[simd_test(enable = "avx512f")]
6053 unsafe fn test_mm512_mask_scalef_round_pd() {
6054 let a = _mm512_set1_pd(1.);
6055 let b = _mm512_set1_pd(3.);
6056 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6057 a, 0, a, b,
6058 );
6059 assert_eq_m512d(r, a);
6060 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6061 a, 0b11110000, a, b,
6062 );
6063 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6064 assert_eq_m512d(r, e);
6065 }
6066
6067 #[simd_test(enable = "avx512f")]
6068 unsafe fn test_mm512_maskz_scalef_round_pd() {
6069 let a = _mm512_set1_pd(1.);
6070 let b = _mm512_set1_pd(3.);
6071 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6072 0, a, b,
6073 );
6074 assert_eq_m512d(r, _mm512_setzero_pd());
6075 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6076 0b11110000, a, b,
6077 );
6078 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6079 assert_eq_m512d(r, e);
6080 }
6081
6082 #[simd_test(enable = "avx512f")]
6083 unsafe fn test_mm512_fixupimm_round_pd() {
6084 let a = _mm512_set1_pd(f64::NAN);
6085 let b = _mm512_set1_pd(f64::MAX);
6086 let c = _mm512_set1_epi64(i32::MAX as i64);
6087 let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6088 let e = _mm512_set1_pd(0.0);
6089 assert_eq_m512d(r, e);
6090 }
6091
6092 #[simd_test(enable = "avx512f")]
6093 unsafe fn test_mm512_mask_fixupimm_round_pd() {
6094 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6095 let b = _mm512_set1_pd(f64::MAX);
6096 let c = _mm512_set1_epi64(i32::MAX as i64);
6097 let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6098 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6099 assert_eq_m512d(r, e);
6100 }
6101
6102 #[simd_test(enable = "avx512f")]
6103 unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6104 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6105 let b = _mm512_set1_pd(f64::MAX);
6106 let c = _mm512_set1_epi64(i32::MAX as i64);
6107 let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6108 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6109 assert_eq_m512d(r, e);
6110 }
6111
6112 #[simd_test(enable = "avx512f")]
6113 unsafe fn test_mm512_getmant_round_pd() {
6114 let a = _mm512_set1_pd(10.);
6115 let r = _mm512_getmant_round_pd::<
6116 _MM_MANT_NORM_1_2,
6117 _MM_MANT_SIGN_SRC,
6118 _MM_FROUND_CUR_DIRECTION,
6119 >(a);
6120 let e = _mm512_set1_pd(1.25);
6121 assert_eq_m512d(r, e);
6122 }
6123
6124 #[simd_test(enable = "avx512f")]
6125 unsafe fn test_mm512_mask_getmant_round_pd() {
6126 let a = _mm512_set1_pd(10.);
6127 let r = _mm512_mask_getmant_round_pd::<
6128 _MM_MANT_NORM_1_2,
6129 _MM_MANT_SIGN_SRC,
6130 _MM_FROUND_CUR_DIRECTION,
6131 >(a, 0, a);
6132 assert_eq_m512d(r, a);
6133 let r = _mm512_mask_getmant_round_pd::<
6134 _MM_MANT_NORM_1_2,
6135 _MM_MANT_SIGN_SRC,
6136 _MM_FROUND_CUR_DIRECTION,
6137 >(a, 0b11110000, a);
6138 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6139 assert_eq_m512d(r, e);
6140 }
6141
6142 #[simd_test(enable = "avx512f")]
6143 unsafe fn test_mm512_maskz_getmant_round_pd() {
6144 let a = _mm512_set1_pd(10.);
6145 let r = _mm512_maskz_getmant_round_pd::<
6146 _MM_MANT_NORM_1_2,
6147 _MM_MANT_SIGN_SRC,
6148 _MM_FROUND_CUR_DIRECTION,
6149 >(0, a);
6150 assert_eq_m512d(r, _mm512_setzero_pd());
6151 let r = _mm512_maskz_getmant_round_pd::<
6152 _MM_MANT_NORM_1_2,
6153 _MM_MANT_SIGN_SRC,
6154 _MM_FROUND_CUR_DIRECTION,
6155 >(0b11110000, a);
6156 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6157 assert_eq_m512d(r, e);
6158 }
6159
6160 #[simd_test(enable = "avx512f")]
6161 unsafe fn test_mm512_cvt_roundps_pd() {
6162 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6163 let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6164 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6165 assert_eq_m512d(r, e);
6166 }
6167
6168 #[simd_test(enable = "avx512f")]
6169 unsafe fn test_mm512_mask_cvt_roundps_pd() {
6170 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6171 let src = _mm512_set1_pd(0.);
6172 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6173 assert_eq_m512d(r, src);
6174 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6175 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6176 assert_eq_m512d(r, e);
6177 }
6178
6179 #[simd_test(enable = "avx512f")]
6180 unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6181 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6182 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6183 assert_eq_m512d(r, _mm512_setzero_pd());
6184 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6185 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6186 assert_eq_m512d(r, e);
6187 }
6188
6189 #[simd_test(enable = "avx512f")]
6190 unsafe fn test_mm512_cvt_roundpd_ps() {
6191 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6192 let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6193 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6194 assert_eq_m256(r, e);
6195 }
6196
6197 #[simd_test(enable = "avx512f")]
6198 unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6199 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6200 let src = _mm256_set1_ps(0.);
6201 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6202 assert_eq_m256(r, src);
6203 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6204 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6205 assert_eq_m256(r, e);
6206 }
6207
6208 #[simd_test(enable = "avx512f")]
6209 unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6210 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6211 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6212 assert_eq_m256(r, _mm256_setzero_ps());
6213 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6214 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6215 assert_eq_m256(r, e);
6216 }
6217
6218 #[simd_test(enable = "avx512f")]
6219 unsafe fn test_mm512_cvt_roundpd_epi32() {
6220 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6221 let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6222 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6223 assert_eq_m256i(r, e);
6224 }
6225
6226 #[simd_test(enable = "avx512f")]
6227 unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6228 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6229 let src = _mm256_set1_epi32(0);
6230 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6231 assert_eq_m256i(r, src);
6232 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6233 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6234 assert_eq_m256i(r, e);
6235 }
6236
6237 #[simd_test(enable = "avx512f")]
6238 unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6239 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6240 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6241 assert_eq_m256i(r, _mm256_setzero_si256());
6242 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6243 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6244 assert_eq_m256i(r, e);
6245 }
6246
6247 #[simd_test(enable = "avx512f")]
6248 unsafe fn test_mm512_cvt_roundpd_epu32() {
6249 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6250 let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6251 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6252 assert_eq_m256i(r, e);
6253 }
6254
6255 #[simd_test(enable = "avx512f")]
6256 unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6257 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6258 let src = _mm256_set1_epi32(0);
6259 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6260 assert_eq_m256i(r, src);
6261 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6262 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6263 assert_eq_m256i(r, e);
6264 }
6265
6266 #[simd_test(enable = "avx512f")]
6267 unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6268 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6269 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6270 assert_eq_m256i(r, _mm256_setzero_si256());
6271 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6272 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6273 assert_eq_m256i(r, e);
6274 }
6275
6276 #[simd_test(enable = "avx512f")]
6277 unsafe fn test_mm512_setzero_pd() {
6278 assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6279 }
6280
6281 unsafe fn test_mm512_set1_epi64() {
6282 let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6283 assert_eq_m512i(r, _mm512_set1_epi64(2));
6284 }
6285
6286 #[simd_test(enable = "avx512f")]
6287 unsafe fn test_mm512_set1_pd() {
6288 let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6289 assert_eq_m512d(expected, _mm512_set1_pd(2.));
6290 }
6291
6292 unsafe fn test_mm512_set4_epi64() {
6293 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6294 assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6295 }
6296
6297 #[simd_test(enable = "avx512f")]
6298 unsafe fn test_mm512_set4_pd() {
6299 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6300 assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6301 }
6302
6303 unsafe fn test_mm512_setr4_epi64() {
6304 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6305 assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6306 }
6307
6308 #[simd_test(enable = "avx512f")]
6309 unsafe fn test_mm512_setr4_pd() {
6310 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6311 assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6312 }
6313
6314 #[simd_test(enable = "avx512f")]
6315 unsafe fn test_mm512_cmplt_pd_mask() {
6316 #[rustfmt::skip]
6317 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6318 let b = _mm512_set1_pd(-1.);
6319 let m = _mm512_cmplt_pd_mask(a, b);
6320 assert_eq!(m, 0b00000101);
6321 }
6322
6323 #[simd_test(enable = "avx512f")]
6324 unsafe fn test_mm512_mask_cmplt_pd_mask() {
6325 #[rustfmt::skip]
6326 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6327 let b = _mm512_set1_pd(-1.);
6328 let mask = 0b01100110;
6329 let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6330 assert_eq!(r, 0b00000100);
6331 }
6332
6333 #[simd_test(enable = "avx512f")]
6334 unsafe fn test_mm512_cmpnlt_pd_mask() {
6335 #[rustfmt::skip]
6336 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6337 let b = _mm512_set1_pd(-1.);
6338 assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6339 }
6340
6341 #[simd_test(enable = "avx512f")]
6342 unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6343 #[rustfmt::skip]
6344 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6345 let b = _mm512_set1_pd(-1.);
6346 let mask = 0b01111010;
6347 assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6348 }
6349
6350 #[simd_test(enable = "avx512f")]
6351 unsafe fn test_mm512_cmple_pd_mask() {
6352 #[rustfmt::skip]
6353 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6354 let b = _mm512_set1_pd(-1.);
6355 assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6356 }
6357
6358 #[simd_test(enable = "avx512f")]
6359 unsafe fn test_mm512_mask_cmple_pd_mask() {
6360 #[rustfmt::skip]
6361 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6362 let b = _mm512_set1_pd(-1.);
6363 let mask = 0b01111010;
6364 assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6365 }
6366
6367 #[simd_test(enable = "avx512f")]
6368 unsafe fn test_mm512_cmpnle_pd_mask() {
6369 #[rustfmt::skip]
6370 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6371 let b = _mm512_set1_pd(-1.);
6372 let m = _mm512_cmpnle_pd_mask(b, a);
6373 assert_eq!(m, 0b00001101);
6374 }
6375
6376 #[simd_test(enable = "avx512f")]
6377 unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6378 #[rustfmt::skip]
6379 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6380 let b = _mm512_set1_pd(-1.);
6381 let mask = 0b01100110;
6382 let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6383 assert_eq!(r, 0b00000100);
6384 }
6385
6386 #[simd_test(enable = "avx512f")]
6387 unsafe fn test_mm512_cmpeq_pd_mask() {
6388 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6389 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6390 let m = _mm512_cmpeq_pd_mask(b, a);
6391 assert_eq!(m, 0b11001101);
6392 }
6393
6394 #[simd_test(enable = "avx512f")]
6395 unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6396 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6397 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6398 let mask = 0b01111010;
6399 let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6400 assert_eq!(r, 0b01001000);
6401 }
6402
6403 #[simd_test(enable = "avx512f")]
6404 unsafe fn test_mm512_cmpneq_pd_mask() {
6405 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6406 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6407 let m = _mm512_cmpneq_pd_mask(b, a);
6408 assert_eq!(m, 0b00110010);
6409 }
6410
6411 #[simd_test(enable = "avx512f")]
6412 unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6413 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6414 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6415 let mask = 0b01111010;
6416 let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6417 assert_eq!(r, 0b00110010)
6418 }
6419
6420 #[simd_test(enable = "avx512f")]
6421 unsafe fn test_mm512_cmp_pd_mask() {
6422 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6423 let b = _mm512_set1_pd(-1.);
6424 let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6425 assert_eq!(m, 0b00000101);
6426 }
6427
6428 #[simd_test(enable = "avx512f")]
6429 unsafe fn test_mm512_mask_cmp_pd_mask() {
6430 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6431 let b = _mm512_set1_pd(-1.);
6432 let mask = 0b01100110;
6433 let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6434 assert_eq!(r, 0b00000100);
6435 }
6436
6437 #[simd_test(enable = "avx512f,avx512vl")]
6438 unsafe fn test_mm256_cmp_pd_mask() {
6439 let a = _mm256_set_pd(0., 1., -1., 13.);
6440 let b = _mm256_set1_pd(1.);
6441 let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6442 assert_eq!(m, 0b00001010);
6443 }
6444
6445 #[simd_test(enable = "avx512f,avx512vl")]
6446 unsafe fn test_mm256_mask_cmp_pd_mask() {
6447 let a = _mm256_set_pd(0., 1., -1., 13.);
6448 let b = _mm256_set1_pd(1.);
6449 let mask = 0b11111111;
6450 let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6451 assert_eq!(r, 0b00001010);
6452 }
6453
6454 #[simd_test(enable = "avx512f,avx512vl")]
6455 unsafe fn test_mm_cmp_pd_mask() {
6456 let a = _mm_set_pd(0., 1.);
6457 let b = _mm_set1_pd(1.);
6458 let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6459 assert_eq!(m, 0b00000010);
6460 }
6461
6462 #[simd_test(enable = "avx512f,avx512vl")]
6463 unsafe fn test_mm_mask_cmp_pd_mask() {
6464 let a = _mm_set_pd(0., 1.);
6465 let b = _mm_set1_pd(1.);
6466 let mask = 0b11111111;
6467 let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6468 assert_eq!(r, 0b00000010);
6469 }
6470
6471 #[simd_test(enable = "avx512f")]
6472 unsafe fn test_mm512_cmp_round_pd_mask() {
6473 #[rustfmt::skip]
6474 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6475 let b = _mm512_set1_pd(-1.);
6476 let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6477 assert_eq!(m, 0b00000101);
6478 }
6479
6480 #[simd_test(enable = "avx512f")]
6481 unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6482 #[rustfmt::skip]
6483 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6484 let b = _mm512_set1_pd(-1.);
6485 let mask = 0b01100110;
6486 let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6487 assert_eq!(r, 0b00000100);
6488 }
6489
6490 #[simd_test(enable = "avx512f")]
6491 unsafe fn test_mm512_cmpord_pd_mask() {
6492 #[rustfmt::skip]
6493 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6494 #[rustfmt::skip]
6495 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6496 let m = _mm512_cmpord_pd_mask(a, b);
6497 assert_eq!(m, 0b00000101);
6498 }
6499
6500 #[simd_test(enable = "avx512f")]
6501 unsafe fn test_mm512_mask_cmpord_pd_mask() {
6502 #[rustfmt::skip]
6503 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6504 #[rustfmt::skip]
6505 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6506 let mask = 0b11000011;
6507 let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6508 assert_eq!(m, 0b00000001);
6509 }
6510
6511 #[simd_test(enable = "avx512f")]
6512 unsafe fn test_mm512_cmpunord_pd_mask() {
6513 #[rustfmt::skip]
6514 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6515 #[rustfmt::skip]
6516 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6517 let m = _mm512_cmpunord_pd_mask(a, b);
6518
6519 assert_eq!(m, 0b11111010);
6520 }
6521
6522 #[simd_test(enable = "avx512f")]
6523 unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6524 #[rustfmt::skip]
6525 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6526 #[rustfmt::skip]
6527 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6528 let mask = 0b00001111;
6529 let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6530 assert_eq!(m, 0b000001010);
6531 }
6532
6533 #[simd_test(enable = "avx512f")]
6534 unsafe fn test_mm512_cmplt_epu64_mask() {
6535 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6536 let b = _mm512_set1_epi64(-1);
6537 let m = _mm512_cmplt_epu64_mask(a, b);
6538 assert_eq!(m, 0b11001111);
6539 }
6540
6541 #[simd_test(enable = "avx512f")]
6542 unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6543 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6544 let b = _mm512_set1_epi64(-1);
6545 let mask = 0b01111010;
6546 let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6547 assert_eq!(r, 0b01001010);
6548 }
6549
6550 #[simd_test(enable = "avx512f,avx512vl")]
6551 unsafe fn test_mm256_cmplt_epu64_mask() {
6552 let a = _mm256_set_epi64x(0, 1, 2, 100);
6553 let b = _mm256_set1_epi64x(2);
6554 let r = _mm256_cmplt_epu64_mask(a, b);
6555 assert_eq!(r, 0b00001100);
6556 }
6557
6558 #[simd_test(enable = "avx512f,avx512vl")]
6559 unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6560 let a = _mm256_set_epi64x(0, 1, 2, 100);
6561 let b = _mm256_set1_epi64x(2);
6562 let mask = 0b11111111;
6563 let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6564 assert_eq!(r, 0b00001100);
6565 }
6566
6567 #[simd_test(enable = "avx512f,avx512vl")]
6568 unsafe fn test_mm_cmplt_epu64_mask() {
6569 let a = _mm_set_epi64x(0, 1);
6570 let b = _mm_set1_epi64x(2);
6571 let r = _mm_cmplt_epu64_mask(a, b);
6572 assert_eq!(r, 0b00000011);
6573 }
6574
6575 #[simd_test(enable = "avx512f,avx512vl")]
6576 unsafe fn test_mm_mask_cmplt_epu64_mask() {
6577 let a = _mm_set_epi64x(0, 1);
6578 let b = _mm_set1_epi64x(2);
6579 let mask = 0b11111111;
6580 let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6581 assert_eq!(r, 0b00000011);
6582 }
6583
6584 #[simd_test(enable = "avx512f")]
6585 unsafe fn test_mm512_cmpgt_epu64_mask() {
6586 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6587 let b = _mm512_set1_epi64(-1);
6588 let m = _mm512_cmpgt_epu64_mask(b, a);
6589 assert_eq!(m, 0b11001111);
6590 }
6591
6592 #[simd_test(enable = "avx512f")]
6593 unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6594 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6595 let b = _mm512_set1_epi64(-1);
6596 let mask = 0b01111010;
6597 let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6598 assert_eq!(r, 0b01001010);
6599 }
6600
6601 #[simd_test(enable = "avx512f,avx512vl")]
6602 unsafe fn test_mm256_cmpgt_epu64_mask() {
6603 let a = _mm256_set_epi64x(0, 1, 2, 3);
6604 let b = _mm256_set1_epi64x(1);
6605 let r = _mm256_cmpgt_epu64_mask(a, b);
6606 assert_eq!(r, 0b00000011);
6607 }
6608
6609 #[simd_test(enable = "avx512f,avx512vl")]
6610 unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6611 let a = _mm256_set_epi64x(0, 1, 2, 3);
6612 let b = _mm256_set1_epi64x(1);
6613 let mask = 0b11111111;
6614 let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6615 assert_eq!(r, 0b00000011);
6616 }
6617
6618 #[simd_test(enable = "avx512f,avx512vl")]
6619 unsafe fn test_mm_cmpgt_epu64_mask() {
6620 let a = _mm_set_epi64x(1, 2);
6621 let b = _mm_set1_epi64x(1);
6622 let r = _mm_cmpgt_epu64_mask(a, b);
6623 assert_eq!(r, 0b00000001);
6624 }
6625
6626 #[simd_test(enable = "avx512f,avx512vl")]
6627 unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6628 let a = _mm_set_epi64x(1, 2);
6629 let b = _mm_set1_epi64x(1);
6630 let mask = 0b11111111;
6631 let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6632 assert_eq!(r, 0b00000001);
6633 }
6634
6635 #[simd_test(enable = "avx512f")]
6636 unsafe fn test_mm512_cmple_epu64_mask() {
6637 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6638 let b = _mm512_set1_epi64(-1);
6639 assert_eq!(
6640 _mm512_cmple_epu64_mask(a, b),
6641 !_mm512_cmpgt_epu64_mask(a, b)
6642 )
6643 }
6644
6645 #[simd_test(enable = "avx512f")]
6646 unsafe fn test_mm512_mask_cmple_epu64_mask() {
6647 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6648 let b = _mm512_set1_epi64(-1);
6649 let mask = 0b01111010;
6650 assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6651 }
6652
6653 #[simd_test(enable = "avx512f,avx512vl")]
6654 unsafe fn test_mm256_cmple_epu64_mask() {
6655 let a = _mm256_set_epi64x(0, 1, 2, 1);
6656 let b = _mm256_set1_epi64x(1);
6657 let r = _mm256_cmple_epu64_mask(a, b);
6658 assert_eq!(r, 0b00001101)
6659 }
6660
6661 #[simd_test(enable = "avx512f,avx512vl")]
6662 unsafe fn test_mm256_mask_cmple_epu64_mask() {
6663 let a = _mm256_set_epi64x(0, 1, 2, 1);
6664 let b = _mm256_set1_epi64x(1);
6665 let mask = 0b11111111;
6666 let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6667 assert_eq!(r, 0b00001101)
6668 }
6669
6670 #[simd_test(enable = "avx512f,avx512vl")]
6671 unsafe fn test_mm_cmple_epu64_mask() {
6672 let a = _mm_set_epi64x(0, 1);
6673 let b = _mm_set1_epi64x(1);
6674 let r = _mm_cmple_epu64_mask(a, b);
6675 assert_eq!(r, 0b00000011)
6676 }
6677
6678 #[simd_test(enable = "avx512f,avx512vl")]
6679 unsafe fn test_mm_mask_cmple_epu64_mask() {
6680 let a = _mm_set_epi64x(0, 1);
6681 let b = _mm_set1_epi64x(1);
6682 let mask = 0b11111111;
6683 let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6684 assert_eq!(r, 0b00000011)
6685 }
6686
6687 #[simd_test(enable = "avx512f")]
6688 unsafe fn test_mm512_cmpge_epu64_mask() {
6689 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6690 let b = _mm512_set1_epi64(-1);
6691 assert_eq!(
6692 _mm512_cmpge_epu64_mask(a, b),
6693 !_mm512_cmplt_epu64_mask(a, b)
6694 );
6695 }
6696
6697 #[simd_test(enable = "avx512f")]
6698 unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6699 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6700 let b = _mm512_set1_epi64(-1);
6701 let mask = 0b11111111;
6702 let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6703 assert_eq!(r, 0b00110000);
6704 }
6705
6706 #[simd_test(enable = "avx512f,avx512vl")]
6707 unsafe fn test_mm256_cmpge_epu64_mask() {
6708 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6709 let b = _mm256_set1_epi64x(1);
6710 let r = _mm256_cmpge_epu64_mask(a, b);
6711 assert_eq!(r, 0b00000111);
6712 }
6713
6714 #[simd_test(enable = "avx512f,avx512vl")]
6715 unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6716 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6717 let b = _mm256_set1_epi64x(1);
6718 let mask = 0b11111111;
6719 let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6720 assert_eq!(r, 0b00000111);
6721 }
6722
6723 #[simd_test(enable = "avx512f,avx512vl")]
6724 unsafe fn test_mm_cmpge_epu64_mask() {
6725 let a = _mm_set_epi64x(0, 1);
6726 let b = _mm_set1_epi64x(1);
6727 let r = _mm_cmpge_epu64_mask(a, b);
6728 assert_eq!(r, 0b00000001);
6729 }
6730
6731 #[simd_test(enable = "avx512f,avx512vl")]
6732 unsafe fn test_mm_mask_cmpge_epu64_mask() {
6733 let a = _mm_set_epi64x(0, 1);
6734 let b = _mm_set1_epi64x(1);
6735 let mask = 0b11111111;
6736 let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6737 assert_eq!(r, 0b00000001);
6738 }
6739
6740 #[simd_test(enable = "avx512f")]
6741 unsafe fn test_mm512_cmpeq_epu64_mask() {
6742 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6743 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6744 let m = _mm512_cmpeq_epu64_mask(b, a);
6745 assert_eq!(m, 0b11001111);
6746 }
6747
6748 #[simd_test(enable = "avx512f")]
6749 unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6750 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6751 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6752 let mask = 0b01111010;
6753 let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6754 assert_eq!(r, 0b01001010);
6755 }
6756
6757 #[simd_test(enable = "avx512f,avx512vl")]
6758 unsafe fn test_mm256_cmpeq_epu64_mask() {
6759 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6760 let b = _mm256_set_epi64x(0, 1, 13, 42);
6761 let m = _mm256_cmpeq_epu64_mask(b, a);
6762 assert_eq!(m, 0b00001100);
6763 }
6764
6765 #[simd_test(enable = "avx512f,avx512vl")]
6766 unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6767 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6768 let b = _mm256_set_epi64x(0, 1, 13, 42);
6769 let mask = 0b11111111;
6770 let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6771 assert_eq!(r, 0b00001100);
6772 }
6773
6774 #[simd_test(enable = "avx512f,avx512vl")]
6775 unsafe fn test_mm_cmpeq_epu64_mask() {
6776 let a = _mm_set_epi64x(0, 1);
6777 let b = _mm_set_epi64x(0, 1);
6778 let m = _mm_cmpeq_epu64_mask(b, a);
6779 assert_eq!(m, 0b00000011);
6780 }
6781
6782 #[simd_test(enable = "avx512f,avx512vl")]
6783 unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6784 let a = _mm_set_epi64x(0, 1);
6785 let b = _mm_set_epi64x(0, 1);
6786 let mask = 0b11111111;
6787 let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6788 assert_eq!(r, 0b00000011);
6789 }
6790
6791 #[simd_test(enable = "avx512f")]
6792 unsafe fn test_mm512_cmpneq_epu64_mask() {
6793 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6794 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6795 let m = _mm512_cmpneq_epu64_mask(b, a);
6796 assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6797 }
6798
6799 #[simd_test(enable = "avx512f")]
6800 unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6801 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6802 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6803 let mask = 0b01111010;
6804 let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6805 assert_eq!(r, 0b00110010);
6806 }
6807
6808 #[simd_test(enable = "avx512f,avx512vl")]
6809 unsafe fn test_mm256_cmpneq_epu64_mask() {
6810 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6811 let b = _mm256_set_epi64x(0, 1, 13, 42);
6812 let r = _mm256_cmpneq_epu64_mask(b, a);
6813 assert_eq!(r, 0b00000011);
6814 }
6815
6816 #[simd_test(enable = "avx512f,avx512vl")]
6817 unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
6818 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6819 let b = _mm256_set_epi64x(0, 1, 13, 42);
6820 let mask = 0b11111111;
6821 let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
6822 assert_eq!(r, 0b00000011);
6823 }
6824
6825 #[simd_test(enable = "avx512f,avx512vl")]
6826 unsafe fn test_mm_cmpneq_epu64_mask() {
6827 let a = _mm_set_epi64x(-1, u64::MAX as i64);
6828 let b = _mm_set_epi64x(13, 42);
6829 let r = _mm_cmpneq_epu64_mask(b, a);
6830 assert_eq!(r, 0b00000011);
6831 }
6832
6833 #[simd_test(enable = "avx512f,avx512vl")]
6834 unsafe fn test_mm_mask_cmpneq_epu64_mask() {
6835 let a = _mm_set_epi64x(-1, u64::MAX as i64);
6836 let b = _mm_set_epi64x(13, 42);
6837 let mask = 0b11111111;
6838 let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
6839 assert_eq!(r, 0b00000011);
6840 }
6841
6842 #[simd_test(enable = "avx512f")]
6843 unsafe fn test_mm512_cmp_epu64_mask() {
6844 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6845 let b = _mm512_set1_epi64(-1);
6846 let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6847 assert_eq!(m, 0b11001111);
6848 }
6849
6850 #[simd_test(enable = "avx512f")]
6851 unsafe fn test_mm512_mask_cmp_epu64_mask() {
6852 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6853 let b = _mm512_set1_epi64(-1);
6854 let mask = 0b01111010;
6855 let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6856 assert_eq!(r, 0b01001010);
6857 }
6858
6859 #[simd_test(enable = "avx512f,avx512vl")]
6860 unsafe fn test_mm256_cmp_epu64_mask() {
6861 let a = _mm256_set_epi64x(0, 1, -1, 100);
6862 let b = _mm256_set1_epi64x(1);
6863 let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6864 assert_eq!(m, 0b00001000);
6865 }
6866
6867 #[simd_test(enable = "avx512f,avx512vl")]
6868 unsafe fn test_mm256_mask_cmp_epu64_mask() {
6869 let a = _mm256_set_epi64x(0, 1, -1, 100);
6870 let b = _mm256_set1_epi64x(1);
6871 let mask = 0b11111111;
6872 let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6873 assert_eq!(r, 0b00001000);
6874 }
6875
6876 #[simd_test(enable = "avx512f,avx512vl")]
6877 unsafe fn test_mm_cmp_epu64_mask() {
6878 let a = _mm_set_epi64x(0, 1);
6879 let b = _mm_set1_epi64x(1);
6880 let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6881 assert_eq!(m, 0b00000010);
6882 }
6883
6884 #[simd_test(enable = "avx512f,avx512vl")]
6885 unsafe fn test_mm_mask_cmp_epu64_mask() {
6886 let a = _mm_set_epi64x(0, 1);
6887 let b = _mm_set1_epi64x(1);
6888 let mask = 0b11111111;
6889 let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6890 assert_eq!(r, 0b00000010);
6891 }
6892
6893 #[simd_test(enable = "avx512f")]
6894 unsafe fn test_mm512_cmplt_epi64_mask() {
6895 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6896 let b = _mm512_set1_epi64(-1);
6897 let m = _mm512_cmplt_epi64_mask(a, b);
6898 assert_eq!(m, 0b00000101);
6899 }
6900
6901 #[simd_test(enable = "avx512f")]
6902 unsafe fn test_mm512_mask_cmplt_epi64_mask() {
6903 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6904 let b = _mm512_set1_epi64(-1);
6905 let mask = 0b01100110;
6906 let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
6907 assert_eq!(r, 0b00000100);
6908 }
6909
6910 #[simd_test(enable = "avx512f,avx512vl")]
6911 unsafe fn test_mm256_cmplt_epi64_mask() {
6912 let a = _mm256_set_epi64x(0, 1, -1, -13);
6913 let b = _mm256_set1_epi64x(-1);
6914 let r = _mm256_cmplt_epi64_mask(a, b);
6915 assert_eq!(r, 0b00000001);
6916 }
6917
6918 #[simd_test(enable = "avx512f,avx512vl")]
6919 unsafe fn test_mm256_mask_cmplt_epi64_mask() {
6920 let a = _mm256_set_epi64x(0, 1, -1, -13);
6921 let b = _mm256_set1_epi64x(-1);
6922 let mask = 0b11111111;
6923 let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
6924 assert_eq!(r, 0b00000001);
6925 }
6926
6927 #[simd_test(enable = "avx512f,avx512vl")]
6928 unsafe fn test_mm_cmplt_epi64_mask() {
6929 let a = _mm_set_epi64x(-1, -13);
6930 let b = _mm_set1_epi64x(-1);
6931 let r = _mm_cmplt_epi64_mask(a, b);
6932 assert_eq!(r, 0b00000001);
6933 }
6934
6935 #[simd_test(enable = "avx512f,avx512vl")]
6936 unsafe fn test_mm_mask_cmplt_epi64_mask() {
6937 let a = _mm_set_epi64x(-1, -13);
6938 let b = _mm_set1_epi64x(-1);
6939 let mask = 0b11111111;
6940 let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
6941 assert_eq!(r, 0b00000001);
6942 }
6943
6944 #[simd_test(enable = "avx512f")]
6945 unsafe fn test_mm512_cmpgt_epi64_mask() {
6946 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6947 let b = _mm512_set1_epi64(-1);
6948 let m = _mm512_cmpgt_epi64_mask(b, a);
6949 assert_eq!(m, 0b00000101);
6950 }
6951
6952 #[simd_test(enable = "avx512f")]
6953 unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
6954 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
6955 let b = _mm512_set1_epi64(-1);
6956 let mask = 0b01100110;
6957 let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
6958 assert_eq!(r, 0b00000100);
6959 }
6960
6961 #[simd_test(enable = "avx512f,avx512vl")]
6962 unsafe fn test_mm256_cmpgt_epi64_mask() {
6963 let a = _mm256_set_epi64x(0, 1, -1, 13);
6964 let b = _mm256_set1_epi64x(-1);
6965 let r = _mm256_cmpgt_epi64_mask(a, b);
6966 assert_eq!(r, 0b00001101);
6967 }
6968
6969 #[simd_test(enable = "avx512f,avx512vl")]
6970 unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
6971 let a = _mm256_set_epi64x(0, 1, -1, 13);
6972 let b = _mm256_set1_epi64x(-1);
6973 let mask = 0b11111111;
6974 let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
6975 assert_eq!(r, 0b00001101);
6976 }
6977
6978 #[simd_test(enable = "avx512f,avx512vl")]
6979 unsafe fn test_mm_cmpgt_epi64_mask() {
6980 let a = _mm_set_epi64x(0, -1);
6981 let b = _mm_set1_epi64x(-1);
6982 let r = _mm_cmpgt_epi64_mask(a, b);
6983 assert_eq!(r, 0b00000010);
6984 }
6985
6986 #[simd_test(enable = "avx512f,avx512vl")]
6987 unsafe fn test_mm_mask_cmpgt_epi64_mask() {
6988 let a = _mm_set_epi64x(0, -1);
6989 let b = _mm_set1_epi64x(-1);
6990 let mask = 0b11111111;
6991 let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
6992 assert_eq!(r, 0b00000010);
6993 }
6994
6995 #[simd_test(enable = "avx512f")]
6996 unsafe fn test_mm512_cmple_epi64_mask() {
6997 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6998 let b = _mm512_set1_epi64(-1);
6999 assert_eq!(
7000 _mm512_cmple_epi64_mask(a, b),
7001 !_mm512_cmpgt_epi64_mask(a, b)
7002 )
7003 }
7004
7005 #[simd_test(enable = "avx512f")]
7006 unsafe fn test_mm512_mask_cmple_epi64_mask() {
7007 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7008 let b = _mm512_set1_epi64(-1);
7009 let mask = 0b01111010;
7010 assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7011 }
7012
7013 #[simd_test(enable = "avx512f,avx512vl")]
7014 unsafe fn test_mm256_cmple_epi64_mask() {
7015 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7016 let b = _mm256_set1_epi64x(-1);
7017 let r = _mm256_cmple_epi64_mask(a, b);
7018 assert_eq!(r, 0b00000010)
7019 }
7020
7021 #[simd_test(enable = "avx512f,avx512vl")]
7022 unsafe fn test_mm256_mask_cmple_epi64_mask() {
7023 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7024 let b = _mm256_set1_epi64x(-1);
7025 let mask = 0b11111111;
7026 let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7027 assert_eq!(r, 0b00000010)
7028 }
7029
7030 #[simd_test(enable = "avx512f,avx512vl")]
7031 unsafe fn test_mm_cmple_epi64_mask() {
7032 let a = _mm_set_epi64x(0, 1);
7033 let b = _mm_set1_epi64x(1);
7034 let r = _mm_cmple_epi64_mask(a, b);
7035 assert_eq!(r, 0b00000011)
7036 }
7037
7038 #[simd_test(enable = "avx512f,avx512vl")]
7039 unsafe fn test_mm_mask_cmple_epi64_mask() {
7040 let a = _mm_set_epi64x(0, 1);
7041 let b = _mm_set1_epi64x(1);
7042 let mask = 0b11111111;
7043 let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7044 assert_eq!(r, 0b00000011)
7045 }
7046
7047 #[simd_test(enable = "avx512f")]
7048 unsafe fn test_mm512_cmpge_epi64_mask() {
7049 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7050 let b = _mm512_set1_epi64(-1);
7051 assert_eq!(
7052 _mm512_cmpge_epi64_mask(a, b),
7053 !_mm512_cmplt_epi64_mask(a, b)
7054 )
7055 }
7056
7057 #[simd_test(enable = "avx512f")]
7058 unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7059 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7060 let b = _mm512_set1_epi64(-1);
7061 let mask = 0b11111111;
7062 let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7063 assert_eq!(r, 0b11111010);
7064 }
7065
7066 #[simd_test(enable = "avx512f,avx512vl")]
7067 unsafe fn test_mm256_cmpge_epi64_mask() {
7068 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7069 let b = _mm256_set1_epi64x(-1);
7070 let r = _mm256_cmpge_epi64_mask(a, b);
7071 assert_eq!(r, 0b00001111);
7072 }
7073
7074 #[simd_test(enable = "avx512f,avx512vl")]
7075 unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7076 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7077 let b = _mm256_set1_epi64x(-1);
7078 let mask = 0b11111111;
7079 let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7080 assert_eq!(r, 0b00001111);
7081 }
7082
7083 #[simd_test(enable = "avx512f,avx512vl")]
7084 unsafe fn test_mm_cmpge_epi64_mask() {
7085 let a = _mm_set_epi64x(0, 1);
7086 let b = _mm_set1_epi64x(-1);
7087 let r = _mm_cmpge_epi64_mask(a, b);
7088 assert_eq!(r, 0b00000011);
7089 }
7090
7091 #[simd_test(enable = "avx512f,avx512vl")]
7092 unsafe fn test_mm_mask_cmpge_epi64_mask() {
7093 let a = _mm_set_epi64x(0, 1);
7094 let b = _mm_set1_epi64x(-1);
7095 let mask = 0b11111111;
7096 let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7097 assert_eq!(r, 0b00000011);
7098 }
7099
7100 #[simd_test(enable = "avx512f")]
7101 unsafe fn test_mm512_cmpeq_epi64_mask() {
7102 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7103 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7104 let m = _mm512_cmpeq_epi64_mask(b, a);
7105 assert_eq!(m, 0b11001111);
7106 }
7107
7108 #[simd_test(enable = "avx512f")]
7109 unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7110 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7111 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7112 let mask = 0b01111010;
7113 let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7114 assert_eq!(r, 0b01001010);
7115 }
7116
7117 #[simd_test(enable = "avx512f,avx512vl")]
7118 unsafe fn test_mm256_cmpeq_epi64_mask() {
7119 let a = _mm256_set_epi64x(0, 1, -1, 13);
7120 let b = _mm256_set_epi64x(0, 1, 13, 42);
7121 let m = _mm256_cmpeq_epi64_mask(b, a);
7122 assert_eq!(m, 0b00001100);
7123 }
7124
7125 #[simd_test(enable = "avx512f,avx512vl")]
7126 unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7127 let a = _mm256_set_epi64x(0, 1, -1, 13);
7128 let b = _mm256_set_epi64x(0, 1, 13, 42);
7129 let mask = 0b11111111;
7130 let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7131 assert_eq!(r, 0b00001100);
7132 }
7133
7134 #[simd_test(enable = "avx512f,avx512vl")]
7135 unsafe fn test_mm_cmpeq_epi64_mask() {
7136 let a = _mm_set_epi64x(0, 1);
7137 let b = _mm_set_epi64x(0, 1);
7138 let m = _mm_cmpeq_epi64_mask(b, a);
7139 assert_eq!(m, 0b00000011);
7140 }
7141
7142 #[simd_test(enable = "avx512f,avx512vl")]
7143 unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7144 let a = _mm_set_epi64x(0, 1);
7145 let b = _mm_set_epi64x(0, 1);
7146 let mask = 0b11111111;
7147 let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7148 assert_eq!(r, 0b00000011);
7149 }
7150
7151 #[simd_test(enable = "avx512f")]
7152 unsafe fn test_mm512_set_epi64() {
7153 let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7154 assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7155 }
7156
7157 #[simd_test(enable = "avx512f")]
7158 unsafe fn test_mm512_setr_epi64() {
7159 let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7160 assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7161 }
7162
7163 unsafe fn test_mm512_cmpneq_epi64_mask() {
7164 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7165 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7166 let m = _mm512_cmpneq_epi64_mask(b, a);
7167 assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7168 }
7169
7170 #[simd_test(enable = "avx512f")]
7171 unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7172 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7173 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7174 let mask = 0b01111010;
7175 let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7176 assert_eq!(r, 0b00110010)
7177 }
7178
7179 #[simd_test(enable = "avx512f,avx512vl")]
7180 unsafe fn test_mm256_cmpneq_epi64_mask() {
7181 let a = _mm256_set_epi64x(0, 1, -1, 13);
7182 let b = _mm256_set_epi64x(0, 1, 13, 42);
7183 let r = _mm256_cmpneq_epi64_mask(b, a);
7184 assert_eq!(r, 0b00000011)
7185 }
7186
7187 #[simd_test(enable = "avx512f,avx512vl")]
7188 unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7189 let a = _mm256_set_epi64x(0, 1, -1, 13);
7190 let b = _mm256_set_epi64x(0, 1, 13, 42);
7191 let mask = 0b11111111;
7192 let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7193 assert_eq!(r, 0b00000011)
7194 }
7195
7196 #[simd_test(enable = "avx512f,avx512vl")]
7197 unsafe fn test_mm_cmpneq_epi64_mask() {
7198 let a = _mm_set_epi64x(-1, 13);
7199 let b = _mm_set_epi64x(13, 42);
7200 let r = _mm_cmpneq_epi64_mask(b, a);
7201 assert_eq!(r, 0b00000011)
7202 }
7203
7204 #[simd_test(enable = "avx512f,avx512vl")]
7205 unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7206 let a = _mm_set_epi64x(-1, 13);
7207 let b = _mm_set_epi64x(13, 42);
7208 let mask = 0b11111111;
7209 let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7210 assert_eq!(r, 0b00000011)
7211 }
7212
7213 #[simd_test(enable = "avx512f")]
7214 unsafe fn test_mm512_cmp_epi64_mask() {
7215 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7216 let b = _mm512_set1_epi64(-1);
7217 let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7218 assert_eq!(m, 0b00000101);
7219 }
7220
7221 #[simd_test(enable = "avx512f")]
7222 unsafe fn test_mm512_mask_cmp_epi64_mask() {
7223 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7224 let b = _mm512_set1_epi64(-1);
7225 let mask = 0b01100110;
7226 let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7227 assert_eq!(r, 0b00000100);
7228 }
7229
7230 #[simd_test(enable = "avx512f,avx512vl")]
7231 unsafe fn test_mm256_cmp_epi64_mask() {
7232 let a = _mm256_set_epi64x(0, 1, -1, 13);
7233 let b = _mm256_set1_epi64x(1);
7234 let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7235 assert_eq!(m, 0b00001010);
7236 }
7237
7238 #[simd_test(enable = "avx512f,avx512vl")]
7239 unsafe fn test_mm256_mask_cmp_epi64_mask() {
7240 let a = _mm256_set_epi64x(0, 1, -1, 13);
7241 let b = _mm256_set1_epi64x(1);
7242 let mask = 0b11111111;
7243 let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7244 assert_eq!(r, 0b00001010);
7245 }
7246
7247 #[simd_test(enable = "avx512f,avx512vl")]
7248 unsafe fn test_mm_cmp_epi64_mask() {
7249 let a = _mm_set_epi64x(0, 1);
7250 let b = _mm_set1_epi64x(1);
7251 let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7252 assert_eq!(m, 0b00000010);
7253 }
7254
7255 #[simd_test(enable = "avx512f,avx512vl")]
7256 unsafe fn test_mm_mask_cmp_epi64_mask() {
7257 let a = _mm_set_epi64x(0, 1);
7258 let b = _mm_set1_epi64x(1);
7259 let mask = 0b11111111;
7260 let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7261 assert_eq!(r, 0b00000010);
7262 }
7263
7264 #[simd_test(enable = "avx512f")]
7265 unsafe fn test_mm512_i32gather_pd() {
7266 let mut arr = [0f64; 128];
7267 for i in 0..128 {
7268 arr[i] = i as f64;
7269 }
7270 // A multiplier of 8 is word-addressing
7271 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7272 let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr() as *const u8);
7273 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7274 }
7275
7276 #[simd_test(enable = "avx512f")]
7277 unsafe fn test_mm512_mask_i32gather_pd() {
7278 let mut arr = [0f64; 128];
7279 for i in 0..128 {
7280 arr[i] = i as f64;
7281 }
7282 let src = _mm512_set1_pd(2.);
7283 let mask = 0b10101010;
7284 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7285 // A multiplier of 8 is word-addressing
7286 let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7287 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7288 }
7289
7290 #[simd_test(enable = "avx512f")]
7291 unsafe fn test_mm512_i64gather_pd() {
7292 let mut arr = [0f64; 128];
7293 for i in 0..128 {
7294 arr[i] = i as f64;
7295 }
7296 // A multiplier of 8 is word-addressing
7297 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7298 let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr() as *const u8);
7299 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7300 }
7301
7302 #[simd_test(enable = "avx512f")]
7303 unsafe fn test_mm512_mask_i64gather_pd() {
7304 let mut arr = [0f64; 128];
7305 for i in 0..128 {
7306 arr[i] = i as f64;
7307 }
7308 let src = _mm512_set1_pd(2.);
7309 let mask = 0b10101010;
7310 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7311 // A multiplier of 8 is word-addressing
7312 let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7313 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7314 }
7315
7316 #[simd_test(enable = "avx512f")]
7317 unsafe fn test_mm512_i64gather_ps() {
7318 let mut arr = [0f32; 128];
7319 for i in 0..128 {
7320 arr[i] = i as f32;
7321 }
7322 // A multiplier of 4 is word-addressing
7323 #[rustfmt::skip]
7324 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7325 let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr() as *const u8);
7326 assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7327 }
7328
7329 #[simd_test(enable = "avx512f")]
7330 unsafe fn test_mm512_mask_i64gather_ps() {
7331 let mut arr = [0f32; 128];
7332 for i in 0..128 {
7333 arr[i] = i as f32;
7334 }
7335 let src = _mm256_set1_ps(2.);
7336 let mask = 0b10101010;
7337 #[rustfmt::skip]
7338 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7339 // A multiplier of 4 is word-addressing
7340 let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr() as *const u8);
7341 assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7342 }
7343
7344 #[simd_test(enable = "avx512f")]
7345 unsafe fn test_mm512_i32gather_epi64() {
7346 let mut arr = [0i64; 128];
7347 for i in 0..128i64 {
7348 arr[i as usize] = i;
7349 }
7350 // A multiplier of 8 is word-addressing
7351 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7352 let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7353 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7354 }
7355
7356 #[simd_test(enable = "avx512f")]
7357 unsafe fn test_mm512_mask_i32gather_epi64() {
7358 let mut arr = [0i64; 128];
7359 for i in 0..128i64 {
7360 arr[i as usize] = i;
7361 }
7362 let src = _mm512_set1_epi64(2);
7363 let mask = 0b10101010;
7364 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7365 // A multiplier of 8 is word-addressing
7366 let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7367 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7368 }
7369
7370 #[simd_test(enable = "avx512f")]
7371 unsafe fn test_mm512_i64gather_epi64() {
7372 let mut arr = [0i64; 128];
7373 for i in 0..128i64 {
7374 arr[i as usize] = i;
7375 }
7376 // A multiplier of 8 is word-addressing
7377 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7378 let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7379 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7380 }
7381
7382 #[simd_test(enable = "avx512f")]
7383 unsafe fn test_mm512_mask_i64gather_epi64() {
7384 let mut arr = [0i64; 128];
7385 for i in 0..128i64 {
7386 arr[i as usize] = i;
7387 }
7388 let src = _mm512_set1_epi64(2);
7389 let mask = 0b10101010;
7390 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7391 // A multiplier of 8 is word-addressing
7392 let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7393 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7394 }
7395
7396 #[simd_test(enable = "avx512f")]
7397 unsafe fn test_mm512_i64gather_epi32() {
7398 let mut arr = [0i64; 128];
7399 for i in 0..128i64 {
7400 arr[i as usize] = i;
7401 }
7402 // A multiplier of 8 is word-addressing
7403 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7404 let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const u8);
7405 assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7406 }
7407
7408 #[simd_test(enable = "avx512f")]
7409 unsafe fn test_mm512_mask_i64gather_epi32() {
7410 let mut arr = [0i64; 128];
7411 for i in 0..128i64 {
7412 arr[i as usize] = i;
7413 }
7414 let src = _mm256_set1_epi32(2);
7415 let mask = 0b10101010;
7416 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7417 // A multiplier of 8 is word-addressing
7418 let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const u8);
7419 assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7420 }
7421
7422 #[simd_test(enable = "avx512f")]
7423 unsafe fn test_mm512_i32scatter_pd() {
7424 let mut arr = [0f64; 128];
7425 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7426 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7427 // A multiplier of 8 is word-addressing
7428 _mm512_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7429 let mut expected = [0f64; 128];
7430 for i in 0..8 {
7431 expected[i * 16] = (i + 1) as f64;
7432 }
7433 assert_eq!(&arr[..], &expected[..],);
7434 }
7435
7436 #[simd_test(enable = "avx512f")]
7437 unsafe fn test_mm512_mask_i32scatter_pd() {
7438 let mut arr = [0f64; 128];
7439 let mask = 0b10101010;
7440 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7441 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7442 // A multiplier of 8 is word-addressing
7443 _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7444 let mut expected = [0f64; 128];
7445 for i in 0..4 {
7446 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7447 }
7448 assert_eq!(&arr[..], &expected[..],);
7449 }
7450
7451 #[simd_test(enable = "avx512f")]
7452 unsafe fn test_mm512_i64scatter_pd() {
7453 let mut arr = [0f64; 128];
7454 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7455 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7456 // A multiplier of 8 is word-addressing
7457 _mm512_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7458 let mut expected = [0f64; 128];
7459 for i in 0..8 {
7460 expected[i * 16] = (i + 1) as f64;
7461 }
7462 assert_eq!(&arr[..], &expected[..],);
7463 }
7464
7465 #[simd_test(enable = "avx512f")]
7466 unsafe fn test_mm512_mask_i64scatter_pd() {
7467 let mut arr = [0f64; 128];
7468 let mask = 0b10101010;
7469 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7470 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7471 // A multiplier of 8 is word-addressing
7472 _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7473 let mut expected = [0f64; 128];
7474 for i in 0..4 {
7475 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7476 }
7477 assert_eq!(&arr[..], &expected[..],);
7478 }
7479
7480 #[simd_test(enable = "avx512f")]
7481 unsafe fn test_mm512_i64scatter_ps() {
7482 let mut arr = [0f32; 128];
7483 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7484 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7485 // A multiplier of 4 is word-addressing
7486 _mm512_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7487 let mut expected = [0f32; 128];
7488 for i in 0..8 {
7489 expected[i * 16] = (i + 1) as f32;
7490 }
7491 assert_eq!(&arr[..], &expected[..],);
7492 }
7493
7494 #[simd_test(enable = "avx512f")]
7495 unsafe fn test_mm512_mask_i64scatter_ps() {
7496 let mut arr = [0f32; 128];
7497 let mask = 0b10101010;
7498 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7499 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7500 // A multiplier of 4 is word-addressing
7501 _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7502 let mut expected = [0f32; 128];
7503 for i in 0..4 {
7504 expected[i * 32 + 16] = 2. * (i + 1) as f32;
7505 }
7506 assert_eq!(&arr[..], &expected[..],);
7507 }
7508
7509 #[simd_test(enable = "avx512f")]
7510 unsafe fn test_mm512_i32scatter_epi64() {
7511 let mut arr = [0i64; 128];
7512 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7513 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7514 // A multiplier of 8 is word-addressing
7515 _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7516 let mut expected = [0i64; 128];
7517 for i in 0..8 {
7518 expected[i * 16] = (i + 1) as i64;
7519 }
7520 assert_eq!(&arr[..], &expected[..],);
7521 }
7522
7523 #[simd_test(enable = "avx512f")]
7524 unsafe fn test_mm512_mask_i32scatter_epi64() {
7525 let mut arr = [0i64; 128];
7526 let mask = 0b10101010;
7527 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7528 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7529 // A multiplier of 8 is word-addressing
7530 _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7531 let mut expected = [0i64; 128];
7532 for i in 0..4 {
7533 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7534 }
7535 assert_eq!(&arr[..], &expected[..],);
7536 }
7537
7538 #[simd_test(enable = "avx512f,avx512vl")]
7539 unsafe fn test_mm256_i32scatter_epi64() {
7540 let mut arr = [0i64; 64];
7541 let index = _mm_setr_epi32(0, 16, 32, 48);
7542 let src = _mm256_setr_epi64x(1, 2, 3, 4);
7543 // A multiplier of 8 is word-addressing
7544 _mm256_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7545 let mut expected = [0i64; 64];
7546 for i in 0..4 {
7547 expected[i * 16] = (i + 1) as i64;
7548 }
7549 assert_eq!(&arr[..], &expected[..],);
7550 }
7551
7552 #[simd_test(enable = "avx512f")]
7553 unsafe fn test_mm512_i64scatter_epi64() {
7554 let mut arr = [0i64; 128];
7555 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7556 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7557 // A multiplier of 8 is word-addressing
7558 _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7559 let mut expected = [0i64; 128];
7560 for i in 0..8 {
7561 expected[i * 16] = (i + 1) as i64;
7562 }
7563 assert_eq!(&arr[..], &expected[..],);
7564 }
7565
7566 #[simd_test(enable = "avx512f")]
7567 unsafe fn test_mm512_mask_i64scatter_epi64() {
7568 let mut arr = [0i64; 128];
7569 let mask = 0b10101010;
7570 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7571 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7572 // A multiplier of 8 is word-addressing
7573 _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7574 let mut expected = [0i64; 128];
7575 for i in 0..4 {
7576 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7577 }
7578 assert_eq!(&arr[..], &expected[..],);
7579 }
7580
7581 #[simd_test(enable = "avx512f")]
7582 unsafe fn test_mm512_i64scatter_epi32() {
7583 let mut arr = [0i32; 128];
7584 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7585 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7586 // A multiplier of 4 is word-addressing
7587 _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7588 let mut expected = [0i32; 128];
7589 for i in 0..8 {
7590 expected[i * 16] = (i + 1) as i32;
7591 }
7592 assert_eq!(&arr[..], &expected[..],);
7593 }
7594
7595 #[simd_test(enable = "avx512f")]
7596 unsafe fn test_mm512_mask_i64scatter_epi32() {
7597 let mut arr = [0i32; 128];
7598 let mask = 0b10101010;
7599 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7600 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7601 // A multiplier of 4 is word-addressing
7602 _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7603 let mut expected = [0i32; 128];
7604 for i in 0..4 {
7605 expected[i * 32 + 16] = 2 * (i + 1) as i32;
7606 }
7607 assert_eq!(&arr[..], &expected[..],);
7608 }
7609
7610 #[simd_test(enable = "avx512f")]
7611 unsafe fn test_mm512_rol_epi64() {
7612 #[rustfmt::skip]
7613 let a = _mm512_set_epi64(
7614 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7615 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7616 );
7617 let r = _mm512_rol_epi64::<1>(a);
7618 #[rustfmt::skip]
7619 let e = _mm512_set_epi64(
7620 1 << 0, 1 << 33, 1 << 33, 1 << 33,
7621 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7622 );
7623 assert_eq_m512i(r, e);
7624 }
7625
7626 #[simd_test(enable = "avx512f")]
7627 unsafe fn test_mm512_mask_rol_epi64() {
7628 #[rustfmt::skip]
7629 let a = _mm512_set_epi64(
7630 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7631 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7632 );
7633 let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
7634 assert_eq_m512i(r, a);
7635 let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
7636 #[rustfmt::skip]
7637 let e = _mm512_set_epi64(
7638 1 << 0, 1 << 33, 1 << 33, 1 << 33,
7639 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7640 );
7641 assert_eq_m512i(r, e);
7642 }
7643
7644 #[simd_test(enable = "avx512f")]
7645 unsafe fn test_mm512_maskz_rol_epi64() {
7646 #[rustfmt::skip]
7647 let a = _mm512_set_epi64(
7648 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7649 1 << 32, 1 << 32, 1 << 32, 1 << 63,
7650 );
7651 let r = _mm512_maskz_rol_epi64::<1>(0, a);
7652 assert_eq_m512i(r, _mm512_setzero_si512());
7653 let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
7654 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
7655 assert_eq_m512i(r, e);
7656 }
7657
7658 #[simd_test(enable = "avx512f,avx512vl")]
7659 unsafe fn test_mm256_rol_epi64() {
7660 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7661 let r = _mm256_rol_epi64::<1>(a);
7662 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
7663 assert_eq_m256i(r, e);
7664 }
7665
7666 #[simd_test(enable = "avx512f,avx512vl")]
7667 unsafe fn test_mm256_mask_rol_epi64() {
7668 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7669 let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
7670 assert_eq_m256i(r, a);
7671 let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
7672 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
7673 assert_eq_m256i(r, e);
7674 }
7675
7676 #[simd_test(enable = "avx512f,avx512vl")]
7677 unsafe fn test_mm256_maskz_rol_epi64() {
7678 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7679 let r = _mm256_maskz_rol_epi64::<1>(0, a);
7680 assert_eq_m256i(r, _mm256_setzero_si256());
7681 let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
7682 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
7683 assert_eq_m256i(r, e);
7684 }
7685
7686 #[simd_test(enable = "avx512f,avx512vl")]
7687 unsafe fn test_mm_rol_epi64() {
7688 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7689 let r = _mm_rol_epi64::<1>(a);
7690 let e = _mm_set_epi64x(1 << 0, 1 << 33);
7691 assert_eq_m128i(r, e);
7692 }
7693
7694 #[simd_test(enable = "avx512f,avx512vl")]
7695 unsafe fn test_mm_mask_rol_epi64() {
7696 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7697 let r = _mm_mask_rol_epi64::<1>(a, 0, a);
7698 assert_eq_m128i(r, a);
7699 let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
7700 let e = _mm_set_epi64x(1 << 0, 1 << 33);
7701 assert_eq_m128i(r, e);
7702 }
7703
7704 #[simd_test(enable = "avx512f,avx512vl")]
7705 unsafe fn test_mm_maskz_rol_epi64() {
7706 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7707 let r = _mm_maskz_rol_epi64::<1>(0, a);
7708 assert_eq_m128i(r, _mm_setzero_si128());
7709 let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
7710 let e = _mm_set_epi64x(1 << 0, 1 << 33);
7711 assert_eq_m128i(r, e);
7712 }
7713
7714 #[simd_test(enable = "avx512f")]
7715 unsafe fn test_mm512_ror_epi64() {
7716 #[rustfmt::skip]
7717 let a = _mm512_set_epi64(
7718 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7719 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7720 );
7721 let r = _mm512_ror_epi64::<1>(a);
7722 #[rustfmt::skip]
7723 let e = _mm512_set_epi64(
7724 1 << 63, 1 << 31, 1 << 31, 1 << 31,
7725 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7726 );
7727 assert_eq_m512i(r, e);
7728 }
7729
7730 #[simd_test(enable = "avx512f")]
7731 unsafe fn test_mm512_mask_ror_epi64() {
7732 #[rustfmt::skip]
7733 let a = _mm512_set_epi64(
7734 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7735 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7736 );
7737 let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
7738 assert_eq_m512i(r, a);
7739 let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
7740 #[rustfmt::skip]
7741 let e = _mm512_set_epi64(
7742 1 << 63, 1 << 31, 1 << 31, 1 << 31,
7743 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7744 );
7745 assert_eq_m512i(r, e);
7746 }
7747
7748 #[simd_test(enable = "avx512f")]
7749 unsafe fn test_mm512_maskz_ror_epi64() {
7750 #[rustfmt::skip]
7751 let a = _mm512_set_epi64(
7752 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7753 1 << 32, 1 << 32, 1 << 32, 1 << 0,
7754 );
7755 let r = _mm512_maskz_ror_epi64::<1>(0, a);
7756 assert_eq_m512i(r, _mm512_setzero_si512());
7757 let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
7758 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
7759 assert_eq_m512i(r, e);
7760 }
7761
7762 #[simd_test(enable = "avx512f,avx512vl")]
7763 unsafe fn test_mm256_ror_epi64() {
7764 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
7765 let r = _mm256_ror_epi64::<1>(a);
7766 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
7767 assert_eq_m256i(r, e);
7768 }
7769
7770 #[simd_test(enable = "avx512f,avx512vl")]
7771 unsafe fn test_mm256_mask_ror_epi64() {
7772 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
7773 let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
7774 assert_eq_m256i(r, a);
7775 let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
7776 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
7777 assert_eq_m256i(r, e);
7778 }
7779
7780 #[simd_test(enable = "avx512f,avx512vl")]
7781 unsafe fn test_mm256_maskz_ror_epi64() {
7782 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
7783 let r = _mm256_maskz_ror_epi64::<1>(0, a);
7784 assert_eq_m256i(r, _mm256_setzero_si256());
7785 let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
7786 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
7787 assert_eq_m256i(r, e);
7788 }
7789
7790 #[simd_test(enable = "avx512f,avx512vl")]
7791 unsafe fn test_mm_ror_epi64() {
7792 let a = _mm_set_epi64x(1 << 0, 1 << 32);
7793 let r = _mm_ror_epi64::<1>(a);
7794 let e = _mm_set_epi64x(1 << 63, 1 << 31);
7795 assert_eq_m128i(r, e);
7796 }
7797
7798 #[simd_test(enable = "avx512f,avx512vl")]
7799 unsafe fn test_mm_mask_ror_epi64() {
7800 let a = _mm_set_epi64x(1 << 0, 1 << 32);
7801 let r = _mm_mask_ror_epi64::<1>(a, 0, a);
7802 assert_eq_m128i(r, a);
7803 let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
7804 let e = _mm_set_epi64x(1 << 63, 1 << 31);
7805 assert_eq_m128i(r, e);
7806 }
7807
7808 #[simd_test(enable = "avx512f,avx512vl")]
7809 unsafe fn test_mm_maskz_ror_epi64() {
7810 let a = _mm_set_epi64x(1 << 0, 1 << 32);
7811 let r = _mm_maskz_ror_epi64::<1>(0, a);
7812 assert_eq_m128i(r, _mm_setzero_si128());
7813 let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
7814 let e = _mm_set_epi64x(1 << 63, 1 << 31);
7815 assert_eq_m128i(r, e);
7816 }
7817
7818 #[simd_test(enable = "avx512f")]
7819 unsafe fn test_mm512_slli_epi64() {
7820 #[rustfmt::skip]
7821 let a = _mm512_set_epi64(
7822 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7823 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7824 );
7825 let r = _mm512_slli_epi64::<1>(a);
7826 #[rustfmt::skip]
7827 let e = _mm512_set_epi64(
7828 0, 1 << 33, 1 << 33, 1 << 33,
7829 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7830 );
7831 assert_eq_m512i(r, e);
7832 }
7833
7834 #[simd_test(enable = "avx512f")]
7835 unsafe fn test_mm512_mask_slli_epi64() {
7836 #[rustfmt::skip]
7837 let a = _mm512_set_epi64(
7838 1 << 63, 1 << 32, 1 << 32, 1 << 32,
7839 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7840 );
7841 let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
7842 assert_eq_m512i(r, a);
7843 let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
7844 #[rustfmt::skip]
7845 let e = _mm512_set_epi64(
7846 0, 1 << 33, 1 << 33, 1 << 33,
7847 1 << 33, 1 << 33, 1 << 33, 1 << 33,
7848 );
7849 assert_eq_m512i(r, e);
7850 }
7851
7852 #[simd_test(enable = "avx512f")]
7853 unsafe fn test_mm512_maskz_slli_epi64() {
7854 #[rustfmt::skip]
7855 let a = _mm512_set_epi64(
7856 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7857 1 << 32, 1 << 32, 1 << 32, 1 << 63,
7858 );
7859 let r = _mm512_maskz_slli_epi64::<1>(0, a);
7860 assert_eq_m512i(r, _mm512_setzero_si512());
7861 let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
7862 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
7863 assert_eq_m512i(r, e);
7864 }
7865
7866 #[simd_test(enable = "avx512f,avx512vl")]
7867 unsafe fn test_mm256_mask_slli_epi64() {
7868 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7869 let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
7870 assert_eq_m256i(r, a);
7871 let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
7872 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
7873 assert_eq_m256i(r, e);
7874 }
7875
7876 #[simd_test(enable = "avx512f,avx512vl")]
7877 unsafe fn test_mm256_maskz_slli_epi64() {
7878 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
7879 let r = _mm256_maskz_slli_epi64::<1>(0, a);
7880 assert_eq_m256i(r, _mm256_setzero_si256());
7881 let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
7882 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
7883 assert_eq_m256i(r, e);
7884 }
7885
7886 #[simd_test(enable = "avx512f,avx512vl")]
7887 unsafe fn test_mm_mask_slli_epi64() {
7888 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7889 let r = _mm_mask_slli_epi64::<1>(a, 0, a);
7890 assert_eq_m128i(r, a);
7891 let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
7892 let e = _mm_set_epi64x(0, 1 << 33);
7893 assert_eq_m128i(r, e);
7894 }
7895
7896 #[simd_test(enable = "avx512f,avx512vl")]
7897 unsafe fn test_mm_maskz_slli_epi64() {
7898 let a = _mm_set_epi64x(1 << 63, 1 << 32);
7899 let r = _mm_maskz_slli_epi64::<1>(0, a);
7900 assert_eq_m128i(r, _mm_setzero_si128());
7901 let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
7902 let e = _mm_set_epi64x(0, 1 << 33);
7903 assert_eq_m128i(r, e);
7904 }
7905
7906 #[simd_test(enable = "avx512f")]
7907 unsafe fn test_mm512_srli_epi64() {
7908 #[rustfmt::skip]
7909 let a = _mm512_set_epi64(
7910 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7911 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7912 );
7913 let r = _mm512_srli_epi64::<1>(a);
7914 #[rustfmt::skip]
7915 let e = _mm512_set_epi64(
7916 0, 1 << 31, 1 << 31, 1 << 31,
7917 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7918 );
7919 assert_eq_m512i(r, e);
7920 }
7921
7922 #[simd_test(enable = "avx512f")]
7923 unsafe fn test_mm512_mask_srli_epi64() {
7924 #[rustfmt::skip]
7925 let a = _mm512_set_epi64(
7926 1 << 0, 1 << 32, 1 << 32, 1 << 32,
7927 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7928 );
7929 let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
7930 assert_eq_m512i(r, a);
7931 let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
7932 #[rustfmt::skip]
7933 let e = _mm512_set_epi64(
7934 0, 1 << 31, 1 << 31, 1 << 31,
7935 1 << 31, 1 << 31, 1 << 31, 1 << 31,
7936 );
7937 assert_eq_m512i(r, e);
7938 }
7939
7940 #[simd_test(enable = "avx512f")]
7941 unsafe fn test_mm512_maskz_srli_epi64() {
7942 #[rustfmt::skip]
7943 let a = _mm512_set_epi64(
7944 1 << 32, 1 << 32, 1 << 32, 1 << 32,
7945 1 << 32, 1 << 32, 1 << 32, 1 << 0,
7946 );
7947 let r = _mm512_maskz_srli_epi64::<1>(0, a);
7948 assert_eq_m512i(r, _mm512_setzero_si512());
7949 let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
7950 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
7951 assert_eq_m512i(r, e);
7952 }
7953
7954 #[simd_test(enable = "avx512f,avx512vl")]
7955 unsafe fn test_mm256_mask_srli_epi64() {
7956 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
7957 let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
7958 assert_eq_m256i(r, a);
7959 let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
7960 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
7961 assert_eq_m256i(r, e);
7962 }
7963
7964 #[simd_test(enable = "avx512f,avx512vl")]
7965 unsafe fn test_mm256_maskz_srli_epi64() {
7966 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
7967 let r = _mm256_maskz_srli_epi64::<1>(0, a);
7968 assert_eq_m256i(r, _mm256_setzero_si256());
7969 let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
7970 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
7971 assert_eq_m256i(r, e);
7972 }
7973
7974 #[simd_test(enable = "avx512f,avx512vl")]
7975 unsafe fn test_mm_mask_srli_epi64() {
7976 let a = _mm_set_epi64x(1 << 5, 0);
7977 let r = _mm_mask_srli_epi64::<1>(a, 0, a);
7978 assert_eq_m128i(r, a);
7979 let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
7980 let e = _mm_set_epi64x(1 << 4, 0);
7981 assert_eq_m128i(r, e);
7982 }
7983
7984 #[simd_test(enable = "avx512f,avx512vl")]
7985 unsafe fn test_mm_maskz_srli_epi64() {
7986 let a = _mm_set_epi64x(1 << 5, 0);
7987 let r = _mm_maskz_srli_epi64::<1>(0, a);
7988 assert_eq_m128i(r, _mm_setzero_si128());
7989 let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
7990 let e = _mm_set_epi64x(1 << 4, 0);
7991 assert_eq_m128i(r, e);
7992 }
7993
7994 #[simd_test(enable = "avx512f")]
7995 unsafe fn test_mm512_rolv_epi64() {
7996 #[rustfmt::skip]
7997 let a = _mm512_set_epi64(
7998 1 << 32, 1 << 63, 1 << 32, 1 << 32,
7999 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8000 );
8001 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8002 let r = _mm512_rolv_epi64(a, b);
8003 #[rustfmt::skip]
8004 let e = _mm512_set_epi64(
8005 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8006 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8007 );
8008 assert_eq_m512i(r, e);
8009 }
8010
8011 #[simd_test(enable = "avx512f")]
8012 unsafe fn test_mm512_mask_rolv_epi64() {
8013 #[rustfmt::skip]
8014 let a = _mm512_set_epi64(
8015 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8016 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8017 );
8018 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8019 let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8020 assert_eq_m512i(r, a);
8021 let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8022 #[rustfmt::skip]
8023 let e = _mm512_set_epi64(
8024 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8025 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8026 );
8027 assert_eq_m512i(r, e);
8028 }
8029
8030 #[simd_test(enable = "avx512f")]
8031 unsafe fn test_mm512_maskz_rolv_epi64() {
8032 #[rustfmt::skip]
8033 let a = _mm512_set_epi64(
8034 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8035 1 << 32, 1 << 32, 1 << 32, 1 << 62,
8036 );
8037 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8038 let r = _mm512_maskz_rolv_epi64(0, a, b);
8039 assert_eq_m512i(r, _mm512_setzero_si512());
8040 let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8041 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8042 assert_eq_m512i(r, e);
8043 }
8044
8045 #[simd_test(enable = "avx512f,avx512vl")]
8046 unsafe fn test_mm256_rolv_epi64() {
8047 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8048 let b = _mm256_set_epi64x(0, 1, 2, 3);
8049 let r = _mm256_rolv_epi64(a, b);
8050 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8051 assert_eq_m256i(r, e);
8052 }
8053
8054 #[simd_test(enable = "avx512f,avx512vl")]
8055 unsafe fn test_mm256_mask_rolv_epi64() {
8056 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8057 let b = _mm256_set_epi64x(0, 1, 2, 3);
8058 let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8059 assert_eq_m256i(r, a);
8060 let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8061 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8062 assert_eq_m256i(r, e);
8063 }
8064
8065 #[simd_test(enable = "avx512f,avx512vl")]
8066 unsafe fn test_mm256_maskz_rolv_epi64() {
8067 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8068 let b = _mm256_set_epi64x(0, 1, 2, 3);
8069 let r = _mm256_maskz_rolv_epi64(0, a, b);
8070 assert_eq_m256i(r, _mm256_setzero_si256());
8071 let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8072 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8073 assert_eq_m256i(r, e);
8074 }
8075
8076 #[simd_test(enable = "avx512f,avx512vl")]
8077 unsafe fn test_mm_rolv_epi64() {
8078 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8079 let b = _mm_set_epi64x(0, 1);
8080 let r = _mm_rolv_epi64(a, b);
8081 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8082 assert_eq_m128i(r, e);
8083 }
8084
8085 #[simd_test(enable = "avx512f,avx512vl")]
8086 unsafe fn test_mm_mask_rolv_epi64() {
8087 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8088 let b = _mm_set_epi64x(0, 1);
8089 let r = _mm_mask_rolv_epi64(a, 0, a, b);
8090 assert_eq_m128i(r, a);
8091 let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8092 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8093 assert_eq_m128i(r, e);
8094 }
8095
8096 #[simd_test(enable = "avx512f,avx512vl")]
8097 unsafe fn test_mm_maskz_rolv_epi64() {
8098 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8099 let b = _mm_set_epi64x(0, 1);
8100 let r = _mm_maskz_rolv_epi64(0, a, b);
8101 assert_eq_m128i(r, _mm_setzero_si128());
8102 let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8103 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8104 assert_eq_m128i(r, e);
8105 }
8106
8107 #[simd_test(enable = "avx512f")]
8108 unsafe fn test_mm512_rorv_epi64() {
8109 #[rustfmt::skip]
8110 let a = _mm512_set_epi64(
8111 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8112 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8113 );
8114 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8115 let r = _mm512_rorv_epi64(a, b);
8116 #[rustfmt::skip]
8117 let e = _mm512_set_epi64(
8118 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8119 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8120 );
8121 assert_eq_m512i(r, e);
8122 }
8123
8124 #[simd_test(enable = "avx512f")]
8125 unsafe fn test_mm512_mask_rorv_epi64() {
8126 #[rustfmt::skip]
8127 let a = _mm512_set_epi64(
8128 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8129 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8130 );
8131 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8132 let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8133 assert_eq_m512i(r, a);
8134 let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8135 #[rustfmt::skip]
8136 let e = _mm512_set_epi64(
8137 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8138 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8139 );
8140 assert_eq_m512i(r, e);
8141 }
8142
8143 #[simd_test(enable = "avx512f")]
8144 unsafe fn test_mm512_maskz_rorv_epi64() {
8145 #[rustfmt::skip]
8146 let a = _mm512_set_epi64(
8147 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8148 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8149 );
8150 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8151 let r = _mm512_maskz_rorv_epi64(0, a, b);
8152 assert_eq_m512i(r, _mm512_setzero_si512());
8153 let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8154 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8155 assert_eq_m512i(r, e);
8156 }
8157
8158 #[simd_test(enable = "avx512f,avx512vl")]
8159 unsafe fn test_mm256_rorv_epi64() {
8160 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8161 let b = _mm256_set_epi64x(0, 1, 2, 3);
8162 let r = _mm256_rorv_epi64(a, b);
8163 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8164 assert_eq_m256i(r, e);
8165 }
8166
8167 #[simd_test(enable = "avx512f,avx512vl")]
8168 unsafe fn test_mm256_mask_rorv_epi64() {
8169 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8170 let b = _mm256_set_epi64x(0, 1, 2, 3);
8171 let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8172 assert_eq_m256i(r, a);
8173 let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8174 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8175 assert_eq_m256i(r, e);
8176 }
8177
8178 #[simd_test(enable = "avx512f,avx512vl")]
8179 unsafe fn test_mm256_maskz_rorv_epi64() {
8180 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8181 let b = _mm256_set_epi64x(0, 1, 2, 3);
8182 let r = _mm256_maskz_rorv_epi64(0, a, b);
8183 assert_eq_m256i(r, _mm256_setzero_si256());
8184 let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8185 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8186 assert_eq_m256i(r, e);
8187 }
8188
8189 #[simd_test(enable = "avx512f,avx512vl")]
8190 unsafe fn test_mm_rorv_epi64() {
8191 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8192 let b = _mm_set_epi64x(0, 1);
8193 let r = _mm_rorv_epi64(a, b);
8194 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8195 assert_eq_m128i(r, e);
8196 }
8197
8198 #[simd_test(enable = "avx512f,avx512vl")]
8199 unsafe fn test_mm_mask_rorv_epi64() {
8200 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8201 let b = _mm_set_epi64x(0, 1);
8202 let r = _mm_mask_rorv_epi64(a, 0, a, b);
8203 assert_eq_m128i(r, a);
8204 let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8205 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8206 assert_eq_m128i(r, e);
8207 }
8208
8209 #[simd_test(enable = "avx512f,avx512vl")]
8210 unsafe fn test_mm_maskz_rorv_epi64() {
8211 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8212 let b = _mm_set_epi64x(0, 1);
8213 let r = _mm_maskz_rorv_epi64(0, a, b);
8214 assert_eq_m128i(r, _mm_setzero_si128());
8215 let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8216 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8217 assert_eq_m128i(r, e);
8218 }
8219
8220 #[simd_test(enable = "avx512f")]
8221 unsafe fn test_mm512_sllv_epi64() {
8222 #[rustfmt::skip]
8223 let a = _mm512_set_epi64(
8224 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8225 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8226 );
8227 let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8228 let r = _mm512_sllv_epi64(a, count);
8229 #[rustfmt::skip]
8230 let e = _mm512_set_epi64(
8231 1 << 32, 0, 1 << 34, 1 << 35,
8232 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8233 );
8234 assert_eq_m512i(r, e);
8235 }
8236
8237 #[simd_test(enable = "avx512f")]
8238 unsafe fn test_mm512_mask_sllv_epi64() {
8239 #[rustfmt::skip]
8240 let a = _mm512_set_epi64(
8241 1 << 32, 1 << 32, 1 << 63, 1 << 32,
8242 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8243 );
8244 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8245 let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8246 assert_eq_m512i(r, a);
8247 let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8248 #[rustfmt::skip]
8249 let e = _mm512_set_epi64(
8250 1 << 32, 1 << 33, 0, 1 << 35,
8251 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8252 );
8253 assert_eq_m512i(r, e);
8254 }
8255
8256 #[simd_test(enable = "avx512f")]
8257 unsafe fn test_mm512_maskz_sllv_epi64() {
8258 #[rustfmt::skip]
8259 let a = _mm512_set_epi64(
8260 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8261 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8262 );
8263 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8264 let r = _mm512_maskz_sllv_epi64(0, a, count);
8265 assert_eq_m512i(r, _mm512_setzero_si512());
8266 let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8267 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8268 assert_eq_m512i(r, e);
8269 }
8270
8271 #[simd_test(enable = "avx512f,avx512vl")]
8272 unsafe fn test_mm256_mask_sllv_epi64() {
8273 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8274 let count = _mm256_set_epi64x(0, 1, 2, 3);
8275 let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8276 assert_eq_m256i(r, a);
8277 let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8278 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8279 assert_eq_m256i(r, e);
8280 }
8281
8282 #[simd_test(enable = "avx512f,avx512vl")]
8283 unsafe fn test_mm256_maskz_sllv_epi64() {
8284 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8285 let count = _mm256_set_epi64x(0, 1, 2, 3);
8286 let r = _mm256_maskz_sllv_epi64(0, a, count);
8287 assert_eq_m256i(r, _mm256_setzero_si256());
8288 let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8289 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8290 assert_eq_m256i(r, e);
8291 }
8292
8293 #[simd_test(enable = "avx512f,avx512vl")]
8294 unsafe fn test_mm_mask_sllv_epi64() {
8295 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8296 let count = _mm_set_epi64x(2, 3);
8297 let r = _mm_mask_sllv_epi64(a, 0, a, count);
8298 assert_eq_m128i(r, a);
8299 let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
8300 let e = _mm_set_epi64x(0, 1 << 35);
8301 assert_eq_m128i(r, e);
8302 }
8303
8304 #[simd_test(enable = "avx512f,avx512vl")]
8305 unsafe fn test_mm_maskz_sllv_epi64() {
8306 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8307 let count = _mm_set_epi64x(2, 3);
8308 let r = _mm_maskz_sllv_epi64(0, a, count);
8309 assert_eq_m128i(r, _mm_setzero_si128());
8310 let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
8311 let e = _mm_set_epi64x(0, 1 << 35);
8312 assert_eq_m128i(r, e);
8313 }
8314
8315 #[simd_test(enable = "avx512f")]
8316 unsafe fn test_mm512_srlv_epi64() {
8317 #[rustfmt::skip]
8318 let a = _mm512_set_epi64(
8319 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8320 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8321 );
8322 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8323 let r = _mm512_srlv_epi64(a, count);
8324 #[rustfmt::skip]
8325 let e = _mm512_set_epi64(
8326 1 << 32, 0, 1 << 30, 1 << 29,
8327 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8328 );
8329 assert_eq_m512i(r, e);
8330 }
8331
8332 #[simd_test(enable = "avx512f")]
8333 unsafe fn test_mm512_mask_srlv_epi64() {
8334 #[rustfmt::skip]
8335 let a = _mm512_set_epi64(
8336 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8337 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8338 );
8339 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8340 let r = _mm512_mask_srlv_epi64(a, 0, a, count);
8341 assert_eq_m512i(r, a);
8342 let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
8343 #[rustfmt::skip]
8344 let e = _mm512_set_epi64(
8345 1 << 32, 0, 1 << 30, 1 << 29,
8346 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8347 );
8348 assert_eq_m512i(r, e);
8349 }
8350
8351 #[simd_test(enable = "avx512f")]
8352 unsafe fn test_mm512_maskz_srlv_epi64() {
8353 #[rustfmt::skip]
8354 let a = _mm512_set_epi64(
8355 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8356 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8357 );
8358 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8359 let r = _mm512_maskz_srlv_epi64(0, a, count);
8360 assert_eq_m512i(r, _mm512_setzero_si512());
8361 let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
8362 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
8363 assert_eq_m512i(r, e);
8364 }
8365
8366 #[simd_test(enable = "avx512f,avx512vl")]
8367 unsafe fn test_mm256_mask_srlv_epi64() {
8368 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8369 let count = _mm256_set1_epi64x(1);
8370 let r = _mm256_mask_srlv_epi64(a, 0, a, count);
8371 assert_eq_m256i(r, a);
8372 let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
8373 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8374 assert_eq_m256i(r, e);
8375 }
8376
8377 #[simd_test(enable = "avx512f,avx512vl")]
8378 unsafe fn test_mm256_maskz_srlv_epi64() {
8379 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8380 let count = _mm256_set1_epi64x(1);
8381 let r = _mm256_maskz_srlv_epi64(0, a, count);
8382 assert_eq_m256i(r, _mm256_setzero_si256());
8383 let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
8384 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8385 assert_eq_m256i(r, e);
8386 }
8387
8388 #[simd_test(enable = "avx512f,avx512vl")]
8389 unsafe fn test_mm_mask_srlv_epi64() {
8390 let a = _mm_set_epi64x(1 << 5, 0);
8391 let count = _mm_set1_epi64x(1);
8392 let r = _mm_mask_srlv_epi64(a, 0, a, count);
8393 assert_eq_m128i(r, a);
8394 let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
8395 let e = _mm_set_epi64x(1 << 4, 0);
8396 assert_eq_m128i(r, e);
8397 }
8398
8399 #[simd_test(enable = "avx512f,avx512vl")]
8400 unsafe fn test_mm_maskz_srlv_epi64() {
8401 let a = _mm_set_epi64x(1 << 5, 0);
8402 let count = _mm_set1_epi64x(1);
8403 let r = _mm_maskz_srlv_epi64(0, a, count);
8404 assert_eq_m128i(r, _mm_setzero_si128());
8405 let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
8406 let e = _mm_set_epi64x(1 << 4, 0);
8407 assert_eq_m128i(r, e);
8408 }
8409
8410 #[simd_test(enable = "avx512f")]
8411 unsafe fn test_mm512_sll_epi64() {
8412 #[rustfmt::skip]
8413 let a = _mm512_set_epi64(
8414 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8415 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8416 );
8417 let count = _mm_set_epi64x(0, 1);
8418 let r = _mm512_sll_epi64(a, count);
8419 #[rustfmt::skip]
8420 let e = _mm512_set_epi64(
8421 0, 1 << 33, 1 << 33, 1 << 33,
8422 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8423 );
8424 assert_eq_m512i(r, e);
8425 let count = _mm_set_epi64x(1, 0);
8426 let r = _mm512_sll_epi64(a, count);
8427 assert_eq_m512i(r, a);
8428 }
8429
8430 #[simd_test(enable = "avx512f")]
8431 unsafe fn test_mm512_mask_sll_epi64() {
8432 #[rustfmt::skip]
8433 let a = _mm512_set_epi64(
8434 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8435 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8436 );
8437 let count = _mm_set_epi64x(0, 1);
8438 let r = _mm512_mask_sll_epi64(a, 0, a, count);
8439 assert_eq_m512i(r, a);
8440 let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
8441 #[rustfmt::skip]
8442 let e = _mm512_set_epi64(
8443 0, 1 << 33, 1 << 33, 1 << 33,
8444 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8445 );
8446 assert_eq_m512i(r, e);
8447 }
8448
8449 #[simd_test(enable = "avx512f")]
8450 unsafe fn test_mm512_maskz_sll_epi64() {
8451 #[rustfmt::skip]
8452 let a = _mm512_set_epi64(
8453 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8454 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8455 );
8456 let count = _mm_set_epi64x(0, 1);
8457 let r = _mm512_maskz_sll_epi64(0, a, count);
8458 assert_eq_m512i(r, _mm512_setzero_si512());
8459 let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
8460 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8461 assert_eq_m512i(r, e);
8462 }
8463
8464 #[simd_test(enable = "avx512f,avx512vl")]
8465 unsafe fn test_mm256_mask_sll_epi64() {
8466 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8467 let count = _mm_set_epi64x(0, 1);
8468 let r = _mm256_mask_sll_epi64(a, 0, a, count);
8469 assert_eq_m256i(r, a);
8470 let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
8471 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8472 assert_eq_m256i(r, e);
8473 }
8474
8475 #[simd_test(enable = "avx512f,avx512vl")]
8476 unsafe fn test_mm256_maskz_sll_epi64() {
8477 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8478 let count = _mm_set_epi64x(0, 1);
8479 let r = _mm256_maskz_sll_epi64(0, a, count);
8480 assert_eq_m256i(r, _mm256_setzero_si256());
8481 let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
8482 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8483 assert_eq_m256i(r, e);
8484 }
8485
8486 #[simd_test(enable = "avx512f,avx512vl")]
8487 unsafe fn test_mm_mask_sll_epi64() {
8488 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8489 let count = _mm_set_epi64x(0, 1);
8490 let r = _mm_mask_sll_epi64(a, 0, a, count);
8491 assert_eq_m128i(r, a);
8492 let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
8493 let e = _mm_set_epi64x(0, 1 << 33);
8494 assert_eq_m128i(r, e);
8495 }
8496
8497 #[simd_test(enable = "avx512f,avx512vl")]
8498 unsafe fn test_mm_maskz_sll_epi64() {
8499 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8500 let count = _mm_set_epi64x(0, 1);
8501 let r = _mm_maskz_sll_epi64(0, a, count);
8502 assert_eq_m128i(r, _mm_setzero_si128());
8503 let r = _mm_maskz_sll_epi64(0b00000011, a, count);
8504 let e = _mm_set_epi64x(0, 1 << 33);
8505 assert_eq_m128i(r, e);
8506 }
8507
8508 #[simd_test(enable = "avx512f")]
8509 unsafe fn test_mm512_srl_epi64() {
8510 #[rustfmt::skip]
8511 let a = _mm512_set_epi64(
8512 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8513 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8514 );
8515 let count = _mm_set_epi64x(0, 1);
8516 let r = _mm512_srl_epi64(a, count);
8517 #[rustfmt::skip]
8518 let e = _mm512_set_epi64(
8519 0, 1 << 31, 1 << 31, 1 << 31,
8520 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8521 );
8522 assert_eq_m512i(r, e);
8523 }
8524
8525 #[simd_test(enable = "avx512f")]
8526 unsafe fn test_mm512_mask_srl_epi64() {
8527 #[rustfmt::skip]
8528 let a = _mm512_set_epi64(
8529 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8530 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8531 );
8532 let count = _mm_set_epi64x(0, 1);
8533 let r = _mm512_mask_srl_epi64(a, 0, a, count);
8534 assert_eq_m512i(r, a);
8535 let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
8536 #[rustfmt::skip]
8537 let e = _mm512_set_epi64(
8538 0, 1 << 31, 1 << 31, 1 << 31,
8539 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8540 );
8541 assert_eq_m512i(r, e);
8542 }
8543
8544 #[simd_test(enable = "avx512f")]
8545 unsafe fn test_mm512_maskz_srl_epi64() {
8546 #[rustfmt::skip]
8547 let a = _mm512_set_epi64(
8548 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8549 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8550 );
8551 let count = _mm_set_epi64x(0, 1);
8552 let r = _mm512_maskz_srl_epi64(0, a, count);
8553 assert_eq_m512i(r, _mm512_setzero_si512());
8554 let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
8555 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8556 assert_eq_m512i(r, e);
8557 }
8558
8559 #[simd_test(enable = "avx512f,avx512vl")]
8560 unsafe fn test_mm256_mask_srl_epi64() {
8561 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8562 let count = _mm_set_epi64x(0, 1);
8563 let r = _mm256_mask_srl_epi64(a, 0, a, count);
8564 assert_eq_m256i(r, a);
8565 let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
8566 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8567 assert_eq_m256i(r, e);
8568 }
8569
8570 #[simd_test(enable = "avx512f,avx512vl")]
8571 unsafe fn test_mm256_maskz_srl_epi64() {
8572 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8573 let count = _mm_set_epi64x(0, 1);
8574 let r = _mm256_maskz_srl_epi64(0, a, count);
8575 assert_eq_m256i(r, _mm256_setzero_si256());
8576 let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
8577 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8578 assert_eq_m256i(r, e);
8579 }
8580
8581 #[simd_test(enable = "avx512f,avx512vl")]
8582 unsafe fn test_mm_mask_srl_epi64() {
8583 let a = _mm_set_epi64x(1 << 5, 0);
8584 let count = _mm_set_epi64x(0, 1);
8585 let r = _mm_mask_srl_epi64(a, 0, a, count);
8586 assert_eq_m128i(r, a);
8587 let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
8588 let e = _mm_set_epi64x(1 << 4, 0);
8589 assert_eq_m128i(r, e);
8590 }
8591
8592 #[simd_test(enable = "avx512f,avx512vl")]
8593 unsafe fn test_mm_maskz_srl_epi64() {
8594 let a = _mm_set_epi64x(1 << 5, 0);
8595 let count = _mm_set_epi64x(0, 1);
8596 let r = _mm_maskz_srl_epi64(0, a, count);
8597 assert_eq_m128i(r, _mm_setzero_si128());
8598 let r = _mm_maskz_srl_epi64(0b00000011, a, count);
8599 let e = _mm_set_epi64x(1 << 4, 0);
8600 assert_eq_m128i(r, e);
8601 }
8602
8603 #[simd_test(enable = "avx512f")]
8604 unsafe fn test_mm512_sra_epi64() {
8605 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8606 let count = _mm_set_epi64x(0, 2);
8607 let r = _mm512_sra_epi64(a, count);
8608 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
8609 assert_eq_m512i(r, e);
8610 }
8611
8612 #[simd_test(enable = "avx512f")]
8613 unsafe fn test_mm512_mask_sra_epi64() {
8614 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8615 let count = _mm_set_epi64x(0, 2);
8616 let r = _mm512_mask_sra_epi64(a, 0, a, count);
8617 assert_eq_m512i(r, a);
8618 let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
8619 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
8620 assert_eq_m512i(r, e);
8621 }
8622
8623 #[simd_test(enable = "avx512f")]
8624 unsafe fn test_mm512_maskz_sra_epi64() {
8625 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8626 let count = _mm_set_epi64x(0, 2);
8627 let r = _mm512_maskz_sra_epi64(0, a, count);
8628 assert_eq_m512i(r, _mm512_setzero_si512());
8629 let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
8630 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
8631 assert_eq_m512i(r, e);
8632 }
8633
8634 #[simd_test(enable = "avx512f,avx512vl")]
8635 unsafe fn test_mm256_sra_epi64() {
8636 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8637 let count = _mm_set_epi64x(0, 1);
8638 let r = _mm256_sra_epi64(a, count);
8639 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8640 assert_eq_m256i(r, e);
8641 }
8642
8643 #[simd_test(enable = "avx512f,avx512vl")]
8644 unsafe fn test_mm256_mask_sra_epi64() {
8645 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8646 let count = _mm_set_epi64x(0, 1);
8647 let r = _mm256_mask_sra_epi64(a, 0, a, count);
8648 assert_eq_m256i(r, a);
8649 let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
8650 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8651 assert_eq_m256i(r, e);
8652 }
8653
8654 #[simd_test(enable = "avx512f,avx512vl")]
8655 unsafe fn test_mm256_maskz_sra_epi64() {
8656 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8657 let count = _mm_set_epi64x(0, 1);
8658 let r = _mm256_maskz_sra_epi64(0, a, count);
8659 assert_eq_m256i(r, _mm256_setzero_si256());
8660 let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
8661 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8662 assert_eq_m256i(r, e);
8663 }
8664
8665 #[simd_test(enable = "avx512f,avx512vl")]
8666 unsafe fn test_mm_sra_epi64() {
8667 let a = _mm_set_epi64x(1 << 5, 0);
8668 let count = _mm_set_epi64x(0, 1);
8669 let r = _mm_sra_epi64(a, count);
8670 let e = _mm_set_epi64x(1 << 4, 0);
8671 assert_eq_m128i(r, e);
8672 }
8673
8674 #[simd_test(enable = "avx512f,avx512vl")]
8675 unsafe fn test_mm_mask_sra_epi64() {
8676 let a = _mm_set_epi64x(1 << 5, 0);
8677 let count = _mm_set_epi64x(0, 1);
8678 let r = _mm_mask_sra_epi64(a, 0, a, count);
8679 assert_eq_m128i(r, a);
8680 let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
8681 let e = _mm_set_epi64x(1 << 4, 0);
8682 assert_eq_m128i(r, e);
8683 }
8684
8685 #[simd_test(enable = "avx512f,avx512vl")]
8686 unsafe fn test_mm_maskz_sra_epi64() {
8687 let a = _mm_set_epi64x(1 << 5, 0);
8688 let count = _mm_set_epi64x(0, 1);
8689 let r = _mm_maskz_sra_epi64(0, a, count);
8690 assert_eq_m128i(r, _mm_setzero_si128());
8691 let r = _mm_maskz_sra_epi64(0b00000011, a, count);
8692 let e = _mm_set_epi64x(1 << 4, 0);
8693 assert_eq_m128i(r, e);
8694 }
8695
8696 #[simd_test(enable = "avx512f")]
8697 unsafe fn test_mm512_srav_epi64() {
8698 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8699 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
8700 let r = _mm512_srav_epi64(a, count);
8701 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
8702 assert_eq_m512i(r, e);
8703 }
8704
8705 #[simd_test(enable = "avx512f")]
8706 unsafe fn test_mm512_mask_srav_epi64() {
8707 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8708 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
8709 let r = _mm512_mask_srav_epi64(a, 0, a, count);
8710 assert_eq_m512i(r, a);
8711 let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
8712 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
8713 assert_eq_m512i(r, e);
8714 }
8715
8716 #[simd_test(enable = "avx512f")]
8717 unsafe fn test_mm512_maskz_srav_epi64() {
8718 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
8719 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
8720 let r = _mm512_maskz_srav_epi64(0, a, count);
8721 assert_eq_m512i(r, _mm512_setzero_si512());
8722 let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
8723 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
8724 assert_eq_m512i(r, e);
8725 }
8726
8727 #[simd_test(enable = "avx512f,avx512vl")]
8728 unsafe fn test_mm256_srav_epi64() {
8729 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8730 let count = _mm256_set1_epi64x(1);
8731 let r = _mm256_srav_epi64(a, count);
8732 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8733 assert_eq_m256i(r, e);
8734 }
8735
8736 #[simd_test(enable = "avx512f,avx512vl")]
8737 unsafe fn test_mm256_mask_srav_epi64() {
8738 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8739 let count = _mm256_set1_epi64x(1);
8740 let r = _mm256_mask_srav_epi64(a, 0, a, count);
8741 assert_eq_m256i(r, a);
8742 let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
8743 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8744 assert_eq_m256i(r, e);
8745 }
8746
8747 #[simd_test(enable = "avx512f,avx512vl")]
8748 unsafe fn test_mm256_maskz_srav_epi64() {
8749 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8750 let count = _mm256_set1_epi64x(1);
8751 let r = _mm256_maskz_srav_epi64(0, a, count);
8752 assert_eq_m256i(r, _mm256_setzero_si256());
8753 let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
8754 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8755 assert_eq_m256i(r, e);
8756 }
8757
8758 #[simd_test(enable = "avx512f,avx512vl")]
8759 unsafe fn test_mm_srav_epi64() {
8760 let a = _mm_set_epi64x(1 << 5, 0);
8761 let count = _mm_set1_epi64x(1);
8762 let r = _mm_srav_epi64(a, count);
8763 let e = _mm_set_epi64x(1 << 4, 0);
8764 assert_eq_m128i(r, e);
8765 }
8766
8767 #[simd_test(enable = "avx512f,avx512vl")]
8768 unsafe fn test_mm_mask_srav_epi64() {
8769 let a = _mm_set_epi64x(1 << 5, 0);
8770 let count = _mm_set1_epi64x(1);
8771 let r = _mm_mask_srav_epi64(a, 0, a, count);
8772 assert_eq_m128i(r, a);
8773 let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
8774 let e = _mm_set_epi64x(1 << 4, 0);
8775 assert_eq_m128i(r, e);
8776 }
8777
8778 #[simd_test(enable = "avx512f,avx512vl")]
8779 unsafe fn test_mm_maskz_srav_epi64() {
8780 let a = _mm_set_epi64x(1 << 5, 0);
8781 let count = _mm_set1_epi64x(1);
8782 let r = _mm_maskz_srav_epi64(0, a, count);
8783 assert_eq_m128i(r, _mm_setzero_si128());
8784 let r = _mm_maskz_srav_epi64(0b00000011, a, count);
8785 let e = _mm_set_epi64x(1 << 4, 0);
8786 assert_eq_m128i(r, e);
8787 }
8788
8789 #[simd_test(enable = "avx512f")]
8790 unsafe fn test_mm512_srai_epi64() {
8791 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
8792 let r = _mm512_srai_epi64::<2>(a);
8793 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
8794 assert_eq_m512i(r, e);
8795 }
8796
8797 #[simd_test(enable = "avx512f")]
8798 unsafe fn test_mm512_mask_srai_epi64() {
8799 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
8800 let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
8801 assert_eq_m512i(r, a);
8802 let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
8803 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
8804 assert_eq_m512i(r, e);
8805 }
8806
8807 #[simd_test(enable = "avx512f")]
8808 unsafe fn test_mm512_maskz_srai_epi64() {
8809 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
8810 let r = _mm512_maskz_srai_epi64::<2>(0, a);
8811 assert_eq_m512i(r, _mm512_setzero_si512());
8812 let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
8813 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
8814 assert_eq_m512i(r, e);
8815 }
8816
8817 #[simd_test(enable = "avx512f,avx512vl")]
8818 unsafe fn test_mm256_srai_epi64() {
8819 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8820 let r = _mm256_srai_epi64::<1>(a);
8821 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8822 assert_eq_m256i(r, e);
8823 }
8824
8825 #[simd_test(enable = "avx512f,avx512vl")]
8826 unsafe fn test_mm256_mask_srai_epi64() {
8827 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8828 let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
8829 assert_eq_m256i(r, a);
8830 let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
8831 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8832 assert_eq_m256i(r, e);
8833 }
8834
8835 #[simd_test(enable = "avx512f,avx512vl")]
8836 unsafe fn test_mm256_maskz_srai_epi64() {
8837 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8838 let r = _mm256_maskz_srai_epi64::<1>(0, a);
8839 assert_eq_m256i(r, _mm256_setzero_si256());
8840 let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
8841 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8842 assert_eq_m256i(r, e);
8843 }
8844
8845 #[simd_test(enable = "avx512f,avx512vl")]
8846 unsafe fn test_mm_srai_epi64() {
8847 let a = _mm_set_epi64x(1 << 5, 0);
8848 let r = _mm_srai_epi64::<1>(a);
8849 let e = _mm_set_epi64x(1 << 4, 0);
8850 assert_eq_m128i(r, e);
8851 }
8852
8853 #[simd_test(enable = "avx512f,avx512vl")]
8854 unsafe fn test_mm_mask_srai_epi64() {
8855 let a = _mm_set_epi64x(1 << 5, 0);
8856 let r = _mm_mask_srai_epi64::<1>(a, 0, a);
8857 assert_eq_m128i(r, a);
8858 let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
8859 let e = _mm_set_epi64x(1 << 4, 0);
8860 assert_eq_m128i(r, e);
8861 }
8862
8863 #[simd_test(enable = "avx512f,avx512vl")]
8864 unsafe fn test_mm_maskz_srai_epi64() {
8865 let a = _mm_set_epi64x(1 << 5, 0);
8866 let r = _mm_maskz_srai_epi64::<1>(0, a);
8867 assert_eq_m128i(r, _mm_setzero_si128());
8868 let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
8869 let e = _mm_set_epi64x(1 << 4, 0);
8870 assert_eq_m128i(r, e);
8871 }
8872
8873 #[simd_test(enable = "avx512f")]
8874 unsafe fn test_mm512_permute_pd() {
8875 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
8876 let r = _mm512_permute_pd::<0b11_11_11_11>(a);
8877 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
8878 assert_eq_m512d(r, e);
8879 }
8880
8881 #[simd_test(enable = "avx512f")]
8882 unsafe fn test_mm512_mask_permute_pd() {
8883 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
8884 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
8885 assert_eq_m512d(r, a);
8886 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
8887 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
8888 assert_eq_m512d(r, e);
8889 }
8890
8891 #[simd_test(enable = "avx512f")]
8892 unsafe fn test_mm512_maskz_permute_pd() {
8893 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
8894 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
8895 assert_eq_m512d(r, _mm512_setzero_pd());
8896 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
8897 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
8898 assert_eq_m512d(r, e);
8899 }
8900
8901 #[simd_test(enable = "avx512f,avx512vl")]
8902 unsafe fn test_mm256_mask_permute_pd() {
8903 let a = _mm256_set_pd(3., 2., 1., 0.);
8904 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
8905 assert_eq_m256d(r, a);
8906 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
8907 let e = _mm256_set_pd(3., 3., 1., 1.);
8908 assert_eq_m256d(r, e);
8909 }
8910
8911 #[simd_test(enable = "avx512f,avx512vl")]
8912 unsafe fn test_mm256_maskz_permute_pd() {
8913 let a = _mm256_set_pd(3., 2., 1., 0.);
8914 let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
8915 assert_eq_m256d(r, _mm256_setzero_pd());
8916 let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
8917 let e = _mm256_set_pd(3., 3., 1., 1.);
8918 assert_eq_m256d(r, e);
8919 }
8920
8921 #[simd_test(enable = "avx512f,avx512vl")]
8922 unsafe fn test_mm_mask_permute_pd() {
8923 let a = _mm_set_pd(1., 0.);
8924 let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
8925 assert_eq_m128d(r, a);
8926 let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
8927 let e = _mm_set_pd(1., 1.);
8928 assert_eq_m128d(r, e);
8929 }
8930
8931 #[simd_test(enable = "avx512f,avx512vl")]
8932 unsafe fn test_mm_maskz_permute_pd() {
8933 let a = _mm_set_pd(1., 0.);
8934 let r = _mm_maskz_permute_pd::<0b11>(0, a);
8935 assert_eq_m128d(r, _mm_setzero_pd());
8936 let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
8937 let e = _mm_set_pd(1., 1.);
8938 assert_eq_m128d(r, e);
8939 }
8940
8941 #[simd_test(enable = "avx512f")]
8942 unsafe fn test_mm512_permutex_epi64() {
8943 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8944 let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
8945 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
8946 assert_eq_m512i(r, e);
8947 }
8948
8949 #[simd_test(enable = "avx512f")]
8950 unsafe fn test_mm512_mask_permutex_epi64() {
8951 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8952 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
8953 assert_eq_m512i(r, a);
8954 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
8955 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
8956 assert_eq_m512i(r, e);
8957 }
8958
8959 #[simd_test(enable = "avx512f")]
8960 unsafe fn test_mm512_maskz_permutex_epi64() {
8961 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8962 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
8963 assert_eq_m512i(r, _mm512_setzero_si512());
8964 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
8965 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
8966 assert_eq_m512i(r, e);
8967 }
8968
8969 #[simd_test(enable = "avx512f,avx512vl")]
8970 unsafe fn test_mm256_permutex_epi64() {
8971 let a = _mm256_set_epi64x(3, 2, 1, 0);
8972 let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
8973 let e = _mm256_set_epi64x(3, 3, 3, 3);
8974 assert_eq_m256i(r, e);
8975 }
8976
8977 #[simd_test(enable = "avx512f,avx512vl")]
8978 unsafe fn test_mm256_mask_permutex_epi64() {
8979 let a = _mm256_set_epi64x(3, 2, 1, 0);
8980 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
8981 assert_eq_m256i(r, a);
8982 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
8983 let e = _mm256_set_epi64x(3, 3, 3, 3);
8984 assert_eq_m256i(r, e);
8985 }
8986
8987 #[simd_test(enable = "avx512f")]
8988 unsafe fn test_mm256_maskz_permutex_epi64() {
8989 let a = _mm256_set_epi64x(3, 2, 1, 0);
8990 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
8991 assert_eq_m256i(r, _mm256_setzero_si256());
8992 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
8993 let e = _mm256_set_epi64x(3, 3, 3, 3);
8994 assert_eq_m256i(r, e);
8995 }
8996
8997 #[simd_test(enable = "avx512f")]
8998 unsafe fn test_mm512_permutex_pd() {
8999 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9000 let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9001 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9002 assert_eq_m512d(r, e);
9003 }
9004
9005 #[simd_test(enable = "avx512f")]
9006 unsafe fn test_mm512_mask_permutex_pd() {
9007 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9008 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9009 assert_eq_m512d(r, a);
9010 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9011 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9012 assert_eq_m512d(r, e);
9013 }
9014
9015 #[simd_test(enable = "avx512f")]
9016 unsafe fn test_mm512_maskz_permutex_pd() {
9017 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9018 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9019 assert_eq_m512d(r, _mm512_setzero_pd());
9020 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9021 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9022 assert_eq_m512d(r, e);
9023 }
9024
9025 #[simd_test(enable = "avx512f,avx512vl")]
9026 unsafe fn test_mm256_permutex_pd() {
9027 let a = _mm256_set_pd(0., 1., 2., 3.);
9028 let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9029 let e = _mm256_set_pd(0., 0., 0., 0.);
9030 assert_eq_m256d(r, e);
9031 }
9032
9033 #[simd_test(enable = "avx512f,avx512vl")]
9034 unsafe fn test_mm256_mask_permutex_pd() {
9035 let a = _mm256_set_pd(0., 1., 2., 3.);
9036 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9037 assert_eq_m256d(r, a);
9038 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9039 let e = _mm256_set_pd(0., 0., 0., 0.);
9040 assert_eq_m256d(r, e);
9041 }
9042
9043 #[simd_test(enable = "avx512f,avx512vl")]
9044 unsafe fn test_mm256_maskz_permutex_pd() {
9045 let a = _mm256_set_pd(0., 1., 2., 3.);
9046 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9047 assert_eq_m256d(r, _mm256_setzero_pd());
9048 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9049 let e = _mm256_set_pd(0., 0., 0., 0.);
9050 assert_eq_m256d(r, e);
9051 }
9052
9053 #[simd_test(enable = "avx512f")]
9054 unsafe fn test_mm512_permutevar_pd() {
9055 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9056 let b = _mm512_set1_epi64(0b1);
9057 let r = _mm512_permutevar_pd(a, b);
9058 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9059 assert_eq_m512d(r, e);
9060 }
9061
9062 #[simd_test(enable = "avx512f")]
9063 unsafe fn test_mm512_mask_permutevar_pd() {
9064 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9065 let b = _mm512_set1_epi64(0b1);
9066 let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9067 assert_eq_m512d(r, a);
9068 let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9069 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9070 assert_eq_m512d(r, e);
9071 }
9072
9073 #[simd_test(enable = "avx512f")]
9074 unsafe fn test_mm512_maskz_permutevar_pd() {
9075 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9076 let b = _mm512_set1_epi64(0b1);
9077 let r = _mm512_maskz_permutevar_pd(0, a, b);
9078 assert_eq_m512d(r, _mm512_setzero_pd());
9079 let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9080 let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9081 assert_eq_m512d(r, e);
9082 }
9083
9084 #[simd_test(enable = "avx512f,avx512vl")]
9085 unsafe fn test_mm256_mask_permutevar_pd() {
9086 let a = _mm256_set_pd(0., 1., 2., 3.);
9087 let b = _mm256_set1_epi64x(0b1);
9088 let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9089 assert_eq_m256d(r, a);
9090 let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9091 let e = _mm256_set_pd(1., 1., 3., 3.);
9092 assert_eq_m256d(r, e);
9093 }
9094
9095 #[simd_test(enable = "avx512f,avx512vl")]
9096 unsafe fn test_mm256_maskz_permutevar_pd() {
9097 let a = _mm256_set_pd(0., 1., 2., 3.);
9098 let b = _mm256_set1_epi64x(0b1);
9099 let r = _mm256_maskz_permutevar_pd(0, a, b);
9100 assert_eq_m256d(r, _mm256_setzero_pd());
9101 let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9102 let e = _mm256_set_pd(1., 1., 3., 3.);
9103 assert_eq_m256d(r, e);
9104 }
9105
9106 #[simd_test(enable = "avx512f,avx512vl")]
9107 unsafe fn test_mm_mask_permutevar_pd() {
9108 let a = _mm_set_pd(0., 1.);
9109 let b = _mm_set1_epi64x(0b1);
9110 let r = _mm_mask_permutevar_pd(a, 0, a, b);
9111 assert_eq_m128d(r, a);
9112 let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9113 let e = _mm_set_pd(1., 1.);
9114 assert_eq_m128d(r, e);
9115 }
9116
9117 #[simd_test(enable = "avx512f,avx512vl")]
9118 unsafe fn test_mm_maskz_permutevar_pd() {
9119 let a = _mm_set_pd(0., 1.);
9120 let b = _mm_set1_epi64x(0b1);
9121 let r = _mm_maskz_permutevar_pd(0, a, b);
9122 assert_eq_m128d(r, _mm_setzero_pd());
9123 let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9124 let e = _mm_set_pd(1., 1.);
9125 assert_eq_m128d(r, e);
9126 }
9127
9128 #[simd_test(enable = "avx512f")]
9129 unsafe fn test_mm512_permutexvar_epi64() {
9130 let idx = _mm512_set1_epi64(1);
9131 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9132 let r = _mm512_permutexvar_epi64(idx, a);
9133 let e = _mm512_set1_epi64(6);
9134 assert_eq_m512i(r, e);
9135 }
9136
9137 #[simd_test(enable = "avx512f")]
9138 unsafe fn test_mm512_mask_permutexvar_epi64() {
9139 let idx = _mm512_set1_epi64(1);
9140 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9141 let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9142 assert_eq_m512i(r, a);
9143 let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9144 let e = _mm512_set1_epi64(6);
9145 assert_eq_m512i(r, e);
9146 }
9147
9148 #[simd_test(enable = "avx512f")]
9149 unsafe fn test_mm512_maskz_permutexvar_epi64() {
9150 let idx = _mm512_set1_epi64(1);
9151 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9152 let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9153 assert_eq_m512i(r, _mm512_setzero_si512());
9154 let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9155 let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9156 assert_eq_m512i(r, e);
9157 }
9158
9159 #[simd_test(enable = "avx512f,avx512vl")]
9160 unsafe fn test_mm256_permutexvar_epi64() {
9161 let idx = _mm256_set1_epi64x(1);
9162 let a = _mm256_set_epi64x(0, 1, 2, 3);
9163 let r = _mm256_permutexvar_epi64(idx, a);
9164 let e = _mm256_set1_epi64x(2);
9165 assert_eq_m256i(r, e);
9166 }
9167
9168 #[simd_test(enable = "avx512f,avx512vl")]
9169 unsafe fn test_mm256_mask_permutexvar_epi64() {
9170 let idx = _mm256_set1_epi64x(1);
9171 let a = _mm256_set_epi64x(0, 1, 2, 3);
9172 let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9173 assert_eq_m256i(r, a);
9174 let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9175 let e = _mm256_set1_epi64x(2);
9176 assert_eq_m256i(r, e);
9177 }
9178
9179 #[simd_test(enable = "avx512f,avx512vl")]
9180 unsafe fn test_mm256_maskz_permutexvar_epi64() {
9181 let idx = _mm256_set1_epi64x(1);
9182 let a = _mm256_set_epi64x(0, 1, 2, 3);
9183 let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9184 assert_eq_m256i(r, _mm256_setzero_si256());
9185 let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9186 let e = _mm256_set1_epi64x(2);
9187 assert_eq_m256i(r, e);
9188 }
9189
9190 #[simd_test(enable = "avx512f")]
9191 unsafe fn test_mm512_permutexvar_pd() {
9192 let idx = _mm512_set1_epi64(1);
9193 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9194 let r = _mm512_permutexvar_pd(idx, a);
9195 let e = _mm512_set1_pd(6.);
9196 assert_eq_m512d(r, e);
9197 }
9198
9199 #[simd_test(enable = "avx512f")]
9200 unsafe fn test_mm512_mask_permutexvar_pd() {
9201 let idx = _mm512_set1_epi64(1);
9202 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9203 let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9204 assert_eq_m512d(r, a);
9205 let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9206 let e = _mm512_set1_pd(6.);
9207 assert_eq_m512d(r, e);
9208 }
9209
9210 #[simd_test(enable = "avx512f")]
9211 unsafe fn test_mm512_maskz_permutexvar_pd() {
9212 let idx = _mm512_set1_epi64(1);
9213 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9214 let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9215 assert_eq_m512d(r, _mm512_setzero_pd());
9216 let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9217 let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9218 assert_eq_m512d(r, e);
9219 }
9220
9221 #[simd_test(enable = "avx512f,avx512vl")]
9222 unsafe fn test_mm256_permutexvar_pd() {
9223 let idx = _mm256_set1_epi64x(1);
9224 let a = _mm256_set_pd(0., 1., 2., 3.);
9225 let r = _mm256_permutexvar_pd(idx, a);
9226 let e = _mm256_set1_pd(2.);
9227 assert_eq_m256d(r, e);
9228 }
9229
9230 #[simd_test(enable = "avx512f,avx512vl")]
9231 unsafe fn test_mm256_mask_permutexvar_pd() {
9232 let idx = _mm256_set1_epi64x(1);
9233 let a = _mm256_set_pd(0., 1., 2., 3.);
9234 let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9235 assert_eq_m256d(r, a);
9236 let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9237 let e = _mm256_set1_pd(2.);
9238 assert_eq_m256d(r, e);
9239 }
9240
9241 #[simd_test(enable = "avx512f,avx512vl")]
9242 unsafe fn test_mm256_maskz_permutexvar_pd() {
9243 let idx = _mm256_set1_epi64x(1);
9244 let a = _mm256_set_pd(0., 1., 2., 3.);
9245 let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9246 assert_eq_m256d(r, _mm256_setzero_pd());
9247 let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9248 let e = _mm256_set1_pd(2.);
9249 assert_eq_m256d(r, e);
9250 }
9251
9252 #[simd_test(enable = "avx512f")]
9253 unsafe fn test_mm512_permutex2var_epi64() {
9254 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9255 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9256 let b = _mm512_set1_epi64(100);
9257 let r = _mm512_permutex2var_epi64(a, idx, b);
9258 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9259 assert_eq_m512i(r, e);
9260 }
9261
9262 #[simd_test(enable = "avx512f")]
9263 unsafe fn test_mm512_mask_permutex2var_epi64() {
9264 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9265 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9266 let b = _mm512_set1_epi64(100);
9267 let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9268 assert_eq_m512i(r, a);
9269 let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9270 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9271 assert_eq_m512i(r, e);
9272 }
9273
9274 #[simd_test(enable = "avx512f")]
9275 unsafe fn test_mm512_maskz_permutex2var_epi64() {
9276 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9277 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9278 let b = _mm512_set1_epi64(100);
9279 let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9280 assert_eq_m512i(r, _mm512_setzero_si512());
9281 let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9282 let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9283 assert_eq_m512i(r, e);
9284 }
9285
9286 #[simd_test(enable = "avx512f")]
9287 unsafe fn test_mm512_mask2_permutex2var_epi64() {
9288 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9289 let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9290 let b = _mm512_set1_epi64(100);
9291 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
9292 assert_eq_m512i(r, idx);
9293 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9294 let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
9295 assert_eq_m512i(r, e);
9296 }
9297
9298 #[simd_test(enable = "avx512f,avx512vl")]
9299 unsafe fn test_mm256_permutex2var_epi64() {
9300 let a = _mm256_set_epi64x(0, 1, 2, 3);
9301 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9302 let b = _mm256_set1_epi64x(100);
9303 let r = _mm256_permutex2var_epi64(a, idx, b);
9304 let e = _mm256_set_epi64x(2, 100, 1, 100);
9305 assert_eq_m256i(r, e);
9306 }
9307
9308 #[simd_test(enable = "avx512f,avx512vl")]
9309 unsafe fn test_mm256_mask_permutex2var_epi64() {
9310 let a = _mm256_set_epi64x(0, 1, 2, 3);
9311 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9312 let b = _mm256_set1_epi64x(100);
9313 let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
9314 assert_eq_m256i(r, a);
9315 let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
9316 let e = _mm256_set_epi64x(2, 100, 1, 100);
9317 assert_eq_m256i(r, e);
9318 }
9319
9320 #[simd_test(enable = "avx512f,avx512vl")]
9321 unsafe fn test_mm256_maskz_permutex2var_epi64() {
9322 let a = _mm256_set_epi64x(0, 1, 2, 3);
9323 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9324 let b = _mm256_set1_epi64x(100);
9325 let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
9326 assert_eq_m256i(r, _mm256_setzero_si256());
9327 let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9328 let e = _mm256_set_epi64x(2, 100, 1, 100);
9329 assert_eq_m256i(r, e);
9330 }
9331
9332 #[simd_test(enable = "avx512f,avx512vl")]
9333 unsafe fn test_mm256_mask2_permutex2var_epi64() {
9334 let a = _mm256_set_epi64x(0, 1, 2, 3);
9335 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9336 let b = _mm256_set1_epi64x(100);
9337 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
9338 assert_eq_m256i(r, idx);
9339 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9340 let e = _mm256_set_epi64x(2, 100, 1, 100);
9341 assert_eq_m256i(r, e);
9342 }
9343
9344 #[simd_test(enable = "avx512f,avx512vl")]
9345 unsafe fn test_mm_permutex2var_epi64() {
9346 let a = _mm_set_epi64x(0, 1);
9347 let idx = _mm_set_epi64x(1, 1 << 1);
9348 let b = _mm_set1_epi64x(100);
9349 let r = _mm_permutex2var_epi64(a, idx, b);
9350 let e = _mm_set_epi64x(0, 100);
9351 assert_eq_m128i(r, e);
9352 }
9353
9354 #[simd_test(enable = "avx512f,avx512vl")]
9355 unsafe fn test_mm_mask_permutex2var_epi64() {
9356 let a = _mm_set_epi64x(0, 1);
9357 let idx = _mm_set_epi64x(1, 1 << 1);
9358 let b = _mm_set1_epi64x(100);
9359 let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
9360 assert_eq_m128i(r, a);
9361 let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
9362 let e = _mm_set_epi64x(0, 100);
9363 assert_eq_m128i(r, e);
9364 }
9365
9366 #[simd_test(enable = "avx512f,avx512vl")]
9367 unsafe fn test_mm_maskz_permutex2var_epi64() {
9368 let a = _mm_set_epi64x(0, 1);
9369 let idx = _mm_set_epi64x(1, 1 << 1);
9370 let b = _mm_set1_epi64x(100);
9371 let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
9372 assert_eq_m128i(r, _mm_setzero_si128());
9373 let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
9374 let e = _mm_set_epi64x(0, 100);
9375 assert_eq_m128i(r, e);
9376 }
9377
9378 #[simd_test(enable = "avx512f,avx512vl")]
9379 unsafe fn test_mm_mask2_permutex2var_epi64() {
9380 let a = _mm_set_epi64x(0, 1);
9381 let idx = _mm_set_epi64x(1, 1 << 1);
9382 let b = _mm_set1_epi64x(100);
9383 let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
9384 assert_eq_m128i(r, idx);
9385 let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
9386 let e = _mm_set_epi64x(0, 100);
9387 assert_eq_m128i(r, e);
9388 }
9389
9390 #[simd_test(enable = "avx512f")]
9391 unsafe fn test_mm512_permutex2var_pd() {
9392 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9393 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9394 let b = _mm512_set1_pd(100.);
9395 let r = _mm512_permutex2var_pd(a, idx, b);
9396 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
9397 assert_eq_m512d(r, e);
9398 }
9399
9400 #[simd_test(enable = "avx512f")]
9401 unsafe fn test_mm512_mask_permutex2var_pd() {
9402 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9403 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9404 let b = _mm512_set1_pd(100.);
9405 let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
9406 assert_eq_m512d(r, a);
9407 let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
9408 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
9409 assert_eq_m512d(r, e);
9410 }
9411
9412 #[simd_test(enable = "avx512f")]
9413 unsafe fn test_mm512_maskz_permutex2var_pd() {
9414 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9415 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9416 let b = _mm512_set1_pd(100.);
9417 let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
9418 assert_eq_m512d(r, _mm512_setzero_pd());
9419 let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
9420 let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
9421 assert_eq_m512d(r, e);
9422 }
9423
9424 #[simd_test(enable = "avx512f")]
9425 unsafe fn test_mm512_mask2_permutex2var_pd() {
9426 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9427 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9428 let b = _mm512_set1_pd(100.);
9429 let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
9430 assert_eq_m512d(r, _mm512_castsi512_pd(idx));
9431 let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
9432 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
9433 assert_eq_m512d(r, e);
9434 }
9435
9436 #[simd_test(enable = "avx512f,avx512vl")]
9437 unsafe fn test_mm256_permutex2var_pd() {
9438 let a = _mm256_set_pd(0., 1., 2., 3.);
9439 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9440 let b = _mm256_set1_pd(100.);
9441 let r = _mm256_permutex2var_pd(a, idx, b);
9442 let e = _mm256_set_pd(2., 100., 1., 100.);
9443 assert_eq_m256d(r, e);
9444 }
9445
9446 #[simd_test(enable = "avx512f,avx512vl")]
9447 unsafe fn test_mm256_mask_permutex2var_pd() {
9448 let a = _mm256_set_pd(0., 1., 2., 3.);
9449 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9450 let b = _mm256_set1_pd(100.);
9451 let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
9452 assert_eq_m256d(r, a);
9453 let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
9454 let e = _mm256_set_pd(2., 100., 1., 100.);
9455 assert_eq_m256d(r, e);
9456 }
9457
9458 #[simd_test(enable = "avx512f,avx512vl")]
9459 unsafe fn test_mm256_maskz_permutex2var_pd() {
9460 let a = _mm256_set_pd(0., 1., 2., 3.);
9461 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9462 let b = _mm256_set1_pd(100.);
9463 let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
9464 assert_eq_m256d(r, _mm256_setzero_pd());
9465 let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
9466 let e = _mm256_set_pd(2., 100., 1., 100.);
9467 assert_eq_m256d(r, e);
9468 }
9469
9470 #[simd_test(enable = "avx512f,avx512vl")]
9471 unsafe fn test_mm256_mask2_permutex2var_pd() {
9472 let a = _mm256_set_pd(0., 1., 2., 3.);
9473 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9474 let b = _mm256_set1_pd(100.);
9475 let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
9476 assert_eq_m256d(r, _mm256_castsi256_pd(idx));
9477 let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
9478 let e = _mm256_set_pd(2., 100., 1., 100.);
9479 assert_eq_m256d(r, e);
9480 }
9481
9482 #[simd_test(enable = "avx512f,avx512vl")]
9483 unsafe fn test_mm_permutex2var_pd() {
9484 let a = _mm_set_pd(0., 1.);
9485 let idx = _mm_set_epi64x(1, 1 << 1);
9486 let b = _mm_set1_pd(100.);
9487 let r = _mm_permutex2var_pd(a, idx, b);
9488 let e = _mm_set_pd(0., 100.);
9489 assert_eq_m128d(r, e);
9490 }
9491
9492 #[simd_test(enable = "avx512f,avx512vl")]
9493 unsafe fn test_mm_mask_permutex2var_pd() {
9494 let a = _mm_set_pd(0., 1.);
9495 let idx = _mm_set_epi64x(1, 1 << 1);
9496 let b = _mm_set1_pd(100.);
9497 let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
9498 assert_eq_m128d(r, a);
9499 let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
9500 let e = _mm_set_pd(0., 100.);
9501 assert_eq_m128d(r, e);
9502 }
9503
9504 #[simd_test(enable = "avx512f,avx512vl")]
9505 unsafe fn test_mm_maskz_permutex2var_pd() {
9506 let a = _mm_set_pd(0., 1.);
9507 let idx = _mm_set_epi64x(1, 1 << 1);
9508 let b = _mm_set1_pd(100.);
9509 let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
9510 assert_eq_m128d(r, _mm_setzero_pd());
9511 let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
9512 let e = _mm_set_pd(0., 100.);
9513 assert_eq_m128d(r, e);
9514 }
9515
9516 #[simd_test(enable = "avx512f,avx512vl")]
9517 unsafe fn test_mm_mask2_permutex2var_pd() {
9518 let a = _mm_set_pd(0., 1.);
9519 let idx = _mm_set_epi64x(1, 1 << 1);
9520 let b = _mm_set1_pd(100.);
9521 let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
9522 assert_eq_m128d(r, _mm_castsi128_pd(idx));
9523 let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
9524 let e = _mm_set_pd(0., 100.);
9525 assert_eq_m128d(r, e);
9526 }
9527
9528 #[simd_test(enable = "avx512f,avx512vl")]
9529 unsafe fn test_mm256_mask_shuffle_pd() {
9530 let a = _mm256_set_pd(1., 4., 5., 8.);
9531 let b = _mm256_set_pd(2., 3., 6., 7.);
9532 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
9533 assert_eq_m256d(r, a);
9534 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
9535 let e = _mm256_set_pd(2., 1., 6., 5.);
9536 assert_eq_m256d(r, e);
9537 }
9538
9539 #[simd_test(enable = "avx512f,avx512vl")]
9540 unsafe fn test_mm256_maskz_shuffle_pd() {
9541 let a = _mm256_set_pd(1., 4., 5., 8.);
9542 let b = _mm256_set_pd(2., 3., 6., 7.);
9543 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
9544 assert_eq_m256d(r, _mm256_setzero_pd());
9545 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
9546 let e = _mm256_set_pd(2., 1., 6., 5.);
9547 assert_eq_m256d(r, e);
9548 }
9549
9550 #[simd_test(enable = "avx512f,avx512vl")]
9551 unsafe fn test_mm_mask_shuffle_pd() {
9552 let a = _mm_set_pd(1., 4.);
9553 let b = _mm_set_pd(2., 3.);
9554 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
9555 assert_eq_m128d(r, a);
9556 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
9557 let e = _mm_set_pd(2., 1.);
9558 assert_eq_m128d(r, e);
9559 }
9560
9561 #[simd_test(enable = "avx512f,avx512vl")]
9562 unsafe fn test_mm_maskz_shuffle_pd() {
9563 let a = _mm_set_pd(1., 4.);
9564 let b = _mm_set_pd(2., 3.);
9565 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
9566 assert_eq_m128d(r, _mm_setzero_pd());
9567 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
9568 let e = _mm_set_pd(2., 1.);
9569 assert_eq_m128d(r, e);
9570 }
9571
9572 #[simd_test(enable = "avx512f")]
9573 unsafe fn test_mm512_shuffle_i64x2() {
9574 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
9575 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
9576 let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
9577 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
9578 assert_eq_m512i(r, e);
9579 }
9580
9581 #[simd_test(enable = "avx512f")]
9582 unsafe fn test_mm512_mask_shuffle_i64x2() {
9583 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
9584 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
9585 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
9586 assert_eq_m512i(r, a);
9587 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
9588 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
9589 assert_eq_m512i(r, e);
9590 }
9591
9592 #[simd_test(enable = "avx512f")]
9593 unsafe fn test_mm512_maskz_shuffle_i64x2() {
9594 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
9595 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
9596 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
9597 assert_eq_m512i(r, _mm512_setzero_si512());
9598 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
9599 let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
9600 assert_eq_m512i(r, e);
9601 }
9602
9603 #[simd_test(enable = "avx512f,avx512vl")]
9604 unsafe fn test_mm256_shuffle_i64x2() {
9605 let a = _mm256_set_epi64x(1, 4, 5, 8);
9606 let b = _mm256_set_epi64x(2, 3, 6, 7);
9607 let r = _mm256_shuffle_i64x2::<0b00>(a, b);
9608 let e = _mm256_set_epi64x(6, 7, 5, 8);
9609 assert_eq_m256i(r, e);
9610 }
9611
9612 #[simd_test(enable = "avx512f,avx512vl")]
9613 unsafe fn test_mm256_mask_shuffle_i64x2() {
9614 let a = _mm256_set_epi64x(1, 4, 5, 8);
9615 let b = _mm256_set_epi64x(2, 3, 6, 7);
9616 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
9617 assert_eq_m256i(r, a);
9618 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
9619 let e = _mm256_set_epi64x(6, 7, 5, 8);
9620 assert_eq_m256i(r, e);
9621 }
9622
9623 #[simd_test(enable = "avx512f,avx512vl")]
9624 unsafe fn test_mm256_maskz_shuffle_i64x2() {
9625 let a = _mm256_set_epi64x(1, 4, 5, 8);
9626 let b = _mm256_set_epi64x(2, 3, 6, 7);
9627 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
9628 assert_eq_m256i(r, _mm256_setzero_si256());
9629 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
9630 let e = _mm256_set_epi64x(6, 7, 5, 8);
9631 assert_eq_m256i(r, e);
9632 }
9633
9634 #[simd_test(enable = "avx512f")]
9635 unsafe fn test_mm512_shuffle_f64x2() {
9636 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
9637 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
9638 let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
9639 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
9640 assert_eq_m512d(r, e);
9641 }
9642
9643 #[simd_test(enable = "avx512f")]
9644 unsafe fn test_mm512_mask_shuffle_f64x2() {
9645 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
9646 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
9647 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
9648 assert_eq_m512d(r, a);
9649 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
9650 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
9651 assert_eq_m512d(r, e);
9652 }
9653
9654 #[simd_test(enable = "avx512f")]
9655 unsafe fn test_mm512_maskz_shuffle_f64x2() {
9656 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
9657 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
9658 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
9659 assert_eq_m512d(r, _mm512_setzero_pd());
9660 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
9661 let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
9662 assert_eq_m512d(r, e);
9663 }
9664
9665 #[simd_test(enable = "avx512f,avx512vl")]
9666 unsafe fn test_mm256_shuffle_f64x2() {
9667 let a = _mm256_set_pd(1., 4., 5., 8.);
9668 let b = _mm256_set_pd(2., 3., 6., 7.);
9669 let r = _mm256_shuffle_f64x2::<0b00>(a, b);
9670 let e = _mm256_set_pd(6., 7., 5., 8.);
9671 assert_eq_m256d(r, e);
9672 }
9673
9674 #[simd_test(enable = "avx512f,avx512vl")]
9675 unsafe fn test_mm256_mask_shuffle_f64x2() {
9676 let a = _mm256_set_pd(1., 4., 5., 8.);
9677 let b = _mm256_set_pd(2., 3., 6., 7.);
9678 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
9679 assert_eq_m256d(r, a);
9680 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
9681 let e = _mm256_set_pd(6., 7., 5., 8.);
9682 assert_eq_m256d(r, e);
9683 }
9684
9685 #[simd_test(enable = "avx512f,avx512vl")]
9686 unsafe fn test_mm256_maskz_shuffle_f64x2() {
9687 let a = _mm256_set_pd(1., 4., 5., 8.);
9688 let b = _mm256_set_pd(2., 3., 6., 7.);
9689 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
9690 assert_eq_m256d(r, _mm256_setzero_pd());
9691 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
9692 let e = _mm256_set_pd(6., 7., 5., 8.);
9693 assert_eq_m256d(r, e);
9694 }
9695
9696 #[simd_test(enable = "avx512f")]
9697 unsafe fn test_mm512_movedup_pd() {
9698 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9699 let r = _mm512_movedup_pd(a);
9700 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9701 assert_eq_m512d(r, e);
9702 }
9703
9704 #[simd_test(enable = "avx512f")]
9705 unsafe fn test_mm512_mask_movedup_pd() {
9706 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9707 let r = _mm512_mask_movedup_pd(a, 0, a);
9708 assert_eq_m512d(r, a);
9709 let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
9710 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9711 assert_eq_m512d(r, e);
9712 }
9713
9714 #[simd_test(enable = "avx512f")]
9715 unsafe fn test_mm512_maskz_movedup_pd() {
9716 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9717 let r = _mm512_maskz_movedup_pd(0, a);
9718 assert_eq_m512d(r, _mm512_setzero_pd());
9719 let r = _mm512_maskz_movedup_pd(0b00001111, a);
9720 let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
9721 assert_eq_m512d(r, e);
9722 }
9723
9724 #[simd_test(enable = "avx512f,avx512vl")]
9725 unsafe fn test_mm256_mask_movedup_pd() {
9726 let a = _mm256_set_pd(1., 2., 3., 4.);
9727 let r = _mm256_mask_movedup_pd(a, 0, a);
9728 assert_eq_m256d(r, a);
9729 let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
9730 let e = _mm256_set_pd(2., 2., 4., 4.);
9731 assert_eq_m256d(r, e);
9732 }
9733
9734 #[simd_test(enable = "avx512f,avx512vl")]
9735 unsafe fn test_mm256_maskz_movedup_pd() {
9736 let a = _mm256_set_pd(1., 2., 3., 4.);
9737 let r = _mm256_maskz_movedup_pd(0, a);
9738 assert_eq_m256d(r, _mm256_setzero_pd());
9739 let r = _mm256_maskz_movedup_pd(0b00001111, a);
9740 let e = _mm256_set_pd(2., 2., 4., 4.);
9741 assert_eq_m256d(r, e);
9742 }
9743
9744 #[simd_test(enable = "avx512f,avx512vl")]
9745 unsafe fn test_mm_mask_movedup_pd() {
9746 let a = _mm_set_pd(1., 2.);
9747 let r = _mm_mask_movedup_pd(a, 0, a);
9748 assert_eq_m128d(r, a);
9749 let r = _mm_mask_movedup_pd(a, 0b00000011, a);
9750 let e = _mm_set_pd(2., 2.);
9751 assert_eq_m128d(r, e);
9752 }
9753
9754 #[simd_test(enable = "avx512f,avx512vl")]
9755 unsafe fn test_mm_maskz_movedup_pd() {
9756 let a = _mm_set_pd(1., 2.);
9757 let r = _mm_maskz_movedup_pd(0, a);
9758 assert_eq_m128d(r, _mm_setzero_pd());
9759 let r = _mm_maskz_movedup_pd(0b00000011, a);
9760 let e = _mm_set_pd(2., 2.);
9761 assert_eq_m128d(r, e);
9762 }
9763
9764 #[simd_test(enable = "avx512f")]
9765 unsafe fn test_mm512_inserti64x4() {
9766 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
9767 let b = _mm256_setr_epi64x(17, 18, 19, 20);
9768 let r = _mm512_inserti64x4::<1>(a, b);
9769 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
9770 assert_eq_m512i(r, e);
9771 }
9772
9773 #[simd_test(enable = "avx512f")]
9774 unsafe fn test_mm512_mask_inserti64x4() {
9775 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
9776 let b = _mm256_setr_epi64x(17, 18, 19, 20);
9777 let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
9778 assert_eq_m512i(r, a);
9779 let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
9780 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
9781 assert_eq_m512i(r, e);
9782 }
9783
9784 #[simd_test(enable = "avx512f")]
9785 unsafe fn test_mm512_maskz_inserti64x4() {
9786 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
9787 let b = _mm256_setr_epi64x(17, 18, 19, 20);
9788 let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
9789 assert_eq_m512i(r, _mm512_setzero_si512());
9790 let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
9791 let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
9792 assert_eq_m512i(r, e);
9793 }
9794
9795 #[simd_test(enable = "avx512f")]
9796 unsafe fn test_mm512_insertf64x4() {
9797 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9798 let b = _mm256_setr_pd(17., 18., 19., 20.);
9799 let r = _mm512_insertf64x4::<1>(a, b);
9800 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
9801 assert_eq_m512d(r, e);
9802 }
9803
9804 #[simd_test(enable = "avx512f")]
9805 unsafe fn test_mm512_mask_insertf64x4() {
9806 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9807 let b = _mm256_setr_pd(17., 18., 19., 20.);
9808 let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
9809 assert_eq_m512d(r, a);
9810 let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
9811 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
9812 assert_eq_m512d(r, e);
9813 }
9814
9815 #[simd_test(enable = "avx512f")]
9816 unsafe fn test_mm512_maskz_insertf64x4() {
9817 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
9818 let b = _mm256_setr_pd(17., 18., 19., 20.);
9819 let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
9820 assert_eq_m512d(r, _mm512_setzero_pd());
9821 let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
9822 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
9823 assert_eq_m512d(r, e);
9824 }
9825
9826 #[simd_test(enable = "avx512f")]
9827 unsafe fn test_mm512_castpd128_pd512() {
9828 let a = _mm_setr_pd(17., 18.);
9829 let r = _mm512_castpd128_pd512(a);
9830 let e = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
9831 assert_eq_m512d(r, e);
9832 }
9833
9834 #[simd_test(enable = "avx512f")]
9835 unsafe fn test_mm512_castpd256_pd512() {
9836 let a = _mm256_setr_pd(17., 18., 19., 20.);
9837 let r = _mm512_castpd256_pd512(a);
9838 let e = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
9839 assert_eq_m512d(r, e);
9840 }
9841
9842 #[simd_test(enable = "avx512f")]
9843 unsafe fn test_mm512_zextpd128_pd512() {
9844 let a = _mm_setr_pd(17., 18.);
9845 let r = _mm512_zextpd128_pd512(a);
9846 let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
9847 assert_eq_m512d(r, e);
9848 }
9849
9850 #[simd_test(enable = "avx512f")]
9851 unsafe fn test_mm512_zextpd256_pd512() {
9852 let a = _mm256_setr_pd(17., 18., 19., 20.);
9853 let r = _mm512_zextpd256_pd512(a);
9854 let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
9855 assert_eq_m512d(r, e);
9856 }
9857
9858 #[simd_test(enable = "avx512f")]
9859 unsafe fn test_mm512_castpd512_pd128() {
9860 let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
9861 let r = _mm512_castpd512_pd128(a);
9862 let e = _mm_setr_pd(17., 18.);
9863 assert_eq_m128d(r, e);
9864 }
9865
9866 #[simd_test(enable = "avx512f")]
9867 unsafe fn test_mm512_castpd512_pd256() {
9868 let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
9869 let r = _mm512_castpd512_pd256(a);
9870 let e = _mm256_setr_pd(17., 18., 19., 20.);
9871 assert_eq_m256d(r, e);
9872 }
9873
9874 #[simd_test(enable = "avx512f")]
9875 unsafe fn test_mm512_castpd_ps() {
9876 let a = _mm512_set1_pd(1.);
9877 let r = _mm512_castpd_ps(a);
9878 let e = _mm512_set_ps(
9879 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
9880 1.875, 0.0,
9881 );
9882 assert_eq_m512(r, e);
9883 }
9884
9885 #[simd_test(enable = "avx512f")]
9886 unsafe fn test_mm512_castpd_si512() {
9887 let a = _mm512_set1_pd(1.);
9888 let r = _mm512_castpd_si512(a);
9889 let e = _mm512_set_epi32(
9890 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
9891 0, 1072693248, 0, 1072693248, 0,
9892 );
9893 assert_eq_m512i(r, e);
9894 }
9895
9896 #[simd_test(enable = "avx512f")]
9897 unsafe fn test_mm512_castsi128_si512() {
9898 let a = _mm_setr_epi64x(17, 18);
9899 let r = _mm512_castsi128_si512(a);
9900 let e = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
9901 assert_eq_m512i(r, e);
9902 }
9903
9904 #[simd_test(enable = "avx512f")]
9905 unsafe fn test_mm512_castsi256_si512() {
9906 let a = _mm256_setr_epi64x(17, 18, 19, 20);
9907 let r = _mm512_castsi256_si512(a);
9908 let e = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
9909 assert_eq_m512i(r, e);
9910 }
9911
9912 #[simd_test(enable = "avx512f")]
9913 unsafe fn test_mm512_zextsi128_si512() {
9914 let a = _mm_setr_epi64x(17, 18);
9915 let r = _mm512_zextsi128_si512(a);
9916 let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
9917 assert_eq_m512i(r, e);
9918 }
9919
9920 #[simd_test(enable = "avx512f")]
9921 unsafe fn test_mm512_zextsi256_si512() {
9922 let a = _mm256_setr_epi64x(17, 18, 19, 20);
9923 let r = _mm512_zextsi256_si512(a);
9924 let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
9925 assert_eq_m512i(r, e);
9926 }
9927
9928 #[simd_test(enable = "avx512f")]
9929 unsafe fn test_mm512_castsi512_si128() {
9930 let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
9931 let r = _mm512_castsi512_si128(a);
9932 let e = _mm_setr_epi64x(17, 18);
9933 assert_eq_m128i(r, e);
9934 }
9935
9936 #[simd_test(enable = "avx512f")]
9937 unsafe fn test_mm512_castsi512_si256() {
9938 let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
9939 let r = _mm512_castsi512_si256(a);
9940 let e = _mm256_setr_epi64x(17, 18, 19, 20);
9941 assert_eq_m256i(r, e);
9942 }
9943
9944 #[simd_test(enable = "avx512f")]
9945 unsafe fn test_mm512_castsi512_ps() {
9946 let a = _mm512_set1_epi64(1 << 62);
9947 let r = _mm512_castsi512_ps(a);
9948 let e = _mm512_set_ps(
9949 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
9950 );
9951 assert_eq_m512(r, e);
9952 }
9953
9954 #[simd_test(enable = "avx512f")]
9955 unsafe fn test_mm512_castsi512_pd() {
9956 let a = _mm512_set1_epi64(1 << 62);
9957 let r = _mm512_castsi512_pd(a);
9958 let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
9959 assert_eq_m512d(r, e);
9960 }
9961
9962 #[simd_test(enable = "avx512f")]
9963 unsafe fn test_mm512_broadcastq_epi64() {
9964 let a = _mm_setr_epi64x(17, 18);
9965 let r = _mm512_broadcastq_epi64(a);
9966 let e = _mm512_set1_epi64(17);
9967 assert_eq_m512i(r, e);
9968 }
9969
9970 #[simd_test(enable = "avx512f")]
9971 unsafe fn test_mm512_mask_broadcastq_epi64() {
9972 let src = _mm512_set1_epi64(18);
9973 let a = _mm_setr_epi64x(17, 18);
9974 let r = _mm512_mask_broadcastq_epi64(src, 0, a);
9975 assert_eq_m512i(r, src);
9976 let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
9977 let e = _mm512_set1_epi64(17);
9978 assert_eq_m512i(r, e);
9979 }
9980
9981 #[simd_test(enable = "avx512f")]
9982 unsafe fn test_mm512_maskz_broadcastq_epi64() {
9983 let a = _mm_setr_epi64x(17, 18);
9984 let r = _mm512_maskz_broadcastq_epi64(0, a);
9985 assert_eq_m512i(r, _mm512_setzero_si512());
9986 let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
9987 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
9988 assert_eq_m512i(r, e);
9989 }
9990
9991 #[simd_test(enable = "avx512f,avx512vl")]
9992 unsafe fn test_mm256_mask_broadcastq_epi64() {
9993 let src = _mm256_set1_epi64x(18);
9994 let a = _mm_set_epi64x(17, 18);
9995 let r = _mm256_mask_broadcastq_epi64(src, 0, a);
9996 assert_eq_m256i(r, src);
9997 let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
9998 let e = _mm256_set1_epi64x(18);
9999 assert_eq_m256i(r, e);
10000 }
10001
10002 #[simd_test(enable = "avx512f,avx512vl")]
10003 unsafe fn test_mm256_maskz_broadcastq_epi64() {
10004 let a = _mm_set_epi64x(17, 18);
10005 let r = _mm256_maskz_broadcastq_epi64(0, a);
10006 assert_eq_m256i(r, _mm256_setzero_si256());
10007 let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10008 let e = _mm256_set1_epi64x(18);
10009 assert_eq_m256i(r, e);
10010 }
10011
10012 #[simd_test(enable = "avx512f,avx512vl")]
10013 unsafe fn test_mm_mask_broadcastq_epi64() {
10014 let src = _mm_set1_epi64x(18);
10015 let a = _mm_set_epi64x(17, 18);
10016 let r = _mm_mask_broadcastq_epi64(src, 0, a);
10017 assert_eq_m128i(r, src);
10018 let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10019 let e = _mm_set1_epi64x(18);
10020 assert_eq_m128i(r, e);
10021 }
10022
10023 #[simd_test(enable = "avx512f,avx512vl")]
10024 unsafe fn test_mm_maskz_broadcastq_epi64() {
10025 let a = _mm_set_epi64x(17, 18);
10026 let r = _mm_maskz_broadcastq_epi64(0, a);
10027 assert_eq_m128i(r, _mm_setzero_si128());
10028 let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10029 let e = _mm_set1_epi64x(18);
10030 assert_eq_m128i(r, e);
10031 }
10032
10033 #[simd_test(enable = "avx512f")]
10034 unsafe fn test_mm512_broadcastsd_pd() {
10035 let a = _mm_set_pd(17., 18.);
10036 let r = _mm512_broadcastsd_pd(a);
10037 let e = _mm512_set1_pd(18.);
10038 assert_eq_m512d(r, e);
10039 }
10040
10041 #[simd_test(enable = "avx512f")]
10042 unsafe fn test_mm512_mask_broadcastsd_pd() {
10043 let src = _mm512_set1_pd(18.);
10044 let a = _mm_set_pd(17., 18.);
10045 let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10046 assert_eq_m512d(r, src);
10047 let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10048 let e = _mm512_set1_pd(18.);
10049 assert_eq_m512d(r, e);
10050 }
10051
10052 #[simd_test(enable = "avx512f")]
10053 unsafe fn test_mm512_maskz_broadcastsd_pd() {
10054 let a = _mm_set_pd(17., 18.);
10055 let r = _mm512_maskz_broadcastsd_pd(0, a);
10056 assert_eq_m512d(r, _mm512_setzero_pd());
10057 let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10058 let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10059 assert_eq_m512d(r, e);
10060 }
10061
10062 #[simd_test(enable = "avx512f,avx512vl")]
10063 unsafe fn test_mm256_mask_broadcastsd_pd() {
10064 let src = _mm256_set1_pd(18.);
10065 let a = _mm_set_pd(17., 18.);
10066 let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10067 assert_eq_m256d(r, src);
10068 let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10069 let e = _mm256_set1_pd(18.);
10070 assert_eq_m256d(r, e);
10071 }
10072
10073 #[simd_test(enable = "avx512f,avx512vl")]
10074 unsafe fn test_mm256_maskz_broadcastsd_pd() {
10075 let a = _mm_set_pd(17., 18.);
10076 let r = _mm256_maskz_broadcastsd_pd(0, a);
10077 assert_eq_m256d(r, _mm256_setzero_pd());
10078 let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10079 let e = _mm256_set1_pd(18.);
10080 assert_eq_m256d(r, e);
10081 }
10082
10083 #[simd_test(enable = "avx512f")]
10084 unsafe fn test_mm512_broadcast_i64x4() {
10085 let a = _mm256_set_epi64x(17, 18, 19, 20);
10086 let r = _mm512_broadcast_i64x4(a);
10087 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10088 assert_eq_m512i(r, e);
10089 }
10090
10091 #[simd_test(enable = "avx512f")]
10092 unsafe fn test_mm512_mask_broadcast_i64x4() {
10093 let src = _mm512_set1_epi64(18);
10094 let a = _mm256_set_epi64x(17, 18, 19, 20);
10095 let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10096 assert_eq_m512i(r, src);
10097 let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10098 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10099 assert_eq_m512i(r, e);
10100 }
10101
10102 #[simd_test(enable = "avx512f")]
10103 unsafe fn test_mm512_maskz_broadcast_i64x4() {
10104 let a = _mm256_set_epi64x(17, 18, 19, 20);
10105 let r = _mm512_maskz_broadcast_i64x4(0, a);
10106 assert_eq_m512i(r, _mm512_setzero_si512());
10107 let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10108 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10109 assert_eq_m512i(r, e);
10110 }
10111
10112 #[simd_test(enable = "avx512f")]
10113 unsafe fn test_mm512_broadcast_f64x4() {
10114 let a = _mm256_set_pd(17., 18., 19., 20.);
10115 let r = _mm512_broadcast_f64x4(a);
10116 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10117 assert_eq_m512d(r, e);
10118 }
10119
10120 #[simd_test(enable = "avx512f")]
10121 unsafe fn test_mm512_mask_broadcast_f64x4() {
10122 let src = _mm512_set1_pd(18.);
10123 let a = _mm256_set_pd(17., 18., 19., 20.);
10124 let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10125 assert_eq_m512d(r, src);
10126 let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10127 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10128 assert_eq_m512d(r, e);
10129 }
10130
10131 #[simd_test(enable = "avx512f")]
10132 unsafe fn test_mm512_maskz_broadcast_f64x4() {
10133 let a = _mm256_set_pd(17., 18., 19., 20.);
10134 let r = _mm512_maskz_broadcast_f64x4(0, a);
10135 assert_eq_m512d(r, _mm512_setzero_pd());
10136 let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10137 let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10138 assert_eq_m512d(r, e);
10139 }
10140
10141 #[simd_test(enable = "avx512f")]
10142 unsafe fn test_mm512_mask_blend_epi64() {
10143 let a = _mm512_set1_epi64(1);
10144 let b = _mm512_set1_epi64(2);
10145 let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10146 let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10147 assert_eq_m512i(r, e);
10148 }
10149
10150 #[simd_test(enable = "avx512f,avx512vl")]
10151 unsafe fn test_mm256_mask_blend_epi64() {
10152 let a = _mm256_set1_epi64x(1);
10153 let b = _mm256_set1_epi64x(2);
10154 let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10155 let e = _mm256_set1_epi64x(2);
10156 assert_eq_m256i(r, e);
10157 }
10158
10159 #[simd_test(enable = "avx512f,avx512vl")]
10160 unsafe fn test_mm_mask_blend_epi64() {
10161 let a = _mm_set1_epi64x(1);
10162 let b = _mm_set1_epi64x(2);
10163 let r = _mm_mask_blend_epi64(0b00000011, a, b);
10164 let e = _mm_set1_epi64x(2);
10165 assert_eq_m128i(r, e);
10166 }
10167
10168 #[simd_test(enable = "avx512f")]
10169 unsafe fn test_mm512_mask_blend_pd() {
10170 let a = _mm512_set1_pd(1.);
10171 let b = _mm512_set1_pd(2.);
10172 let r = _mm512_mask_blend_pd(0b11110000, a, b);
10173 let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10174 assert_eq_m512d(r, e);
10175 }
10176
10177 #[simd_test(enable = "avx512f,avx512vl")]
10178 unsafe fn test_mm256_mask_blend_pd() {
10179 let a = _mm256_set1_pd(1.);
10180 let b = _mm256_set1_pd(2.);
10181 let r = _mm256_mask_blend_pd(0b00001111, a, b);
10182 let e = _mm256_set1_pd(2.);
10183 assert_eq_m256d(r, e);
10184 }
10185
10186 #[simd_test(enable = "avx512f,avx512vl")]
10187 unsafe fn test_mm_mask_blend_pd() {
10188 let a = _mm_set1_pd(1.);
10189 let b = _mm_set1_pd(2.);
10190 let r = _mm_mask_blend_pd(0b00000011, a, b);
10191 let e = _mm_set1_pd(2.);
10192 assert_eq_m128d(r, e);
10193 }
10194
10195 #[simd_test(enable = "avx512f")]
10196 unsafe fn test_mm512_unpackhi_epi64() {
10197 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10198 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10199 let r = _mm512_unpackhi_epi64(a, b);
10200 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10201 assert_eq_m512i(r, e);
10202 }
10203
10204 #[simd_test(enable = "avx512f")]
10205 unsafe fn test_mm512_mask_unpackhi_epi64() {
10206 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10207 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10208 let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10209 assert_eq_m512i(r, a);
10210 let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10211 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10212 assert_eq_m512i(r, e);
10213 }
10214
10215 #[simd_test(enable = "avx512f")]
10216 unsafe fn test_mm512_maskz_unpackhi_epi64() {
10217 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10218 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10219 let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10220 assert_eq_m512i(r, _mm512_setzero_si512());
10221 let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10222 let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10223 assert_eq_m512i(r, e);
10224 }
10225
10226 #[simd_test(enable = "avx512f,avx512vl")]
10227 unsafe fn test_mm256_mask_unpackhi_epi64() {
10228 let a = _mm256_set_epi64x(1, 2, 3, 4);
10229 let b = _mm256_set_epi64x(17, 18, 19, 20);
10230 let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10231 assert_eq_m256i(r, a);
10232 let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10233 let e = _mm256_set_epi64x(17, 1, 19, 3);
10234 assert_eq_m256i(r, e);
10235 }
10236
10237 #[simd_test(enable = "avx512f,avx512vl")]
10238 unsafe fn test_mm256_maskz_unpackhi_epi64() {
10239 let a = _mm256_set_epi64x(1, 2, 3, 4);
10240 let b = _mm256_set_epi64x(17, 18, 19, 20);
10241 let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10242 assert_eq_m256i(r, _mm256_setzero_si256());
10243 let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10244 let e = _mm256_set_epi64x(17, 1, 19, 3);
10245 assert_eq_m256i(r, e);
10246 }
10247
10248 #[simd_test(enable = "avx512f,avx512vl")]
10249 unsafe fn test_mm_mask_unpackhi_epi64() {
10250 let a = _mm_set_epi64x(1, 2);
10251 let b = _mm_set_epi64x(17, 18);
10252 let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10253 assert_eq_m128i(r, a);
10254 let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10255 let e = _mm_set_epi64x(17, 1);
10256 assert_eq_m128i(r, e);
10257 }
10258
10259 #[simd_test(enable = "avx512f,avx512vl")]
10260 unsafe fn test_mm_maskz_unpackhi_epi64() {
10261 let a = _mm_set_epi64x(1, 2);
10262 let b = _mm_set_epi64x(17, 18);
10263 let r = _mm_maskz_unpackhi_epi64(0, a, b);
10264 assert_eq_m128i(r, _mm_setzero_si128());
10265 let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10266 let e = _mm_set_epi64x(17, 1);
10267 assert_eq_m128i(r, e);
10268 }
10269
10270 #[simd_test(enable = "avx512f")]
10271 unsafe fn test_mm512_unpackhi_pd() {
10272 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10273 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10274 let r = _mm512_unpackhi_pd(a, b);
10275 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10276 assert_eq_m512d(r, e);
10277 }
10278
10279 #[simd_test(enable = "avx512f")]
10280 unsafe fn test_mm512_mask_unpackhi_pd() {
10281 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10282 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10283 let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10284 assert_eq_m512d(r, a);
10285 let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10286 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10287 assert_eq_m512d(r, e);
10288 }
10289
10290 #[simd_test(enable = "avx512f")]
10291 unsafe fn test_mm512_maskz_unpackhi_pd() {
10292 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10293 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10294 let r = _mm512_maskz_unpackhi_pd(0, a, b);
10295 assert_eq_m512d(r, _mm512_setzero_pd());
10296 let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
10297 let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
10298 assert_eq_m512d(r, e);
10299 }
10300
10301 #[simd_test(enable = "avx512f,avx512vl")]
10302 unsafe fn test_mm256_mask_unpackhi_pd() {
10303 let a = _mm256_set_pd(1., 2., 3., 4.);
10304 let b = _mm256_set_pd(17., 18., 19., 20.);
10305 let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
10306 assert_eq_m256d(r, a);
10307 let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
10308 let e = _mm256_set_pd(17., 1., 19., 3.);
10309 assert_eq_m256d(r, e);
10310 }
10311
10312 #[simd_test(enable = "avx512f,avx512vl")]
10313 unsafe fn test_mm256_maskz_unpackhi_pd() {
10314 let a = _mm256_set_pd(1., 2., 3., 4.);
10315 let b = _mm256_set_pd(17., 18., 19., 20.);
10316 let r = _mm256_maskz_unpackhi_pd(0, a, b);
10317 assert_eq_m256d(r, _mm256_setzero_pd());
10318 let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
10319 let e = _mm256_set_pd(17., 1., 19., 3.);
10320 assert_eq_m256d(r, e);
10321 }
10322
10323 #[simd_test(enable = "avx512f,avx512vl")]
10324 unsafe fn test_mm_mask_unpackhi_pd() {
10325 let a = _mm_set_pd(1., 2.);
10326 let b = _mm_set_pd(17., 18.);
10327 let r = _mm_mask_unpackhi_pd(a, 0, a, b);
10328 assert_eq_m128d(r, a);
10329 let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
10330 let e = _mm_set_pd(17., 1.);
10331 assert_eq_m128d(r, e);
10332 }
10333
10334 #[simd_test(enable = "avx512f,avx512vl")]
10335 unsafe fn test_mm_maskz_unpackhi_pd() {
10336 let a = _mm_set_pd(1., 2.);
10337 let b = _mm_set_pd(17., 18.);
10338 let r = _mm_maskz_unpackhi_pd(0, a, b);
10339 assert_eq_m128d(r, _mm_setzero_pd());
10340 let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
10341 let e = _mm_set_pd(17., 1.);
10342 assert_eq_m128d(r, e);
10343 }
10344
10345 #[simd_test(enable = "avx512f")]
10346 unsafe fn test_mm512_unpacklo_epi64() {
10347 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10348 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10349 let r = _mm512_unpacklo_epi64(a, b);
10350 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
10351 assert_eq_m512i(r, e);
10352 }
10353
10354 #[simd_test(enable = "avx512f")]
10355 unsafe fn test_mm512_mask_unpacklo_epi64() {
10356 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10357 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10358 let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
10359 assert_eq_m512i(r, a);
10360 let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
10361 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
10362 assert_eq_m512i(r, e);
10363 }
10364
10365 #[simd_test(enable = "avx512f")]
10366 unsafe fn test_mm512_maskz_unpacklo_epi64() {
10367 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10368 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10369 let r = _mm512_maskz_unpacklo_epi64(0, a, b);
10370 assert_eq_m512i(r, _mm512_setzero_si512());
10371 let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
10372 let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
10373 assert_eq_m512i(r, e);
10374 }
10375
10376 #[simd_test(enable = "avx512f,avx512vl")]
10377 unsafe fn test_mm256_mask_unpacklo_epi64() {
10378 let a = _mm256_set_epi64x(1, 2, 3, 4);
10379 let b = _mm256_set_epi64x(17, 18, 19, 20);
10380 let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
10381 assert_eq_m256i(r, a);
10382 let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
10383 let e = _mm256_set_epi64x(18, 2, 20, 4);
10384 assert_eq_m256i(r, e);
10385 }
10386
10387 #[simd_test(enable = "avx512f,avx512vl")]
10388 unsafe fn test_mm256_maskz_unpacklo_epi64() {
10389 let a = _mm256_set_epi64x(1, 2, 3, 4);
10390 let b = _mm256_set_epi64x(17, 18, 19, 20);
10391 let r = _mm256_maskz_unpacklo_epi64(0, a, b);
10392 assert_eq_m256i(r, _mm256_setzero_si256());
10393 let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
10394 let e = _mm256_set_epi64x(18, 2, 20, 4);
10395 assert_eq_m256i(r, e);
10396 }
10397
10398 #[simd_test(enable = "avx512f,avx512vl")]
10399 unsafe fn test_mm_mask_unpacklo_epi64() {
10400 let a = _mm_set_epi64x(1, 2);
10401 let b = _mm_set_epi64x(17, 18);
10402 let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
10403 assert_eq_m128i(r, a);
10404 let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
10405 let e = _mm_set_epi64x(18, 2);
10406 assert_eq_m128i(r, e);
10407 }
10408
10409 #[simd_test(enable = "avx512f,avx512vl")]
10410 unsafe fn test_mm_maskz_unpacklo_epi64() {
10411 let a = _mm_set_epi64x(1, 2);
10412 let b = _mm_set_epi64x(17, 18);
10413 let r = _mm_maskz_unpacklo_epi64(0, a, b);
10414 assert_eq_m128i(r, _mm_setzero_si128());
10415 let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
10416 let e = _mm_set_epi64x(18, 2);
10417 assert_eq_m128i(r, e);
10418 }
10419
10420 #[simd_test(enable = "avx512f")]
10421 unsafe fn test_mm512_unpacklo_pd() {
10422 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10423 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10424 let r = _mm512_unpacklo_pd(a, b);
10425 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
10426 assert_eq_m512d(r, e);
10427 }
10428
10429 #[simd_test(enable = "avx512f")]
10430 unsafe fn test_mm512_mask_unpacklo_pd() {
10431 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10432 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10433 let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
10434 assert_eq_m512d(r, a);
10435 let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
10436 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
10437 assert_eq_m512d(r, e);
10438 }
10439
10440 #[simd_test(enable = "avx512f")]
10441 unsafe fn test_mm512_maskz_unpacklo_pd() {
10442 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10443 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10444 let r = _mm512_maskz_unpacklo_pd(0, a, b);
10445 assert_eq_m512d(r, _mm512_setzero_pd());
10446 let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
10447 let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
10448 assert_eq_m512d(r, e);
10449 }
10450
10451 #[simd_test(enable = "avx512f,avx512vl")]
10452 unsafe fn test_mm256_mask_unpacklo_pd() {
10453 let a = _mm256_set_pd(1., 2., 3., 4.);
10454 let b = _mm256_set_pd(17., 18., 19., 20.);
10455 let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
10456 assert_eq_m256d(r, a);
10457 let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
10458 let e = _mm256_set_pd(18., 2., 20., 4.);
10459 assert_eq_m256d(r, e);
10460 }
10461
10462 #[simd_test(enable = "avx512f,avx512vl")]
10463 unsafe fn test_mm256_maskz_unpacklo_pd() {
10464 let a = _mm256_set_pd(1., 2., 3., 4.);
10465 let b = _mm256_set_pd(17., 18., 19., 20.);
10466 let r = _mm256_maskz_unpacklo_pd(0, a, b);
10467 assert_eq_m256d(r, _mm256_setzero_pd());
10468 let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
10469 let e = _mm256_set_pd(18., 2., 20., 4.);
10470 assert_eq_m256d(r, e);
10471 }
10472
10473 #[simd_test(enable = "avx512f,avx512vl")]
10474 unsafe fn test_mm_mask_unpacklo_pd() {
10475 let a = _mm_set_pd(1., 2.);
10476 let b = _mm_set_pd(17., 18.);
10477 let r = _mm_mask_unpacklo_pd(a, 0, a, b);
10478 assert_eq_m128d(r, a);
10479 let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
10480 let e = _mm_set_pd(18., 2.);
10481 assert_eq_m128d(r, e);
10482 }
10483
10484 #[simd_test(enable = "avx512f,avx512vl")]
10485 unsafe fn test_mm_maskz_unpacklo_pd() {
10486 let a = _mm_set_pd(1., 2.);
10487 let b = _mm_set_pd(17., 18.);
10488 let r = _mm_maskz_unpacklo_pd(0, a, b);
10489 assert_eq_m128d(r, _mm_setzero_pd());
10490 let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
10491 let e = _mm_set_pd(18., 2.);
10492 assert_eq_m128d(r, e);
10493 }
10494
10495 #[simd_test(enable = "avx512f")]
10496 unsafe fn test_mm512_alignr_epi64() {
10497 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
10498 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
10499 let r = _mm512_alignr_epi64::<0>(a, b);
10500 assert_eq_m512i(r, b);
10501 let r = _mm512_alignr_epi64::<8>(a, b);
10502 assert_eq_m512i(r, b);
10503 let r = _mm512_alignr_epi64::<1>(a, b);
10504 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
10505 assert_eq_m512i(r, e);
10506 }
10507
10508 #[simd_test(enable = "avx512f")]
10509 unsafe fn test_mm512_mask_alignr_epi64() {
10510 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
10511 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
10512 let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
10513 assert_eq_m512i(r, a);
10514 let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
10515 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
10516 assert_eq_m512i(r, e);
10517 }
10518
10519 #[simd_test(enable = "avx512f")]
10520 unsafe fn test_mm512_maskz_alignr_epi64() {
10521 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
10522 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
10523 let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
10524 assert_eq_m512i(r, _mm512_setzero_si512());
10525 let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
10526 let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
10527 assert_eq_m512i(r, e);
10528 }
10529
10530 #[simd_test(enable = "avx512f,avx512vl")]
10531 unsafe fn test_mm256_alignr_epi64() {
10532 let a = _mm256_set_epi64x(4, 3, 2, 1);
10533 let b = _mm256_set_epi64x(8, 7, 6, 5);
10534 let r = _mm256_alignr_epi64::<0>(a, b);
10535 let e = _mm256_set_epi64x(8, 7, 6, 5);
10536 assert_eq_m256i(r, e);
10537 let r = _mm256_alignr_epi64::<6>(a, b);
10538 let e = _mm256_set_epi64x(6, 5, 4, 3);
10539 assert_eq_m256i(r, e);
10540 }
10541
10542 #[simd_test(enable = "avx512f,avx512vl")]
10543 unsafe fn test_mm256_mask_alignr_epi64() {
10544 let a = _mm256_set_epi64x(4, 3, 2, 1);
10545 let b = _mm256_set_epi64x(8, 7, 6, 5);
10546 let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
10547 assert_eq_m256i(r, a);
10548 let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
10549 let e = _mm256_set_epi64x(8, 7, 6, 5);
10550 assert_eq_m256i(r, e);
10551 }
10552
10553 #[simd_test(enable = "avx512f,avx512vl")]
10554 unsafe fn test_mm256_maskz_alignr_epi64() {
10555 let a = _mm256_set_epi64x(4, 3, 2, 1);
10556 let b = _mm256_set_epi64x(8, 7, 6, 5);
10557 let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
10558 assert_eq_m256i(r, _mm256_setzero_si256());
10559 let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
10560 let e = _mm256_set_epi64x(8, 7, 6, 5);
10561 assert_eq_m256i(r, e);
10562 }
10563
10564 #[simd_test(enable = "avx512f,avx512vl")]
10565 unsafe fn test_mm_alignr_epi64() {
10566 let a = _mm_set_epi64x(2, 1);
10567 let b = _mm_set_epi64x(4, 3);
10568 let r = _mm_alignr_epi64::<0>(a, b);
10569 let e = _mm_set_epi64x(4, 3);
10570 assert_eq_m128i(r, e);
10571 }
10572
10573 #[simd_test(enable = "avx512f,avx512vl")]
10574 unsafe fn test_mm_mask_alignr_epi64() {
10575 let a = _mm_set_epi64x(2, 1);
10576 let b = _mm_set_epi64x(4, 3);
10577 let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
10578 assert_eq_m128i(r, a);
10579 let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
10580 let e = _mm_set_epi64x(4, 3);
10581 assert_eq_m128i(r, e);
10582 }
10583
10584 #[simd_test(enable = "avx512f,avx512vl")]
10585 unsafe fn test_mm_maskz_alignr_epi64() {
10586 let a = _mm_set_epi64x(2, 1);
10587 let b = _mm_set_epi64x(4, 3);
10588 let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
10589 assert_eq_m128i(r, _mm_setzero_si128());
10590 let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
10591 let e = _mm_set_epi64x(4, 3);
10592 assert_eq_m128i(r, e);
10593 }
10594
10595 #[simd_test(enable = "avx512f")]
10596 unsafe fn test_mm512_and_epi64() {
10597 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10598 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10599 let r = _mm512_and_epi64(a, b);
10600 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10601 assert_eq_m512i(r, e);
10602 }
10603
10604 #[simd_test(enable = "avx512f")]
10605 unsafe fn test_mm512_mask_and_epi64() {
10606 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10607 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10608 let r = _mm512_mask_and_epi64(a, 0, a, b);
10609 assert_eq_m512i(r, a);
10610 let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
10611 let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10612 assert_eq_m512i(r, e);
10613 }
10614
10615 #[simd_test(enable = "avx512f")]
10616 unsafe fn test_mm512_maskz_and_epi64() {
10617 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10618 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10619 let r = _mm512_maskz_and_epi64(0, a, b);
10620 assert_eq_m512i(r, _mm512_setzero_si512());
10621 let r = _mm512_maskz_and_epi64(0b00001111, a, b);
10622 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10623 assert_eq_m512i(r, e);
10624 }
10625
10626 #[simd_test(enable = "avx512f,avx512vl")]
10627 unsafe fn test_mm256_mask_and_epi64() {
10628 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10629 let b = _mm256_set1_epi64x(1 << 0);
10630 let r = _mm256_mask_and_epi64(a, 0, a, b);
10631 assert_eq_m256i(r, a);
10632 let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
10633 let e = _mm256_set1_epi64x(1 << 0);
10634 assert_eq_m256i(r, e);
10635 }
10636
10637 #[simd_test(enable = "avx512f,avx512vl")]
10638 unsafe fn test_mm256_maskz_and_epi64() {
10639 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10640 let b = _mm256_set1_epi64x(1 << 0);
10641 let r = _mm256_maskz_and_epi64(0, a, b);
10642 assert_eq_m256i(r, _mm256_setzero_si256());
10643 let r = _mm256_maskz_and_epi64(0b00001111, a, b);
10644 let e = _mm256_set1_epi64x(1 << 0);
10645 assert_eq_m256i(r, e);
10646 }
10647
10648 #[simd_test(enable = "avx512f,avx512vl")]
10649 unsafe fn test_mm_mask_and_epi64() {
10650 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10651 let b = _mm_set1_epi64x(1 << 0);
10652 let r = _mm_mask_and_epi64(a, 0, a, b);
10653 assert_eq_m128i(r, a);
10654 let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
10655 let e = _mm_set1_epi64x(1 << 0);
10656 assert_eq_m128i(r, e);
10657 }
10658
10659 #[simd_test(enable = "avx512f,avx512vl")]
10660 unsafe fn test_mm_maskz_and_epi64() {
10661 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10662 let b = _mm_set1_epi64x(1 << 0);
10663 let r = _mm_maskz_and_epi64(0, a, b);
10664 assert_eq_m128i(r, _mm_setzero_si128());
10665 let r = _mm_maskz_and_epi64(0b00000011, a, b);
10666 let e = _mm_set1_epi64x(1 << 0);
10667 assert_eq_m128i(r, e);
10668 }
10669
10670 #[simd_test(enable = "avx512f")]
10671 unsafe fn test_mm512_and_si512() {
10672 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10673 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10674 let r = _mm512_and_epi64(a, b);
10675 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10676 assert_eq_m512i(r, e);
10677 }
10678
10679 #[simd_test(enable = "avx512f")]
10680 unsafe fn test_mm512_or_epi64() {
10681 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10682 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10683 let r = _mm512_or_epi64(a, b);
10684 #[rustfmt::skip]
10685 let e = _mm512_set_epi64(
10686 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
10687 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
10688 );
10689 assert_eq_m512i(r, e);
10690 }
10691
10692 #[simd_test(enable = "avx512f")]
10693 unsafe fn test_mm512_mask_or_epi64() {
10694 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10695 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10696 let r = _mm512_mask_or_epi64(a, 0, a, b);
10697 assert_eq_m512i(r, a);
10698 let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
10699 #[rustfmt::skip]
10700 let e = _mm512_set_epi64(
10701 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
10702 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
10703 );
10704 assert_eq_m512i(r, e);
10705 }
10706
10707 #[simd_test(enable = "avx512f")]
10708 unsafe fn test_mm512_maskz_or_epi64() {
10709 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10710 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10711 let r = _mm512_maskz_or_epi64(0, a, b);
10712 assert_eq_m512i(r, _mm512_setzero_si512());
10713 let r = _mm512_maskz_or_epi64(0b00001111, a, b);
10714 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10715 assert_eq_m512i(r, e);
10716 }
10717
10718 #[simd_test(enable = "avx512f,avx512vl")]
10719 unsafe fn test_mm256_or_epi64() {
10720 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10721 let b = _mm256_set1_epi64x(1 << 13);
10722 let r = _mm256_or_epi64(a, b);
10723 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10724 assert_eq_m256i(r, e);
10725 }
10726
10727 #[simd_test(enable = "avx512f,avx512vl")]
10728 unsafe fn test_mm256_mask_or_epi64() {
10729 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10730 let b = _mm256_set1_epi64x(1 << 13);
10731 let r = _mm256_mask_or_epi64(a, 0, a, b);
10732 assert_eq_m256i(r, a);
10733 let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
10734 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10735 assert_eq_m256i(r, e);
10736 }
10737
10738 #[simd_test(enable = "avx512f,avx512vl")]
10739 unsafe fn test_mm256_maskz_or_epi64() {
10740 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10741 let b = _mm256_set1_epi64x(1 << 13);
10742 let r = _mm256_maskz_or_epi64(0, a, b);
10743 assert_eq_m256i(r, _mm256_setzero_si256());
10744 let r = _mm256_maskz_or_epi64(0b00001111, a, b);
10745 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10746 assert_eq_m256i(r, e);
10747 }
10748
10749 #[simd_test(enable = "avx512f,avx512vl")]
10750 unsafe fn test_mm_or_epi64() {
10751 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10752 let b = _mm_set1_epi64x(1 << 13);
10753 let r = _mm_or_epi64(a, b);
10754 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10755 assert_eq_m128i(r, e);
10756 }
10757
10758 #[simd_test(enable = "avx512f,avx512vl")]
10759 unsafe fn test_mm_mask_or_epi64() {
10760 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10761 let b = _mm_set1_epi64x(1 << 13);
10762 let r = _mm_mask_or_epi64(a, 0, a, b);
10763 assert_eq_m128i(r, a);
10764 let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
10765 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10766 assert_eq_m128i(r, e);
10767 }
10768
10769 #[simd_test(enable = "avx512f,avx512vl")]
10770 unsafe fn test_mm_maskz_or_epi64() {
10771 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10772 let b = _mm_set1_epi64x(1 << 13);
10773 let r = _mm_maskz_or_epi64(0, a, b);
10774 assert_eq_m128i(r, _mm_setzero_si128());
10775 let r = _mm_maskz_or_epi64(0b00000011, a, b);
10776 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10777 assert_eq_m128i(r, e);
10778 }
10779
10780 #[simd_test(enable = "avx512f")]
10781 unsafe fn test_mm512_or_si512() {
10782 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10783 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10784 let r = _mm512_or_epi64(a, b);
10785 #[rustfmt::skip]
10786 let e = _mm512_set_epi64(
10787 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
10788 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
10789 );
10790 assert_eq_m512i(r, e);
10791 }
10792
10793 #[simd_test(enable = "avx512f")]
10794 unsafe fn test_mm512_xor_epi64() {
10795 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10796 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10797 let r = _mm512_xor_epi64(a, b);
10798 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
10799 assert_eq_m512i(r, e);
10800 }
10801
10802 #[simd_test(enable = "avx512f")]
10803 unsafe fn test_mm512_mask_xor_epi64() {
10804 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10805 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10806 let r = _mm512_mask_xor_epi64(a, 0, a, b);
10807 assert_eq_m512i(r, a);
10808 let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
10809 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
10810 assert_eq_m512i(r, e);
10811 }
10812
10813 #[simd_test(enable = "avx512f")]
10814 unsafe fn test_mm512_maskz_xor_epi64() {
10815 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10816 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10817 let r = _mm512_maskz_xor_epi64(0, a, b);
10818 assert_eq_m512i(r, _mm512_setzero_si512());
10819 let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
10820 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
10821 assert_eq_m512i(r, e);
10822 }
10823
10824 #[simd_test(enable = "avx512f,avx512vl")]
10825 unsafe fn test_mm256_xor_epi64() {
10826 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10827 let b = _mm256_set1_epi64x(1 << 13);
10828 let r = _mm256_xor_epi64(a, b);
10829 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10830 assert_eq_m256i(r, e);
10831 }
10832
10833 #[simd_test(enable = "avx512f,avx512vl")]
10834 unsafe fn test_mm256_mask_xor_epi64() {
10835 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10836 let b = _mm256_set1_epi64x(1 << 13);
10837 let r = _mm256_mask_xor_epi64(a, 0, a, b);
10838 assert_eq_m256i(r, a);
10839 let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
10840 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10841 assert_eq_m256i(r, e);
10842 }
10843
10844 #[simd_test(enable = "avx512f,avx512vl")]
10845 unsafe fn test_mm256_maskz_xor_epi64() {
10846 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
10847 let b = _mm256_set1_epi64x(1 << 13);
10848 let r = _mm256_maskz_xor_epi64(0, a, b);
10849 assert_eq_m256i(r, _mm256_setzero_si256());
10850 let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
10851 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10852 assert_eq_m256i(r, e);
10853 }
10854
10855 #[simd_test(enable = "avx512f,avx512vl")]
10856 unsafe fn test_mm_xor_epi64() {
10857 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10858 let b = _mm_set1_epi64x(1 << 13);
10859 let r = _mm_xor_epi64(a, b);
10860 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10861 assert_eq_m128i(r, e);
10862 }
10863
10864 #[simd_test(enable = "avx512f,avx512vl")]
10865 unsafe fn test_mm_mask_xor_epi64() {
10866 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10867 let b = _mm_set1_epi64x(1 << 13);
10868 let r = _mm_mask_xor_epi64(a, 0, a, b);
10869 assert_eq_m128i(r, a);
10870 let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
10871 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10872 assert_eq_m128i(r, e);
10873 }
10874
10875 #[simd_test(enable = "avx512f,avx512vl")]
10876 unsafe fn test_mm_maskz_xor_epi64() {
10877 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
10878 let b = _mm_set1_epi64x(1 << 13);
10879 let r = _mm_maskz_xor_epi64(0, a, b);
10880 assert_eq_m128i(r, _mm_setzero_si128());
10881 let r = _mm_maskz_xor_epi64(0b00000011, a, b);
10882 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
10883 assert_eq_m128i(r, e);
10884 }
10885
10886 #[simd_test(enable = "avx512f")]
10887 unsafe fn test_mm512_xor_si512() {
10888 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10889 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
10890 let r = _mm512_xor_epi64(a, b);
10891 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
10892 assert_eq_m512i(r, e);
10893 }
10894
10895 #[simd_test(enable = "avx512f")]
10896 unsafe fn test_mm512_andnot_epi64() {
10897 let a = _mm512_set1_epi64(0);
10898 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10899 let r = _mm512_andnot_epi64(a, b);
10900 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
10901 assert_eq_m512i(r, e);
10902 }
10903
10904 #[simd_test(enable = "avx512f")]
10905 unsafe fn test_mm512_mask_andnot_epi64() {
10906 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
10907 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10908 let r = _mm512_mask_andnot_epi64(a, 0, a, b);
10909 assert_eq_m512i(r, a);
10910 let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
10911 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
10912 assert_eq_m512i(r, e);
10913 }
10914
10915 #[simd_test(enable = "avx512f")]
10916 unsafe fn test_mm512_maskz_andnot_epi64() {
10917 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
10918 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10919 let r = _mm512_maskz_andnot_epi64(0, a, b);
10920 assert_eq_m512i(r, _mm512_setzero_si512());
10921 let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
10922 #[rustfmt::skip]
10923 let e = _mm512_set_epi64(
10924 0, 0, 0, 0,
10925 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
10926 );
10927 assert_eq_m512i(r, e);
10928 }
10929
10930 #[simd_test(enable = "avx512f,avx512vl")]
10931 unsafe fn test_mm256_mask_andnot_epi64() {
10932 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
10933 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10934 let r = _mm256_mask_andnot_epi64(a, 0, a, b);
10935 assert_eq_m256i(r, a);
10936 let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
10937 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10938 assert_eq_m256i(r, e);
10939 }
10940
10941 #[simd_test(enable = "avx512f,avx512vl")]
10942 unsafe fn test_mm256_maskz_andnot_epi64() {
10943 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
10944 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10945 let r = _mm256_maskz_andnot_epi64(0, a, b);
10946 assert_eq_m256i(r, _mm256_setzero_si256());
10947 let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
10948 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
10949 assert_eq_m256i(r, e);
10950 }
10951
10952 #[simd_test(enable = "avx512f,avx512vl")]
10953 unsafe fn test_mm_mask_andnot_epi64() {
10954 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
10955 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
10956 let r = _mm_mask_andnot_epi64(a, 0, a, b);
10957 assert_eq_m128i(r, a);
10958 let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
10959 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
10960 assert_eq_m128i(r, e);
10961 }
10962
10963 #[simd_test(enable = "avx512f,avx512vl")]
10964 unsafe fn test_mm_maskz_andnot_epi64() {
10965 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
10966 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
10967 let r = _mm_maskz_andnot_epi64(0, a, b);
10968 assert_eq_m128i(r, _mm_setzero_si128());
10969 let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
10970 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
10971 assert_eq_m128i(r, e);
10972 }
10973
10974 #[simd_test(enable = "avx512f")]
10975 unsafe fn test_mm512_andnot_si512() {
10976 let a = _mm512_set1_epi64(0);
10977 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
10978 let r = _mm512_andnot_si512(a, b);
10979 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
10980 assert_eq_m512i(r, e);
10981 }
10982
10983 #[simd_test(enable = "avx512f")]
10984 unsafe fn test_mm512_reduce_add_epi64() {
10985 let a = _mm512_set1_epi64(1);
10986 let e: i64 = _mm512_reduce_add_epi64(a);
10987 assert_eq!(8, e);
10988 }
10989
10990 #[simd_test(enable = "avx512f")]
10991 unsafe fn test_mm512_mask_reduce_add_epi64() {
10992 let a = _mm512_set1_epi64(1);
10993 let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
10994 assert_eq!(4, e);
10995 }
10996
10997 #[simd_test(enable = "avx512f")]
10998 unsafe fn test_mm512_reduce_add_pd() {
10999 let a = _mm512_set1_pd(1.);
11000 let e: f64 = _mm512_reduce_add_pd(a);
11001 assert_eq!(8., e);
11002 }
11003
11004 #[simd_test(enable = "avx512f")]
11005 unsafe fn test_mm512_mask_reduce_add_pd() {
11006 let a = _mm512_set1_pd(1.);
11007 let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11008 assert_eq!(4., e);
11009 }
11010
11011 #[simd_test(enable = "avx512f")]
11012 unsafe fn test_mm512_reduce_mul_epi64() {
11013 let a = _mm512_set1_epi64(2);
11014 let e: i64 = _mm512_reduce_mul_epi64(a);
11015 assert_eq!(256, e);
11016 }
11017
11018 #[simd_test(enable = "avx512f")]
11019 unsafe fn test_mm512_mask_reduce_mul_epi64() {
11020 let a = _mm512_set1_epi64(2);
11021 let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11022 assert_eq!(16, e);
11023 }
11024
11025 #[simd_test(enable = "avx512f")]
11026 unsafe fn test_mm512_reduce_mul_pd() {
11027 let a = _mm512_set1_pd(2.);
11028 let e: f64 = _mm512_reduce_mul_pd(a);
11029 assert_eq!(256., e);
11030 }
11031
11032 #[simd_test(enable = "avx512f")]
11033 unsafe fn test_mm512_mask_reduce_mul_pd() {
11034 let a = _mm512_set1_pd(2.);
11035 let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11036 assert_eq!(16., e);
11037 }
11038
11039 #[simd_test(enable = "avx512f")]
11040 unsafe fn test_mm512_reduce_max_epi64() {
11041 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11042 let e: i64 = _mm512_reduce_max_epi64(a);
11043 assert_eq!(7, e);
11044 }
11045
11046 #[simd_test(enable = "avx512f")]
11047 unsafe fn test_mm512_mask_reduce_max_epi64() {
11048 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11049 let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11050 assert_eq!(3, e);
11051 }
11052
11053 #[simd_test(enable = "avx512f")]
11054 unsafe fn test_mm512_reduce_max_epu64() {
11055 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11056 let e: u64 = _mm512_reduce_max_epu64(a);
11057 assert_eq!(7, e);
11058 }
11059
11060 #[simd_test(enable = "avx512f")]
11061 unsafe fn test_mm512_mask_reduce_max_epu64() {
11062 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11063 let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11064 assert_eq!(3, e);
11065 }
11066
11067 #[simd_test(enable = "avx512f")]
11068 unsafe fn test_mm512_reduce_max_pd() {
11069 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11070 let e: f64 = _mm512_reduce_max_pd(a);
11071 assert_eq!(7., e);
11072 }
11073
11074 #[simd_test(enable = "avx512f")]
11075 unsafe fn test_mm512_mask_reduce_max_pd() {
11076 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11077 let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11078 assert_eq!(3., e);
11079 }
11080
11081 #[simd_test(enable = "avx512f")]
11082 unsafe fn test_mm512_reduce_min_epi64() {
11083 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11084 let e: i64 = _mm512_reduce_min_epi64(a);
11085 assert_eq!(0, e);
11086 }
11087
11088 #[simd_test(enable = "avx512f")]
11089 unsafe fn test_mm512_mask_reduce_min_epi64() {
11090 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11091 let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11092 assert_eq!(0, e);
11093 }
11094
11095 #[simd_test(enable = "avx512f")]
11096 unsafe fn test_mm512_reduce_min_epu64() {
11097 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11098 let e: u64 = _mm512_reduce_min_epu64(a);
11099 assert_eq!(0, e);
11100 }
11101
11102 #[simd_test(enable = "avx512f")]
11103 unsafe fn test_mm512_mask_reduce_min_epu64() {
11104 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11105 let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11106 assert_eq!(0, e);
11107 }
11108
11109 #[simd_test(enable = "avx512f")]
11110 unsafe fn test_mm512_reduce_min_pd() {
11111 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11112 let e: f64 = _mm512_reduce_min_pd(a);
11113 assert_eq!(0., e);
11114 }
11115
11116 #[simd_test(enable = "avx512f")]
11117 unsafe fn test_mm512_mask_reduce_min_pd() {
11118 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11119 let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11120 assert_eq!(0., e);
11121 }
11122
11123 #[simd_test(enable = "avx512f")]
11124 unsafe fn test_mm512_reduce_and_epi64() {
11125 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11126 let e: i64 = _mm512_reduce_and_epi64(a);
11127 assert_eq!(0, e);
11128 }
11129
11130 #[simd_test(enable = "avx512f")]
11131 unsafe fn test_mm512_mask_reduce_and_epi64() {
11132 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11133 let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11134 assert_eq!(1, e);
11135 }
11136
11137 #[simd_test(enable = "avx512f")]
11138 unsafe fn test_mm512_reduce_or_epi64() {
11139 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11140 let e: i64 = _mm512_reduce_or_epi64(a);
11141 assert_eq!(3, e);
11142 }
11143
11144 #[simd_test(enable = "avx512f")]
11145 unsafe fn test_mm512_mask_reduce_or_epi64() {
11146 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11147 let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11148 assert_eq!(1, e);
11149 }
11150
11151 #[simd_test(enable = "avx512f")]
11152 unsafe fn test_mm512_extractf64x4_pd() {
11153 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11154 let r = _mm512_extractf64x4_pd::<1>(a);
11155 let e = _mm256_setr_pd(5., 6., 7., 8.);
11156 assert_eq_m256d(r, e);
11157 }
11158
11159 #[simd_test(enable = "avx512f")]
11160 unsafe fn test_mm512_mask_extractf64x4_pd() {
11161 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11162 let src = _mm256_set1_pd(100.);
11163 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11164 assert_eq_m256d(r, src);
11165 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11166 let e = _mm256_setr_pd(5., 6., 7., 8.);
11167 assert_eq_m256d(r, e);
11168 }
11169
11170 #[simd_test(enable = "avx512f")]
11171 unsafe fn test_mm512_maskz_extractf64x4_pd() {
11172 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11173 let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11174 assert_eq_m256d(r, _mm256_setzero_pd());
11175 let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11176 let e = _mm256_setr_pd(5., 0., 0., 0.);
11177 assert_eq_m256d(r, e);
11178 }
11179
11180 #[simd_test(enable = "avx512f")]
11181 unsafe fn test_mm512_extracti64x4_epi64() {
11182 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11183 let r = _mm512_extracti64x4_epi64::<0x1>(a);
11184 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11185 assert_eq_m256i(r, e);
11186 }
11187
11188 #[simd_test(enable = "avx512f")]
11189 unsafe fn test_mm512_mask_extracti64x4_epi64() {
11190 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11191 let src = _mm256_set1_epi64x(100);
11192 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11193 assert_eq_m256i(r, src);
11194 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11195 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11196 assert_eq_m256i(r, e);
11197 }
11198
11199 #[simd_test(enable = "avx512f")]
11200 unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11201 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11202 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11203 assert_eq_m256i(r, _mm256_setzero_si256());
11204 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11205 let e = _mm256_setr_epi64x(5, 0, 0, 0);
11206 assert_eq_m256i(r, e);
11207 }
11208
11209 #[simd_test(enable = "avx512f")]
11210 unsafe fn test_mm512_mask_compress_epi64() {
11211 let src = _mm512_set1_epi64(200);
11212 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11213 let r = _mm512_mask_compress_epi64(src, 0, a);
11214 assert_eq_m512i(r, src);
11215 let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11216 let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11217 assert_eq_m512i(r, e);
11218 }
11219
11220 #[simd_test(enable = "avx512f")]
11221 unsafe fn test_mm512_maskz_compress_epi64() {
11222 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11223 let r = _mm512_maskz_compress_epi64(0, a);
11224 assert_eq_m512i(r, _mm512_setzero_si512());
11225 let r = _mm512_maskz_compress_epi64(0b01010101, a);
11226 let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11227 assert_eq_m512i(r, e);
11228 }
11229
11230 #[simd_test(enable = "avx512f,avx512vl")]
11231 unsafe fn test_mm256_mask_compress_epi64() {
11232 let src = _mm256_set1_epi64x(200);
11233 let a = _mm256_set_epi64x(0, 1, 2, 3);
11234 let r = _mm256_mask_compress_epi64(src, 0, a);
11235 assert_eq_m256i(r, src);
11236 let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11237 let e = _mm256_set_epi64x(200, 200, 1, 3);
11238 assert_eq_m256i(r, e);
11239 }
11240
11241 #[simd_test(enable = "avx512f,avx512vl")]
11242 unsafe fn test_mm256_maskz_compress_epi64() {
11243 let a = _mm256_set_epi64x(0, 1, 2, 3);
11244 let r = _mm256_maskz_compress_epi64(0, a);
11245 assert_eq_m256i(r, _mm256_setzero_si256());
11246 let r = _mm256_maskz_compress_epi64(0b00000101, a);
11247 let e = _mm256_set_epi64x(0, 0, 1, 3);
11248 assert_eq_m256i(r, e);
11249 }
11250
11251 #[simd_test(enable = "avx512f,avx512vl")]
11252 unsafe fn test_mm_mask_compress_epi64() {
11253 let src = _mm_set1_epi64x(200);
11254 let a = _mm_set_epi64x(0, 1);
11255 let r = _mm_mask_compress_epi64(src, 0, a);
11256 assert_eq_m128i(r, src);
11257 let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11258 let e = _mm_set_epi64x(200, 1);
11259 assert_eq_m128i(r, e);
11260 }
11261
11262 #[simd_test(enable = "avx512f,avx512vl")]
11263 unsafe fn test_mm_maskz_compress_epi64() {
11264 let a = _mm_set_epi64x(0, 1);
11265 let r = _mm_maskz_compress_epi64(0, a);
11266 assert_eq_m128i(r, _mm_setzero_si128());
11267 let r = _mm_maskz_compress_epi64(0b00000001, a);
11268 let e = _mm_set_epi64x(0, 1);
11269 assert_eq_m128i(r, e);
11270 }
11271
11272 #[simd_test(enable = "avx512f")]
11273 unsafe fn test_mm512_mask_compress_pd() {
11274 let src = _mm512_set1_pd(200.);
11275 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11276 let r = _mm512_mask_compress_pd(src, 0, a);
11277 assert_eq_m512d(r, src);
11278 let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11279 let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11280 assert_eq_m512d(r, e);
11281 }
11282
11283 #[simd_test(enable = "avx512f")]
11284 unsafe fn test_mm512_maskz_compress_pd() {
11285 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11286 let r = _mm512_maskz_compress_pd(0, a);
11287 assert_eq_m512d(r, _mm512_setzero_pd());
11288 let r = _mm512_maskz_compress_pd(0b01010101, a);
11289 let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11290 assert_eq_m512d(r, e);
11291 }
11292
11293 #[simd_test(enable = "avx512f,avx512vl")]
11294 unsafe fn test_mm256_mask_compress_pd() {
11295 let src = _mm256_set1_pd(200.);
11296 let a = _mm256_set_pd(0., 1., 2., 3.);
11297 let r = _mm256_mask_compress_pd(src, 0, a);
11298 assert_eq_m256d(r, src);
11299 let r = _mm256_mask_compress_pd(src, 0b00000101, a);
11300 let e = _mm256_set_pd(200., 200., 1., 3.);
11301 assert_eq_m256d(r, e);
11302 }
11303
11304 #[simd_test(enable = "avx512f,avx512vl")]
11305 unsafe fn test_mm256_maskz_compress_pd() {
11306 let a = _mm256_set_pd(0., 1., 2., 3.);
11307 let r = _mm256_maskz_compress_pd(0, a);
11308 assert_eq_m256d(r, _mm256_setzero_pd());
11309 let r = _mm256_maskz_compress_pd(0b00000101, a);
11310 let e = _mm256_set_pd(0., 0., 1., 3.);
11311 assert_eq_m256d(r, e);
11312 }
11313
11314 #[simd_test(enable = "avx512f,avx512vl")]
11315 unsafe fn test_mm_mask_compress_pd() {
11316 let src = _mm_set1_pd(200.);
11317 let a = _mm_set_pd(0., 1.);
11318 let r = _mm_mask_compress_pd(src, 0, a);
11319 assert_eq_m128d(r, src);
11320 let r = _mm_mask_compress_pd(src, 0b00000001, a);
11321 let e = _mm_set_pd(200., 1.);
11322 assert_eq_m128d(r, e);
11323 }
11324
11325 #[simd_test(enable = "avx512f,avx512vl")]
11326 unsafe fn test_mm_maskz_compress_pd() {
11327 let a = _mm_set_pd(0., 1.);
11328 let r = _mm_maskz_compress_pd(0, a);
11329 assert_eq_m128d(r, _mm_setzero_pd());
11330 let r = _mm_maskz_compress_pd(0b00000001, a);
11331 let e = _mm_set_pd(0., 1.);
11332 assert_eq_m128d(r, e);
11333 }
11334
11335 #[simd_test(enable = "avx512f")]
11336 unsafe fn test_mm512_mask_expand_epi64() {
11337 let src = _mm512_set1_epi64(200);
11338 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11339 let r = _mm512_mask_expand_epi64(src, 0, a);
11340 assert_eq_m512i(r, src);
11341 let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
11342 let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
11343 assert_eq_m512i(r, e);
11344 }
11345
11346 #[simd_test(enable = "avx512f")]
11347 unsafe fn test_mm512_maskz_expand_epi64() {
11348 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11349 let r = _mm512_maskz_expand_epi64(0, a);
11350 assert_eq_m512i(r, _mm512_setzero_si512());
11351 let r = _mm512_maskz_expand_epi64(0b01010101, a);
11352 let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
11353 assert_eq_m512i(r, e);
11354 }
11355
11356 #[simd_test(enable = "avx512f,avx512vl")]
11357 unsafe fn test_mm256_mask_expand_epi64() {
11358 let src = _mm256_set1_epi64x(200);
11359 let a = _mm256_set_epi64x(0, 1, 2, 3);
11360 let r = _mm256_mask_expand_epi64(src, 0, a);
11361 assert_eq_m256i(r, src);
11362 let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
11363 let e = _mm256_set_epi64x(200, 2, 200, 3);
11364 assert_eq_m256i(r, e);
11365 }
11366
11367 #[simd_test(enable = "avx512f,avx512vl")]
11368 unsafe fn test_mm256_maskz_expand_epi64() {
11369 let a = _mm256_set_epi64x(0, 1, 2, 3);
11370 let r = _mm256_maskz_expand_epi64(0, a);
11371 assert_eq_m256i(r, _mm256_setzero_si256());
11372 let r = _mm256_maskz_expand_epi64(0b00000101, a);
11373 let e = _mm256_set_epi64x(0, 2, 0, 3);
11374 assert_eq_m256i(r, e);
11375 }
11376
11377 #[simd_test(enable = "avx512f,avx512vl")]
11378 unsafe fn test_mm_mask_expand_epi64() {
11379 let src = _mm_set1_epi64x(200);
11380 let a = _mm_set_epi64x(0, 1);
11381 let r = _mm_mask_expand_epi64(src, 0, a);
11382 assert_eq_m128i(r, src);
11383 let r = _mm_mask_expand_epi64(src, 0b00000001, a);
11384 let e = _mm_set_epi64x(200, 1);
11385 assert_eq_m128i(r, e);
11386 }
11387
11388 #[simd_test(enable = "avx512f,avx512vl")]
11389 unsafe fn test_mm_maskz_expand_epi64() {
11390 let a = _mm_set_epi64x(0, 1);
11391 let r = _mm_maskz_expand_epi64(0, a);
11392 assert_eq_m128i(r, _mm_setzero_si128());
11393 let r = _mm_maskz_expand_epi64(0b00000001, a);
11394 let e = _mm_set_epi64x(0, 1);
11395 assert_eq_m128i(r, e);
11396 }
11397
11398 #[simd_test(enable = "avx512f")]
11399 unsafe fn test_mm512_mask_expand_pd() {
11400 let src = _mm512_set1_pd(200.);
11401 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11402 let r = _mm512_mask_expand_pd(src, 0, a);
11403 assert_eq_m512d(r, src);
11404 let r = _mm512_mask_expand_pd(src, 0b01010101, a);
11405 let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
11406 assert_eq_m512d(r, e);
11407 }
11408
11409 #[simd_test(enable = "avx512f")]
11410 unsafe fn test_mm512_maskz_expand_pd() {
11411 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11412 let r = _mm512_maskz_expand_pd(0, a);
11413 assert_eq_m512d(r, _mm512_setzero_pd());
11414 let r = _mm512_maskz_expand_pd(0b01010101, a);
11415 let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
11416 assert_eq_m512d(r, e);
11417 }
11418
11419 #[simd_test(enable = "avx512f,avx512vl")]
11420 unsafe fn test_mm256_mask_expand_pd() {
11421 let src = _mm256_set1_pd(200.);
11422 let a = _mm256_set_pd(0., 1., 2., 3.);
11423 let r = _mm256_mask_expand_pd(src, 0, a);
11424 assert_eq_m256d(r, src);
11425 let r = _mm256_mask_expand_pd(src, 0b00000101, a);
11426 let e = _mm256_set_pd(200., 2., 200., 3.);
11427 assert_eq_m256d(r, e);
11428 }
11429
11430 #[simd_test(enable = "avx512f,avx512vl")]
11431 unsafe fn test_mm256_maskz_expand_pd() {
11432 let a = _mm256_set_pd(0., 1., 2., 3.);
11433 let r = _mm256_maskz_expand_pd(0, a);
11434 assert_eq_m256d(r, _mm256_setzero_pd());
11435 let r = _mm256_maskz_expand_pd(0b00000101, a);
11436 let e = _mm256_set_pd(0., 2., 0., 3.);
11437 assert_eq_m256d(r, e);
11438 }
11439
11440 #[simd_test(enable = "avx512f,avx512vl")]
11441 unsafe fn test_mm_mask_expand_pd() {
11442 let src = _mm_set1_pd(200.);
11443 let a = _mm_set_pd(0., 1.);
11444 let r = _mm_mask_expand_pd(src, 0, a);
11445 assert_eq_m128d(r, src);
11446 let r = _mm_mask_expand_pd(src, 0b00000001, a);
11447 let e = _mm_set_pd(200., 1.);
11448 assert_eq_m128d(r, e);
11449 }
11450
11451 #[simd_test(enable = "avx512f,avx512vl")]
11452 unsafe fn test_mm_maskz_expand_pd() {
11453 let a = _mm_set_pd(0., 1.);
11454 let r = _mm_maskz_expand_pd(0, a);
11455 assert_eq_m128d(r, _mm_setzero_pd());
11456 let r = _mm_maskz_expand_pd(0b00000001, a);
11457 let e = _mm_set_pd(0., 1.);
11458 assert_eq_m128d(r, e);
11459 }
11460
11461 #[simd_test(enable = "avx512f")]
11462 unsafe fn test_mm512_loadu_epi64() {
11463 let a = &[4, 3, 2, 5, -8, -9, -64, -50];
11464 let p = a.as_ptr();
11465 let r = _mm512_loadu_epi64(black_box(p));
11466 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
11467 assert_eq_m512i(r, e);
11468 }
11469
11470 #[simd_test(enable = "avx512f,avx512vl")]
11471 unsafe fn test_mm256_loadu_epi64() {
11472 let a = &[4, 3, 2, 5];
11473 let p = a.as_ptr();
11474 let r = _mm256_loadu_epi64(black_box(p));
11475 let e = _mm256_setr_epi64x(4, 3, 2, 5);
11476 assert_eq_m256i(r, e);
11477 }
11478
11479 #[simd_test(enable = "avx512f,avx512vl")]
11480 unsafe fn test_mm_loadu_epi64() {
11481 let a = &[4, 3];
11482 let p = a.as_ptr();
11483 let r = _mm_loadu_epi64(black_box(p));
11484 let e = _mm_setr_epi64x(4, 3);
11485 assert_eq_m128i(r, e);
11486 }
11487
11488 #[simd_test(enable = "avx512f")]
11489 unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
11490 let a = _mm512_set1_epi64(9);
11491 let mut r = _mm_undefined_si128();
11492 _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11493 let e = _mm_set1_epi16(9);
11494 assert_eq_m128i(r, e);
11495 }
11496
11497 #[simd_test(enable = "avx512f,avx512vl")]
11498 unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
11499 let a = _mm256_set1_epi64x(9);
11500 let mut r = _mm_set1_epi16(0);
11501 _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11502 let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
11503 assert_eq_m128i(r, e);
11504 }
11505
11506 #[simd_test(enable = "avx512f,avx512vl")]
11507 unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
11508 let a = _mm_set1_epi64x(9);
11509 let mut r = _mm_set1_epi16(0);
11510 _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11511 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
11512 assert_eq_m128i(r, e);
11513 }
11514
11515 #[simd_test(enable = "avx512f")]
11516 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
11517 let a = _mm512_set1_epi64(i64::MAX);
11518 let mut r = _mm_undefined_si128();
11519 _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11520 let e = _mm_set1_epi16(i16::MAX);
11521 assert_eq_m128i(r, e);
11522 }
11523
11524 #[simd_test(enable = "avx512f,avx512vl")]
11525 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
11526 let a = _mm256_set1_epi64x(i64::MAX);
11527 let mut r = _mm_set1_epi16(0);
11528 _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11529 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11530 assert_eq_m128i(r, e);
11531 }
11532
11533 #[simd_test(enable = "avx512f,avx512vl")]
11534 unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
11535 let a = _mm_set1_epi64x(i64::MAX);
11536 let mut r = _mm_set1_epi16(0);
11537 _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11538 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
11539 assert_eq_m128i(r, e);
11540 }
11541
11542 #[simd_test(enable = "avx512f")]
11543 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
11544 let a = _mm512_set1_epi64(i64::MAX);
11545 let mut r = _mm_undefined_si128();
11546 _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11547 let e = _mm_set1_epi16(u16::MAX as i16);
11548 assert_eq_m128i(r, e);
11549 }
11550
11551 #[simd_test(enable = "avx512f,avx512vl")]
11552 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
11553 let a = _mm256_set1_epi64x(i64::MAX);
11554 let mut r = _mm_set1_epi16(0);
11555 _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11556 let e = _mm_set_epi16(
11557 0,
11558 0,
11559 0,
11560 0,
11561 u16::MAX as i16,
11562 u16::MAX as i16,
11563 u16::MAX as i16,
11564 u16::MAX as i16,
11565 );
11566 assert_eq_m128i(r, e);
11567 }
11568
11569 #[simd_test(enable = "avx512f,avx512vl")]
11570 unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
11571 let a = _mm_set1_epi64x(i64::MAX);
11572 let mut r = _mm_set1_epi16(0);
11573 _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
11574 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
11575 assert_eq_m128i(r, e);
11576 }
11577
11578 #[simd_test(enable = "avx512f")]
11579 unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
11580 let a = _mm512_set1_epi64(9);
11581 let mut r = _mm_set1_epi8(0);
11582 _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11583 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
11584 assert_eq_m128i(r, e);
11585 }
11586
11587 #[simd_test(enable = "avx512f,avx512vl")]
11588 unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
11589 let a = _mm256_set1_epi64x(9);
11590 let mut r = _mm_set1_epi8(0);
11591 _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11592 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
11593 assert_eq_m128i(r, e);
11594 }
11595
11596 #[simd_test(enable = "avx512f,avx512vl")]
11597 unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
11598 let a = _mm_set1_epi64x(9);
11599 let mut r = _mm_set1_epi8(0);
11600 _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11601 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
11602 assert_eq_m128i(r, e);
11603 }
11604
11605 #[simd_test(enable = "avx512f")]
11606 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
11607 let a = _mm512_set1_epi64(i64::MAX);
11608 let mut r = _mm_set1_epi8(0);
11609 _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11610 #[rustfmt::skip]
11611 let e = _mm_set_epi8(
11612 0, 0, 0, 0,
11613 0, 0, 0, 0,
11614 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
11615 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
11616 );
11617 assert_eq_m128i(r, e);
11618 }
11619
11620 #[simd_test(enable = "avx512f,avx512vl")]
11621 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
11622 let a = _mm256_set1_epi64x(i64::MAX);
11623 let mut r = _mm_set1_epi8(0);
11624 _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11625 #[rustfmt::skip]
11626 let e = _mm_set_epi8(
11627 0, 0, 0, 0,
11628 0, 0, 0, 0,
11629 0, 0, 0, 0,
11630 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
11631 );
11632 assert_eq_m128i(r, e);
11633 }
11634
11635 #[simd_test(enable = "avx512f,avx512vl")]
11636 unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
11637 let a = _mm_set1_epi64x(i64::MAX);
11638 let mut r = _mm_set1_epi8(0);
11639 _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11640 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
11641 assert_eq_m128i(r, e);
11642 }
11643
11644 #[simd_test(enable = "avx512f")]
11645 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
11646 let a = _mm512_set1_epi64(i64::MAX);
11647 let mut r = _mm_set1_epi8(0);
11648 _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11649 #[rustfmt::skip]
11650 let e = _mm_set_epi8(
11651 0, 0, 0, 0,
11652 0, 0, 0, 0,
11653 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
11654 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
11655 );
11656 assert_eq_m128i(r, e);
11657 }
11658
11659 #[simd_test(enable = "avx512f,avx512vl")]
11660 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
11661 let a = _mm256_set1_epi64x(i64::MAX);
11662 let mut r = _mm_set1_epi8(0);
11663 _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11664 #[rustfmt::skip]
11665 let e = _mm_set_epi8(
11666 0, 0, 0, 0,
11667 0, 0, 0, 0,
11668 0, 0, 0, 0,
11669 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
11670 );
11671 assert_eq_m128i(r, e);
11672 }
11673
11674 #[simd_test(enable = "avx512f,avx512vl")]
11675 unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
11676 let a = _mm_set1_epi64x(i64::MAX);
11677 let mut r = _mm_set1_epi8(0);
11678 _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
11679 #[rustfmt::skip]
11680 let e = _mm_set_epi8(
11681 0, 0, 0, 0,
11682 0, 0, 0, 0,
11683 0, 0, 0, 0,
11684 0, 0, u8::MAX as i8, u8::MAX as i8,
11685 );
11686 assert_eq_m128i(r, e);
11687 }
11688
11689 #[simd_test(enable = "avx512f")]
11690 unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
11691 let a = _mm512_set1_epi64(9);
11692 let mut r = _mm256_undefined_si256();
11693 _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11694 let e = _mm256_set1_epi32(9);
11695 assert_eq_m256i(r, e);
11696 }
11697
11698 #[simd_test(enable = "avx512f,avx512vl")]
11699 unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
11700 let a = _mm256_set1_epi64x(9);
11701 let mut r = _mm_set1_epi32(0);
11702 _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11703 let e = _mm_set_epi32(9, 9, 9, 9);
11704 assert_eq_m128i(r, e);
11705 }
11706
11707 #[simd_test(enable = "avx512f,avx512vl")]
11708 unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
11709 let a = _mm_set1_epi64x(9);
11710 let mut r = _mm_set1_epi16(0);
11711 _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11712 let e = _mm_set_epi32(0, 0, 9, 9);
11713 assert_eq_m128i(r, e);
11714 }
11715
11716 #[simd_test(enable = "avx512f")]
11717 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
11718 let a = _mm512_set1_epi64(i64::MAX);
11719 let mut r = _mm256_undefined_si256();
11720 _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11721 let e = _mm256_set1_epi32(i32::MAX);
11722 assert_eq_m256i(r, e);
11723 }
11724
11725 #[simd_test(enable = "avx512f,avx512vl")]
11726 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
11727 let a = _mm256_set1_epi64x(i64::MAX);
11728 let mut r = _mm_set1_epi32(0);
11729 _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
11730 let e = _mm_set1_epi32(i32::MAX);
11731 assert_eq_m128i(r, e);
11732 }
11733
11734 #[simd_test(enable = "avx512f,avx512vl")]
11735 unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
11736 let a = _mm_set1_epi64x(i64::MAX);
11737 let mut r = _mm_set1_epi16(0);
11738 _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
11739 let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
11740 assert_eq_m128i(r, e);
11741 }
11742
11743 #[simd_test(enable = "avx512f")]
11744 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
11745 let a = _mm512_set1_epi64(i64::MAX);
11746 let mut r = _mm256_undefined_si256();
11747 _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
11748 let e = _mm256_set1_epi32(u32::MAX as i32);
11749 assert_eq_m256i(r, e);
11750 }
11751
11752 #[simd_test(enable = "avx512f,avx512vl")]
11753 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
11754 let a = _mm256_set1_epi64x(i64::MAX);
11755 let mut r = _mm_set1_epi32(0);
11756 _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
11757 let e = _mm_set1_epi32(u32::MAX as i32);
11758 assert_eq_m128i(r, e);
11759 }
11760
11761 #[simd_test(enable = "avx512f,avx512vl")]
11762 unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
11763 let a = _mm_set1_epi64x(i64::MAX);
11764 let mut r = _mm_set1_epi16(0);
11765 _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
11766 let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
11767 assert_eq_m128i(r, e);
11768 }
11769
11770 #[simd_test(enable = "avx512f")]
11771 unsafe fn test_mm512_storeu_epi64() {
11772 let a = _mm512_set1_epi64(9);
11773 let mut r = _mm512_set1_epi64(0);
11774 _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
11775 assert_eq_m512i(r, a);
11776 }
11777
11778 #[simd_test(enable = "avx512f,avx512vl")]
11779 unsafe fn test_mm256_storeu_epi64() {
11780 let a = _mm256_set1_epi64x(9);
11781 let mut r = _mm256_set1_epi64x(0);
11782 _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
11783 assert_eq_m256i(r, a);
11784 }
11785
11786 #[simd_test(enable = "avx512f,avx512vl")]
11787 unsafe fn test_mm_storeu_epi64() {
11788 let a = _mm_set1_epi64x(9);
11789 let mut r = _mm_set1_epi64x(0);
11790 _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
11791 assert_eq_m128i(r, a);
11792 }
11793
11794 #[simd_test(enable = "avx512f")]
11795 unsafe fn test_mm512_load_epi64() {
11796 #[repr(align(64))]
11797 struct Align {
11798 data: [i64; 8], // 64 bytes
11799 }
11800 let a = Align {
11801 data: [4, 3, 2, 5, -8, -9, -64, -50],
11802 };
11803 let p = (a.data).as_ptr();
11804 let r = _mm512_load_epi64(black_box(p));
11805 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
11806 assert_eq_m512i(r, e);
11807 }
11808
11809 #[simd_test(enable = "avx512f,avx512vl")]
11810 unsafe fn test_mm256_load_epi64() {
11811 #[repr(align(64))]
11812 struct Align {
11813 data: [i64; 4],
11814 }
11815 let a = Align { data: [4, 3, 2, 5] };
11816 let p = (a.data).as_ptr();
11817 let r = _mm256_load_epi64(black_box(p));
11818 let e = _mm256_set_epi64x(5, 2, 3, 4);
11819 assert_eq_m256i(r, e);
11820 }
11821
11822 #[simd_test(enable = "avx512f,avx512vl")]
11823 unsafe fn test_mm_load_epi64() {
11824 #[repr(align(64))]
11825 struct Align {
11826 data: [i64; 2],
11827 }
11828 let a = Align { data: [4, 3] };
11829 let p = (a.data).as_ptr();
11830 let r = _mm_load_epi64(black_box(p));
11831 let e = _mm_set_epi64x(3, 4);
11832 assert_eq_m128i(r, e);
11833 }
11834
11835 #[simd_test(enable = "avx512f")]
11836 unsafe fn test_mm512_store_epi64() {
11837 let a = _mm512_set1_epi64(9);
11838 let mut r = _mm512_set1_epi64(0);
11839 _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
11840 assert_eq_m512i(r, a);
11841 }
11842
11843 #[simd_test(enable = "avx512f,avx512vl")]
11844 unsafe fn test_mm256_store_epi64() {
11845 let a = _mm256_set1_epi64x(9);
11846 let mut r = _mm256_set1_epi64x(0);
11847 _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
11848 assert_eq_m256i(r, a);
11849 }
11850
11851 #[simd_test(enable = "avx512f,avx512vl")]
11852 unsafe fn test_mm_store_epi64() {
11853 let a = _mm_set1_epi64x(9);
11854 let mut r = _mm_set1_epi64x(0);
11855 _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
11856 assert_eq_m128i(r, a);
11857 }
11858
11859 #[simd_test(enable = "avx512f")]
11860 unsafe fn test_mm512_load_pd() {
11861 #[repr(align(64))]
11862 struct Align {
11863 data: [f64; 8], // 64 bytes
11864 }
11865 let a = Align {
11866 data: [4., 3., 2., 5., -8., -9., -64., -50.],
11867 };
11868 let p = (a.data).as_ptr();
11869 let r = _mm512_load_pd(black_box(p));
11870 let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
11871 assert_eq_m512d(r, e);
11872 }
11873
11874 #[simd_test(enable = "avx512f")]
11875 unsafe fn test_mm512_store_pd() {
11876 let a = _mm512_set1_pd(9.);
11877 let mut r = _mm512_undefined_pd();
11878 _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
11879 assert_eq_m512d(r, a);
11880 }
11881
11882 #[simd_test(enable = "avx512f")]
11883 unsafe fn test_mm512_test_epi64_mask() {
11884 let a = _mm512_set1_epi64(1 << 0);
11885 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
11886 let r = _mm512_test_epi64_mask(a, b);
11887 let e: __mmask8 = 0b11111111;
11888 assert_eq!(r, e);
11889 }
11890
11891 #[simd_test(enable = "avx512f")]
11892 unsafe fn test_mm512_mask_test_epi64_mask() {
11893 let a = _mm512_set1_epi64(1 << 0);
11894 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
11895 let r = _mm512_mask_test_epi64_mask(0, a, b);
11896 assert_eq!(r, 0);
11897 let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
11898 let e: __mmask8 = 0b11111111;
11899 assert_eq!(r, e);
11900 }
11901
11902 #[simd_test(enable = "avx512f,avx512vl")]
11903 unsafe fn test_mm256_test_epi64_mask() {
11904 let a = _mm256_set1_epi64x(1 << 0);
11905 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
11906 let r = _mm256_test_epi64_mask(a, b);
11907 let e: __mmask8 = 0b00001111;
11908 assert_eq!(r, e);
11909 }
11910
11911 #[simd_test(enable = "avx512f,avx512vl")]
11912 unsafe fn test_mm256_mask_test_epi64_mask() {
11913 let a = _mm256_set1_epi64x(1 << 0);
11914 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
11915 let r = _mm256_mask_test_epi64_mask(0, a, b);
11916 assert_eq!(r, 0);
11917 let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
11918 let e: __mmask8 = 0b00001111;
11919 assert_eq!(r, e);
11920 }
11921
11922 #[simd_test(enable = "avx512f,avx512vl")]
11923 unsafe fn test_mm_test_epi64_mask() {
11924 let a = _mm_set1_epi64x(1 << 0);
11925 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
11926 let r = _mm_test_epi64_mask(a, b);
11927 let e: __mmask8 = 0b00000011;
11928 assert_eq!(r, e);
11929 }
11930
11931 #[simd_test(enable = "avx512f,avx512vl")]
11932 unsafe fn test_mm_mask_test_epi64_mask() {
11933 let a = _mm_set1_epi64x(1 << 0);
11934 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
11935 let r = _mm_mask_test_epi64_mask(0, a, b);
11936 assert_eq!(r, 0);
11937 let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
11938 let e: __mmask8 = 0b00000011;
11939 assert_eq!(r, e);
11940 }
11941
11942 #[simd_test(enable = "avx512f")]
11943 unsafe fn test_mm512_testn_epi64_mask() {
11944 let a = _mm512_set1_epi64(1 << 0);
11945 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
11946 let r = _mm512_testn_epi64_mask(a, b);
11947 let e: __mmask8 = 0b00000000;
11948 assert_eq!(r, e);
11949 }
11950
11951 #[simd_test(enable = "avx512f")]
11952 unsafe fn test_mm512_mask_testn_epi64_mask() {
11953 let a = _mm512_set1_epi64(1 << 0);
11954 let b = _mm512_set1_epi64(1 << 1);
11955 let r = _mm512_mask_testn_epi64_mask(0, a, b);
11956 assert_eq!(r, 0);
11957 let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
11958 let e: __mmask8 = 0b11111111;
11959 assert_eq!(r, e);
11960 }
11961
11962 #[simd_test(enable = "avx512f,avx512vl")]
11963 unsafe fn test_mm256_testn_epi64_mask() {
11964 let a = _mm256_set1_epi64x(1 << 0);
11965 let b = _mm256_set1_epi64x(1 << 1);
11966 let r = _mm256_testn_epi64_mask(a, b);
11967 let e: __mmask8 = 0b00001111;
11968 assert_eq!(r, e);
11969 }
11970
11971 #[simd_test(enable = "avx512f,avx512vl")]
11972 unsafe fn test_mm256_mask_testn_epi64_mask() {
11973 let a = _mm256_set1_epi64x(1 << 0);
11974 let b = _mm256_set1_epi64x(1 << 1);
11975 let r = _mm256_mask_testn_epi64_mask(0, a, b);
11976 assert_eq!(r, 0);
11977 let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
11978 let e: __mmask8 = 0b00001111;
11979 assert_eq!(r, e);
11980 }
11981
11982 #[simd_test(enable = "avx512f,avx512vl")]
11983 unsafe fn test_mm_testn_epi64_mask() {
11984 let a = _mm_set1_epi64x(1 << 0);
11985 let b = _mm_set1_epi64x(1 << 1);
11986 let r = _mm_testn_epi64_mask(a, b);
11987 let e: __mmask8 = 0b00000011;
11988 assert_eq!(r, e);
11989 }
11990
11991 #[simd_test(enable = "avx512f,avx512vl")]
11992 unsafe fn test_mm_mask_testn_epi64_mask() {
11993 let a = _mm_set1_epi64x(1 << 0);
11994 let b = _mm_set1_epi64x(1 << 1);
11995 let r = _mm_mask_testn_epi64_mask(0, a, b);
11996 assert_eq!(r, 0);
11997 let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
11998 let e: __mmask8 = 0b00000011;
11999 assert_eq!(r, e);
12000 }
12001
12002 #[simd_test(enable = "avx512f")]
12003 unsafe fn test_mm512_stream_pd() {
12004 #[repr(align(64))]
12005 struct Memory {
12006 pub data: [f64; 8],
12007 }
12008 let a = _mm512_set1_pd(7.0);
12009 let mut mem = Memory { data: [-1.0; 8] };
12010
12011 _mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
12012 for i in 0..8 {
12013 assert_eq!(mem.data[i], get_m512d(a, i));
12014 }
12015 }
12016
12017 #[simd_test(enable = "avx512f")]
12018 unsafe fn test_mm512_stream_si512() {
12019 #[repr(align(64))]
12020 struct Memory {
12021 pub data: [i64; 8],
12022 }
12023 let a = _mm512_set1_epi64(7);
12024 let mut mem = Memory { data: [-1; 8] };
12025
12026 _mm512_stream_si512(&mut mem.data[0] as *mut i64, a);
12027 for i in 0..8 {
12028 assert_eq!(mem.data[i], get_m512i(a, i));
12029 }
12030 }
12031
12032 #[simd_test(enable = "avx512f")]
12033 unsafe fn test_mm512_mask_set1_epi64() {
12034 let src = _mm512_set1_epi64(2);
12035 let a: i64 = 11;
12036 let r = _mm512_mask_set1_epi64(src, 0, a);
12037 assert_eq_m512i(r, src);
12038 let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12039 let e = _mm512_set1_epi64(11);
12040 assert_eq_m512i(r, e);
12041 }
12042
12043 #[simd_test(enable = "avx512f")]
12044 unsafe fn test_mm512_maskz_set1_epi64() {
12045 let a: i64 = 11;
12046 let r = _mm512_maskz_set1_epi64(0, a);
12047 assert_eq_m512i(r, _mm512_setzero_si512());
12048 let r = _mm512_maskz_set1_epi64(0b11111111, a);
12049 let e = _mm512_set1_epi64(11);
12050 assert_eq_m512i(r, e);
12051 }
12052
12053 #[simd_test(enable = "avx512f,avx512vl")]
12054 unsafe fn test_mm256_mask_set1_epi64() {
12055 let src = _mm256_set1_epi64x(2);
12056 let a: i64 = 11;
12057 let r = _mm256_mask_set1_epi64(src, 0, a);
12058 assert_eq_m256i(r, src);
12059 let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12060 let e = _mm256_set1_epi64x(11);
12061 assert_eq_m256i(r, e);
12062 }
12063
12064 #[simd_test(enable = "avx512f,avx512vl")]
12065 unsafe fn test_mm256_maskz_set1_epi64() {
12066 let a: i64 = 11;
12067 let r = _mm256_maskz_set1_epi64(0, a);
12068 assert_eq_m256i(r, _mm256_setzero_si256());
12069 let r = _mm256_maskz_set1_epi64(0b00001111, a);
12070 let e = _mm256_set1_epi64x(11);
12071 assert_eq_m256i(r, e);
12072 }
12073
12074 #[simd_test(enable = "avx512f,avx512vl")]
12075 unsafe fn test_mm_mask_set1_epi64() {
12076 let src = _mm_set1_epi64x(2);
12077 let a: i64 = 11;
12078 let r = _mm_mask_set1_epi64(src, 0, a);
12079 assert_eq_m128i(r, src);
12080 let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12081 let e = _mm_set1_epi64x(11);
12082 assert_eq_m128i(r, e);
12083 }
12084
12085 #[simd_test(enable = "avx512f,avx512vl")]
12086 unsafe fn test_mm_maskz_set1_epi64() {
12087 let a: i64 = 11;
12088 let r = _mm_maskz_set1_epi64(0, a);
12089 assert_eq_m128i(r, _mm_setzero_si128());
12090 let r = _mm_maskz_set1_epi64(0b00000011, a);
12091 let e = _mm_set1_epi64x(11);
12092 assert_eq_m128i(r, e);
12093 }
12094
12095 #[simd_test(enable = "avx512f")]
12096 unsafe fn test_mm_cvtsd_i64() {
12097 let a = _mm_set_pd(1., -1.5);
12098 let r = _mm_cvtsd_i64(a);
12099 let e: i64 = -2;
12100 assert_eq!(r, e);
12101 }
12102
12103 #[simd_test(enable = "avx512f")]
12104 unsafe fn test_mm_cvtss_i64() {
12105 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12106 let r = _mm_cvtss_i64(a);
12107 let e: i64 = -2;
12108 assert_eq!(r, e);
12109 }
12110
12111 #[simd_test(enable = "avx512f")]
12112 unsafe fn test_mm_cvt_roundi64_ss() {
12113 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12114 let b: i64 = 9;
12115 let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12116 let e = _mm_set_ps(0., -0.5, 1., 9.);
12117 assert_eq_m128(r, e);
12118 }
12119
12120 #[simd_test(enable = "avx512f")]
12121 unsafe fn test_mm_cvt_roundsi64_ss() {
12122 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12123 let b: i64 = 9;
12124 let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12125 let e = _mm_set_ps(0., -0.5, 1., 9.);
12126 assert_eq_m128(r, e);
12127 }
12128
12129 #[simd_test(enable = "avx512f")]
12130 unsafe fn test_mm_cvti64_ss() {
12131 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12132 let b: i64 = 9;
12133 let r = _mm_cvti64_ss(a, b);
12134 let e = _mm_set_ps(0., -0.5, 1., 9.);
12135 assert_eq_m128(r, e);
12136 }
12137
12138 #[simd_test(enable = "avx512f")]
12139 unsafe fn test_mm_cvti64_sd() {
12140 let a = _mm_set_pd(1., -1.5);
12141 let b: i64 = 9;
12142 let r = _mm_cvti64_sd(a, b);
12143 let e = _mm_set_pd(1., 9.);
12144 assert_eq_m128d(r, e);
12145 }
12146
12147 #[simd_test(enable = "avx512f")]
12148 unsafe fn test_mm_cvt_roundsd_si64() {
12149 let a = _mm_set_pd(1., -1.5);
12150 let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12151 let e: i64 = -1;
12152 assert_eq!(r, e);
12153 }
12154
12155 #[simd_test(enable = "avx512f")]
12156 unsafe fn test_mm_cvt_roundsd_i64() {
12157 let a = _mm_set_pd(1., -1.5);
12158 let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12159 let e: i64 = -1;
12160 assert_eq!(r, e);
12161 }
12162
12163 #[simd_test(enable = "avx512f")]
12164 unsafe fn test_mm_cvt_roundsd_u64() {
12165 let a = _mm_set_pd(1., f64::MAX);
12166 let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12167 let e: u64 = u64::MAX;
12168 assert_eq!(r, e);
12169 }
12170
12171 #[simd_test(enable = "avx512f")]
12172 unsafe fn test_mm_cvtsd_u64() {
12173 let a = _mm_set_pd(1., -1.5);
12174 let r = _mm_cvtsd_u64(a);
12175 let e: u64 = u64::MAX;
12176 assert_eq!(r, e);
12177 }
12178
12179 #[simd_test(enable = "avx512f")]
12180 unsafe fn test_mm_cvt_roundss_i64() {
12181 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12182 let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12183 let e: i64 = -1;
12184 assert_eq!(r, e);
12185 }
12186
12187 #[simd_test(enable = "avx512f")]
12188 unsafe fn test_mm_cvt_roundss_si64() {
12189 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12190 let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12191 let e: i64 = -1;
12192 assert_eq!(r, e);
12193 }
12194
12195 #[simd_test(enable = "avx512f")]
12196 unsafe fn test_mm_cvt_roundss_u64() {
12197 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12198 let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12199 let e: u64 = u64::MAX;
12200 assert_eq!(r, e);
12201 }
12202
12203 #[simd_test(enable = "avx512f")]
12204 unsafe fn test_mm_cvtss_u64() {
12205 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12206 let r = _mm_cvtss_u64(a);
12207 let e: u64 = u64::MAX;
12208 assert_eq!(r, e);
12209 }
12210
12211 #[simd_test(enable = "avx512f")]
12212 unsafe fn test_mm_cvttsd_i64() {
12213 let a = _mm_set_pd(1., -1.5);
12214 let r = _mm_cvttsd_i64(a);
12215 let e: i64 = -2;
12216 assert_eq!(r, e);
12217 }
12218
12219 #[simd_test(enable = "avx512f")]
12220 unsafe fn test_mm_cvtt_roundsd_i64() {
12221 let a = _mm_set_pd(1., -1.5);
12222 let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_CUR_DIRECTION>(a);
12223 let e: i64 = -2;
12224 assert_eq!(r, e);
12225 }
12226
12227 #[simd_test(enable = "avx512f")]
12228 unsafe fn test_mm_cvtt_roundsd_si64() {
12229 let a = _mm_set_pd(1., -1.5);
12230 let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_CUR_DIRECTION>(a);
12231 let e: i64 = -2;
12232 assert_eq!(r, e);
12233 }
12234
12235 #[simd_test(enable = "avx512f")]
12236 unsafe fn test_mm_cvtt_roundsd_u64() {
12237 let a = _mm_set_pd(1., -1.5);
12238 let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_CUR_DIRECTION>(a);
12239 let e: u64 = u64::MAX;
12240 assert_eq!(r, e);
12241 }
12242
12243 #[simd_test(enable = "avx512f")]
12244 unsafe fn test_mm_cvttsd_u64() {
12245 let a = _mm_set_pd(1., -1.5);
12246 let r = _mm_cvttsd_u64(a);
12247 let e: u64 = u64::MAX;
12248 assert_eq!(r, e);
12249 }
12250
12251 #[simd_test(enable = "avx512f")]
12252 unsafe fn test_mm_cvttss_i64() {
12253 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12254 let r = _mm_cvttss_i64(a);
12255 let e: i64 = -2;
12256 assert_eq!(r, e);
12257 }
12258
12259 #[simd_test(enable = "avx512f")]
12260 unsafe fn test_mm_cvtt_roundss_i64() {
12261 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12262 let r = _mm_cvtt_roundss_i64::<_MM_FROUND_CUR_DIRECTION>(a);
12263 let e: i64 = -2;
12264 assert_eq!(r, e);
12265 }
12266
12267 #[simd_test(enable = "avx512f")]
12268 unsafe fn test_mm_cvtt_roundss_si64() {
12269 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12270 let r = _mm_cvtt_roundss_si64::<_MM_FROUND_CUR_DIRECTION>(a);
12271 let e: i64 = -2;
12272 assert_eq!(r, e);
12273 }
12274
12275 #[simd_test(enable = "avx512f")]
12276 unsafe fn test_mm_cvtt_roundss_u64() {
12277 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12278 let r = _mm_cvtt_roundss_u64::<_MM_FROUND_CUR_DIRECTION>(a);
12279 let e: u64 = u64::MAX;
12280 assert_eq!(r, e);
12281 }
12282
12283 #[simd_test(enable = "avx512f")]
12284 unsafe fn test_mm_cvttss_u64() {
12285 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12286 let r = _mm_cvttss_u64(a);
12287 let e: u64 = u64::MAX;
12288 assert_eq!(r, e);
12289 }
12290
12291 #[simd_test(enable = "avx512f")]
12292 unsafe fn test_mm_cvtu64_ss() {
12293 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12294 let b: u64 = 9;
12295 let r = _mm_cvtu64_ss(a, b);
12296 let e = _mm_set_ps(0., -0.5, 1., 9.);
12297 assert_eq_m128(r, e);
12298 }
12299
12300 #[simd_test(enable = "avx512f")]
12301 unsafe fn test_mm_cvtu64_sd() {
12302 let a = _mm_set_pd(1., -1.5);
12303 let b: u64 = 9;
12304 let r = _mm_cvtu64_sd(a, b);
12305 let e = _mm_set_pd(1., 9.);
12306 assert_eq_m128d(r, e);
12307 }
12308
12309 #[simd_test(enable = "avx512f")]
12310 unsafe fn test_mm_cvt_roundu64_ss() {
12311 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12312 let b: u64 = 9;
12313 let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12314 let e = _mm_set_ps(0., -0.5, 1., 9.);
12315 assert_eq_m128(r, e);
12316 }
12317
12318 #[simd_test(enable = "avx512f")]
12319 unsafe fn test_mm_cvt_roundu64_sd() {
12320 let a = _mm_set_pd(1., -1.5);
12321 let b: u64 = 9;
12322 let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12323 let e = _mm_set_pd(1., 9.);
12324 assert_eq_m128d(r, e);
12325 }
12326
12327 #[simd_test(enable = "avx512f")]
12328 unsafe fn test_mm_cvt_roundi64_sd() {
12329 let a = _mm_set_pd(1., -1.5);
12330 let b: i64 = 9;
12331 let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12332 let e = _mm_set_pd(1., 9.);
12333 assert_eq_m128d(r, e);
12334 }
12335
12336 #[simd_test(enable = "avx512f")]
12337 unsafe fn test_mm_cvt_roundsi64_sd() {
12338 let a = _mm_set_pd(1., -1.5);
12339 let b: i64 = 9;
12340 let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12341 let e = _mm_set_pd(1., 9.);
12342 assert_eq_m128d(r, e);
12343 }
12344}
12345