1use crate::{
2 core_arch::{simd::*, x86::*, x86_64::*},
3 mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
10///
11/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
12#[inline]
13#[target_feature(enable = "avx512f")]
14#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
15#[cfg_attr(test, assert_instr(vcvtsd2si))]
16pub fn _mm_cvtsd_i64(a: __m128d) -> i64 {
17 _mm_cvtsd_si64(a)
18}
19
20/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
21///
22/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
23#[inline]
24#[target_feature(enable = "avx512f")]
25#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
26#[cfg_attr(test, assert_instr(vcvtss2si))]
27pub fn _mm_cvtss_i64(a: __m128) -> i64 {
28 _mm_cvtss_si64(a)
29}
30
31/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
32///
33/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
34#[inline]
35#[target_feature(enable = "avx512f")]
36#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
37#[cfg_attr(test, assert_instr(vcvtss2usi))]
38pub fn _mm_cvtss_u64(a: __m128) -> u64 {
39 unsafe { vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
40}
41
42/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
43///
44/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
45#[inline]
46#[target_feature(enable = "avx512f")]
47#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
48#[cfg_attr(test, assert_instr(vcvtsd2usi))]
49pub fn _mm_cvtsd_u64(a: __m128d) -> u64 {
50 unsafe { vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
51}
52
53/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
54///
55/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti64_ss&expand=1643)
56#[inline]
57#[target_feature(enable = "avx512f")]
58#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
59#[cfg_attr(test, assert_instr(vcvtsi2ss))]
60pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
61 unsafe {
62 let b: f32 = b as f32;
63 simd_insert!(a, 0, b)
64 }
65}
66
67/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
68///
69/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
70#[inline]
71#[target_feature(enable = "avx512f")]
72#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
73#[cfg_attr(test, assert_instr(vcvtsi2sd))]
74pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
75 unsafe {
76 let b: f64 = b as f64;
77 simd_insert!(a, 0, b)
78 }
79}
80
81/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
82///
83/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
84#[inline]
85#[target_feature(enable = "avx512f")]
86#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
87#[cfg_attr(test, assert_instr(vcvtusi2ss))]
88pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
89 unsafe {
90 let b: f32 = b as f32;
91 simd_insert!(a, 0, b)
92 }
93}
94
95/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
96///
97/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
98#[inline]
99#[target_feature(enable = "avx512f")]
100#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
101#[cfg_attr(test, assert_instr(vcvtusi2sd))]
102pub fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
103 unsafe {
104 let b: f64 = b as f64;
105 simd_insert!(a, 0, b)
106 }
107}
108
109/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
110///
111/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
112#[inline]
113#[target_feature(enable = "avx512f")]
114#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
115#[cfg_attr(test, assert_instr(vcvttsd2si))]
116pub fn _mm_cvttsd_i64(a: __m128d) -> i64 {
117 unsafe { vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
118}
119
120/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
121///
122/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
123#[inline]
124#[target_feature(enable = "avx512f")]
125#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
126#[cfg_attr(test, assert_instr(vcvttsd2usi))]
127pub fn _mm_cvttsd_u64(a: __m128d) -> u64 {
128 unsafe { vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
129}
130
131/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
132///
133/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
134#[inline]
135#[target_feature(enable = "avx512f")]
136#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
137#[cfg_attr(test, assert_instr(vcvttss2si))]
138pub fn _mm_cvttss_i64(a: __m128) -> i64 {
139 unsafe { vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
140}
141
142/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
143///
144/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
145#[inline]
146#[target_feature(enable = "avx512f")]
147#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
148#[cfg_attr(test, assert_instr(vcvttss2usi))]
149pub fn _mm_cvttss_u64(a: __m128) -> u64 {
150 unsafe { vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
151}
152
153/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
154/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
155/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
156/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
157/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
158/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
159/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
160///
161/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
162#[inline]
163#[target_feature(enable = "avx512f")]
164#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
165#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
166#[rustc_legacy_const_generics(2)]
167pub fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
168 unsafe {
169 static_assert_rounding!(ROUNDING);
170 let a: f64x2 = a.as_f64x2();
171 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
172 transmute(src:r)
173 }
174}
175
176/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
177/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
178/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
179/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
180/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
181/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
182/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
183///
184/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
185#[inline]
186#[target_feature(enable = "avx512f")]
187#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
188#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
189#[rustc_legacy_const_generics(2)]
190pub fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
191 unsafe {
192 static_assert_rounding!(ROUNDING);
193 let a: f64x2 = a.as_f64x2();
194 let r: f64x2 = vcvtsi2sd64(a, b, ROUNDING);
195 transmute(src:r)
196 }
197}
198
199/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
200/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
201/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
202/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
203/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
204/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
205/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
206///
207/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
208#[inline]
209#[target_feature(enable = "avx512f")]
210#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
211#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
212#[rustc_legacy_const_generics(2)]
213pub fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
214 unsafe {
215 static_assert_rounding!(ROUNDING);
216 let a: f32x4 = a.as_f32x4();
217 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
218 transmute(src:r)
219 }
220}
221
222/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
223/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
224/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
225/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
226/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
227/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
228/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
229///
230/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
231#[inline]
232#[target_feature(enable = "avx512f")]
233#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
234#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
235#[rustc_legacy_const_generics(2)]
236pub fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
237 unsafe {
238 static_assert_rounding!(ROUNDING);
239 let a: f64x2 = a.as_f64x2();
240 let r: f64x2 = vcvtusi2sd64(a, b, ROUNDING);
241 transmute(src:r)
242 }
243}
244
245/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
246/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
247/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
248/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
249/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
250/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
251/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
252///
253/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
254#[inline]
255#[target_feature(enable = "avx512f")]
256#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
257#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
258#[rustc_legacy_const_generics(2)]
259pub fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
260 unsafe {
261 static_assert_rounding!(ROUNDING);
262 let a: f32x4 = a.as_f32x4();
263 let r: f32x4 = vcvtsi2ss64(a, b, ROUNDING);
264 transmute(src:r)
265 }
266}
267
268/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
269/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
270/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
271/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
272/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
273/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
274/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
275///
276/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
277#[inline]
278#[target_feature(enable = "avx512f")]
279#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
280#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
281#[rustc_legacy_const_generics(2)]
282pub fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
283 unsafe {
284 static_assert_rounding!(ROUNDING);
285 let a: f32x4 = a.as_f32x4();
286 let r: f32x4 = vcvtusi2ss64(a, b, ROUNDING);
287 transmute(src:r)
288 }
289}
290
291/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
292/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
293/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
294/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
295/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
296/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
297/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
298///
299/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
300#[inline]
301#[target_feature(enable = "avx512f")]
302#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
303#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
304#[rustc_legacy_const_generics(1)]
305pub fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
306 unsafe {
307 static_assert_rounding!(ROUNDING);
308 let a: f64x2 = a.as_f64x2();
309 vcvtsd2si64(a, ROUNDING)
310 }
311}
312
313/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
314/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
315/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
316/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
317/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
318/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
319/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
320///
321/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
322#[inline]
323#[target_feature(enable = "avx512f")]
324#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
325#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
326#[rustc_legacy_const_generics(1)]
327pub fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
328 unsafe {
329 static_assert_rounding!(ROUNDING);
330 let a: f64x2 = a.as_f64x2();
331 vcvtsd2si64(a, ROUNDING)
332 }
333}
334
335/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
336/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
337/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
338/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
339/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
340/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
341/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
342///
343/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
344#[inline]
345#[target_feature(enable = "avx512f")]
346#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
347#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
348#[rustc_legacy_const_generics(1)]
349pub fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
350 unsafe {
351 static_assert_rounding!(ROUNDING);
352 let a: f64x2 = a.as_f64x2();
353 vcvtsd2usi64(a, ROUNDING)
354 }
355}
356
357/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
358/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
359/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
360/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
361/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
362/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
363/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
364///
365/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
366#[inline]
367#[target_feature(enable = "avx512f")]
368#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
369#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
370#[rustc_legacy_const_generics(1)]
371pub fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
372 unsafe {
373 static_assert_rounding!(ROUNDING);
374 let a: f32x4 = a.as_f32x4();
375 vcvtss2si64(a, ROUNDING)
376 }
377}
378
379/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
380/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
381/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
382/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
383/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
384/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
385/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
386///
387/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
388#[inline]
389#[target_feature(enable = "avx512f")]
390#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
391#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
392#[rustc_legacy_const_generics(1)]
393pub fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
394 unsafe {
395 static_assert_rounding!(ROUNDING);
396 let a: f32x4 = a.as_f32x4();
397 vcvtss2si64(a, ROUNDING)
398 }
399}
400
401/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
402/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
403/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
404/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
405/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
406/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
407/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
408///
409/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
410#[inline]
411#[target_feature(enable = "avx512f")]
412#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
413#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
414#[rustc_legacy_const_generics(1)]
415pub fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
416 unsafe {
417 static_assert_rounding!(ROUNDING);
418 let a: f32x4 = a.as_f32x4();
419 vcvtss2usi64(a, ROUNDING)
420 }
421}
422
423/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
424/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
425///
426/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
427#[inline]
428#[target_feature(enable = "avx512f")]
429#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
430#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
431#[rustc_legacy_const_generics(1)]
432pub fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
433 unsafe {
434 static_assert_sae!(SAE);
435 let a: f64x2 = a.as_f64x2();
436 vcvttsd2si64(a, SAE)
437 }
438}
439
440/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
441/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
442///
443/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
444#[inline]
445#[target_feature(enable = "avx512f")]
446#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
447#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
448#[rustc_legacy_const_generics(1)]
449pub fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
450 unsafe {
451 static_assert_sae!(SAE);
452 let a: f64x2 = a.as_f64x2();
453 vcvttsd2si64(a, SAE)
454 }
455}
456
457/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
458/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
459///
460/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
461#[inline]
462#[target_feature(enable = "avx512f")]
463#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
464#[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))]
465#[rustc_legacy_const_generics(1)]
466pub fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
467 unsafe {
468 static_assert_sae!(SAE);
469 let a: f64x2 = a.as_f64x2();
470 vcvttsd2usi64(a, SAE)
471 }
472}
473
474/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
475/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
476///
477/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
478#[inline]
479#[target_feature(enable = "avx512f")]
480#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
481#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
482#[rustc_legacy_const_generics(1)]
483pub fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
484 unsafe {
485 static_assert_sae!(SAE);
486 let a: f32x4 = a.as_f32x4();
487 vcvttss2si64(a, SAE)
488 }
489}
490
491/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
492/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
493///
494/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
495#[inline]
496#[target_feature(enable = "avx512f")]
497#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
498#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
499#[rustc_legacy_const_generics(1)]
500pub fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
501 unsafe {
502 static_assert_sae!(SAE);
503 let a: f32x4 = a.as_f32x4();
504 vcvttss2si64(a, SAE)
505 }
506}
507
508/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
509/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
510///
511/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
512#[inline]
513#[target_feature(enable = "avx512f")]
514#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
515#[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))]
516#[rustc_legacy_const_generics(1)]
517pub fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
518 unsafe {
519 static_assert_sae!(SAE);
520 let a: f32x4 = a.as_f32x4();
521 vcvttss2usi64(a, SAE)
522 }
523}
524
525#[allow(improper_ctypes)]
526unsafe extern "C" {
527 #[link_name = "llvm.x86.avx512.vcvtss2si64"]
528 unsafefn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
529 #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
530 unsafefn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
531 #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
532 unsafefn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
533 #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
534 unsafefn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
535
536 #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
537 unsafefn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
538 #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
539 unsafefn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
540 #[link_name = "llvm.x86.avx512.cvtusi642ss"]
541 unsafefn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
542 #[link_name = "llvm.x86.avx512.cvtusi642sd"]
543 unsafefn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
544
545 #[link_name = "llvm.x86.avx512.cvttss2si64"]
546 unsafefn vcvttss2si64(a: f32x4, rounding: i32) -> i64;
547 #[link_name = "llvm.x86.avx512.cvttss2usi64"]
548 unsafefn vcvttss2usi64(a: f32x4, rounding: i32) -> u64;
549 #[link_name = "llvm.x86.avx512.cvttsd2si64"]
550 unsafefn vcvttsd2si64(a: f64x2, rounding: i32) -> i64;
551 #[link_name = "llvm.x86.avx512.cvttsd2usi64"]
552 unsafefn vcvttsd2usi64(a: f64x2, rounding: i32) -> u64;
553}
554
555#[cfg(test)]
556mod tests {
557
558 use stdarch_test::simd_test;
559
560 use crate::core_arch::x86::*;
561 use crate::core_arch::x86_64::*;
562 use crate::hint::black_box;
563
564 #[simd_test(enable = "avx512f")]
565 unsafe fn test_mm512_abs_epi64() {
566 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
567 let r = _mm512_abs_epi64(a);
568 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
569 assert_eq_m512i(r, e);
570 }
571
572 #[simd_test(enable = "avx512f")]
573 unsafe fn test_mm512_mask_abs_epi64() {
574 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
575 let r = _mm512_mask_abs_epi64(a, 0, a);
576 assert_eq_m512i(r, a);
577 let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
578 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
579 assert_eq_m512i(r, e);
580 }
581
582 #[simd_test(enable = "avx512f")]
583 unsafe fn test_mm512_maskz_abs_epi64() {
584 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
585 let r = _mm512_maskz_abs_epi64(0, a);
586 assert_eq_m512i(r, _mm512_setzero_si512());
587 let r = _mm512_maskz_abs_epi64(0b11111111, a);
588 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
589 assert_eq_m512i(r, e);
590 }
591
592 #[simd_test(enable = "avx512f,avx512vl")]
593 unsafe fn test_mm256_abs_epi64() {
594 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
595 let r = _mm256_abs_epi64(a);
596 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
597 assert_eq_m256i(r, e);
598 }
599
600 #[simd_test(enable = "avx512f,avx512vl")]
601 unsafe fn test_mm256_mask_abs_epi64() {
602 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
603 let r = _mm256_mask_abs_epi64(a, 0, a);
604 assert_eq_m256i(r, a);
605 let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
606 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
607 assert_eq_m256i(r, e);
608 }
609
610 #[simd_test(enable = "avx512f,avx512vl")]
611 unsafe fn test_mm256_maskz_abs_epi64() {
612 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
613 let r = _mm256_maskz_abs_epi64(0, a);
614 assert_eq_m256i(r, _mm256_setzero_si256());
615 let r = _mm256_maskz_abs_epi64(0b00001111, a);
616 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
617 assert_eq_m256i(r, e);
618 }
619
620 #[simd_test(enable = "avx512f,avx512vl")]
621 unsafe fn test_mm_abs_epi64() {
622 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
623 let r = _mm_abs_epi64(a);
624 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
625 assert_eq_m128i(r, e);
626 let a = _mm_set_epi64x(100, -100);
627 let r = _mm_abs_epi64(a);
628 let e = _mm_set_epi64x(100, 100);
629 assert_eq_m128i(r, e);
630 }
631
632 #[simd_test(enable = "avx512f,avx512vl")]
633 unsafe fn test_mm_mask_abs_epi64() {
634 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
635 let r = _mm_mask_abs_epi64(a, 0, a);
636 assert_eq_m128i(r, a);
637 let r = _mm_mask_abs_epi64(a, 0b00000011, a);
638 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
639 assert_eq_m128i(r, e);
640 let a = _mm_set_epi64x(100, -100);
641 let r = _mm_mask_abs_epi64(a, 0b00000011, a);
642 let e = _mm_set_epi64x(100, 100);
643 assert_eq_m128i(r, e);
644 }
645
646 #[simd_test(enable = "avx512f,avx512vl")]
647 unsafe fn test_mm_maskz_abs_epi64() {
648 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
649 let r = _mm_maskz_abs_epi64(0, a);
650 assert_eq_m128i(r, _mm_setzero_si128());
651 let r = _mm_maskz_abs_epi64(0b00000011, a);
652 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
653 assert_eq_m128i(r, e);
654 let a = _mm_set_epi64x(100, -100);
655 let r = _mm_maskz_abs_epi64(0b00000011, a);
656 let e = _mm_set_epi64x(100, 100);
657 assert_eq_m128i(r, e);
658 }
659
660 #[simd_test(enable = "avx512f")]
661 unsafe fn test_mm512_abs_pd() {
662 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
663 let r = _mm512_abs_pd(a);
664 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
665 assert_eq_m512d(r, e);
666 }
667
668 #[simd_test(enable = "avx512f")]
669 unsafe fn test_mm512_mask_abs_pd() {
670 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
671 let r = _mm512_mask_abs_pd(a, 0, a);
672 assert_eq_m512d(r, a);
673 let r = _mm512_mask_abs_pd(a, 0b00001111, a);
674 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
675 assert_eq_m512d(r, e);
676 }
677
678 #[simd_test(enable = "avx512f")]
679 unsafe fn test_mm512_mask_mov_epi64() {
680 let src = _mm512_set1_epi64(1);
681 let a = _mm512_set1_epi64(2);
682 let r = _mm512_mask_mov_epi64(src, 0, a);
683 assert_eq_m512i(r, src);
684 let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
685 assert_eq_m512i(r, a);
686 }
687
688 #[simd_test(enable = "avx512f")]
689 unsafe fn test_mm512_maskz_mov_epi64() {
690 let a = _mm512_set1_epi64(2);
691 let r = _mm512_maskz_mov_epi64(0, a);
692 assert_eq_m512i(r, _mm512_setzero_si512());
693 let r = _mm512_maskz_mov_epi64(0b11111111, a);
694 assert_eq_m512i(r, a);
695 }
696
697 #[simd_test(enable = "avx512f,avx512vl")]
698 unsafe fn test_mm256_mask_mov_epi64() {
699 let src = _mm256_set1_epi64x(1);
700 let a = _mm256_set1_epi64x(2);
701 let r = _mm256_mask_mov_epi64(src, 0, a);
702 assert_eq_m256i(r, src);
703 let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
704 assert_eq_m256i(r, a);
705 }
706
707 #[simd_test(enable = "avx512f,avx512vl")]
708 unsafe fn test_mm256_maskz_mov_epi64() {
709 let a = _mm256_set1_epi64x(2);
710 let r = _mm256_maskz_mov_epi64(0, a);
711 assert_eq_m256i(r, _mm256_setzero_si256());
712 let r = _mm256_maskz_mov_epi64(0b00001111, a);
713 assert_eq_m256i(r, a);
714 }
715
716 #[simd_test(enable = "avx512f,avx512vl")]
717 unsafe fn test_mm_mask_mov_epi64() {
718 let src = _mm_set1_epi64x(1);
719 let a = _mm_set1_epi64x(2);
720 let r = _mm_mask_mov_epi64(src, 0, a);
721 assert_eq_m128i(r, src);
722 let r = _mm_mask_mov_epi64(src, 0b00000011, a);
723 assert_eq_m128i(r, a);
724 }
725
726 #[simd_test(enable = "avx512f,avx512vl")]
727 unsafe fn test_mm_maskz_mov_epi64() {
728 let a = _mm_set1_epi64x(2);
729 let r = _mm_maskz_mov_epi64(0, a);
730 assert_eq_m128i(r, _mm_setzero_si128());
731 let r = _mm_maskz_mov_epi64(0b00000011, a);
732 assert_eq_m128i(r, a);
733 }
734
735 #[simd_test(enable = "avx512f")]
736 unsafe fn test_mm512_mask_mov_pd() {
737 let src = _mm512_set1_pd(1.);
738 let a = _mm512_set1_pd(2.);
739 let r = _mm512_mask_mov_pd(src, 0, a);
740 assert_eq_m512d(r, src);
741 let r = _mm512_mask_mov_pd(src, 0b11111111, a);
742 assert_eq_m512d(r, a);
743 }
744
745 #[simd_test(enable = "avx512f")]
746 unsafe fn test_mm512_maskz_mov_pd() {
747 let a = _mm512_set1_pd(2.);
748 let r = _mm512_maskz_mov_pd(0, a);
749 assert_eq_m512d(r, _mm512_setzero_pd());
750 let r = _mm512_maskz_mov_pd(0b11111111, a);
751 assert_eq_m512d(r, a);
752 }
753
754 #[simd_test(enable = "avx512f,avx512vl")]
755 unsafe fn test_mm256_mask_mov_pd() {
756 let src = _mm256_set1_pd(1.);
757 let a = _mm256_set1_pd(2.);
758 let r = _mm256_mask_mov_pd(src, 0, a);
759 assert_eq_m256d(r, src);
760 let r = _mm256_mask_mov_pd(src, 0b00001111, a);
761 assert_eq_m256d(r, a);
762 }
763
764 #[simd_test(enable = "avx512f,avx512vl")]
765 unsafe fn test_mm256_maskz_mov_pd() {
766 let a = _mm256_set1_pd(2.);
767 let r = _mm256_maskz_mov_pd(0, a);
768 assert_eq_m256d(r, _mm256_setzero_pd());
769 let r = _mm256_maskz_mov_pd(0b00001111, a);
770 assert_eq_m256d(r, a);
771 }
772
773 #[simd_test(enable = "avx512f,avx512vl")]
774 unsafe fn test_mm_mask_mov_pd() {
775 let src = _mm_set1_pd(1.);
776 let a = _mm_set1_pd(2.);
777 let r = _mm_mask_mov_pd(src, 0, a);
778 assert_eq_m128d(r, src);
779 let r = _mm_mask_mov_pd(src, 0b00000011, a);
780 assert_eq_m128d(r, a);
781 }
782
783 #[simd_test(enable = "avx512f,avx512vl")]
784 unsafe fn test_mm_maskz_mov_pd() {
785 let a = _mm_set1_pd(2.);
786 let r = _mm_maskz_mov_pd(0, a);
787 assert_eq_m128d(r, _mm_setzero_pd());
788 let r = _mm_maskz_mov_pd(0b00000011, a);
789 assert_eq_m128d(r, a);
790 }
791
792 #[simd_test(enable = "avx512f")]
793 unsafe fn test_mm512_add_epi64() {
794 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
795 let b = _mm512_set1_epi64(1);
796 let r = _mm512_add_epi64(a, b);
797 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
798 assert_eq_m512i(r, e);
799 }
800
801 #[simd_test(enable = "avx512f")]
802 unsafe fn test_mm512_mask_add_epi64() {
803 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
804 let b = _mm512_set1_epi64(1);
805 let r = _mm512_mask_add_epi64(a, 0, a, b);
806 assert_eq_m512i(r, a);
807 let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
808 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
809 assert_eq_m512i(r, e);
810 }
811
812 #[simd_test(enable = "avx512f")]
813 unsafe fn test_mm512_maskz_add_epi64() {
814 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
815 let b = _mm512_set1_epi64(1);
816 let r = _mm512_maskz_add_epi64(0, a, b);
817 assert_eq_m512i(r, _mm512_setzero_si512());
818 let r = _mm512_maskz_add_epi64(0b00001111, a, b);
819 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
820 assert_eq_m512i(r, e);
821 }
822
823 #[simd_test(enable = "avx512f,avx512vl")]
824 unsafe fn test_mm256_mask_add_epi64() {
825 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
826 let b = _mm256_set1_epi64x(1);
827 let r = _mm256_mask_add_epi64(a, 0, a, b);
828 assert_eq_m256i(r, a);
829 let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
830 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
831 assert_eq_m256i(r, e);
832 }
833
834 #[simd_test(enable = "avx512f,avx512vl")]
835 unsafe fn test_mm256_maskz_add_epi64() {
836 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
837 let b = _mm256_set1_epi64x(1);
838 let r = _mm256_maskz_add_epi64(0, a, b);
839 assert_eq_m256i(r, _mm256_setzero_si256());
840 let r = _mm256_maskz_add_epi64(0b00001111, a, b);
841 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
842 assert_eq_m256i(r, e);
843 }
844
845 #[simd_test(enable = "avx512f,avx512vl")]
846 unsafe fn test_mm_mask_add_epi64() {
847 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
848 let b = _mm_set1_epi64x(1);
849 let r = _mm_mask_add_epi64(a, 0, a, b);
850 assert_eq_m128i(r, a);
851 let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
852 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
853 assert_eq_m128i(r, e);
854 }
855
856 #[simd_test(enable = "avx512f,avx512vl")]
857 unsafe fn test_mm_maskz_add_epi64() {
858 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
859 let b = _mm_set1_epi64x(1);
860 let r = _mm_maskz_add_epi64(0, a, b);
861 assert_eq_m128i(r, _mm_setzero_si128());
862 let r = _mm_maskz_add_epi64(0b00000011, a, b);
863 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
864 assert_eq_m128i(r, e);
865 }
866
867 #[simd_test(enable = "avx512f")]
868 unsafe fn test_mm512_add_pd() {
869 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
870 let b = _mm512_set1_pd(1.);
871 let r = _mm512_add_pd(a, b);
872 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
873 assert_eq_m512d(r, e);
874 }
875
876 #[simd_test(enable = "avx512f")]
877 unsafe fn test_mm512_mask_add_pd() {
878 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
879 let b = _mm512_set1_pd(1.);
880 let r = _mm512_mask_add_pd(a, 0, a, b);
881 assert_eq_m512d(r, a);
882 let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
883 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
884 assert_eq_m512d(r, e);
885 }
886
887 #[simd_test(enable = "avx512f")]
888 unsafe fn test_mm512_maskz_add_pd() {
889 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
890 let b = _mm512_set1_pd(1.);
891 let r = _mm512_maskz_add_pd(0, a, b);
892 assert_eq_m512d(r, _mm512_setzero_pd());
893 let r = _mm512_maskz_add_pd(0b00001111, a, b);
894 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
895 assert_eq_m512d(r, e);
896 }
897
898 #[simd_test(enable = "avx512f,avx512vl")]
899 unsafe fn test_mm256_mask_add_pd() {
900 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
901 let b = _mm256_set1_pd(1.);
902 let r = _mm256_mask_add_pd(a, 0, a, b);
903 assert_eq_m256d(r, a);
904 let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
905 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
906 assert_eq_m256d(r, e);
907 }
908
909 #[simd_test(enable = "avx512f,avx512vl")]
910 unsafe fn test_mm256_maskz_add_pd() {
911 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
912 let b = _mm256_set1_pd(1.);
913 let r = _mm256_maskz_add_pd(0, a, b);
914 assert_eq_m256d(r, _mm256_setzero_pd());
915 let r = _mm256_maskz_add_pd(0b00001111, a, b);
916 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
917 assert_eq_m256d(r, e);
918 }
919
920 #[simd_test(enable = "avx512f,avx512vl")]
921 unsafe fn test_mm_mask_add_pd() {
922 let a = _mm_set_pd(f64::MAX, f64::MIN);
923 let b = _mm_set1_pd(1.);
924 let r = _mm_mask_add_pd(a, 0, a, b);
925 assert_eq_m128d(r, a);
926 let r = _mm_mask_add_pd(a, 0b00000011, a, b);
927 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
928 assert_eq_m128d(r, e);
929 }
930
931 #[simd_test(enable = "avx512f,avx512vl")]
932 unsafe fn test_mm_maskz_add_pd() {
933 let a = _mm_set_pd(f64::MAX, f64::MIN);
934 let b = _mm_set1_pd(1.);
935 let r = _mm_maskz_add_pd(0, a, b);
936 assert_eq_m128d(r, _mm_setzero_pd());
937 let r = _mm_maskz_add_pd(0b00000011, a, b);
938 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
939 assert_eq_m128d(r, e);
940 }
941
942 #[simd_test(enable = "avx512f")]
943 unsafe fn test_mm512_sub_epi64() {
944 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
945 let b = _mm512_set1_epi64(1);
946 let r = _mm512_sub_epi64(a, b);
947 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
948 assert_eq_m512i(r, e);
949 }
950
951 #[simd_test(enable = "avx512f")]
952 unsafe fn test_mm512_mask_sub_epi64() {
953 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
954 let b = _mm512_set1_epi64(1);
955 let r = _mm512_mask_sub_epi64(a, 0, a, b);
956 assert_eq_m512i(r, a);
957 let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
958 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
959 assert_eq_m512i(r, e);
960 }
961
962 #[simd_test(enable = "avx512f")]
963 unsafe fn test_mm512_maskz_sub_epi64() {
964 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
965 let b = _mm512_set1_epi64(1);
966 let r = _mm512_maskz_sub_epi64(0, a, b);
967 assert_eq_m512i(r, _mm512_setzero_si512());
968 let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
969 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
970 assert_eq_m512i(r, e);
971 }
972
973 #[simd_test(enable = "avx512f,avx512vl")]
974 unsafe fn test_mm256_mask_sub_epi64() {
975 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
976 let b = _mm256_set1_epi64x(1);
977 let r = _mm256_mask_sub_epi64(a, 0, a, b);
978 assert_eq_m256i(r, a);
979 let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
980 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
981 assert_eq_m256i(r, e);
982 }
983
984 #[simd_test(enable = "avx512f,avx512vl")]
985 unsafe fn test_mm256_maskz_sub_epi64() {
986 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
987 let b = _mm256_set1_epi64x(1);
988 let r = _mm256_maskz_sub_epi64(0, a, b);
989 assert_eq_m256i(r, _mm256_setzero_si256());
990 let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
991 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
992 assert_eq_m256i(r, e);
993 }
994
995 #[simd_test(enable = "avx512f,avx512vl")]
996 unsafe fn test_mm_mask_sub_epi64() {
997 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
998 let b = _mm_set1_epi64x(1);
999 let r = _mm_mask_sub_epi64(a, 0, a, b);
1000 assert_eq_m128i(r, a);
1001 let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
1002 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1003 assert_eq_m128i(r, e);
1004 }
1005
1006 #[simd_test(enable = "avx512f,avx512vl")]
1007 unsafe fn test_mm_maskz_sub_epi64() {
1008 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1009 let b = _mm_set1_epi64x(1);
1010 let r = _mm_maskz_sub_epi64(0, a, b);
1011 assert_eq_m128i(r, _mm_setzero_si128());
1012 let r = _mm_maskz_sub_epi64(0b00000011, a, b);
1013 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1014 assert_eq_m128i(r, e);
1015 }
1016
1017 #[simd_test(enable = "avx512f")]
1018 unsafe fn test_mm512_sub_pd() {
1019 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1020 let b = _mm512_set1_pd(1.);
1021 let r = _mm512_sub_pd(a, b);
1022 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
1023 assert_eq_m512d(r, e);
1024 }
1025
1026 #[simd_test(enable = "avx512f")]
1027 unsafe fn test_mm512_mask_sub_pd() {
1028 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1029 let b = _mm512_set1_pd(1.);
1030 let r = _mm512_mask_sub_pd(a, 0, a, b);
1031 assert_eq_m512d(r, a);
1032 let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
1033 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
1034 assert_eq_m512d(r, e);
1035 }
1036
1037 #[simd_test(enable = "avx512f")]
1038 unsafe fn test_mm512_maskz_sub_pd() {
1039 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1040 let b = _mm512_set1_pd(1.);
1041 let r = _mm512_maskz_sub_pd(0, a, b);
1042 assert_eq_m512d(r, _mm512_setzero_pd());
1043 let r = _mm512_maskz_sub_pd(0b00001111, a, b);
1044 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
1045 assert_eq_m512d(r, e);
1046 }
1047
1048 #[simd_test(enable = "avx512f,avx512vl")]
1049 unsafe fn test_mm256_mask_sub_pd() {
1050 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1051 let b = _mm256_set1_pd(1.);
1052 let r = _mm256_mask_sub_pd(a, 0, a, b);
1053 assert_eq_m256d(r, a);
1054 let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
1055 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1056 assert_eq_m256d(r, e);
1057 }
1058
1059 #[simd_test(enable = "avx512f,avx512vl")]
1060 unsafe fn test_mm256_maskz_sub_pd() {
1061 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1062 let b = _mm256_set1_pd(1.);
1063 let r = _mm256_maskz_sub_pd(0, a, b);
1064 assert_eq_m256d(r, _mm256_setzero_pd());
1065 let r = _mm256_maskz_sub_pd(0b00001111, a, b);
1066 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1067 assert_eq_m256d(r, e);
1068 }
1069
1070 #[simd_test(enable = "avx512f,avx512vl")]
1071 unsafe fn test_mm_mask_sub_pd() {
1072 let a = _mm_set_pd(f64::MAX, f64::MIN);
1073 let b = _mm_set1_pd(1.);
1074 let r = _mm_mask_sub_pd(a, 0, a, b);
1075 assert_eq_m128d(r, a);
1076 let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
1077 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1078 assert_eq_m128d(r, e);
1079 }
1080
1081 #[simd_test(enable = "avx512f,avx512vl")]
1082 unsafe fn test_mm_maskz_sub_pd() {
1083 let a = _mm_set_pd(f64::MAX, f64::MIN);
1084 let b = _mm_set1_pd(1.);
1085 let r = _mm_maskz_sub_pd(0, a, b);
1086 assert_eq_m128d(r, _mm_setzero_pd());
1087 let r = _mm_maskz_sub_pd(0b00000011, a, b);
1088 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1089 assert_eq_m128d(r, e);
1090 }
1091
1092 #[simd_test(enable = "avx512f")]
1093 unsafe fn test_mm512_mul_epi32() {
1094 let a = _mm512_set1_epi32(1);
1095 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1096 let r = _mm512_mul_epi32(a, b);
1097 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1098 assert_eq_m512i(r, e);
1099 }
1100
1101 #[simd_test(enable = "avx512f")]
1102 unsafe fn test_mm512_mask_mul_epi32() {
1103 let a = _mm512_set1_epi32(1);
1104 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1105 let r = _mm512_mask_mul_epi32(a, 0, a, b);
1106 assert_eq_m512i(r, a);
1107 let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1108 #[rustfmt::skip]
1109 let e = _mm512_set_epi64(
1110 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1111 7, 5, 3, 1,
1112 );
1113 assert_eq_m512i(r, e);
1114 }
1115
1116 #[simd_test(enable = "avx512f")]
1117 unsafe fn test_mm512_maskz_mul_epi32() {
1118 let a = _mm512_set1_epi32(1);
1119 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1120 let r = _mm512_maskz_mul_epi32(0, a, b);
1121 assert_eq_m512i(r, _mm512_setzero_si512());
1122 let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1123 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1124 assert_eq_m512i(r, e);
1125 }
1126
1127 #[simd_test(enable = "avx512f,avx512vl")]
1128 unsafe fn test_mm256_mask_mul_epi32() {
1129 let a = _mm256_set1_epi32(1);
1130 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1131 let r = _mm256_mask_mul_epi32(a, 0, a, b);
1132 assert_eq_m256i(r, a);
1133 let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1134 let e = _mm256_set_epi64x(2, 4, 6, 8);
1135 assert_eq_m256i(r, e);
1136 }
1137
1138 #[simd_test(enable = "avx512f,avx512vl")]
1139 unsafe fn test_mm256_maskz_mul_epi32() {
1140 let a = _mm256_set1_epi32(1);
1141 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1142 let r = _mm256_maskz_mul_epi32(0, a, b);
1143 assert_eq_m256i(r, _mm256_setzero_si256());
1144 let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1145 let e = _mm256_set_epi64x(2, 4, 6, 8);
1146 assert_eq_m256i(r, e);
1147 }
1148
1149 #[simd_test(enable = "avx512f,avx512vl")]
1150 unsafe fn test_mm_mask_mul_epi32() {
1151 let a = _mm_set1_epi32(1);
1152 let b = _mm_set_epi32(1, 2, 3, 4);
1153 let r = _mm_mask_mul_epi32(a, 0, a, b);
1154 assert_eq_m128i(r, a);
1155 let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1156 let e = _mm_set_epi64x(2, 4);
1157 assert_eq_m128i(r, e);
1158 }
1159
1160 #[simd_test(enable = "avx512f,avx512vl")]
1161 unsafe fn test_mm_maskz_mul_epi32() {
1162 let a = _mm_set1_epi32(1);
1163 let b = _mm_set_epi32(1, 2, 3, 4);
1164 let r = _mm_maskz_mul_epi32(0, a, b);
1165 assert_eq_m128i(r, _mm_setzero_si128());
1166 let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1167 let e = _mm_set_epi64x(2, 4);
1168 assert_eq_m128i(r, e);
1169 }
1170
1171 #[simd_test(enable = "avx512f")]
1172 unsafe fn test_mm512_mul_epu32() {
1173 let a = _mm512_set1_epi32(1);
1174 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1175 let r = _mm512_mul_epu32(a, b);
1176 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1177 assert_eq_m512i(r, e);
1178 }
1179
1180 #[simd_test(enable = "avx512f")]
1181 unsafe fn test_mm512_mask_mul_epu32() {
1182 let a = _mm512_set1_epi32(1);
1183 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1184 let r = _mm512_mask_mul_epu32(a, 0, a, b);
1185 assert_eq_m512i(r, a);
1186 let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1187 #[rustfmt::skip]
1188 let e = _mm512_set_epi64(
1189 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1190 7, 5, 3, 1,
1191 );
1192 assert_eq_m512i(r, e);
1193 }
1194
1195 #[simd_test(enable = "avx512f")]
1196 unsafe fn test_mm512_maskz_mul_epu32() {
1197 let a = _mm512_set1_epi32(1);
1198 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1199 let r = _mm512_maskz_mul_epu32(0, a, b);
1200 assert_eq_m512i(r, _mm512_setzero_si512());
1201 let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1202 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1203 assert_eq_m512i(r, e);
1204 }
1205
1206 #[simd_test(enable = "avx512f,avx512vl")]
1207 unsafe fn test_mm256_mask_mul_epu32() {
1208 let a = _mm256_set1_epi32(1);
1209 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1210 let r = _mm256_mask_mul_epu32(a, 0, a, b);
1211 assert_eq_m256i(r, a);
1212 let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1213 let e = _mm256_set_epi64x(2, 4, 6, 8);
1214 assert_eq_m256i(r, e);
1215 }
1216
1217 #[simd_test(enable = "avx512f,avx512vl")]
1218 unsafe fn test_mm256_maskz_mul_epu32() {
1219 let a = _mm256_set1_epi32(1);
1220 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1221 let r = _mm256_maskz_mul_epu32(0, a, b);
1222 assert_eq_m256i(r, _mm256_setzero_si256());
1223 let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1224 let e = _mm256_set_epi64x(2, 4, 6, 8);
1225 assert_eq_m256i(r, e);
1226 }
1227
1228 #[simd_test(enable = "avx512f,avx512vl")]
1229 unsafe fn test_mm_mask_mul_epu32() {
1230 let a = _mm_set1_epi32(1);
1231 let b = _mm_set_epi32(1, 2, 3, 4);
1232 let r = _mm_mask_mul_epu32(a, 0, a, b);
1233 assert_eq_m128i(r, a);
1234 let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1235 let e = _mm_set_epi64x(2, 4);
1236 assert_eq_m128i(r, e);
1237 }
1238
1239 #[simd_test(enable = "avx512f,avx512vl")]
1240 unsafe fn test_mm_maskz_mul_epu32() {
1241 let a = _mm_set1_epi32(1);
1242 let b = _mm_set_epi32(1, 2, 3, 4);
1243 let r = _mm_maskz_mul_epu32(0, a, b);
1244 assert_eq_m128i(r, _mm_setzero_si128());
1245 let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1246 let e = _mm_set_epi64x(2, 4);
1247 assert_eq_m128i(r, e);
1248 }
1249
1250 #[simd_test(enable = "avx512f")]
1251 unsafe fn test_mm512_mullox_epi64() {
1252 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1253 let b = _mm512_set1_epi64(2);
1254 let r = _mm512_mullox_epi64(a, b);
1255 let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1256 assert_eq_m512i(r, e);
1257 }
1258
1259 #[simd_test(enable = "avx512f")]
1260 unsafe fn test_mm512_mask_mullox_epi64() {
1261 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1262 let b = _mm512_set1_epi64(2);
1263 let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1264 assert_eq_m512i(r, a);
1265 let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1266 let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1267 assert_eq_m512i(r, e);
1268 }
1269
1270 #[simd_test(enable = "avx512f")]
1271 unsafe fn test_mm512_mul_pd() {
1272 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1273 let b = _mm512_set1_pd(2.);
1274 let r = _mm512_mul_pd(a, b);
1275 #[rustfmt::skip]
1276 let e = _mm512_setr_pd(
1277 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1278 f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1279 );
1280 assert_eq_m512d(r, e);
1281 }
1282
1283 #[simd_test(enable = "avx512f")]
1284 unsafe fn test_mm512_mask_mul_pd() {
1285 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1286 let b = _mm512_set1_pd(2.);
1287 let r = _mm512_mask_mul_pd(a, 0, a, b);
1288 assert_eq_m512d(r, a);
1289 let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1290 #[rustfmt::skip]
1291 let e = _mm512_setr_pd(
1292 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1293 f64::MAX, f64::MIN, -100., -32.,
1294 );
1295 assert_eq_m512d(r, e);
1296 }
1297
1298 #[simd_test(enable = "avx512f")]
1299 unsafe fn test_mm512_maskz_mul_pd() {
1300 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1301 let b = _mm512_set1_pd(2.);
1302 let r = _mm512_maskz_mul_pd(0, a, b);
1303 assert_eq_m512d(r, _mm512_setzero_pd());
1304 let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1305 let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1306 assert_eq_m512d(r, e);
1307 }
1308
1309 #[simd_test(enable = "avx512f,avx512vl")]
1310 unsafe fn test_mm256_mask_mul_pd() {
1311 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1312 let b = _mm256_set1_pd(2.);
1313 let r = _mm256_mask_mul_pd(a, 0, a, b);
1314 assert_eq_m256d(r, a);
1315 let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1316 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1317 assert_eq_m256d(r, e);
1318 }
1319
1320 #[simd_test(enable = "avx512f,avx512vl")]
1321 unsafe fn test_mm256_maskz_mul_pd() {
1322 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1323 let b = _mm256_set1_pd(2.);
1324 let r = _mm256_maskz_mul_pd(0, a, b);
1325 assert_eq_m256d(r, _mm256_setzero_pd());
1326 let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1327 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1328 assert_eq_m256d(r, e);
1329 }
1330
1331 #[simd_test(enable = "avx512f,avx512vl")]
1332 unsafe fn test_mm_mask_mul_pd() {
1333 let a = _mm_set_pd(f64::MAX, f64::MIN);
1334 let b = _mm_set1_pd(2.);
1335 let r = _mm_mask_mul_pd(a, 0, a, b);
1336 assert_eq_m128d(r, a);
1337 let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1338 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1339 assert_eq_m128d(r, e);
1340 }
1341
1342 #[simd_test(enable = "avx512f,avx512vl")]
1343 unsafe fn test_mm_maskz_mul_pd() {
1344 let a = _mm_set_pd(f64::MAX, f64::MIN);
1345 let b = _mm_set1_pd(2.);
1346 let r = _mm_maskz_mul_pd(0, a, b);
1347 assert_eq_m128d(r, _mm_setzero_pd());
1348 let r = _mm_maskz_mul_pd(0b00000011, a, b);
1349 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1350 assert_eq_m128d(r, e);
1351 }
1352
1353 #[simd_test(enable = "avx512f")]
1354 unsafe fn test_mm512_div_pd() {
1355 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1356 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1357 let r = _mm512_div_pd(a, b);
1358 #[rustfmt::skip]
1359 let e = _mm512_setr_pd(
1360 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1361 f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1362 );
1363 assert_eq_m512d(r, e);
1364 }
1365
1366 #[simd_test(enable = "avx512f")]
1367 unsafe fn test_mm512_mask_div_pd() {
1368 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1369 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1370 let r = _mm512_mask_div_pd(a, 0, a, b);
1371 assert_eq_m512d(r, a);
1372 let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1373 #[rustfmt::skip]
1374 let e = _mm512_setr_pd(
1375 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1376 f64::MAX, f64::MIN, -100., -32.,
1377 );
1378 assert_eq_m512d(r, e);
1379 }
1380
1381 #[simd_test(enable = "avx512f")]
1382 unsafe fn test_mm512_maskz_div_pd() {
1383 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1384 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1385 let r = _mm512_maskz_div_pd(0, a, b);
1386 assert_eq_m512d(r, _mm512_setzero_pd());
1387 let r = _mm512_maskz_div_pd(0b00001111, a, b);
1388 let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1389 assert_eq_m512d(r, e);
1390 }
1391
1392 #[simd_test(enable = "avx512f,avx512vl")]
1393 unsafe fn test_mm256_mask_div_pd() {
1394 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1395 let b = _mm256_set_pd(2., 2., 0., 0.);
1396 let r = _mm256_mask_div_pd(a, 0, a, b);
1397 assert_eq_m256d(r, a);
1398 let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1399 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1400 assert_eq_m256d(r, e);
1401 }
1402
1403 #[simd_test(enable = "avx512f,avx512vl")]
1404 unsafe fn test_mm256_maskz_div_pd() {
1405 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1406 let b = _mm256_set_pd(2., 2., 0., 0.);
1407 let r = _mm256_maskz_div_pd(0, a, b);
1408 assert_eq_m256d(r, _mm256_setzero_pd());
1409 let r = _mm256_maskz_div_pd(0b00001111, a, b);
1410 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1411 assert_eq_m256d(r, e);
1412 }
1413
1414 #[simd_test(enable = "avx512f,avx512vl")]
1415 unsafe fn test_mm_mask_div_pd() {
1416 let a = _mm_set_pd(f64::MAX, f64::MIN);
1417 let b = _mm_set_pd(0., 0.);
1418 let r = _mm_mask_div_pd(a, 0, a, b);
1419 assert_eq_m128d(r, a);
1420 let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1421 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1422 assert_eq_m128d(r, e);
1423 }
1424
1425 #[simd_test(enable = "avx512f,avx512vl")]
1426 unsafe fn test_mm_maskz_div_pd() {
1427 let a = _mm_set_pd(f64::MAX, f64::MIN);
1428 let b = _mm_set_pd(0., 0.);
1429 let r = _mm_maskz_div_pd(0, a, b);
1430 assert_eq_m128d(r, _mm_setzero_pd());
1431 let r = _mm_maskz_div_pd(0b00000011, a, b);
1432 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1433 assert_eq_m128d(r, e);
1434 }
1435
1436 #[simd_test(enable = "avx512f")]
1437 unsafe fn test_mm512_max_epi64() {
1438 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1439 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1440 let r = _mm512_max_epi64(a, b);
1441 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1442 assert_eq_m512i(r, e);
1443 }
1444
1445 #[simd_test(enable = "avx512f")]
1446 unsafe fn test_mm512_mask_max_epi64() {
1447 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1448 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1449 let r = _mm512_mask_max_epi64(a, 0, a, b);
1450 assert_eq_m512i(r, a);
1451 let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1452 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1453 assert_eq_m512i(r, e);
1454 }
1455
1456 #[simd_test(enable = "avx512f")]
1457 unsafe fn test_mm512_maskz_max_epi64() {
1458 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1459 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1460 let r = _mm512_maskz_max_epi64(0, a, b);
1461 assert_eq_m512i(r, _mm512_setzero_si512());
1462 let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1463 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1464 assert_eq_m512i(r, e);
1465 }
1466
1467 #[simd_test(enable = "avx512f,avx512vl")]
1468 unsafe fn test_mm256_max_epi64() {
1469 let a = _mm256_set_epi64x(0, 1, 2, 3);
1470 let b = _mm256_set_epi64x(3, 2, 1, 0);
1471 let r = _mm256_max_epi64(a, b);
1472 let e = _mm256_set_epi64x(3, 2, 2, 3);
1473 assert_eq_m256i(r, e);
1474 }
1475
1476 #[simd_test(enable = "avx512f,avx512vl")]
1477 unsafe fn test_mm256_mask_max_epi64() {
1478 let a = _mm256_set_epi64x(0, 1, 2, 3);
1479 let b = _mm256_set_epi64x(3, 2, 1, 0);
1480 let r = _mm256_mask_max_epi64(a, 0, a, b);
1481 assert_eq_m256i(r, a);
1482 let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1483 let e = _mm256_set_epi64x(3, 2, 2, 3);
1484 assert_eq_m256i(r, e);
1485 }
1486
1487 #[simd_test(enable = "avx512f,avx512vl")]
1488 unsafe fn test_mm256_maskz_max_epi64() {
1489 let a = _mm256_set_epi64x(0, 1, 2, 3);
1490 let b = _mm256_set_epi64x(3, 2, 1, 0);
1491 let r = _mm256_maskz_max_epi64(0, a, b);
1492 assert_eq_m256i(r, _mm256_setzero_si256());
1493 let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1494 let e = _mm256_set_epi64x(3, 2, 2, 3);
1495 assert_eq_m256i(r, e);
1496 }
1497
1498 #[simd_test(enable = "avx512f,avx512vl")]
1499 unsafe fn test_mm_max_epi64() {
1500 let a = _mm_set_epi64x(2, 3);
1501 let b = _mm_set_epi64x(3, 2);
1502 let r = _mm_max_epi64(a, b);
1503 let e = _mm_set_epi64x(3, 3);
1504 assert_eq_m128i(r, e);
1505 }
1506
1507 #[simd_test(enable = "avx512f,avx512vl")]
1508 unsafe fn test_mm_mask_max_epi64() {
1509 let a = _mm_set_epi64x(2, 3);
1510 let b = _mm_set_epi64x(3, 2);
1511 let r = _mm_mask_max_epi64(a, 0, a, b);
1512 assert_eq_m128i(r, a);
1513 let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1514 let e = _mm_set_epi64x(3, 3);
1515 assert_eq_m128i(r, e);
1516 }
1517
1518 #[simd_test(enable = "avx512f,avx512vl")]
1519 unsafe fn test_mm_maskz_max_epi64() {
1520 let a = _mm_set_epi64x(2, 3);
1521 let b = _mm_set_epi64x(3, 2);
1522 let r = _mm_maskz_max_epi64(0, a, b);
1523 assert_eq_m128i(r, _mm_setzero_si128());
1524 let r = _mm_maskz_max_epi64(0b00000011, a, b);
1525 let e = _mm_set_epi64x(3, 3);
1526 assert_eq_m128i(r, e);
1527 }
1528
1529 #[simd_test(enable = "avx512f")]
1530 unsafe fn test_mm512_max_pd() {
1531 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1532 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1533 let r = _mm512_max_pd(a, b);
1534 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1535 assert_eq_m512d(r, e);
1536 }
1537
1538 #[simd_test(enable = "avx512f")]
1539 unsafe fn test_mm512_mask_max_pd() {
1540 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1541 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1542 let r = _mm512_mask_max_pd(a, 0, a, b);
1543 assert_eq_m512d(r, a);
1544 let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1545 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1546 assert_eq_m512d(r, e);
1547 }
1548
1549 #[simd_test(enable = "avx512f")]
1550 unsafe fn test_mm512_maskz_max_pd() {
1551 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1552 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1553 let r = _mm512_maskz_max_pd(0, a, b);
1554 assert_eq_m512d(r, _mm512_setzero_pd());
1555 let r = _mm512_maskz_max_pd(0b00001111, a, b);
1556 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1557 assert_eq_m512d(r, e);
1558 }
1559
1560 #[simd_test(enable = "avx512f,avx512vl")]
1561 unsafe fn test_mm256_mask_max_pd() {
1562 let a = _mm256_set_pd(0., 1., 2., 3.);
1563 let b = _mm256_set_pd(3., 2., 1., 0.);
1564 let r = _mm256_mask_max_pd(a, 0, a, b);
1565 assert_eq_m256d(r, a);
1566 let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1567 let e = _mm256_set_pd(3., 2., 2., 3.);
1568 assert_eq_m256d(r, e);
1569 }
1570
1571 #[simd_test(enable = "avx512f,avx512vl")]
1572 unsafe fn test_mm256_maskz_max_pd() {
1573 let a = _mm256_set_pd(0., 1., 2., 3.);
1574 let b = _mm256_set_pd(3., 2., 1., 0.);
1575 let r = _mm256_maskz_max_pd(0, a, b);
1576 assert_eq_m256d(r, _mm256_setzero_pd());
1577 let r = _mm256_maskz_max_pd(0b00001111, a, b);
1578 let e = _mm256_set_pd(3., 2., 2., 3.);
1579 assert_eq_m256d(r, e);
1580 }
1581
1582 #[simd_test(enable = "avx512f,avx512vl")]
1583 unsafe fn test_mm_mask_max_pd() {
1584 let a = _mm_set_pd(2., 3.);
1585 let b = _mm_set_pd(3., 2.);
1586 let r = _mm_mask_max_pd(a, 0, a, b);
1587 assert_eq_m128d(r, a);
1588 let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1589 let e = _mm_set_pd(3., 3.);
1590 assert_eq_m128d(r, e);
1591 }
1592
1593 #[simd_test(enable = "avx512f,avx512vl")]
1594 unsafe fn test_mm_maskz_max_pd() {
1595 let a = _mm_set_pd(2., 3.);
1596 let b = _mm_set_pd(3., 2.);
1597 let r = _mm_maskz_max_pd(0, a, b);
1598 assert_eq_m128d(r, _mm_setzero_pd());
1599 let r = _mm_maskz_max_pd(0b00000011, a, b);
1600 let e = _mm_set_pd(3., 3.);
1601 assert_eq_m128d(r, e);
1602 }
1603
1604 #[simd_test(enable = "avx512f")]
1605 unsafe fn test_mm512_max_epu64() {
1606 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1607 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1608 let r = _mm512_max_epu64(a, b);
1609 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1610 assert_eq_m512i(r, e);
1611 }
1612
1613 #[simd_test(enable = "avx512f")]
1614 unsafe fn test_mm512_mask_max_epu64() {
1615 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1616 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1617 let r = _mm512_mask_max_epu64(a, 0, a, b);
1618 assert_eq_m512i(r, a);
1619 let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1620 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1621 assert_eq_m512i(r, e);
1622 }
1623
1624 #[simd_test(enable = "avx512f")]
1625 unsafe fn test_mm512_maskz_max_epu64() {
1626 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1627 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1628 let r = _mm512_maskz_max_epu64(0, a, b);
1629 assert_eq_m512i(r, _mm512_setzero_si512());
1630 let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1631 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1632 assert_eq_m512i(r, e);
1633 }
1634
1635 #[simd_test(enable = "avx512f,avx512vl")]
1636 unsafe fn test_mm256_max_epu64() {
1637 let a = _mm256_set_epi64x(0, 1, 2, 3);
1638 let b = _mm256_set_epi64x(3, 2, 1, 0);
1639 let r = _mm256_max_epu64(a, b);
1640 let e = _mm256_set_epi64x(3, 2, 2, 3);
1641 assert_eq_m256i(r, e);
1642 }
1643
1644 #[simd_test(enable = "avx512f,avx512vl")]
1645 unsafe fn test_mm256_mask_max_epu64() {
1646 let a = _mm256_set_epi64x(0, 1, 2, 3);
1647 let b = _mm256_set_epi64x(3, 2, 1, 0);
1648 let r = _mm256_mask_max_epu64(a, 0, a, b);
1649 assert_eq_m256i(r, a);
1650 let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1651 let e = _mm256_set_epi64x(3, 2, 2, 3);
1652 assert_eq_m256i(r, e);
1653 }
1654
1655 #[simd_test(enable = "avx512f,avx512vl")]
1656 unsafe fn test_mm256_maskz_max_epu64() {
1657 let a = _mm256_set_epi64x(0, 1, 2, 3);
1658 let b = _mm256_set_epi64x(3, 2, 1, 0);
1659 let r = _mm256_maskz_max_epu64(0, a, b);
1660 assert_eq_m256i(r, _mm256_setzero_si256());
1661 let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1662 let e = _mm256_set_epi64x(3, 2, 2, 3);
1663 assert_eq_m256i(r, e);
1664 }
1665
1666 #[simd_test(enable = "avx512f,avx512vl")]
1667 unsafe fn test_mm_max_epu64() {
1668 let a = _mm_set_epi64x(2, 3);
1669 let b = _mm_set_epi64x(3, 2);
1670 let r = _mm_max_epu64(a, b);
1671 let e = _mm_set_epi64x(3, 3);
1672 assert_eq_m128i(r, e);
1673 }
1674
1675 #[simd_test(enable = "avx512f,avx512vl")]
1676 unsafe fn test_mm_mask_max_epu64() {
1677 let a = _mm_set_epi64x(2, 3);
1678 let b = _mm_set_epi64x(3, 2);
1679 let r = _mm_mask_max_epu64(a, 0, a, b);
1680 assert_eq_m128i(r, a);
1681 let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1682 let e = _mm_set_epi64x(3, 3);
1683 assert_eq_m128i(r, e);
1684 }
1685
1686 #[simd_test(enable = "avx512f,avx512vl")]
1687 unsafe fn test_mm_maskz_max_epu64() {
1688 let a = _mm_set_epi64x(2, 3);
1689 let b = _mm_set_epi64x(3, 2);
1690 let r = _mm_maskz_max_epu64(0, a, b);
1691 assert_eq_m128i(r, _mm_setzero_si128());
1692 let r = _mm_maskz_max_epu64(0b00000011, a, b);
1693 let e = _mm_set_epi64x(3, 3);
1694 assert_eq_m128i(r, e);
1695 }
1696
1697 #[simd_test(enable = "avx512f")]
1698 unsafe fn test_mm512_min_epi64() {
1699 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1700 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1701 let r = _mm512_min_epi64(a, b);
1702 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1703 assert_eq_m512i(r, e);
1704 }
1705
1706 #[simd_test(enable = "avx512f")]
1707 unsafe fn test_mm512_mask_min_epi64() {
1708 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1709 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1710 let r = _mm512_mask_min_epi64(a, 0, a, b);
1711 assert_eq_m512i(r, a);
1712 let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1713 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1714 assert_eq_m512i(r, e);
1715 }
1716
1717 #[simd_test(enable = "avx512f")]
1718 unsafe fn test_mm512_maskz_min_epi64() {
1719 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1720 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1721 let r = _mm512_maskz_min_epi64(0, a, b);
1722 assert_eq_m512i(r, _mm512_setzero_si512());
1723 let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1724 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1725 assert_eq_m512i(r, e);
1726 }
1727
1728 #[simd_test(enable = "avx512f,avx512vl")]
1729 unsafe fn test_mm256_min_epi64() {
1730 let a = _mm256_set_epi64x(0, 1, 2, 3);
1731 let b = _mm256_set_epi64x(3, 2, 1, 0);
1732 let r = _mm256_min_epi64(a, b);
1733 let e = _mm256_set_epi64x(0, 1, 1, 0);
1734 assert_eq_m256i(r, e);
1735 }
1736
1737 #[simd_test(enable = "avx512f,avx512vl")]
1738 unsafe fn test_mm256_mask_min_epi64() {
1739 let a = _mm256_set_epi64x(0, 1, 2, 3);
1740 let b = _mm256_set_epi64x(3, 2, 1, 0);
1741 let r = _mm256_mask_min_epi64(a, 0, a, b);
1742 assert_eq_m256i(r, a);
1743 let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1744 let e = _mm256_set_epi64x(0, 1, 1, 0);
1745 assert_eq_m256i(r, e);
1746 }
1747
1748 #[simd_test(enable = "avx512f,avx512vl")]
1749 unsafe fn test_mm256_maskz_min_epi64() {
1750 let a = _mm256_set_epi64x(0, 1, 2, 3);
1751 let b = _mm256_set_epi64x(3, 2, 1, 0);
1752 let r = _mm256_maskz_min_epi64(0, a, b);
1753 assert_eq_m256i(r, _mm256_setzero_si256());
1754 let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1755 let e = _mm256_set_epi64x(0, 1, 1, 0);
1756 assert_eq_m256i(r, e);
1757 }
1758
1759 #[simd_test(enable = "avx512f,avx512vl")]
1760 unsafe fn test_mm_min_epi64() {
1761 let a = _mm_set_epi64x(0, 1);
1762 let b = _mm_set_epi64x(3, 2);
1763 let r = _mm_min_epi64(a, b);
1764 let e = _mm_set_epi64x(0, 1);
1765 assert_eq_m128i(r, e);
1766 let a = _mm_set_epi64x(2, 3);
1767 let b = _mm_set_epi64x(1, 0);
1768 let r = _mm_min_epi64(a, b);
1769 let e = _mm_set_epi64x(1, 0);
1770 assert_eq_m128i(r, e);
1771 }
1772
1773 #[simd_test(enable = "avx512f,avx512vl")]
1774 unsafe fn test_mm_mask_min_epi64() {
1775 let a = _mm_set_epi64x(0, 1);
1776 let b = _mm_set_epi64x(3, 2);
1777 let r = _mm_mask_min_epi64(a, 0, a, b);
1778 assert_eq_m128i(r, a);
1779 let r = _mm_mask_min_epi64(a, 0b00000011, a, b);
1780 let e = _mm_set_epi64x(0, 1);
1781 assert_eq_m128i(r, e);
1782 }
1783
1784 #[simd_test(enable = "avx512f,avx512vl")]
1785 unsafe fn test_mm_maskz_min_epi64() {
1786 let a = _mm_set_epi64x(0, 1);
1787 let b = _mm_set_epi64x(3, 2);
1788 let r = _mm_maskz_min_epi64(0, a, b);
1789 assert_eq_m128i(r, _mm_setzero_si128());
1790 let r = _mm_maskz_min_epi64(0b00000011, a, b);
1791 let e = _mm_set_epi64x(0, 1);
1792 assert_eq_m128i(r, e);
1793 }
1794
1795 #[simd_test(enable = "avx512f")]
1796 unsafe fn test_mm512_min_pd() {
1797 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1798 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1799 let r = _mm512_min_pd(a, b);
1800 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1801 assert_eq_m512d(r, e);
1802 }
1803
1804 #[simd_test(enable = "avx512f")]
1805 unsafe fn test_mm512_mask_min_pd() {
1806 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1807 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1808 let r = _mm512_mask_min_pd(a, 0, a, b);
1809 assert_eq_m512d(r, a);
1810 let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1811 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1812 assert_eq_m512d(r, e);
1813 }
1814
1815 #[simd_test(enable = "avx512f")]
1816 unsafe fn test_mm512_maskz_min_pd() {
1817 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1818 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1819 let r = _mm512_maskz_min_pd(0, a, b);
1820 assert_eq_m512d(r, _mm512_setzero_pd());
1821 let r = _mm512_maskz_min_pd(0b00001111, a, b);
1822 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1823 assert_eq_m512d(r, e);
1824 }
1825
1826 #[simd_test(enable = "avx512f,avx512vl")]
1827 unsafe fn test_mm256_mask_min_pd() {
1828 let a = _mm256_set_pd(0., 1., 2., 3.);
1829 let b = _mm256_set_pd(3., 2., 1., 0.);
1830 let r = _mm256_mask_min_pd(a, 0, a, b);
1831 assert_eq_m256d(r, a);
1832 let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1833 let e = _mm256_set_pd(0., 1., 1., 0.);
1834 assert_eq_m256d(r, e);
1835 }
1836
1837 #[simd_test(enable = "avx512f,avx512vl")]
1838 unsafe fn test_mm256_maskz_min_pd() {
1839 let a = _mm256_set_pd(0., 1., 2., 3.);
1840 let b = _mm256_set_pd(3., 2., 1., 0.);
1841 let r = _mm256_maskz_min_pd(0, a, b);
1842 assert_eq_m256d(r, _mm256_setzero_pd());
1843 let r = _mm256_maskz_min_pd(0b00001111, a, b);
1844 let e = _mm256_set_pd(0., 1., 1., 0.);
1845 assert_eq_m256d(r, e);
1846 }
1847
1848 #[simd_test(enable = "avx512f,avx512vl")]
1849 unsafe fn test_mm_mask_min_pd() {
1850 let a = _mm_set_pd(0., 1.);
1851 let b = _mm_set_pd(1., 0.);
1852 let r = _mm_mask_min_pd(a, 0, a, b);
1853 assert_eq_m128d(r, a);
1854 let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1855 let e = _mm_set_pd(0., 0.);
1856 assert_eq_m128d(r, e);
1857 }
1858
1859 #[simd_test(enable = "avx512f,avx512vl")]
1860 unsafe fn test_mm_maskz_min_pd() {
1861 let a = _mm_set_pd(0., 1.);
1862 let b = _mm_set_pd(1., 0.);
1863 let r = _mm_maskz_min_pd(0, a, b);
1864 assert_eq_m128d(r, _mm_setzero_pd());
1865 let r = _mm_maskz_min_pd(0b00000011, a, b);
1866 let e = _mm_set_pd(0., 0.);
1867 assert_eq_m128d(r, e);
1868 }
1869
1870 #[simd_test(enable = "avx512f")]
1871 unsafe fn test_mm512_min_epu64() {
1872 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1873 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1874 let r = _mm512_min_epu64(a, b);
1875 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1876 assert_eq_m512i(r, e);
1877 }
1878
1879 #[simd_test(enable = "avx512f")]
1880 unsafe fn test_mm512_mask_min_epu64() {
1881 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1882 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1883 let r = _mm512_mask_min_epu64(a, 0, a, b);
1884 assert_eq_m512i(r, a);
1885 let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1886 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1887 assert_eq_m512i(r, e);
1888 }
1889
1890 #[simd_test(enable = "avx512f")]
1891 unsafe fn test_mm512_maskz_min_epu64() {
1892 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1893 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1894 let r = _mm512_maskz_min_epu64(0, a, b);
1895 assert_eq_m512i(r, _mm512_setzero_si512());
1896 let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1897 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1898 assert_eq_m512i(r, e);
1899 }
1900
1901 #[simd_test(enable = "avx512f,avx512vl")]
1902 unsafe fn test_mm256_min_epu64() {
1903 let a = _mm256_set_epi64x(0, 1, 2, 3);
1904 let b = _mm256_set_epi64x(3, 2, 1, 0);
1905 let r = _mm256_min_epu64(a, b);
1906 let e = _mm256_set_epi64x(0, 1, 1, 0);
1907 assert_eq_m256i(r, e);
1908 }
1909
1910 #[simd_test(enable = "avx512f,avx512vl")]
1911 unsafe fn test_mm256_mask_min_epu64() {
1912 let a = _mm256_set_epi64x(0, 1, 2, 3);
1913 let b = _mm256_set_epi64x(3, 2, 1, 0);
1914 let r = _mm256_mask_min_epu64(a, 0, a, b);
1915 assert_eq_m256i(r, a);
1916 let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1917 let e = _mm256_set_epi64x(0, 1, 1, 0);
1918 assert_eq_m256i(r, e);
1919 }
1920
1921 #[simd_test(enable = "avx512f,avx512vl")]
1922 unsafe fn test_mm256_maskz_min_epu64() {
1923 let a = _mm256_set_epi64x(0, 1, 2, 3);
1924 let b = _mm256_set_epi64x(3, 2, 1, 0);
1925 let r = _mm256_maskz_min_epu64(0, a, b);
1926 assert_eq_m256i(r, _mm256_setzero_si256());
1927 let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1928 let e = _mm256_set_epi64x(0, 1, 1, 0);
1929 assert_eq_m256i(r, e);
1930 }
1931
1932 #[simd_test(enable = "avx512f,avx512vl")]
1933 unsafe fn test_mm_min_epu64() {
1934 let a = _mm_set_epi64x(0, 1);
1935 let b = _mm_set_epi64x(1, 0);
1936 let r = _mm_min_epu64(a, b);
1937 let e = _mm_set_epi64x(0, 0);
1938 assert_eq_m128i(r, e);
1939 }
1940
1941 #[simd_test(enable = "avx512f,avx512vl")]
1942 unsafe fn test_mm_mask_min_epu64() {
1943 let a = _mm_set_epi64x(0, 1);
1944 let b = _mm_set_epi64x(1, 0);
1945 let r = _mm_mask_min_epu64(a, 0, a, b);
1946 assert_eq_m128i(r, a);
1947 let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1948 let e = _mm_set_epi64x(0, 0);
1949 assert_eq_m128i(r, e);
1950 }
1951
1952 #[simd_test(enable = "avx512f,avx512vl")]
1953 unsafe fn test_mm_maskz_min_epu64() {
1954 let a = _mm_set_epi64x(0, 1);
1955 let b = _mm_set_epi64x(1, 0);
1956 let r = _mm_maskz_min_epu64(0, a, b);
1957 assert_eq_m128i(r, _mm_setzero_si128());
1958 let r = _mm_maskz_min_epu64(0b00000011, a, b);
1959 let e = _mm_set_epi64x(0, 0);
1960 assert_eq_m128i(r, e);
1961 }
1962
1963 #[simd_test(enable = "avx512f")]
1964 unsafe fn test_mm512_sqrt_pd() {
1965 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1966 let r = _mm512_sqrt_pd(a);
1967 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1968 assert_eq_m512d(r, e);
1969 }
1970
1971 #[simd_test(enable = "avx512f")]
1972 unsafe fn test_mm512_mask_sqrt_pd() {
1973 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1974 let r = _mm512_mask_sqrt_pd(a, 0, a);
1975 assert_eq_m512d(r, a);
1976 let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1977 let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1978 assert_eq_m512d(r, e);
1979 }
1980
1981 #[simd_test(enable = "avx512f")]
1982 unsafe fn test_mm512_maskz_sqrt_pd() {
1983 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1984 let r = _mm512_maskz_sqrt_pd(0, a);
1985 assert_eq_m512d(r, _mm512_setzero_pd());
1986 let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1987 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1988 assert_eq_m512d(r, e);
1989 }
1990
1991 #[simd_test(enable = "avx512f,avx512vl")]
1992 unsafe fn test_mm256_mask_sqrt_pd() {
1993 let a = _mm256_set_pd(0., 1., 4., 9.);
1994 let r = _mm256_mask_sqrt_pd(a, 0, a);
1995 assert_eq_m256d(r, a);
1996 let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
1997 let e = _mm256_set_pd(0., 1., 2., 3.);
1998 assert_eq_m256d(r, e);
1999 }
2000
2001 #[simd_test(enable = "avx512f,avx512vl")]
2002 unsafe fn test_mm256_maskz_sqrt_pd() {
2003 let a = _mm256_set_pd(0., 1., 4., 9.);
2004 let r = _mm256_maskz_sqrt_pd(0, a);
2005 assert_eq_m256d(r, _mm256_setzero_pd());
2006 let r = _mm256_maskz_sqrt_pd(0b00001111, a);
2007 let e = _mm256_set_pd(0., 1., 2., 3.);
2008 assert_eq_m256d(r, e);
2009 }
2010
2011 #[simd_test(enable = "avx512f,avx512vl")]
2012 unsafe fn test_mm_mask_sqrt_pd() {
2013 let a = _mm_set_pd(0., 1.);
2014 let r = _mm_mask_sqrt_pd(a, 0, a);
2015 assert_eq_m128d(r, a);
2016 let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
2017 let e = _mm_set_pd(0., 1.);
2018 assert_eq_m128d(r, e);
2019 }
2020
2021 #[simd_test(enable = "avx512f,avx512vl")]
2022 unsafe fn test_mm_maskz_sqrt_pd() {
2023 let a = _mm_set_pd(0., 1.);
2024 let r = _mm_maskz_sqrt_pd(0, a);
2025 assert_eq_m128d(r, _mm_setzero_pd());
2026 let r = _mm_maskz_sqrt_pd(0b00000011, a);
2027 let e = _mm_set_pd(0., 1.);
2028 assert_eq_m128d(r, e);
2029 }
2030
2031 #[simd_test(enable = "avx512f")]
2032 unsafe fn test_mm512_fmadd_pd() {
2033 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2034 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2035 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2036 let r = _mm512_fmadd_pd(a, b, c);
2037 let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
2038 assert_eq_m512d(r, e);
2039 }
2040
2041 #[simd_test(enable = "avx512f")]
2042 unsafe fn test_mm512_mask_fmadd_pd() {
2043 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2044 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2045 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2046 let r = _mm512_mask_fmadd_pd(a, 0, b, c);
2047 assert_eq_m512d(r, a);
2048 let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
2049 let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
2050 assert_eq_m512d(r, e);
2051 }
2052
2053 #[simd_test(enable = "avx512f")]
2054 unsafe fn test_mm512_maskz_fmadd_pd() {
2055 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2056 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2057 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2058 let r = _mm512_maskz_fmadd_pd(0, a, b, c);
2059 assert_eq_m512d(r, _mm512_setzero_pd());
2060 let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
2061 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
2062 assert_eq_m512d(r, e);
2063 }
2064
2065 #[simd_test(enable = "avx512f")]
2066 unsafe fn test_mm512_mask3_fmadd_pd() {
2067 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2068 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2069 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2070 let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
2071 assert_eq_m512d(r, c);
2072 let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
2073 let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
2074 assert_eq_m512d(r, e);
2075 }
2076
2077 #[simd_test(enable = "avx512f,avx512vl")]
2078 unsafe fn test_mm256_mask_fmadd_pd() {
2079 let a = _mm256_set1_pd(1.);
2080 let b = _mm256_set_pd(0., 1., 2., 3.);
2081 let c = _mm256_set1_pd(1.);
2082 let r = _mm256_mask_fmadd_pd(a, 0, b, c);
2083 assert_eq_m256d(r, a);
2084 let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
2085 let e = _mm256_set_pd(1., 2., 3., 4.);
2086 assert_eq_m256d(r, e);
2087 }
2088
2089 #[simd_test(enable = "avx512f,avx512vl")]
2090 unsafe fn test_mm256_maskz_fmadd_pd() {
2091 let a = _mm256_set1_pd(1.);
2092 let b = _mm256_set_pd(0., 1., 2., 3.);
2093 let c = _mm256_set1_pd(1.);
2094 let r = _mm256_maskz_fmadd_pd(0, a, b, c);
2095 assert_eq_m256d(r, _mm256_setzero_pd());
2096 let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
2097 let e = _mm256_set_pd(1., 2., 3., 4.);
2098 assert_eq_m256d(r, e);
2099 }
2100
2101 #[simd_test(enable = "avx512f,avx512vl")]
2102 unsafe fn test_mm256_mask3_fmadd_pd() {
2103 let a = _mm256_set1_pd(1.);
2104 let b = _mm256_set_pd(0., 1., 2., 3.);
2105 let c = _mm256_set1_pd(1.);
2106 let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
2107 assert_eq_m256d(r, c);
2108 let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
2109 let e = _mm256_set_pd(1., 2., 3., 4.);
2110 assert_eq_m256d(r, e);
2111 }
2112
2113 #[simd_test(enable = "avx512f,avx512vl")]
2114 unsafe fn test_mm_mask_fmadd_pd() {
2115 let a = _mm_set1_pd(1.);
2116 let b = _mm_set_pd(0., 1.);
2117 let c = _mm_set1_pd(1.);
2118 let r = _mm_mask_fmadd_pd(a, 0, b, c);
2119 assert_eq_m128d(r, a);
2120 let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
2121 let e = _mm_set_pd(1., 2.);
2122 assert_eq_m128d(r, e);
2123 }
2124
2125 #[simd_test(enable = "avx512f,avx512vl")]
2126 unsafe fn test_mm_maskz_fmadd_pd() {
2127 let a = _mm_set1_pd(1.);
2128 let b = _mm_set_pd(0., 1.);
2129 let c = _mm_set1_pd(1.);
2130 let r = _mm_maskz_fmadd_pd(0, a, b, c);
2131 assert_eq_m128d(r, _mm_setzero_pd());
2132 let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2133 let e = _mm_set_pd(1., 2.);
2134 assert_eq_m128d(r, e);
2135 }
2136
2137 #[simd_test(enable = "avx512f,avx512vl")]
2138 unsafe fn test_mm_mask3_fmadd_pd() {
2139 let a = _mm_set1_pd(1.);
2140 let b = _mm_set_pd(0., 1.);
2141 let c = _mm_set1_pd(1.);
2142 let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2143 assert_eq_m128d(r, c);
2144 let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2145 let e = _mm_set_pd(1., 2.);
2146 assert_eq_m128d(r, e);
2147 }
2148
2149 #[simd_test(enable = "avx512f")]
2150 unsafe fn test_mm512_fmsub_pd() {
2151 let a = _mm512_set1_pd(1.);
2152 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2153 let c = _mm512_set1_pd(1.);
2154 let r = _mm512_fmsub_pd(a, b, c);
2155 let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2156 assert_eq_m512d(r, e);
2157 }
2158
2159 #[simd_test(enable = "avx512f")]
2160 unsafe fn test_mm512_mask_fmsub_pd() {
2161 let a = _mm512_set1_pd(1.);
2162 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2163 let c = _mm512_set1_pd(1.);
2164 let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2165 assert_eq_m512d(r, a);
2166 let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2167 let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2168 assert_eq_m512d(r, e);
2169 }
2170
2171 #[simd_test(enable = "avx512f")]
2172 unsafe fn test_mm512_maskz_fmsub_pd() {
2173 let a = _mm512_set1_pd(1.);
2174 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2175 let c = _mm512_set1_pd(1.);
2176 let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2177 assert_eq_m512d(r, _mm512_setzero_pd());
2178 let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2179 let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2180 assert_eq_m512d(r, e);
2181 }
2182
2183 #[simd_test(enable = "avx512f")]
2184 unsafe fn test_mm512_mask3_fmsub_pd() {
2185 let a = _mm512_set1_pd(1.);
2186 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2187 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2188 let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2189 assert_eq_m512d(r, c);
2190 let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2191 let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2192 assert_eq_m512d(r, e);
2193 }
2194
2195 #[simd_test(enable = "avx512f,avx512vl")]
2196 unsafe fn test_mm256_mask_fmsub_pd() {
2197 let a = _mm256_set1_pd(1.);
2198 let b = _mm256_set_pd(0., 1., 2., 3.);
2199 let c = _mm256_set1_pd(1.);
2200 let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2201 assert_eq_m256d(r, a);
2202 let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2203 let e = _mm256_set_pd(-1., 0., 1., 2.);
2204 assert_eq_m256d(r, e);
2205 }
2206
2207 #[simd_test(enable = "avx512f,avx512vl")]
2208 unsafe fn test_mm256_maskz_fmsub_pd() {
2209 let a = _mm256_set1_pd(1.);
2210 let b = _mm256_set_pd(0., 1., 2., 3.);
2211 let c = _mm256_set1_pd(1.);
2212 let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2213 assert_eq_m256d(r, _mm256_setzero_pd());
2214 let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2215 let e = _mm256_set_pd(-1., 0., 1., 2.);
2216 assert_eq_m256d(r, e);
2217 }
2218
2219 #[simd_test(enable = "avx512f,avx512vl")]
2220 unsafe fn test_mm256_mask3_fmsub_pd() {
2221 let a = _mm256_set1_pd(1.);
2222 let b = _mm256_set_pd(0., 1., 2., 3.);
2223 let c = _mm256_set1_pd(1.);
2224 let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2225 assert_eq_m256d(r, c);
2226 let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2227 let e = _mm256_set_pd(-1., 0., 1., 2.);
2228 assert_eq_m256d(r, e);
2229 }
2230
2231 #[simd_test(enable = "avx512f,avx512vl")]
2232 unsafe fn test_mm_mask_fmsub_pd() {
2233 let a = _mm_set1_pd(1.);
2234 let b = _mm_set_pd(0., 1.);
2235 let c = _mm_set1_pd(1.);
2236 let r = _mm_mask_fmsub_pd(a, 0, b, c);
2237 assert_eq_m128d(r, a);
2238 let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2239 let e = _mm_set_pd(-1., 0.);
2240 assert_eq_m128d(r, e);
2241 }
2242
2243 #[simd_test(enable = "avx512f,avx512vl")]
2244 unsafe fn test_mm_maskz_fmsub_pd() {
2245 let a = _mm_set1_pd(1.);
2246 let b = _mm_set_pd(0., 1.);
2247 let c = _mm_set1_pd(1.);
2248 let r = _mm_maskz_fmsub_pd(0, a, b, c);
2249 assert_eq_m128d(r, _mm_setzero_pd());
2250 let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2251 let e = _mm_set_pd(-1., 0.);
2252 assert_eq_m128d(r, e);
2253 }
2254
2255 #[simd_test(enable = "avx512f,avx512vl")]
2256 unsafe fn test_mm_mask3_fmsub_pd() {
2257 let a = _mm_set1_pd(1.);
2258 let b = _mm_set_pd(0., 1.);
2259 let c = _mm_set1_pd(1.);
2260 let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2261 assert_eq_m128d(r, c);
2262 let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2263 let e = _mm_set_pd(-1., 0.);
2264 assert_eq_m128d(r, e);
2265 }
2266
2267 #[simd_test(enable = "avx512f")]
2268 unsafe fn test_mm512_fmaddsub_pd() {
2269 let a = _mm512_set1_pd(1.);
2270 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2271 let c = _mm512_set1_pd(1.);
2272 let r = _mm512_fmaddsub_pd(a, b, c);
2273 let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2274 assert_eq_m512d(r, e);
2275 }
2276
2277 #[simd_test(enable = "avx512f")]
2278 unsafe fn test_mm512_mask_fmaddsub_pd() {
2279 let a = _mm512_set1_pd(1.);
2280 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2281 let c = _mm512_set1_pd(1.);
2282 let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2283 assert_eq_m512d(r, a);
2284 let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2285 let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2286 assert_eq_m512d(r, e);
2287 }
2288
2289 #[simd_test(enable = "avx512f")]
2290 unsafe fn test_mm512_maskz_fmaddsub_pd() {
2291 let a = _mm512_set1_pd(1.);
2292 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2293 let c = _mm512_set1_pd(1.);
2294 let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2295 assert_eq_m512d(r, _mm512_setzero_pd());
2296 let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2297 let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2298 assert_eq_m512d(r, e);
2299 }
2300
2301 #[simd_test(enable = "avx512f")]
2302 unsafe fn test_mm512_mask3_fmaddsub_pd() {
2303 let a = _mm512_set1_pd(1.);
2304 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2305 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2306 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2307 assert_eq_m512d(r, c);
2308 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2309 let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2310 assert_eq_m512d(r, e);
2311 }
2312
2313 #[simd_test(enable = "avx512f,avx512vl")]
2314 unsafe fn test_mm256_mask_fmaddsub_pd() {
2315 let a = _mm256_set1_pd(1.);
2316 let b = _mm256_set_pd(0., 1., 2., 3.);
2317 let c = _mm256_set1_pd(1.);
2318 let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2319 assert_eq_m256d(r, a);
2320 let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2321 let e = _mm256_set_pd(1., 0., 3., 2.);
2322 assert_eq_m256d(r, e);
2323 }
2324
2325 #[simd_test(enable = "avx512f,avx512vl")]
2326 unsafe fn test_mm256_maskz_fmaddsub_pd() {
2327 let a = _mm256_set1_pd(1.);
2328 let b = _mm256_set_pd(0., 1., 2., 3.);
2329 let c = _mm256_set1_pd(1.);
2330 let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2331 assert_eq_m256d(r, _mm256_setzero_pd());
2332 let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2333 let e = _mm256_set_pd(1., 0., 3., 2.);
2334 assert_eq_m256d(r, e);
2335 }
2336
2337 #[simd_test(enable = "avx512f,avx512vl")]
2338 unsafe fn test_mm256_mask3_fmaddsub_pd() {
2339 let a = _mm256_set1_pd(1.);
2340 let b = _mm256_set_pd(0., 1., 2., 3.);
2341 let c = _mm256_set1_pd(1.);
2342 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2343 assert_eq_m256d(r, c);
2344 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2345 let e = _mm256_set_pd(1., 0., 3., 2.);
2346 assert_eq_m256d(r, e);
2347 }
2348
2349 #[simd_test(enable = "avx512f,avx512vl")]
2350 unsafe fn test_mm_mask_fmaddsub_pd() {
2351 let a = _mm_set1_pd(1.);
2352 let b = _mm_set_pd(0., 1.);
2353 let c = _mm_set1_pd(1.);
2354 let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2355 assert_eq_m128d(r, a);
2356 let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2357 let e = _mm_set_pd(1., 0.);
2358 assert_eq_m128d(r, e);
2359 }
2360
2361 #[simd_test(enable = "avx512f,avx512vl")]
2362 unsafe fn test_mm_maskz_fmaddsub_pd() {
2363 let a = _mm_set1_pd(1.);
2364 let b = _mm_set_pd(0., 1.);
2365 let c = _mm_set1_pd(1.);
2366 let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2367 assert_eq_m128d(r, _mm_setzero_pd());
2368 let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2369 let e = _mm_set_pd(1., 0.);
2370 assert_eq_m128d(r, e);
2371 }
2372
2373 #[simd_test(enable = "avx512f,avx512vl")]
2374 unsafe fn test_mm_mask3_fmaddsub_pd() {
2375 let a = _mm_set1_pd(1.);
2376 let b = _mm_set_pd(0., 1.);
2377 let c = _mm_set1_pd(1.);
2378 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2379 assert_eq_m128d(r, c);
2380 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2381 let e = _mm_set_pd(1., 0.);
2382 assert_eq_m128d(r, e);
2383 }
2384
2385 #[simd_test(enable = "avx512f")]
2386 unsafe fn test_mm512_fmsubadd_pd() {
2387 let a = _mm512_set1_pd(1.);
2388 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2389 let c = _mm512_set1_pd(1.);
2390 let r = _mm512_fmsubadd_pd(a, b, c);
2391 let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2392 assert_eq_m512d(r, e);
2393 }
2394
2395 #[simd_test(enable = "avx512f")]
2396 unsafe fn test_mm512_mask_fmsubadd_pd() {
2397 let a = _mm512_set1_pd(1.);
2398 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2399 let c = _mm512_set1_pd(1.);
2400 let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2401 assert_eq_m512d(r, a);
2402 let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2403 let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2404 assert_eq_m512d(r, e);
2405 }
2406
2407 #[simd_test(enable = "avx512f")]
2408 unsafe fn test_mm512_maskz_fmsubadd_pd() {
2409 let a = _mm512_set1_pd(1.);
2410 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2411 let c = _mm512_set1_pd(1.);
2412 let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2413 assert_eq_m512d(r, _mm512_setzero_pd());
2414 let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2415 let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2416 assert_eq_m512d(r, e);
2417 }
2418
2419 #[simd_test(enable = "avx512f")]
2420 unsafe fn test_mm512_mask3_fmsubadd_pd() {
2421 let a = _mm512_set1_pd(1.);
2422 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2423 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2424 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2425 assert_eq_m512d(r, c);
2426 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2427 let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2428 assert_eq_m512d(r, e);
2429 }
2430
2431 #[simd_test(enable = "avx512f,avx512vl")]
2432 unsafe fn test_mm256_mask_fmsubadd_pd() {
2433 let a = _mm256_set1_pd(1.);
2434 let b = _mm256_set_pd(0., 1., 2., 3.);
2435 let c = _mm256_set1_pd(1.);
2436 let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2437 assert_eq_m256d(r, a);
2438 let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2439 let e = _mm256_set_pd(-1., 2., 1., 4.);
2440 assert_eq_m256d(r, e);
2441 }
2442
2443 #[simd_test(enable = "avx512f,avx512vl")]
2444 unsafe fn test_mm256_maskz_fmsubadd_pd() {
2445 let a = _mm256_set1_pd(1.);
2446 let b = _mm256_set_pd(0., 1., 2., 3.);
2447 let c = _mm256_set1_pd(1.);
2448 let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2449 assert_eq_m256d(r, _mm256_setzero_pd());
2450 let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2451 let e = _mm256_set_pd(-1., 2., 1., 4.);
2452 assert_eq_m256d(r, e);
2453 }
2454
2455 #[simd_test(enable = "avx512f,avx512vl")]
2456 unsafe fn test_mm256_mask3_fmsubadd_pd() {
2457 let a = _mm256_set1_pd(1.);
2458 let b = _mm256_set_pd(0., 1., 2., 3.);
2459 let c = _mm256_set1_pd(1.);
2460 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2461 assert_eq_m256d(r, c);
2462 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2463 let e = _mm256_set_pd(-1., 2., 1., 4.);
2464 assert_eq_m256d(r, e);
2465 }
2466
2467 #[simd_test(enable = "avx512f,avx512vl")]
2468 unsafe fn test_mm_mask_fmsubadd_pd() {
2469 let a = _mm_set1_pd(1.);
2470 let b = _mm_set_pd(0., 1.);
2471 let c = _mm_set1_pd(1.);
2472 let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2473 assert_eq_m128d(r, a);
2474 let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2475 let e = _mm_set_pd(-1., 2.);
2476 assert_eq_m128d(r, e);
2477 }
2478
2479 #[simd_test(enable = "avx512f,avx512vl")]
2480 unsafe fn test_mm_maskz_fmsubadd_pd() {
2481 let a = _mm_set1_pd(1.);
2482 let b = _mm_set_pd(0., 1.);
2483 let c = _mm_set1_pd(1.);
2484 let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2485 assert_eq_m128d(r, _mm_setzero_pd());
2486 let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2487 let e = _mm_set_pd(-1., 2.);
2488 assert_eq_m128d(r, e);
2489 }
2490
2491 #[simd_test(enable = "avx512f,avx512vl")]
2492 unsafe fn test_mm_mask3_fmsubadd_pd() {
2493 let a = _mm_set1_pd(1.);
2494 let b = _mm_set_pd(0., 1.);
2495 let c = _mm_set1_pd(1.);
2496 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2497 assert_eq_m128d(r, c);
2498 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2499 let e = _mm_set_pd(-1., 2.);
2500 assert_eq_m128d(r, e);
2501 }
2502
2503 #[simd_test(enable = "avx512f")]
2504 unsafe fn test_mm512_fnmadd_pd() {
2505 let a = _mm512_set1_pd(1.);
2506 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2507 let c = _mm512_set1_pd(1.);
2508 let r = _mm512_fnmadd_pd(a, b, c);
2509 let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2510 assert_eq_m512d(r, e);
2511 }
2512
2513 #[simd_test(enable = "avx512f")]
2514 unsafe fn test_mm512_mask_fnmadd_pd() {
2515 let a = _mm512_set1_pd(1.);
2516 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2517 let c = _mm512_set1_pd(1.);
2518 let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2519 assert_eq_m512d(r, a);
2520 let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2521 let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2522 assert_eq_m512d(r, e);
2523 }
2524
2525 #[simd_test(enable = "avx512f")]
2526 unsafe fn test_mm512_maskz_fnmadd_pd() {
2527 let a = _mm512_set1_pd(1.);
2528 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2529 let c = _mm512_set1_pd(1.);
2530 let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2531 assert_eq_m512d(r, _mm512_setzero_pd());
2532 let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2533 let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2534 assert_eq_m512d(r, e);
2535 }
2536
2537 #[simd_test(enable = "avx512f")]
2538 unsafe fn test_mm512_mask3_fnmadd_pd() {
2539 let a = _mm512_set1_pd(1.);
2540 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2541 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2542 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2543 assert_eq_m512d(r, c);
2544 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2545 let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2546 assert_eq_m512d(r, e);
2547 }
2548
2549 #[simd_test(enable = "avx512f,avx512vl")]
2550 unsafe fn test_mm256_mask_fnmadd_pd() {
2551 let a = _mm256_set1_pd(1.);
2552 let b = _mm256_set_pd(0., 1., 2., 3.);
2553 let c = _mm256_set1_pd(1.);
2554 let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2555 assert_eq_m256d(r, a);
2556 let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2557 let e = _mm256_set_pd(1., 0., -1., -2.);
2558 assert_eq_m256d(r, e);
2559 }
2560
2561 #[simd_test(enable = "avx512f,avx512vl")]
2562 unsafe fn test_mm256_maskz_fnmadd_pd() {
2563 let a = _mm256_set1_pd(1.);
2564 let b = _mm256_set_pd(0., 1., 2., 3.);
2565 let c = _mm256_set1_pd(1.);
2566 let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2567 assert_eq_m256d(r, _mm256_setzero_pd());
2568 let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2569 let e = _mm256_set_pd(1., 0., -1., -2.);
2570 assert_eq_m256d(r, e);
2571 }
2572
2573 #[simd_test(enable = "avx512f,avx512vl")]
2574 unsafe fn test_mm256_mask3_fnmadd_pd() {
2575 let a = _mm256_set1_pd(1.);
2576 let b = _mm256_set_pd(0., 1., 2., 3.);
2577 let c = _mm256_set1_pd(1.);
2578 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2579 assert_eq_m256d(r, c);
2580 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2581 let e = _mm256_set_pd(1., 0., -1., -2.);
2582 assert_eq_m256d(r, e);
2583 }
2584
2585 #[simd_test(enable = "avx512f,avx512vl")]
2586 unsafe fn test_mm_mask_fnmadd_pd() {
2587 let a = _mm_set1_pd(1.);
2588 let b = _mm_set_pd(0., 1.);
2589 let c = _mm_set1_pd(1.);
2590 let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2591 assert_eq_m128d(r, a);
2592 let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2593 let e = _mm_set_pd(1., 0.);
2594 assert_eq_m128d(r, e);
2595 }
2596
2597 #[simd_test(enable = "avx512f,avx512vl")]
2598 unsafe fn test_mm_maskz_fnmadd_pd() {
2599 let a = _mm_set1_pd(1.);
2600 let b = _mm_set_pd(0., 1.);
2601 let c = _mm_set1_pd(1.);
2602 let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2603 assert_eq_m128d(r, _mm_setzero_pd());
2604 let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2605 let e = _mm_set_pd(1., 0.);
2606 assert_eq_m128d(r, e);
2607 }
2608
2609 #[simd_test(enable = "avx512f,avx512vl")]
2610 unsafe fn test_mm_mask3_fnmadd_pd() {
2611 let a = _mm_set1_pd(1.);
2612 let b = _mm_set_pd(0., 1.);
2613 let c = _mm_set1_pd(1.);
2614 let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2615 assert_eq_m128d(r, c);
2616 let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2617 let e = _mm_set_pd(1., 0.);
2618 assert_eq_m128d(r, e);
2619 }
2620
2621 #[simd_test(enable = "avx512f")]
2622 unsafe fn test_mm512_fnmsub_pd() {
2623 let a = _mm512_set1_pd(1.);
2624 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2625 let c = _mm512_set1_pd(1.);
2626 let r = _mm512_fnmsub_pd(a, b, c);
2627 let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2628 assert_eq_m512d(r, e);
2629 }
2630
2631 #[simd_test(enable = "avx512f")]
2632 unsafe fn test_mm512_mask_fnmsub_pd() {
2633 let a = _mm512_set1_pd(1.);
2634 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2635 let c = _mm512_set1_pd(1.);
2636 let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2637 assert_eq_m512d(r, a);
2638 let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2639 let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2640 assert_eq_m512d(r, e);
2641 }
2642
2643 #[simd_test(enable = "avx512f")]
2644 unsafe fn test_mm512_maskz_fnmsub_pd() {
2645 let a = _mm512_set1_pd(1.);
2646 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2647 let c = _mm512_set1_pd(1.);
2648 let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2649 assert_eq_m512d(r, _mm512_setzero_pd());
2650 let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2651 let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2652 assert_eq_m512d(r, e);
2653 }
2654
2655 #[simd_test(enable = "avx512f")]
2656 unsafe fn test_mm512_mask3_fnmsub_pd() {
2657 let a = _mm512_set1_pd(1.);
2658 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2659 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2660 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2661 assert_eq_m512d(r, c);
2662 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2663 let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2664 assert_eq_m512d(r, e);
2665 }
2666
2667 #[simd_test(enable = "avx512f,avx512vl")]
2668 unsafe fn test_mm256_mask_fnmsub_pd() {
2669 let a = _mm256_set1_pd(1.);
2670 let b = _mm256_set_pd(0., 1., 2., 3.);
2671 let c = _mm256_set1_pd(1.);
2672 let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2673 assert_eq_m256d(r, a);
2674 let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2675 let e = _mm256_set_pd(-1., -2., -3., -4.);
2676 assert_eq_m256d(r, e);
2677 }
2678
2679 #[simd_test(enable = "avx512f,avx512vl")]
2680 unsafe fn test_mm256_maskz_fnmsub_pd() {
2681 let a = _mm256_set1_pd(1.);
2682 let b = _mm256_set_pd(0., 1., 2., 3.);
2683 let c = _mm256_set1_pd(1.);
2684 let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2685 assert_eq_m256d(r, _mm256_setzero_pd());
2686 let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2687 let e = _mm256_set_pd(-1., -2., -3., -4.);
2688 assert_eq_m256d(r, e);
2689 }
2690
2691 #[simd_test(enable = "avx512f,avx512vl")]
2692 unsafe fn test_mm256_mask3_fnmsub_pd() {
2693 let a = _mm256_set1_pd(1.);
2694 let b = _mm256_set_pd(0., 1., 2., 3.);
2695 let c = _mm256_set1_pd(1.);
2696 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2697 assert_eq_m256d(r, c);
2698 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2699 let e = _mm256_set_pd(-1., -2., -3., -4.);
2700 assert_eq_m256d(r, e);
2701 }
2702
2703 #[simd_test(enable = "avx512f,avx512vl")]
2704 unsafe fn test_mm_mask_fnmsub_pd() {
2705 let a = _mm_set1_pd(1.);
2706 let b = _mm_set_pd(0., 1.);
2707 let c = _mm_set1_pd(1.);
2708 let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2709 assert_eq_m128d(r, a);
2710 let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2711 let e = _mm_set_pd(-1., -2.);
2712 assert_eq_m128d(r, e);
2713 }
2714
2715 #[simd_test(enable = "avx512f,avx512vl")]
2716 unsafe fn test_mm_maskz_fnmsub_pd() {
2717 let a = _mm_set1_pd(1.);
2718 let b = _mm_set_pd(0., 1.);
2719 let c = _mm_set1_pd(1.);
2720 let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2721 assert_eq_m128d(r, _mm_setzero_pd());
2722 let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2723 let e = _mm_set_pd(-1., -2.);
2724 assert_eq_m128d(r, e);
2725 }
2726
2727 #[simd_test(enable = "avx512f,avx512vl")]
2728 unsafe fn test_mm_mask3_fnmsub_pd() {
2729 let a = _mm_set1_pd(1.);
2730 let b = _mm_set_pd(0., 1.);
2731 let c = _mm_set1_pd(1.);
2732 let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2733 assert_eq_m128d(r, c);
2734 let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2735 let e = _mm_set_pd(-1., -2.);
2736 assert_eq_m128d(r, e);
2737 }
2738
2739 #[simd_test(enable = "avx512f")]
2740 unsafe fn test_mm512_rcp14_pd() {
2741 let a = _mm512_set1_pd(3.);
2742 let r = _mm512_rcp14_pd(a);
2743 let e = _mm512_set1_pd(0.3333320617675781);
2744 assert_eq_m512d(r, e);
2745 }
2746
2747 #[simd_test(enable = "avx512f")]
2748 unsafe fn test_mm512_mask_rcp14_pd() {
2749 let a = _mm512_set1_pd(3.);
2750 let r = _mm512_mask_rcp14_pd(a, 0, a);
2751 assert_eq_m512d(r, a);
2752 let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2753 #[rustfmt::skip]
2754 let e = _mm512_setr_pd(
2755 3., 3., 3., 3.,
2756 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2757 );
2758 assert_eq_m512d(r, e);
2759 }
2760
2761 #[simd_test(enable = "avx512f")]
2762 unsafe fn test_mm512_maskz_rcp14_pd() {
2763 let a = _mm512_set1_pd(3.);
2764 let r = _mm512_maskz_rcp14_pd(0, a);
2765 assert_eq_m512d(r, _mm512_setzero_pd());
2766 let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2767 #[rustfmt::skip]
2768 let e = _mm512_setr_pd(
2769 0., 0., 0., 0.,
2770 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2771 );
2772 assert_eq_m512d(r, e);
2773 }
2774
2775 #[simd_test(enable = "avx512f,avx512vl")]
2776 unsafe fn test_mm256_rcp14_pd() {
2777 let a = _mm256_set1_pd(3.);
2778 let r = _mm256_rcp14_pd(a);
2779 let e = _mm256_set1_pd(0.3333320617675781);
2780 assert_eq_m256d(r, e);
2781 }
2782
2783 #[simd_test(enable = "avx512f,avx512vl")]
2784 unsafe fn test_mm256_mask_rcp14_pd() {
2785 let a = _mm256_set1_pd(3.);
2786 let r = _mm256_mask_rcp14_pd(a, 0, a);
2787 assert_eq_m256d(r, a);
2788 let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2789 let e = _mm256_set1_pd(0.3333320617675781);
2790 assert_eq_m256d(r, e);
2791 }
2792
2793 #[simd_test(enable = "avx512f,avx512vl")]
2794 unsafe fn test_mm256_maskz_rcp14_pd() {
2795 let a = _mm256_set1_pd(3.);
2796 let r = _mm256_maskz_rcp14_pd(0, a);
2797 assert_eq_m256d(r, _mm256_setzero_pd());
2798 let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2799 let e = _mm256_set1_pd(0.3333320617675781);
2800 assert_eq_m256d(r, e);
2801 }
2802
2803 #[simd_test(enable = "avx512f,avx512vl")]
2804 unsafe fn test_mm_rcp14_pd() {
2805 let a = _mm_set1_pd(3.);
2806 let r = _mm_rcp14_pd(a);
2807 let e = _mm_set1_pd(0.3333320617675781);
2808 assert_eq_m128d(r, e);
2809 }
2810
2811 #[simd_test(enable = "avx512f,avx512vl")]
2812 unsafe fn test_mm_mask_rcp14_pd() {
2813 let a = _mm_set1_pd(3.);
2814 let r = _mm_mask_rcp14_pd(a, 0, a);
2815 assert_eq_m128d(r, a);
2816 let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2817 let e = _mm_set1_pd(0.3333320617675781);
2818 assert_eq_m128d(r, e);
2819 }
2820
2821 #[simd_test(enable = "avx512f,avx512vl")]
2822 unsafe fn test_mm_maskz_rcp14_pd() {
2823 let a = _mm_set1_pd(3.);
2824 let r = _mm_maskz_rcp14_pd(0, a);
2825 assert_eq_m128d(r, _mm_setzero_pd());
2826 let r = _mm_maskz_rcp14_pd(0b00000011, a);
2827 let e = _mm_set1_pd(0.3333320617675781);
2828 assert_eq_m128d(r, e);
2829 }
2830
2831 #[simd_test(enable = "avx512f")]
2832 unsafe fn test_mm512_rsqrt14_pd() {
2833 let a = _mm512_set1_pd(3.);
2834 let r = _mm512_rsqrt14_pd(a);
2835 let e = _mm512_set1_pd(0.5773391723632813);
2836 assert_eq_m512d(r, e);
2837 }
2838
2839 #[simd_test(enable = "avx512f")]
2840 unsafe fn test_mm512_mask_rsqrt14_pd() {
2841 let a = _mm512_set1_pd(3.);
2842 let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2843 assert_eq_m512d(r, a);
2844 let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2845 #[rustfmt::skip]
2846 let e = _mm512_setr_pd(
2847 3., 3., 3., 3.,
2848 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2849 );
2850 assert_eq_m512d(r, e);
2851 }
2852
2853 #[simd_test(enable = "avx512f")]
2854 unsafe fn test_mm512_maskz_rsqrt14_pd() {
2855 let a = _mm512_set1_pd(3.);
2856 let r = _mm512_maskz_rsqrt14_pd(0, a);
2857 assert_eq_m512d(r, _mm512_setzero_pd());
2858 let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2859 #[rustfmt::skip]
2860 let e = _mm512_setr_pd(
2861 0., 0., 0., 0.,
2862 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2863 );
2864 assert_eq_m512d(r, e);
2865 }
2866
2867 #[simd_test(enable = "avx512f,avx512vl")]
2868 unsafe fn test_mm256_rsqrt14_pd() {
2869 let a = _mm256_set1_pd(3.);
2870 let r = _mm256_rsqrt14_pd(a);
2871 let e = _mm256_set1_pd(0.5773391723632813);
2872 assert_eq_m256d(r, e);
2873 }
2874
2875 #[simd_test(enable = "avx512f,avx512vl")]
2876 unsafe fn test_mm256_mask_rsqrt14_pd() {
2877 let a = _mm256_set1_pd(3.);
2878 let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2879 assert_eq_m256d(r, a);
2880 let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2881 let e = _mm256_set1_pd(0.5773391723632813);
2882 assert_eq_m256d(r, e);
2883 }
2884
2885 #[simd_test(enable = "avx512f,avx512vl")]
2886 unsafe fn test_mm256_maskz_rsqrt14_pd() {
2887 let a = _mm256_set1_pd(3.);
2888 let r = _mm256_maskz_rsqrt14_pd(0, a);
2889 assert_eq_m256d(r, _mm256_setzero_pd());
2890 let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2891 let e = _mm256_set1_pd(0.5773391723632813);
2892 assert_eq_m256d(r, e);
2893 }
2894
2895 #[simd_test(enable = "avx512f,avx512vl")]
2896 unsafe fn test_mm_rsqrt14_pd() {
2897 let a = _mm_set1_pd(3.);
2898 let r = _mm_rsqrt14_pd(a);
2899 let e = _mm_set1_pd(0.5773391723632813);
2900 assert_eq_m128d(r, e);
2901 }
2902
2903 #[simd_test(enable = "avx512f,avx512vl")]
2904 unsafe fn test_mm_mask_rsqrt14_pd() {
2905 let a = _mm_set1_pd(3.);
2906 let r = _mm_mask_rsqrt14_pd(a, 0, a);
2907 assert_eq_m128d(r, a);
2908 let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2909 let e = _mm_set1_pd(0.5773391723632813);
2910 assert_eq_m128d(r, e);
2911 }
2912
2913 #[simd_test(enable = "avx512f,avx512vl")]
2914 unsafe fn test_mm_maskz_rsqrt14_pd() {
2915 let a = _mm_set1_pd(3.);
2916 let r = _mm_maskz_rsqrt14_pd(0, a);
2917 assert_eq_m128d(r, _mm_setzero_pd());
2918 let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2919 let e = _mm_set1_pd(0.5773391723632813);
2920 assert_eq_m128d(r, e);
2921 }
2922
2923 #[simd_test(enable = "avx512f")]
2924 unsafe fn test_mm512_getexp_pd() {
2925 let a = _mm512_set1_pd(3.);
2926 let r = _mm512_getexp_pd(a);
2927 let e = _mm512_set1_pd(1.);
2928 assert_eq_m512d(r, e);
2929 }
2930
2931 #[simd_test(enable = "avx512f")]
2932 unsafe fn test_mm512_mask_getexp_pd() {
2933 let a = _mm512_set1_pd(3.);
2934 let r = _mm512_mask_getexp_pd(a, 0, a);
2935 assert_eq_m512d(r, a);
2936 let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2937 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2938 assert_eq_m512d(r, e);
2939 }
2940
2941 #[simd_test(enable = "avx512f")]
2942 unsafe fn test_mm512_maskz_getexp_pd() {
2943 let a = _mm512_set1_pd(3.);
2944 let r = _mm512_maskz_getexp_pd(0, a);
2945 assert_eq_m512d(r, _mm512_setzero_pd());
2946 let r = _mm512_maskz_getexp_pd(0b11110000, a);
2947 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2948 assert_eq_m512d(r, e);
2949 }
2950
2951 #[simd_test(enable = "avx512f,avx512vl")]
2952 unsafe fn test_mm256_getexp_pd() {
2953 let a = _mm256_set1_pd(3.);
2954 let r = _mm256_getexp_pd(a);
2955 let e = _mm256_set1_pd(1.);
2956 assert_eq_m256d(r, e);
2957 }
2958
2959 #[simd_test(enable = "avx512f,avx512vl")]
2960 unsafe fn test_mm256_mask_getexp_pd() {
2961 let a = _mm256_set1_pd(3.);
2962 let r = _mm256_mask_getexp_pd(a, 0, a);
2963 assert_eq_m256d(r, a);
2964 let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2965 let e = _mm256_set1_pd(1.);
2966 assert_eq_m256d(r, e);
2967 }
2968
2969 #[simd_test(enable = "avx512f,avx512vl")]
2970 unsafe fn test_mm256_maskz_getexp_pd() {
2971 let a = _mm256_set1_pd(3.);
2972 let r = _mm256_maskz_getexp_pd(0, a);
2973 assert_eq_m256d(r, _mm256_setzero_pd());
2974 let r = _mm256_maskz_getexp_pd(0b00001111, a);
2975 let e = _mm256_set1_pd(1.);
2976 assert_eq_m256d(r, e);
2977 }
2978
2979 #[simd_test(enable = "avx512f,avx512vl")]
2980 unsafe fn test_mm_getexp_pd() {
2981 let a = _mm_set1_pd(3.);
2982 let r = _mm_getexp_pd(a);
2983 let e = _mm_set1_pd(1.);
2984 assert_eq_m128d(r, e);
2985 }
2986
2987 #[simd_test(enable = "avx512f,avx512vl")]
2988 unsafe fn test_mm_mask_getexp_pd() {
2989 let a = _mm_set1_pd(3.);
2990 let r = _mm_mask_getexp_pd(a, 0, a);
2991 assert_eq_m128d(r, a);
2992 let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2993 let e = _mm_set1_pd(1.);
2994 assert_eq_m128d(r, e);
2995 }
2996
2997 #[simd_test(enable = "avx512f,avx512vl")]
2998 unsafe fn test_mm_maskz_getexp_pd() {
2999 let a = _mm_set1_pd(3.);
3000 let r = _mm_maskz_getexp_pd(0, a);
3001 assert_eq_m128d(r, _mm_setzero_pd());
3002 let r = _mm_maskz_getexp_pd(0b00000011, a);
3003 let e = _mm_set1_pd(1.);
3004 assert_eq_m128d(r, e);
3005 }
3006
3007 #[simd_test(enable = "avx512f")]
3008 unsafe fn test_mm512_roundscale_pd() {
3009 let a = _mm512_set1_pd(1.1);
3010 let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
3011 let e = _mm512_set1_pd(1.0);
3012 assert_eq_m512d(r, e);
3013 }
3014
3015 #[simd_test(enable = "avx512f")]
3016 unsafe fn test_mm512_mask_roundscale_pd() {
3017 let a = _mm512_set1_pd(1.1);
3018 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3019 let e = _mm512_set1_pd(1.1);
3020 assert_eq_m512d(r, e);
3021 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
3022 let e = _mm512_set1_pd(1.0);
3023 assert_eq_m512d(r, e);
3024 }
3025
3026 #[simd_test(enable = "avx512f")]
3027 unsafe fn test_mm512_maskz_roundscale_pd() {
3028 let a = _mm512_set1_pd(1.1);
3029 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3030 assert_eq_m512d(r, _mm512_setzero_pd());
3031 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
3032 let e = _mm512_set1_pd(1.0);
3033 assert_eq_m512d(r, e);
3034 }
3035
3036 #[simd_test(enable = "avx512f,avx512vl")]
3037 unsafe fn test_mm256_roundscale_pd() {
3038 let a = _mm256_set1_pd(1.1);
3039 let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
3040 let e = _mm256_set1_pd(1.0);
3041 assert_eq_m256d(r, e);
3042 }
3043
3044 #[simd_test(enable = "avx512f,avx512vl")]
3045 unsafe fn test_mm256_mask_roundscale_pd() {
3046 let a = _mm256_set1_pd(1.1);
3047 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3048 assert_eq_m256d(r, a);
3049 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
3050 let e = _mm256_set1_pd(1.0);
3051 assert_eq_m256d(r, e);
3052 }
3053
3054 #[simd_test(enable = "avx512f,avx512vl")]
3055 unsafe fn test_mm256_maskz_roundscale_pd() {
3056 let a = _mm256_set1_pd(1.1);
3057 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3058 assert_eq_m256d(r, _mm256_setzero_pd());
3059 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
3060 let e = _mm256_set1_pd(1.0);
3061 assert_eq_m256d(r, e);
3062 }
3063
3064 #[simd_test(enable = "avx512f,avx512vl")]
3065 unsafe fn test_mm_roundscale_pd() {
3066 let a = _mm_set1_pd(1.1);
3067 let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
3068 let e = _mm_set1_pd(1.0);
3069 assert_eq_m128d(r, e);
3070 }
3071
3072 #[simd_test(enable = "avx512f,avx512vl")]
3073 unsafe fn test_mm_mask_roundscale_pd() {
3074 let a = _mm_set1_pd(1.1);
3075 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3076 let e = _mm_set1_pd(1.1);
3077 assert_eq_m128d(r, e);
3078 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
3079 let e = _mm_set1_pd(1.0);
3080 assert_eq_m128d(r, e);
3081 }
3082
3083 #[simd_test(enable = "avx512f,avx512vl")]
3084 unsafe fn test_mm_maskz_roundscale_pd() {
3085 let a = _mm_set1_pd(1.1);
3086 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3087 assert_eq_m128d(r, _mm_setzero_pd());
3088 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
3089 let e = _mm_set1_pd(1.0);
3090 assert_eq_m128d(r, e);
3091 }
3092
3093 #[simd_test(enable = "avx512f")]
3094 unsafe fn test_mm512_scalef_pd() {
3095 let a = _mm512_set1_pd(1.);
3096 let b = _mm512_set1_pd(3.);
3097 let r = _mm512_scalef_pd(a, b);
3098 let e = _mm512_set1_pd(8.);
3099 assert_eq_m512d(r, e);
3100 }
3101
3102 #[simd_test(enable = "avx512f")]
3103 unsafe fn test_mm512_mask_scalef_pd() {
3104 let a = _mm512_set1_pd(1.);
3105 let b = _mm512_set1_pd(3.);
3106 let r = _mm512_mask_scalef_pd(a, 0, a, b);
3107 assert_eq_m512d(r, a);
3108 let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
3109 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
3110 assert_eq_m512d(r, e);
3111 }
3112
3113 #[simd_test(enable = "avx512f")]
3114 unsafe fn test_mm512_maskz_scalef_pd() {
3115 let a = _mm512_set1_pd(1.);
3116 let b = _mm512_set1_pd(3.);
3117 let r = _mm512_maskz_scalef_pd(0, a, b);
3118 assert_eq_m512d(r, _mm512_setzero_pd());
3119 let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
3120 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
3121 assert_eq_m512d(r, e);
3122 }
3123
3124 #[simd_test(enable = "avx512f,avx512vl")]
3125 unsafe fn test_mm256_scalef_pd() {
3126 let a = _mm256_set1_pd(1.);
3127 let b = _mm256_set1_pd(3.);
3128 let r = _mm256_scalef_pd(a, b);
3129 let e = _mm256_set1_pd(8.);
3130 assert_eq_m256d(r, e);
3131 }
3132
3133 #[simd_test(enable = "avx512f,avx512vl")]
3134 unsafe fn test_mm256_mask_scalef_pd() {
3135 let a = _mm256_set1_pd(1.);
3136 let b = _mm256_set1_pd(3.);
3137 let r = _mm256_mask_scalef_pd(a, 0, a, b);
3138 assert_eq_m256d(r, a);
3139 let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
3140 let e = _mm256_set1_pd(8.);
3141 assert_eq_m256d(r, e);
3142 }
3143
3144 #[simd_test(enable = "avx512f,avx512vl")]
3145 unsafe fn test_mm256_maskz_scalef_pd() {
3146 let a = _mm256_set1_pd(1.);
3147 let b = _mm256_set1_pd(3.);
3148 let r = _mm256_maskz_scalef_pd(0, a, b);
3149 assert_eq_m256d(r, _mm256_setzero_pd());
3150 let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3151 let e = _mm256_set1_pd(8.);
3152 assert_eq_m256d(r, e);
3153 }
3154
3155 #[simd_test(enable = "avx512f,avx512vl")]
3156 unsafe fn test_mm_scalef_pd() {
3157 let a = _mm_set1_pd(1.);
3158 let b = _mm_set1_pd(3.);
3159 let r = _mm_scalef_pd(a, b);
3160 let e = _mm_set1_pd(8.);
3161 assert_eq_m128d(r, e);
3162 }
3163
3164 #[simd_test(enable = "avx512f,avx512vl")]
3165 unsafe fn test_mm_mask_scalef_pd() {
3166 let a = _mm_set1_pd(1.);
3167 let b = _mm_set1_pd(3.);
3168 let r = _mm_mask_scalef_pd(a, 0, a, b);
3169 assert_eq_m128d(r, a);
3170 let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3171 let e = _mm_set1_pd(8.);
3172 assert_eq_m128d(r, e);
3173 }
3174
3175 #[simd_test(enable = "avx512f,avx512vl")]
3176 unsafe fn test_mm_maskz_scalef_pd() {
3177 let a = _mm_set1_pd(1.);
3178 let b = _mm_set1_pd(3.);
3179 let r = _mm_maskz_scalef_pd(0, a, b);
3180 assert_eq_m128d(r, _mm_setzero_pd());
3181 let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3182 let e = _mm_set1_pd(8.);
3183 assert_eq_m128d(r, e);
3184 }
3185
3186 #[simd_test(enable = "avx512f")]
3187 unsafe fn test_mm512_fixupimm_pd() {
3188 let a = _mm512_set1_pd(f64::NAN);
3189 let b = _mm512_set1_pd(f64::MAX);
3190 let c = _mm512_set1_epi64(i32::MAX as i64);
3191 let r = _mm512_fixupimm_pd::<5>(a, b, c);
3192 let e = _mm512_set1_pd(0.0);
3193 assert_eq_m512d(r, e);
3194 }
3195
3196 #[simd_test(enable = "avx512f")]
3197 unsafe fn test_mm512_mask_fixupimm_pd() {
3198 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3199 let b = _mm512_set1_pd(f64::MAX);
3200 let c = _mm512_set1_epi64(i32::MAX as i64);
3201 let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3202 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3203 assert_eq_m512d(r, e);
3204 }
3205
3206 #[simd_test(enable = "avx512f")]
3207 unsafe fn test_mm512_maskz_fixupimm_pd() {
3208 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3209 let b = _mm512_set1_pd(f64::MAX);
3210 let c = _mm512_set1_epi64(i32::MAX as i64);
3211 let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3212 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3213 assert_eq_m512d(r, e);
3214 }
3215
3216 #[simd_test(enable = "avx512f,avx512vl")]
3217 unsafe fn test_mm256_fixupimm_pd() {
3218 let a = _mm256_set1_pd(f64::NAN);
3219 let b = _mm256_set1_pd(f64::MAX);
3220 let c = _mm256_set1_epi64x(i32::MAX as i64);
3221 let r = _mm256_fixupimm_pd::<5>(a, b, c);
3222 let e = _mm256_set1_pd(0.0);
3223 assert_eq_m256d(r, e);
3224 }
3225
3226 #[simd_test(enable = "avx512f,avx512vl")]
3227 unsafe fn test_mm256_mask_fixupimm_pd() {
3228 let a = _mm256_set1_pd(f64::NAN);
3229 let b = _mm256_set1_pd(f64::MAX);
3230 let c = _mm256_set1_epi64x(i32::MAX as i64);
3231 let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3232 let e = _mm256_set1_pd(0.0);
3233 assert_eq_m256d(r, e);
3234 }
3235
3236 #[simd_test(enable = "avx512f,avx512vl")]
3237 unsafe fn test_mm256_maskz_fixupimm_pd() {
3238 let a = _mm256_set1_pd(f64::NAN);
3239 let b = _mm256_set1_pd(f64::MAX);
3240 let c = _mm256_set1_epi64x(i32::MAX as i64);
3241 let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3242 let e = _mm256_set1_pd(0.0);
3243 assert_eq_m256d(r, e);
3244 }
3245
3246 #[simd_test(enable = "avx512f,avx512vl")]
3247 unsafe fn test_mm_fixupimm_pd() {
3248 let a = _mm_set1_pd(f64::NAN);
3249 let b = _mm_set1_pd(f64::MAX);
3250 let c = _mm_set1_epi64x(i32::MAX as i64);
3251 let r = _mm_fixupimm_pd::<5>(a, b, c);
3252 let e = _mm_set1_pd(0.0);
3253 assert_eq_m128d(r, e);
3254 }
3255
3256 #[simd_test(enable = "avx512f,avx512vl")]
3257 unsafe fn test_mm_mask_fixupimm_pd() {
3258 let a = _mm_set1_pd(f64::NAN);
3259 let b = _mm_set1_pd(f64::MAX);
3260 let c = _mm_set1_epi64x(i32::MAX as i64);
3261 let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3262 let e = _mm_set1_pd(0.0);
3263 assert_eq_m128d(r, e);
3264 }
3265
3266 #[simd_test(enable = "avx512f,avx512vl")]
3267 unsafe fn test_mm_maskz_fixupimm_pd() {
3268 let a = _mm_set1_pd(f64::NAN);
3269 let b = _mm_set1_pd(f64::MAX);
3270 let c = _mm_set1_epi64x(i32::MAX as i64);
3271 let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3272 let e = _mm_set1_pd(0.0);
3273 assert_eq_m128d(r, e);
3274 }
3275
3276 #[simd_test(enable = "avx512f")]
3277 unsafe fn test_mm512_ternarylogic_epi64() {
3278 let a = _mm512_set1_epi64(1 << 2);
3279 let b = _mm512_set1_epi64(1 << 1);
3280 let c = _mm512_set1_epi64(1 << 0);
3281 let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3282 let e = _mm512_set1_epi64(0);
3283 assert_eq_m512i(r, e);
3284 }
3285
3286 #[simd_test(enable = "avx512f")]
3287 unsafe fn test_mm512_mask_ternarylogic_epi64() {
3288 let src = _mm512_set1_epi64(1 << 2);
3289 let a = _mm512_set1_epi64(1 << 1);
3290 let b = _mm512_set1_epi64(1 << 0);
3291 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3292 assert_eq_m512i(r, src);
3293 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3294 let e = _mm512_set1_epi64(0);
3295 assert_eq_m512i(r, e);
3296 }
3297
3298 #[simd_test(enable = "avx512f")]
3299 unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3300 let a = _mm512_set1_epi64(1 << 2);
3301 let b = _mm512_set1_epi64(1 << 1);
3302 let c = _mm512_set1_epi64(1 << 0);
3303 let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3304 assert_eq_m512i(r, _mm512_setzero_si512());
3305 let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3306 let e = _mm512_set1_epi64(0);
3307 assert_eq_m512i(r, e);
3308 }
3309
3310 #[simd_test(enable = "avx512f,avx512vl")]
3311 unsafe fn test_mm256_ternarylogic_epi64() {
3312 let a = _mm256_set1_epi64x(1 << 2);
3313 let b = _mm256_set1_epi64x(1 << 1);
3314 let c = _mm256_set1_epi64x(1 << 0);
3315 let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3316 let e = _mm256_set1_epi64x(0);
3317 assert_eq_m256i(r, e);
3318 }
3319
3320 #[simd_test(enable = "avx512f,avx512vl")]
3321 unsafe fn test_mm256_mask_ternarylogic_epi64() {
3322 let src = _mm256_set1_epi64x(1 << 2);
3323 let a = _mm256_set1_epi64x(1 << 1);
3324 let b = _mm256_set1_epi64x(1 << 0);
3325 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3326 assert_eq_m256i(r, src);
3327 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3328 let e = _mm256_set1_epi64x(0);
3329 assert_eq_m256i(r, e);
3330 }
3331
3332 #[simd_test(enable = "avx512f,avx512vl")]
3333 unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3334 let a = _mm256_set1_epi64x(1 << 2);
3335 let b = _mm256_set1_epi64x(1 << 1);
3336 let c = _mm256_set1_epi64x(1 << 0);
3337 let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3338 assert_eq_m256i(r, _mm256_setzero_si256());
3339 let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3340 let e = _mm256_set1_epi64x(0);
3341 assert_eq_m256i(r, e);
3342 }
3343
3344 #[simd_test(enable = "avx512f,avx512vl")]
3345 unsafe fn test_mm_ternarylogic_epi64() {
3346 let a = _mm_set1_epi64x(1 << 2);
3347 let b = _mm_set1_epi64x(1 << 1);
3348 let c = _mm_set1_epi64x(1 << 0);
3349 let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3350 let e = _mm_set1_epi64x(0);
3351 assert_eq_m128i(r, e);
3352 }
3353
3354 #[simd_test(enable = "avx512f,avx512vl")]
3355 unsafe fn test_mm_mask_ternarylogic_epi64() {
3356 let src = _mm_set1_epi64x(1 << 2);
3357 let a = _mm_set1_epi64x(1 << 1);
3358 let b = _mm_set1_epi64x(1 << 0);
3359 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3360 assert_eq_m128i(r, src);
3361 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3362 let e = _mm_set1_epi64x(0);
3363 assert_eq_m128i(r, e);
3364 }
3365
3366 #[simd_test(enable = "avx512f,avx512vl")]
3367 unsafe fn test_mm_maskz_ternarylogic_epi64() {
3368 let a = _mm_set1_epi64x(1 << 2);
3369 let b = _mm_set1_epi64x(1 << 1);
3370 let c = _mm_set1_epi64x(1 << 0);
3371 let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3372 assert_eq_m128i(r, _mm_setzero_si128());
3373 let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3374 let e = _mm_set1_epi64x(0);
3375 assert_eq_m128i(r, e);
3376 }
3377
3378 #[simd_test(enable = "avx512f")]
3379 unsafe fn test_mm512_getmant_pd() {
3380 let a = _mm512_set1_pd(10.);
3381 let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3382 let e = _mm512_set1_pd(1.25);
3383 assert_eq_m512d(r, e);
3384 }
3385
3386 #[simd_test(enable = "avx512f")]
3387 unsafe fn test_mm512_mask_getmant_pd() {
3388 let a = _mm512_set1_pd(10.);
3389 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3390 assert_eq_m512d(r, a);
3391 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3392 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3393 assert_eq_m512d(r, e);
3394 }
3395
3396 #[simd_test(enable = "avx512f")]
3397 unsafe fn test_mm512_maskz_getmant_pd() {
3398 let a = _mm512_set1_pd(10.);
3399 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3400 assert_eq_m512d(r, _mm512_setzero_pd());
3401 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3402 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3403 assert_eq_m512d(r, e);
3404 }
3405
3406 #[simd_test(enable = "avx512f,avx512vl")]
3407 unsafe fn test_mm256_getmant_pd() {
3408 let a = _mm256_set1_pd(10.);
3409 let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3410 let e = _mm256_set1_pd(1.25);
3411 assert_eq_m256d(r, e);
3412 }
3413
3414 #[simd_test(enable = "avx512f,avx512vl")]
3415 unsafe fn test_mm256_mask_getmant_pd() {
3416 let a = _mm256_set1_pd(10.);
3417 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3418 assert_eq_m256d(r, a);
3419 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3420 let e = _mm256_set1_pd(1.25);
3421 assert_eq_m256d(r, e);
3422 }
3423
3424 #[simd_test(enable = "avx512f,avx512vl")]
3425 unsafe fn test_mm256_maskz_getmant_pd() {
3426 let a = _mm256_set1_pd(10.);
3427 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3428 assert_eq_m256d(r, _mm256_setzero_pd());
3429 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3430 let e = _mm256_set1_pd(1.25);
3431 assert_eq_m256d(r, e);
3432 }
3433
3434 #[simd_test(enable = "avx512f,avx512vl")]
3435 unsafe fn test_mm_getmant_pd() {
3436 let a = _mm_set1_pd(10.);
3437 let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3438 let e = _mm_set1_pd(1.25);
3439 assert_eq_m128d(r, e);
3440 }
3441
3442 #[simd_test(enable = "avx512f,avx512vl")]
3443 unsafe fn test_mm_mask_getmant_pd() {
3444 let a = _mm_set1_pd(10.);
3445 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3446 assert_eq_m128d(r, a);
3447 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3448 let e = _mm_set1_pd(1.25);
3449 assert_eq_m128d(r, e);
3450 }
3451
3452 #[simd_test(enable = "avx512f,avx512vl")]
3453 unsafe fn test_mm_maskz_getmant_pd() {
3454 let a = _mm_set1_pd(10.);
3455 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3456 assert_eq_m128d(r, _mm_setzero_pd());
3457 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3458 let e = _mm_set1_pd(1.25);
3459 assert_eq_m128d(r, e);
3460 }
3461
3462 #[simd_test(enable = "avx512f")]
3463 unsafe fn test_mm512_cvtps_pd() {
3464 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3465 let r = _mm512_cvtps_pd(a);
3466 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3467 assert_eq_m512d(r, e);
3468 }
3469
3470 #[simd_test(enable = "avx512f")]
3471 unsafe fn test_mm512_mask_cvtps_pd() {
3472 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3473 let src = _mm512_set1_pd(0.);
3474 let r = _mm512_mask_cvtps_pd(src, 0, a);
3475 assert_eq_m512d(r, src);
3476 let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3477 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3478 assert_eq_m512d(r, e);
3479 }
3480
3481 #[simd_test(enable = "avx512f")]
3482 unsafe fn test_mm512_maskz_cvtps_pd() {
3483 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3484 let r = _mm512_maskz_cvtps_pd(0, a);
3485 assert_eq_m512d(r, _mm512_setzero_pd());
3486 let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3487 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3488 assert_eq_m512d(r, e);
3489 }
3490
3491 #[simd_test(enable = "avx512f")]
3492 unsafe fn test_mm512_cvtpslo_pd() {
3493 let v2 = _mm512_setr_ps(
3494 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3495 );
3496 let r = _mm512_cvtpslo_pd(v2);
3497 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3498 assert_eq_m512d(r, e);
3499 }
3500
3501 #[simd_test(enable = "avx512f")]
3502 unsafe fn test_mm512_mask_cvtpslo_pd() {
3503 let v2 = _mm512_setr_ps(
3504 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3505 );
3506 let src = _mm512_set1_pd(0.);
3507 let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3508 assert_eq_m512d(r, src);
3509 let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3510 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3511 assert_eq_m512d(r, e);
3512 }
3513
3514 #[simd_test(enable = "avx512f")]
3515 unsafe fn test_mm512_cvtpd_ps() {
3516 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3517 let r = _mm512_cvtpd_ps(a);
3518 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3519 assert_eq_m256(r, e);
3520 }
3521
3522 #[simd_test(enable = "avx512f")]
3523 unsafe fn test_mm512_mask_cvtpd_ps() {
3524 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3525 let src = _mm256_set1_ps(0.);
3526 let r = _mm512_mask_cvtpd_ps(src, 0, a);
3527 assert_eq_m256(r, src);
3528 let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3529 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3530 assert_eq_m256(r, e);
3531 }
3532
3533 #[simd_test(enable = "avx512f")]
3534 unsafe fn test_mm512_maskz_cvtpd_ps() {
3535 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3536 let r = _mm512_maskz_cvtpd_ps(0, a);
3537 assert_eq_m256(r, _mm256_setzero_ps());
3538 let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3539 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3540 assert_eq_m256(r, e);
3541 }
3542
3543 #[simd_test(enable = "avx512f,avx512vl")]
3544 unsafe fn test_mm256_mask_cvtpd_ps() {
3545 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3546 let src = _mm_set1_ps(0.);
3547 let r = _mm256_mask_cvtpd_ps(src, 0, a);
3548 assert_eq_m128(r, src);
3549 let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3550 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3551 assert_eq_m128(r, e);
3552 }
3553
3554 #[simd_test(enable = "avx512f,avx512vl")]
3555 unsafe fn test_mm256_maskz_cvtpd_ps() {
3556 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3557 let r = _mm256_maskz_cvtpd_ps(0, a);
3558 assert_eq_m128(r, _mm_setzero_ps());
3559 let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3560 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3561 assert_eq_m128(r, e);
3562 }
3563
3564 #[simd_test(enable = "avx512f,avx512vl")]
3565 unsafe fn test_mm_mask_cvtpd_ps() {
3566 let a = _mm_set_pd(6., -7.5);
3567 let src = _mm_set1_ps(0.);
3568 let r = _mm_mask_cvtpd_ps(src, 0, a);
3569 assert_eq_m128(r, src);
3570 let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3571 let e = _mm_set_ps(0., 0., 6., -7.5);
3572 assert_eq_m128(r, e);
3573 }
3574
3575 #[simd_test(enable = "avx512f,avx512vl")]
3576 unsafe fn test_mm_maskz_cvtpd_ps() {
3577 let a = _mm_set_pd(6., -7.5);
3578 let r = _mm_maskz_cvtpd_ps(0, a);
3579 assert_eq_m128(r, _mm_setzero_ps());
3580 let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3581 let e = _mm_set_ps(0., 0., 6., -7.5);
3582 assert_eq_m128(r, e);
3583 }
3584
3585 #[simd_test(enable = "avx512f")]
3586 unsafe fn test_mm512_cvtpd_epi32() {
3587 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3588 let r = _mm512_cvtpd_epi32(a);
3589 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3590 assert_eq_m256i(r, e);
3591 }
3592
3593 #[simd_test(enable = "avx512f")]
3594 unsafe fn test_mm512_mask_cvtpd_epi32() {
3595 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3596 let src = _mm256_set1_epi32(0);
3597 let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3598 assert_eq_m256i(r, src);
3599 let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3600 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3601 assert_eq_m256i(r, e);
3602 }
3603
3604 #[simd_test(enable = "avx512f")]
3605 unsafe fn test_mm512_maskz_cvtpd_epi32() {
3606 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3607 let r = _mm512_maskz_cvtpd_epi32(0, a);
3608 assert_eq_m256i(r, _mm256_setzero_si256());
3609 let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3610 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3611 assert_eq_m256i(r, e);
3612 }
3613
3614 #[simd_test(enable = "avx512f,avx512vl")]
3615 unsafe fn test_mm256_mask_cvtpd_epi32() {
3616 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3617 let src = _mm_set1_epi32(0);
3618 let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3619 assert_eq_m128i(r, src);
3620 let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3621 let e = _mm_set_epi32(4, -6, 6, -8);
3622 assert_eq_m128i(r, e);
3623 }
3624
3625 #[simd_test(enable = "avx512f,avx512vl")]
3626 unsafe fn test_mm256_maskz_cvtpd_epi32() {
3627 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3628 let r = _mm256_maskz_cvtpd_epi32(0, a);
3629 assert_eq_m128i(r, _mm_setzero_si128());
3630 let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3631 let e = _mm_set_epi32(4, -6, 6, -8);
3632 assert_eq_m128i(r, e);
3633 }
3634
3635 #[simd_test(enable = "avx512f,avx512vl")]
3636 unsafe fn test_mm_mask_cvtpd_epi32() {
3637 let a = _mm_set_pd(6., -7.5);
3638 let src = _mm_set1_epi32(0);
3639 let r = _mm_mask_cvtpd_epi32(src, 0, a);
3640 assert_eq_m128i(r, src);
3641 let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3642 let e = _mm_set_epi32(0, 0, 6, -8);
3643 assert_eq_m128i(r, e);
3644 }
3645
3646 #[simd_test(enable = "avx512f,avx512vl")]
3647 unsafe fn test_mm_maskz_cvtpd_epi32() {
3648 let a = _mm_set_pd(6., -7.5);
3649 let r = _mm_maskz_cvtpd_epi32(0, a);
3650 assert_eq_m128i(r, _mm_setzero_si128());
3651 let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3652 let e = _mm_set_epi32(0, 0, 6, -8);
3653 assert_eq_m128i(r, e);
3654 }
3655
3656 #[simd_test(enable = "avx512f")]
3657 unsafe fn test_mm512_cvtpd_epu32() {
3658 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3659 let r = _mm512_cvtpd_epu32(a);
3660 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3661 assert_eq_m256i(r, e);
3662 }
3663
3664 #[simd_test(enable = "avx512f")]
3665 unsafe fn test_mm512_mask_cvtpd_epu32() {
3666 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3667 let src = _mm256_set1_epi32(0);
3668 let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3669 assert_eq_m256i(r, src);
3670 let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3671 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3672 assert_eq_m256i(r, e);
3673 }
3674
3675 #[simd_test(enable = "avx512f")]
3676 unsafe fn test_mm512_maskz_cvtpd_epu32() {
3677 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3678 let r = _mm512_maskz_cvtpd_epu32(0, a);
3679 assert_eq_m256i(r, _mm256_setzero_si256());
3680 let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3681 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3682 assert_eq_m256i(r, e);
3683 }
3684
3685 #[simd_test(enable = "avx512f,avx512vl")]
3686 unsafe fn test_mm256_cvtpd_epu32() {
3687 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3688 let r = _mm256_cvtpd_epu32(a);
3689 let e = _mm_set_epi32(4, 6, 6, 8);
3690 assert_eq_m128i(r, e);
3691 }
3692
3693 #[simd_test(enable = "avx512f,avx512vl")]
3694 unsafe fn test_mm256_mask_cvtpd_epu32() {
3695 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3696 let src = _mm_set1_epi32(0);
3697 let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3698 assert_eq_m128i(r, src);
3699 let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3700 let e = _mm_set_epi32(4, 6, 6, 8);
3701 assert_eq_m128i(r, e);
3702 }
3703
3704 #[simd_test(enable = "avx512f,avx512vl")]
3705 unsafe fn test_mm256_maskz_cvtpd_epu32() {
3706 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3707 let r = _mm256_maskz_cvtpd_epu32(0, a);
3708 assert_eq_m128i(r, _mm_setzero_si128());
3709 let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3710 let e = _mm_set_epi32(4, 6, 6, 8);
3711 assert_eq_m128i(r, e);
3712 }
3713
3714 #[simd_test(enable = "avx512f,avx512vl")]
3715 unsafe fn test_mm_cvtpd_epu32() {
3716 let a = _mm_set_pd(6., 7.5);
3717 let r = _mm_cvtpd_epu32(a);
3718 let e = _mm_set_epi32(0, 0, 6, 8);
3719 assert_eq_m128i(r, e);
3720 }
3721
3722 #[simd_test(enable = "avx512f,avx512vl")]
3723 unsafe fn test_mm_mask_cvtpd_epu32() {
3724 let a = _mm_set_pd(6., 7.5);
3725 let src = _mm_set1_epi32(0);
3726 let r = _mm_mask_cvtpd_epu32(src, 0, a);
3727 assert_eq_m128i(r, src);
3728 let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3729 let e = _mm_set_epi32(0, 0, 6, 8);
3730 assert_eq_m128i(r, e);
3731 }
3732
3733 #[simd_test(enable = "avx512f,avx512vl")]
3734 unsafe fn test_mm_maskz_cvtpd_epu32() {
3735 let a = _mm_set_pd(6., 7.5);
3736 let r = _mm_maskz_cvtpd_epu32(0, a);
3737 assert_eq_m128i(r, _mm_setzero_si128());
3738 let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3739 let e = _mm_set_epi32(0, 0, 6, 8);
3740 assert_eq_m128i(r, e);
3741 }
3742
3743 #[simd_test(enable = "avx512f")]
3744 unsafe fn test_mm512_cvtpd_pslo() {
3745 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3746 let r = _mm512_cvtpd_pslo(v2);
3747 let e = _mm512_setr_ps(
3748 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3749 );
3750 assert_eq_m512(r, e);
3751 }
3752
3753 #[simd_test(enable = "avx512f")]
3754 unsafe fn test_mm512_mask_cvtpd_pslo() {
3755 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3756 let src = _mm512_set1_ps(0.);
3757 let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3758 assert_eq_m512(r, src);
3759 let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3760 let e = _mm512_setr_ps(
3761 0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3762 );
3763 assert_eq_m512(r, e);
3764 }
3765
3766 #[simd_test(enable = "avx512f")]
3767 unsafe fn test_mm512_cvtepi8_epi64() {
3768 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3769 let r = _mm512_cvtepi8_epi64(a);
3770 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3771 assert_eq_m512i(r, e);
3772 }
3773
3774 #[simd_test(enable = "avx512f")]
3775 unsafe fn test_mm512_mask_cvtepi8_epi64() {
3776 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3777 let src = _mm512_set1_epi64(-1);
3778 let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3779 assert_eq_m512i(r, src);
3780 let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3781 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3782 assert_eq_m512i(r, e);
3783 }
3784
3785 #[simd_test(enable = "avx512f")]
3786 unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3787 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3788 let r = _mm512_maskz_cvtepi8_epi64(0, a);
3789 assert_eq_m512i(r, _mm512_setzero_si512());
3790 let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3791 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3792 assert_eq_m512i(r, e);
3793 }
3794
3795 #[simd_test(enable = "avx512f,avx512vl")]
3796 unsafe fn test_mm256_mask_cvtepi8_epi64() {
3797 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3798 let src = _mm256_set1_epi64x(-1);
3799 let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3800 assert_eq_m256i(r, src);
3801 let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3802 let e = _mm256_set_epi64x(12, 13, 14, 15);
3803 assert_eq_m256i(r, e);
3804 }
3805
3806 #[simd_test(enable = "avx512f,avx512vl")]
3807 unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3808 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3809 let r = _mm256_maskz_cvtepi8_epi64(0, a);
3810 assert_eq_m256i(r, _mm256_setzero_si256());
3811 let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3812 let e = _mm256_set_epi64x(12, 13, 14, 15);
3813 assert_eq_m256i(r, e);
3814 }
3815
3816 #[simd_test(enable = "avx512f,avx512vl")]
3817 unsafe fn test_mm_mask_cvtepi8_epi64() {
3818 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3819 let src = _mm_set1_epi64x(-1);
3820 let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3821 assert_eq_m128i(r, src);
3822 let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3823 let e = _mm_set_epi64x(14, 15);
3824 assert_eq_m128i(r, e);
3825 }
3826
3827 #[simd_test(enable = "avx512f,avx512vl")]
3828 unsafe fn test_mm_maskz_cvtepi8_epi64() {
3829 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3830 let r = _mm_maskz_cvtepi8_epi64(0, a);
3831 assert_eq_m128i(r, _mm_setzero_si128());
3832 let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3833 let e = _mm_set_epi64x(14, 15);
3834 assert_eq_m128i(r, e);
3835 }
3836
3837 #[simd_test(enable = "avx512f")]
3838 unsafe fn test_mm512_cvtepu8_epi64() {
3839 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3840 let r = _mm512_cvtepu8_epi64(a);
3841 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3842 assert_eq_m512i(r, e);
3843 }
3844
3845 #[simd_test(enable = "avx512f")]
3846 unsafe fn test_mm512_mask_cvtepu8_epi64() {
3847 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3848 let src = _mm512_set1_epi64(-1);
3849 let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3850 assert_eq_m512i(r, src);
3851 let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3852 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3853 assert_eq_m512i(r, e);
3854 }
3855
3856 #[simd_test(enable = "avx512f")]
3857 unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3858 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3859 let r = _mm512_maskz_cvtepu8_epi64(0, a);
3860 assert_eq_m512i(r, _mm512_setzero_si512());
3861 let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3862 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3863 assert_eq_m512i(r, e);
3864 }
3865
3866 #[simd_test(enable = "avx512f,avx512vl")]
3867 unsafe fn test_mm256_mask_cvtepu8_epi64() {
3868 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3869 let src = _mm256_set1_epi64x(-1);
3870 let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3871 assert_eq_m256i(r, src);
3872 let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3873 let e = _mm256_set_epi64x(12, 13, 14, 15);
3874 assert_eq_m256i(r, e);
3875 }
3876
3877 #[simd_test(enable = "avx512f,avx512vl")]
3878 unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3879 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3880 let r = _mm256_maskz_cvtepu8_epi64(0, a);
3881 assert_eq_m256i(r, _mm256_setzero_si256());
3882 let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3883 let e = _mm256_set_epi64x(12, 13, 14, 15);
3884 assert_eq_m256i(r, e);
3885 }
3886
3887 #[simd_test(enable = "avx512f,avx512vl")]
3888 unsafe fn test_mm_mask_cvtepu8_epi64() {
3889 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3890 let src = _mm_set1_epi64x(-1);
3891 let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3892 assert_eq_m128i(r, src);
3893 let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3894 let e = _mm_set_epi64x(14, 15);
3895 assert_eq_m128i(r, e);
3896 }
3897
3898 #[simd_test(enable = "avx512f,avx512vl")]
3899 unsafe fn test_mm_maskz_cvtepu8_epi64() {
3900 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3901 let r = _mm_maskz_cvtepu8_epi64(0, a);
3902 assert_eq_m128i(r, _mm_setzero_si128());
3903 let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3904 let e = _mm_set_epi64x(14, 15);
3905 assert_eq_m128i(r, e);
3906 }
3907
3908 #[simd_test(enable = "avx512f")]
3909 unsafe fn test_mm512_cvtepi16_epi64() {
3910 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3911 let r = _mm512_cvtepi16_epi64(a);
3912 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3913 assert_eq_m512i(r, e);
3914 }
3915
3916 #[simd_test(enable = "avx512f")]
3917 unsafe fn test_mm512_mask_cvtepi16_epi64() {
3918 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3919 let src = _mm512_set1_epi64(-1);
3920 let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3921 assert_eq_m512i(r, src);
3922 let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3923 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3924 assert_eq_m512i(r, e);
3925 }
3926
3927 #[simd_test(enable = "avx512f")]
3928 unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3929 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3930 let r = _mm512_maskz_cvtepi16_epi64(0, a);
3931 assert_eq_m512i(r, _mm512_setzero_si512());
3932 let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3933 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3934 assert_eq_m512i(r, e);
3935 }
3936
3937 #[simd_test(enable = "avx512f,avx512vl")]
3938 unsafe fn test_mm256_mask_cvtepi16_epi64() {
3939 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3940 let src = _mm256_set1_epi64x(-1);
3941 let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3942 assert_eq_m256i(r, src);
3943 let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3944 let e = _mm256_set_epi64x(12, 13, 14, 15);
3945 assert_eq_m256i(r, e);
3946 }
3947
3948 #[simd_test(enable = "avx512f,avx512vl")]
3949 unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3950 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3951 let r = _mm256_maskz_cvtepi16_epi64(0, a);
3952 assert_eq_m256i(r, _mm256_setzero_si256());
3953 let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3954 let e = _mm256_set_epi64x(12, 13, 14, 15);
3955 assert_eq_m256i(r, e);
3956 }
3957
3958 #[simd_test(enable = "avx512f,avx512vl")]
3959 unsafe fn test_mm_mask_cvtepi16_epi64() {
3960 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3961 let src = _mm_set1_epi64x(-1);
3962 let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3963 assert_eq_m128i(r, src);
3964 let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3965 let e = _mm_set_epi64x(14, 15);
3966 assert_eq_m128i(r, e);
3967 }
3968
3969 #[simd_test(enable = "avx512f,avx512vl")]
3970 unsafe fn test_mm_maskz_cvtepi16_epi64() {
3971 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3972 let r = _mm_maskz_cvtepi16_epi64(0, a);
3973 assert_eq_m128i(r, _mm_setzero_si128());
3974 let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3975 let e = _mm_set_epi64x(14, 15);
3976 assert_eq_m128i(r, e);
3977 }
3978
3979 #[simd_test(enable = "avx512f")]
3980 unsafe fn test_mm512_cvtepu16_epi64() {
3981 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3982 let r = _mm512_cvtepu16_epi64(a);
3983 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3984 assert_eq_m512i(r, e);
3985 }
3986
3987 #[simd_test(enable = "avx512f")]
3988 unsafe fn test_mm512_mask_cvtepu16_epi64() {
3989 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3990 let src = _mm512_set1_epi64(-1);
3991 let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3992 assert_eq_m512i(r, src);
3993 let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3994 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3995 assert_eq_m512i(r, e);
3996 }
3997
3998 #[simd_test(enable = "avx512f")]
3999 unsafe fn test_mm512_maskz_cvtepu16_epi64() {
4000 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4001 let r = _mm512_maskz_cvtepu16_epi64(0, a);
4002 assert_eq_m512i(r, _mm512_setzero_si512());
4003 let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
4004 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4005 assert_eq_m512i(r, e);
4006 }
4007
4008 #[simd_test(enable = "avx512f,avx512vl")]
4009 unsafe fn test_mm256_mask_cvtepu16_epi64() {
4010 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4011 let src = _mm256_set1_epi64x(-1);
4012 let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
4013 assert_eq_m256i(r, src);
4014 let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
4015 let e = _mm256_set_epi64x(12, 13, 14, 15);
4016 assert_eq_m256i(r, e);
4017 }
4018
4019 #[simd_test(enable = "avx512f,avx512vl")]
4020 unsafe fn test_mm256_maskz_cvtepu16_epi64() {
4021 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4022 let r = _mm256_maskz_cvtepu16_epi64(0, a);
4023 assert_eq_m256i(r, _mm256_setzero_si256());
4024 let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
4025 let e = _mm256_set_epi64x(12, 13, 14, 15);
4026 assert_eq_m256i(r, e);
4027 }
4028
4029 #[simd_test(enable = "avx512f,avx512vl")]
4030 unsafe fn test_mm_mask_cvtepu16_epi64() {
4031 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4032 let src = _mm_set1_epi64x(-1);
4033 let r = _mm_mask_cvtepu16_epi64(src, 0, a);
4034 assert_eq_m128i(r, src);
4035 let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
4036 let e = _mm_set_epi64x(14, 15);
4037 assert_eq_m128i(r, e);
4038 }
4039
4040 #[simd_test(enable = "avx512f,avx512vl")]
4041 unsafe fn test_mm_maskz_cvtepu16_epi64() {
4042 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4043 let r = _mm_maskz_cvtepu16_epi64(0, a);
4044 assert_eq_m128i(r, _mm_setzero_si128());
4045 let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
4046 let e = _mm_set_epi64x(14, 15);
4047 assert_eq_m128i(r, e);
4048 }
4049
4050 #[simd_test(enable = "avx512f")]
4051 unsafe fn test_mm512_cvtepi32_epi64() {
4052 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4053 let r = _mm512_cvtepi32_epi64(a);
4054 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4055 assert_eq_m512i(r, e);
4056 }
4057
4058 #[simd_test(enable = "avx512f")]
4059 unsafe fn test_mm512_mask_cvtepi32_epi64() {
4060 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4061 let src = _mm512_set1_epi64(-1);
4062 let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
4063 assert_eq_m512i(r, src);
4064 let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
4065 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4066 assert_eq_m512i(r, e);
4067 }
4068
4069 #[simd_test(enable = "avx512f")]
4070 unsafe fn test_mm512_maskz_cvtepi32_epi64() {
4071 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4072 let r = _mm512_maskz_cvtepi32_epi64(0, a);
4073 assert_eq_m512i(r, _mm512_setzero_si512());
4074 let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
4075 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4076 assert_eq_m512i(r, e);
4077 }
4078
4079 #[simd_test(enable = "avx512f,avx512vl")]
4080 unsafe fn test_mm256_mask_cvtepi32_epi64() {
4081 let a = _mm_set_epi32(8, 9, 10, 11);
4082 let src = _mm256_set1_epi64x(-1);
4083 let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
4084 assert_eq_m256i(r, src);
4085 let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
4086 let e = _mm256_set_epi64x(8, 9, 10, 11);
4087 assert_eq_m256i(r, e);
4088 }
4089
4090 #[simd_test(enable = "avx512f,avx512vl")]
4091 unsafe fn test_mm256_maskz_cvtepi32_epi64() {
4092 let a = _mm_set_epi32(8, 9, 10, 11);
4093 let r = _mm256_maskz_cvtepi32_epi64(0, a);
4094 assert_eq_m256i(r, _mm256_setzero_si256());
4095 let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
4096 let e = _mm256_set_epi64x(8, 9, 10, 11);
4097 assert_eq_m256i(r, e);
4098 }
4099
4100 #[simd_test(enable = "avx512f,avx512vl")]
4101 unsafe fn test_mm_mask_cvtepi32_epi64() {
4102 let a = _mm_set_epi32(8, 9, 10, 11);
4103 let src = _mm_set1_epi64x(0);
4104 let r = _mm_mask_cvtepi32_epi64(src, 0, a);
4105 assert_eq_m128i(r, src);
4106 let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
4107 let e = _mm_set_epi64x(10, 11);
4108 assert_eq_m128i(r, e);
4109 }
4110
4111 #[simd_test(enable = "avx512f,avx512vl")]
4112 unsafe fn test_mm_maskz_cvtepi32_epi64() {
4113 let a = _mm_set_epi32(8, 9, 10, 11);
4114 let r = _mm_maskz_cvtepi32_epi64(0, a);
4115 assert_eq_m128i(r, _mm_setzero_si128());
4116 let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
4117 let e = _mm_set_epi64x(10, 11);
4118 assert_eq_m128i(r, e);
4119 }
4120
4121 #[simd_test(enable = "avx512f")]
4122 unsafe fn test_mm512_cvtepu32_epi64() {
4123 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4124 let r = _mm512_cvtepu32_epi64(a);
4125 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4126 assert_eq_m512i(r, e);
4127 }
4128
4129 #[simd_test(enable = "avx512f")]
4130 unsafe fn test_mm512_mask_cvtepu32_epi64() {
4131 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4132 let src = _mm512_set1_epi64(-1);
4133 let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
4134 assert_eq_m512i(r, src);
4135 let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
4136 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4137 assert_eq_m512i(r, e);
4138 }
4139
4140 #[simd_test(enable = "avx512f")]
4141 unsafe fn test_mm512_maskz_cvtepu32_epi64() {
4142 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4143 let r = _mm512_maskz_cvtepu32_epi64(0, a);
4144 assert_eq_m512i(r, _mm512_setzero_si512());
4145 let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4146 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4147 assert_eq_m512i(r, e);
4148 }
4149
4150 #[simd_test(enable = "avx512f,avx512vl")]
4151 unsafe fn test_mm256_mask_cvtepu32_epi64() {
4152 let a = _mm_set_epi32(12, 13, 14, 15);
4153 let src = _mm256_set1_epi64x(-1);
4154 let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4155 assert_eq_m256i(r, src);
4156 let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4157 let e = _mm256_set_epi64x(12, 13, 14, 15);
4158 assert_eq_m256i(r, e);
4159 }
4160
4161 #[simd_test(enable = "avx512f,avx512vl")]
4162 unsafe fn test_mm256_maskz_cvtepu32_epi64() {
4163 let a = _mm_set_epi32(12, 13, 14, 15);
4164 let r = _mm256_maskz_cvtepu32_epi64(0, a);
4165 assert_eq_m256i(r, _mm256_setzero_si256());
4166 let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4167 let e = _mm256_set_epi64x(12, 13, 14, 15);
4168 assert_eq_m256i(r, e);
4169 }
4170
4171 #[simd_test(enable = "avx512f,avx512vl")]
4172 unsafe fn test_mm_mask_cvtepu32_epi64() {
4173 let a = _mm_set_epi32(12, 13, 14, 15);
4174 let src = _mm_set1_epi64x(-1);
4175 let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4176 assert_eq_m128i(r, src);
4177 let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4178 let e = _mm_set_epi64x(14, 15);
4179 assert_eq_m128i(r, e);
4180 }
4181
4182 #[simd_test(enable = "avx512f,avx512vl")]
4183 unsafe fn test_mm_maskz_cvtepu32_epi64() {
4184 let a = _mm_set_epi32(12, 13, 14, 15);
4185 let r = _mm_maskz_cvtepu32_epi64(0, a);
4186 assert_eq_m128i(r, _mm_setzero_si128());
4187 let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4188 let e = _mm_set_epi64x(14, 15);
4189 assert_eq_m128i(r, e);
4190 }
4191
4192 #[simd_test(enable = "avx512f")]
4193 unsafe fn test_mm512_cvtepi32_pd() {
4194 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4195 let r = _mm512_cvtepi32_pd(a);
4196 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4197 assert_eq_m512d(r, e);
4198 }
4199
4200 #[simd_test(enable = "avx512f")]
4201 unsafe fn test_mm512_mask_cvtepi32_pd() {
4202 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4203 let src = _mm512_set1_pd(-1.);
4204 let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4205 assert_eq_m512d(r, src);
4206 let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4207 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4208 assert_eq_m512d(r, e);
4209 }
4210
4211 #[simd_test(enable = "avx512f")]
4212 unsafe fn test_mm512_maskz_cvtepi32_pd() {
4213 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4214 let r = _mm512_maskz_cvtepi32_pd(0, a);
4215 assert_eq_m512d(r, _mm512_setzero_pd());
4216 let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4217 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4218 assert_eq_m512d(r, e);
4219 }
4220
4221 #[simd_test(enable = "avx512f,avx512vl")]
4222 unsafe fn test_mm256_mask_cvtepi32_pd() {
4223 let a = _mm_set_epi32(12, 13, 14, 15);
4224 let src = _mm256_set1_pd(-1.);
4225 let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4226 assert_eq_m256d(r, src);
4227 let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4228 let e = _mm256_set_pd(12., 13., 14., 15.);
4229 assert_eq_m256d(r, e);
4230 }
4231
4232 #[simd_test(enable = "avx512f,avx512vl")]
4233 unsafe fn test_mm256_maskz_cvtepi32_pd() {
4234 let a = _mm_set_epi32(12, 13, 14, 15);
4235 let r = _mm256_maskz_cvtepi32_pd(0, a);
4236 assert_eq_m256d(r, _mm256_setzero_pd());
4237 let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4238 let e = _mm256_set_pd(12., 13., 14., 15.);
4239 assert_eq_m256d(r, e);
4240 }
4241
4242 #[simd_test(enable = "avx512f,avx512vl")]
4243 unsafe fn test_mm_mask_cvtepi32_pd() {
4244 let a = _mm_set_epi32(12, 13, 14, 15);
4245 let src = _mm_set1_pd(-1.);
4246 let r = _mm_mask_cvtepi32_pd(src, 0, a);
4247 assert_eq_m128d(r, src);
4248 let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4249 let e = _mm_set_pd(14., 15.);
4250 assert_eq_m128d(r, e);
4251 }
4252
4253 #[simd_test(enable = "avx512f,avx512vl")]
4254 unsafe fn test_mm_maskz_cvtepi32_pd() {
4255 let a = _mm_set_epi32(12, 13, 14, 15);
4256 let r = _mm_maskz_cvtepi32_pd(0, a);
4257 assert_eq_m128d(r, _mm_setzero_pd());
4258 let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4259 let e = _mm_set_pd(14., 15.);
4260 assert_eq_m128d(r, e);
4261 }
4262
4263 #[simd_test(enable = "avx512f")]
4264 unsafe fn test_mm512_cvtepu32_pd() {
4265 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4266 let r = _mm512_cvtepu32_pd(a);
4267 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4268 assert_eq_m512d(r, e);
4269 }
4270
4271 #[simd_test(enable = "avx512f")]
4272 unsafe fn test_mm512_mask_cvtepu32_pd() {
4273 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4274 let src = _mm512_set1_pd(-1.);
4275 let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4276 assert_eq_m512d(r, src);
4277 let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4278 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4279 assert_eq_m512d(r, e);
4280 }
4281
4282 #[simd_test(enable = "avx512f")]
4283 unsafe fn test_mm512_maskz_cvtepu32_pd() {
4284 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4285 let r = _mm512_maskz_cvtepu32_pd(0, a);
4286 assert_eq_m512d(r, _mm512_setzero_pd());
4287 let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4288 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4289 assert_eq_m512d(r, e);
4290 }
4291
4292 #[simd_test(enable = "avx512f,avx512vl")]
4293 unsafe fn test_mm256_cvtepu32_pd() {
4294 let a = _mm_set_epi32(12, 13, 14, 15);
4295 let r = _mm256_cvtepu32_pd(a);
4296 let e = _mm256_set_pd(12., 13., 14., 15.);
4297 assert_eq_m256d(r, e);
4298 }
4299
4300 #[simd_test(enable = "avx512f,avx512vl")]
4301 unsafe fn test_mm256_mask_cvtepu32_pd() {
4302 let a = _mm_set_epi32(12, 13, 14, 15);
4303 let src = _mm256_set1_pd(-1.);
4304 let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4305 assert_eq_m256d(r, src);
4306 let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4307 let e = _mm256_set_pd(12., 13., 14., 15.);
4308 assert_eq_m256d(r, e);
4309 }
4310
4311 #[simd_test(enable = "avx512f,avx512vl")]
4312 unsafe fn test_mm256_maskz_cvtepu32_pd() {
4313 let a = _mm_set_epi32(12, 13, 14, 15);
4314 let r = _mm256_maskz_cvtepu32_pd(0, a);
4315 assert_eq_m256d(r, _mm256_setzero_pd());
4316 let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4317 let e = _mm256_set_pd(12., 13., 14., 15.);
4318 assert_eq_m256d(r, e);
4319 }
4320
4321 #[simd_test(enable = "avx512f,avx512vl")]
4322 unsafe fn test_mm_cvtepu32_pd() {
4323 let a = _mm_set_epi32(12, 13, 14, 15);
4324 let r = _mm_cvtepu32_pd(a);
4325 let e = _mm_set_pd(14., 15.);
4326 assert_eq_m128d(r, e);
4327 }
4328
4329 #[simd_test(enable = "avx512f,avx512vl")]
4330 unsafe fn test_mm_mask_cvtepu32_pd() {
4331 let a = _mm_set_epi32(12, 13, 14, 15);
4332 let src = _mm_set1_pd(-1.);
4333 let r = _mm_mask_cvtepu32_pd(src, 0, a);
4334 assert_eq_m128d(r, src);
4335 let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4336 let e = _mm_set_pd(14., 15.);
4337 assert_eq_m128d(r, e);
4338 }
4339
4340 #[simd_test(enable = "avx512f,avx512vl")]
4341 unsafe fn test_mm_maskz_cvtepu32_pd() {
4342 let a = _mm_set_epi32(12, 13, 14, 15);
4343 let r = _mm_maskz_cvtepu32_pd(0, a);
4344 assert_eq_m128d(r, _mm_setzero_pd());
4345 let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4346 let e = _mm_set_pd(14., 15.);
4347 assert_eq_m128d(r, e);
4348 }
4349
4350 #[simd_test(enable = "avx512f")]
4351 unsafe fn test_mm512_cvtepi32lo_pd() {
4352 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4353 let r = _mm512_cvtepi32lo_pd(a);
4354 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4355 assert_eq_m512d(r, e);
4356 }
4357
4358 #[simd_test(enable = "avx512f")]
4359 unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4360 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4361 let src = _mm512_set1_pd(-1.);
4362 let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4363 assert_eq_m512d(r, src);
4364 let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4365 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4366 assert_eq_m512d(r, e);
4367 }
4368
4369 #[simd_test(enable = "avx512f")]
4370 unsafe fn test_mm512_cvtepu32lo_pd() {
4371 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4372 let r = _mm512_cvtepu32lo_pd(a);
4373 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4374 assert_eq_m512d(r, e);
4375 }
4376
4377 #[simd_test(enable = "avx512f")]
4378 unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4379 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4380 let src = _mm512_set1_pd(-1.);
4381 let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4382 assert_eq_m512d(r, src);
4383 let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4384 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4385 assert_eq_m512d(r, e);
4386 }
4387
4388 #[simd_test(enable = "avx512f")]
4389 unsafe fn test_mm512_cvtepi64_epi32() {
4390 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4391 let r = _mm512_cvtepi64_epi32(a);
4392 let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4393 assert_eq_m256i(r, e);
4394 }
4395
4396 #[simd_test(enable = "avx512f")]
4397 unsafe fn test_mm512_mask_cvtepi64_epi32() {
4398 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4399 let src = _mm256_set1_epi32(-1);
4400 let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4401 assert_eq_m256i(r, src);
4402 let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4403 let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4404 assert_eq_m256i(r, e);
4405 }
4406
4407 #[simd_test(enable = "avx512f")]
4408 unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4409 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4410 let r = _mm512_maskz_cvtepi64_epi32(0, a);
4411 assert_eq_m256i(r, _mm256_setzero_si256());
4412 let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4413 let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4414 assert_eq_m256i(r, e);
4415 }
4416
4417 #[simd_test(enable = "avx512f,avx512vl")]
4418 unsafe fn test_mm256_cvtepi64_epi32() {
4419 let a = _mm256_set_epi64x(1, 2, 3, 4);
4420 let r = _mm256_cvtepi64_epi32(a);
4421 let e = _mm_set_epi32(1, 2, 3, 4);
4422 assert_eq_m128i(r, e);
4423 }
4424
4425 #[simd_test(enable = "avx512f,avx512vl")]
4426 unsafe fn test_mm256_mask_cvtepi64_epi32() {
4427 let a = _mm256_set_epi64x(1, 2, 3, 4);
4428 let src = _mm_set1_epi32(0);
4429 let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4430 assert_eq_m128i(r, src);
4431 let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4432 let e = _mm_set_epi32(1, 2, 3, 4);
4433 assert_eq_m128i(r, e);
4434 }
4435
4436 #[simd_test(enable = "avx512f,avx512vl")]
4437 unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4438 let a = _mm256_set_epi64x(1, 2, 3, 4);
4439 let r = _mm256_maskz_cvtepi64_epi32(0, a);
4440 assert_eq_m128i(r, _mm_setzero_si128());
4441 let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4442 let e = _mm_set_epi32(1, 2, 3, 4);
4443 assert_eq_m128i(r, e);
4444 }
4445
4446 #[simd_test(enable = "avx512f,avx512vl")]
4447 unsafe fn test_mm_cvtepi64_epi32() {
4448 let a = _mm_set_epi64x(3, 4);
4449 let r = _mm_cvtepi64_epi32(a);
4450 let e = _mm_set_epi32(0, 0, 3, 4);
4451 assert_eq_m128i(r, e);
4452 }
4453
4454 #[simd_test(enable = "avx512f,avx512vl")]
4455 unsafe fn test_mm_mask_cvtepi64_epi32() {
4456 let a = _mm_set_epi64x(3, 4);
4457 let src = _mm_set1_epi32(0);
4458 let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4459 assert_eq_m128i(r, src);
4460 let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4461 let e = _mm_set_epi32(0, 0, 3, 4);
4462 assert_eq_m128i(r, e);
4463 }
4464
4465 #[simd_test(enable = "avx512f,avx512vl")]
4466 unsafe fn test_mm_maskz_cvtepi64_epi32() {
4467 let a = _mm_set_epi64x(3, 4);
4468 let r = _mm_maskz_cvtepi64_epi32(0, a);
4469 assert_eq_m128i(r, _mm_setzero_si128());
4470 let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4471 let e = _mm_set_epi32(0, 0, 3, 4);
4472 assert_eq_m128i(r, e);
4473 }
4474
4475 #[simd_test(enable = "avx512f")]
4476 unsafe fn test_mm512_cvtepi64_epi16() {
4477 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4478 let r = _mm512_cvtepi64_epi16(a);
4479 let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4480 assert_eq_m128i(r, e);
4481 }
4482
4483 #[simd_test(enable = "avx512f")]
4484 unsafe fn test_mm512_mask_cvtepi64_epi16() {
4485 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4486 let src = _mm_set1_epi16(-1);
4487 let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4488 assert_eq_m128i(r, src);
4489 let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4490 let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4491 assert_eq_m128i(r, e);
4492 }
4493
4494 #[simd_test(enable = "avx512f")]
4495 unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4496 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4497 let r = _mm512_maskz_cvtepi64_epi16(0, a);
4498 assert_eq_m128i(r, _mm_setzero_si128());
4499 let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4500 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4501 assert_eq_m128i(r, e);
4502 }
4503
4504 #[simd_test(enable = "avx512f,avx512vl")]
4505 unsafe fn test_mm256_cvtepi64_epi16() {
4506 let a = _mm256_set_epi64x(12, 13, 14, 15);
4507 let r = _mm256_cvtepi64_epi16(a);
4508 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4509 assert_eq_m128i(r, e);
4510 }
4511
4512 #[simd_test(enable = "avx512f,avx512vl")]
4513 unsafe fn test_mm256_mask_cvtepi64_epi16() {
4514 let a = _mm256_set_epi64x(12, 13, 14, 15);
4515 let src = _mm_set1_epi16(0);
4516 let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4517 assert_eq_m128i(r, src);
4518 let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4519 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4520 assert_eq_m128i(r, e);
4521 }
4522
4523 #[simd_test(enable = "avx512f,avx512vl")]
4524 unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4525 let a = _mm256_set_epi64x(12, 13, 14, 15);
4526 let r = _mm256_maskz_cvtepi64_epi16(0, a);
4527 assert_eq_m128i(r, _mm_setzero_si128());
4528 let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4529 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4530 assert_eq_m128i(r, e);
4531 }
4532
4533 #[simd_test(enable = "avx512f,avx512vl")]
4534 unsafe fn test_mm_cvtepi64_epi16() {
4535 let a = _mm_set_epi64x(14, 15);
4536 let r = _mm_cvtepi64_epi16(a);
4537 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4538 assert_eq_m128i(r, e);
4539 }
4540
4541 #[simd_test(enable = "avx512f,avx512vl")]
4542 unsafe fn test_mm_mask_cvtepi64_epi16() {
4543 let a = _mm_set_epi64x(14, 15);
4544 let src = _mm_set1_epi16(0);
4545 let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4546 assert_eq_m128i(r, src);
4547 let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4548 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4549 assert_eq_m128i(r, e);
4550 }
4551
4552 #[simd_test(enable = "avx512f,avx512vl")]
4553 unsafe fn test_mm_maskz_cvtepi64_epi16() {
4554 let a = _mm_set_epi64x(14, 15);
4555 let r = _mm_maskz_cvtepi64_epi16(0, a);
4556 assert_eq_m128i(r, _mm_setzero_si128());
4557 let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4558 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4559 assert_eq_m128i(r, e);
4560 }
4561
4562 #[simd_test(enable = "avx512f")]
4563 unsafe fn test_mm512_cvtepi64_epi8() {
4564 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4565 let r = _mm512_cvtepi64_epi8(a);
4566 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4567 assert_eq_m128i(r, e);
4568 }
4569
4570 #[simd_test(enable = "avx512f")]
4571 unsafe fn test_mm512_mask_cvtepi64_epi8() {
4572 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4573 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4574 let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4575 assert_eq_m128i(r, src);
4576 let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4577 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4578 assert_eq_m128i(r, e);
4579 }
4580
4581 #[simd_test(enable = "avx512f")]
4582 unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4583 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4584 let r = _mm512_maskz_cvtepi64_epi8(0, a);
4585 assert_eq_m128i(r, _mm_setzero_si128());
4586 let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4587 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4588 assert_eq_m128i(r, e);
4589 }
4590
4591 #[simd_test(enable = "avx512f,avx512vl")]
4592 unsafe fn test_mm256_cvtepi64_epi8() {
4593 let a = _mm256_set_epi64x(12, 13, 14, 15);
4594 let r = _mm256_cvtepi64_epi8(a);
4595 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4596 assert_eq_m128i(r, e);
4597 }
4598
4599 #[simd_test(enable = "avx512f,avx512vl")]
4600 unsafe fn test_mm256_mask_cvtepi64_epi8() {
4601 let a = _mm256_set_epi64x(12, 13, 14, 15);
4602 let src = _mm_set1_epi8(0);
4603 let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4604 assert_eq_m128i(r, src);
4605 let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4606 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4607 assert_eq_m128i(r, e);
4608 }
4609
4610 #[simd_test(enable = "avx512f,avx512vl")]
4611 unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4612 let a = _mm256_set_epi64x(12, 13, 14, 15);
4613 let r = _mm256_maskz_cvtepi64_epi8(0, a);
4614 assert_eq_m128i(r, _mm_setzero_si128());
4615 let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4616 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4617 assert_eq_m128i(r, e);
4618 }
4619
4620 #[simd_test(enable = "avx512f,avx512vl")]
4621 unsafe fn test_mm_cvtepi64_epi8() {
4622 let a = _mm_set_epi64x(14, 15);
4623 let r = _mm_cvtepi64_epi8(a);
4624 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4625 assert_eq_m128i(r, e);
4626 }
4627
4628 #[simd_test(enable = "avx512f,avx512vl")]
4629 unsafe fn test_mm_mask_cvtepi64_epi8() {
4630 let a = _mm_set_epi64x(14, 15);
4631 let src = _mm_set1_epi8(0);
4632 let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4633 assert_eq_m128i(r, src);
4634 let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4635 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4636 assert_eq_m128i(r, e);
4637 }
4638
4639 #[simd_test(enable = "avx512f,avx512vl")]
4640 unsafe fn test_mm_maskz_cvtepi64_epi8() {
4641 let a = _mm_set_epi64x(14, 15);
4642 let r = _mm_maskz_cvtepi64_epi8(0, a);
4643 assert_eq_m128i(r, _mm_setzero_si128());
4644 let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4645 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4646 assert_eq_m128i(r, e);
4647 }
4648
4649 #[simd_test(enable = "avx512f")]
4650 unsafe fn test_mm512_cvtsepi64_epi32() {
4651 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4652 let r = _mm512_cvtsepi64_epi32(a);
4653 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4654 assert_eq_m256i(r, e);
4655 }
4656
4657 #[simd_test(enable = "avx512f")]
4658 unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4659 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4660 let src = _mm256_set1_epi32(-1);
4661 let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4662 assert_eq_m256i(r, src);
4663 let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4664 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4665 assert_eq_m256i(r, e);
4666 }
4667
4668 #[simd_test(enable = "avx512f")]
4669 unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4670 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4671 let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4672 assert_eq_m256i(r, _mm256_setzero_si256());
4673 let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4674 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4675 assert_eq_m256i(r, e);
4676 }
4677
4678 #[simd_test(enable = "avx512f,avx512vl")]
4679 unsafe fn test_mm256_cvtsepi64_epi32() {
4680 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4681 let r = _mm256_cvtsepi64_epi32(a);
4682 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4683 assert_eq_m128i(r, e);
4684 }
4685
4686 #[simd_test(enable = "avx512f,avx512vl")]
4687 unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4688 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4689 let src = _mm_set1_epi32(-1);
4690 let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4691 assert_eq_m128i(r, src);
4692 let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4693 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4694 assert_eq_m128i(r, e);
4695 }
4696
4697 #[simd_test(enable = "avx512f,avx512vl")]
4698 unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4699 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4700 let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4701 assert_eq_m128i(r, _mm_setzero_si128());
4702 let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4703 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4704 assert_eq_m128i(r, e);
4705 }
4706
4707 #[simd_test(enable = "avx512f,avx512vl")]
4708 unsafe fn test_mm_cvtsepi64_epi32() {
4709 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4710 let r = _mm_cvtsepi64_epi32(a);
4711 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4712 assert_eq_m128i(r, e);
4713 }
4714
4715 #[simd_test(enable = "avx512f,avx512vl")]
4716 unsafe fn test_mm_mask_cvtsepi64_epi32() {
4717 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4718 let src = _mm_set1_epi32(0);
4719 let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4720 assert_eq_m128i(r, src);
4721 let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4722 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4723 assert_eq_m128i(r, e);
4724 }
4725
4726 #[simd_test(enable = "avx512f,avx512vl")]
4727 unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4728 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4729 let r = _mm_maskz_cvtsepi64_epi32(0, a);
4730 assert_eq_m128i(r, _mm_setzero_si128());
4731 let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4732 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4733 assert_eq_m128i(r, e);
4734 }
4735
4736 #[simd_test(enable = "avx512f")]
4737 unsafe fn test_mm512_cvtsepi64_epi16() {
4738 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4739 let r = _mm512_cvtsepi64_epi16(a);
4740 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4741 assert_eq_m128i(r, e);
4742 }
4743
4744 #[simd_test(enable = "avx512f")]
4745 unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4746 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4747 let src = _mm_set1_epi16(-1);
4748 let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4749 assert_eq_m128i(r, src);
4750 let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4751 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4752 assert_eq_m128i(r, e);
4753 }
4754
4755 #[simd_test(enable = "avx512f")]
4756 unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4757 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4758 let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4759 assert_eq_m128i(r, _mm_setzero_si128());
4760 let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4761 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4762 assert_eq_m128i(r, e);
4763 }
4764
4765 #[simd_test(enable = "avx512f,avx512vl")]
4766 unsafe fn test_mm256_cvtsepi64_epi16() {
4767 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4768 let r = _mm256_cvtsepi64_epi16(a);
4769 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4770 assert_eq_m128i(r, e);
4771 }
4772
4773 #[simd_test(enable = "avx512f,avx512vl")]
4774 unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4775 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4776 let src = _mm_set1_epi16(0);
4777 let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4778 assert_eq_m128i(r, src);
4779 let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4780 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4781 assert_eq_m128i(r, e);
4782 }
4783
4784 #[simd_test(enable = "avx512f,avx512vl")]
4785 unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4786 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4787 let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4788 assert_eq_m128i(r, _mm_setzero_si128());
4789 let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4790 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4791 assert_eq_m128i(r, e);
4792 }
4793
4794 #[simd_test(enable = "avx512f,avx512vl")]
4795 unsafe fn test_mm_cvtsepi64_epi16() {
4796 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4797 let r = _mm_cvtsepi64_epi16(a);
4798 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4799 assert_eq_m128i(r, e);
4800 }
4801
4802 #[simd_test(enable = "avx512f,avx512vl")]
4803 unsafe fn test_mm_mask_cvtsepi64_epi16() {
4804 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4805 let src = _mm_set1_epi16(0);
4806 let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4807 assert_eq_m128i(r, src);
4808 let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4809 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4810 assert_eq_m128i(r, e);
4811 }
4812
4813 #[simd_test(enable = "avx512f,avx512vl")]
4814 unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4815 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4816 let r = _mm_maskz_cvtsepi64_epi16(0, a);
4817 assert_eq_m128i(r, _mm_setzero_si128());
4818 let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4819 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4820 assert_eq_m128i(r, e);
4821 }
4822
4823 #[simd_test(enable = "avx512f")]
4824 unsafe fn test_mm512_cvtsepi64_epi8() {
4825 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4826 let r = _mm512_cvtsepi64_epi8(a);
4827 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4828 assert_eq_m128i(r, e);
4829 }
4830
4831 #[simd_test(enable = "avx512f")]
4832 unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4833 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4834 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4835 let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4836 assert_eq_m128i(r, src);
4837 let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4838 #[rustfmt::skip]
4839 let e = _mm_set_epi8(
4840 0, 0, 0, 0,
4841 0, 0, 0, 0,
4842 -1, -1, -1, -1,
4843 4, 5, i8::MIN, i8::MAX,
4844 );
4845 assert_eq_m128i(r, e);
4846 }
4847
4848 #[simd_test(enable = "avx512f")]
4849 unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4850 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4851 let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4852 assert_eq_m128i(r, _mm_setzero_si128());
4853 let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4854 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4855 assert_eq_m128i(r, e);
4856 }
4857
4858 #[simd_test(enable = "avx512f,avx512vl")]
4859 unsafe fn test_mm256_cvtsepi64_epi8() {
4860 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4861 let r = _mm256_cvtsepi64_epi8(a);
4862 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4863 assert_eq_m128i(r, e);
4864 }
4865
4866 #[simd_test(enable = "avx512f,avx512vl")]
4867 unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4868 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4869 let src = _mm_set1_epi8(0);
4870 let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4871 assert_eq_m128i(r, src);
4872 let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4873 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4874 assert_eq_m128i(r, e);
4875 }
4876
4877 #[simd_test(enable = "avx512f,avx512vl")]
4878 unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4879 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4880 let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4881 assert_eq_m128i(r, _mm_setzero_si128());
4882 let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4883 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4884 assert_eq_m128i(r, e);
4885 }
4886
4887 #[simd_test(enable = "avx512f,avx512vl")]
4888 unsafe fn test_mm_cvtsepi64_epi8() {
4889 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4890 let r = _mm_cvtsepi64_epi8(a);
4891 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4892 assert_eq_m128i(r, e);
4893 }
4894
4895 #[simd_test(enable = "avx512f,avx512vl")]
4896 unsafe fn test_mm_mask_cvtsepi64_epi8() {
4897 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4898 let src = _mm_set1_epi8(0);
4899 let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4900 assert_eq_m128i(r, src);
4901 let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4902 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4903 assert_eq_m128i(r, e);
4904 }
4905
4906 #[simd_test(enable = "avx512f,avx512vl")]
4907 unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4908 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4909 let r = _mm_maskz_cvtsepi64_epi8(0, a);
4910 assert_eq_m128i(r, _mm_setzero_si128());
4911 let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4912 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4913 assert_eq_m128i(r, e);
4914 }
4915
4916 #[simd_test(enable = "avx512f")]
4917 unsafe fn test_mm512_cvtusepi64_epi32() {
4918 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4919 let r = _mm512_cvtusepi64_epi32(a);
4920 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4921 assert_eq_m256i(r, e);
4922 }
4923
4924 #[simd_test(enable = "avx512f")]
4925 unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4926 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4927 let src = _mm256_set1_epi32(-1);
4928 let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4929 assert_eq_m256i(r, src);
4930 let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4931 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4932 assert_eq_m256i(r, e);
4933 }
4934
4935 #[simd_test(enable = "avx512f")]
4936 unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4937 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4938 let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4939 assert_eq_m256i(r, _mm256_setzero_si256());
4940 let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4941 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4942 assert_eq_m256i(r, e);
4943 }
4944
4945 #[simd_test(enable = "avx512f,avx512vl")]
4946 unsafe fn test_mm256_cvtusepi64_epi32() {
4947 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4948 let r = _mm256_cvtusepi64_epi32(a);
4949 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4950 assert_eq_m128i(r, e);
4951 }
4952
4953 #[simd_test(enable = "avx512f,avx512vl")]
4954 unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4955 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4956 let src = _mm_set1_epi32(0);
4957 let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4958 assert_eq_m128i(r, src);
4959 let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4960 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4961 assert_eq_m128i(r, e);
4962 }
4963
4964 #[simd_test(enable = "avx512f,avx512vl")]
4965 unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4966 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4967 let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4968 assert_eq_m128i(r, _mm_setzero_si128());
4969 let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4970 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4971 assert_eq_m128i(r, e);
4972 }
4973
4974 #[simd_test(enable = "avx512f,avx512vl")]
4975 unsafe fn test_mm_cvtusepi64_epi32() {
4976 let a = _mm_set_epi64x(6, i64::MAX);
4977 let r = _mm_cvtusepi64_epi32(a);
4978 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4979 assert_eq_m128i(r, e);
4980 }
4981
4982 #[simd_test(enable = "avx512f,avx512vl")]
4983 unsafe fn test_mm_mask_cvtusepi64_epi32() {
4984 let a = _mm_set_epi64x(6, i64::MAX);
4985 let src = _mm_set1_epi32(0);
4986 let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4987 assert_eq_m128i(r, src);
4988 let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4989 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4990 assert_eq_m128i(r, e);
4991 }
4992
4993 #[simd_test(enable = "avx512f,avx512vl")]
4994 unsafe fn test_mm_maskz_cvtusepi64_epi32() {
4995 let a = _mm_set_epi64x(6, i64::MAX);
4996 let r = _mm_maskz_cvtusepi64_epi32(0, a);
4997 assert_eq_m128i(r, _mm_setzero_si128());
4998 let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
4999 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
5000 assert_eq_m128i(r, e);
5001 }
5002
5003 #[simd_test(enable = "avx512f")]
5004 unsafe fn test_mm512_cvtusepi64_epi16() {
5005 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5006 let r = _mm512_cvtusepi64_epi16(a);
5007 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
5008 assert_eq_m128i(r, e);
5009 }
5010
5011 #[simd_test(enable = "avx512f")]
5012 unsafe fn test_mm512_mask_cvtusepi64_epi16() {
5013 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5014 let src = _mm_set1_epi16(-1);
5015 let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
5016 assert_eq_m128i(r, src);
5017 let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
5018 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
5019 assert_eq_m128i(r, e);
5020 }
5021
5022 #[simd_test(enable = "avx512f")]
5023 unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
5024 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5025 let r = _mm512_maskz_cvtusepi64_epi16(0, a);
5026 assert_eq_m128i(r, _mm_setzero_si128());
5027 let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
5028 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
5029 assert_eq_m128i(r, e);
5030 }
5031
5032 #[simd_test(enable = "avx512f,avx512vl")]
5033 unsafe fn test_mm256_cvtusepi64_epi16() {
5034 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5035 let r = _mm256_cvtusepi64_epi16(a);
5036 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5037 assert_eq_m128i(r, e);
5038 }
5039
5040 #[simd_test(enable = "avx512f,avx512vl")]
5041 unsafe fn test_mm256_mask_cvtusepi64_epi16() {
5042 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5043 let src = _mm_set1_epi16(0);
5044 let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
5045 assert_eq_m128i(r, src);
5046 let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
5047 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5048 assert_eq_m128i(r, e);
5049 }
5050
5051 #[simd_test(enable = "avx512f,avx512vl")]
5052 unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
5053 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5054 let r = _mm256_maskz_cvtusepi64_epi16(0, a);
5055 assert_eq_m128i(r, _mm_setzero_si128());
5056 let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
5057 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5058 assert_eq_m128i(r, e);
5059 }
5060
5061 #[simd_test(enable = "avx512f,avx512vl")]
5062 unsafe fn test_mm_cvtusepi64_epi16() {
5063 let a = _mm_set_epi64x(6, i64::MAX);
5064 let r = _mm_cvtusepi64_epi16(a);
5065 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5066 assert_eq_m128i(r, e);
5067 }
5068
5069 #[simd_test(enable = "avx512f,avx512vl")]
5070 unsafe fn test_mm_mask_cvtusepi64_epi16() {
5071 let a = _mm_set_epi64x(6, i64::MAX);
5072 let src = _mm_set1_epi16(0);
5073 let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
5074 assert_eq_m128i(r, src);
5075 let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
5076 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5077 assert_eq_m128i(r, e);
5078 }
5079
5080 #[simd_test(enable = "avx512f,avx512vl")]
5081 unsafe fn test_mm_maskz_cvtusepi64_epi16() {
5082 let a = _mm_set_epi64x(6, i64::MAX);
5083 let r = _mm_maskz_cvtusepi64_epi16(0, a);
5084 assert_eq_m128i(r, _mm_setzero_si128());
5085 let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
5086 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5087 assert_eq_m128i(r, e);
5088 }
5089
5090 #[simd_test(enable = "avx512f")]
5091 unsafe fn test_mm512_cvtusepi64_epi8() {
5092 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5093 let r = _mm512_cvtusepi64_epi8(a);
5094 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
5095 assert_eq_m128i(r, e);
5096 }
5097
5098 #[simd_test(enable = "avx512f")]
5099 unsafe fn test_mm512_mask_cvtusepi64_epi8() {
5100 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5101 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
5102 let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
5103 assert_eq_m128i(r, src);
5104 let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
5105 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
5106 assert_eq_m128i(r, e);
5107 }
5108
5109 #[simd_test(enable = "avx512f")]
5110 unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
5111 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5112 let r = _mm512_maskz_cvtusepi64_epi8(0, a);
5113 assert_eq_m128i(r, _mm_setzero_si128());
5114 let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
5115 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
5116 assert_eq_m128i(r, e);
5117 }
5118
5119 #[simd_test(enable = "avx512f,avx512vl")]
5120 unsafe fn test_mm256_cvtusepi64_epi8() {
5121 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5122 let r = _mm256_cvtusepi64_epi8(a);
5123 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5124 assert_eq_m128i(r, e);
5125 }
5126
5127 #[simd_test(enable = "avx512f,avx512vl")]
5128 unsafe fn test_mm256_mask_cvtusepi64_epi8() {
5129 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5130 let src = _mm_set1_epi8(0);
5131 let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
5132 assert_eq_m128i(r, src);
5133 let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
5134 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5135 assert_eq_m128i(r, e);
5136 }
5137
5138 #[simd_test(enable = "avx512f,avx512vl")]
5139 unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
5140 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5141 let r = _mm256_maskz_cvtusepi64_epi8(0, a);
5142 assert_eq_m128i(r, _mm_setzero_si128());
5143 let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5144 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5145 assert_eq_m128i(r, e);
5146 }
5147
5148 #[simd_test(enable = "avx512f,avx512vl")]
5149 unsafe fn test_mm_cvtusepi64_epi8() {
5150 let a = _mm_set_epi64x(6, i64::MAX);
5151 let r = _mm_cvtusepi64_epi8(a);
5152 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5153 assert_eq_m128i(r, e);
5154 }
5155
5156 #[simd_test(enable = "avx512f,avx512vl")]
5157 unsafe fn test_mm_mask_cvtusepi64_epi8() {
5158 let a = _mm_set_epi64x(6, i64::MAX);
5159 let src = _mm_set1_epi8(0);
5160 let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5161 assert_eq_m128i(r, src);
5162 let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5163 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5164 assert_eq_m128i(r, e);
5165 }
5166
5167 #[simd_test(enable = "avx512f,avx512vl")]
5168 unsafe fn test_mm_maskz_cvtusepi64_epi8() {
5169 let a = _mm_set_epi64x(6, i64::MAX);
5170 let r = _mm_maskz_cvtusepi64_epi8(0, a);
5171 assert_eq_m128i(r, _mm_setzero_si128());
5172 let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5173 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5174 assert_eq_m128i(r, e);
5175 }
5176
5177 #[simd_test(enable = "avx512f")]
5178 unsafe fn test_mm512_cvtt_roundpd_epi32() {
5179 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5180 let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5181 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5182 assert_eq_m256i(r, e);
5183 }
5184
5185 #[simd_test(enable = "avx512f")]
5186 unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5187 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5188 let src = _mm256_set1_epi32(0);
5189 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5190 assert_eq_m256i(r, src);
5191 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5192 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5193 assert_eq_m256i(r, e);
5194 }
5195
5196 #[simd_test(enable = "avx512f")]
5197 unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5198 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5199 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5200 assert_eq_m256i(r, _mm256_setzero_si256());
5201 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5202 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5203 assert_eq_m256i(r, e);
5204 }
5205
5206 #[simd_test(enable = "avx512f")]
5207 unsafe fn test_mm512_cvtt_roundpd_epu32() {
5208 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5209 let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5210 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5211 assert_eq_m256i(r, e);
5212 }
5213
5214 #[simd_test(enable = "avx512f")]
5215 unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5216 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5217 let src = _mm256_set1_epi32(0);
5218 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5219 assert_eq_m256i(r, src);
5220 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5221 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5222 assert_eq_m256i(r, e);
5223 }
5224
5225 #[simd_test(enable = "avx512f")]
5226 unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5227 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5228 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5229 assert_eq_m256i(r, _mm256_setzero_si256());
5230 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5231 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5232 assert_eq_m256i(r, e);
5233 }
5234
5235 #[simd_test(enable = "avx512f")]
5236 unsafe fn test_mm512_cvttpd_epi32() {
5237 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5238 let r = _mm512_cvttpd_epi32(a);
5239 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5240 assert_eq_m256i(r, e);
5241 }
5242
5243 #[simd_test(enable = "avx512f")]
5244 unsafe fn test_mm512_mask_cvttpd_epi32() {
5245 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5246 let src = _mm256_set1_epi32(0);
5247 let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5248 assert_eq_m256i(r, src);
5249 let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5250 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5251 assert_eq_m256i(r, e);
5252 }
5253
5254 #[simd_test(enable = "avx512f")]
5255 unsafe fn test_mm512_maskz_cvttpd_epi32() {
5256 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5257 let r = _mm512_maskz_cvttpd_epi32(0, a);
5258 assert_eq_m256i(r, _mm256_setzero_si256());
5259 let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5260 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5261 assert_eq_m256i(r, e);
5262 }
5263
5264 #[simd_test(enable = "avx512f,avx512vl")]
5265 unsafe fn test_mm256_mask_cvttpd_epi32() {
5266 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5267 let src = _mm_set1_epi32(0);
5268 let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5269 assert_eq_m128i(r, src);
5270 let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5271 let e = _mm_setr_epi32(4, -5, 6, -7);
5272 assert_eq_m128i(r, e);
5273 }
5274
5275 #[simd_test(enable = "avx512f,avx512vl")]
5276 unsafe fn test_mm256_maskz_cvttpd_epi32() {
5277 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5278 let r = _mm256_maskz_cvttpd_epi32(0, a);
5279 assert_eq_m128i(r, _mm_setzero_si128());
5280 let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5281 let e = _mm_setr_epi32(4, -5, 6, -7);
5282 assert_eq_m128i(r, e);
5283 }
5284
5285 #[simd_test(enable = "avx512f,avx512vl")]
5286 unsafe fn test_mm_mask_cvttpd_epi32() {
5287 let a = _mm_set_pd(6., -7.5);
5288 let src = _mm_set1_epi32(0);
5289 let r = _mm_mask_cvttpd_epi32(src, 0, a);
5290 assert_eq_m128i(r, src);
5291 let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5292 let e = _mm_set_epi32(0, 0, 6, -7);
5293 assert_eq_m128i(r, e);
5294 }
5295
5296 #[simd_test(enable = "avx512f,avx512vl")]
5297 unsafe fn test_mm_maskz_cvttpd_epi32() {
5298 let a = _mm_set_pd(6., -7.5);
5299 let r = _mm_maskz_cvttpd_epi32(0, a);
5300 assert_eq_m128i(r, _mm_setzero_si128());
5301 let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5302 let e = _mm_set_epi32(0, 0, 6, -7);
5303 assert_eq_m128i(r, e);
5304 }
5305
5306 #[simd_test(enable = "avx512f")]
5307 unsafe fn test_mm512_cvttpd_epu32() {
5308 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5309 let r = _mm512_cvttpd_epu32(a);
5310 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5311 assert_eq_m256i(r, e);
5312 }
5313
5314 #[simd_test(enable = "avx512f")]
5315 unsafe fn test_mm512_mask_cvttpd_epu32() {
5316 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5317 let src = _mm256_set1_epi32(0);
5318 let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5319 assert_eq_m256i(r, src);
5320 let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5321 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5322 assert_eq_m256i(r, e);
5323 }
5324
5325 #[simd_test(enable = "avx512f")]
5326 unsafe fn test_mm512_maskz_cvttpd_epu32() {
5327 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5328 let r = _mm512_maskz_cvttpd_epu32(0, a);
5329 assert_eq_m256i(r, _mm256_setzero_si256());
5330 let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5331 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5332 assert_eq_m256i(r, e);
5333 }
5334
5335 #[simd_test(enable = "avx512f,avx512vl")]
5336 unsafe fn test_mm256_cvttpd_epu32() {
5337 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5338 let r = _mm256_cvttpd_epu32(a);
5339 let e = _mm_set_epi32(4, 5, 6, 7);
5340 assert_eq_m128i(r, e);
5341 }
5342
5343 #[simd_test(enable = "avx512f,avx512vl")]
5344 unsafe fn test_mm256_mask_cvttpd_epu32() {
5345 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5346 let src = _mm_set1_epi32(0);
5347 let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5348 assert_eq_m128i(r, src);
5349 let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5350 let e = _mm_set_epi32(4, 5, 6, 7);
5351 assert_eq_m128i(r, e);
5352 }
5353
5354 #[simd_test(enable = "avx512f,avx512vl")]
5355 unsafe fn test_mm256_maskz_cvttpd_epu32() {
5356 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5357 let r = _mm256_maskz_cvttpd_epu32(0, a);
5358 assert_eq_m128i(r, _mm_setzero_si128());
5359 let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5360 let e = _mm_set_epi32(4, 5, 6, 7);
5361 assert_eq_m128i(r, e);
5362 }
5363
5364 #[simd_test(enable = "avx512f,avx512vl")]
5365 unsafe fn test_mm_cvttpd_epu32() {
5366 let a = _mm_set_pd(6., 7.5);
5367 let r = _mm_cvttpd_epu32(a);
5368 let e = _mm_set_epi32(0, 0, 6, 7);
5369 assert_eq_m128i(r, e);
5370 }
5371
5372 #[simd_test(enable = "avx512f,avx512vl")]
5373 unsafe fn test_mm_mask_cvttpd_epu32() {
5374 let a = _mm_set_pd(6., 7.5);
5375 let src = _mm_set1_epi32(0);
5376 let r = _mm_mask_cvttpd_epu32(src, 0, a);
5377 assert_eq_m128i(r, src);
5378 let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5379 let e = _mm_set_epi32(0, 0, 6, 7);
5380 assert_eq_m128i(r, e);
5381 }
5382
5383 #[simd_test(enable = "avx512f,avx512vl")]
5384 unsafe fn test_mm_maskz_cvttpd_epu32() {
5385 let a = _mm_set_pd(6., 7.5);
5386 let r = _mm_maskz_cvttpd_epu32(0, a);
5387 assert_eq_m128i(r, _mm_setzero_si128());
5388 let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5389 let e = _mm_set_epi32(0, 0, 6, 7);
5390 assert_eq_m128i(r, e);
5391 }
5392
5393 #[simd_test(enable = "avx512f")]
5394 unsafe fn test_mm512_add_round_pd() {
5395 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5396 let b = _mm512_set1_pd(-1.);
5397 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5398 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5399 assert_eq_m512d(r, e);
5400 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5401 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5402 assert_eq_m512d(r, e);
5403 }
5404
5405 #[simd_test(enable = "avx512f")]
5406 unsafe fn test_mm512_mask_add_round_pd() {
5407 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5408 let b = _mm512_set1_pd(-1.);
5409 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5410 a, 0, a, b,
5411 );
5412 assert_eq_m512d(r, a);
5413 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5414 a, 0b11110000, a, b,
5415 );
5416 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5417 assert_eq_m512d(r, e);
5418 }
5419
5420 #[simd_test(enable = "avx512f")]
5421 unsafe fn test_mm512_maskz_add_round_pd() {
5422 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5423 let b = _mm512_set1_pd(-1.);
5424 let r =
5425 _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5426 assert_eq_m512d(r, _mm512_setzero_pd());
5427 let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5428 0b11110000, a, b,
5429 );
5430 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5431 assert_eq_m512d(r, e);
5432 }
5433
5434 #[simd_test(enable = "avx512f")]
5435 unsafe fn test_mm512_sub_round_pd() {
5436 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5437 let b = _mm512_set1_pd(1.);
5438 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5439 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5440 assert_eq_m512d(r, e);
5441 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5442 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5443 assert_eq_m512d(r, e);
5444 }
5445
5446 #[simd_test(enable = "avx512f")]
5447 unsafe fn test_mm512_mask_sub_round_pd() {
5448 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5449 let b = _mm512_set1_pd(1.);
5450 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5451 a, 0, a, b,
5452 );
5453 assert_eq_m512d(r, a);
5454 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5455 a, 0b11110000, a, b,
5456 );
5457 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5458 assert_eq_m512d(r, e);
5459 }
5460
5461 #[simd_test(enable = "avx512f")]
5462 unsafe fn test_mm512_maskz_sub_round_pd() {
5463 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5464 let b = _mm512_set1_pd(1.);
5465 let r =
5466 _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5467 assert_eq_m512d(r, _mm512_setzero_pd());
5468 let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5469 0b11110000, a, b,
5470 );
5471 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5472 assert_eq_m512d(r, e);
5473 }
5474
5475 #[simd_test(enable = "avx512f")]
5476 unsafe fn test_mm512_mul_round_pd() {
5477 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5478 let b = _mm512_set1_pd(0.1);
5479 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5480 let e = _mm512_setr_pd(
5481 0.8,
5482 0.9500000000000001,
5483 1.,
5484 1.1500000000000001,
5485 1.2000000000000002,
5486 1.35,
5487 1.4000000000000001,
5488 0.,
5489 );
5490 assert_eq_m512d(r, e);
5491 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5492 let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5493 assert_eq_m512d(r, e);
5494 }
5495
5496 #[simd_test(enable = "avx512f")]
5497 unsafe fn test_mm512_mask_mul_round_pd() {
5498 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5499 let b = _mm512_set1_pd(0.1);
5500 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5501 a, 0, a, b,
5502 );
5503 assert_eq_m512d(r, a);
5504 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5505 a, 0b11110000, a, b,
5506 );
5507 let e = _mm512_setr_pd(
5508 8.,
5509 9.5,
5510 10.,
5511 11.5,
5512 1.2000000000000002,
5513 1.35,
5514 1.4000000000000001,
5515 0.,
5516 );
5517 assert_eq_m512d(r, e);
5518 }
5519
5520 #[simd_test(enable = "avx512f")]
5521 unsafe fn test_mm512_maskz_mul_round_pd() {
5522 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5523 let b = _mm512_set1_pd(0.1);
5524 let r =
5525 _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5526 assert_eq_m512d(r, _mm512_setzero_pd());
5527 let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5528 0b11110000, a, b,
5529 );
5530 let e = _mm512_setr_pd(
5531 0.,
5532 0.,
5533 0.,
5534 0.,
5535 1.2000000000000002,
5536 1.35,
5537 1.4000000000000001,
5538 0.,
5539 );
5540 assert_eq_m512d(r, e);
5541 }
5542
5543 #[simd_test(enable = "avx512f")]
5544 unsafe fn test_mm512_div_round_pd() {
5545 let a = _mm512_set1_pd(1.);
5546 let b = _mm512_set1_pd(3.);
5547 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5548 let e = _mm512_set1_pd(0.3333333333333333);
5549 assert_eq_m512d(r, e);
5550 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5551 let e = _mm512_set1_pd(0.3333333333333333);
5552 assert_eq_m512d(r, e);
5553 }
5554
5555 #[simd_test(enable = "avx512f")]
5556 unsafe fn test_mm512_mask_div_round_pd() {
5557 let a = _mm512_set1_pd(1.);
5558 let b = _mm512_set1_pd(3.);
5559 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5560 a, 0, a, b,
5561 );
5562 assert_eq_m512d(r, a);
5563 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5564 a, 0b11110000, a, b,
5565 );
5566 let e = _mm512_setr_pd(
5567 1.,
5568 1.,
5569 1.,
5570 1.,
5571 0.3333333333333333,
5572 0.3333333333333333,
5573 0.3333333333333333,
5574 0.3333333333333333,
5575 );
5576 assert_eq_m512d(r, e);
5577 }
5578
5579 #[simd_test(enable = "avx512f")]
5580 unsafe fn test_mm512_maskz_div_round_pd() {
5581 let a = _mm512_set1_pd(1.);
5582 let b = _mm512_set1_pd(3.);
5583 let r =
5584 _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5585 assert_eq_m512d(r, _mm512_setzero_pd());
5586 let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5587 0b11110000, a, b,
5588 );
5589 let e = _mm512_setr_pd(
5590 0.,
5591 0.,
5592 0.,
5593 0.,
5594 0.3333333333333333,
5595 0.3333333333333333,
5596 0.3333333333333333,
5597 0.3333333333333333,
5598 );
5599 assert_eq_m512d(r, e);
5600 }
5601
5602 #[simd_test(enable = "avx512f")]
5603 unsafe fn test_mm512_sqrt_round_pd() {
5604 let a = _mm512_set1_pd(3.);
5605 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5606 let e = _mm512_set1_pd(1.7320508075688772);
5607 assert_eq_m512d(r, e);
5608 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5609 let e = _mm512_set1_pd(1.7320508075688774);
5610 assert_eq_m512d(r, e);
5611 }
5612
5613 #[simd_test(enable = "avx512f")]
5614 unsafe fn test_mm512_mask_sqrt_round_pd() {
5615 let a = _mm512_set1_pd(3.);
5616 let r =
5617 _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5618 assert_eq_m512d(r, a);
5619 let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5620 a, 0b11110000, a,
5621 );
5622 let e = _mm512_setr_pd(
5623 3.,
5624 3.,
5625 3.,
5626 3.,
5627 1.7320508075688772,
5628 1.7320508075688772,
5629 1.7320508075688772,
5630 1.7320508075688772,
5631 );
5632 assert_eq_m512d(r, e);
5633 }
5634
5635 #[simd_test(enable = "avx512f")]
5636 unsafe fn test_mm512_maskz_sqrt_round_pd() {
5637 let a = _mm512_set1_pd(3.);
5638 let r =
5639 _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5640 assert_eq_m512d(r, _mm512_setzero_pd());
5641 let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5642 0b11110000, a,
5643 );
5644 let e = _mm512_setr_pd(
5645 0.,
5646 0.,
5647 0.,
5648 0.,
5649 1.7320508075688772,
5650 1.7320508075688772,
5651 1.7320508075688772,
5652 1.7320508075688772,
5653 );
5654 assert_eq_m512d(r, e);
5655 }
5656
5657 #[simd_test(enable = "avx512f")]
5658 unsafe fn test_mm512_fmadd_round_pd() {
5659 let a = _mm512_set1_pd(0.000000000000000007);
5660 let b = _mm512_set1_pd(1.);
5661 let c = _mm512_set1_pd(-1.);
5662 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5663 let e = _mm512_set1_pd(-1.);
5664 assert_eq_m512d(r, e);
5665 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5666 let e = _mm512_set1_pd(-0.9999999999999999);
5667 assert_eq_m512d(r, e);
5668 }
5669
5670 #[simd_test(enable = "avx512f")]
5671 unsafe fn test_mm512_mask_fmadd_round_pd() {
5672 let a = _mm512_set1_pd(0.000000000000000007);
5673 let b = _mm512_set1_pd(1.);
5674 let c = _mm512_set1_pd(-1.);
5675 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5676 a, 0, b, c,
5677 );
5678 assert_eq_m512d(r, a);
5679 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5680 a, 0b00001111, b, c,
5681 );
5682 let e = _mm512_setr_pd(
5683 -1.,
5684 -1.,
5685 -1.,
5686 -1.,
5687 0.000000000000000007,
5688 0.000000000000000007,
5689 0.000000000000000007,
5690 0.000000000000000007,
5691 );
5692 assert_eq_m512d(r, e);
5693 }
5694
5695 #[simd_test(enable = "avx512f")]
5696 unsafe fn test_mm512_maskz_fmadd_round_pd() {
5697 let a = _mm512_set1_pd(0.000000000000000007);
5698 let b = _mm512_set1_pd(1.);
5699 let c = _mm512_set1_pd(-1.);
5700 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5701 0, a, b, c,
5702 );
5703 assert_eq_m512d(r, _mm512_setzero_pd());
5704 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5705 0b00001111, a, b, c,
5706 );
5707 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5708 assert_eq_m512d(r, e);
5709 }
5710
5711 #[simd_test(enable = "avx512f")]
5712 unsafe fn test_mm512_mask3_fmadd_round_pd() {
5713 let a = _mm512_set1_pd(0.000000000000000007);
5714 let b = _mm512_set1_pd(1.);
5715 let c = _mm512_set1_pd(-1.);
5716 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5717 a, b, c, 0,
5718 );
5719 assert_eq_m512d(r, c);
5720 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5721 a, b, c, 0b00001111,
5722 );
5723 let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5724 assert_eq_m512d(r, e);
5725 }
5726
5727 #[simd_test(enable = "avx512f")]
5728 unsafe fn test_mm512_fmsub_round_pd() {
5729 let a = _mm512_set1_pd(0.000000000000000007);
5730 let b = _mm512_set1_pd(1.);
5731 let c = _mm512_set1_pd(1.);
5732 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5733 let e = _mm512_set1_pd(-1.);
5734 assert_eq_m512d(r, e);
5735 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5736 let e = _mm512_set1_pd(-0.9999999999999999);
5737 assert_eq_m512d(r, e);
5738 }
5739
5740 #[simd_test(enable = "avx512f")]
5741 unsafe fn test_mm512_mask_fmsub_round_pd() {
5742 let a = _mm512_set1_pd(0.000000000000000007);
5743 let b = _mm512_set1_pd(1.);
5744 let c = _mm512_set1_pd(1.);
5745 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5746 a, 0, b, c,
5747 );
5748 assert_eq_m512d(r, a);
5749 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5750 a, 0b00001111, b, c,
5751 );
5752 let e = _mm512_setr_pd(
5753 -1.,
5754 -1.,
5755 -1.,
5756 -1.,
5757 0.000000000000000007,
5758 0.000000000000000007,
5759 0.000000000000000007,
5760 0.000000000000000007,
5761 );
5762 assert_eq_m512d(r, e);
5763 }
5764
5765 #[simd_test(enable = "avx512f")]
5766 unsafe fn test_mm512_maskz_fmsub_round_pd() {
5767 let a = _mm512_set1_pd(0.000000000000000007);
5768 let b = _mm512_set1_pd(1.);
5769 let c = _mm512_set1_pd(1.);
5770 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5771 0, a, b, c,
5772 );
5773 assert_eq_m512d(r, _mm512_setzero_pd());
5774 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5775 0b00001111, a, b, c,
5776 );
5777 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5778 assert_eq_m512d(r, e);
5779 }
5780
5781 #[simd_test(enable = "avx512f")]
5782 unsafe fn test_mm512_mask3_fmsub_round_pd() {
5783 let a = _mm512_set1_pd(0.000000000000000007);
5784 let b = _mm512_set1_pd(1.);
5785 let c = _mm512_set1_pd(1.);
5786 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5787 a, b, c, 0,
5788 );
5789 assert_eq_m512d(r, c);
5790 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5791 a, b, c, 0b00001111,
5792 );
5793 let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5794 assert_eq_m512d(r, e);
5795 }
5796
5797 #[simd_test(enable = "avx512f")]
5798 unsafe fn test_mm512_fmaddsub_round_pd() {
5799 let a = _mm512_set1_pd(0.000000000000000007);
5800 let b = _mm512_set1_pd(1.);
5801 let c = _mm512_set1_pd(-1.);
5802 let r =
5803 _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5804 let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5805 assert_eq_m512d(r, e);
5806 let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5807 let e = _mm512_setr_pd(
5808 1.,
5809 -0.9999999999999999,
5810 1.,
5811 -0.9999999999999999,
5812 1.,
5813 -0.9999999999999999,
5814 1.,
5815 -0.9999999999999999,
5816 );
5817 assert_eq_m512d(r, e);
5818 }
5819
5820 #[simd_test(enable = "avx512f")]
5821 unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5822 let a = _mm512_set1_pd(0.000000000000000007);
5823 let b = _mm512_set1_pd(1.);
5824 let c = _mm512_set1_pd(-1.);
5825 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5826 a, 0, b, c,
5827 );
5828 assert_eq_m512d(r, a);
5829 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5830 a, 0b00001111, b, c,
5831 );
5832 let e = _mm512_setr_pd(
5833 1.,
5834 -1.,
5835 1.,
5836 -1.,
5837 0.000000000000000007,
5838 0.000000000000000007,
5839 0.000000000000000007,
5840 0.000000000000000007,
5841 );
5842 assert_eq_m512d(r, e);
5843 }
5844
5845 #[simd_test(enable = "avx512f")]
5846 unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5847 let a = _mm512_set1_pd(0.000000000000000007);
5848 let b = _mm512_set1_pd(1.);
5849 let c = _mm512_set1_pd(-1.);
5850 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5851 0, a, b, c,
5852 );
5853 assert_eq_m512d(r, _mm512_setzero_pd());
5854 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5855 0b00001111, a, b, c,
5856 );
5857 let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5858 assert_eq_m512d(r, e);
5859 }
5860
5861 #[simd_test(enable = "avx512f")]
5862 unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5863 let a = _mm512_set1_pd(0.000000000000000007);
5864 let b = _mm512_set1_pd(1.);
5865 let c = _mm512_set1_pd(-1.);
5866 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5867 a, b, c, 0,
5868 );
5869 assert_eq_m512d(r, c);
5870 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5871 a, b, c, 0b00001111,
5872 );
5873 let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5874 assert_eq_m512d(r, e);
5875 }
5876
5877 #[simd_test(enable = "avx512f")]
5878 unsafe fn test_mm512_fmsubadd_round_pd() {
5879 let a = _mm512_set1_pd(0.000000000000000007);
5880 let b = _mm512_set1_pd(1.);
5881 let c = _mm512_set1_pd(-1.);
5882 let r =
5883 _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5884 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5885 assert_eq_m512d(r, e);
5886 let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5887 let e = _mm512_setr_pd(
5888 -0.9999999999999999,
5889 1.,
5890 -0.9999999999999999,
5891 1.,
5892 -0.9999999999999999,
5893 1.,
5894 -0.9999999999999999,
5895 1.,
5896 );
5897 assert_eq_m512d(r, e);
5898 }
5899
5900 #[simd_test(enable = "avx512f")]
5901 unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5902 let a = _mm512_set1_pd(0.000000000000000007);
5903 let b = _mm512_set1_pd(1.);
5904 let c = _mm512_set1_pd(-1.);
5905 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5906 a, 0, b, c,
5907 );
5908 assert_eq_m512d(r, a);
5909 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5910 a, 0b00001111, b, c,
5911 );
5912 let e = _mm512_setr_pd(
5913 -1.,
5914 1.,
5915 -1.,
5916 1.,
5917 0.000000000000000007,
5918 0.000000000000000007,
5919 0.000000000000000007,
5920 0.000000000000000007,
5921 );
5922 assert_eq_m512d(r, e);
5923 }
5924
5925 #[simd_test(enable = "avx512f")]
5926 unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5927 let a = _mm512_set1_pd(0.000000000000000007);
5928 let b = _mm512_set1_pd(1.);
5929 let c = _mm512_set1_pd(-1.);
5930 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5931 0, a, b, c,
5932 );
5933 assert_eq_m512d(r, _mm512_setzero_pd());
5934 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5935 0b00001111, a, b, c,
5936 );
5937 let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5938 assert_eq_m512d(r, e);
5939 }
5940
5941 #[simd_test(enable = "avx512f")]
5942 unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5943 let a = _mm512_set1_pd(0.000000000000000007);
5944 let b = _mm512_set1_pd(1.);
5945 let c = _mm512_set1_pd(-1.);
5946 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5947 a, b, c, 0,
5948 );
5949 assert_eq_m512d(r, c);
5950 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5951 a, b, c, 0b00001111,
5952 );
5953 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5954 assert_eq_m512d(r, e);
5955 }
5956
5957 #[simd_test(enable = "avx512f")]
5958 unsafe fn test_mm512_fnmadd_round_pd() {
5959 let a = _mm512_set1_pd(0.000000000000000007);
5960 let b = _mm512_set1_pd(1.);
5961 let c = _mm512_set1_pd(1.);
5962 let r =
5963 _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5964 let e = _mm512_set1_pd(1.);
5965 assert_eq_m512d(r, e);
5966 let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5967 let e = _mm512_set1_pd(0.9999999999999999);
5968 assert_eq_m512d(r, e);
5969 }
5970
5971 #[simd_test(enable = "avx512f")]
5972 unsafe fn test_mm512_mask_fnmadd_round_pd() {
5973 let a = _mm512_set1_pd(0.000000000000000007);
5974 let b = _mm512_set1_pd(1.);
5975 let c = _mm512_set1_pd(1.);
5976 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5977 a, 0, b, c,
5978 );
5979 assert_eq_m512d(r, a);
5980 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5981 a, 0b00001111, b, c,
5982 );
5983 let e = _mm512_setr_pd(
5984 1.,
5985 1.,
5986 1.,
5987 1.,
5988 0.000000000000000007,
5989 0.000000000000000007,
5990 0.000000000000000007,
5991 0.000000000000000007,
5992 );
5993 assert_eq_m512d(r, e);
5994 }
5995
5996 #[simd_test(enable = "avx512f")]
5997 unsafe fn test_mm512_maskz_fnmadd_round_pd() {
5998 let a = _mm512_set1_pd(0.000000000000000007);
5999 let b = _mm512_set1_pd(1.);
6000 let c = _mm512_set1_pd(1.);
6001 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6002 0, a, b, c,
6003 );
6004 assert_eq_m512d(r, _mm512_setzero_pd());
6005 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6006 0b00001111, a, b, c,
6007 );
6008 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6009 assert_eq_m512d(r, e);
6010 }
6011
6012 #[simd_test(enable = "avx512f")]
6013 unsafe fn test_mm512_mask3_fnmadd_round_pd() {
6014 let a = _mm512_set1_pd(0.000000000000000007);
6015 let b = _mm512_set1_pd(1.);
6016 let c = _mm512_set1_pd(1.);
6017 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6018 a, b, c, 0,
6019 );
6020 assert_eq_m512d(r, c);
6021 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6022 a, b, c, 0b00001111,
6023 );
6024 let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
6025 assert_eq_m512d(r, e);
6026 }
6027
6028 #[simd_test(enable = "avx512f")]
6029 unsafe fn test_mm512_fnmsub_round_pd() {
6030 let a = _mm512_set1_pd(0.000000000000000007);
6031 let b = _mm512_set1_pd(1.);
6032 let c = _mm512_set1_pd(-1.);
6033 let r =
6034 _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
6035 let e = _mm512_set1_pd(1.);
6036 assert_eq_m512d(r, e);
6037 let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
6038 let e = _mm512_set1_pd(0.9999999999999999);
6039 assert_eq_m512d(r, e);
6040 }
6041
6042 #[simd_test(enable = "avx512f")]
6043 unsafe fn test_mm512_mask_fnmsub_round_pd() {
6044 let a = _mm512_set1_pd(0.000000000000000007);
6045 let b = _mm512_set1_pd(1.);
6046 let c = _mm512_set1_pd(-1.);
6047 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6048 a, 0, b, c,
6049 );
6050 assert_eq_m512d(r, a);
6051 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6052 a, 0b00001111, b, c,
6053 );
6054 let e = _mm512_setr_pd(
6055 1.,
6056 1.,
6057 1.,
6058 1.,
6059 0.000000000000000007,
6060 0.000000000000000007,
6061 0.000000000000000007,
6062 0.000000000000000007,
6063 );
6064 assert_eq_m512d(r, e);
6065 }
6066
6067 #[simd_test(enable = "avx512f")]
6068 unsafe fn test_mm512_maskz_fnmsub_round_pd() {
6069 let a = _mm512_set1_pd(0.000000000000000007);
6070 let b = _mm512_set1_pd(1.);
6071 let c = _mm512_set1_pd(-1.);
6072 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6073 0, a, b, c,
6074 );
6075 assert_eq_m512d(r, _mm512_setzero_pd());
6076 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6077 0b00001111, a, b, c,
6078 );
6079 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6080 assert_eq_m512d(r, e);
6081 }
6082
6083 #[simd_test(enable = "avx512f")]
6084 unsafe fn test_mm512_mask3_fnmsub_round_pd() {
6085 let a = _mm512_set1_pd(0.000000000000000007);
6086 let b = _mm512_set1_pd(1.);
6087 let c = _mm512_set1_pd(-1.);
6088 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6089 a, b, c, 0,
6090 );
6091 assert_eq_m512d(r, c);
6092 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6093 a, b, c, 0b00001111,
6094 );
6095 let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
6096 assert_eq_m512d(r, e);
6097 }
6098
6099 #[simd_test(enable = "avx512f")]
6100 unsafe fn test_mm512_max_round_pd() {
6101 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6102 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6103 let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6104 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6105 assert_eq_m512d(r, e);
6106 }
6107
6108 #[simd_test(enable = "avx512f")]
6109 unsafe fn test_mm512_mask_max_round_pd() {
6110 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6111 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6112 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6113 assert_eq_m512d(r, a);
6114 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6115 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6116 assert_eq_m512d(r, e);
6117 }
6118
6119 #[simd_test(enable = "avx512f")]
6120 unsafe fn test_mm512_maskz_max_round_pd() {
6121 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6122 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6123 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6124 assert_eq_m512d(r, _mm512_setzero_pd());
6125 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6126 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
6127 assert_eq_m512d(r, e);
6128 }
6129
6130 #[simd_test(enable = "avx512f")]
6131 unsafe fn test_mm512_min_round_pd() {
6132 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6133 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6134 let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6135 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
6136 assert_eq_m512d(r, e);
6137 }
6138
6139 #[simd_test(enable = "avx512f")]
6140 unsafe fn test_mm512_mask_min_round_pd() {
6141 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6142 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6143 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6144 assert_eq_m512d(r, a);
6145 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6146 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6147 assert_eq_m512d(r, e);
6148 }
6149
6150 #[simd_test(enable = "avx512f")]
6151 unsafe fn test_mm512_maskz_min_round_pd() {
6152 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6153 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6154 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6155 assert_eq_m512d(r, _mm512_setzero_pd());
6156 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6157 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6158 assert_eq_m512d(r, e);
6159 }
6160
6161 #[simd_test(enable = "avx512f")]
6162 unsafe fn test_mm512_getexp_round_pd() {
6163 let a = _mm512_set1_pd(3.);
6164 let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6165 let e = _mm512_set1_pd(1.);
6166 assert_eq_m512d(r, e);
6167 }
6168
6169 #[simd_test(enable = "avx512f")]
6170 unsafe fn test_mm512_mask_getexp_round_pd() {
6171 let a = _mm512_set1_pd(3.);
6172 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6173 assert_eq_m512d(r, a);
6174 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6175 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6176 assert_eq_m512d(r, e);
6177 }
6178
6179 #[simd_test(enable = "avx512f")]
6180 unsafe fn test_mm512_maskz_getexp_round_pd() {
6181 let a = _mm512_set1_pd(3.);
6182 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6183 assert_eq_m512d(r, _mm512_setzero_pd());
6184 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6185 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6186 assert_eq_m512d(r, e);
6187 }
6188
6189 #[simd_test(enable = "avx512f")]
6190 unsafe fn test_mm512_roundscale_round_pd() {
6191 let a = _mm512_set1_pd(1.1);
6192 let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6193 let e = _mm512_set1_pd(1.0);
6194 assert_eq_m512d(r, e);
6195 }
6196
6197 #[simd_test(enable = "avx512f")]
6198 unsafe fn test_mm512_mask_roundscale_round_pd() {
6199 let a = _mm512_set1_pd(1.1);
6200 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6201 let e = _mm512_set1_pd(1.1);
6202 assert_eq_m512d(r, e);
6203 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6204 let e = _mm512_set1_pd(1.0);
6205 assert_eq_m512d(r, e);
6206 }
6207
6208 #[simd_test(enable = "avx512f")]
6209 unsafe fn test_mm512_maskz_roundscale_round_pd() {
6210 let a = _mm512_set1_pd(1.1);
6211 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6212 assert_eq_m512d(r, _mm512_setzero_pd());
6213 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6214 let e = _mm512_set1_pd(1.0);
6215 assert_eq_m512d(r, e);
6216 }
6217
6218 #[simd_test(enable = "avx512f")]
6219 unsafe fn test_mm512_scalef_round_pd() {
6220 let a = _mm512_set1_pd(1.);
6221 let b = _mm512_set1_pd(3.);
6222 let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6223 let e = _mm512_set1_pd(8.);
6224 assert_eq_m512d(r, e);
6225 }
6226
6227 #[simd_test(enable = "avx512f")]
6228 unsafe fn test_mm512_mask_scalef_round_pd() {
6229 let a = _mm512_set1_pd(1.);
6230 let b = _mm512_set1_pd(3.);
6231 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6232 a, 0, a, b,
6233 );
6234 assert_eq_m512d(r, a);
6235 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6236 a, 0b11110000, a, b,
6237 );
6238 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6239 assert_eq_m512d(r, e);
6240 }
6241
6242 #[simd_test(enable = "avx512f")]
6243 unsafe fn test_mm512_maskz_scalef_round_pd() {
6244 let a = _mm512_set1_pd(1.);
6245 let b = _mm512_set1_pd(3.);
6246 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6247 0, a, b,
6248 );
6249 assert_eq_m512d(r, _mm512_setzero_pd());
6250 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6251 0b11110000, a, b,
6252 );
6253 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6254 assert_eq_m512d(r, e);
6255 }
6256
6257 #[simd_test(enable = "avx512f")]
6258 unsafe fn test_mm512_fixupimm_round_pd() {
6259 let a = _mm512_set1_pd(f64::NAN);
6260 let b = _mm512_set1_pd(f64::MAX);
6261 let c = _mm512_set1_epi64(i32::MAX as i64);
6262 let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6263 let e = _mm512_set1_pd(0.0);
6264 assert_eq_m512d(r, e);
6265 }
6266
6267 #[simd_test(enable = "avx512f")]
6268 unsafe fn test_mm512_mask_fixupimm_round_pd() {
6269 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6270 let b = _mm512_set1_pd(f64::MAX);
6271 let c = _mm512_set1_epi64(i32::MAX as i64);
6272 let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6273 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6274 assert_eq_m512d(r, e);
6275 }
6276
6277 #[simd_test(enable = "avx512f")]
6278 unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6279 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6280 let b = _mm512_set1_pd(f64::MAX);
6281 let c = _mm512_set1_epi64(i32::MAX as i64);
6282 let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6283 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6284 assert_eq_m512d(r, e);
6285 }
6286
6287 #[simd_test(enable = "avx512f")]
6288 unsafe fn test_mm512_getmant_round_pd() {
6289 let a = _mm512_set1_pd(10.);
6290 let r = _mm512_getmant_round_pd::<
6291 _MM_MANT_NORM_1_2,
6292 _MM_MANT_SIGN_SRC,
6293 _MM_FROUND_CUR_DIRECTION,
6294 >(a);
6295 let e = _mm512_set1_pd(1.25);
6296 assert_eq_m512d(r, e);
6297 }
6298
6299 #[simd_test(enable = "avx512f")]
6300 unsafe fn test_mm512_mask_getmant_round_pd() {
6301 let a = _mm512_set1_pd(10.);
6302 let r = _mm512_mask_getmant_round_pd::<
6303 _MM_MANT_NORM_1_2,
6304 _MM_MANT_SIGN_SRC,
6305 _MM_FROUND_CUR_DIRECTION,
6306 >(a, 0, a);
6307 assert_eq_m512d(r, a);
6308 let r = _mm512_mask_getmant_round_pd::<
6309 _MM_MANT_NORM_1_2,
6310 _MM_MANT_SIGN_SRC,
6311 _MM_FROUND_CUR_DIRECTION,
6312 >(a, 0b11110000, a);
6313 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6314 assert_eq_m512d(r, e);
6315 }
6316
6317 #[simd_test(enable = "avx512f")]
6318 unsafe fn test_mm512_maskz_getmant_round_pd() {
6319 let a = _mm512_set1_pd(10.);
6320 let r = _mm512_maskz_getmant_round_pd::<
6321 _MM_MANT_NORM_1_2,
6322 _MM_MANT_SIGN_SRC,
6323 _MM_FROUND_CUR_DIRECTION,
6324 >(0, a);
6325 assert_eq_m512d(r, _mm512_setzero_pd());
6326 let r = _mm512_maskz_getmant_round_pd::<
6327 _MM_MANT_NORM_1_2,
6328 _MM_MANT_SIGN_SRC,
6329 _MM_FROUND_CUR_DIRECTION,
6330 >(0b11110000, a);
6331 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6332 assert_eq_m512d(r, e);
6333 }
6334
6335 #[simd_test(enable = "avx512f")]
6336 unsafe fn test_mm512_cvt_roundps_pd() {
6337 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6338 let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6339 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6340 assert_eq_m512d(r, e);
6341 }
6342
6343 #[simd_test(enable = "avx512f")]
6344 unsafe fn test_mm512_mask_cvt_roundps_pd() {
6345 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6346 let src = _mm512_set1_pd(0.);
6347 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6348 assert_eq_m512d(r, src);
6349 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6350 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6351 assert_eq_m512d(r, e);
6352 }
6353
6354 #[simd_test(enable = "avx512f")]
6355 unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6356 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6357 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6358 assert_eq_m512d(r, _mm512_setzero_pd());
6359 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6360 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6361 assert_eq_m512d(r, e);
6362 }
6363
6364 #[simd_test(enable = "avx512f")]
6365 unsafe fn test_mm512_cvt_roundpd_ps() {
6366 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6367 let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6368 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6369 assert_eq_m256(r, e);
6370 }
6371
6372 #[simd_test(enable = "avx512f")]
6373 unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6374 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6375 let src = _mm256_set1_ps(0.);
6376 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6377 assert_eq_m256(r, src);
6378 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6379 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6380 assert_eq_m256(r, e);
6381 }
6382
6383 #[simd_test(enable = "avx512f")]
6384 unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6385 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6386 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6387 assert_eq_m256(r, _mm256_setzero_ps());
6388 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6389 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6390 assert_eq_m256(r, e);
6391 }
6392
6393 #[simd_test(enable = "avx512f")]
6394 unsafe fn test_mm512_cvt_roundpd_epi32() {
6395 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6396 let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6397 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6398 assert_eq_m256i(r, e);
6399 }
6400
6401 #[simd_test(enable = "avx512f")]
6402 unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6403 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6404 let src = _mm256_set1_epi32(0);
6405 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6406 assert_eq_m256i(r, src);
6407 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6408 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6409 assert_eq_m256i(r, e);
6410 }
6411
6412 #[simd_test(enable = "avx512f")]
6413 unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6414 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6415 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6416 assert_eq_m256i(r, _mm256_setzero_si256());
6417 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6418 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6419 assert_eq_m256i(r, e);
6420 }
6421
6422 #[simd_test(enable = "avx512f")]
6423 unsafe fn test_mm512_cvt_roundpd_epu32() {
6424 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6425 let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6426 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6427 assert_eq_m256i(r, e);
6428 }
6429
6430 #[simd_test(enable = "avx512f")]
6431 unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6432 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6433 let src = _mm256_set1_epi32(0);
6434 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6435 assert_eq_m256i(r, src);
6436 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6437 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6438 assert_eq_m256i(r, e);
6439 }
6440
6441 #[simd_test(enable = "avx512f")]
6442 unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6443 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6444 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6445 assert_eq_m256i(r, _mm256_setzero_si256());
6446 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6447 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6448 assert_eq_m256i(r, e);
6449 }
6450
6451 #[simd_test(enable = "avx512f")]
6452 unsafe fn test_mm512_setzero_pd() {
6453 assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6454 }
6455
6456 unsafe fn test_mm512_set1_epi64() {
6457 let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6458 assert_eq_m512i(r, _mm512_set1_epi64(2));
6459 }
6460
6461 #[simd_test(enable = "avx512f")]
6462 unsafe fn test_mm512_set1_pd() {
6463 let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6464 assert_eq_m512d(expected, _mm512_set1_pd(2.));
6465 }
6466
6467 unsafe fn test_mm512_set4_epi64() {
6468 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6469 assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6470 }
6471
6472 #[simd_test(enable = "avx512f")]
6473 unsafe fn test_mm512_set4_pd() {
6474 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6475 assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6476 }
6477
6478 unsafe fn test_mm512_setr4_epi64() {
6479 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6480 assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6481 }
6482
6483 #[simd_test(enable = "avx512f")]
6484 unsafe fn test_mm512_setr4_pd() {
6485 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6486 assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6487 }
6488
6489 #[simd_test(enable = "avx512f")]
6490 unsafe fn test_mm512_cmplt_pd_mask() {
6491 #[rustfmt::skip]
6492 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6493 let b = _mm512_set1_pd(-1.);
6494 let m = _mm512_cmplt_pd_mask(a, b);
6495 assert_eq!(m, 0b00000101);
6496 }
6497
6498 #[simd_test(enable = "avx512f")]
6499 unsafe fn test_mm512_mask_cmplt_pd_mask() {
6500 #[rustfmt::skip]
6501 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6502 let b = _mm512_set1_pd(-1.);
6503 let mask = 0b01100110;
6504 let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6505 assert_eq!(r, 0b00000100);
6506 }
6507
6508 #[simd_test(enable = "avx512f")]
6509 unsafe fn test_mm512_cmpnlt_pd_mask() {
6510 #[rustfmt::skip]
6511 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6512 let b = _mm512_set1_pd(-1.);
6513 assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6514 }
6515
6516 #[simd_test(enable = "avx512f")]
6517 unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6518 #[rustfmt::skip]
6519 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6520 let b = _mm512_set1_pd(-1.);
6521 let mask = 0b01111010;
6522 assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6523 }
6524
6525 #[simd_test(enable = "avx512f")]
6526 unsafe fn test_mm512_cmple_pd_mask() {
6527 #[rustfmt::skip]
6528 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6529 let b = _mm512_set1_pd(-1.);
6530 assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6531 }
6532
6533 #[simd_test(enable = "avx512f")]
6534 unsafe fn test_mm512_mask_cmple_pd_mask() {
6535 #[rustfmt::skip]
6536 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6537 let b = _mm512_set1_pd(-1.);
6538 let mask = 0b01111010;
6539 assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6540 }
6541
6542 #[simd_test(enable = "avx512f")]
6543 unsafe fn test_mm512_cmpnle_pd_mask() {
6544 #[rustfmt::skip]
6545 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6546 let b = _mm512_set1_pd(-1.);
6547 let m = _mm512_cmpnle_pd_mask(b, a);
6548 assert_eq!(m, 0b00001101);
6549 }
6550
6551 #[simd_test(enable = "avx512f")]
6552 unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6553 #[rustfmt::skip]
6554 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6555 let b = _mm512_set1_pd(-1.);
6556 let mask = 0b01100110;
6557 let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6558 assert_eq!(r, 0b00000100);
6559 }
6560
6561 #[simd_test(enable = "avx512f")]
6562 unsafe fn test_mm512_cmpeq_pd_mask() {
6563 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6564 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6565 let m = _mm512_cmpeq_pd_mask(b, a);
6566 assert_eq!(m, 0b11001101);
6567 }
6568
6569 #[simd_test(enable = "avx512f")]
6570 unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6571 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6572 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6573 let mask = 0b01111010;
6574 let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6575 assert_eq!(r, 0b01001000);
6576 }
6577
6578 #[simd_test(enable = "avx512f")]
6579 unsafe fn test_mm512_cmpneq_pd_mask() {
6580 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6581 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6582 let m = _mm512_cmpneq_pd_mask(b, a);
6583 assert_eq!(m, 0b00110010);
6584 }
6585
6586 #[simd_test(enable = "avx512f")]
6587 unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6588 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6589 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6590 let mask = 0b01111010;
6591 let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6592 assert_eq!(r, 0b00110010)
6593 }
6594
6595 #[simd_test(enable = "avx512f")]
6596 unsafe fn test_mm512_cmp_pd_mask() {
6597 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6598 let b = _mm512_set1_pd(-1.);
6599 let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6600 assert_eq!(m, 0b00000101);
6601 }
6602
6603 #[simd_test(enable = "avx512f")]
6604 unsafe fn test_mm512_mask_cmp_pd_mask() {
6605 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6606 let b = _mm512_set1_pd(-1.);
6607 let mask = 0b01100110;
6608 let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6609 assert_eq!(r, 0b00000100);
6610 }
6611
6612 #[simd_test(enable = "avx512f,avx512vl")]
6613 unsafe fn test_mm256_cmp_pd_mask() {
6614 let a = _mm256_set_pd(0., 1., -1., 13.);
6615 let b = _mm256_set1_pd(1.);
6616 let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6617 assert_eq!(m, 0b00001010);
6618 }
6619
6620 #[simd_test(enable = "avx512f,avx512vl")]
6621 unsafe fn test_mm256_mask_cmp_pd_mask() {
6622 let a = _mm256_set_pd(0., 1., -1., 13.);
6623 let b = _mm256_set1_pd(1.);
6624 let mask = 0b11111111;
6625 let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6626 assert_eq!(r, 0b00001010);
6627 }
6628
6629 #[simd_test(enable = "avx512f,avx512vl")]
6630 unsafe fn test_mm_cmp_pd_mask() {
6631 let a = _mm_set_pd(0., 1.);
6632 let b = _mm_set1_pd(1.);
6633 let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6634 assert_eq!(m, 0b00000010);
6635 }
6636
6637 #[simd_test(enable = "avx512f,avx512vl")]
6638 unsafe fn test_mm_mask_cmp_pd_mask() {
6639 let a = _mm_set_pd(0., 1.);
6640 let b = _mm_set1_pd(1.);
6641 let mask = 0b11111111;
6642 let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6643 assert_eq!(r, 0b00000010);
6644 }
6645
6646 #[simd_test(enable = "avx512f")]
6647 unsafe fn test_mm512_cmp_round_pd_mask() {
6648 #[rustfmt::skip]
6649 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6650 let b = _mm512_set1_pd(-1.);
6651 let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6652 assert_eq!(m, 0b00000101);
6653 }
6654
6655 #[simd_test(enable = "avx512f")]
6656 unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6657 #[rustfmt::skip]
6658 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6659 let b = _mm512_set1_pd(-1.);
6660 let mask = 0b01100110;
6661 let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6662 assert_eq!(r, 0b00000100);
6663 }
6664
6665 #[simd_test(enable = "avx512f")]
6666 unsafe fn test_mm512_cmpord_pd_mask() {
6667 #[rustfmt::skip]
6668 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6669 #[rustfmt::skip]
6670 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6671 let m = _mm512_cmpord_pd_mask(a, b);
6672 assert_eq!(m, 0b00000101);
6673 }
6674
6675 #[simd_test(enable = "avx512f")]
6676 unsafe fn test_mm512_mask_cmpord_pd_mask() {
6677 #[rustfmt::skip]
6678 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6679 #[rustfmt::skip]
6680 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6681 let mask = 0b11000011;
6682 let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6683 assert_eq!(m, 0b00000001);
6684 }
6685
6686 #[simd_test(enable = "avx512f")]
6687 unsafe fn test_mm512_cmpunord_pd_mask() {
6688 #[rustfmt::skip]
6689 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6690 #[rustfmt::skip]
6691 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6692 let m = _mm512_cmpunord_pd_mask(a, b);
6693
6694 assert_eq!(m, 0b11111010);
6695 }
6696
6697 #[simd_test(enable = "avx512f")]
6698 unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6699 #[rustfmt::skip]
6700 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6701 #[rustfmt::skip]
6702 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6703 let mask = 0b00001111;
6704 let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6705 assert_eq!(m, 0b000001010);
6706 }
6707
6708 #[simd_test(enable = "avx512f")]
6709 unsafe fn test_mm512_cmplt_epu64_mask() {
6710 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6711 let b = _mm512_set1_epi64(-1);
6712 let m = _mm512_cmplt_epu64_mask(a, b);
6713 assert_eq!(m, 0b11001111);
6714 }
6715
6716 #[simd_test(enable = "avx512f")]
6717 unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6718 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6719 let b = _mm512_set1_epi64(-1);
6720 let mask = 0b01111010;
6721 let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6722 assert_eq!(r, 0b01001010);
6723 }
6724
6725 #[simd_test(enable = "avx512f,avx512vl")]
6726 unsafe fn test_mm256_cmplt_epu64_mask() {
6727 let a = _mm256_set_epi64x(0, 1, 2, 100);
6728 let b = _mm256_set1_epi64x(2);
6729 let r = _mm256_cmplt_epu64_mask(a, b);
6730 assert_eq!(r, 0b00001100);
6731 }
6732
6733 #[simd_test(enable = "avx512f,avx512vl")]
6734 unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6735 let a = _mm256_set_epi64x(0, 1, 2, 100);
6736 let b = _mm256_set1_epi64x(2);
6737 let mask = 0b11111111;
6738 let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6739 assert_eq!(r, 0b00001100);
6740 }
6741
6742 #[simd_test(enable = "avx512f,avx512vl")]
6743 unsafe fn test_mm_cmplt_epu64_mask() {
6744 let a = _mm_set_epi64x(0, 1);
6745 let b = _mm_set1_epi64x(2);
6746 let r = _mm_cmplt_epu64_mask(a, b);
6747 assert_eq!(r, 0b00000011);
6748 }
6749
6750 #[simd_test(enable = "avx512f,avx512vl")]
6751 unsafe fn test_mm_mask_cmplt_epu64_mask() {
6752 let a = _mm_set_epi64x(0, 1);
6753 let b = _mm_set1_epi64x(2);
6754 let mask = 0b11111111;
6755 let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6756 assert_eq!(r, 0b00000011);
6757 }
6758
6759 #[simd_test(enable = "avx512f")]
6760 unsafe fn test_mm512_cmpgt_epu64_mask() {
6761 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6762 let b = _mm512_set1_epi64(-1);
6763 let m = _mm512_cmpgt_epu64_mask(b, a);
6764 assert_eq!(m, 0b11001111);
6765 }
6766
6767 #[simd_test(enable = "avx512f")]
6768 unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6769 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6770 let b = _mm512_set1_epi64(-1);
6771 let mask = 0b01111010;
6772 let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6773 assert_eq!(r, 0b01001010);
6774 }
6775
6776 #[simd_test(enable = "avx512f,avx512vl")]
6777 unsafe fn test_mm256_cmpgt_epu64_mask() {
6778 let a = _mm256_set_epi64x(0, 1, 2, 3);
6779 let b = _mm256_set1_epi64x(1);
6780 let r = _mm256_cmpgt_epu64_mask(a, b);
6781 assert_eq!(r, 0b00000011);
6782 }
6783
6784 #[simd_test(enable = "avx512f,avx512vl")]
6785 unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6786 let a = _mm256_set_epi64x(0, 1, 2, 3);
6787 let b = _mm256_set1_epi64x(1);
6788 let mask = 0b11111111;
6789 let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6790 assert_eq!(r, 0b00000011);
6791 }
6792
6793 #[simd_test(enable = "avx512f,avx512vl")]
6794 unsafe fn test_mm_cmpgt_epu64_mask() {
6795 let a = _mm_set_epi64x(1, 2);
6796 let b = _mm_set1_epi64x(1);
6797 let r = _mm_cmpgt_epu64_mask(a, b);
6798 assert_eq!(r, 0b00000001);
6799 }
6800
6801 #[simd_test(enable = "avx512f,avx512vl")]
6802 unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6803 let a = _mm_set_epi64x(1, 2);
6804 let b = _mm_set1_epi64x(1);
6805 let mask = 0b11111111;
6806 let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6807 assert_eq!(r, 0b00000001);
6808 }
6809
6810 #[simd_test(enable = "avx512f")]
6811 unsafe fn test_mm512_cmple_epu64_mask() {
6812 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6813 let b = _mm512_set1_epi64(-1);
6814 assert_eq!(
6815 _mm512_cmple_epu64_mask(a, b),
6816 !_mm512_cmpgt_epu64_mask(a, b)
6817 )
6818 }
6819
6820 #[simd_test(enable = "avx512f")]
6821 unsafe fn test_mm512_mask_cmple_epu64_mask() {
6822 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6823 let b = _mm512_set1_epi64(-1);
6824 let mask = 0b01111010;
6825 assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6826 }
6827
6828 #[simd_test(enable = "avx512f,avx512vl")]
6829 unsafe fn test_mm256_cmple_epu64_mask() {
6830 let a = _mm256_set_epi64x(0, 1, 2, 1);
6831 let b = _mm256_set1_epi64x(1);
6832 let r = _mm256_cmple_epu64_mask(a, b);
6833 assert_eq!(r, 0b00001101)
6834 }
6835
6836 #[simd_test(enable = "avx512f,avx512vl")]
6837 unsafe fn test_mm256_mask_cmple_epu64_mask() {
6838 let a = _mm256_set_epi64x(0, 1, 2, 1);
6839 let b = _mm256_set1_epi64x(1);
6840 let mask = 0b11111111;
6841 let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6842 assert_eq!(r, 0b00001101)
6843 }
6844
6845 #[simd_test(enable = "avx512f,avx512vl")]
6846 unsafe fn test_mm_cmple_epu64_mask() {
6847 let a = _mm_set_epi64x(0, 1);
6848 let b = _mm_set1_epi64x(1);
6849 let r = _mm_cmple_epu64_mask(a, b);
6850 assert_eq!(r, 0b00000011)
6851 }
6852
6853 #[simd_test(enable = "avx512f,avx512vl")]
6854 unsafe fn test_mm_mask_cmple_epu64_mask() {
6855 let a = _mm_set_epi64x(0, 1);
6856 let b = _mm_set1_epi64x(1);
6857 let mask = 0b11111111;
6858 let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6859 assert_eq!(r, 0b00000011)
6860 }
6861
6862 #[simd_test(enable = "avx512f")]
6863 unsafe fn test_mm512_cmpge_epu64_mask() {
6864 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6865 let b = _mm512_set1_epi64(-1);
6866 assert_eq!(
6867 _mm512_cmpge_epu64_mask(a, b),
6868 !_mm512_cmplt_epu64_mask(a, b)
6869 );
6870 }
6871
6872 #[simd_test(enable = "avx512f")]
6873 unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6874 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6875 let b = _mm512_set1_epi64(-1);
6876 let mask = 0b11111111;
6877 let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6878 assert_eq!(r, 0b00110000);
6879 }
6880
6881 #[simd_test(enable = "avx512f,avx512vl")]
6882 unsafe fn test_mm256_cmpge_epu64_mask() {
6883 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6884 let b = _mm256_set1_epi64x(1);
6885 let r = _mm256_cmpge_epu64_mask(a, b);
6886 assert_eq!(r, 0b00000111);
6887 }
6888
6889 #[simd_test(enable = "avx512f,avx512vl")]
6890 unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6891 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6892 let b = _mm256_set1_epi64x(1);
6893 let mask = 0b11111111;
6894 let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6895 assert_eq!(r, 0b00000111);
6896 }
6897
6898 #[simd_test(enable = "avx512f,avx512vl")]
6899 unsafe fn test_mm_cmpge_epu64_mask() {
6900 let a = _mm_set_epi64x(0, 1);
6901 let b = _mm_set1_epi64x(1);
6902 let r = _mm_cmpge_epu64_mask(a, b);
6903 assert_eq!(r, 0b00000001);
6904 }
6905
6906 #[simd_test(enable = "avx512f,avx512vl")]
6907 unsafe fn test_mm_mask_cmpge_epu64_mask() {
6908 let a = _mm_set_epi64x(0, 1);
6909 let b = _mm_set1_epi64x(1);
6910 let mask = 0b11111111;
6911 let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6912 assert_eq!(r, 0b00000001);
6913 }
6914
6915 #[simd_test(enable = "avx512f")]
6916 unsafe fn test_mm512_cmpeq_epu64_mask() {
6917 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6918 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6919 let m = _mm512_cmpeq_epu64_mask(b, a);
6920 assert_eq!(m, 0b11001111);
6921 }
6922
6923 #[simd_test(enable = "avx512f")]
6924 unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6925 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6926 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6927 let mask = 0b01111010;
6928 let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6929 assert_eq!(r, 0b01001010);
6930 }
6931
6932 #[simd_test(enable = "avx512f,avx512vl")]
6933 unsafe fn test_mm256_cmpeq_epu64_mask() {
6934 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6935 let b = _mm256_set_epi64x(0, 1, 13, 42);
6936 let m = _mm256_cmpeq_epu64_mask(b, a);
6937 assert_eq!(m, 0b00001100);
6938 }
6939
6940 #[simd_test(enable = "avx512f,avx512vl")]
6941 unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6942 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6943 let b = _mm256_set_epi64x(0, 1, 13, 42);
6944 let mask = 0b11111111;
6945 let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6946 assert_eq!(r, 0b00001100);
6947 }
6948
6949 #[simd_test(enable = "avx512f,avx512vl")]
6950 unsafe fn test_mm_cmpeq_epu64_mask() {
6951 let a = _mm_set_epi64x(0, 1);
6952 let b = _mm_set_epi64x(0, 1);
6953 let m = _mm_cmpeq_epu64_mask(b, a);
6954 assert_eq!(m, 0b00000011);
6955 }
6956
6957 #[simd_test(enable = "avx512f,avx512vl")]
6958 unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6959 let a = _mm_set_epi64x(0, 1);
6960 let b = _mm_set_epi64x(0, 1);
6961 let mask = 0b11111111;
6962 let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6963 assert_eq!(r, 0b00000011);
6964 }
6965
6966 #[simd_test(enable = "avx512f")]
6967 unsafe fn test_mm512_cmpneq_epu64_mask() {
6968 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6969 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6970 let m = _mm512_cmpneq_epu64_mask(b, a);
6971 assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6972 }
6973
6974 #[simd_test(enable = "avx512f")]
6975 unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6976 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6977 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6978 let mask = 0b01111010;
6979 let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6980 assert_eq!(r, 0b00110010);
6981 }
6982
6983 #[simd_test(enable = "avx512f,avx512vl")]
6984 unsafe fn test_mm256_cmpneq_epu64_mask() {
6985 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6986 let b = _mm256_set_epi64x(0, 1, 13, 42);
6987 let r = _mm256_cmpneq_epu64_mask(b, a);
6988 assert_eq!(r, 0b00000011);
6989 }
6990
6991 #[simd_test(enable = "avx512f,avx512vl")]
6992 unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
6993 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6994 let b = _mm256_set_epi64x(0, 1, 13, 42);
6995 let mask = 0b11111111;
6996 let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
6997 assert_eq!(r, 0b00000011);
6998 }
6999
7000 #[simd_test(enable = "avx512f,avx512vl")]
7001 unsafe fn test_mm_cmpneq_epu64_mask() {
7002 let a = _mm_set_epi64x(-1, u64::MAX as i64);
7003 let b = _mm_set_epi64x(13, 42);
7004 let r = _mm_cmpneq_epu64_mask(b, a);
7005 assert_eq!(r, 0b00000011);
7006 }
7007
7008 #[simd_test(enable = "avx512f,avx512vl")]
7009 unsafe fn test_mm_mask_cmpneq_epu64_mask() {
7010 let a = _mm_set_epi64x(-1, u64::MAX as i64);
7011 let b = _mm_set_epi64x(13, 42);
7012 let mask = 0b11111111;
7013 let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
7014 assert_eq!(r, 0b00000011);
7015 }
7016
7017 #[simd_test(enable = "avx512f")]
7018 unsafe fn test_mm512_cmp_epu64_mask() {
7019 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7020 let b = _mm512_set1_epi64(-1);
7021 let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7022 assert_eq!(m, 0b11001111);
7023 }
7024
7025 #[simd_test(enable = "avx512f")]
7026 unsafe fn test_mm512_mask_cmp_epu64_mask() {
7027 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7028 let b = _mm512_set1_epi64(-1);
7029 let mask = 0b01111010;
7030 let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7031 assert_eq!(r, 0b01001010);
7032 }
7033
7034 #[simd_test(enable = "avx512f,avx512vl")]
7035 unsafe fn test_mm256_cmp_epu64_mask() {
7036 let a = _mm256_set_epi64x(0, 1, -1, 100);
7037 let b = _mm256_set1_epi64x(1);
7038 let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7039 assert_eq!(m, 0b00001000);
7040 }
7041
7042 #[simd_test(enable = "avx512f,avx512vl")]
7043 unsafe fn test_mm256_mask_cmp_epu64_mask() {
7044 let a = _mm256_set_epi64x(0, 1, -1, 100);
7045 let b = _mm256_set1_epi64x(1);
7046 let mask = 0b11111111;
7047 let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7048 assert_eq!(r, 0b00001000);
7049 }
7050
7051 #[simd_test(enable = "avx512f,avx512vl")]
7052 unsafe fn test_mm_cmp_epu64_mask() {
7053 let a = _mm_set_epi64x(0, 1);
7054 let b = _mm_set1_epi64x(1);
7055 let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7056 assert_eq!(m, 0b00000010);
7057 }
7058
7059 #[simd_test(enable = "avx512f,avx512vl")]
7060 unsafe fn test_mm_mask_cmp_epu64_mask() {
7061 let a = _mm_set_epi64x(0, 1);
7062 let b = _mm_set1_epi64x(1);
7063 let mask = 0b11111111;
7064 let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7065 assert_eq!(r, 0b00000010);
7066 }
7067
7068 #[simd_test(enable = "avx512f")]
7069 unsafe fn test_mm512_cmplt_epi64_mask() {
7070 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7071 let b = _mm512_set1_epi64(-1);
7072 let m = _mm512_cmplt_epi64_mask(a, b);
7073 assert_eq!(m, 0b00000101);
7074 }
7075
7076 #[simd_test(enable = "avx512f")]
7077 unsafe fn test_mm512_mask_cmplt_epi64_mask() {
7078 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7079 let b = _mm512_set1_epi64(-1);
7080 let mask = 0b01100110;
7081 let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
7082 assert_eq!(r, 0b00000100);
7083 }
7084
7085 #[simd_test(enable = "avx512f,avx512vl")]
7086 unsafe fn test_mm256_cmplt_epi64_mask() {
7087 let a = _mm256_set_epi64x(0, 1, -1, -13);
7088 let b = _mm256_set1_epi64x(-1);
7089 let r = _mm256_cmplt_epi64_mask(a, b);
7090 assert_eq!(r, 0b00000001);
7091 }
7092
7093 #[simd_test(enable = "avx512f,avx512vl")]
7094 unsafe fn test_mm256_mask_cmplt_epi64_mask() {
7095 let a = _mm256_set_epi64x(0, 1, -1, -13);
7096 let b = _mm256_set1_epi64x(-1);
7097 let mask = 0b11111111;
7098 let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
7099 assert_eq!(r, 0b00000001);
7100 }
7101
7102 #[simd_test(enable = "avx512f,avx512vl")]
7103 unsafe fn test_mm_cmplt_epi64_mask() {
7104 let a = _mm_set_epi64x(-1, -13);
7105 let b = _mm_set1_epi64x(-1);
7106 let r = _mm_cmplt_epi64_mask(a, b);
7107 assert_eq!(r, 0b00000001);
7108 }
7109
7110 #[simd_test(enable = "avx512f,avx512vl")]
7111 unsafe fn test_mm_mask_cmplt_epi64_mask() {
7112 let a = _mm_set_epi64x(-1, -13);
7113 let b = _mm_set1_epi64x(-1);
7114 let mask = 0b11111111;
7115 let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
7116 assert_eq!(r, 0b00000001);
7117 }
7118
7119 #[simd_test(enable = "avx512f")]
7120 unsafe fn test_mm512_cmpgt_epi64_mask() {
7121 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7122 let b = _mm512_set1_epi64(-1);
7123 let m = _mm512_cmpgt_epi64_mask(b, a);
7124 assert_eq!(m, 0b00000101);
7125 }
7126
7127 #[simd_test(enable = "avx512f")]
7128 unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
7129 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7130 let b = _mm512_set1_epi64(-1);
7131 let mask = 0b01100110;
7132 let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
7133 assert_eq!(r, 0b00000100);
7134 }
7135
7136 #[simd_test(enable = "avx512f,avx512vl")]
7137 unsafe fn test_mm256_cmpgt_epi64_mask() {
7138 let a = _mm256_set_epi64x(0, 1, -1, 13);
7139 let b = _mm256_set1_epi64x(-1);
7140 let r = _mm256_cmpgt_epi64_mask(a, b);
7141 assert_eq!(r, 0b00001101);
7142 }
7143
7144 #[simd_test(enable = "avx512f,avx512vl")]
7145 unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
7146 let a = _mm256_set_epi64x(0, 1, -1, 13);
7147 let b = _mm256_set1_epi64x(-1);
7148 let mask = 0b11111111;
7149 let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7150 assert_eq!(r, 0b00001101);
7151 }
7152
7153 #[simd_test(enable = "avx512f,avx512vl")]
7154 unsafe fn test_mm_cmpgt_epi64_mask() {
7155 let a = _mm_set_epi64x(0, -1);
7156 let b = _mm_set1_epi64x(-1);
7157 let r = _mm_cmpgt_epi64_mask(a, b);
7158 assert_eq!(r, 0b00000010);
7159 }
7160
7161 #[simd_test(enable = "avx512f,avx512vl")]
7162 unsafe fn test_mm_mask_cmpgt_epi64_mask() {
7163 let a = _mm_set_epi64x(0, -1);
7164 let b = _mm_set1_epi64x(-1);
7165 let mask = 0b11111111;
7166 let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7167 assert_eq!(r, 0b00000010);
7168 }
7169
7170 #[simd_test(enable = "avx512f")]
7171 unsafe fn test_mm512_cmple_epi64_mask() {
7172 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7173 let b = _mm512_set1_epi64(-1);
7174 assert_eq!(
7175 _mm512_cmple_epi64_mask(a, b),
7176 !_mm512_cmpgt_epi64_mask(a, b)
7177 )
7178 }
7179
7180 #[simd_test(enable = "avx512f")]
7181 unsafe fn test_mm512_mask_cmple_epi64_mask() {
7182 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7183 let b = _mm512_set1_epi64(-1);
7184 let mask = 0b01111010;
7185 assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7186 }
7187
7188 #[simd_test(enable = "avx512f,avx512vl")]
7189 unsafe fn test_mm256_cmple_epi64_mask() {
7190 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7191 let b = _mm256_set1_epi64x(-1);
7192 let r = _mm256_cmple_epi64_mask(a, b);
7193 assert_eq!(r, 0b00000010)
7194 }
7195
7196 #[simd_test(enable = "avx512f,avx512vl")]
7197 unsafe fn test_mm256_mask_cmple_epi64_mask() {
7198 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7199 let b = _mm256_set1_epi64x(-1);
7200 let mask = 0b11111111;
7201 let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7202 assert_eq!(r, 0b00000010)
7203 }
7204
7205 #[simd_test(enable = "avx512f,avx512vl")]
7206 unsafe fn test_mm_cmple_epi64_mask() {
7207 let a = _mm_set_epi64x(0, 1);
7208 let b = _mm_set1_epi64x(1);
7209 let r = _mm_cmple_epi64_mask(a, b);
7210 assert_eq!(r, 0b00000011)
7211 }
7212
7213 #[simd_test(enable = "avx512f,avx512vl")]
7214 unsafe fn test_mm_mask_cmple_epi64_mask() {
7215 let a = _mm_set_epi64x(0, 1);
7216 let b = _mm_set1_epi64x(1);
7217 let mask = 0b11111111;
7218 let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7219 assert_eq!(r, 0b00000011)
7220 }
7221
7222 #[simd_test(enable = "avx512f")]
7223 unsafe fn test_mm512_cmpge_epi64_mask() {
7224 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7225 let b = _mm512_set1_epi64(-1);
7226 assert_eq!(
7227 _mm512_cmpge_epi64_mask(a, b),
7228 !_mm512_cmplt_epi64_mask(a, b)
7229 )
7230 }
7231
7232 #[simd_test(enable = "avx512f")]
7233 unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7234 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7235 let b = _mm512_set1_epi64(-1);
7236 let mask = 0b11111111;
7237 let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7238 assert_eq!(r, 0b11111010);
7239 }
7240
7241 #[simd_test(enable = "avx512f,avx512vl")]
7242 unsafe fn test_mm256_cmpge_epi64_mask() {
7243 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7244 let b = _mm256_set1_epi64x(-1);
7245 let r = _mm256_cmpge_epi64_mask(a, b);
7246 assert_eq!(r, 0b00001111);
7247 }
7248
7249 #[simd_test(enable = "avx512f,avx512vl")]
7250 unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7251 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7252 let b = _mm256_set1_epi64x(-1);
7253 let mask = 0b11111111;
7254 let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7255 assert_eq!(r, 0b00001111);
7256 }
7257
7258 #[simd_test(enable = "avx512f,avx512vl")]
7259 unsafe fn test_mm_cmpge_epi64_mask() {
7260 let a = _mm_set_epi64x(0, 1);
7261 let b = _mm_set1_epi64x(-1);
7262 let r = _mm_cmpge_epi64_mask(a, b);
7263 assert_eq!(r, 0b00000011);
7264 }
7265
7266 #[simd_test(enable = "avx512f,avx512vl")]
7267 unsafe fn test_mm_mask_cmpge_epi64_mask() {
7268 let a = _mm_set_epi64x(0, 1);
7269 let b = _mm_set1_epi64x(-1);
7270 let mask = 0b11111111;
7271 let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7272 assert_eq!(r, 0b00000011);
7273 }
7274
7275 #[simd_test(enable = "avx512f")]
7276 unsafe fn test_mm512_cmpeq_epi64_mask() {
7277 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7278 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7279 let m = _mm512_cmpeq_epi64_mask(b, a);
7280 assert_eq!(m, 0b11001111);
7281 }
7282
7283 #[simd_test(enable = "avx512f")]
7284 unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7285 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7286 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7287 let mask = 0b01111010;
7288 let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7289 assert_eq!(r, 0b01001010);
7290 }
7291
7292 #[simd_test(enable = "avx512f,avx512vl")]
7293 unsafe fn test_mm256_cmpeq_epi64_mask() {
7294 let a = _mm256_set_epi64x(0, 1, -1, 13);
7295 let b = _mm256_set_epi64x(0, 1, 13, 42);
7296 let m = _mm256_cmpeq_epi64_mask(b, a);
7297 assert_eq!(m, 0b00001100);
7298 }
7299
7300 #[simd_test(enable = "avx512f,avx512vl")]
7301 unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7302 let a = _mm256_set_epi64x(0, 1, -1, 13);
7303 let b = _mm256_set_epi64x(0, 1, 13, 42);
7304 let mask = 0b11111111;
7305 let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7306 assert_eq!(r, 0b00001100);
7307 }
7308
7309 #[simd_test(enable = "avx512f,avx512vl")]
7310 unsafe fn test_mm_cmpeq_epi64_mask() {
7311 let a = _mm_set_epi64x(0, 1);
7312 let b = _mm_set_epi64x(0, 1);
7313 let m = _mm_cmpeq_epi64_mask(b, a);
7314 assert_eq!(m, 0b00000011);
7315 }
7316
7317 #[simd_test(enable = "avx512f,avx512vl")]
7318 unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7319 let a = _mm_set_epi64x(0, 1);
7320 let b = _mm_set_epi64x(0, 1);
7321 let mask = 0b11111111;
7322 let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7323 assert_eq!(r, 0b00000011);
7324 }
7325
7326 #[simd_test(enable = "avx512f")]
7327 unsafe fn test_mm512_set_epi64() {
7328 let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7329 assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7330 }
7331
7332 #[simd_test(enable = "avx512f")]
7333 unsafe fn test_mm512_setr_epi64() {
7334 let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7335 assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7336 }
7337
7338 unsafe fn test_mm512_cmpneq_epi64_mask() {
7339 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7340 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7341 let m = _mm512_cmpneq_epi64_mask(b, a);
7342 assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7343 }
7344
7345 #[simd_test(enable = "avx512f")]
7346 unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7347 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7348 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7349 let mask = 0b01111010;
7350 let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7351 assert_eq!(r, 0b00110010)
7352 }
7353
7354 #[simd_test(enable = "avx512f,avx512vl")]
7355 unsafe fn test_mm256_cmpneq_epi64_mask() {
7356 let a = _mm256_set_epi64x(0, 1, -1, 13);
7357 let b = _mm256_set_epi64x(0, 1, 13, 42);
7358 let r = _mm256_cmpneq_epi64_mask(b, a);
7359 assert_eq!(r, 0b00000011)
7360 }
7361
7362 #[simd_test(enable = "avx512f,avx512vl")]
7363 unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7364 let a = _mm256_set_epi64x(0, 1, -1, 13);
7365 let b = _mm256_set_epi64x(0, 1, 13, 42);
7366 let mask = 0b11111111;
7367 let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7368 assert_eq!(r, 0b00000011)
7369 }
7370
7371 #[simd_test(enable = "avx512f,avx512vl")]
7372 unsafe fn test_mm_cmpneq_epi64_mask() {
7373 let a = _mm_set_epi64x(-1, 13);
7374 let b = _mm_set_epi64x(13, 42);
7375 let r = _mm_cmpneq_epi64_mask(b, a);
7376 assert_eq!(r, 0b00000011)
7377 }
7378
7379 #[simd_test(enable = "avx512f,avx512vl")]
7380 unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7381 let a = _mm_set_epi64x(-1, 13);
7382 let b = _mm_set_epi64x(13, 42);
7383 let mask = 0b11111111;
7384 let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7385 assert_eq!(r, 0b00000011)
7386 }
7387
7388 #[simd_test(enable = "avx512f")]
7389 unsafe fn test_mm512_cmp_epi64_mask() {
7390 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7391 let b = _mm512_set1_epi64(-1);
7392 let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7393 assert_eq!(m, 0b00000101);
7394 }
7395
7396 #[simd_test(enable = "avx512f")]
7397 unsafe fn test_mm512_mask_cmp_epi64_mask() {
7398 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7399 let b = _mm512_set1_epi64(-1);
7400 let mask = 0b01100110;
7401 let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7402 assert_eq!(r, 0b00000100);
7403 }
7404
7405 #[simd_test(enable = "avx512f,avx512vl")]
7406 unsafe fn test_mm256_cmp_epi64_mask() {
7407 let a = _mm256_set_epi64x(0, 1, -1, 13);
7408 let b = _mm256_set1_epi64x(1);
7409 let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7410 assert_eq!(m, 0b00001010);
7411 }
7412
7413 #[simd_test(enable = "avx512f,avx512vl")]
7414 unsafe fn test_mm256_mask_cmp_epi64_mask() {
7415 let a = _mm256_set_epi64x(0, 1, -1, 13);
7416 let b = _mm256_set1_epi64x(1);
7417 let mask = 0b11111111;
7418 let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7419 assert_eq!(r, 0b00001010);
7420 }
7421
7422 #[simd_test(enable = "avx512f,avx512vl")]
7423 unsafe fn test_mm_cmp_epi64_mask() {
7424 let a = _mm_set_epi64x(0, 1);
7425 let b = _mm_set1_epi64x(1);
7426 let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7427 assert_eq!(m, 0b00000010);
7428 }
7429
7430 #[simd_test(enable = "avx512f,avx512vl")]
7431 unsafe fn test_mm_mask_cmp_epi64_mask() {
7432 let a = _mm_set_epi64x(0, 1);
7433 let b = _mm_set1_epi64x(1);
7434 let mask = 0b11111111;
7435 let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7436 assert_eq!(r, 0b00000010);
7437 }
7438
7439 #[simd_test(enable = "avx512f")]
7440 unsafe fn test_mm512_i32gather_pd() {
7441 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7442 // A multiplier of 8 is word-addressing
7443 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7444 let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr() as *const u8);
7445 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7446 }
7447
7448 #[simd_test(enable = "avx512f")]
7449 unsafe fn test_mm512_mask_i32gather_pd() {
7450 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7451 let src = _mm512_set1_pd(2.);
7452 let mask = 0b10101010;
7453 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7454 // A multiplier of 8 is word-addressing
7455 let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7456 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7457 }
7458
7459 #[simd_test(enable = "avx512f")]
7460 unsafe fn test_mm512_i64gather_pd() {
7461 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7462 // A multiplier of 8 is word-addressing
7463 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7464 let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr() as *const u8);
7465 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7466 }
7467
7468 #[simd_test(enable = "avx512f")]
7469 unsafe fn test_mm512_mask_i64gather_pd() {
7470 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7471 let src = _mm512_set1_pd(2.);
7472 let mask = 0b10101010;
7473 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7474 // A multiplier of 8 is word-addressing
7475 let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7476 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7477 }
7478
7479 #[simd_test(enable = "avx512f")]
7480 unsafe fn test_mm512_i64gather_ps() {
7481 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7482 // A multiplier of 4 is word-addressing
7483 #[rustfmt::skip]
7484 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7485 let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr() as *const u8);
7486 assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7487 }
7488
7489 #[simd_test(enable = "avx512f")]
7490 unsafe fn test_mm512_mask_i64gather_ps() {
7491 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7492 let src = _mm256_set1_ps(2.);
7493 let mask = 0b10101010;
7494 #[rustfmt::skip]
7495 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7496 // A multiplier of 4 is word-addressing
7497 let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr() as *const u8);
7498 assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7499 }
7500
7501 #[simd_test(enable = "avx512f")]
7502 unsafe fn test_mm512_i32gather_epi64() {
7503 let mut arr = [0i64; 128];
7504 for i in 0..128i64 {
7505 arr[i as usize] = i;
7506 }
7507 // A multiplier of 8 is word-addressing
7508 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7509 let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7510 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7511 }
7512
7513 #[simd_test(enable = "avx512f")]
7514 unsafe fn test_mm512_mask_i32gather_epi64() {
7515 let mut arr = [0i64; 128];
7516 for i in 0..128i64 {
7517 arr[i as usize] = i;
7518 }
7519 let src = _mm512_set1_epi64(2);
7520 let mask = 0b10101010;
7521 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7522 // A multiplier of 8 is word-addressing
7523 let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7524 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7525 }
7526
7527 #[simd_test(enable = "avx512f")]
7528 unsafe fn test_mm512_i64gather_epi64() {
7529 let mut arr = [0i64; 128];
7530 for i in 0..128i64 {
7531 arr[i as usize] = i;
7532 }
7533 // A multiplier of 8 is word-addressing
7534 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7535 let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7536 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7537 }
7538
7539 #[simd_test(enable = "avx512f")]
7540 unsafe fn test_mm512_mask_i64gather_epi64() {
7541 let mut arr = [0i64; 128];
7542 for i in 0..128i64 {
7543 arr[i as usize] = i;
7544 }
7545 let src = _mm512_set1_epi64(2);
7546 let mask = 0b10101010;
7547 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7548 // A multiplier of 8 is word-addressing
7549 let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7550 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7551 }
7552
7553 #[simd_test(enable = "avx512f")]
7554 unsafe fn test_mm512_i64gather_epi32() {
7555 let mut arr = [0i64; 128];
7556 for i in 0..128i64 {
7557 arr[i as usize] = i;
7558 }
7559 // A multiplier of 8 is word-addressing
7560 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7561 let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const u8);
7562 assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7563 }
7564
7565 #[simd_test(enable = "avx512f")]
7566 unsafe fn test_mm512_mask_i64gather_epi32() {
7567 let mut arr = [0i64; 128];
7568 for i in 0..128i64 {
7569 arr[i as usize] = i;
7570 }
7571 let src = _mm256_set1_epi32(2);
7572 let mask = 0b10101010;
7573 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7574 // A multiplier of 8 is word-addressing
7575 let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const u8);
7576 assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7577 }
7578
7579 #[simd_test(enable = "avx512f")]
7580 unsafe fn test_mm512_i32scatter_pd() {
7581 let mut arr = [0f64; 128];
7582 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7583 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7584 // A multiplier of 8 is word-addressing
7585 _mm512_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7586 let mut expected = [0f64; 128];
7587 for i in 0..8 {
7588 expected[i * 16] = (i + 1) as f64;
7589 }
7590 assert_eq!(&arr[..], &expected[..],);
7591 }
7592
7593 #[simd_test(enable = "avx512f")]
7594 unsafe fn test_mm512_mask_i32scatter_pd() {
7595 let mut arr = [0f64; 128];
7596 let mask = 0b10101010;
7597 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7598 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7599 // A multiplier of 8 is word-addressing
7600 _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7601 let mut expected = [0f64; 128];
7602 for i in 0..4 {
7603 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7604 }
7605 assert_eq!(&arr[..], &expected[..],);
7606 }
7607
7608 #[simd_test(enable = "avx512f")]
7609 unsafe fn test_mm512_i64scatter_pd() {
7610 let mut arr = [0f64; 128];
7611 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7612 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7613 // A multiplier of 8 is word-addressing
7614 _mm512_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7615 let mut expected = [0f64; 128];
7616 for i in 0..8 {
7617 expected[i * 16] = (i + 1) as f64;
7618 }
7619 assert_eq!(&arr[..], &expected[..],);
7620 }
7621
7622 #[simd_test(enable = "avx512f")]
7623 unsafe fn test_mm512_mask_i64scatter_pd() {
7624 let mut arr = [0f64; 128];
7625 let mask = 0b10101010;
7626 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7627 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7628 // A multiplier of 8 is word-addressing
7629 _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7630 let mut expected = [0f64; 128];
7631 for i in 0..4 {
7632 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7633 }
7634 assert_eq!(&arr[..], &expected[..],);
7635 }
7636
7637 #[simd_test(enable = "avx512f")]
7638 unsafe fn test_mm512_i64scatter_ps() {
7639 let mut arr = [0f32; 128];
7640 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7641 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7642 // A multiplier of 4 is word-addressing
7643 _mm512_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7644 let mut expected = [0f32; 128];
7645 for i in 0..8 {
7646 expected[i * 16] = (i + 1) as f32;
7647 }
7648 assert_eq!(&arr[..], &expected[..],);
7649 }
7650
7651 #[simd_test(enable = "avx512f")]
7652 unsafe fn test_mm512_mask_i64scatter_ps() {
7653 let mut arr = [0f32; 128];
7654 let mask = 0b10101010;
7655 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7656 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7657 // A multiplier of 4 is word-addressing
7658 _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7659 let mut expected = [0f32; 128];
7660 for i in 0..4 {
7661 expected[i * 32 + 16] = 2. * (i + 1) as f32;
7662 }
7663 assert_eq!(&arr[..], &expected[..],);
7664 }
7665
7666 #[simd_test(enable = "avx512f")]
7667 unsafe fn test_mm512_i32scatter_epi64() {
7668 let mut arr = [0i64; 128];
7669 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7670 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7671 // A multiplier of 8 is word-addressing
7672 _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7673 let mut expected = [0i64; 128];
7674 for i in 0..8 {
7675 expected[i * 16] = (i + 1) as i64;
7676 }
7677 assert_eq!(&arr[..], &expected[..],);
7678 }
7679
7680 #[simd_test(enable = "avx512f")]
7681 unsafe fn test_mm512_mask_i32scatter_epi64() {
7682 let mut arr = [0i64; 128];
7683 let mask = 0b10101010;
7684 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7685 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7686 // A multiplier of 8 is word-addressing
7687 _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7688 let mut expected = [0i64; 128];
7689 for i in 0..4 {
7690 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7691 }
7692 assert_eq!(&arr[..], &expected[..],);
7693 }
7694
7695 #[simd_test(enable = "avx512f")]
7696 unsafe fn test_mm512_i64scatter_epi64() {
7697 let mut arr = [0i64; 128];
7698 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7699 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7700 // A multiplier of 8 is word-addressing
7701 _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7702 let mut expected = [0i64; 128];
7703 for i in 0..8 {
7704 expected[i * 16] = (i + 1) as i64;
7705 }
7706 assert_eq!(&arr[..], &expected[..],);
7707 }
7708
7709 #[simd_test(enable = "avx512f")]
7710 unsafe fn test_mm512_mask_i64scatter_epi64() {
7711 let mut arr = [0i64; 128];
7712 let mask = 0b10101010;
7713 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7714 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7715 // A multiplier of 8 is word-addressing
7716 _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7717 let mut expected = [0i64; 128];
7718 for i in 0..4 {
7719 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7720 }
7721 assert_eq!(&arr[..], &expected[..],);
7722 }
7723
7724 #[simd_test(enable = "avx512f")]
7725 unsafe fn test_mm512_i64scatter_epi32() {
7726 let mut arr = [0i32; 128];
7727 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7728 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7729 // A multiplier of 4 is word-addressing
7730 _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7731 let mut expected = [0i32; 128];
7732 for i in 0..8 {
7733 expected[i * 16] = (i + 1) as i32;
7734 }
7735 assert_eq!(&arr[..], &expected[..],);
7736 }
7737
7738 #[simd_test(enable = "avx512f")]
7739 unsafe fn test_mm512_mask_i64scatter_epi32() {
7740 let mut arr = [0i32; 128];
7741 let mask = 0b10101010;
7742 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7743 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7744 // A multiplier of 4 is word-addressing
7745 _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7746 let mut expected = [0i32; 128];
7747 for i in 0..4 {
7748 expected[i * 32 + 16] = 2 * (i + 1) as i32;
7749 }
7750 assert_eq!(&arr[..], &expected[..],);
7751 }
7752
7753 #[simd_test(enable = "avx512f")]
7754 unsafe fn test_mm512_i32logather_epi64() {
7755 let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7756 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7757 let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr().cast());
7758 let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7759 assert_eq_m512i(expected, r);
7760 }
7761
7762 #[simd_test(enable = "avx512f")]
7763 unsafe fn test_mm512_mask_i32logather_epi64() {
7764 let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7765 let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
7766 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7767 let r =
7768 _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7769 let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
7770 assert_eq_m512i(expected, r);
7771 }
7772
7773 #[simd_test(enable = "avx512f")]
7774 unsafe fn test_mm512_i32logather_pd() {
7775 let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7776 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7777 let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr().cast());
7778 let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7779 assert_eq_m512d(expected, r);
7780 }
7781
7782 #[simd_test(enable = "avx512f")]
7783 unsafe fn test_mm512_mask_i32logather_pd() {
7784 let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7785 let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
7786 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7787 let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7788 let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
7789 assert_eq_m512d(expected, r);
7790 }
7791
7792 #[simd_test(enable = "avx512f")]
7793 unsafe fn test_mm512_i32loscatter_epi64() {
7794 let mut base_addr: [i64; 8] = [0; 8];
7795 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7796 let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7797 _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
7798 let expected = [1, 2, 3, 4, 5, 6, 7, 8];
7799 assert_eq!(expected, base_addr);
7800 }
7801
7802 #[simd_test(enable = "avx512f")]
7803 unsafe fn test_mm512_mask_i32loscatter_epi64() {
7804 let mut base_addr: [i64; 8] = [0; 8];
7805 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7806 let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7807 _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
7808 let expected = [0, 2, 0, 4, 0, 6, 0, 8];
7809 assert_eq!(expected, base_addr);
7810 }
7811
7812 #[simd_test(enable = "avx512f")]
7813 unsafe fn test_mm512_i32loscatter_pd() {
7814 let mut base_addr: [f64; 8] = [0.; 8];
7815 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7816 let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7817 _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
7818 let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
7819 assert_eq!(expected, base_addr);
7820 }
7821
7822 #[simd_test(enable = "avx512f")]
7823 unsafe fn test_mm512_mask_i32loscatter_pd() {
7824 let mut base_addr: [f64; 8] = [0.; 8];
7825 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7826 let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7827 _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
7828 let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
7829 assert_eq!(expected, base_addr);
7830 }
7831
7832 #[simd_test(enable = "avx512f,avx512vl")]
7833 unsafe fn test_mm_mmask_i32gather_epi32() {
7834 let base_addr: [i32; 4] = [1, 2, 3, 4];
7835 let src = _mm_setr_epi32(5, 6, 7, 8);
7836 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7837 let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7838 let expected = _mm_setr_epi32(2, 6, 4, 8);
7839 assert_eq_m128i(expected, r);
7840 }
7841
7842 #[simd_test(enable = "avx512f,avx512vl")]
7843 unsafe fn test_mm_mmask_i32gather_epi64() {
7844 let base_addr: [i64; 2] = [1, 2];
7845 let src = _mm_setr_epi64x(5, 6);
7846 let vindex = _mm_setr_epi32(1, 0, -1, -1);
7847 let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7848 let expected = _mm_setr_epi64x(2, 6);
7849 assert_eq_m128i(expected, r);
7850 }
7851
7852 #[simd_test(enable = "avx512f,avx512vl")]
7853 unsafe fn test_mm_mmask_i32gather_pd() {
7854 let base_addr: [f64; 2] = [1., 2.];
7855 let src = _mm_setr_pd(5., 6.);
7856 let vindex = _mm_setr_epi32(1, 0, -1, -1);
7857 let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7858 let expected = _mm_setr_pd(2., 6.);
7859 assert_eq_m128d(expected, r);
7860 }
7861
7862 #[simd_test(enable = "avx512f,avx512vl")]
7863 unsafe fn test_mm_mmask_i32gather_ps() {
7864 let base_addr: [f32; 4] = [1., 2., 3., 4.];
7865 let src = _mm_setr_ps(5., 6., 7., 8.);
7866 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7867 let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7868 let expected = _mm_setr_ps(2., 6., 4., 8.);
7869 assert_eq_m128(expected, r);
7870 }
7871
7872 #[simd_test(enable = "avx512f,avx512vl")]
7873 unsafe fn test_mm_mmask_i64gather_epi32() {
7874 let base_addr: [i32; 2] = [1, 2];
7875 let src = _mm_setr_epi32(5, 6, 7, 8);
7876 let vindex = _mm_setr_epi64x(1, 0);
7877 let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr().cast());
7878 let expected = _mm_setr_epi32(2, 6, 0, 0);
7879 assert_eq_m128i(expected, r);
7880 }
7881
7882 #[simd_test(enable = "avx512f,avx512vl")]
7883 unsafe fn test_mm_mmask_i64gather_epi64() {
7884 let base_addr: [i64; 2] = [1, 2];
7885 let src = _mm_setr_epi64x(5, 6);
7886 let vindex = _mm_setr_epi64x(1, 0);
7887 let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7888 let expected = _mm_setr_epi64x(2, 6);
7889 assert_eq_m128i(expected, r);
7890 }
7891
7892 #[simd_test(enable = "avx512f,avx512vl")]
7893 unsafe fn test_mm_mmask_i64gather_pd() {
7894 let base_addr: [f64; 2] = [1., 2.];
7895 let src = _mm_setr_pd(5., 6.);
7896 let vindex = _mm_setr_epi64x(1, 0);
7897 let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7898 let expected = _mm_setr_pd(2., 6.);
7899 assert_eq_m128d(expected, r);
7900 }
7901
7902 #[simd_test(enable = "avx512f,avx512vl")]
7903 unsafe fn test_mm_mmask_i64gather_ps() {
7904 let base_addr: [f32; 2] = [1., 2.];
7905 let src = _mm_setr_ps(5., 6., 7., 8.);
7906 let vindex = _mm_setr_epi64x(1, 0);
7907 let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr().cast());
7908 let expected = _mm_setr_ps(2., 6., 0., 0.);
7909 assert_eq_m128(expected, r);
7910 }
7911
7912 #[simd_test(enable = "avx512f,avx512vl")]
7913 unsafe fn test_mm256_mmask_i32gather_epi32() {
7914 let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7915 let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
7916 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7917 let r =
7918 _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7919 let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
7920 assert_eq_m256i(expected, r);
7921 }
7922
7923 #[simd_test(enable = "avx512f,avx512vl")]
7924 unsafe fn test_mm256_mmask_i32gather_epi64() {
7925 let base_addr: [i64; 4] = [1, 2, 3, 4];
7926 let src = _mm256_setr_epi64x(9, 10, 11, 12);
7927 let vindex = _mm_setr_epi32(1, 2, 3, 4);
7928 let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7929 let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7930 assert_eq_m256i(expected, r);
7931 }
7932
7933 #[simd_test(enable = "avx512f,avx512vl")]
7934 unsafe fn test_mm256_mmask_i32gather_pd() {
7935 let base_addr: [f64; 4] = [1., 2., 3., 4.];
7936 let src = _mm256_setr_pd(9., 10., 11., 12.);
7937 let vindex = _mm_setr_epi32(1, 2, 3, 4);
7938 let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7939 let expected = _mm256_setr_pd(2., 10., 4., 12.);
7940 assert_eq_m256d(expected, r);
7941 }
7942
7943 #[simd_test(enable = "avx512f,avx512vl")]
7944 unsafe fn test_mm256_mmask_i32gather_ps() {
7945 let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7946 let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
7947 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7948 let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7949 let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
7950 assert_eq_m256(expected, r);
7951 }
7952
7953 #[simd_test(enable = "avx512f,avx512vl")]
7954 unsafe fn test_mm256_mmask_i64gather_epi32() {
7955 let base_addr: [i32; 4] = [1, 2, 3, 4];
7956 let src = _mm_setr_epi32(9, 10, 11, 12);
7957 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7958 let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7959 let expected = _mm_setr_epi32(2, 10, 4, 12);
7960 assert_eq_m128i(expected, r);
7961 }
7962
7963 #[simd_test(enable = "avx512f,avx512vl")]
7964 unsafe fn test_mm256_mmask_i64gather_epi64() {
7965 let base_addr: [i64; 4] = [1, 2, 3, 4];
7966 let src = _mm256_setr_epi64x(9, 10, 11, 12);
7967 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7968 let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7969 let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7970 assert_eq_m256i(expected, r);
7971 }
7972
7973 #[simd_test(enable = "avx512f,avx512vl")]
7974 unsafe fn test_mm256_mmask_i64gather_pd() {
7975 let base_addr: [f64; 4] = [1., 2., 3., 4.];
7976 let src = _mm256_setr_pd(9., 10., 11., 12.);
7977 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7978 let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7979 let expected = _mm256_setr_pd(2., 10., 4., 12.);
7980 assert_eq_m256d(expected, r);
7981 }
7982
7983 #[simd_test(enable = "avx512f,avx512vl")]
7984 unsafe fn test_mm256_mmask_i64gather_ps() {
7985 let base_addr: [f32; 4] = [1., 2., 3., 4.];
7986 let src = _mm_setr_ps(9., 10., 11., 12.);
7987 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7988 let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7989 let expected = _mm_setr_ps(2., 10., 4., 12.);
7990 assert_eq_m128(expected, r);
7991 }
7992
7993 #[simd_test(enable = "avx512f,avx512vl")]
7994 unsafe fn test_mm_i32scatter_epi32() {
7995 let mut base_addr: [i32; 4] = [0; 4];
7996 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7997 let src = _mm_setr_epi32(2, 3, 4, 1);
7998 _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
7999 let expected = [1, 2, 3, 4];
8000 assert_eq!(expected, base_addr);
8001 }
8002
8003 #[simd_test(enable = "avx512f,avx512vl")]
8004 unsafe fn test_mm_mask_i32scatter_epi32() {
8005 let mut base_addr: [i32; 4] = [0; 4];
8006 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8007 let src = _mm_setr_epi32(2, 3, 4, 1);
8008 _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8009 let expected = [0, 2, 0, 4];
8010 assert_eq!(expected, base_addr);
8011 }
8012
8013 #[simd_test(enable = "avx512f,avx512vl")]
8014 unsafe fn test_mm_i32scatter_epi64() {
8015 let mut base_addr: [i64; 2] = [0; 2];
8016 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8017 let src = _mm_setr_epi64x(2, 1);
8018 _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8019 let expected = [1, 2];
8020 assert_eq!(expected, base_addr);
8021 }
8022
8023 #[simd_test(enable = "avx512f,avx512vl")]
8024 unsafe fn test_mm_mask_i32scatter_epi64() {
8025 let mut base_addr: [i64; 2] = [0; 2];
8026 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8027 let src = _mm_setr_epi64x(2, 1);
8028 _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8029 let expected = [0, 2];
8030 assert_eq!(expected, base_addr);
8031 }
8032
8033 #[simd_test(enable = "avx512f,avx512vl")]
8034 unsafe fn test_mm_i32scatter_pd() {
8035 let mut base_addr: [f64; 2] = [0.; 2];
8036 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8037 let src = _mm_setr_pd(2., 1.);
8038 _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8039 let expected = [1., 2.];
8040 assert_eq!(expected, base_addr);
8041 }
8042
8043 #[simd_test(enable = "avx512f,avx512vl")]
8044 unsafe fn test_mm_mask_i32scatter_pd() {
8045 let mut base_addr: [f64; 2] = [0.; 2];
8046 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8047 let src = _mm_setr_pd(2., 1.);
8048 _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8049 let expected = [0., 2.];
8050 assert_eq!(expected, base_addr);
8051 }
8052
8053 #[simd_test(enable = "avx512f,avx512vl")]
8054 unsafe fn test_mm_i32scatter_ps() {
8055 let mut base_addr: [f32; 4] = [0.; 4];
8056 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8057 let src = _mm_setr_ps(2., 3., 4., 1.);
8058 _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8059 let expected = [1., 2., 3., 4.];
8060 assert_eq!(expected, base_addr);
8061 }
8062
8063 #[simd_test(enable = "avx512f,avx512vl")]
8064 unsafe fn test_mm_mask_i32scatter_ps() {
8065 let mut base_addr: [f32; 4] = [0.; 4];
8066 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8067 let src = _mm_setr_ps(2., 3., 4., 1.);
8068 _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8069 let expected = [0., 2., 0., 4.];
8070 assert_eq!(expected, base_addr);
8071 }
8072
8073 #[simd_test(enable = "avx512f,avx512vl")]
8074 unsafe fn test_mm_i64scatter_epi32() {
8075 let mut base_addr: [i32; 2] = [0; 2];
8076 let vindex = _mm_setr_epi64x(1, 0);
8077 let src = _mm_setr_epi32(2, 1, -1, -1);
8078 _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8079 let expected = [1, 2];
8080 assert_eq!(expected, base_addr);
8081 }
8082
8083 #[simd_test(enable = "avx512f,avx512vl")]
8084 unsafe fn test_mm_mask_i64scatter_epi32() {
8085 let mut base_addr: [i32; 2] = [0; 2];
8086 let vindex = _mm_setr_epi64x(1, 0);
8087 let src = _mm_setr_epi32(2, 1, -1, -1);
8088 _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8089 let expected = [0, 2];
8090 assert_eq!(expected, base_addr);
8091 }
8092
8093 #[simd_test(enable = "avx512f,avx512vl")]
8094 unsafe fn test_mm_i64scatter_epi64() {
8095 let mut base_addr: [i64; 2] = [0; 2];
8096 let vindex = _mm_setr_epi64x(1, 0);
8097 let src = _mm_setr_epi64x(2, 1);
8098 _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8099 let expected = [1, 2];
8100 assert_eq!(expected, base_addr);
8101 }
8102
8103 #[simd_test(enable = "avx512f,avx512vl")]
8104 unsafe fn test_mm_mask_i64scatter_epi64() {
8105 let mut base_addr: [i64; 2] = [0; 2];
8106 let vindex = _mm_setr_epi64x(1, 0);
8107 let src = _mm_setr_epi64x(2, 1);
8108 _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8109 let expected = [0, 2];
8110 assert_eq!(expected, base_addr);
8111 }
8112
8113 #[simd_test(enable = "avx512f,avx512vl")]
8114 unsafe fn test_mm_i64scatter_pd() {
8115 let mut base_addr: [f64; 2] = [0.; 2];
8116 let vindex = _mm_setr_epi64x(1, 0);
8117 let src = _mm_setr_pd(2., 1.);
8118 _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8119 let expected = [1., 2.];
8120 assert_eq!(expected, base_addr);
8121 }
8122
8123 #[simd_test(enable = "avx512f,avx512vl")]
8124 unsafe fn test_mm_mask_i64scatter_pd() {
8125 let mut base_addr: [f64; 2] = [0.; 2];
8126 let vindex = _mm_setr_epi64x(1, 0);
8127 let src = _mm_setr_pd(2., 1.);
8128 _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8129 let expected = [0., 2.];
8130 assert_eq!(expected, base_addr);
8131 }
8132
8133 #[simd_test(enable = "avx512f,avx512vl")]
8134 unsafe fn test_mm_i64scatter_ps() {
8135 let mut base_addr: [f32; 2] = [0.; 2];
8136 let vindex = _mm_setr_epi64x(1, 0);
8137 let src = _mm_setr_ps(2., 1., -1., -1.);
8138 _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8139 let expected = [1., 2.];
8140 assert_eq!(expected, base_addr);
8141 }
8142
8143 #[simd_test(enable = "avx512f,avx512vl")]
8144 unsafe fn test_mm_mask_i64scatter_ps() {
8145 let mut base_addr: [f32; 2] = [0.; 2];
8146 let vindex = _mm_setr_epi64x(1, 0);
8147 let src = _mm_setr_ps(2., 1., -1., -1.);
8148 _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8149 let expected = [0., 2.];
8150 assert_eq!(expected, base_addr);
8151 }
8152
8153 #[simd_test(enable = "avx512f,avx512vl")]
8154 unsafe fn test_mm256_i32scatter_epi32() {
8155 let mut base_addr: [i32; 8] = [0; 8];
8156 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8157 let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8158 _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8159 let expected = [1, 2, 3, 4, 5, 6, 7, 8];
8160 assert_eq!(expected, base_addr);
8161 }
8162
8163 #[simd_test(enable = "avx512f,avx512vl")]
8164 unsafe fn test_mm256_mask_i32scatter_epi32() {
8165 let mut base_addr: [i32; 8] = [0; 8];
8166 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8167 let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8168 _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
8169 let expected = [0, 2, 0, 4, 0, 6, 0, 8];
8170 assert_eq!(expected, base_addr);
8171 }
8172
8173 #[simd_test(enable = "avx512f,avx512vl")]
8174 unsafe fn test_mm256_i32scatter_epi64() {
8175 let mut base_addr: [i64; 4] = [0; 4];
8176 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8177 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8178 _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8179 let expected = [1, 2, 3, 4];
8180 assert_eq!(expected, base_addr);
8181 }
8182
8183 #[simd_test(enable = "avx512f,avx512vl")]
8184 unsafe fn test_mm256_mask_i32scatter_epi64() {
8185 let mut base_addr: [i64; 4] = [0; 4];
8186 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8187 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8188 _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8189 let expected = [0, 2, 0, 4];
8190 assert_eq!(expected, base_addr);
8191 }
8192
8193 #[simd_test(enable = "avx512f,avx512vl")]
8194 unsafe fn test_mm256_i32scatter_pd() {
8195 let mut base_addr: [f64; 4] = [0.; 4];
8196 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8197 let src = _mm256_setr_pd(2., 3., 4., 1.);
8198 _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8199 let expected = [1., 2., 3., 4.];
8200 assert_eq!(expected, base_addr);
8201 }
8202
8203 #[simd_test(enable = "avx512f,avx512vl")]
8204 unsafe fn test_mm256_mask_i32scatter_pd() {
8205 let mut base_addr: [f64; 4] = [0.; 4];
8206 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8207 let src = _mm256_setr_pd(2., 3., 4., 1.);
8208 _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8209 let expected = [0., 2., 0., 4.];
8210 assert_eq!(expected, base_addr);
8211 }
8212
8213 #[simd_test(enable = "avx512f,avx512vl")]
8214 unsafe fn test_mm256_i32scatter_ps() {
8215 let mut base_addr: [f32; 8] = [0.; 8];
8216 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8217 let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8218 _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8219 let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
8220 assert_eq!(expected, base_addr);
8221 }
8222
8223 #[simd_test(enable = "avx512f,avx512vl")]
8224 unsafe fn test_mm256_mask_i32scatter_ps() {
8225 let mut base_addr: [f32; 8] = [0.; 8];
8226 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8227 let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8228 _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
8229 let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
8230 assert_eq!(expected, base_addr);
8231 }
8232
8233 #[simd_test(enable = "avx512f,avx512vl")]
8234 unsafe fn test_mm256_i64scatter_epi32() {
8235 let mut base_addr: [i32; 4] = [0; 4];
8236 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8237 let src = _mm_setr_epi32(2, 3, 4, 1);
8238 _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8239 let expected = [1, 2, 3, 4];
8240 assert_eq!(expected, base_addr);
8241 }
8242
8243 #[simd_test(enable = "avx512f,avx512vl")]
8244 unsafe fn test_mm256_mask_i64scatter_epi32() {
8245 let mut base_addr: [i32; 4] = [0; 4];
8246 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8247 let src = _mm_setr_epi32(2, 3, 4, 1);
8248 _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8249 let expected = [0, 2, 0, 4];
8250 assert_eq!(expected, base_addr);
8251 }
8252
8253 #[simd_test(enable = "avx512f,avx512vl")]
8254 unsafe fn test_mm256_i64scatter_epi64() {
8255 let mut base_addr: [i64; 4] = [0; 4];
8256 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8257 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8258 _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8259 let expected = [1, 2, 3, 4];
8260 assert_eq!(expected, base_addr);
8261 }
8262
8263 #[simd_test(enable = "avx512f,avx512vl")]
8264 unsafe fn test_mm256_mask_i64scatter_epi64() {
8265 let mut base_addr: [i64; 4] = [0; 4];
8266 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8267 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8268 _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8269 let expected = [0, 2, 0, 4];
8270 assert_eq!(expected, base_addr);
8271 }
8272
8273 #[simd_test(enable = "avx512f,avx512vl")]
8274 unsafe fn test_mm256_i64scatter_pd() {
8275 let mut base_addr: [f64; 4] = [0.; 4];
8276 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8277 let src = _mm256_setr_pd(2., 3., 4., 1.);
8278 _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8279 let expected = [1., 2., 3., 4.];
8280 assert_eq!(expected, base_addr);
8281 }
8282
8283 #[simd_test(enable = "avx512f,avx512vl")]
8284 unsafe fn test_mm256_mask_i64scatter_pd() {
8285 let mut base_addr: [f64; 4] = [0.; 4];
8286 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8287 let src = _mm256_setr_pd(2., 3., 4., 1.);
8288 _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8289 let expected = [0., 2., 0., 4.];
8290 assert_eq!(expected, base_addr);
8291 }
8292
8293 #[simd_test(enable = "avx512f,avx512vl")]
8294 unsafe fn test_mm256_i64scatter_ps() {
8295 let mut base_addr: [f32; 4] = [0.; 4];
8296 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8297 let src = _mm_setr_ps(2., 3., 4., 1.);
8298 _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8299 let expected = [1., 2., 3., 4.];
8300 assert_eq!(expected, base_addr);
8301 }
8302
8303 #[simd_test(enable = "avx512f,avx512vl")]
8304 unsafe fn test_mm256_mask_i64scatter_ps() {
8305 let mut base_addr: [f32; 4] = [0.; 4];
8306 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8307 let src = _mm_setr_ps(2., 3., 4., 1.);
8308 _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8309 let expected = [0., 2., 0., 4.];
8310 assert_eq!(expected, base_addr);
8311 }
8312
8313 #[simd_test(enable = "avx512f")]
8314 unsafe fn test_mm512_rol_epi64() {
8315 #[rustfmt::skip]
8316 let a = _mm512_set_epi64(
8317 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8318 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8319 );
8320 let r = _mm512_rol_epi64::<1>(a);
8321 #[rustfmt::skip]
8322 let e = _mm512_set_epi64(
8323 1 << 0, 1 << 33, 1 << 33, 1 << 33,
8324 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8325 );
8326 assert_eq_m512i(r, e);
8327 }
8328
8329 #[simd_test(enable = "avx512f")]
8330 unsafe fn test_mm512_mask_rol_epi64() {
8331 #[rustfmt::skip]
8332 let a = _mm512_set_epi64(
8333 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8334 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8335 );
8336 let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
8337 assert_eq_m512i(r, a);
8338 let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
8339 #[rustfmt::skip]
8340 let e = _mm512_set_epi64(
8341 1 << 0, 1 << 33, 1 << 33, 1 << 33,
8342 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8343 );
8344 assert_eq_m512i(r, e);
8345 }
8346
8347 #[simd_test(enable = "avx512f")]
8348 unsafe fn test_mm512_maskz_rol_epi64() {
8349 #[rustfmt::skip]
8350 let a = _mm512_set_epi64(
8351 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8352 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8353 );
8354 let r = _mm512_maskz_rol_epi64::<1>(0, a);
8355 assert_eq_m512i(r, _mm512_setzero_si512());
8356 let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
8357 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
8358 assert_eq_m512i(r, e);
8359 }
8360
8361 #[simd_test(enable = "avx512f,avx512vl")]
8362 unsafe fn test_mm256_rol_epi64() {
8363 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8364 let r = _mm256_rol_epi64::<1>(a);
8365 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8366 assert_eq_m256i(r, e);
8367 }
8368
8369 #[simd_test(enable = "avx512f,avx512vl")]
8370 unsafe fn test_mm256_mask_rol_epi64() {
8371 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8372 let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
8373 assert_eq_m256i(r, a);
8374 let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
8375 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8376 assert_eq_m256i(r, e);
8377 }
8378
8379 #[simd_test(enable = "avx512f,avx512vl")]
8380 unsafe fn test_mm256_maskz_rol_epi64() {
8381 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8382 let r = _mm256_maskz_rol_epi64::<1>(0, a);
8383 assert_eq_m256i(r, _mm256_setzero_si256());
8384 let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
8385 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8386 assert_eq_m256i(r, e);
8387 }
8388
8389 #[simd_test(enable = "avx512f,avx512vl")]
8390 unsafe fn test_mm_rol_epi64() {
8391 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8392 let r = _mm_rol_epi64::<1>(a);
8393 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8394 assert_eq_m128i(r, e);
8395 }
8396
8397 #[simd_test(enable = "avx512f,avx512vl")]
8398 unsafe fn test_mm_mask_rol_epi64() {
8399 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8400 let r = _mm_mask_rol_epi64::<1>(a, 0, a);
8401 assert_eq_m128i(r, a);
8402 let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
8403 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8404 assert_eq_m128i(r, e);
8405 }
8406
8407 #[simd_test(enable = "avx512f,avx512vl")]
8408 unsafe fn test_mm_maskz_rol_epi64() {
8409 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8410 let r = _mm_maskz_rol_epi64::<1>(0, a);
8411 assert_eq_m128i(r, _mm_setzero_si128());
8412 let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
8413 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8414 assert_eq_m128i(r, e);
8415 }
8416
8417 #[simd_test(enable = "avx512f")]
8418 unsafe fn test_mm512_ror_epi64() {
8419 #[rustfmt::skip]
8420 let a = _mm512_set_epi64(
8421 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8422 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8423 );
8424 let r = _mm512_ror_epi64::<1>(a);
8425 #[rustfmt::skip]
8426 let e = _mm512_set_epi64(
8427 1 << 63, 1 << 31, 1 << 31, 1 << 31,
8428 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8429 );
8430 assert_eq_m512i(r, e);
8431 }
8432
8433 #[simd_test(enable = "avx512f")]
8434 unsafe fn test_mm512_mask_ror_epi64() {
8435 #[rustfmt::skip]
8436 let a = _mm512_set_epi64(
8437 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8438 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8439 );
8440 let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
8441 assert_eq_m512i(r, a);
8442 let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
8443 #[rustfmt::skip]
8444 let e = _mm512_set_epi64(
8445 1 << 63, 1 << 31, 1 << 31, 1 << 31,
8446 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8447 );
8448 assert_eq_m512i(r, e);
8449 }
8450
8451 #[simd_test(enable = "avx512f")]
8452 unsafe fn test_mm512_maskz_ror_epi64() {
8453 #[rustfmt::skip]
8454 let a = _mm512_set_epi64(
8455 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8456 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8457 );
8458 let r = _mm512_maskz_ror_epi64::<1>(0, a);
8459 assert_eq_m512i(r, _mm512_setzero_si512());
8460 let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
8461 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
8462 assert_eq_m512i(r, e);
8463 }
8464
8465 #[simd_test(enable = "avx512f,avx512vl")]
8466 unsafe fn test_mm256_ror_epi64() {
8467 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8468 let r = _mm256_ror_epi64::<1>(a);
8469 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8470 assert_eq_m256i(r, e);
8471 }
8472
8473 #[simd_test(enable = "avx512f,avx512vl")]
8474 unsafe fn test_mm256_mask_ror_epi64() {
8475 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8476 let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
8477 assert_eq_m256i(r, a);
8478 let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
8479 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8480 assert_eq_m256i(r, e);
8481 }
8482
8483 #[simd_test(enable = "avx512f,avx512vl")]
8484 unsafe fn test_mm256_maskz_ror_epi64() {
8485 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8486 let r = _mm256_maskz_ror_epi64::<1>(0, a);
8487 assert_eq_m256i(r, _mm256_setzero_si256());
8488 let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
8489 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8490 assert_eq_m256i(r, e);
8491 }
8492
8493 #[simd_test(enable = "avx512f,avx512vl")]
8494 unsafe fn test_mm_ror_epi64() {
8495 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8496 let r = _mm_ror_epi64::<1>(a);
8497 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8498 assert_eq_m128i(r, e);
8499 }
8500
8501 #[simd_test(enable = "avx512f,avx512vl")]
8502 unsafe fn test_mm_mask_ror_epi64() {
8503 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8504 let r = _mm_mask_ror_epi64::<1>(a, 0, a);
8505 assert_eq_m128i(r, a);
8506 let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
8507 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8508 assert_eq_m128i(r, e);
8509 }
8510
8511 #[simd_test(enable = "avx512f,avx512vl")]
8512 unsafe fn test_mm_maskz_ror_epi64() {
8513 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8514 let r = _mm_maskz_ror_epi64::<1>(0, a);
8515 assert_eq_m128i(r, _mm_setzero_si128());
8516 let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
8517 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8518 assert_eq_m128i(r, e);
8519 }
8520
8521 #[simd_test(enable = "avx512f")]
8522 unsafe fn test_mm512_slli_epi64() {
8523 #[rustfmt::skip]
8524 let a = _mm512_set_epi64(
8525 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8526 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8527 );
8528 let r = _mm512_slli_epi64::<1>(a);
8529 #[rustfmt::skip]
8530 let e = _mm512_set_epi64(
8531 0, 1 << 33, 1 << 33, 1 << 33,
8532 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8533 );
8534 assert_eq_m512i(r, e);
8535 }
8536
8537 #[simd_test(enable = "avx512f")]
8538 unsafe fn test_mm512_mask_slli_epi64() {
8539 #[rustfmt::skip]
8540 let a = _mm512_set_epi64(
8541 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8542 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8543 );
8544 let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
8545 assert_eq_m512i(r, a);
8546 let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
8547 #[rustfmt::skip]
8548 let e = _mm512_set_epi64(
8549 0, 1 << 33, 1 << 33, 1 << 33,
8550 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8551 );
8552 assert_eq_m512i(r, e);
8553 }
8554
8555 #[simd_test(enable = "avx512f")]
8556 unsafe fn test_mm512_maskz_slli_epi64() {
8557 #[rustfmt::skip]
8558 let a = _mm512_set_epi64(
8559 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8560 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8561 );
8562 let r = _mm512_maskz_slli_epi64::<1>(0, a);
8563 assert_eq_m512i(r, _mm512_setzero_si512());
8564 let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
8565 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8566 assert_eq_m512i(r, e);
8567 }
8568
8569 #[simd_test(enable = "avx512f,avx512vl")]
8570 unsafe fn test_mm256_mask_slli_epi64() {
8571 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8572 let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
8573 assert_eq_m256i(r, a);
8574 let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
8575 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8576 assert_eq_m256i(r, e);
8577 }
8578
8579 #[simd_test(enable = "avx512f,avx512vl")]
8580 unsafe fn test_mm256_maskz_slli_epi64() {
8581 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8582 let r = _mm256_maskz_slli_epi64::<1>(0, a);
8583 assert_eq_m256i(r, _mm256_setzero_si256());
8584 let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
8585 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8586 assert_eq_m256i(r, e);
8587 }
8588
8589 #[simd_test(enable = "avx512f,avx512vl")]
8590 unsafe fn test_mm_mask_slli_epi64() {
8591 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8592 let r = _mm_mask_slli_epi64::<1>(a, 0, a);
8593 assert_eq_m128i(r, a);
8594 let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
8595 let e = _mm_set_epi64x(0, 1 << 33);
8596 assert_eq_m128i(r, e);
8597 }
8598
8599 #[simd_test(enable = "avx512f,avx512vl")]
8600 unsafe fn test_mm_maskz_slli_epi64() {
8601 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8602 let r = _mm_maskz_slli_epi64::<1>(0, a);
8603 assert_eq_m128i(r, _mm_setzero_si128());
8604 let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
8605 let e = _mm_set_epi64x(0, 1 << 33);
8606 assert_eq_m128i(r, e);
8607 }
8608
8609 #[simd_test(enable = "avx512f")]
8610 unsafe fn test_mm512_srli_epi64() {
8611 #[rustfmt::skip]
8612 let a = _mm512_set_epi64(
8613 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8614 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8615 );
8616 let r = _mm512_srli_epi64::<1>(a);
8617 #[rustfmt::skip]
8618 let e = _mm512_set_epi64(
8619 0, 1 << 31, 1 << 31, 1 << 31,
8620 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8621 );
8622 assert_eq_m512i(r, e);
8623 }
8624
8625 #[simd_test(enable = "avx512f")]
8626 unsafe fn test_mm512_mask_srli_epi64() {
8627 #[rustfmt::skip]
8628 let a = _mm512_set_epi64(
8629 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8630 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8631 );
8632 let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
8633 assert_eq_m512i(r, a);
8634 let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
8635 #[rustfmt::skip]
8636 let e = _mm512_set_epi64(
8637 0, 1 << 31, 1 << 31, 1 << 31,
8638 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8639 );
8640 assert_eq_m512i(r, e);
8641 }
8642
8643 #[simd_test(enable = "avx512f")]
8644 unsafe fn test_mm512_maskz_srli_epi64() {
8645 #[rustfmt::skip]
8646 let a = _mm512_set_epi64(
8647 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8648 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8649 );
8650 let r = _mm512_maskz_srli_epi64::<1>(0, a);
8651 assert_eq_m512i(r, _mm512_setzero_si512());
8652 let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
8653 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8654 assert_eq_m512i(r, e);
8655 }
8656
8657 #[simd_test(enable = "avx512f,avx512vl")]
8658 unsafe fn test_mm256_mask_srli_epi64() {
8659 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8660 let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
8661 assert_eq_m256i(r, a);
8662 let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
8663 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8664 assert_eq_m256i(r, e);
8665 }
8666
8667 #[simd_test(enable = "avx512f,avx512vl")]
8668 unsafe fn test_mm256_maskz_srli_epi64() {
8669 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8670 let r = _mm256_maskz_srli_epi64::<1>(0, a);
8671 assert_eq_m256i(r, _mm256_setzero_si256());
8672 let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
8673 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8674 assert_eq_m256i(r, e);
8675 }
8676
8677 #[simd_test(enable = "avx512f,avx512vl")]
8678 unsafe fn test_mm_mask_srli_epi64() {
8679 let a = _mm_set_epi64x(1 << 5, 0);
8680 let r = _mm_mask_srli_epi64::<1>(a, 0, a);
8681 assert_eq_m128i(r, a);
8682 let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
8683 let e = _mm_set_epi64x(1 << 4, 0);
8684 assert_eq_m128i(r, e);
8685 }
8686
8687 #[simd_test(enable = "avx512f,avx512vl")]
8688 unsafe fn test_mm_maskz_srli_epi64() {
8689 let a = _mm_set_epi64x(1 << 5, 0);
8690 let r = _mm_maskz_srli_epi64::<1>(0, a);
8691 assert_eq_m128i(r, _mm_setzero_si128());
8692 let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8693 let e = _mm_set_epi64x(1 << 4, 0);
8694 assert_eq_m128i(r, e);
8695 }
8696
8697 #[simd_test(enable = "avx512f")]
8698 unsafe fn test_mm512_rolv_epi64() {
8699 #[rustfmt::skip]
8700 let a = _mm512_set_epi64(
8701 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8702 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8703 );
8704 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8705 let r = _mm512_rolv_epi64(a, b);
8706 #[rustfmt::skip]
8707 let e = _mm512_set_epi64(
8708 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8709 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8710 );
8711 assert_eq_m512i(r, e);
8712 }
8713
8714 #[simd_test(enable = "avx512f")]
8715 unsafe fn test_mm512_mask_rolv_epi64() {
8716 #[rustfmt::skip]
8717 let a = _mm512_set_epi64(
8718 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8719 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8720 );
8721 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8722 let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8723 assert_eq_m512i(r, a);
8724 let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8725 #[rustfmt::skip]
8726 let e = _mm512_set_epi64(
8727 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8728 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8729 );
8730 assert_eq_m512i(r, e);
8731 }
8732
8733 #[simd_test(enable = "avx512f")]
8734 unsafe fn test_mm512_maskz_rolv_epi64() {
8735 #[rustfmt::skip]
8736 let a = _mm512_set_epi64(
8737 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8738 1 << 32, 1 << 32, 1 << 32, 1 << 62,
8739 );
8740 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8741 let r = _mm512_maskz_rolv_epi64(0, a, b);
8742 assert_eq_m512i(r, _mm512_setzero_si512());
8743 let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8744 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8745 assert_eq_m512i(r, e);
8746 }
8747
8748 #[simd_test(enable = "avx512f,avx512vl")]
8749 unsafe fn test_mm256_rolv_epi64() {
8750 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8751 let b = _mm256_set_epi64x(0, 1, 2, 3);
8752 let r = _mm256_rolv_epi64(a, b);
8753 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8754 assert_eq_m256i(r, e);
8755 }
8756
8757 #[simd_test(enable = "avx512f,avx512vl")]
8758 unsafe fn test_mm256_mask_rolv_epi64() {
8759 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8760 let b = _mm256_set_epi64x(0, 1, 2, 3);
8761 let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8762 assert_eq_m256i(r, a);
8763 let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8764 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8765 assert_eq_m256i(r, e);
8766 }
8767
8768 #[simd_test(enable = "avx512f,avx512vl")]
8769 unsafe fn test_mm256_maskz_rolv_epi64() {
8770 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8771 let b = _mm256_set_epi64x(0, 1, 2, 3);
8772 let r = _mm256_maskz_rolv_epi64(0, a, b);
8773 assert_eq_m256i(r, _mm256_setzero_si256());
8774 let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8775 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8776 assert_eq_m256i(r, e);
8777 }
8778
8779 #[simd_test(enable = "avx512f,avx512vl")]
8780 unsafe fn test_mm_rolv_epi64() {
8781 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8782 let b = _mm_set_epi64x(0, 1);
8783 let r = _mm_rolv_epi64(a, b);
8784 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8785 assert_eq_m128i(r, e);
8786 }
8787
8788 #[simd_test(enable = "avx512f,avx512vl")]
8789 unsafe fn test_mm_mask_rolv_epi64() {
8790 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8791 let b = _mm_set_epi64x(0, 1);
8792 let r = _mm_mask_rolv_epi64(a, 0, a, b);
8793 assert_eq_m128i(r, a);
8794 let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8795 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8796 assert_eq_m128i(r, e);
8797 }
8798
8799 #[simd_test(enable = "avx512f,avx512vl")]
8800 unsafe fn test_mm_maskz_rolv_epi64() {
8801 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8802 let b = _mm_set_epi64x(0, 1);
8803 let r = _mm_maskz_rolv_epi64(0, a, b);
8804 assert_eq_m128i(r, _mm_setzero_si128());
8805 let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8806 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8807 assert_eq_m128i(r, e);
8808 }
8809
8810 #[simd_test(enable = "avx512f")]
8811 unsafe fn test_mm512_rorv_epi64() {
8812 #[rustfmt::skip]
8813 let a = _mm512_set_epi64(
8814 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8815 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8816 );
8817 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8818 let r = _mm512_rorv_epi64(a, b);
8819 #[rustfmt::skip]
8820 let e = _mm512_set_epi64(
8821 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8822 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8823 );
8824 assert_eq_m512i(r, e);
8825 }
8826
8827 #[simd_test(enable = "avx512f")]
8828 unsafe fn test_mm512_mask_rorv_epi64() {
8829 #[rustfmt::skip]
8830 let a = _mm512_set_epi64(
8831 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8832 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8833 );
8834 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8835 let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8836 assert_eq_m512i(r, a);
8837 let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8838 #[rustfmt::skip]
8839 let e = _mm512_set_epi64(
8840 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8841 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8842 );
8843 assert_eq_m512i(r, e);
8844 }
8845
8846 #[simd_test(enable = "avx512f")]
8847 unsafe fn test_mm512_maskz_rorv_epi64() {
8848 #[rustfmt::skip]
8849 let a = _mm512_set_epi64(
8850 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8851 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8852 );
8853 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8854 let r = _mm512_maskz_rorv_epi64(0, a, b);
8855 assert_eq_m512i(r, _mm512_setzero_si512());
8856 let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8857 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8858 assert_eq_m512i(r, e);
8859 }
8860
8861 #[simd_test(enable = "avx512f,avx512vl")]
8862 unsafe fn test_mm256_rorv_epi64() {
8863 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8864 let b = _mm256_set_epi64x(0, 1, 2, 3);
8865 let r = _mm256_rorv_epi64(a, b);
8866 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8867 assert_eq_m256i(r, e);
8868 }
8869
8870 #[simd_test(enable = "avx512f,avx512vl")]
8871 unsafe fn test_mm256_mask_rorv_epi64() {
8872 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8873 let b = _mm256_set_epi64x(0, 1, 2, 3);
8874 let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8875 assert_eq_m256i(r, a);
8876 let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8877 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8878 assert_eq_m256i(r, e);
8879 }
8880
8881 #[simd_test(enable = "avx512f,avx512vl")]
8882 unsafe fn test_mm256_maskz_rorv_epi64() {
8883 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8884 let b = _mm256_set_epi64x(0, 1, 2, 3);
8885 let r = _mm256_maskz_rorv_epi64(0, a, b);
8886 assert_eq_m256i(r, _mm256_setzero_si256());
8887 let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8888 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8889 assert_eq_m256i(r, e);
8890 }
8891
8892 #[simd_test(enable = "avx512f,avx512vl")]
8893 unsafe fn test_mm_rorv_epi64() {
8894 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8895 let b = _mm_set_epi64x(0, 1);
8896 let r = _mm_rorv_epi64(a, b);
8897 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8898 assert_eq_m128i(r, e);
8899 }
8900
8901 #[simd_test(enable = "avx512f,avx512vl")]
8902 unsafe fn test_mm_mask_rorv_epi64() {
8903 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8904 let b = _mm_set_epi64x(0, 1);
8905 let r = _mm_mask_rorv_epi64(a, 0, a, b);
8906 assert_eq_m128i(r, a);
8907 let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8908 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8909 assert_eq_m128i(r, e);
8910 }
8911
8912 #[simd_test(enable = "avx512f,avx512vl")]
8913 unsafe fn test_mm_maskz_rorv_epi64() {
8914 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8915 let b = _mm_set_epi64x(0, 1);
8916 let r = _mm_maskz_rorv_epi64(0, a, b);
8917 assert_eq_m128i(r, _mm_setzero_si128());
8918 let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8919 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8920 assert_eq_m128i(r, e);
8921 }
8922
8923 #[simd_test(enable = "avx512f")]
8924 unsafe fn test_mm512_sllv_epi64() {
8925 #[rustfmt::skip]
8926 let a = _mm512_set_epi64(
8927 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8928 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8929 );
8930 let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8931 let r = _mm512_sllv_epi64(a, count);
8932 #[rustfmt::skip]
8933 let e = _mm512_set_epi64(
8934 1 << 32, 0, 1 << 34, 1 << 35,
8935 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8936 );
8937 assert_eq_m512i(r, e);
8938 }
8939
8940 #[simd_test(enable = "avx512f")]
8941 unsafe fn test_mm512_mask_sllv_epi64() {
8942 #[rustfmt::skip]
8943 let a = _mm512_set_epi64(
8944 1 << 32, 1 << 32, 1 << 63, 1 << 32,
8945 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8946 );
8947 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8948 let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8949 assert_eq_m512i(r, a);
8950 let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8951 #[rustfmt::skip]
8952 let e = _mm512_set_epi64(
8953 1 << 32, 1 << 33, 0, 1 << 35,
8954 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8955 );
8956 assert_eq_m512i(r, e);
8957 }
8958
8959 #[simd_test(enable = "avx512f")]
8960 unsafe fn test_mm512_maskz_sllv_epi64() {
8961 #[rustfmt::skip]
8962 let a = _mm512_set_epi64(
8963 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8964 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8965 );
8966 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8967 let r = _mm512_maskz_sllv_epi64(0, a, count);
8968 assert_eq_m512i(r, _mm512_setzero_si512());
8969 let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8970 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8971 assert_eq_m512i(r, e);
8972 }
8973
8974 #[simd_test(enable = "avx512f,avx512vl")]
8975 unsafe fn test_mm256_mask_sllv_epi64() {
8976 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8977 let count = _mm256_set_epi64x(0, 1, 2, 3);
8978 let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8979 assert_eq_m256i(r, a);
8980 let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8981 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8982 assert_eq_m256i(r, e);
8983 }
8984
8985 #[simd_test(enable = "avx512f,avx512vl")]
8986 unsafe fn test_mm256_maskz_sllv_epi64() {
8987 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8988 let count = _mm256_set_epi64x(0, 1, 2, 3);
8989 let r = _mm256_maskz_sllv_epi64(0, a, count);
8990 assert_eq_m256i(r, _mm256_setzero_si256());
8991 let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8992 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8993 assert_eq_m256i(r, e);
8994 }
8995
8996 #[simd_test(enable = "avx512f,avx512vl")]
8997 unsafe fn test_mm_mask_sllv_epi64() {
8998 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8999 let count = _mm_set_epi64x(2, 3);
9000 let r = _mm_mask_sllv_epi64(a, 0, a, count);
9001 assert_eq_m128i(r, a);
9002 let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
9003 let e = _mm_set_epi64x(0, 1 << 35);
9004 assert_eq_m128i(r, e);
9005 }
9006
9007 #[simd_test(enable = "avx512f,avx512vl")]
9008 unsafe fn test_mm_maskz_sllv_epi64() {
9009 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9010 let count = _mm_set_epi64x(2, 3);
9011 let r = _mm_maskz_sllv_epi64(0, a, count);
9012 assert_eq_m128i(r, _mm_setzero_si128());
9013 let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
9014 let e = _mm_set_epi64x(0, 1 << 35);
9015 assert_eq_m128i(r, e);
9016 }
9017
9018 #[simd_test(enable = "avx512f")]
9019 unsafe fn test_mm512_srlv_epi64() {
9020 #[rustfmt::skip]
9021 let a = _mm512_set_epi64(
9022 1 << 32, 1 << 0, 1 << 32, 1 << 32,
9023 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9024 );
9025 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9026 let r = _mm512_srlv_epi64(a, count);
9027 #[rustfmt::skip]
9028 let e = _mm512_set_epi64(
9029 1 << 32, 0, 1 << 30, 1 << 29,
9030 1 << 28, 1 << 27, 1 << 26, 1 << 25,
9031 );
9032 assert_eq_m512i(r, e);
9033 }
9034
9035 #[simd_test(enable = "avx512f")]
9036 unsafe fn test_mm512_mask_srlv_epi64() {
9037 #[rustfmt::skip]
9038 let a = _mm512_set_epi64(
9039 1 << 32, 1 << 0, 1 << 32, 1 << 32,
9040 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9041 );
9042 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9043 let r = _mm512_mask_srlv_epi64(a, 0, a, count);
9044 assert_eq_m512i(r, a);
9045 let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
9046 #[rustfmt::skip]
9047 let e = _mm512_set_epi64(
9048 1 << 32, 0, 1 << 30, 1 << 29,
9049 1 << 28, 1 << 27, 1 << 26, 1 << 25,
9050 );
9051 assert_eq_m512i(r, e);
9052 }
9053
9054 #[simd_test(enable = "avx512f")]
9055 unsafe fn test_mm512_maskz_srlv_epi64() {
9056 #[rustfmt::skip]
9057 let a = _mm512_set_epi64(
9058 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9059 1 << 32, 1 << 32, 1 << 32, 1 << 0,
9060 );
9061 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9062 let r = _mm512_maskz_srlv_epi64(0, a, count);
9063 assert_eq_m512i(r, _mm512_setzero_si512());
9064 let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
9065 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
9066 assert_eq_m512i(r, e);
9067 }
9068
9069 #[simd_test(enable = "avx512f,avx512vl")]
9070 unsafe fn test_mm256_mask_srlv_epi64() {
9071 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9072 let count = _mm256_set1_epi64x(1);
9073 let r = _mm256_mask_srlv_epi64(a, 0, a, count);
9074 assert_eq_m256i(r, a);
9075 let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
9076 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9077 assert_eq_m256i(r, e);
9078 }
9079
9080 #[simd_test(enable = "avx512f,avx512vl")]
9081 unsafe fn test_mm256_maskz_srlv_epi64() {
9082 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9083 let count = _mm256_set1_epi64x(1);
9084 let r = _mm256_maskz_srlv_epi64(0, a, count);
9085 assert_eq_m256i(r, _mm256_setzero_si256());
9086 let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
9087 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9088 assert_eq_m256i(r, e);
9089 }
9090
9091 #[simd_test(enable = "avx512f,avx512vl")]
9092 unsafe fn test_mm_mask_srlv_epi64() {
9093 let a = _mm_set_epi64x(1 << 5, 0);
9094 let count = _mm_set1_epi64x(1);
9095 let r = _mm_mask_srlv_epi64(a, 0, a, count);
9096 assert_eq_m128i(r, a);
9097 let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
9098 let e = _mm_set_epi64x(1 << 4, 0);
9099 assert_eq_m128i(r, e);
9100 }
9101
9102 #[simd_test(enable = "avx512f,avx512vl")]
9103 unsafe fn test_mm_maskz_srlv_epi64() {
9104 let a = _mm_set_epi64x(1 << 5, 0);
9105 let count = _mm_set1_epi64x(1);
9106 let r = _mm_maskz_srlv_epi64(0, a, count);
9107 assert_eq_m128i(r, _mm_setzero_si128());
9108 let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
9109 let e = _mm_set_epi64x(1 << 4, 0);
9110 assert_eq_m128i(r, e);
9111 }
9112
9113 #[simd_test(enable = "avx512f")]
9114 unsafe fn test_mm512_sll_epi64() {
9115 #[rustfmt::skip]
9116 let a = _mm512_set_epi64(
9117 1 << 63, 1 << 32, 1 << 32, 1 << 32,
9118 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9119 );
9120 let count = _mm_set_epi64x(0, 1);
9121 let r = _mm512_sll_epi64(a, count);
9122 #[rustfmt::skip]
9123 let e = _mm512_set_epi64(
9124 0, 1 << 33, 1 << 33, 1 << 33,
9125 1 << 33, 1 << 33, 1 << 33, 1 << 33,
9126 );
9127 assert_eq_m512i(r, e);
9128 let count = _mm_set_epi64x(1, 0);
9129 let r = _mm512_sll_epi64(a, count);
9130 assert_eq_m512i(r, a);
9131 }
9132
9133 #[simd_test(enable = "avx512f")]
9134 unsafe fn test_mm512_mask_sll_epi64() {
9135 #[rustfmt::skip]
9136 let a = _mm512_set_epi64(
9137 1 << 63, 1 << 32, 1 << 32, 1 << 32,
9138 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9139 );
9140 let count = _mm_set_epi64x(0, 1);
9141 let r = _mm512_mask_sll_epi64(a, 0, a, count);
9142 assert_eq_m512i(r, a);
9143 let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
9144 #[rustfmt::skip]
9145 let e = _mm512_set_epi64(
9146 0, 1 << 33, 1 << 33, 1 << 33,
9147 1 << 33, 1 << 33, 1 << 33, 1 << 33,
9148 );
9149 assert_eq_m512i(r, e);
9150 }
9151
9152 #[simd_test(enable = "avx512f")]
9153 unsafe fn test_mm512_maskz_sll_epi64() {
9154 #[rustfmt::skip]
9155 let a = _mm512_set_epi64(
9156 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9157 1 << 32, 1 << 32, 1 << 32, 1 << 63,
9158 );
9159 let count = _mm_set_epi64x(0, 1);
9160 let r = _mm512_maskz_sll_epi64(0, a, count);
9161 assert_eq_m512i(r, _mm512_setzero_si512());
9162 let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
9163 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
9164 assert_eq_m512i(r, e);
9165 }
9166
9167 #[simd_test(enable = "avx512f,avx512vl")]
9168 unsafe fn test_mm256_mask_sll_epi64() {
9169 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9170 let count = _mm_set_epi64x(0, 1);
9171 let r = _mm256_mask_sll_epi64(a, 0, a, count);
9172 assert_eq_m256i(r, a);
9173 let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
9174 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9175 assert_eq_m256i(r, e);
9176 }
9177
9178 #[simd_test(enable = "avx512f,avx512vl")]
9179 unsafe fn test_mm256_maskz_sll_epi64() {
9180 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9181 let count = _mm_set_epi64x(0, 1);
9182 let r = _mm256_maskz_sll_epi64(0, a, count);
9183 assert_eq_m256i(r, _mm256_setzero_si256());
9184 let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
9185 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9186 assert_eq_m256i(r, e);
9187 }
9188
9189 #[simd_test(enable = "avx512f,avx512vl")]
9190 unsafe fn test_mm_mask_sll_epi64() {
9191 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9192 let count = _mm_set_epi64x(0, 1);
9193 let r = _mm_mask_sll_epi64(a, 0, a, count);
9194 assert_eq_m128i(r, a);
9195 let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
9196 let e = _mm_set_epi64x(0, 1 << 33);
9197 assert_eq_m128i(r, e);
9198 }
9199
9200 #[simd_test(enable = "avx512f,avx512vl")]
9201 unsafe fn test_mm_maskz_sll_epi64() {
9202 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9203 let count = _mm_set_epi64x(0, 1);
9204 let r = _mm_maskz_sll_epi64(0, a, count);
9205 assert_eq_m128i(r, _mm_setzero_si128());
9206 let r = _mm_maskz_sll_epi64(0b00000011, a, count);
9207 let e = _mm_set_epi64x(0, 1 << 33);
9208 assert_eq_m128i(r, e);
9209 }
9210
9211 #[simd_test(enable = "avx512f")]
9212 unsafe fn test_mm512_srl_epi64() {
9213 #[rustfmt::skip]
9214 let a = _mm512_set_epi64(
9215 1 << 0, 1 << 32, 1 << 32, 1 << 32,
9216 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9217 );
9218 let count = _mm_set_epi64x(0, 1);
9219 let r = _mm512_srl_epi64(a, count);
9220 #[rustfmt::skip]
9221 let e = _mm512_set_epi64(
9222 0, 1 << 31, 1 << 31, 1 << 31,
9223 1 << 31, 1 << 31, 1 << 31, 1 << 31,
9224 );
9225 assert_eq_m512i(r, e);
9226 }
9227
9228 #[simd_test(enable = "avx512f")]
9229 unsafe fn test_mm512_mask_srl_epi64() {
9230 #[rustfmt::skip]
9231 let a = _mm512_set_epi64(
9232 1 << 0, 1 << 32, 1 << 32, 1 << 32,
9233 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9234 );
9235 let count = _mm_set_epi64x(0, 1);
9236 let r = _mm512_mask_srl_epi64(a, 0, a, count);
9237 assert_eq_m512i(r, a);
9238 let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
9239 #[rustfmt::skip]
9240 let e = _mm512_set_epi64(
9241 0, 1 << 31, 1 << 31, 1 << 31,
9242 1 << 31, 1 << 31, 1 << 31, 1 << 31,
9243 );
9244 assert_eq_m512i(r, e);
9245 }
9246
9247 #[simd_test(enable = "avx512f")]
9248 unsafe fn test_mm512_maskz_srl_epi64() {
9249 #[rustfmt::skip]
9250 let a = _mm512_set_epi64(
9251 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9252 1 << 32, 1 << 32, 1 << 32, 1 << 0,
9253 );
9254 let count = _mm_set_epi64x(0, 1);
9255 let r = _mm512_maskz_srl_epi64(0, a, count);
9256 assert_eq_m512i(r, _mm512_setzero_si512());
9257 let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
9258 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
9259 assert_eq_m512i(r, e);
9260 }
9261
9262 #[simd_test(enable = "avx512f,avx512vl")]
9263 unsafe fn test_mm256_mask_srl_epi64() {
9264 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9265 let count = _mm_set_epi64x(0, 1);
9266 let r = _mm256_mask_srl_epi64(a, 0, a, count);
9267 assert_eq_m256i(r, a);
9268 let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
9269 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9270 assert_eq_m256i(r, e);
9271 }
9272
9273 #[simd_test(enable = "avx512f,avx512vl")]
9274 unsafe fn test_mm256_maskz_srl_epi64() {
9275 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9276 let count = _mm_set_epi64x(0, 1);
9277 let r = _mm256_maskz_srl_epi64(0, a, count);
9278 assert_eq_m256i(r, _mm256_setzero_si256());
9279 let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
9280 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9281 assert_eq_m256i(r, e);
9282 }
9283
9284 #[simd_test(enable = "avx512f,avx512vl")]
9285 unsafe fn test_mm_mask_srl_epi64() {
9286 let a = _mm_set_epi64x(1 << 5, 0);
9287 let count = _mm_set_epi64x(0, 1);
9288 let r = _mm_mask_srl_epi64(a, 0, a, count);
9289 assert_eq_m128i(r, a);
9290 let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
9291 let e = _mm_set_epi64x(1 << 4, 0);
9292 assert_eq_m128i(r, e);
9293 }
9294
9295 #[simd_test(enable = "avx512f,avx512vl")]
9296 unsafe fn test_mm_maskz_srl_epi64() {
9297 let a = _mm_set_epi64x(1 << 5, 0);
9298 let count = _mm_set_epi64x(0, 1);
9299 let r = _mm_maskz_srl_epi64(0, a, count);
9300 assert_eq_m128i(r, _mm_setzero_si128());
9301 let r = _mm_maskz_srl_epi64(0b00000011, a, count);
9302 let e = _mm_set_epi64x(1 << 4, 0);
9303 assert_eq_m128i(r, e);
9304 }
9305
9306 #[simd_test(enable = "avx512f")]
9307 unsafe fn test_mm512_sra_epi64() {
9308 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9309 let count = _mm_set_epi64x(0, 2);
9310 let r = _mm512_sra_epi64(a, count);
9311 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9312 assert_eq_m512i(r, e);
9313 }
9314
9315 #[simd_test(enable = "avx512f")]
9316 unsafe fn test_mm512_mask_sra_epi64() {
9317 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9318 let count = _mm_set_epi64x(0, 2);
9319 let r = _mm512_mask_sra_epi64(a, 0, a, count);
9320 assert_eq_m512i(r, a);
9321 let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
9322 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9323 assert_eq_m512i(r, e);
9324 }
9325
9326 #[simd_test(enable = "avx512f")]
9327 unsafe fn test_mm512_maskz_sra_epi64() {
9328 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9329 let count = _mm_set_epi64x(0, 2);
9330 let r = _mm512_maskz_sra_epi64(0, a, count);
9331 assert_eq_m512i(r, _mm512_setzero_si512());
9332 let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
9333 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
9334 assert_eq_m512i(r, e);
9335 }
9336
9337 #[simd_test(enable = "avx512f,avx512vl")]
9338 unsafe fn test_mm256_sra_epi64() {
9339 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9340 let count = _mm_set_epi64x(0, 1);
9341 let r = _mm256_sra_epi64(a, count);
9342 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9343 assert_eq_m256i(r, e);
9344 }
9345
9346 #[simd_test(enable = "avx512f,avx512vl")]
9347 unsafe fn test_mm256_mask_sra_epi64() {
9348 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9349 let count = _mm_set_epi64x(0, 1);
9350 let r = _mm256_mask_sra_epi64(a, 0, a, count);
9351 assert_eq_m256i(r, a);
9352 let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
9353 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9354 assert_eq_m256i(r, e);
9355 }
9356
9357 #[simd_test(enable = "avx512f,avx512vl")]
9358 unsafe fn test_mm256_maskz_sra_epi64() {
9359 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9360 let count = _mm_set_epi64x(0, 1);
9361 let r = _mm256_maskz_sra_epi64(0, a, count);
9362 assert_eq_m256i(r, _mm256_setzero_si256());
9363 let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
9364 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9365 assert_eq_m256i(r, e);
9366 }
9367
9368 #[simd_test(enable = "avx512f,avx512vl")]
9369 unsafe fn test_mm_sra_epi64() {
9370 let a = _mm_set_epi64x(1 << 5, 0);
9371 let count = _mm_set_epi64x(0, 1);
9372 let r = _mm_sra_epi64(a, count);
9373 let e = _mm_set_epi64x(1 << 4, 0);
9374 assert_eq_m128i(r, e);
9375 }
9376
9377 #[simd_test(enable = "avx512f,avx512vl")]
9378 unsafe fn test_mm_mask_sra_epi64() {
9379 let a = _mm_set_epi64x(1 << 5, 0);
9380 let count = _mm_set_epi64x(0, 1);
9381 let r = _mm_mask_sra_epi64(a, 0, a, count);
9382 assert_eq_m128i(r, a);
9383 let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
9384 let e = _mm_set_epi64x(1 << 4, 0);
9385 assert_eq_m128i(r, e);
9386 }
9387
9388 #[simd_test(enable = "avx512f,avx512vl")]
9389 unsafe fn test_mm_maskz_sra_epi64() {
9390 let a = _mm_set_epi64x(1 << 5, 0);
9391 let count = _mm_set_epi64x(0, 1);
9392 let r = _mm_maskz_sra_epi64(0, a, count);
9393 assert_eq_m128i(r, _mm_setzero_si128());
9394 let r = _mm_maskz_sra_epi64(0b00000011, a, count);
9395 let e = _mm_set_epi64x(1 << 4, 0);
9396 assert_eq_m128i(r, e);
9397 }
9398
9399 #[simd_test(enable = "avx512f")]
9400 unsafe fn test_mm512_srav_epi64() {
9401 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9402 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9403 let r = _mm512_srav_epi64(a, count);
9404 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9405 assert_eq_m512i(r, e);
9406 }
9407
9408 #[simd_test(enable = "avx512f")]
9409 unsafe fn test_mm512_mask_srav_epi64() {
9410 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9411 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9412 let r = _mm512_mask_srav_epi64(a, 0, a, count);
9413 assert_eq_m512i(r, a);
9414 let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
9415 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9416 assert_eq_m512i(r, e);
9417 }
9418
9419 #[simd_test(enable = "avx512f")]
9420 unsafe fn test_mm512_maskz_srav_epi64() {
9421 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9422 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9423 let r = _mm512_maskz_srav_epi64(0, a, count);
9424 assert_eq_m512i(r, _mm512_setzero_si512());
9425 let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
9426 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
9427 assert_eq_m512i(r, e);
9428 }
9429
9430 #[simd_test(enable = "avx512f,avx512vl")]
9431 unsafe fn test_mm256_srav_epi64() {
9432 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9433 let count = _mm256_set1_epi64x(1);
9434 let r = _mm256_srav_epi64(a, count);
9435 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9436 assert_eq_m256i(r, e);
9437 }
9438
9439 #[simd_test(enable = "avx512f,avx512vl")]
9440 unsafe fn test_mm256_mask_srav_epi64() {
9441 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9442 let count = _mm256_set1_epi64x(1);
9443 let r = _mm256_mask_srav_epi64(a, 0, a, count);
9444 assert_eq_m256i(r, a);
9445 let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
9446 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9447 assert_eq_m256i(r, e);
9448 }
9449
9450 #[simd_test(enable = "avx512f,avx512vl")]
9451 unsafe fn test_mm256_maskz_srav_epi64() {
9452 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9453 let count = _mm256_set1_epi64x(1);
9454 let r = _mm256_maskz_srav_epi64(0, a, count);
9455 assert_eq_m256i(r, _mm256_setzero_si256());
9456 let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
9457 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9458 assert_eq_m256i(r, e);
9459 }
9460
9461 #[simd_test(enable = "avx512f,avx512vl")]
9462 unsafe fn test_mm_srav_epi64() {
9463 let a = _mm_set_epi64x(1 << 5, 0);
9464 let count = _mm_set1_epi64x(1);
9465 let r = _mm_srav_epi64(a, count);
9466 let e = _mm_set_epi64x(1 << 4, 0);
9467 assert_eq_m128i(r, e);
9468 }
9469
9470 #[simd_test(enable = "avx512f,avx512vl")]
9471 unsafe fn test_mm_mask_srav_epi64() {
9472 let a = _mm_set_epi64x(1 << 5, 0);
9473 let count = _mm_set1_epi64x(1);
9474 let r = _mm_mask_srav_epi64(a, 0, a, count);
9475 assert_eq_m128i(r, a);
9476 let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
9477 let e = _mm_set_epi64x(1 << 4, 0);
9478 assert_eq_m128i(r, e);
9479 }
9480
9481 #[simd_test(enable = "avx512f,avx512vl")]
9482 unsafe fn test_mm_maskz_srav_epi64() {
9483 let a = _mm_set_epi64x(1 << 5, 0);
9484 let count = _mm_set1_epi64x(1);
9485 let r = _mm_maskz_srav_epi64(0, a, count);
9486 assert_eq_m128i(r, _mm_setzero_si128());
9487 let r = _mm_maskz_srav_epi64(0b00000011, a, count);
9488 let e = _mm_set_epi64x(1 << 4, 0);
9489 assert_eq_m128i(r, e);
9490 }
9491
9492 #[simd_test(enable = "avx512f")]
9493 unsafe fn test_mm512_srai_epi64() {
9494 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9495 let r = _mm512_srai_epi64::<2>(a);
9496 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9497 assert_eq_m512i(r, e);
9498 }
9499
9500 #[simd_test(enable = "avx512f")]
9501 unsafe fn test_mm512_mask_srai_epi64() {
9502 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9503 let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
9504 assert_eq_m512i(r, a);
9505 let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
9506 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9507 assert_eq_m512i(r, e);
9508 }
9509
9510 #[simd_test(enable = "avx512f")]
9511 unsafe fn test_mm512_maskz_srai_epi64() {
9512 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9513 let r = _mm512_maskz_srai_epi64::<2>(0, a);
9514 assert_eq_m512i(r, _mm512_setzero_si512());
9515 let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
9516 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
9517 assert_eq_m512i(r, e);
9518 }
9519
9520 #[simd_test(enable = "avx512f,avx512vl")]
9521 unsafe fn test_mm256_srai_epi64() {
9522 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9523 let r = _mm256_srai_epi64::<1>(a);
9524 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9525 assert_eq_m256i(r, e);
9526 }
9527
9528 #[simd_test(enable = "avx512f,avx512vl")]
9529 unsafe fn test_mm256_mask_srai_epi64() {
9530 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9531 let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
9532 assert_eq_m256i(r, a);
9533 let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
9534 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9535 assert_eq_m256i(r, e);
9536 }
9537
9538 #[simd_test(enable = "avx512f,avx512vl")]
9539 unsafe fn test_mm256_maskz_srai_epi64() {
9540 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9541 let r = _mm256_maskz_srai_epi64::<1>(0, a);
9542 assert_eq_m256i(r, _mm256_setzero_si256());
9543 let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
9544 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9545 assert_eq_m256i(r, e);
9546 }
9547
9548 #[simd_test(enable = "avx512f,avx512vl")]
9549 unsafe fn test_mm_srai_epi64() {
9550 let a = _mm_set_epi64x(1 << 5, 0);
9551 let r = _mm_srai_epi64::<1>(a);
9552 let e = _mm_set_epi64x(1 << 4, 0);
9553 assert_eq_m128i(r, e);
9554 }
9555
9556 #[simd_test(enable = "avx512f,avx512vl")]
9557 unsafe fn test_mm_mask_srai_epi64() {
9558 let a = _mm_set_epi64x(1 << 5, 0);
9559 let r = _mm_mask_srai_epi64::<1>(a, 0, a);
9560 assert_eq_m128i(r, a);
9561 let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
9562 let e = _mm_set_epi64x(1 << 4, 0);
9563 assert_eq_m128i(r, e);
9564 }
9565
9566 #[simd_test(enable = "avx512f,avx512vl")]
9567 unsafe fn test_mm_maskz_srai_epi64() {
9568 let a = _mm_set_epi64x(1 << 5, 0);
9569 let r = _mm_maskz_srai_epi64::<1>(0, a);
9570 assert_eq_m128i(r, _mm_setzero_si128());
9571 let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
9572 let e = _mm_set_epi64x(1 << 4, 0);
9573 assert_eq_m128i(r, e);
9574 }
9575
9576 #[simd_test(enable = "avx512f")]
9577 unsafe fn test_mm512_permute_pd() {
9578 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9579 let r = _mm512_permute_pd::<0b11_11_11_11>(a);
9580 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9581 assert_eq_m512d(r, e);
9582 }
9583
9584 #[simd_test(enable = "avx512f")]
9585 unsafe fn test_mm512_mask_permute_pd() {
9586 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9587 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
9588 assert_eq_m512d(r, a);
9589 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
9590 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9591 assert_eq_m512d(r, e);
9592 }
9593
9594 #[simd_test(enable = "avx512f")]
9595 unsafe fn test_mm512_maskz_permute_pd() {
9596 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9597 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
9598 assert_eq_m512d(r, _mm512_setzero_pd());
9599 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
9600 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9601 assert_eq_m512d(r, e);
9602 }
9603
9604 #[simd_test(enable = "avx512f,avx512vl")]
9605 unsafe fn test_mm256_mask_permute_pd() {
9606 let a = _mm256_set_pd(3., 2., 1., 0.);
9607 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
9608 assert_eq_m256d(r, a);
9609 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
9610 let e = _mm256_set_pd(3., 3., 1., 1.);
9611 assert_eq_m256d(r, e);
9612 }
9613
9614 #[simd_test(enable = "avx512f,avx512vl")]
9615 unsafe fn test_mm256_maskz_permute_pd() {
9616 let a = _mm256_set_pd(3., 2., 1., 0.);
9617 let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
9618 assert_eq_m256d(r, _mm256_setzero_pd());
9619 let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
9620 let e = _mm256_set_pd(3., 3., 1., 1.);
9621 assert_eq_m256d(r, e);
9622 }
9623
9624 #[simd_test(enable = "avx512f,avx512vl")]
9625 unsafe fn test_mm_mask_permute_pd() {
9626 let a = _mm_set_pd(1., 0.);
9627 let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
9628 assert_eq_m128d(r, a);
9629 let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
9630 let e = _mm_set_pd(1., 1.);
9631 assert_eq_m128d(r, e);
9632 }
9633
9634 #[simd_test(enable = "avx512f,avx512vl")]
9635 unsafe fn test_mm_maskz_permute_pd() {
9636 let a = _mm_set_pd(1., 0.);
9637 let r = _mm_maskz_permute_pd::<0b11>(0, a);
9638 assert_eq_m128d(r, _mm_setzero_pd());
9639 let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
9640 let e = _mm_set_pd(1., 1.);
9641 assert_eq_m128d(r, e);
9642 }
9643
9644 #[simd_test(enable = "avx512f")]
9645 unsafe fn test_mm512_permutex_epi64() {
9646 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9647 let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
9648 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9649 assert_eq_m512i(r, e);
9650 }
9651
9652 #[simd_test(enable = "avx512f")]
9653 unsafe fn test_mm512_mask_permutex_epi64() {
9654 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9655 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9656 assert_eq_m512i(r, a);
9657 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
9658 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9659 assert_eq_m512i(r, e);
9660 }
9661
9662 #[simd_test(enable = "avx512f")]
9663 unsafe fn test_mm512_maskz_permutex_epi64() {
9664 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9665 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9666 assert_eq_m512i(r, _mm512_setzero_si512());
9667 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
9668 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9669 assert_eq_m512i(r, e);
9670 }
9671
9672 #[simd_test(enable = "avx512f,avx512vl")]
9673 unsafe fn test_mm256_permutex_epi64() {
9674 let a = _mm256_set_epi64x(3, 2, 1, 0);
9675 let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
9676 let e = _mm256_set_epi64x(3, 3, 3, 3);
9677 assert_eq_m256i(r, e);
9678 }
9679
9680 #[simd_test(enable = "avx512f,avx512vl")]
9681 unsafe fn test_mm256_mask_permutex_epi64() {
9682 let a = _mm256_set_epi64x(3, 2, 1, 0);
9683 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9684 assert_eq_m256i(r, a);
9685 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
9686 let e = _mm256_set_epi64x(3, 3, 3, 3);
9687 assert_eq_m256i(r, e);
9688 }
9689
9690 #[simd_test(enable = "avx512f")]
9691 unsafe fn test_mm256_maskz_permutex_epi64() {
9692 let a = _mm256_set_epi64x(3, 2, 1, 0);
9693 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9694 assert_eq_m256i(r, _mm256_setzero_si256());
9695 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9696 let e = _mm256_set_epi64x(3, 3, 3, 3);
9697 assert_eq_m256i(r, e);
9698 }
9699
9700 #[simd_test(enable = "avx512f")]
9701 unsafe fn test_mm512_permutex_pd() {
9702 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9703 let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9704 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9705 assert_eq_m512d(r, e);
9706 }
9707
9708 #[simd_test(enable = "avx512f")]
9709 unsafe fn test_mm512_mask_permutex_pd() {
9710 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9711 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9712 assert_eq_m512d(r, a);
9713 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9714 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9715 assert_eq_m512d(r, e);
9716 }
9717
9718 #[simd_test(enable = "avx512f")]
9719 unsafe fn test_mm512_maskz_permutex_pd() {
9720 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9721 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9722 assert_eq_m512d(r, _mm512_setzero_pd());
9723 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9724 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9725 assert_eq_m512d(r, e);
9726 }
9727
9728 #[simd_test(enable = "avx512f,avx512vl")]
9729 unsafe fn test_mm256_permutex_pd() {
9730 let a = _mm256_set_pd(0., 1., 2., 3.);
9731 let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9732 let e = _mm256_set_pd(0., 0., 0., 0.);
9733 assert_eq_m256d(r, e);
9734 }
9735
9736 #[simd_test(enable = "avx512f,avx512vl")]
9737 unsafe fn test_mm256_mask_permutex_pd() {
9738 let a = _mm256_set_pd(0., 1., 2., 3.);
9739 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9740 assert_eq_m256d(r, a);
9741 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9742 let e = _mm256_set_pd(0., 0., 0., 0.);
9743 assert_eq_m256d(r, e);
9744 }
9745
9746 #[simd_test(enable = "avx512f,avx512vl")]
9747 unsafe fn test_mm256_maskz_permutex_pd() {
9748 let a = _mm256_set_pd(0., 1., 2., 3.);
9749 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9750 assert_eq_m256d(r, _mm256_setzero_pd());
9751 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9752 let e = _mm256_set_pd(0., 0., 0., 0.);
9753 assert_eq_m256d(r, e);
9754 }
9755
9756 #[simd_test(enable = "avx512f")]
9757 unsafe fn test_mm512_permutevar_pd() {
9758 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9759 let b = _mm512_set1_epi64(0b1);
9760 let r = _mm512_permutevar_pd(a, b);
9761 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9762 assert_eq_m512d(r, e);
9763 }
9764
9765 #[simd_test(enable = "avx512f")]
9766 unsafe fn test_mm512_mask_permutevar_pd() {
9767 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9768 let b = _mm512_set1_epi64(0b1);
9769 let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9770 assert_eq_m512d(r, a);
9771 let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9772 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9773 assert_eq_m512d(r, e);
9774 }
9775
9776 #[simd_test(enable = "avx512f")]
9777 unsafe fn test_mm512_maskz_permutevar_pd() {
9778 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9779 let b = _mm512_set1_epi64(0b1);
9780 let r = _mm512_maskz_permutevar_pd(0, a, b);
9781 assert_eq_m512d(r, _mm512_setzero_pd());
9782 let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9783 let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9784 assert_eq_m512d(r, e);
9785 }
9786
9787 #[simd_test(enable = "avx512f,avx512vl")]
9788 unsafe fn test_mm256_mask_permutevar_pd() {
9789 let a = _mm256_set_pd(0., 1., 2., 3.);
9790 let b = _mm256_set1_epi64x(0b1);
9791 let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9792 assert_eq_m256d(r, a);
9793 let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9794 let e = _mm256_set_pd(1., 1., 3., 3.);
9795 assert_eq_m256d(r, e);
9796 }
9797
9798 #[simd_test(enable = "avx512f,avx512vl")]
9799 unsafe fn test_mm256_maskz_permutevar_pd() {
9800 let a = _mm256_set_pd(0., 1., 2., 3.);
9801 let b = _mm256_set1_epi64x(0b1);
9802 let r = _mm256_maskz_permutevar_pd(0, a, b);
9803 assert_eq_m256d(r, _mm256_setzero_pd());
9804 let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9805 let e = _mm256_set_pd(1., 1., 3., 3.);
9806 assert_eq_m256d(r, e);
9807 }
9808
9809 #[simd_test(enable = "avx512f,avx512vl")]
9810 unsafe fn test_mm_mask_permutevar_pd() {
9811 let a = _mm_set_pd(0., 1.);
9812 let b = _mm_set1_epi64x(0b1);
9813 let r = _mm_mask_permutevar_pd(a, 0, a, b);
9814 assert_eq_m128d(r, a);
9815 let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9816 let e = _mm_set_pd(1., 1.);
9817 assert_eq_m128d(r, e);
9818 }
9819
9820 #[simd_test(enable = "avx512f,avx512vl")]
9821 unsafe fn test_mm_maskz_permutevar_pd() {
9822 let a = _mm_set_pd(0., 1.);
9823 let b = _mm_set1_epi64x(0b1);
9824 let r = _mm_maskz_permutevar_pd(0, a, b);
9825 assert_eq_m128d(r, _mm_setzero_pd());
9826 let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9827 let e = _mm_set_pd(1., 1.);
9828 assert_eq_m128d(r, e);
9829 }
9830
9831 #[simd_test(enable = "avx512f")]
9832 unsafe fn test_mm512_permutexvar_epi64() {
9833 let idx = _mm512_set1_epi64(1);
9834 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9835 let r = _mm512_permutexvar_epi64(idx, a);
9836 let e = _mm512_set1_epi64(6);
9837 assert_eq_m512i(r, e);
9838 }
9839
9840 #[simd_test(enable = "avx512f")]
9841 unsafe fn test_mm512_mask_permutexvar_epi64() {
9842 let idx = _mm512_set1_epi64(1);
9843 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9844 let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9845 assert_eq_m512i(r, a);
9846 let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9847 let e = _mm512_set1_epi64(6);
9848 assert_eq_m512i(r, e);
9849 }
9850
9851 #[simd_test(enable = "avx512f")]
9852 unsafe fn test_mm512_maskz_permutexvar_epi64() {
9853 let idx = _mm512_set1_epi64(1);
9854 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9855 let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9856 assert_eq_m512i(r, _mm512_setzero_si512());
9857 let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9858 let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9859 assert_eq_m512i(r, e);
9860 }
9861
9862 #[simd_test(enable = "avx512f,avx512vl")]
9863 unsafe fn test_mm256_permutexvar_epi64() {
9864 let idx = _mm256_set1_epi64x(1);
9865 let a = _mm256_set_epi64x(0, 1, 2, 3);
9866 let r = _mm256_permutexvar_epi64(idx, a);
9867 let e = _mm256_set1_epi64x(2);
9868 assert_eq_m256i(r, e);
9869 }
9870
9871 #[simd_test(enable = "avx512f,avx512vl")]
9872 unsafe fn test_mm256_mask_permutexvar_epi64() {
9873 let idx = _mm256_set1_epi64x(1);
9874 let a = _mm256_set_epi64x(0, 1, 2, 3);
9875 let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9876 assert_eq_m256i(r, a);
9877 let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9878 let e = _mm256_set1_epi64x(2);
9879 assert_eq_m256i(r, e);
9880 }
9881
9882 #[simd_test(enable = "avx512f,avx512vl")]
9883 unsafe fn test_mm256_maskz_permutexvar_epi64() {
9884 let idx = _mm256_set1_epi64x(1);
9885 let a = _mm256_set_epi64x(0, 1, 2, 3);
9886 let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9887 assert_eq_m256i(r, _mm256_setzero_si256());
9888 let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9889 let e = _mm256_set1_epi64x(2);
9890 assert_eq_m256i(r, e);
9891 }
9892
9893 #[simd_test(enable = "avx512f")]
9894 unsafe fn test_mm512_permutexvar_pd() {
9895 let idx = _mm512_set1_epi64(1);
9896 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9897 let r = _mm512_permutexvar_pd(idx, a);
9898 let e = _mm512_set1_pd(6.);
9899 assert_eq_m512d(r, e);
9900 }
9901
9902 #[simd_test(enable = "avx512f")]
9903 unsafe fn test_mm512_mask_permutexvar_pd() {
9904 let idx = _mm512_set1_epi64(1);
9905 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9906 let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9907 assert_eq_m512d(r, a);
9908 let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9909 let e = _mm512_set1_pd(6.);
9910 assert_eq_m512d(r, e);
9911 }
9912
9913 #[simd_test(enable = "avx512f")]
9914 unsafe fn test_mm512_maskz_permutexvar_pd() {
9915 let idx = _mm512_set1_epi64(1);
9916 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9917 let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9918 assert_eq_m512d(r, _mm512_setzero_pd());
9919 let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9920 let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9921 assert_eq_m512d(r, e);
9922 }
9923
9924 #[simd_test(enable = "avx512f,avx512vl")]
9925 unsafe fn test_mm256_permutexvar_pd() {
9926 let idx = _mm256_set1_epi64x(1);
9927 let a = _mm256_set_pd(0., 1., 2., 3.);
9928 let r = _mm256_permutexvar_pd(idx, a);
9929 let e = _mm256_set1_pd(2.);
9930 assert_eq_m256d(r, e);
9931 }
9932
9933 #[simd_test(enable = "avx512f,avx512vl")]
9934 unsafe fn test_mm256_mask_permutexvar_pd() {
9935 let idx = _mm256_set1_epi64x(1);
9936 let a = _mm256_set_pd(0., 1., 2., 3.);
9937 let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9938 assert_eq_m256d(r, a);
9939 let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9940 let e = _mm256_set1_pd(2.);
9941 assert_eq_m256d(r, e);
9942 }
9943
9944 #[simd_test(enable = "avx512f,avx512vl")]
9945 unsafe fn test_mm256_maskz_permutexvar_pd() {
9946 let idx = _mm256_set1_epi64x(1);
9947 let a = _mm256_set_pd(0., 1., 2., 3.);
9948 let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9949 assert_eq_m256d(r, _mm256_setzero_pd());
9950 let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9951 let e = _mm256_set1_pd(2.);
9952 assert_eq_m256d(r, e);
9953 }
9954
9955 #[simd_test(enable = "avx512f")]
9956 unsafe fn test_mm512_permutex2var_epi64() {
9957 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9958 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9959 let b = _mm512_set1_epi64(100);
9960 let r = _mm512_permutex2var_epi64(a, idx, b);
9961 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9962 assert_eq_m512i(r, e);
9963 }
9964
9965 #[simd_test(enable = "avx512f")]
9966 unsafe fn test_mm512_mask_permutex2var_epi64() {
9967 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9968 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9969 let b = _mm512_set1_epi64(100);
9970 let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9971 assert_eq_m512i(r, a);
9972 let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9973 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9974 assert_eq_m512i(r, e);
9975 }
9976
9977 #[simd_test(enable = "avx512f")]
9978 unsafe fn test_mm512_maskz_permutex2var_epi64() {
9979 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9980 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9981 let b = _mm512_set1_epi64(100);
9982 let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9983 assert_eq_m512i(r, _mm512_setzero_si512());
9984 let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9985 let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9986 assert_eq_m512i(r, e);
9987 }
9988
9989 #[simd_test(enable = "avx512f")]
9990 unsafe fn test_mm512_mask2_permutex2var_epi64() {
9991 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9992 let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9993 let b = _mm512_set1_epi64(100);
9994 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
9995 assert_eq_m512i(r, idx);
9996 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9997 let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
9998 assert_eq_m512i(r, e);
9999 }
10000
10001 #[simd_test(enable = "avx512f,avx512vl")]
10002 unsafe fn test_mm256_permutex2var_epi64() {
10003 let a = _mm256_set_epi64x(0, 1, 2, 3);
10004 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10005 let b = _mm256_set1_epi64x(100);
10006 let r = _mm256_permutex2var_epi64(a, idx, b);
10007 let e = _mm256_set_epi64x(2, 100, 1, 100);
10008 assert_eq_m256i(r, e);
10009 }
10010
10011 #[simd_test(enable = "avx512f,avx512vl")]
10012 unsafe fn test_mm256_mask_permutex2var_epi64() {
10013 let a = _mm256_set_epi64x(0, 1, 2, 3);
10014 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10015 let b = _mm256_set1_epi64x(100);
10016 let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
10017 assert_eq_m256i(r, a);
10018 let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
10019 let e = _mm256_set_epi64x(2, 100, 1, 100);
10020 assert_eq_m256i(r, e);
10021 }
10022
10023 #[simd_test(enable = "avx512f,avx512vl")]
10024 unsafe fn test_mm256_maskz_permutex2var_epi64() {
10025 let a = _mm256_set_epi64x(0, 1, 2, 3);
10026 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10027 let b = _mm256_set1_epi64x(100);
10028 let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
10029 assert_eq_m256i(r, _mm256_setzero_si256());
10030 let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
10031 let e = _mm256_set_epi64x(2, 100, 1, 100);
10032 assert_eq_m256i(r, e);
10033 }
10034
10035 #[simd_test(enable = "avx512f,avx512vl")]
10036 unsafe fn test_mm256_mask2_permutex2var_epi64() {
10037 let a = _mm256_set_epi64x(0, 1, 2, 3);
10038 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10039 let b = _mm256_set1_epi64x(100);
10040 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
10041 assert_eq_m256i(r, idx);
10042 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10043 let e = _mm256_set_epi64x(2, 100, 1, 100);
10044 assert_eq_m256i(r, e);
10045 }
10046
10047 #[simd_test(enable = "avx512f,avx512vl")]
10048 unsafe fn test_mm_permutex2var_epi64() {
10049 let a = _mm_set_epi64x(0, 1);
10050 let idx = _mm_set_epi64x(1, 1 << 1);
10051 let b = _mm_set1_epi64x(100);
10052 let r = _mm_permutex2var_epi64(a, idx, b);
10053 let e = _mm_set_epi64x(0, 100);
10054 assert_eq_m128i(r, e);
10055 }
10056
10057 #[simd_test(enable = "avx512f,avx512vl")]
10058 unsafe fn test_mm_mask_permutex2var_epi64() {
10059 let a = _mm_set_epi64x(0, 1);
10060 let idx = _mm_set_epi64x(1, 1 << 1);
10061 let b = _mm_set1_epi64x(100);
10062 let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
10063 assert_eq_m128i(r, a);
10064 let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
10065 let e = _mm_set_epi64x(0, 100);
10066 assert_eq_m128i(r, e);
10067 }
10068
10069 #[simd_test(enable = "avx512f,avx512vl")]
10070 unsafe fn test_mm_maskz_permutex2var_epi64() {
10071 let a = _mm_set_epi64x(0, 1);
10072 let idx = _mm_set_epi64x(1, 1 << 1);
10073 let b = _mm_set1_epi64x(100);
10074 let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
10075 assert_eq_m128i(r, _mm_setzero_si128());
10076 let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
10077 let e = _mm_set_epi64x(0, 100);
10078 assert_eq_m128i(r, e);
10079 }
10080
10081 #[simd_test(enable = "avx512f,avx512vl")]
10082 unsafe fn test_mm_mask2_permutex2var_epi64() {
10083 let a = _mm_set_epi64x(0, 1);
10084 let idx = _mm_set_epi64x(1, 1 << 1);
10085 let b = _mm_set1_epi64x(100);
10086 let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
10087 assert_eq_m128i(r, idx);
10088 let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
10089 let e = _mm_set_epi64x(0, 100);
10090 assert_eq_m128i(r, e);
10091 }
10092
10093 #[simd_test(enable = "avx512f")]
10094 unsafe fn test_mm512_permutex2var_pd() {
10095 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10096 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10097 let b = _mm512_set1_pd(100.);
10098 let r = _mm512_permutex2var_pd(a, idx, b);
10099 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10100 assert_eq_m512d(r, e);
10101 }
10102
10103 #[simd_test(enable = "avx512f")]
10104 unsafe fn test_mm512_mask_permutex2var_pd() {
10105 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10106 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10107 let b = _mm512_set1_pd(100.);
10108 let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
10109 assert_eq_m512d(r, a);
10110 let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
10111 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10112 assert_eq_m512d(r, e);
10113 }
10114
10115 #[simd_test(enable = "avx512f")]
10116 unsafe fn test_mm512_maskz_permutex2var_pd() {
10117 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10118 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10119 let b = _mm512_set1_pd(100.);
10120 let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
10121 assert_eq_m512d(r, _mm512_setzero_pd());
10122 let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
10123 let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
10124 assert_eq_m512d(r, e);
10125 }
10126
10127 #[simd_test(enable = "avx512f")]
10128 unsafe fn test_mm512_mask2_permutex2var_pd() {
10129 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10130 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10131 let b = _mm512_set1_pd(100.);
10132 let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
10133 assert_eq_m512d(r, _mm512_castsi512_pd(idx));
10134 let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
10135 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10136 assert_eq_m512d(r, e);
10137 }
10138
10139 #[simd_test(enable = "avx512f,avx512vl")]
10140 unsafe fn test_mm256_permutex2var_pd() {
10141 let a = _mm256_set_pd(0., 1., 2., 3.);
10142 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10143 let b = _mm256_set1_pd(100.);
10144 let r = _mm256_permutex2var_pd(a, idx, b);
10145 let e = _mm256_set_pd(2., 100., 1., 100.);
10146 assert_eq_m256d(r, e);
10147 }
10148
10149 #[simd_test(enable = "avx512f,avx512vl")]
10150 unsafe fn test_mm256_mask_permutex2var_pd() {
10151 let a = _mm256_set_pd(0., 1., 2., 3.);
10152 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10153 let b = _mm256_set1_pd(100.);
10154 let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
10155 assert_eq_m256d(r, a);
10156 let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
10157 let e = _mm256_set_pd(2., 100., 1., 100.);
10158 assert_eq_m256d(r, e);
10159 }
10160
10161 #[simd_test(enable = "avx512f,avx512vl")]
10162 unsafe fn test_mm256_maskz_permutex2var_pd() {
10163 let a = _mm256_set_pd(0., 1., 2., 3.);
10164 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10165 let b = _mm256_set1_pd(100.);
10166 let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
10167 assert_eq_m256d(r, _mm256_setzero_pd());
10168 let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
10169 let e = _mm256_set_pd(2., 100., 1., 100.);
10170 assert_eq_m256d(r, e);
10171 }
10172
10173 #[simd_test(enable = "avx512f,avx512vl")]
10174 unsafe fn test_mm256_mask2_permutex2var_pd() {
10175 let a = _mm256_set_pd(0., 1., 2., 3.);
10176 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10177 let b = _mm256_set1_pd(100.);
10178 let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
10179 assert_eq_m256d(r, _mm256_castsi256_pd(idx));
10180 let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
10181 let e = _mm256_set_pd(2., 100., 1., 100.);
10182 assert_eq_m256d(r, e);
10183 }
10184
10185 #[simd_test(enable = "avx512f,avx512vl")]
10186 unsafe fn test_mm_permutex2var_pd() {
10187 let a = _mm_set_pd(0., 1.);
10188 let idx = _mm_set_epi64x(1, 1 << 1);
10189 let b = _mm_set1_pd(100.);
10190 let r = _mm_permutex2var_pd(a, idx, b);
10191 let e = _mm_set_pd(0., 100.);
10192 assert_eq_m128d(r, e);
10193 }
10194
10195 #[simd_test(enable = "avx512f,avx512vl")]
10196 unsafe fn test_mm_mask_permutex2var_pd() {
10197 let a = _mm_set_pd(0., 1.);
10198 let idx = _mm_set_epi64x(1, 1 << 1);
10199 let b = _mm_set1_pd(100.);
10200 let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
10201 assert_eq_m128d(r, a);
10202 let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
10203 let e = _mm_set_pd(0., 100.);
10204 assert_eq_m128d(r, e);
10205 }
10206
10207 #[simd_test(enable = "avx512f,avx512vl")]
10208 unsafe fn test_mm_maskz_permutex2var_pd() {
10209 let a = _mm_set_pd(0., 1.);
10210 let idx = _mm_set_epi64x(1, 1 << 1);
10211 let b = _mm_set1_pd(100.);
10212 let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
10213 assert_eq_m128d(r, _mm_setzero_pd());
10214 let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
10215 let e = _mm_set_pd(0., 100.);
10216 assert_eq_m128d(r, e);
10217 }
10218
10219 #[simd_test(enable = "avx512f,avx512vl")]
10220 unsafe fn test_mm_mask2_permutex2var_pd() {
10221 let a = _mm_set_pd(0., 1.);
10222 let idx = _mm_set_epi64x(1, 1 << 1);
10223 let b = _mm_set1_pd(100.);
10224 let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
10225 assert_eq_m128d(r, _mm_castsi128_pd(idx));
10226 let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
10227 let e = _mm_set_pd(0., 100.);
10228 assert_eq_m128d(r, e);
10229 }
10230
10231 #[simd_test(enable = "avx512f,avx512vl")]
10232 unsafe fn test_mm256_mask_shuffle_pd() {
10233 let a = _mm256_set_pd(1., 4., 5., 8.);
10234 let b = _mm256_set_pd(2., 3., 6., 7.);
10235 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10236 assert_eq_m256d(r, a);
10237 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
10238 let e = _mm256_set_pd(2., 1., 6., 5.);
10239 assert_eq_m256d(r, e);
10240 }
10241
10242 #[simd_test(enable = "avx512f,avx512vl")]
10243 unsafe fn test_mm256_maskz_shuffle_pd() {
10244 let a = _mm256_set_pd(1., 4., 5., 8.);
10245 let b = _mm256_set_pd(2., 3., 6., 7.);
10246 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10247 assert_eq_m256d(r, _mm256_setzero_pd());
10248 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
10249 let e = _mm256_set_pd(2., 1., 6., 5.);
10250 assert_eq_m256d(r, e);
10251 }
10252
10253 #[simd_test(enable = "avx512f,avx512vl")]
10254 unsafe fn test_mm_mask_shuffle_pd() {
10255 let a = _mm_set_pd(1., 4.);
10256 let b = _mm_set_pd(2., 3.);
10257 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10258 assert_eq_m128d(r, a);
10259 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
10260 let e = _mm_set_pd(2., 1.);
10261 assert_eq_m128d(r, e);
10262 }
10263
10264 #[simd_test(enable = "avx512f,avx512vl")]
10265 unsafe fn test_mm_maskz_shuffle_pd() {
10266 let a = _mm_set_pd(1., 4.);
10267 let b = _mm_set_pd(2., 3.);
10268 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10269 assert_eq_m128d(r, _mm_setzero_pd());
10270 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
10271 let e = _mm_set_pd(2., 1.);
10272 assert_eq_m128d(r, e);
10273 }
10274
10275 #[simd_test(enable = "avx512f")]
10276 unsafe fn test_mm512_shuffle_i64x2() {
10277 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10278 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10279 let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
10280 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10281 assert_eq_m512i(r, e);
10282 }
10283
10284 #[simd_test(enable = "avx512f")]
10285 unsafe fn test_mm512_mask_shuffle_i64x2() {
10286 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10287 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10288 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
10289 assert_eq_m512i(r, a);
10290 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10291 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10292 assert_eq_m512i(r, e);
10293 }
10294
10295 #[simd_test(enable = "avx512f")]
10296 unsafe fn test_mm512_maskz_shuffle_i64x2() {
10297 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10298 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10299 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
10300 assert_eq_m512i(r, _mm512_setzero_si512());
10301 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
10302 let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
10303 assert_eq_m512i(r, e);
10304 }
10305
10306 #[simd_test(enable = "avx512f,avx512vl")]
10307 unsafe fn test_mm256_shuffle_i64x2() {
10308 let a = _mm256_set_epi64x(1, 4, 5, 8);
10309 let b = _mm256_set_epi64x(2, 3, 6, 7);
10310 let r = _mm256_shuffle_i64x2::<0b00>(a, b);
10311 let e = _mm256_set_epi64x(6, 7, 5, 8);
10312 assert_eq_m256i(r, e);
10313 }
10314
10315 #[simd_test(enable = "avx512f,avx512vl")]
10316 unsafe fn test_mm256_mask_shuffle_i64x2() {
10317 let a = _mm256_set_epi64x(1, 4, 5, 8);
10318 let b = _mm256_set_epi64x(2, 3, 6, 7);
10319 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
10320 assert_eq_m256i(r, a);
10321 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
10322 let e = _mm256_set_epi64x(6, 7, 5, 8);
10323 assert_eq_m256i(r, e);
10324 }
10325
10326 #[simd_test(enable = "avx512f,avx512vl")]
10327 unsafe fn test_mm256_maskz_shuffle_i64x2() {
10328 let a = _mm256_set_epi64x(1, 4, 5, 8);
10329 let b = _mm256_set_epi64x(2, 3, 6, 7);
10330 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
10331 assert_eq_m256i(r, _mm256_setzero_si256());
10332 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
10333 let e = _mm256_set_epi64x(6, 7, 5, 8);
10334 assert_eq_m256i(r, e);
10335 }
10336
10337 #[simd_test(enable = "avx512f")]
10338 unsafe fn test_mm512_shuffle_f64x2() {
10339 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10340 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10341 let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
10342 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10343 assert_eq_m512d(r, e);
10344 }
10345
10346 #[simd_test(enable = "avx512f")]
10347 unsafe fn test_mm512_mask_shuffle_f64x2() {
10348 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10349 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10350 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
10351 assert_eq_m512d(r, a);
10352 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10353 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10354 assert_eq_m512d(r, e);
10355 }
10356
10357 #[simd_test(enable = "avx512f")]
10358 unsafe fn test_mm512_maskz_shuffle_f64x2() {
10359 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10360 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10361 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
10362 assert_eq_m512d(r, _mm512_setzero_pd());
10363 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
10364 let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
10365 assert_eq_m512d(r, e);
10366 }
10367
10368 #[simd_test(enable = "avx512f,avx512vl")]
10369 unsafe fn test_mm256_shuffle_f64x2() {
10370 let a = _mm256_set_pd(1., 4., 5., 8.);
10371 let b = _mm256_set_pd(2., 3., 6., 7.);
10372 let r = _mm256_shuffle_f64x2::<0b00>(a, b);
10373 let e = _mm256_set_pd(6., 7., 5., 8.);
10374 assert_eq_m256d(r, e);
10375 }
10376
10377 #[simd_test(enable = "avx512f,avx512vl")]
10378 unsafe fn test_mm256_mask_shuffle_f64x2() {
10379 let a = _mm256_set_pd(1., 4., 5., 8.);
10380 let b = _mm256_set_pd(2., 3., 6., 7.);
10381 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
10382 assert_eq_m256d(r, a);
10383 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
10384 let e = _mm256_set_pd(6., 7., 5., 8.);
10385 assert_eq_m256d(r, e);
10386 }
10387
10388 #[simd_test(enable = "avx512f,avx512vl")]
10389 unsafe fn test_mm256_maskz_shuffle_f64x2() {
10390 let a = _mm256_set_pd(1., 4., 5., 8.);
10391 let b = _mm256_set_pd(2., 3., 6., 7.);
10392 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
10393 assert_eq_m256d(r, _mm256_setzero_pd());
10394 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
10395 let e = _mm256_set_pd(6., 7., 5., 8.);
10396 assert_eq_m256d(r, e);
10397 }
10398
10399 #[simd_test(enable = "avx512f")]
10400 unsafe fn test_mm512_movedup_pd() {
10401 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10402 let r = _mm512_movedup_pd(a);
10403 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10404 assert_eq_m512d(r, e);
10405 }
10406
10407 #[simd_test(enable = "avx512f")]
10408 unsafe fn test_mm512_mask_movedup_pd() {
10409 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10410 let r = _mm512_mask_movedup_pd(a, 0, a);
10411 assert_eq_m512d(r, a);
10412 let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
10413 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10414 assert_eq_m512d(r, e);
10415 }
10416
10417 #[simd_test(enable = "avx512f")]
10418 unsafe fn test_mm512_maskz_movedup_pd() {
10419 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10420 let r = _mm512_maskz_movedup_pd(0, a);
10421 assert_eq_m512d(r, _mm512_setzero_pd());
10422 let r = _mm512_maskz_movedup_pd(0b00001111, a);
10423 let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
10424 assert_eq_m512d(r, e);
10425 }
10426
10427 #[simd_test(enable = "avx512f,avx512vl")]
10428 unsafe fn test_mm256_mask_movedup_pd() {
10429 let a = _mm256_set_pd(1., 2., 3., 4.);
10430 let r = _mm256_mask_movedup_pd(a, 0, a);
10431 assert_eq_m256d(r, a);
10432 let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
10433 let e = _mm256_set_pd(2., 2., 4., 4.);
10434 assert_eq_m256d(r, e);
10435 }
10436
10437 #[simd_test(enable = "avx512f,avx512vl")]
10438 unsafe fn test_mm256_maskz_movedup_pd() {
10439 let a = _mm256_set_pd(1., 2., 3., 4.);
10440 let r = _mm256_maskz_movedup_pd(0, a);
10441 assert_eq_m256d(r, _mm256_setzero_pd());
10442 let r = _mm256_maskz_movedup_pd(0b00001111, a);
10443 let e = _mm256_set_pd(2., 2., 4., 4.);
10444 assert_eq_m256d(r, e);
10445 }
10446
10447 #[simd_test(enable = "avx512f,avx512vl")]
10448 unsafe fn test_mm_mask_movedup_pd() {
10449 let a = _mm_set_pd(1., 2.);
10450 let r = _mm_mask_movedup_pd(a, 0, a);
10451 assert_eq_m128d(r, a);
10452 let r = _mm_mask_movedup_pd(a, 0b00000011, a);
10453 let e = _mm_set_pd(2., 2.);
10454 assert_eq_m128d(r, e);
10455 }
10456
10457 #[simd_test(enable = "avx512f,avx512vl")]
10458 unsafe fn test_mm_maskz_movedup_pd() {
10459 let a = _mm_set_pd(1., 2.);
10460 let r = _mm_maskz_movedup_pd(0, a);
10461 assert_eq_m128d(r, _mm_setzero_pd());
10462 let r = _mm_maskz_movedup_pd(0b00000011, a);
10463 let e = _mm_set_pd(2., 2.);
10464 assert_eq_m128d(r, e);
10465 }
10466
10467 #[simd_test(enable = "avx512f")]
10468 unsafe fn test_mm512_inserti64x4() {
10469 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10470 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10471 let r = _mm512_inserti64x4::<1>(a, b);
10472 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10473 assert_eq_m512i(r, e);
10474 }
10475
10476 #[simd_test(enable = "avx512f")]
10477 unsafe fn test_mm512_mask_inserti64x4() {
10478 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10479 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10480 let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
10481 assert_eq_m512i(r, a);
10482 let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
10483 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10484 assert_eq_m512i(r, e);
10485 }
10486
10487 #[simd_test(enable = "avx512f")]
10488 unsafe fn test_mm512_maskz_inserti64x4() {
10489 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10490 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10491 let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
10492 assert_eq_m512i(r, _mm512_setzero_si512());
10493 let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
10494 let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
10495 assert_eq_m512i(r, e);
10496 }
10497
10498 #[simd_test(enable = "avx512f")]
10499 unsafe fn test_mm512_insertf64x4() {
10500 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10501 let b = _mm256_setr_pd(17., 18., 19., 20.);
10502 let r = _mm512_insertf64x4::<1>(a, b);
10503 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10504 assert_eq_m512d(r, e);
10505 }
10506
10507 #[simd_test(enable = "avx512f")]
10508 unsafe fn test_mm512_mask_insertf64x4() {
10509 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10510 let b = _mm256_setr_pd(17., 18., 19., 20.);
10511 let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
10512 assert_eq_m512d(r, a);
10513 let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
10514 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10515 assert_eq_m512d(r, e);
10516 }
10517
10518 #[simd_test(enable = "avx512f")]
10519 unsafe fn test_mm512_maskz_insertf64x4() {
10520 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10521 let b = _mm256_setr_pd(17., 18., 19., 20.);
10522 let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
10523 assert_eq_m512d(r, _mm512_setzero_pd());
10524 let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
10525 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
10526 assert_eq_m512d(r, e);
10527 }
10528
10529 #[simd_test(enable = "avx512f")]
10530 unsafe fn test_mm512_castpd128_pd512() {
10531 let a = _mm_setr_pd(17., 18.);
10532 let r = _mm512_castpd128_pd512(a);
10533 assert_eq_m128d(_mm512_castpd512_pd128(r), a);
10534 }
10535
10536 #[simd_test(enable = "avx512f")]
10537 unsafe fn test_mm512_castpd256_pd512() {
10538 let a = _mm256_setr_pd(17., 18., 19., 20.);
10539 let r = _mm512_castpd256_pd512(a);
10540 assert_eq_m256d(_mm512_castpd512_pd256(r), a);
10541 }
10542
10543 #[simd_test(enable = "avx512f")]
10544 unsafe fn test_mm512_zextpd128_pd512() {
10545 let a = _mm_setr_pd(17., 18.);
10546 let r = _mm512_zextpd128_pd512(a);
10547 let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
10548 assert_eq_m512d(r, e);
10549 }
10550
10551 #[simd_test(enable = "avx512f")]
10552 unsafe fn test_mm512_zextpd256_pd512() {
10553 let a = _mm256_setr_pd(17., 18., 19., 20.);
10554 let r = _mm512_zextpd256_pd512(a);
10555 let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
10556 assert_eq_m512d(r, e);
10557 }
10558
10559 #[simd_test(enable = "avx512f")]
10560 unsafe fn test_mm512_castpd512_pd128() {
10561 let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
10562 let r = _mm512_castpd512_pd128(a);
10563 let e = _mm_setr_pd(17., 18.);
10564 assert_eq_m128d(r, e);
10565 }
10566
10567 #[simd_test(enable = "avx512f")]
10568 unsafe fn test_mm512_castpd512_pd256() {
10569 let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
10570 let r = _mm512_castpd512_pd256(a);
10571 let e = _mm256_setr_pd(17., 18., 19., 20.);
10572 assert_eq_m256d(r, e);
10573 }
10574
10575 #[simd_test(enable = "avx512f")]
10576 unsafe fn test_mm512_castpd_ps() {
10577 let a = _mm512_set1_pd(1.);
10578 let r = _mm512_castpd_ps(a);
10579 let e = _mm512_set_ps(
10580 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
10581 1.875, 0.0,
10582 );
10583 assert_eq_m512(r, e);
10584 }
10585
10586 #[simd_test(enable = "avx512f")]
10587 unsafe fn test_mm512_castpd_si512() {
10588 let a = _mm512_set1_pd(1.);
10589 let r = _mm512_castpd_si512(a);
10590 let e = _mm512_set_epi32(
10591 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
10592 0, 1072693248, 0, 1072693248, 0,
10593 );
10594 assert_eq_m512i(r, e);
10595 }
10596
10597 #[simd_test(enable = "avx512f")]
10598 unsafe fn test_mm512_castsi128_si512() {
10599 let a = _mm_setr_epi64x(17, 18);
10600 let r = _mm512_castsi128_si512(a);
10601 assert_eq_m128i(_mm512_castsi512_si128(r), a);
10602 }
10603
10604 #[simd_test(enable = "avx512f")]
10605 unsafe fn test_mm512_castsi256_si512() {
10606 let a = _mm256_setr_epi64x(17, 18, 19, 20);
10607 let r = _mm512_castsi256_si512(a);
10608 assert_eq_m256i(_mm512_castsi512_si256(r), a);
10609 }
10610
10611 #[simd_test(enable = "avx512f")]
10612 unsafe fn test_mm512_zextsi128_si512() {
10613 let a = _mm_setr_epi64x(17, 18);
10614 let r = _mm512_zextsi128_si512(a);
10615 let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
10616 assert_eq_m512i(r, e);
10617 }
10618
10619 #[simd_test(enable = "avx512f")]
10620 unsafe fn test_mm512_zextsi256_si512() {
10621 let a = _mm256_setr_epi64x(17, 18, 19, 20);
10622 let r = _mm512_zextsi256_si512(a);
10623 let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
10624 assert_eq_m512i(r, e);
10625 }
10626
10627 #[simd_test(enable = "avx512f")]
10628 unsafe fn test_mm512_castsi512_si128() {
10629 let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
10630 let r = _mm512_castsi512_si128(a);
10631 let e = _mm_setr_epi64x(17, 18);
10632 assert_eq_m128i(r, e);
10633 }
10634
10635 #[simd_test(enable = "avx512f")]
10636 unsafe fn test_mm512_castsi512_si256() {
10637 let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
10638 let r = _mm512_castsi512_si256(a);
10639 let e = _mm256_setr_epi64x(17, 18, 19, 20);
10640 assert_eq_m256i(r, e);
10641 }
10642
10643 #[simd_test(enable = "avx512f")]
10644 unsafe fn test_mm512_castsi512_ps() {
10645 let a = _mm512_set1_epi64(1 << 62);
10646 let r = _mm512_castsi512_ps(a);
10647 let e = _mm512_set_ps(
10648 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
10649 );
10650 assert_eq_m512(r, e);
10651 }
10652
10653 #[simd_test(enable = "avx512f")]
10654 unsafe fn test_mm512_castsi512_pd() {
10655 let a = _mm512_set1_epi64(1 << 62);
10656 let r = _mm512_castsi512_pd(a);
10657 let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
10658 assert_eq_m512d(r, e);
10659 }
10660
10661 #[simd_test(enable = "avx512f")]
10662 unsafe fn test_mm512_broadcastq_epi64() {
10663 let a = _mm_setr_epi64x(17, 18);
10664 let r = _mm512_broadcastq_epi64(a);
10665 let e = _mm512_set1_epi64(17);
10666 assert_eq_m512i(r, e);
10667 }
10668
10669 #[simd_test(enable = "avx512f")]
10670 unsafe fn test_mm512_mask_broadcastq_epi64() {
10671 let src = _mm512_set1_epi64(18);
10672 let a = _mm_setr_epi64x(17, 18);
10673 let r = _mm512_mask_broadcastq_epi64(src, 0, a);
10674 assert_eq_m512i(r, src);
10675 let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
10676 let e = _mm512_set1_epi64(17);
10677 assert_eq_m512i(r, e);
10678 }
10679
10680 #[simd_test(enable = "avx512f")]
10681 unsafe fn test_mm512_maskz_broadcastq_epi64() {
10682 let a = _mm_setr_epi64x(17, 18);
10683 let r = _mm512_maskz_broadcastq_epi64(0, a);
10684 assert_eq_m512i(r, _mm512_setzero_si512());
10685 let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10686 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10687 assert_eq_m512i(r, e);
10688 }
10689
10690 #[simd_test(enable = "avx512f,avx512vl")]
10691 unsafe fn test_mm256_mask_broadcastq_epi64() {
10692 let src = _mm256_set1_epi64x(18);
10693 let a = _mm_set_epi64x(17, 18);
10694 let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10695 assert_eq_m256i(r, src);
10696 let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10697 let e = _mm256_set1_epi64x(18);
10698 assert_eq_m256i(r, e);
10699 }
10700
10701 #[simd_test(enable = "avx512f,avx512vl")]
10702 unsafe fn test_mm256_maskz_broadcastq_epi64() {
10703 let a = _mm_set_epi64x(17, 18);
10704 let r = _mm256_maskz_broadcastq_epi64(0, a);
10705 assert_eq_m256i(r, _mm256_setzero_si256());
10706 let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10707 let e = _mm256_set1_epi64x(18);
10708 assert_eq_m256i(r, e);
10709 }
10710
10711 #[simd_test(enable = "avx512f,avx512vl")]
10712 unsafe fn test_mm_mask_broadcastq_epi64() {
10713 let src = _mm_set1_epi64x(18);
10714 let a = _mm_set_epi64x(17, 18);
10715 let r = _mm_mask_broadcastq_epi64(src, 0, a);
10716 assert_eq_m128i(r, src);
10717 let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10718 let e = _mm_set1_epi64x(18);
10719 assert_eq_m128i(r, e);
10720 }
10721
10722 #[simd_test(enable = "avx512f,avx512vl")]
10723 unsafe fn test_mm_maskz_broadcastq_epi64() {
10724 let a = _mm_set_epi64x(17, 18);
10725 let r = _mm_maskz_broadcastq_epi64(0, a);
10726 assert_eq_m128i(r, _mm_setzero_si128());
10727 let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10728 let e = _mm_set1_epi64x(18);
10729 assert_eq_m128i(r, e);
10730 }
10731
10732 #[simd_test(enable = "avx512f")]
10733 unsafe fn test_mm512_broadcastsd_pd() {
10734 let a = _mm_set_pd(17., 18.);
10735 let r = _mm512_broadcastsd_pd(a);
10736 let e = _mm512_set1_pd(18.);
10737 assert_eq_m512d(r, e);
10738 }
10739
10740 #[simd_test(enable = "avx512f")]
10741 unsafe fn test_mm512_mask_broadcastsd_pd() {
10742 let src = _mm512_set1_pd(18.);
10743 let a = _mm_set_pd(17., 18.);
10744 let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10745 assert_eq_m512d(r, src);
10746 let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10747 let e = _mm512_set1_pd(18.);
10748 assert_eq_m512d(r, e);
10749 }
10750
10751 #[simd_test(enable = "avx512f")]
10752 unsafe fn test_mm512_maskz_broadcastsd_pd() {
10753 let a = _mm_set_pd(17., 18.);
10754 let r = _mm512_maskz_broadcastsd_pd(0, a);
10755 assert_eq_m512d(r, _mm512_setzero_pd());
10756 let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10757 let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10758 assert_eq_m512d(r, e);
10759 }
10760
10761 #[simd_test(enable = "avx512f,avx512vl")]
10762 unsafe fn test_mm256_mask_broadcastsd_pd() {
10763 let src = _mm256_set1_pd(18.);
10764 let a = _mm_set_pd(17., 18.);
10765 let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10766 assert_eq_m256d(r, src);
10767 let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10768 let e = _mm256_set1_pd(18.);
10769 assert_eq_m256d(r, e);
10770 }
10771
10772 #[simd_test(enable = "avx512f,avx512vl")]
10773 unsafe fn test_mm256_maskz_broadcastsd_pd() {
10774 let a = _mm_set_pd(17., 18.);
10775 let r = _mm256_maskz_broadcastsd_pd(0, a);
10776 assert_eq_m256d(r, _mm256_setzero_pd());
10777 let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10778 let e = _mm256_set1_pd(18.);
10779 assert_eq_m256d(r, e);
10780 }
10781
10782 #[simd_test(enable = "avx512f")]
10783 unsafe fn test_mm512_broadcast_i64x4() {
10784 let a = _mm256_set_epi64x(17, 18, 19, 20);
10785 let r = _mm512_broadcast_i64x4(a);
10786 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10787 assert_eq_m512i(r, e);
10788 }
10789
10790 #[simd_test(enable = "avx512f")]
10791 unsafe fn test_mm512_mask_broadcast_i64x4() {
10792 let src = _mm512_set1_epi64(18);
10793 let a = _mm256_set_epi64x(17, 18, 19, 20);
10794 let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10795 assert_eq_m512i(r, src);
10796 let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10797 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10798 assert_eq_m512i(r, e);
10799 }
10800
10801 #[simd_test(enable = "avx512f")]
10802 unsafe fn test_mm512_maskz_broadcast_i64x4() {
10803 let a = _mm256_set_epi64x(17, 18, 19, 20);
10804 let r = _mm512_maskz_broadcast_i64x4(0, a);
10805 assert_eq_m512i(r, _mm512_setzero_si512());
10806 let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10807 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10808 assert_eq_m512i(r, e);
10809 }
10810
10811 #[simd_test(enable = "avx512f")]
10812 unsafe fn test_mm512_broadcast_f64x4() {
10813 let a = _mm256_set_pd(17., 18., 19., 20.);
10814 let r = _mm512_broadcast_f64x4(a);
10815 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10816 assert_eq_m512d(r, e);
10817 }
10818
10819 #[simd_test(enable = "avx512f")]
10820 unsafe fn test_mm512_mask_broadcast_f64x4() {
10821 let src = _mm512_set1_pd(18.);
10822 let a = _mm256_set_pd(17., 18., 19., 20.);
10823 let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10824 assert_eq_m512d(r, src);
10825 let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10826 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10827 assert_eq_m512d(r, e);
10828 }
10829
10830 #[simd_test(enable = "avx512f")]
10831 unsafe fn test_mm512_maskz_broadcast_f64x4() {
10832 let a = _mm256_set_pd(17., 18., 19., 20.);
10833 let r = _mm512_maskz_broadcast_f64x4(0, a);
10834 assert_eq_m512d(r, _mm512_setzero_pd());
10835 let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10836 let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10837 assert_eq_m512d(r, e);
10838 }
10839
10840 #[simd_test(enable = "avx512f")]
10841 unsafe fn test_mm512_mask_blend_epi64() {
10842 let a = _mm512_set1_epi64(1);
10843 let b = _mm512_set1_epi64(2);
10844 let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10845 let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10846 assert_eq_m512i(r, e);
10847 }
10848
10849 #[simd_test(enable = "avx512f,avx512vl")]
10850 unsafe fn test_mm256_mask_blend_epi64() {
10851 let a = _mm256_set1_epi64x(1);
10852 let b = _mm256_set1_epi64x(2);
10853 let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10854 let e = _mm256_set1_epi64x(2);
10855 assert_eq_m256i(r, e);
10856 }
10857
10858 #[simd_test(enable = "avx512f,avx512vl")]
10859 unsafe fn test_mm_mask_blend_epi64() {
10860 let a = _mm_set1_epi64x(1);
10861 let b = _mm_set1_epi64x(2);
10862 let r = _mm_mask_blend_epi64(0b00000011, a, b);
10863 let e = _mm_set1_epi64x(2);
10864 assert_eq_m128i(r, e);
10865 }
10866
10867 #[simd_test(enable = "avx512f")]
10868 unsafe fn test_mm512_mask_blend_pd() {
10869 let a = _mm512_set1_pd(1.);
10870 let b = _mm512_set1_pd(2.);
10871 let r = _mm512_mask_blend_pd(0b11110000, a, b);
10872 let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10873 assert_eq_m512d(r, e);
10874 }
10875
10876 #[simd_test(enable = "avx512f,avx512vl")]
10877 unsafe fn test_mm256_mask_blend_pd() {
10878 let a = _mm256_set1_pd(1.);
10879 let b = _mm256_set1_pd(2.);
10880 let r = _mm256_mask_blend_pd(0b00001111, a, b);
10881 let e = _mm256_set1_pd(2.);
10882 assert_eq_m256d(r, e);
10883 }
10884
10885 #[simd_test(enable = "avx512f,avx512vl")]
10886 unsafe fn test_mm_mask_blend_pd() {
10887 let a = _mm_set1_pd(1.);
10888 let b = _mm_set1_pd(2.);
10889 let r = _mm_mask_blend_pd(0b00000011, a, b);
10890 let e = _mm_set1_pd(2.);
10891 assert_eq_m128d(r, e);
10892 }
10893
10894 #[simd_test(enable = "avx512f")]
10895 unsafe fn test_mm512_unpackhi_epi64() {
10896 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10897 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10898 let r = _mm512_unpackhi_epi64(a, b);
10899 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10900 assert_eq_m512i(r, e);
10901 }
10902
10903 #[simd_test(enable = "avx512f")]
10904 unsafe fn test_mm512_mask_unpackhi_epi64() {
10905 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10906 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10907 let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10908 assert_eq_m512i(r, a);
10909 let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10910 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10911 assert_eq_m512i(r, e);
10912 }
10913
10914 #[simd_test(enable = "avx512f")]
10915 unsafe fn test_mm512_maskz_unpackhi_epi64() {
10916 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10917 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10918 let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10919 assert_eq_m512i(r, _mm512_setzero_si512());
10920 let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10921 let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10922 assert_eq_m512i(r, e);
10923 }
10924
10925 #[simd_test(enable = "avx512f,avx512vl")]
10926 unsafe fn test_mm256_mask_unpackhi_epi64() {
10927 let a = _mm256_set_epi64x(1, 2, 3, 4);
10928 let b = _mm256_set_epi64x(17, 18, 19, 20);
10929 let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10930 assert_eq_m256i(r, a);
10931 let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10932 let e = _mm256_set_epi64x(17, 1, 19, 3);
10933 assert_eq_m256i(r, e);
10934 }
10935
10936 #[simd_test(enable = "avx512f,avx512vl")]
10937 unsafe fn test_mm256_maskz_unpackhi_epi64() {
10938 let a = _mm256_set_epi64x(1, 2, 3, 4);
10939 let b = _mm256_set_epi64x(17, 18, 19, 20);
10940 let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10941 assert_eq_m256i(r, _mm256_setzero_si256());
10942 let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10943 let e = _mm256_set_epi64x(17, 1, 19, 3);
10944 assert_eq_m256i(r, e);
10945 }
10946
10947 #[simd_test(enable = "avx512f,avx512vl")]
10948 unsafe fn test_mm_mask_unpackhi_epi64() {
10949 let a = _mm_set_epi64x(1, 2);
10950 let b = _mm_set_epi64x(17, 18);
10951 let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10952 assert_eq_m128i(r, a);
10953 let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10954 let e = _mm_set_epi64x(17, 1);
10955 assert_eq_m128i(r, e);
10956 }
10957
10958 #[simd_test(enable = "avx512f,avx512vl")]
10959 unsafe fn test_mm_maskz_unpackhi_epi64() {
10960 let a = _mm_set_epi64x(1, 2);
10961 let b = _mm_set_epi64x(17, 18);
10962 let r = _mm_maskz_unpackhi_epi64(0, a, b);
10963 assert_eq_m128i(r, _mm_setzero_si128());
10964 let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10965 let e = _mm_set_epi64x(17, 1);
10966 assert_eq_m128i(r, e);
10967 }
10968
10969 #[simd_test(enable = "avx512f")]
10970 unsafe fn test_mm512_unpackhi_pd() {
10971 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10972 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10973 let r = _mm512_unpackhi_pd(a, b);
10974 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10975 assert_eq_m512d(r, e);
10976 }
10977
10978 #[simd_test(enable = "avx512f")]
10979 unsafe fn test_mm512_mask_unpackhi_pd() {
10980 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10981 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10982 let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10983 assert_eq_m512d(r, a);
10984 let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10985 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10986 assert_eq_m512d(r, e);
10987 }
10988
10989 #[simd_test(enable = "avx512f")]
10990 unsafe fn test_mm512_maskz_unpackhi_pd() {
10991 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10992 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10993 let r = _mm512_maskz_unpackhi_pd(0, a, b);
10994 assert_eq_m512d(r, _mm512_setzero_pd());
10995 let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
10996 let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
10997 assert_eq_m512d(r, e);
10998 }
10999
11000 #[simd_test(enable = "avx512f,avx512vl")]
11001 unsafe fn test_mm256_mask_unpackhi_pd() {
11002 let a = _mm256_set_pd(1., 2., 3., 4.);
11003 let b = _mm256_set_pd(17., 18., 19., 20.);
11004 let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
11005 assert_eq_m256d(r, a);
11006 let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
11007 let e = _mm256_set_pd(17., 1., 19., 3.);
11008 assert_eq_m256d(r, e);
11009 }
11010
11011 #[simd_test(enable = "avx512f,avx512vl")]
11012 unsafe fn test_mm256_maskz_unpackhi_pd() {
11013 let a = _mm256_set_pd(1., 2., 3., 4.);
11014 let b = _mm256_set_pd(17., 18., 19., 20.);
11015 let r = _mm256_maskz_unpackhi_pd(0, a, b);
11016 assert_eq_m256d(r, _mm256_setzero_pd());
11017 let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
11018 let e = _mm256_set_pd(17., 1., 19., 3.);
11019 assert_eq_m256d(r, e);
11020 }
11021
11022 #[simd_test(enable = "avx512f,avx512vl")]
11023 unsafe fn test_mm_mask_unpackhi_pd() {
11024 let a = _mm_set_pd(1., 2.);
11025 let b = _mm_set_pd(17., 18.);
11026 let r = _mm_mask_unpackhi_pd(a, 0, a, b);
11027 assert_eq_m128d(r, a);
11028 let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
11029 let e = _mm_set_pd(17., 1.);
11030 assert_eq_m128d(r, e);
11031 }
11032
11033 #[simd_test(enable = "avx512f,avx512vl")]
11034 unsafe fn test_mm_maskz_unpackhi_pd() {
11035 let a = _mm_set_pd(1., 2.);
11036 let b = _mm_set_pd(17., 18.);
11037 let r = _mm_maskz_unpackhi_pd(0, a, b);
11038 assert_eq_m128d(r, _mm_setzero_pd());
11039 let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
11040 let e = _mm_set_pd(17., 1.);
11041 assert_eq_m128d(r, e);
11042 }
11043
11044 #[simd_test(enable = "avx512f")]
11045 unsafe fn test_mm512_unpacklo_epi64() {
11046 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11047 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11048 let r = _mm512_unpacklo_epi64(a, b);
11049 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11050 assert_eq_m512i(r, e);
11051 }
11052
11053 #[simd_test(enable = "avx512f")]
11054 unsafe fn test_mm512_mask_unpacklo_epi64() {
11055 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11056 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11057 let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
11058 assert_eq_m512i(r, a);
11059 let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
11060 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11061 assert_eq_m512i(r, e);
11062 }
11063
11064 #[simd_test(enable = "avx512f")]
11065 unsafe fn test_mm512_maskz_unpacklo_epi64() {
11066 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11067 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11068 let r = _mm512_maskz_unpacklo_epi64(0, a, b);
11069 assert_eq_m512i(r, _mm512_setzero_si512());
11070 let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
11071 let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
11072 assert_eq_m512i(r, e);
11073 }
11074
11075 #[simd_test(enable = "avx512f,avx512vl")]
11076 unsafe fn test_mm256_mask_unpacklo_epi64() {
11077 let a = _mm256_set_epi64x(1, 2, 3, 4);
11078 let b = _mm256_set_epi64x(17, 18, 19, 20);
11079 let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
11080 assert_eq_m256i(r, a);
11081 let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
11082 let e = _mm256_set_epi64x(18, 2, 20, 4);
11083 assert_eq_m256i(r, e);
11084 }
11085
11086 #[simd_test(enable = "avx512f,avx512vl")]
11087 unsafe fn test_mm256_maskz_unpacklo_epi64() {
11088 let a = _mm256_set_epi64x(1, 2, 3, 4);
11089 let b = _mm256_set_epi64x(17, 18, 19, 20);
11090 let r = _mm256_maskz_unpacklo_epi64(0, a, b);
11091 assert_eq_m256i(r, _mm256_setzero_si256());
11092 let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
11093 let e = _mm256_set_epi64x(18, 2, 20, 4);
11094 assert_eq_m256i(r, e);
11095 }
11096
11097 #[simd_test(enable = "avx512f,avx512vl")]
11098 unsafe fn test_mm_mask_unpacklo_epi64() {
11099 let a = _mm_set_epi64x(1, 2);
11100 let b = _mm_set_epi64x(17, 18);
11101 let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
11102 assert_eq_m128i(r, a);
11103 let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
11104 let e = _mm_set_epi64x(18, 2);
11105 assert_eq_m128i(r, e);
11106 }
11107
11108 #[simd_test(enable = "avx512f,avx512vl")]
11109 unsafe fn test_mm_maskz_unpacklo_epi64() {
11110 let a = _mm_set_epi64x(1, 2);
11111 let b = _mm_set_epi64x(17, 18);
11112 let r = _mm_maskz_unpacklo_epi64(0, a, b);
11113 assert_eq_m128i(r, _mm_setzero_si128());
11114 let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
11115 let e = _mm_set_epi64x(18, 2);
11116 assert_eq_m128i(r, e);
11117 }
11118
11119 #[simd_test(enable = "avx512f")]
11120 unsafe fn test_mm512_unpacklo_pd() {
11121 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11122 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11123 let r = _mm512_unpacklo_pd(a, b);
11124 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11125 assert_eq_m512d(r, e);
11126 }
11127
11128 #[simd_test(enable = "avx512f")]
11129 unsafe fn test_mm512_mask_unpacklo_pd() {
11130 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11131 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11132 let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
11133 assert_eq_m512d(r, a);
11134 let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
11135 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11136 assert_eq_m512d(r, e);
11137 }
11138
11139 #[simd_test(enable = "avx512f")]
11140 unsafe fn test_mm512_maskz_unpacklo_pd() {
11141 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11142 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11143 let r = _mm512_maskz_unpacklo_pd(0, a, b);
11144 assert_eq_m512d(r, _mm512_setzero_pd());
11145 let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
11146 let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
11147 assert_eq_m512d(r, e);
11148 }
11149
11150 #[simd_test(enable = "avx512f,avx512vl")]
11151 unsafe fn test_mm256_mask_unpacklo_pd() {
11152 let a = _mm256_set_pd(1., 2., 3., 4.);
11153 let b = _mm256_set_pd(17., 18., 19., 20.);
11154 let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
11155 assert_eq_m256d(r, a);
11156 let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
11157 let e = _mm256_set_pd(18., 2., 20., 4.);
11158 assert_eq_m256d(r, e);
11159 }
11160
11161 #[simd_test(enable = "avx512f,avx512vl")]
11162 unsafe fn test_mm256_maskz_unpacklo_pd() {
11163 let a = _mm256_set_pd(1., 2., 3., 4.);
11164 let b = _mm256_set_pd(17., 18., 19., 20.);
11165 let r = _mm256_maskz_unpacklo_pd(0, a, b);
11166 assert_eq_m256d(r, _mm256_setzero_pd());
11167 let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
11168 let e = _mm256_set_pd(18., 2., 20., 4.);
11169 assert_eq_m256d(r, e);
11170 }
11171
11172 #[simd_test(enable = "avx512f,avx512vl")]
11173 unsafe fn test_mm_mask_unpacklo_pd() {
11174 let a = _mm_set_pd(1., 2.);
11175 let b = _mm_set_pd(17., 18.);
11176 let r = _mm_mask_unpacklo_pd(a, 0, a, b);
11177 assert_eq_m128d(r, a);
11178 let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
11179 let e = _mm_set_pd(18., 2.);
11180 assert_eq_m128d(r, e);
11181 }
11182
11183 #[simd_test(enable = "avx512f,avx512vl")]
11184 unsafe fn test_mm_maskz_unpacklo_pd() {
11185 let a = _mm_set_pd(1., 2.);
11186 let b = _mm_set_pd(17., 18.);
11187 let r = _mm_maskz_unpacklo_pd(0, a, b);
11188 assert_eq_m128d(r, _mm_setzero_pd());
11189 let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
11190 let e = _mm_set_pd(18., 2.);
11191 assert_eq_m128d(r, e);
11192 }
11193
11194 #[simd_test(enable = "avx512f")]
11195 unsafe fn test_mm512_alignr_epi64() {
11196 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11197 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11198 let r = _mm512_alignr_epi64::<0>(a, b);
11199 assert_eq_m512i(r, b);
11200 let r = _mm512_alignr_epi64::<8>(a, b);
11201 assert_eq_m512i(r, b);
11202 let r = _mm512_alignr_epi64::<1>(a, b);
11203 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11204 assert_eq_m512i(r, e);
11205 }
11206
11207 #[simd_test(enable = "avx512f")]
11208 unsafe fn test_mm512_mask_alignr_epi64() {
11209 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11210 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11211 let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
11212 assert_eq_m512i(r, a);
11213 let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
11214 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11215 assert_eq_m512i(r, e);
11216 }
11217
11218 #[simd_test(enable = "avx512f")]
11219 unsafe fn test_mm512_maskz_alignr_epi64() {
11220 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11221 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11222 let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
11223 assert_eq_m512i(r, _mm512_setzero_si512());
11224 let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
11225 let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
11226 assert_eq_m512i(r, e);
11227 }
11228
11229 #[simd_test(enable = "avx512f,avx512vl")]
11230 unsafe fn test_mm256_alignr_epi64() {
11231 let a = _mm256_set_epi64x(4, 3, 2, 1);
11232 let b = _mm256_set_epi64x(8, 7, 6, 5);
11233 let r = _mm256_alignr_epi64::<0>(a, b);
11234 let e = _mm256_set_epi64x(8, 7, 6, 5);
11235 assert_eq_m256i(r, e);
11236 let r = _mm256_alignr_epi64::<1>(a, b);
11237 let e = _mm256_set_epi64x(1, 8, 7, 6);
11238 assert_eq_m256i(r, e);
11239 let r = _mm256_alignr_epi64::<6>(a, b);
11240 let e = _mm256_set_epi64x(2, 1, 8, 7);
11241 assert_eq_m256i(r, e);
11242 }
11243
11244 #[simd_test(enable = "avx512f,avx512vl")]
11245 unsafe fn test_mm256_mask_alignr_epi64() {
11246 let a = _mm256_set_epi64x(4, 3, 2, 1);
11247 let b = _mm256_set_epi64x(8, 7, 6, 5);
11248 let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
11249 assert_eq_m256i(r, a);
11250 let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
11251 let e = _mm256_set_epi64x(8, 7, 6, 5);
11252 assert_eq_m256i(r, e);
11253 }
11254
11255 #[simd_test(enable = "avx512f,avx512vl")]
11256 unsafe fn test_mm256_maskz_alignr_epi64() {
11257 let a = _mm256_set_epi64x(4, 3, 2, 1);
11258 let b = _mm256_set_epi64x(8, 7, 6, 5);
11259 let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
11260 assert_eq_m256i(r, _mm256_setzero_si256());
11261 let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
11262 let e = _mm256_set_epi64x(8, 7, 6, 5);
11263 assert_eq_m256i(r, e);
11264 }
11265
11266 #[simd_test(enable = "avx512f,avx512vl")]
11267 unsafe fn test_mm_alignr_epi64() {
11268 let a = _mm_set_epi64x(2, 1);
11269 let b = _mm_set_epi64x(4, 3);
11270 let r = _mm_alignr_epi64::<0>(a, b);
11271 let e = _mm_set_epi64x(4, 3);
11272 assert_eq_m128i(r, e);
11273 }
11274
11275 #[simd_test(enable = "avx512f,avx512vl")]
11276 unsafe fn test_mm_mask_alignr_epi64() {
11277 let a = _mm_set_epi64x(2, 1);
11278 let b = _mm_set_epi64x(4, 3);
11279 let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
11280 assert_eq_m128i(r, a);
11281 let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
11282 let e = _mm_set_epi64x(4, 3);
11283 assert_eq_m128i(r, e);
11284 }
11285
11286 #[simd_test(enable = "avx512f,avx512vl")]
11287 unsafe fn test_mm_maskz_alignr_epi64() {
11288 let a = _mm_set_epi64x(2, 1);
11289 let b = _mm_set_epi64x(4, 3);
11290 let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
11291 assert_eq_m128i(r, _mm_setzero_si128());
11292 let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
11293 let e = _mm_set_epi64x(4, 3);
11294 assert_eq_m128i(r, e);
11295 }
11296
11297 #[simd_test(enable = "avx512f")]
11298 unsafe fn test_mm512_and_epi64() {
11299 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11300 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11301 let r = _mm512_and_epi64(a, b);
11302 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11303 assert_eq_m512i(r, e);
11304 }
11305
11306 #[simd_test(enable = "avx512f")]
11307 unsafe fn test_mm512_mask_and_epi64() {
11308 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11309 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11310 let r = _mm512_mask_and_epi64(a, 0, a, b);
11311 assert_eq_m512i(r, a);
11312 let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
11313 let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11314 assert_eq_m512i(r, e);
11315 }
11316
11317 #[simd_test(enable = "avx512f")]
11318 unsafe fn test_mm512_maskz_and_epi64() {
11319 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11320 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11321 let r = _mm512_maskz_and_epi64(0, a, b);
11322 assert_eq_m512i(r, _mm512_setzero_si512());
11323 let r = _mm512_maskz_and_epi64(0b00001111, a, b);
11324 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11325 assert_eq_m512i(r, e);
11326 }
11327
11328 #[simd_test(enable = "avx512f,avx512vl")]
11329 unsafe fn test_mm256_mask_and_epi64() {
11330 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11331 let b = _mm256_set1_epi64x(1 << 0);
11332 let r = _mm256_mask_and_epi64(a, 0, a, b);
11333 assert_eq_m256i(r, a);
11334 let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
11335 let e = _mm256_set1_epi64x(1 << 0);
11336 assert_eq_m256i(r, e);
11337 }
11338
11339 #[simd_test(enable = "avx512f,avx512vl")]
11340 unsafe fn test_mm256_maskz_and_epi64() {
11341 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11342 let b = _mm256_set1_epi64x(1 << 0);
11343 let r = _mm256_maskz_and_epi64(0, a, b);
11344 assert_eq_m256i(r, _mm256_setzero_si256());
11345 let r = _mm256_maskz_and_epi64(0b00001111, a, b);
11346 let e = _mm256_set1_epi64x(1 << 0);
11347 assert_eq_m256i(r, e);
11348 }
11349
11350 #[simd_test(enable = "avx512f,avx512vl")]
11351 unsafe fn test_mm_mask_and_epi64() {
11352 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11353 let b = _mm_set1_epi64x(1 << 0);
11354 let r = _mm_mask_and_epi64(a, 0, a, b);
11355 assert_eq_m128i(r, a);
11356 let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
11357 let e = _mm_set1_epi64x(1 << 0);
11358 assert_eq_m128i(r, e);
11359 }
11360
11361 #[simd_test(enable = "avx512f,avx512vl")]
11362 unsafe fn test_mm_maskz_and_epi64() {
11363 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11364 let b = _mm_set1_epi64x(1 << 0);
11365 let r = _mm_maskz_and_epi64(0, a, b);
11366 assert_eq_m128i(r, _mm_setzero_si128());
11367 let r = _mm_maskz_and_epi64(0b00000011, a, b);
11368 let e = _mm_set1_epi64x(1 << 0);
11369 assert_eq_m128i(r, e);
11370 }
11371
11372 #[simd_test(enable = "avx512f")]
11373 unsafe fn test_mm512_and_si512() {
11374 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11375 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11376 let r = _mm512_and_epi64(a, b);
11377 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11378 assert_eq_m512i(r, e);
11379 }
11380
11381 #[simd_test(enable = "avx512f")]
11382 unsafe fn test_mm512_or_epi64() {
11383 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11384 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11385 let r = _mm512_or_epi64(a, b);
11386 #[rustfmt::skip]
11387 let e = _mm512_set_epi64(
11388 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11389 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11390 );
11391 assert_eq_m512i(r, e);
11392 }
11393
11394 #[simd_test(enable = "avx512f")]
11395 unsafe fn test_mm512_mask_or_epi64() {
11396 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11397 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11398 let r = _mm512_mask_or_epi64(a, 0, a, b);
11399 assert_eq_m512i(r, a);
11400 let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
11401 #[rustfmt::skip]
11402 let e = _mm512_set_epi64(
11403 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11404 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11405 );
11406 assert_eq_m512i(r, e);
11407 }
11408
11409 #[simd_test(enable = "avx512f")]
11410 unsafe fn test_mm512_maskz_or_epi64() {
11411 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11412 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11413 let r = _mm512_maskz_or_epi64(0, a, b);
11414 assert_eq_m512i(r, _mm512_setzero_si512());
11415 let r = _mm512_maskz_or_epi64(0b00001111, a, b);
11416 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11417 assert_eq_m512i(r, e);
11418 }
11419
11420 #[simd_test(enable = "avx512f,avx512vl")]
11421 unsafe fn test_mm256_or_epi64() {
11422 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11423 let b = _mm256_set1_epi64x(1 << 13);
11424 let r = _mm256_or_epi64(a, b);
11425 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11426 assert_eq_m256i(r, e);
11427 }
11428
11429 #[simd_test(enable = "avx512f,avx512vl")]
11430 unsafe fn test_mm256_mask_or_epi64() {
11431 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11432 let b = _mm256_set1_epi64x(1 << 13);
11433 let r = _mm256_mask_or_epi64(a, 0, a, b);
11434 assert_eq_m256i(r, a);
11435 let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
11436 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11437 assert_eq_m256i(r, e);
11438 }
11439
11440 #[simd_test(enable = "avx512f,avx512vl")]
11441 unsafe fn test_mm256_maskz_or_epi64() {
11442 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11443 let b = _mm256_set1_epi64x(1 << 13);
11444 let r = _mm256_maskz_or_epi64(0, a, b);
11445 assert_eq_m256i(r, _mm256_setzero_si256());
11446 let r = _mm256_maskz_or_epi64(0b00001111, a, b);
11447 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11448 assert_eq_m256i(r, e);
11449 }
11450
11451 #[simd_test(enable = "avx512f,avx512vl")]
11452 unsafe fn test_mm_or_epi64() {
11453 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11454 let b = _mm_set1_epi64x(1 << 13);
11455 let r = _mm_or_epi64(a, b);
11456 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11457 assert_eq_m128i(r, e);
11458 }
11459
11460 #[simd_test(enable = "avx512f,avx512vl")]
11461 unsafe fn test_mm_mask_or_epi64() {
11462 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11463 let b = _mm_set1_epi64x(1 << 13);
11464 let r = _mm_mask_or_epi64(a, 0, a, b);
11465 assert_eq_m128i(r, a);
11466 let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
11467 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11468 assert_eq_m128i(r, e);
11469 }
11470
11471 #[simd_test(enable = "avx512f,avx512vl")]
11472 unsafe fn test_mm_maskz_or_epi64() {
11473 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11474 let b = _mm_set1_epi64x(1 << 13);
11475 let r = _mm_maskz_or_epi64(0, a, b);
11476 assert_eq_m128i(r, _mm_setzero_si128());
11477 let r = _mm_maskz_or_epi64(0b00000011, a, b);
11478 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11479 assert_eq_m128i(r, e);
11480 }
11481
11482 #[simd_test(enable = "avx512f")]
11483 unsafe fn test_mm512_or_si512() {
11484 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11485 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11486 let r = _mm512_or_epi64(a, b);
11487 #[rustfmt::skip]
11488 let e = _mm512_set_epi64(
11489 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11490 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11491 );
11492 assert_eq_m512i(r, e);
11493 }
11494
11495 #[simd_test(enable = "avx512f")]
11496 unsafe fn test_mm512_xor_epi64() {
11497 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11498 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11499 let r = _mm512_xor_epi64(a, b);
11500 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11501 assert_eq_m512i(r, e);
11502 }
11503
11504 #[simd_test(enable = "avx512f")]
11505 unsafe fn test_mm512_mask_xor_epi64() {
11506 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11507 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11508 let r = _mm512_mask_xor_epi64(a, 0, a, b);
11509 assert_eq_m512i(r, a);
11510 let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
11511 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11512 assert_eq_m512i(r, e);
11513 }
11514
11515 #[simd_test(enable = "avx512f")]
11516 unsafe fn test_mm512_maskz_xor_epi64() {
11517 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11518 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11519 let r = _mm512_maskz_xor_epi64(0, a, b);
11520 assert_eq_m512i(r, _mm512_setzero_si512());
11521 let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
11522 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
11523 assert_eq_m512i(r, e);
11524 }
11525
11526 #[simd_test(enable = "avx512f,avx512vl")]
11527 unsafe fn test_mm256_xor_epi64() {
11528 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11529 let b = _mm256_set1_epi64x(1 << 13);
11530 let r = _mm256_xor_epi64(a, b);
11531 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11532 assert_eq_m256i(r, e);
11533 }
11534
11535 #[simd_test(enable = "avx512f,avx512vl")]
11536 unsafe fn test_mm256_mask_xor_epi64() {
11537 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11538 let b = _mm256_set1_epi64x(1 << 13);
11539 let r = _mm256_mask_xor_epi64(a, 0, a, b);
11540 assert_eq_m256i(r, a);
11541 let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
11542 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11543 assert_eq_m256i(r, e);
11544 }
11545
11546 #[simd_test(enable = "avx512f,avx512vl")]
11547 unsafe fn test_mm256_maskz_xor_epi64() {
11548 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11549 let b = _mm256_set1_epi64x(1 << 13);
11550 let r = _mm256_maskz_xor_epi64(0, a, b);
11551 assert_eq_m256i(r, _mm256_setzero_si256());
11552 let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
11553 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11554 assert_eq_m256i(r, e);
11555 }
11556
11557 #[simd_test(enable = "avx512f,avx512vl")]
11558 unsafe fn test_mm_xor_epi64() {
11559 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11560 let b = _mm_set1_epi64x(1 << 13);
11561 let r = _mm_xor_epi64(a, b);
11562 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11563 assert_eq_m128i(r, e);
11564 }
11565
11566 #[simd_test(enable = "avx512f,avx512vl")]
11567 unsafe fn test_mm_mask_xor_epi64() {
11568 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11569 let b = _mm_set1_epi64x(1 << 13);
11570 let r = _mm_mask_xor_epi64(a, 0, a, b);
11571 assert_eq_m128i(r, a);
11572 let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
11573 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11574 assert_eq_m128i(r, e);
11575 }
11576
11577 #[simd_test(enable = "avx512f,avx512vl")]
11578 unsafe fn test_mm_maskz_xor_epi64() {
11579 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11580 let b = _mm_set1_epi64x(1 << 13);
11581 let r = _mm_maskz_xor_epi64(0, a, b);
11582 assert_eq_m128i(r, _mm_setzero_si128());
11583 let r = _mm_maskz_xor_epi64(0b00000011, a, b);
11584 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11585 assert_eq_m128i(r, e);
11586 }
11587
11588 #[simd_test(enable = "avx512f")]
11589 unsafe fn test_mm512_xor_si512() {
11590 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11591 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11592 let r = _mm512_xor_epi64(a, b);
11593 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11594 assert_eq_m512i(r, e);
11595 }
11596
11597 #[simd_test(enable = "avx512f")]
11598 unsafe fn test_mm512_andnot_epi64() {
11599 let a = _mm512_set1_epi64(0);
11600 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11601 let r = _mm512_andnot_epi64(a, b);
11602 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11603 assert_eq_m512i(r, e);
11604 }
11605
11606 #[simd_test(enable = "avx512f")]
11607 unsafe fn test_mm512_mask_andnot_epi64() {
11608 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11609 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11610 let r = _mm512_mask_andnot_epi64(a, 0, a, b);
11611 assert_eq_m512i(r, a);
11612 let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
11613 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11614 assert_eq_m512i(r, e);
11615 }
11616
11617 #[simd_test(enable = "avx512f")]
11618 unsafe fn test_mm512_maskz_andnot_epi64() {
11619 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11620 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11621 let r = _mm512_maskz_andnot_epi64(0, a, b);
11622 assert_eq_m512i(r, _mm512_setzero_si512());
11623 let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
11624 #[rustfmt::skip]
11625 let e = _mm512_set_epi64(
11626 0, 0, 0, 0,
11627 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
11628 );
11629 assert_eq_m512i(r, e);
11630 }
11631
11632 #[simd_test(enable = "avx512f,avx512vl")]
11633 unsafe fn test_mm256_mask_andnot_epi64() {
11634 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11635 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11636 let r = _mm256_mask_andnot_epi64(a, 0, a, b);
11637 assert_eq_m256i(r, a);
11638 let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
11639 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11640 assert_eq_m256i(r, e);
11641 }
11642
11643 #[simd_test(enable = "avx512f,avx512vl")]
11644 unsafe fn test_mm256_maskz_andnot_epi64() {
11645 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11646 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11647 let r = _mm256_maskz_andnot_epi64(0, a, b);
11648 assert_eq_m256i(r, _mm256_setzero_si256());
11649 let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
11650 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11651 assert_eq_m256i(r, e);
11652 }
11653
11654 #[simd_test(enable = "avx512f,avx512vl")]
11655 unsafe fn test_mm_mask_andnot_epi64() {
11656 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11657 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11658 let r = _mm_mask_andnot_epi64(a, 0, a, b);
11659 assert_eq_m128i(r, a);
11660 let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
11661 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11662 assert_eq_m128i(r, e);
11663 }
11664
11665 #[simd_test(enable = "avx512f,avx512vl")]
11666 unsafe fn test_mm_maskz_andnot_epi64() {
11667 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11668 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11669 let r = _mm_maskz_andnot_epi64(0, a, b);
11670 assert_eq_m128i(r, _mm_setzero_si128());
11671 let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
11672 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11673 assert_eq_m128i(r, e);
11674 }
11675
11676 #[simd_test(enable = "avx512f")]
11677 unsafe fn test_mm512_andnot_si512() {
11678 let a = _mm512_set1_epi64(0);
11679 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11680 let r = _mm512_andnot_si512(a, b);
11681 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11682 assert_eq_m512i(r, e);
11683 }
11684
11685 #[simd_test(enable = "avx512f")]
11686 unsafe fn test_mm512_reduce_add_epi64() {
11687 let a = _mm512_set1_epi64(1);
11688 let e: i64 = _mm512_reduce_add_epi64(a);
11689 assert_eq!(8, e);
11690 }
11691
11692 #[simd_test(enable = "avx512f")]
11693 unsafe fn test_mm512_mask_reduce_add_epi64() {
11694 let a = _mm512_set1_epi64(1);
11695 let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11696 assert_eq!(4, e);
11697 }
11698
11699 #[simd_test(enable = "avx512f")]
11700 unsafe fn test_mm512_reduce_add_pd() {
11701 let a = _mm512_set1_pd(1.);
11702 let e: f64 = _mm512_reduce_add_pd(a);
11703 assert_eq!(8., e);
11704 }
11705
11706 #[simd_test(enable = "avx512f")]
11707 unsafe fn test_mm512_mask_reduce_add_pd() {
11708 let a = _mm512_set1_pd(1.);
11709 let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11710 assert_eq!(4., e);
11711 }
11712
11713 #[simd_test(enable = "avx512f")]
11714 unsafe fn test_mm512_reduce_mul_epi64() {
11715 let a = _mm512_set1_epi64(2);
11716 let e: i64 = _mm512_reduce_mul_epi64(a);
11717 assert_eq!(256, e);
11718 }
11719
11720 #[simd_test(enable = "avx512f")]
11721 unsafe fn test_mm512_mask_reduce_mul_epi64() {
11722 let a = _mm512_set1_epi64(2);
11723 let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11724 assert_eq!(16, e);
11725 }
11726
11727 #[simd_test(enable = "avx512f")]
11728 unsafe fn test_mm512_reduce_mul_pd() {
11729 let a = _mm512_set1_pd(2.);
11730 let e: f64 = _mm512_reduce_mul_pd(a);
11731 assert_eq!(256., e);
11732 }
11733
11734 #[simd_test(enable = "avx512f")]
11735 unsafe fn test_mm512_mask_reduce_mul_pd() {
11736 let a = _mm512_set1_pd(2.);
11737 let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11738 assert_eq!(16., e);
11739 }
11740
11741 #[simd_test(enable = "avx512f")]
11742 unsafe fn test_mm512_reduce_max_epi64() {
11743 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11744 let e: i64 = _mm512_reduce_max_epi64(a);
11745 assert_eq!(7, e);
11746 }
11747
11748 #[simd_test(enable = "avx512f")]
11749 unsafe fn test_mm512_mask_reduce_max_epi64() {
11750 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11751 let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11752 assert_eq!(3, e);
11753 }
11754
11755 #[simd_test(enable = "avx512f")]
11756 unsafe fn test_mm512_reduce_max_epu64() {
11757 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11758 let e: u64 = _mm512_reduce_max_epu64(a);
11759 assert_eq!(7, e);
11760 }
11761
11762 #[simd_test(enable = "avx512f")]
11763 unsafe fn test_mm512_mask_reduce_max_epu64() {
11764 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11765 let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11766 assert_eq!(3, e);
11767 }
11768
11769 #[simd_test(enable = "avx512f")]
11770 unsafe fn test_mm512_reduce_max_pd() {
11771 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11772 let e: f64 = _mm512_reduce_max_pd(a);
11773 assert_eq!(7., e);
11774 }
11775
11776 #[simd_test(enable = "avx512f")]
11777 unsafe fn test_mm512_mask_reduce_max_pd() {
11778 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11779 let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11780 assert_eq!(3., e);
11781 }
11782
11783 #[simd_test(enable = "avx512f")]
11784 unsafe fn test_mm512_reduce_min_epi64() {
11785 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11786 let e: i64 = _mm512_reduce_min_epi64(a);
11787 assert_eq!(0, e);
11788 }
11789
11790 #[simd_test(enable = "avx512f")]
11791 unsafe fn test_mm512_mask_reduce_min_epi64() {
11792 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11793 let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11794 assert_eq!(0, e);
11795 }
11796
11797 #[simd_test(enable = "avx512f")]
11798 unsafe fn test_mm512_reduce_min_epu64() {
11799 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11800 let e: u64 = _mm512_reduce_min_epu64(a);
11801 assert_eq!(0, e);
11802 }
11803
11804 #[simd_test(enable = "avx512f")]
11805 unsafe fn test_mm512_mask_reduce_min_epu64() {
11806 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11807 let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11808 assert_eq!(0, e);
11809 }
11810
11811 #[simd_test(enable = "avx512f")]
11812 unsafe fn test_mm512_reduce_min_pd() {
11813 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11814 let e: f64 = _mm512_reduce_min_pd(a);
11815 assert_eq!(0., e);
11816 }
11817
11818 #[simd_test(enable = "avx512f")]
11819 unsafe fn test_mm512_mask_reduce_min_pd() {
11820 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11821 let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11822 assert_eq!(0., e);
11823 }
11824
11825 #[simd_test(enable = "avx512f")]
11826 unsafe fn test_mm512_reduce_and_epi64() {
11827 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11828 let e: i64 = _mm512_reduce_and_epi64(a);
11829 assert_eq!(0, e);
11830 }
11831
11832 #[simd_test(enable = "avx512f")]
11833 unsafe fn test_mm512_mask_reduce_and_epi64() {
11834 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11835 let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11836 assert_eq!(1, e);
11837 }
11838
11839 #[simd_test(enable = "avx512f")]
11840 unsafe fn test_mm512_reduce_or_epi64() {
11841 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11842 let e: i64 = _mm512_reduce_or_epi64(a);
11843 assert_eq!(3, e);
11844 }
11845
11846 #[simd_test(enable = "avx512f")]
11847 unsafe fn test_mm512_mask_reduce_or_epi64() {
11848 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11849 let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11850 assert_eq!(1, e);
11851 }
11852
11853 #[simd_test(enable = "avx512f")]
11854 unsafe fn test_mm512_extractf64x4_pd() {
11855 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11856 let r = _mm512_extractf64x4_pd::<1>(a);
11857 let e = _mm256_setr_pd(5., 6., 7., 8.);
11858 assert_eq_m256d(r, e);
11859 }
11860
11861 #[simd_test(enable = "avx512f")]
11862 unsafe fn test_mm512_mask_extractf64x4_pd() {
11863 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11864 let src = _mm256_set1_pd(100.);
11865 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11866 assert_eq_m256d(r, src);
11867 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11868 let e = _mm256_setr_pd(5., 6., 7., 8.);
11869 assert_eq_m256d(r, e);
11870 }
11871
11872 #[simd_test(enable = "avx512f")]
11873 unsafe fn test_mm512_maskz_extractf64x4_pd() {
11874 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11875 let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11876 assert_eq_m256d(r, _mm256_setzero_pd());
11877 let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11878 let e = _mm256_setr_pd(5., 0., 0., 0.);
11879 assert_eq_m256d(r, e);
11880 }
11881
11882 #[simd_test(enable = "avx512f")]
11883 unsafe fn test_mm512_extracti64x4_epi64() {
11884 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11885 let r = _mm512_extracti64x4_epi64::<0x1>(a);
11886 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11887 assert_eq_m256i(r, e);
11888 }
11889
11890 #[simd_test(enable = "avx512f")]
11891 unsafe fn test_mm512_mask_extracti64x4_epi64() {
11892 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11893 let src = _mm256_set1_epi64x(100);
11894 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11895 assert_eq_m256i(r, src);
11896 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11897 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11898 assert_eq_m256i(r, e);
11899 }
11900
11901 #[simd_test(enable = "avx512f")]
11902 unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11903 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11904 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11905 assert_eq_m256i(r, _mm256_setzero_si256());
11906 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11907 let e = _mm256_setr_epi64x(5, 0, 0, 0);
11908 assert_eq_m256i(r, e);
11909 }
11910
11911 #[simd_test(enable = "avx512f")]
11912 unsafe fn test_mm512_mask_compress_epi64() {
11913 let src = _mm512_set1_epi64(200);
11914 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11915 let r = _mm512_mask_compress_epi64(src, 0, a);
11916 assert_eq_m512i(r, src);
11917 let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11918 let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11919 assert_eq_m512i(r, e);
11920 }
11921
11922 #[simd_test(enable = "avx512f")]
11923 unsafe fn test_mm512_maskz_compress_epi64() {
11924 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11925 let r = _mm512_maskz_compress_epi64(0, a);
11926 assert_eq_m512i(r, _mm512_setzero_si512());
11927 let r = _mm512_maskz_compress_epi64(0b01010101, a);
11928 let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11929 assert_eq_m512i(r, e);
11930 }
11931
11932 #[simd_test(enable = "avx512f,avx512vl")]
11933 unsafe fn test_mm256_mask_compress_epi64() {
11934 let src = _mm256_set1_epi64x(200);
11935 let a = _mm256_set_epi64x(0, 1, 2, 3);
11936 let r = _mm256_mask_compress_epi64(src, 0, a);
11937 assert_eq_m256i(r, src);
11938 let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11939 let e = _mm256_set_epi64x(200, 200, 1, 3);
11940 assert_eq_m256i(r, e);
11941 }
11942
11943 #[simd_test(enable = "avx512f,avx512vl")]
11944 unsafe fn test_mm256_maskz_compress_epi64() {
11945 let a = _mm256_set_epi64x(0, 1, 2, 3);
11946 let r = _mm256_maskz_compress_epi64(0, a);
11947 assert_eq_m256i(r, _mm256_setzero_si256());
11948 let r = _mm256_maskz_compress_epi64(0b00000101, a);
11949 let e = _mm256_set_epi64x(0, 0, 1, 3);
11950 assert_eq_m256i(r, e);
11951 }
11952
11953 #[simd_test(enable = "avx512f,avx512vl")]
11954 unsafe fn test_mm_mask_compress_epi64() {
11955 let src = _mm_set1_epi64x(200);
11956 let a = _mm_set_epi64x(0, 1);
11957 let r = _mm_mask_compress_epi64(src, 0, a);
11958 assert_eq_m128i(r, src);
11959 let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11960 let e = _mm_set_epi64x(200, 1);
11961 assert_eq_m128i(r, e);
11962 }
11963
11964 #[simd_test(enable = "avx512f,avx512vl")]
11965 unsafe fn test_mm_maskz_compress_epi64() {
11966 let a = _mm_set_epi64x(0, 1);
11967 let r = _mm_maskz_compress_epi64(0, a);
11968 assert_eq_m128i(r, _mm_setzero_si128());
11969 let r = _mm_maskz_compress_epi64(0b00000001, a);
11970 let e = _mm_set_epi64x(0, 1);
11971 assert_eq_m128i(r, e);
11972 }
11973
11974 #[simd_test(enable = "avx512f")]
11975 unsafe fn test_mm512_mask_compress_pd() {
11976 let src = _mm512_set1_pd(200.);
11977 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11978 let r = _mm512_mask_compress_pd(src, 0, a);
11979 assert_eq_m512d(r, src);
11980 let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11981 let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11982 assert_eq_m512d(r, e);
11983 }
11984
11985 #[simd_test(enable = "avx512f")]
11986 unsafe fn test_mm512_maskz_compress_pd() {
11987 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11988 let r = _mm512_maskz_compress_pd(0, a);
11989 assert_eq_m512d(r, _mm512_setzero_pd());
11990 let r = _mm512_maskz_compress_pd(0b01010101, a);
11991 let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11992 assert_eq_m512d(r, e);
11993 }
11994
11995 #[simd_test(enable = "avx512f,avx512vl")]
11996 unsafe fn test_mm256_mask_compress_pd() {
11997 let src = _mm256_set1_pd(200.);
11998 let a = _mm256_set_pd(0., 1., 2., 3.);
11999 let r = _mm256_mask_compress_pd(src, 0, a);
12000 assert_eq_m256d(r, src);
12001 let r = _mm256_mask_compress_pd(src, 0b00000101, a);
12002 let e = _mm256_set_pd(200., 200., 1., 3.);
12003 assert_eq_m256d(r, e);
12004 }
12005
12006 #[simd_test(enable = "avx512f,avx512vl")]
12007 unsafe fn test_mm256_maskz_compress_pd() {
12008 let a = _mm256_set_pd(0., 1., 2., 3.);
12009 let r = _mm256_maskz_compress_pd(0, a);
12010 assert_eq_m256d(r, _mm256_setzero_pd());
12011 let r = _mm256_maskz_compress_pd(0b00000101, a);
12012 let e = _mm256_set_pd(0., 0., 1., 3.);
12013 assert_eq_m256d(r, e);
12014 }
12015
12016 #[simd_test(enable = "avx512f,avx512vl")]
12017 unsafe fn test_mm_mask_compress_pd() {
12018 let src = _mm_set1_pd(200.);
12019 let a = _mm_set_pd(0., 1.);
12020 let r = _mm_mask_compress_pd(src, 0, a);
12021 assert_eq_m128d(r, src);
12022 let r = _mm_mask_compress_pd(src, 0b00000001, a);
12023 let e = _mm_set_pd(200., 1.);
12024 assert_eq_m128d(r, e);
12025 }
12026
12027 #[simd_test(enable = "avx512f,avx512vl")]
12028 unsafe fn test_mm_maskz_compress_pd() {
12029 let a = _mm_set_pd(0., 1.);
12030 let r = _mm_maskz_compress_pd(0, a);
12031 assert_eq_m128d(r, _mm_setzero_pd());
12032 let r = _mm_maskz_compress_pd(0b00000001, a);
12033 let e = _mm_set_pd(0., 1.);
12034 assert_eq_m128d(r, e);
12035 }
12036
12037 #[simd_test(enable = "avx512f")]
12038 unsafe fn test_mm512_mask_expand_epi64() {
12039 let src = _mm512_set1_epi64(200);
12040 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12041 let r = _mm512_mask_expand_epi64(src, 0, a);
12042 assert_eq_m512i(r, src);
12043 let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
12044 let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
12045 assert_eq_m512i(r, e);
12046 }
12047
12048 #[simd_test(enable = "avx512f")]
12049 unsafe fn test_mm512_maskz_expand_epi64() {
12050 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12051 let r = _mm512_maskz_expand_epi64(0, a);
12052 assert_eq_m512i(r, _mm512_setzero_si512());
12053 let r = _mm512_maskz_expand_epi64(0b01010101, a);
12054 let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
12055 assert_eq_m512i(r, e);
12056 }
12057
12058 #[simd_test(enable = "avx512f,avx512vl")]
12059 unsafe fn test_mm256_mask_expand_epi64() {
12060 let src = _mm256_set1_epi64x(200);
12061 let a = _mm256_set_epi64x(0, 1, 2, 3);
12062 let r = _mm256_mask_expand_epi64(src, 0, a);
12063 assert_eq_m256i(r, src);
12064 let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
12065 let e = _mm256_set_epi64x(200, 2, 200, 3);
12066 assert_eq_m256i(r, e);
12067 }
12068
12069 #[simd_test(enable = "avx512f,avx512vl")]
12070 unsafe fn test_mm256_maskz_expand_epi64() {
12071 let a = _mm256_set_epi64x(0, 1, 2, 3);
12072 let r = _mm256_maskz_expand_epi64(0, a);
12073 assert_eq_m256i(r, _mm256_setzero_si256());
12074 let r = _mm256_maskz_expand_epi64(0b00000101, a);
12075 let e = _mm256_set_epi64x(0, 2, 0, 3);
12076 assert_eq_m256i(r, e);
12077 }
12078
12079 #[simd_test(enable = "avx512f,avx512vl")]
12080 unsafe fn test_mm_mask_expand_epi64() {
12081 let src = _mm_set1_epi64x(200);
12082 let a = _mm_set_epi64x(0, 1);
12083 let r = _mm_mask_expand_epi64(src, 0, a);
12084 assert_eq_m128i(r, src);
12085 let r = _mm_mask_expand_epi64(src, 0b00000001, a);
12086 let e = _mm_set_epi64x(200, 1);
12087 assert_eq_m128i(r, e);
12088 }
12089
12090 #[simd_test(enable = "avx512f,avx512vl")]
12091 unsafe fn test_mm_maskz_expand_epi64() {
12092 let a = _mm_set_epi64x(0, 1);
12093 let r = _mm_maskz_expand_epi64(0, a);
12094 assert_eq_m128i(r, _mm_setzero_si128());
12095 let r = _mm_maskz_expand_epi64(0b00000001, a);
12096 let e = _mm_set_epi64x(0, 1);
12097 assert_eq_m128i(r, e);
12098 }
12099
12100 #[simd_test(enable = "avx512f")]
12101 unsafe fn test_mm512_mask_expand_pd() {
12102 let src = _mm512_set1_pd(200.);
12103 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12104 let r = _mm512_mask_expand_pd(src, 0, a);
12105 assert_eq_m512d(r, src);
12106 let r = _mm512_mask_expand_pd(src, 0b01010101, a);
12107 let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
12108 assert_eq_m512d(r, e);
12109 }
12110
12111 #[simd_test(enable = "avx512f")]
12112 unsafe fn test_mm512_maskz_expand_pd() {
12113 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12114 let r = _mm512_maskz_expand_pd(0, a);
12115 assert_eq_m512d(r, _mm512_setzero_pd());
12116 let r = _mm512_maskz_expand_pd(0b01010101, a);
12117 let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
12118 assert_eq_m512d(r, e);
12119 }
12120
12121 #[simd_test(enable = "avx512f,avx512vl")]
12122 unsafe fn test_mm256_mask_expand_pd() {
12123 let src = _mm256_set1_pd(200.);
12124 let a = _mm256_set_pd(0., 1., 2., 3.);
12125 let r = _mm256_mask_expand_pd(src, 0, a);
12126 assert_eq_m256d(r, src);
12127 let r = _mm256_mask_expand_pd(src, 0b00000101, a);
12128 let e = _mm256_set_pd(200., 2., 200., 3.);
12129 assert_eq_m256d(r, e);
12130 }
12131
12132 #[simd_test(enable = "avx512f,avx512vl")]
12133 unsafe fn test_mm256_maskz_expand_pd() {
12134 let a = _mm256_set_pd(0., 1., 2., 3.);
12135 let r = _mm256_maskz_expand_pd(0, a);
12136 assert_eq_m256d(r, _mm256_setzero_pd());
12137 let r = _mm256_maskz_expand_pd(0b00000101, a);
12138 let e = _mm256_set_pd(0., 2., 0., 3.);
12139 assert_eq_m256d(r, e);
12140 }
12141
12142 #[simd_test(enable = "avx512f,avx512vl")]
12143 unsafe fn test_mm_mask_expand_pd() {
12144 let src = _mm_set1_pd(200.);
12145 let a = _mm_set_pd(0., 1.);
12146 let r = _mm_mask_expand_pd(src, 0, a);
12147 assert_eq_m128d(r, src);
12148 let r = _mm_mask_expand_pd(src, 0b00000001, a);
12149 let e = _mm_set_pd(200., 1.);
12150 assert_eq_m128d(r, e);
12151 }
12152
12153 #[simd_test(enable = "avx512f,avx512vl")]
12154 unsafe fn test_mm_maskz_expand_pd() {
12155 let a = _mm_set_pd(0., 1.);
12156 let r = _mm_maskz_expand_pd(0, a);
12157 assert_eq_m128d(r, _mm_setzero_pd());
12158 let r = _mm_maskz_expand_pd(0b00000001, a);
12159 let e = _mm_set_pd(0., 1.);
12160 assert_eq_m128d(r, e);
12161 }
12162
12163 #[simd_test(enable = "avx512f")]
12164 unsafe fn test_mm512_loadu_epi64() {
12165 let a = &[4, 3, 2, 5, -8, -9, -64, -50];
12166 let p = a.as_ptr();
12167 let r = _mm512_loadu_epi64(black_box(p));
12168 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12169 assert_eq_m512i(r, e);
12170 }
12171
12172 #[simd_test(enable = "avx512f,avx512vl")]
12173 unsafe fn test_mm256_loadu_epi64() {
12174 let a = &[4, 3, 2, 5];
12175 let p = a.as_ptr();
12176 let r = _mm256_loadu_epi64(black_box(p));
12177 let e = _mm256_setr_epi64x(4, 3, 2, 5);
12178 assert_eq_m256i(r, e);
12179 }
12180
12181 #[simd_test(enable = "avx512f,avx512vl")]
12182 unsafe fn test_mm_loadu_epi64() {
12183 let a = &[4, 3];
12184 let p = a.as_ptr();
12185 let r = _mm_loadu_epi64(black_box(p));
12186 let e = _mm_setr_epi64x(4, 3);
12187 assert_eq_m128i(r, e);
12188 }
12189
12190 #[simd_test(enable = "avx512f")]
12191 unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
12192 let a = _mm512_set1_epi64(9);
12193 let mut r = _mm_undefined_si128();
12194 _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12195 let e = _mm_set1_epi16(9);
12196 assert_eq_m128i(r, e);
12197 }
12198
12199 #[simd_test(enable = "avx512f,avx512vl")]
12200 unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
12201 let a = _mm256_set1_epi64x(9);
12202 let mut r = _mm_set1_epi16(0);
12203 _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12204 let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
12205 assert_eq_m128i(r, e);
12206 }
12207
12208 #[simd_test(enable = "avx512f,avx512vl")]
12209 unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
12210 let a = _mm_set1_epi64x(9);
12211 let mut r = _mm_set1_epi16(0);
12212 _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12213 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
12214 assert_eq_m128i(r, e);
12215 }
12216
12217 #[simd_test(enable = "avx512f")]
12218 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
12219 let a = _mm512_set1_epi64(i64::MAX);
12220 let mut r = _mm_undefined_si128();
12221 _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12222 let e = _mm_set1_epi16(i16::MAX);
12223 assert_eq_m128i(r, e);
12224 }
12225
12226 #[simd_test(enable = "avx512f,avx512vl")]
12227 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
12228 let a = _mm256_set1_epi64x(i64::MAX);
12229 let mut r = _mm_set1_epi16(0);
12230 _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12231 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
12232 assert_eq_m128i(r, e);
12233 }
12234
12235 #[simd_test(enable = "avx512f,avx512vl")]
12236 unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
12237 let a = _mm_set1_epi64x(i64::MAX);
12238 let mut r = _mm_set1_epi16(0);
12239 _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12240 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
12241 assert_eq_m128i(r, e);
12242 }
12243
12244 #[simd_test(enable = "avx512f")]
12245 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
12246 let a = _mm512_set1_epi64(i64::MAX);
12247 let mut r = _mm_undefined_si128();
12248 _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12249 let e = _mm_set1_epi16(u16::MAX as i16);
12250 assert_eq_m128i(r, e);
12251 }
12252
12253 #[simd_test(enable = "avx512f,avx512vl")]
12254 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
12255 let a = _mm256_set1_epi64x(i64::MAX);
12256 let mut r = _mm_set1_epi16(0);
12257 _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12258 let e = _mm_set_epi16(
12259 0,
12260 0,
12261 0,
12262 0,
12263 u16::MAX as i16,
12264 u16::MAX as i16,
12265 u16::MAX as i16,
12266 u16::MAX as i16,
12267 );
12268 assert_eq_m128i(r, e);
12269 }
12270
12271 #[simd_test(enable = "avx512f,avx512vl")]
12272 unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
12273 let a = _mm_set1_epi64x(i64::MAX);
12274 let mut r = _mm_set1_epi16(0);
12275 _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12276 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
12277 assert_eq_m128i(r, e);
12278 }
12279
12280 #[simd_test(enable = "avx512f")]
12281 unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
12282 let a = _mm512_set1_epi64(9);
12283 let mut r = _mm_set1_epi8(0);
12284 _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12285 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
12286 assert_eq_m128i(r, e);
12287 }
12288
12289 #[simd_test(enable = "avx512f,avx512vl")]
12290 unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
12291 let a = _mm256_set1_epi64x(9);
12292 let mut r = _mm_set1_epi8(0);
12293 _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12294 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
12295 assert_eq_m128i(r, e);
12296 }
12297
12298 #[simd_test(enable = "avx512f,avx512vl")]
12299 unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
12300 let a = _mm_set1_epi64x(9);
12301 let mut r = _mm_set1_epi8(0);
12302 _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12303 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
12304 assert_eq_m128i(r, e);
12305 }
12306
12307 #[simd_test(enable = "avx512f")]
12308 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
12309 let a = _mm512_set1_epi64(i64::MAX);
12310 let mut r = _mm_set1_epi8(0);
12311 _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12312 #[rustfmt::skip]
12313 let e = _mm_set_epi8(
12314 0, 0, 0, 0,
12315 0, 0, 0, 0,
12316 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12317 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12318 );
12319 assert_eq_m128i(r, e);
12320 }
12321
12322 #[simd_test(enable = "avx512f,avx512vl")]
12323 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
12324 let a = _mm256_set1_epi64x(i64::MAX);
12325 let mut r = _mm_set1_epi8(0);
12326 _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12327 #[rustfmt::skip]
12328 let e = _mm_set_epi8(
12329 0, 0, 0, 0,
12330 0, 0, 0, 0,
12331 0, 0, 0, 0,
12332 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12333 );
12334 assert_eq_m128i(r, e);
12335 }
12336
12337 #[simd_test(enable = "avx512f,avx512vl")]
12338 unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
12339 let a = _mm_set1_epi64x(i64::MAX);
12340 let mut r = _mm_set1_epi8(0);
12341 _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12342 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
12343 assert_eq_m128i(r, e);
12344 }
12345
12346 #[simd_test(enable = "avx512f")]
12347 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
12348 let a = _mm512_set1_epi64(i64::MAX);
12349 let mut r = _mm_set1_epi8(0);
12350 _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12351 #[rustfmt::skip]
12352 let e = _mm_set_epi8(
12353 0, 0, 0, 0,
12354 0, 0, 0, 0,
12355 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12356 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12357 );
12358 assert_eq_m128i(r, e);
12359 }
12360
12361 #[simd_test(enable = "avx512f,avx512vl")]
12362 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
12363 let a = _mm256_set1_epi64x(i64::MAX);
12364 let mut r = _mm_set1_epi8(0);
12365 _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12366 #[rustfmt::skip]
12367 let e = _mm_set_epi8(
12368 0, 0, 0, 0,
12369 0, 0, 0, 0,
12370 0, 0, 0, 0,
12371 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12372 );
12373 assert_eq_m128i(r, e);
12374 }
12375
12376 #[simd_test(enable = "avx512f,avx512vl")]
12377 unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
12378 let a = _mm_set1_epi64x(i64::MAX);
12379 let mut r = _mm_set1_epi8(0);
12380 _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12381 #[rustfmt::skip]
12382 let e = _mm_set_epi8(
12383 0, 0, 0, 0,
12384 0, 0, 0, 0,
12385 0, 0, 0, 0,
12386 0, 0, u8::MAX as i8, u8::MAX as i8,
12387 );
12388 assert_eq_m128i(r, e);
12389 }
12390
12391 #[simd_test(enable = "avx512f")]
12392 unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
12393 let a = _mm512_set1_epi64(9);
12394 let mut r = _mm256_undefined_si256();
12395 _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12396 let e = _mm256_set1_epi32(9);
12397 assert_eq_m256i(r, e);
12398 }
12399
12400 #[simd_test(enable = "avx512f,avx512vl")]
12401 unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
12402 let a = _mm256_set1_epi64x(9);
12403 let mut r = _mm_set1_epi32(0);
12404 _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12405 let e = _mm_set_epi32(9, 9, 9, 9);
12406 assert_eq_m128i(r, e);
12407 }
12408
12409 #[simd_test(enable = "avx512f,avx512vl")]
12410 unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
12411 let a = _mm_set1_epi64x(9);
12412 let mut r = _mm_set1_epi16(0);
12413 _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12414 let e = _mm_set_epi32(0, 0, 9, 9);
12415 assert_eq_m128i(r, e);
12416 }
12417
12418 #[simd_test(enable = "avx512f")]
12419 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
12420 let a = _mm512_set1_epi64(i64::MAX);
12421 let mut r = _mm256_undefined_si256();
12422 _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12423 let e = _mm256_set1_epi32(i32::MAX);
12424 assert_eq_m256i(r, e);
12425 }
12426
12427 #[simd_test(enable = "avx512f,avx512vl")]
12428 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
12429 let a = _mm256_set1_epi64x(i64::MAX);
12430 let mut r = _mm_set1_epi32(0);
12431 _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
12432 let e = _mm_set1_epi32(i32::MAX);
12433 assert_eq_m128i(r, e);
12434 }
12435
12436 #[simd_test(enable = "avx512f,avx512vl")]
12437 unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
12438 let a = _mm_set1_epi64x(i64::MAX);
12439 let mut r = _mm_set1_epi16(0);
12440 _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
12441 let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
12442 assert_eq_m128i(r, e);
12443 }
12444
12445 #[simd_test(enable = "avx512f")]
12446 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
12447 let a = _mm512_set1_epi64(i64::MAX);
12448 let mut r = _mm256_undefined_si256();
12449 _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12450 let e = _mm256_set1_epi32(u32::MAX as i32);
12451 assert_eq_m256i(r, e);
12452 }
12453
12454 #[simd_test(enable = "avx512f,avx512vl")]
12455 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
12456 let a = _mm256_set1_epi64x(i64::MAX);
12457 let mut r = _mm_set1_epi32(0);
12458 _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
12459 let e = _mm_set1_epi32(u32::MAX as i32);
12460 assert_eq_m128i(r, e);
12461 }
12462
12463 #[simd_test(enable = "avx512f,avx512vl")]
12464 unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
12465 let a = _mm_set1_epi64x(i64::MAX);
12466 let mut r = _mm_set1_epi16(0);
12467 _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
12468 let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
12469 assert_eq_m128i(r, e);
12470 }
12471
12472 #[simd_test(enable = "avx512f")]
12473 unsafe fn test_mm512_storeu_epi64() {
12474 let a = _mm512_set1_epi64(9);
12475 let mut r = _mm512_set1_epi64(0);
12476 _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12477 assert_eq_m512i(r, a);
12478 }
12479
12480 #[simd_test(enable = "avx512f,avx512vl")]
12481 unsafe fn test_mm256_storeu_epi64() {
12482 let a = _mm256_set1_epi64x(9);
12483 let mut r = _mm256_set1_epi64x(0);
12484 _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12485 assert_eq_m256i(r, a);
12486 }
12487
12488 #[simd_test(enable = "avx512f,avx512vl")]
12489 unsafe fn test_mm_storeu_epi64() {
12490 let a = _mm_set1_epi64x(9);
12491 let mut r = _mm_set1_epi64x(0);
12492 _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12493 assert_eq_m128i(r, a);
12494 }
12495
12496 #[simd_test(enable = "avx512f")]
12497 unsafe fn test_mm512_load_epi64() {
12498 #[repr(align(64))]
12499 struct Align {
12500 data: [i64; 8], // 64 bytes
12501 }
12502 let a = Align {
12503 data: [4, 3, 2, 5, -8, -9, -64, -50],
12504 };
12505 let p = (a.data).as_ptr();
12506 let r = _mm512_load_epi64(black_box(p));
12507 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12508 assert_eq_m512i(r, e);
12509 }
12510
12511 #[simd_test(enable = "avx512f,avx512vl")]
12512 unsafe fn test_mm256_load_epi64() {
12513 #[repr(align(64))]
12514 struct Align {
12515 data: [i64; 4],
12516 }
12517 let a = Align { data: [4, 3, 2, 5] };
12518 let p = (a.data).as_ptr();
12519 let r = _mm256_load_epi64(black_box(p));
12520 let e = _mm256_set_epi64x(5, 2, 3, 4);
12521 assert_eq_m256i(r, e);
12522 }
12523
12524 #[simd_test(enable = "avx512f,avx512vl")]
12525 unsafe fn test_mm_load_epi64() {
12526 #[repr(align(64))]
12527 struct Align {
12528 data: [i64; 2],
12529 }
12530 let a = Align { data: [4, 3] };
12531 let p = (a.data).as_ptr();
12532 let r = _mm_load_epi64(black_box(p));
12533 let e = _mm_set_epi64x(3, 4);
12534 assert_eq_m128i(r, e);
12535 }
12536
12537 #[simd_test(enable = "avx512f")]
12538 unsafe fn test_mm512_store_epi64() {
12539 let a = _mm512_set1_epi64(9);
12540 let mut r = _mm512_set1_epi64(0);
12541 _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
12542 assert_eq_m512i(r, a);
12543 }
12544
12545 #[simd_test(enable = "avx512f,avx512vl")]
12546 unsafe fn test_mm256_store_epi64() {
12547 let a = _mm256_set1_epi64x(9);
12548 let mut r = _mm256_set1_epi64x(0);
12549 _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
12550 assert_eq_m256i(r, a);
12551 }
12552
12553 #[simd_test(enable = "avx512f,avx512vl")]
12554 unsafe fn test_mm_store_epi64() {
12555 let a = _mm_set1_epi64x(9);
12556 let mut r = _mm_set1_epi64x(0);
12557 _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
12558 assert_eq_m128i(r, a);
12559 }
12560
12561 #[simd_test(enable = "avx512f")]
12562 unsafe fn test_mm512_load_pd() {
12563 #[repr(align(64))]
12564 struct Align {
12565 data: [f64; 8], // 64 bytes
12566 }
12567 let a = Align {
12568 data: [4., 3., 2., 5., -8., -9., -64., -50.],
12569 };
12570 let p = (a.data).as_ptr();
12571 let r = _mm512_load_pd(black_box(p));
12572 let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
12573 assert_eq_m512d(r, e);
12574 }
12575
12576 #[simd_test(enable = "avx512f")]
12577 unsafe fn test_mm512_store_pd() {
12578 let a = _mm512_set1_pd(9.);
12579 let mut r = _mm512_undefined_pd();
12580 _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
12581 assert_eq_m512d(r, a);
12582 }
12583
12584 #[simd_test(enable = "avx512f")]
12585 unsafe fn test_mm512_test_epi64_mask() {
12586 let a = _mm512_set1_epi64(1 << 0);
12587 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12588 let r = _mm512_test_epi64_mask(a, b);
12589 let e: __mmask8 = 0b11111111;
12590 assert_eq!(r, e);
12591 }
12592
12593 #[simd_test(enable = "avx512f")]
12594 unsafe fn test_mm512_mask_test_epi64_mask() {
12595 let a = _mm512_set1_epi64(1 << 0);
12596 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12597 let r = _mm512_mask_test_epi64_mask(0, a, b);
12598 assert_eq!(r, 0);
12599 let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
12600 let e: __mmask8 = 0b11111111;
12601 assert_eq!(r, e);
12602 }
12603
12604 #[simd_test(enable = "avx512f,avx512vl")]
12605 unsafe fn test_mm256_test_epi64_mask() {
12606 let a = _mm256_set1_epi64x(1 << 0);
12607 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12608 let r = _mm256_test_epi64_mask(a, b);
12609 let e: __mmask8 = 0b00001111;
12610 assert_eq!(r, e);
12611 }
12612
12613 #[simd_test(enable = "avx512f,avx512vl")]
12614 unsafe fn test_mm256_mask_test_epi64_mask() {
12615 let a = _mm256_set1_epi64x(1 << 0);
12616 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12617 let r = _mm256_mask_test_epi64_mask(0, a, b);
12618 assert_eq!(r, 0);
12619 let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
12620 let e: __mmask8 = 0b00001111;
12621 assert_eq!(r, e);
12622 }
12623
12624 #[simd_test(enable = "avx512f,avx512vl")]
12625 unsafe fn test_mm_test_epi64_mask() {
12626 let a = _mm_set1_epi64x(1 << 0);
12627 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12628 let r = _mm_test_epi64_mask(a, b);
12629 let e: __mmask8 = 0b00000011;
12630 assert_eq!(r, e);
12631 }
12632
12633 #[simd_test(enable = "avx512f,avx512vl")]
12634 unsafe fn test_mm_mask_test_epi64_mask() {
12635 let a = _mm_set1_epi64x(1 << 0);
12636 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12637 let r = _mm_mask_test_epi64_mask(0, a, b);
12638 assert_eq!(r, 0);
12639 let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
12640 let e: __mmask8 = 0b00000011;
12641 assert_eq!(r, e);
12642 }
12643
12644 #[simd_test(enable = "avx512f")]
12645 unsafe fn test_mm512_testn_epi64_mask() {
12646 let a = _mm512_set1_epi64(1 << 0);
12647 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12648 let r = _mm512_testn_epi64_mask(a, b);
12649 let e: __mmask8 = 0b00000000;
12650 assert_eq!(r, e);
12651 }
12652
12653 #[simd_test(enable = "avx512f")]
12654 unsafe fn test_mm512_mask_testn_epi64_mask() {
12655 let a = _mm512_set1_epi64(1 << 0);
12656 let b = _mm512_set1_epi64(1 << 1);
12657 let r = _mm512_mask_testn_epi64_mask(0, a, b);
12658 assert_eq!(r, 0);
12659 let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
12660 let e: __mmask8 = 0b11111111;
12661 assert_eq!(r, e);
12662 }
12663
12664 #[simd_test(enable = "avx512f,avx512vl")]
12665 unsafe fn test_mm256_testn_epi64_mask() {
12666 let a = _mm256_set1_epi64x(1 << 0);
12667 let b = _mm256_set1_epi64x(1 << 1);
12668 let r = _mm256_testn_epi64_mask(a, b);
12669 let e: __mmask8 = 0b00001111;
12670 assert_eq!(r, e);
12671 }
12672
12673 #[simd_test(enable = "avx512f,avx512vl")]
12674 unsafe fn test_mm256_mask_testn_epi64_mask() {
12675 let a = _mm256_set1_epi64x(1 << 0);
12676 let b = _mm256_set1_epi64x(1 << 1);
12677 let r = _mm256_mask_testn_epi64_mask(0, a, b);
12678 assert_eq!(r, 0);
12679 let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
12680 let e: __mmask8 = 0b00001111;
12681 assert_eq!(r, e);
12682 }
12683
12684 #[simd_test(enable = "avx512f,avx512vl")]
12685 unsafe fn test_mm_testn_epi64_mask() {
12686 let a = _mm_set1_epi64x(1 << 0);
12687 let b = _mm_set1_epi64x(1 << 1);
12688 let r = _mm_testn_epi64_mask(a, b);
12689 let e: __mmask8 = 0b00000011;
12690 assert_eq!(r, e);
12691 }
12692
12693 #[simd_test(enable = "avx512f,avx512vl")]
12694 unsafe fn test_mm_mask_testn_epi64_mask() {
12695 let a = _mm_set1_epi64x(1 << 0);
12696 let b = _mm_set1_epi64x(1 << 1);
12697 let r = _mm_mask_testn_epi64_mask(0, a, b);
12698 assert_eq!(r, 0);
12699 let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12700 let e: __mmask8 = 0b00000011;
12701 assert_eq!(r, e);
12702 }
12703
12704 #[simd_test(enable = "avx512f")]
12705 unsafe fn test_mm512_mask_set1_epi64() {
12706 let src = _mm512_set1_epi64(2);
12707 let a: i64 = 11;
12708 let r = _mm512_mask_set1_epi64(src, 0, a);
12709 assert_eq_m512i(r, src);
12710 let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12711 let e = _mm512_set1_epi64(11);
12712 assert_eq_m512i(r, e);
12713 }
12714
12715 #[simd_test(enable = "avx512f")]
12716 unsafe fn test_mm512_maskz_set1_epi64() {
12717 let a: i64 = 11;
12718 let r = _mm512_maskz_set1_epi64(0, a);
12719 assert_eq_m512i(r, _mm512_setzero_si512());
12720 let r = _mm512_maskz_set1_epi64(0b11111111, a);
12721 let e = _mm512_set1_epi64(11);
12722 assert_eq_m512i(r, e);
12723 }
12724
12725 #[simd_test(enable = "avx512f,avx512vl")]
12726 unsafe fn test_mm256_mask_set1_epi64() {
12727 let src = _mm256_set1_epi64x(2);
12728 let a: i64 = 11;
12729 let r = _mm256_mask_set1_epi64(src, 0, a);
12730 assert_eq_m256i(r, src);
12731 let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12732 let e = _mm256_set1_epi64x(11);
12733 assert_eq_m256i(r, e);
12734 }
12735
12736 #[simd_test(enable = "avx512f,avx512vl")]
12737 unsafe fn test_mm256_maskz_set1_epi64() {
12738 let a: i64 = 11;
12739 let r = _mm256_maskz_set1_epi64(0, a);
12740 assert_eq_m256i(r, _mm256_setzero_si256());
12741 let r = _mm256_maskz_set1_epi64(0b00001111, a);
12742 let e = _mm256_set1_epi64x(11);
12743 assert_eq_m256i(r, e);
12744 }
12745
12746 #[simd_test(enable = "avx512f,avx512vl")]
12747 unsafe fn test_mm_mask_set1_epi64() {
12748 let src = _mm_set1_epi64x(2);
12749 let a: i64 = 11;
12750 let r = _mm_mask_set1_epi64(src, 0, a);
12751 assert_eq_m128i(r, src);
12752 let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12753 let e = _mm_set1_epi64x(11);
12754 assert_eq_m128i(r, e);
12755 }
12756
12757 #[simd_test(enable = "avx512f,avx512vl")]
12758 unsafe fn test_mm_maskz_set1_epi64() {
12759 let a: i64 = 11;
12760 let r = _mm_maskz_set1_epi64(0, a);
12761 assert_eq_m128i(r, _mm_setzero_si128());
12762 let r = _mm_maskz_set1_epi64(0b00000011, a);
12763 let e = _mm_set1_epi64x(11);
12764 assert_eq_m128i(r, e);
12765 }
12766
12767 #[simd_test(enable = "avx512f")]
12768 unsafe fn test_mm_cvtsd_i64() {
12769 let a = _mm_set_pd(1., -1.5);
12770 let r = _mm_cvtsd_i64(a);
12771 let e: i64 = -2;
12772 assert_eq!(r, e);
12773 }
12774
12775 #[simd_test(enable = "avx512f")]
12776 unsafe fn test_mm_cvtss_i64() {
12777 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12778 let r = _mm_cvtss_i64(a);
12779 let e: i64 = -2;
12780 assert_eq!(r, e);
12781 }
12782
12783 #[simd_test(enable = "avx512f")]
12784 unsafe fn test_mm_cvt_roundi64_ss() {
12785 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12786 let b: i64 = 9;
12787 let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12788 let e = _mm_set_ps(0., -0.5, 1., 9.);
12789 assert_eq_m128(r, e);
12790 }
12791
12792 #[simd_test(enable = "avx512f")]
12793 unsafe fn test_mm_cvt_roundsi64_ss() {
12794 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12795 let b: i64 = 9;
12796 let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12797 let e = _mm_set_ps(0., -0.5, 1., 9.);
12798 assert_eq_m128(r, e);
12799 }
12800
12801 #[simd_test(enable = "avx512f")]
12802 unsafe fn test_mm_cvti64_ss() {
12803 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12804 let b: i64 = 9;
12805 let r = _mm_cvti64_ss(a, b);
12806 let e = _mm_set_ps(0., -0.5, 1., 9.);
12807 assert_eq_m128(r, e);
12808 }
12809
12810 #[simd_test(enable = "avx512f")]
12811 unsafe fn test_mm_cvti64_sd() {
12812 let a = _mm_set_pd(1., -1.5);
12813 let b: i64 = 9;
12814 let r = _mm_cvti64_sd(a, b);
12815 let e = _mm_set_pd(1., 9.);
12816 assert_eq_m128d(r, e);
12817 }
12818
12819 #[simd_test(enable = "avx512f")]
12820 unsafe fn test_mm_cvt_roundsd_si64() {
12821 let a = _mm_set_pd(1., -1.5);
12822 let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12823 let e: i64 = -1;
12824 assert_eq!(r, e);
12825 }
12826
12827 #[simd_test(enable = "avx512f")]
12828 unsafe fn test_mm_cvt_roundsd_i64() {
12829 let a = _mm_set_pd(1., -1.5);
12830 let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12831 let e: i64 = -1;
12832 assert_eq!(r, e);
12833 }
12834
12835 #[simd_test(enable = "avx512f")]
12836 unsafe fn test_mm_cvt_roundsd_u64() {
12837 let a = _mm_set_pd(1., f64::MAX);
12838 let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12839 let e: u64 = u64::MAX;
12840 assert_eq!(r, e);
12841 }
12842
12843 #[simd_test(enable = "avx512f")]
12844 unsafe fn test_mm_cvtsd_u64() {
12845 let a = _mm_set_pd(1., -1.5);
12846 let r = _mm_cvtsd_u64(a);
12847 let e: u64 = u64::MAX;
12848 assert_eq!(r, e);
12849 }
12850
12851 #[simd_test(enable = "avx512f")]
12852 unsafe fn test_mm_cvt_roundss_i64() {
12853 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12854 let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12855 let e: i64 = -1;
12856 assert_eq!(r, e);
12857 }
12858
12859 #[simd_test(enable = "avx512f")]
12860 unsafe fn test_mm_cvt_roundss_si64() {
12861 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12862 let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12863 let e: i64 = -1;
12864 assert_eq!(r, e);
12865 }
12866
12867 #[simd_test(enable = "avx512f")]
12868 unsafe fn test_mm_cvt_roundss_u64() {
12869 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12870 let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12871 let e: u64 = u64::MAX;
12872 assert_eq!(r, e);
12873 }
12874
12875 #[simd_test(enable = "avx512f")]
12876 unsafe fn test_mm_cvtss_u64() {
12877 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12878 let r = _mm_cvtss_u64(a);
12879 let e: u64 = u64::MAX;
12880 assert_eq!(r, e);
12881 }
12882
12883 #[simd_test(enable = "avx512f")]
12884 unsafe fn test_mm_cvttsd_i64() {
12885 let a = _mm_set_pd(1., -1.5);
12886 let r = _mm_cvttsd_i64(a);
12887 let e: i64 = -1;
12888 assert_eq!(r, e);
12889 }
12890
12891 #[simd_test(enable = "avx512f")]
12892 unsafe fn test_mm_cvtt_roundsd_i64() {
12893 let a = _mm_set_pd(1., -1.5);
12894 let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
12895 let e: i64 = -1;
12896 assert_eq!(r, e);
12897 }
12898
12899 #[simd_test(enable = "avx512f")]
12900 unsafe fn test_mm_cvtt_roundsd_si64() {
12901 let a = _mm_set_pd(1., -1.5);
12902 let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
12903 let e: i64 = -1;
12904 assert_eq!(r, e);
12905 }
12906
12907 #[simd_test(enable = "avx512f")]
12908 unsafe fn test_mm_cvtt_roundsd_u64() {
12909 let a = _mm_set_pd(1., -1.5);
12910 let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
12911 let e: u64 = u64::MAX;
12912 assert_eq!(r, e);
12913 }
12914
12915 #[simd_test(enable = "avx512f")]
12916 unsafe fn test_mm_cvttsd_u64() {
12917 let a = _mm_set_pd(1., -1.5);
12918 let r = _mm_cvttsd_u64(a);
12919 let e: u64 = u64::MAX;
12920 assert_eq!(r, e);
12921 }
12922
12923 #[simd_test(enable = "avx512f")]
12924 unsafe fn test_mm_cvttss_i64() {
12925 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12926 let r = _mm_cvttss_i64(a);
12927 let e: i64 = -1;
12928 assert_eq!(r, e);
12929 }
12930
12931 #[simd_test(enable = "avx512f")]
12932 unsafe fn test_mm_cvtt_roundss_i64() {
12933 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12934 let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
12935 let e: i64 = -1;
12936 assert_eq!(r, e);
12937 }
12938
12939 #[simd_test(enable = "avx512f")]
12940 unsafe fn test_mm_cvtt_roundss_si64() {
12941 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12942 let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
12943 let e: i64 = -1;
12944 assert_eq!(r, e);
12945 }
12946
12947 #[simd_test(enable = "avx512f")]
12948 unsafe fn test_mm_cvtt_roundss_u64() {
12949 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12950 let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
12951 let e: u64 = u64::MAX;
12952 assert_eq!(r, e);
12953 }
12954
12955 #[simd_test(enable = "avx512f")]
12956 unsafe fn test_mm_cvttss_u64() {
12957 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12958 let r = _mm_cvttss_u64(a);
12959 let e: u64 = u64::MAX;
12960 assert_eq!(r, e);
12961 }
12962
12963 #[simd_test(enable = "avx512f")]
12964 unsafe fn test_mm_cvtu64_ss() {
12965 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12966 let b: u64 = 9;
12967 let r = _mm_cvtu64_ss(a, b);
12968 let e = _mm_set_ps(0., -0.5, 1., 9.);
12969 assert_eq_m128(r, e);
12970 }
12971
12972 #[simd_test(enable = "avx512f")]
12973 unsafe fn test_mm_cvtu64_sd() {
12974 let a = _mm_set_pd(1., -1.5);
12975 let b: u64 = 9;
12976 let r = _mm_cvtu64_sd(a, b);
12977 let e = _mm_set_pd(1., 9.);
12978 assert_eq_m128d(r, e);
12979 }
12980
12981 #[simd_test(enable = "avx512f")]
12982 unsafe fn test_mm_cvt_roundu64_ss() {
12983 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12984 let b: u64 = 9;
12985 let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12986 let e = _mm_set_ps(0., -0.5, 1., 9.);
12987 assert_eq_m128(r, e);
12988 }
12989
12990 #[simd_test(enable = "avx512f")]
12991 unsafe fn test_mm_cvt_roundu64_sd() {
12992 let a = _mm_set_pd(1., -1.5);
12993 let b: u64 = 9;
12994 let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12995 let e = _mm_set_pd(1., 9.);
12996 assert_eq_m128d(r, e);
12997 }
12998
12999 #[simd_test(enable = "avx512f")]
13000 unsafe fn test_mm_cvt_roundi64_sd() {
13001 let a = _mm_set_pd(1., -1.5);
13002 let b: i64 = 9;
13003 let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13004 let e = _mm_set_pd(1., 9.);
13005 assert_eq_m128d(r, e);
13006 }
13007
13008 #[simd_test(enable = "avx512f")]
13009 unsafe fn test_mm_cvt_roundsi64_sd() {
13010 let a = _mm_set_pd(1., -1.5);
13011 let b: i64 = 9;
13012 let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13013 let e = _mm_set_pd(1., 9.);
13014 assert_eq_m128d(r, e);
13015 }
13016}
13017