1/* Subroutines for the gcc driver.
2 Copyright (C) 2006-2023 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20#define IN_TARGET_CODE 1
21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "tm.h"
26
27const char *host_detect_local_cpu (int argc, const char **argv);
28
29#if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
30#include "cpuid.h"
31#include "common/config/i386/cpuinfo.h"
32#include "common/config/i386/i386-isas.h"
33
34struct cache_desc
35{
36 unsigned sizekb;
37 unsigned assoc;
38 unsigned line;
39};
40
41/* Returns command line parameters that describe size and
42 cache line size of the processor caches. */
43
44static char *
45describe_cache (struct cache_desc level1, struct cache_desc level2)
46{
47 char size[100], line[100], size2[100];
48
49 /* At the moment, gcc does not use the information
50 about the associativity of the cache. */
51
52 snprintf (s: size, maxlen: sizeof (size),
53 format: "--param l1-cache-size=%u ", level1.sizekb);
54 snprintf (s: line, maxlen: sizeof (line),
55 format: "--param l1-cache-line-size=%u ", level1.line);
56
57 snprintf (s: size2, maxlen: sizeof (size2),
58 format: "--param l2-cache-size=%u ", level2.sizekb);
59
60 return concat (size, line, size2, NULL);
61}
62
63/* Detect L2 cache parameters using CPUID extended function 0x80000006. */
64
65static void
66detect_l2_cache (struct cache_desc *level2)
67{
68 unsigned eax, ebx, ecx, edx;
69 unsigned assoc;
70
71 __cpuid (0x80000006, eax, ebx, ecx, edx);
72
73 level2->sizekb = (ecx >> 16) & 0xffff;
74 level2->line = ecx & 0xff;
75
76 assoc = (ecx >> 12) & 0xf;
77 if (assoc == 6)
78 assoc = 8;
79 else if (assoc == 8)
80 assoc = 16;
81 else if (assoc >= 0xa && assoc <= 0xc)
82 assoc = 32 + (assoc - 0xa) * 16;
83 else if (assoc >= 0xd && assoc <= 0xe)
84 assoc = 96 + (assoc - 0xd) * 32;
85
86 level2->assoc = assoc;
87}
88
89/* Returns the description of caches for an AMD processor. */
90
91static const char *
92detect_caches_amd (unsigned max_ext_level)
93{
94 unsigned eax, ebx, ecx, edx;
95
96 struct cache_desc level1, level2 = {.sizekb: 0, .assoc: 0, .line: 0};
97
98 if (max_ext_level < 0x80000005)
99 return "";
100
101 __cpuid (0x80000005, eax, ebx, ecx, edx);
102
103 level1.sizekb = (ecx >> 24) & 0xff;
104 level1.assoc = (ecx >> 16) & 0xff;
105 level1.line = ecx & 0xff;
106
107 if (max_ext_level >= 0x80000006)
108 detect_l2_cache (level2: &level2);
109
110 return describe_cache (level1, level2);
111}
112
113/* Decodes the size, the associativity and the cache line size of
114 L1/L2 caches of an Intel processor. Values are based on
115 "Intel Processor Identification and the CPUID Instruction"
116 [Application Note 485], revision -032, December 2007. */
117
118static void
119decode_caches_intel (unsigned reg, bool xeon_mp,
120 struct cache_desc *level1, struct cache_desc *level2)
121{
122 int i;
123
124 for (i = 24; i >= 0; i -= 8)
125 switch ((reg >> i) & 0xff)
126 {
127 case 0x0a:
128 level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
129 break;
130 case 0x0c:
131 level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
132 break;
133 case 0x0d:
134 level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
135 break;
136 case 0x0e:
137 level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
138 break;
139 case 0x21:
140 level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
141 break;
142 case 0x24:
143 level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
144 break;
145 case 0x2c:
146 level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
147 break;
148 case 0x39:
149 level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
150 break;
151 case 0x3a:
152 level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
153 break;
154 case 0x3b:
155 level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
156 break;
157 case 0x3c:
158 level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
159 break;
160 case 0x3d:
161 level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
162 break;
163 case 0x3e:
164 level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
165 break;
166 case 0x41:
167 level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
168 break;
169 case 0x42:
170 level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
171 break;
172 case 0x43:
173 level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
174 break;
175 case 0x44:
176 level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
177 break;
178 case 0x45:
179 level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
180 break;
181 case 0x48:
182 level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
183 break;
184 case 0x49:
185 if (xeon_mp)
186 break;
187 level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
188 break;
189 case 0x4e:
190 level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
191 break;
192 case 0x60:
193 level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
194 break;
195 case 0x66:
196 level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
197 break;
198 case 0x67:
199 level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
200 break;
201 case 0x68:
202 level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
203 break;
204 case 0x78:
205 level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
206 break;
207 case 0x79:
208 level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
209 break;
210 case 0x7a:
211 level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
212 break;
213 case 0x7b:
214 level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
215 break;
216 case 0x7c:
217 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
218 break;
219 case 0x7d:
220 level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
221 break;
222 case 0x7f:
223 level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
224 break;
225 case 0x80:
226 level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
227 break;
228 case 0x82:
229 level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
230 break;
231 case 0x83:
232 level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
233 break;
234 case 0x84:
235 level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
236 break;
237 case 0x85:
238 level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
239 break;
240 case 0x86:
241 level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
242 break;
243 case 0x87:
244 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
245
246 default:
247 break;
248 }
249}
250
251/* Detect cache parameters using CPUID function 2. */
252
253static void
254detect_caches_cpuid2 (bool xeon_mp,
255 struct cache_desc *level1, struct cache_desc *level2)
256{
257 unsigned regs[4];
258 int nreps, i;
259
260 __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
261
262 nreps = regs[0] & 0x0f;
263 regs[0] &= ~0x0f;
264
265 while (--nreps >= 0)
266 {
267 for (i = 0; i < 4; i++)
268 if (regs[i] && !((regs[i] >> 31) & 1))
269 decode_caches_intel (reg: regs[i], xeon_mp, level1, level2);
270
271 if (nreps)
272 __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
273 }
274}
275
276/* Detect cache parameters using CPUID function 4. This
277 method doesn't require hardcoded tables. */
278
279enum cache_type
280{
281 CACHE_END = 0,
282 CACHE_DATA = 1,
283 CACHE_INST = 2,
284 CACHE_UNIFIED = 3
285};
286
287static void
288detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
289 struct cache_desc *level3)
290{
291 struct cache_desc *cache;
292
293 unsigned eax, ebx, ecx, edx;
294 int count;
295
296 for (count = 0;; count++)
297 {
298 __cpuid_count(4, count, eax, ebx, ecx, edx);
299 switch (eax & 0x1f)
300 {
301 case CACHE_END:
302 return;
303 case CACHE_DATA:
304 case CACHE_UNIFIED:
305 {
306 switch ((eax >> 5) & 0x07)
307 {
308 case 1:
309 cache = level1;
310 break;
311 case 2:
312 cache = level2;
313 break;
314 case 3:
315 cache = level3;
316 break;
317 default:
318 cache = NULL;
319 }
320
321 if (cache)
322 {
323 unsigned sets = ecx + 1;
324 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
325
326 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
327 cache->line = (ebx & 0x0fff) + 1;
328
329 cache->sizekb = (cache->assoc * part
330 * cache->line * sets) / 1024;
331 }
332 }
333 default:
334 break;
335 }
336 }
337}
338
339/* Returns the description of caches for an Intel processor. */
340
341static const char *
342detect_caches_intel (bool xeon_mp, unsigned max_level,
343 unsigned max_ext_level, unsigned *l2sizekb)
344{
345 struct cache_desc level1 = {.sizekb: 0, .assoc: 0, .line: 0}, level2 = {.sizekb: 0, .assoc: 0, .line: 0}, level3 = {.sizekb: 0, .assoc: 0, .line: 0};
346
347 if (max_level >= 4)
348 detect_caches_cpuid4 (level1: &level1, level2: &level2, level3: &level3);
349 else if (max_level >= 2)
350 detect_caches_cpuid2 (xeon_mp, level1: &level1, level2: &level2);
351 else
352 return "";
353
354 if (level1.sizekb == 0)
355 return "";
356
357 /* Let the L3 replace the L2. This assumes inclusive caches
358 and single threaded program for now. */
359 if (level3.sizekb)
360 level2 = level3;
361
362 /* Intel CPUs are equipped with AMD style L2 cache info. Try this
363 method if other methods fail to provide L2 cache parameters. */
364 if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
365 detect_l2_cache (level2: &level2);
366
367 *l2sizekb = level2.sizekb;
368
369 return describe_cache (level1, level2);
370}
371
372/* This will be called by the spec parser in gcc.cc when it sees
373 a %:local_cpu_detect(args) construct. Currently it will be
374 called with either "arch [32|64]" or "tune [32|64]" as argument
375 depending on if -march=native or -mtune=native is to be substituted.
376
377 It returns a string containing new command line parameters to be
378 put at the place of the above two options, depending on what CPU
379 this is executed. E.g. "-march=k8" on an AMD64 machine
380 for -march=native.
381
382 ARGC and ARGV are set depending on the actual arguments given
383 in the spec. */
384
385const char *host_detect_local_cpu (int argc, const char **argv)
386{
387 enum processor_type processor = PROCESSOR_I386;
388 const char *cpu = "i386";
389
390 const char *cache = "";
391 const char *options = "";
392
393 unsigned int ebx, ecx, edx;
394
395 unsigned int max_level, ext_level;
396
397 unsigned int vendor;
398 unsigned int model, family;
399
400 bool arch;
401
402 unsigned int l2sizekb = 0;
403
404 if (argc < 2)
405 return NULL;
406
407 arch = !strcmp (s1: argv[0], s2: "arch");
408
409 if (!arch && strcmp (s1: argv[0], s2: "tune"))
410 return NULL;
411
412 bool codegen_x86_64;
413
414 if (!strcmp (s1: argv[1], s2: "32"))
415 codegen_x86_64 = false;
416 else if (!strcmp (s1: argv[1], s2: "64"))
417 codegen_x86_64 = true;
418 else
419 return NULL;
420
421 struct __processor_model cpu_model = { };
422 struct __processor_model2 cpu_model2 = { };
423 unsigned int cpu_features2[SIZE_OF_CPU_FEATURES] = { };
424
425 if (cpu_indicator_init (cpu_model: &cpu_model, cpu_model2: &cpu_model2, cpu_features2) != 0)
426 goto done;
427
428 vendor = cpu_model.__cpu_vendor;
429 family = cpu_model2.__cpu_family;
430 model = cpu_model2.__cpu_model;
431 max_level = cpu_model2.__cpu_max_level;
432 ext_level = cpu_model2.__cpu_ext_level;
433
434 if (!arch)
435 {
436 if (vendor == VENDOR_AMD
437 || vendor == VENDOR_CENTAUR
438 || vendor == VENDOR_CYRIX
439 || vendor == VENDOR_NSC)
440 cache = detect_caches_amd (max_ext_level: ext_level);
441 else if (vendor == VENDOR_INTEL
442 || vendor == VENDOR_ZHAOXIN)
443 {
444 bool xeon_mp = (family == 15 && model == 6);
445 cache = detect_caches_intel (xeon_mp, max_level,
446 max_ext_level: ext_level, l2sizekb: &l2sizekb);
447 }
448 }
449
450 /* Extended features */
451#define has_feature(f) \
452 has_cpu_feature (&cpu_model, cpu_features2, f)
453
454 if (vendor == VENDOR_AMD)
455 {
456 unsigned int name;
457
458 /* Detect geode processor by its processor signature. */
459 if (ext_level >= 0x80000002)
460 __cpuid (0x80000002, name, ebx, ecx, edx);
461 else
462 name = 0;
463
464 if (name == signature_NSC_ebx)
465 processor = PROCESSOR_GEODE;
466 else if (has_feature (FEATURE_MOVBE) && family == 22)
467 processor = PROCESSOR_BTVER2;
468 else if (has_feature (FEATURE_AVX512F))
469 processor = PROCESSOR_ZNVER4;
470 else if (has_feature (FEATURE_VAES))
471 processor = PROCESSOR_ZNVER3;
472 else if (has_feature (FEATURE_CLWB))
473 processor = PROCESSOR_ZNVER2;
474 else if (has_feature (FEATURE_CLZERO))
475 processor = PROCESSOR_ZNVER1;
476 else if (has_feature (FEATURE_AVX2))
477 processor = PROCESSOR_BDVER4;
478 else if (has_feature (FEATURE_XSAVEOPT))
479 processor = PROCESSOR_BDVER3;
480 else if (has_feature (FEATURE_BMI))
481 processor = PROCESSOR_BDVER2;
482 else if (has_feature (FEATURE_XOP))
483 processor = PROCESSOR_BDVER1;
484 else if (has_feature (FEATURE_SSE4_A)
485 && has_feature (FEATURE_SSSE3))
486 processor = PROCESSOR_BTVER1;
487 else if (has_feature (FEATURE_SSE4_A))
488 processor = PROCESSOR_AMDFAM10;
489 else if (has_feature (FEATURE_SSE2)
490 || has_feature (FEATURE_LM))
491 processor = PROCESSOR_K8;
492 else if (has_feature (FEATURE_3DNOWP) && family == 6)
493 processor = PROCESSOR_ATHLON;
494 else if (has_feature (FEATURE_MMX))
495 processor = PROCESSOR_K6;
496 else
497 processor = PROCESSOR_PENTIUM;
498 }
499 else if (vendor == VENDOR_CENTAUR)
500 {
501 processor = PROCESSOR_GENERIC;
502
503 switch (family)
504 {
505 default:
506 /* We have no idea. */
507 break;
508
509 case 5:
510 if (has_feature (FEATURE_3DNOW)
511 || has_feature (FEATURE_MMX))
512 processor = PROCESSOR_I486;
513 break;
514
515 case 6:
516 if (has_feature (FEATURE_LM))
517 processor = PROCESSOR_K8;
518 else if (model >= 9)
519 processor = PROCESSOR_PENTIUMPRO;
520 else if (model >= 6)
521 processor = PROCESSOR_I486;
522 }
523 }
524 else if (vendor == VENDOR_ZHAOXIN)
525 {
526 processor = PROCESSOR_GENERIC;
527
528 switch (family)
529 {
530 case 7:
531 if (model == 0x3b)
532 processor = PROCESSOR_LUJIAZUI;
533 else if (model >= 0x5b)
534 processor = PROCESSOR_YONGFENG;
535 break;
536 default:
537 break;
538 }
539 }
540 else
541 {
542 switch (family)
543 {
544 case 4:
545 processor = PROCESSOR_I486;
546 break;
547 case 5:
548 processor = PROCESSOR_PENTIUM;
549 break;
550 case 6:
551 processor = PROCESSOR_PENTIUMPRO;
552 break;
553 case 15:
554 processor = PROCESSOR_PENTIUM4;
555 break;
556 default:
557 /* We have no idea. */
558 processor = PROCESSOR_GENERIC;
559 }
560 }
561
562 switch (processor)
563 {
564 case PROCESSOR_I386:
565 /* Default. */
566 break;
567 case PROCESSOR_I486:
568 if (arch && vendor == VENDOR_CENTAUR)
569 {
570 if (model >= 6)
571 cpu = "c3";
572 else if (has_feature (FEATURE_3DNOW))
573 cpu = "winchip2";
574 else
575 /* Assume WinChip C6. */
576 cpu = "winchip-c6";
577 }
578 else
579 cpu = "i486";
580 break;
581 case PROCESSOR_PENTIUM:
582 if (arch && has_feature (FEATURE_MMX))
583 cpu = "pentium-mmx";
584 else
585 cpu = "pentium";
586 break;
587 case PROCESSOR_PENTIUMPRO:
588 cpu = get_intel_cpu (cpu_model: &cpu_model, cpu_model2: &cpu_model2, cpu_features2);
589 if (cpu == NULL)
590 {
591 if (arch)
592 {
593 /* This is unknown family 0x6 CPU. */
594 if (has_feature (FEATURE_AVX512F))
595 {
596 /* Assume Granite Rapids D. */
597 if (has_feature (FEATURE_AMX_COMPLEX))
598 cpu = "graniterapids-d";
599 /* Assume Granite Rapids. */
600 else if (has_feature (FEATURE_AMX_FP16))
601 cpu = "graniterapids";
602 /* Assume Tiger Lake */
603 else if (has_feature (FEATURE_AVX512VP2INTERSECT))
604 cpu = "tigerlake";
605 /* Assume Sapphire Rapids. */
606 else if (has_feature (FEATURE_TSXLDTRK))
607 cpu = "sapphirerapids";
608 /* Assume Cooper Lake */
609 else if (has_feature (FEATURE_AVX512BF16))
610 cpu = "cooperlake";
611 /* Assume Ice Lake Server. */
612 else if (has_feature (FEATURE_WBNOINVD))
613 cpu = "icelake-server";
614 /* Assume Ice Lake. */
615 else if (has_feature (FEATURE_AVX512BITALG))
616 cpu = "icelake-client";
617 /* Assume Cannon Lake. */
618 else if (has_feature (FEATURE_AVX512VBMI))
619 cpu = "cannonlake";
620 /* Assume Knights Mill. */
621 else if (has_feature (FEATURE_AVX5124VNNIW))
622 cpu = "knm";
623 /* Assume Knights Landing. */
624 else if (has_feature (FEATURE_AVX512ER))
625 cpu = "knl";
626 /* Assume Skylake with AVX-512. */
627 else
628 cpu = "skylake-avx512";
629 }
630 else if (has_feature (FEATURE_AVX))
631 {
632 /* Assume Panther Lake. */
633 if (has_feature (FEATURE_PREFETCHI))
634 cpu = "pantherlake";
635 /* Assume Clearwater Forest. */
636 else if (has_feature (FEATURE_USER_MSR))
637 cpu = "clearwaterforest";
638 /* Assume Arrow Lake S. */
639 else if (has_feature (FEATURE_SM3))
640 cpu = "arrowlake-s";
641 /* Assume Grand Ridge. */
642 else if (has_feature (FEATURE_RAOINT))
643 cpu = "grandridge";
644 /* Assume Sierra Forest. */
645 else if (has_feature (FEATURE_AVXVNNIINT8))
646 cpu = "sierraforest";
647 /* Assume Alder Lake. */
648 else if (has_feature (FEATURE_SERIALIZE))
649 cpu = "alderlake";
650 /* Assume Skylake. */
651 else if (has_feature (FEATURE_CLFLUSHOPT))
652 cpu = "skylake";
653 /* Assume Broadwell. */
654 else if (has_feature (FEATURE_ADX))
655 cpu = "broadwell";
656 /* Assume Haswell. */
657 else if (has_feature (FEATURE_AVX2))
658 cpu = "haswell";
659 /* Assume Sandy Bridge. */
660 else
661 cpu = "sandybridge";
662 }
663 else if (has_feature (FEATURE_SSE4_2))
664 {
665 if (has_feature (FEATURE_GFNI))
666 /* Assume Tremont. */
667 cpu = "tremont";
668 else if (has_feature (FEATURE_SGX))
669 /* Assume Goldmont Plus. */
670 cpu = "goldmont-plus";
671 else if (has_feature (FEATURE_XSAVE))
672 /* Assume Goldmont. */
673 cpu = "goldmont";
674 else if (has_feature (FEATURE_MOVBE))
675 /* Assume Silvermont. */
676 cpu = "silvermont";
677 else
678 /* Assume Nehalem. */
679 cpu = "nehalem";
680 }
681 else if (has_feature (FEATURE_SSSE3))
682 {
683 if (has_feature (FEATURE_MOVBE))
684 /* Assume Bonnell. */
685 cpu = "bonnell";
686 else
687 /* Assume Core 2. */
688 cpu = "core2";
689 }
690 else if (has_feature (FEATURE_LM))
691 /* Perhaps some emulator? Assume x86-64, otherwise gcc
692 -march=native would be unusable for 64-bit compilations,
693 as all the CPUs below are 32-bit only. */
694 cpu = "x86-64";
695 else if (has_feature (FEATURE_SSE3))
696 {
697 if (vendor == VENDOR_CENTAUR)
698 /* C7 / Eden "Esther" */
699 cpu = "c7";
700 else
701 /* It is Core Duo. */
702 cpu = "pentium-m";
703 }
704 else if (has_feature (FEATURE_SSE2))
705 /* It is Pentium M. */
706 cpu = "pentium-m";
707 else if (has_feature (FEATURE_SSE))
708 {
709 if (vendor == VENDOR_CENTAUR)
710 {
711 if (model >= 9)
712 /* Eden "Nehemiah" */
713 cpu = "nehemiah";
714 else
715 cpu = "c3-2";
716 }
717 else
718 /* It is Pentium III. */
719 cpu = "pentium3";
720 }
721 else if (has_feature (FEATURE_MMX))
722 /* It is Pentium II. */
723 cpu = "pentium2";
724 else
725 /* Default to Pentium Pro. */
726 cpu = "pentiumpro";
727 }
728 else
729 /* For -mtune, we default to -mtune=generic. */
730 cpu = "generic";
731 }
732 break;
733 case PROCESSOR_PENTIUM4:
734 if (has_feature (FEATURE_SSE3))
735 {
736 if (has_feature (FEATURE_LM))
737 cpu = "nocona";
738 else
739 cpu = "prescott";
740 }
741 else
742 cpu = "pentium4";
743 break;
744 case PROCESSOR_GEODE:
745 cpu = "geode";
746 break;
747 case PROCESSOR_K6:
748 if (arch && has_feature (FEATURE_3DNOW))
749 cpu = "k6-3";
750 else
751 cpu = "k6";
752 break;
753 case PROCESSOR_ATHLON:
754 if (arch && has_feature (FEATURE_SSE))
755 cpu = "athlon-4";
756 else
757 cpu = "athlon";
758 break;
759 case PROCESSOR_K8:
760 if (arch)
761 {
762 if (vendor == VENDOR_CENTAUR)
763 {
764 if (has_feature (FEATURE_SSE4_1))
765 /* Nano 3000 | Nano dual / quad core | Eden X4 */
766 cpu = "nano-3000";
767 else if (has_feature (FEATURE_SSSE3))
768 /* Nano 1000 | Nano 2000 */
769 cpu = "nano";
770 else if (has_feature (FEATURE_SSE3))
771 /* Eden X2 */
772 cpu = "eden-x2";
773 else
774 /* Default to k8 */
775 cpu = "k8";
776 }
777 else if (has_feature (FEATURE_SSE3))
778 cpu = "k8-sse3";
779 else
780 cpu = "k8";
781 }
782 else
783 /* For -mtune, we default to -mtune=k8 */
784 cpu = "k8";
785 break;
786 case PROCESSOR_AMDFAM10:
787 cpu = "amdfam10";
788 break;
789 case PROCESSOR_BDVER1:
790 cpu = "bdver1";
791 break;
792 case PROCESSOR_BDVER2:
793 cpu = "bdver2";
794 break;
795 case PROCESSOR_BDVER3:
796 cpu = "bdver3";
797 break;
798 case PROCESSOR_BDVER4:
799 cpu = "bdver4";
800 break;
801 case PROCESSOR_ZNVER1:
802 cpu = "znver1";
803 break;
804 case PROCESSOR_ZNVER2:
805 cpu = "znver2";
806 break;
807 case PROCESSOR_ZNVER3:
808 cpu = "znver3";
809 break;
810 case PROCESSOR_ZNVER4:
811 cpu = "znver4";
812 break;
813 case PROCESSOR_BTVER1:
814 cpu = "btver1";
815 break;
816 case PROCESSOR_BTVER2:
817 cpu = "btver2";
818 break;
819 case PROCESSOR_LUJIAZUI:
820 cpu = "lujiazui";
821 break;
822 case PROCESSOR_YONGFENG:
823 cpu = "yongfeng";
824 break;
825
826 default:
827 /* Use something reasonable. */
828 if (arch)
829 {
830 if (has_feature (FEATURE_SSSE3))
831 cpu = "core2";
832 else if (has_feature (FEATURE_SSE3))
833 {
834 if (has_feature (FEATURE_LM))
835 cpu = "nocona";
836 else
837 cpu = "prescott";
838 }
839 else if (has_feature (FEATURE_LM))
840 /* Perhaps some emulator? Assume x86-64, otherwise gcc
841 -march=native would be unusable for 64-bit compilations,
842 as all the CPUs below are 32-bit only. */
843 cpu = "x86-64";
844 else if (has_feature (FEATURE_SSE2))
845 cpu = "pentium4";
846 else if (has_feature (FEATURE_CMOV))
847 cpu = "pentiumpro";
848 else if (has_feature (FEATURE_MMX))
849 cpu = "pentium-mmx";
850 else if (has_feature (FEATURE_CMPXCHG8B))
851 cpu = "pentium";
852 }
853 else
854 cpu = "generic";
855 }
856
857 if (arch)
858 {
859 unsigned int i;
860 const char *const neg_option = " -mno-";
861 for (i = 0; i < ARRAY_SIZE (isa_names_table); i++)
862 if (isa_names_table[i].option)
863 {
864 if (has_feature (isa_names_table[i].feature))
865 {
866 if (codegen_x86_64
867 || isa_names_table[i].feature != FEATURE_UINTR)
868 options = concat (options, " ",
869 isa_names_table[i].option, NULL);
870 }
871 else
872 options = concat (options, neg_option,
873 isa_names_table[i].option + 2, NULL);
874 }
875 }
876
877done:
878 return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
879}
880#else
881
882/* If we are compiling with GCC where %EBX register is fixed, then the
883 driver will just ignore -march and -mtune "native" target and will leave
884 to the newly built compiler to generate code for its default target. */
885
886const char *host_detect_local_cpu (int, const char **)
887{
888 return NULL;
889}
890#endif /* __GNUC__ */
891

source code of gcc/config/i386/driver-i386.cc