1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2026 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16Under Section 7 of GPL version 3, you are granted additional
17permissions described in the GCC Runtime Library Exception, version
183.1, as published by the Free Software Foundation.
19
20You should have received a copy of the GNU General Public License and
21a copy of the GCC Runtime Library Exception along with this program;
22see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23<http://www.gnu.org/licenses/>. */
24
25/* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
27
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
30
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
33
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
39
40/* Redefines for option macros. */
41
42#define TARGET_CMPXCHG16B TARGET_CX16
43#define TARGET_CMPXCHG16B_P(x) TARGET_CX16_P(x)
44
45#define TARGET_LP64 TARGET_ABI_64
46#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
47#define TARGET_X32 TARGET_ABI_X32
48#define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
49#define TARGET_16BIT TARGET_CODE16
50#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
51
52#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
53
54#define TARGET_APX_EGPR (ix86_apx_features & apx_egpr)
55#define TARGET_APX_PUSH2POP2 (ix86_apx_features & apx_push2pop2)
56#define TARGET_APX_NDD (ix86_apx_features & apx_ndd)
57#define TARGET_APX_PPX (ix86_apx_features & apx_ppx)
58#define TARGET_APX_NF (ix86_apx_features & apx_nf)
59#define TARGET_APX_CCMP (ix86_apx_features & apx_ccmp)
60#define TARGET_APX_ZU (ix86_apx_features & apx_zu)
61
62#include "config/vxworks-dummy.h"
63
64#include "config/i386/i386-opts.h"
65
66#define MAX_STRINGOP_ALGS 4
67
68/* Specify what algorithm to use for stringops on known size.
69 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
70 known at compile time or estimated via feedback, the SIZE array
71 is walked in order until MAX is greater then the estimate (or -1
72 means infinity). Corresponding ALG is used then.
73 When NOALIGN is true the code guaranting the alignment of the memory
74 block is skipped.
75
76 For example initializer:
77 {{256, loop}, {-1, rep_prefix_4_byte}}
78 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
79 be used otherwise. */
80struct stringop_algs
81{
82 const enum stringop_alg unknown_size;
83 const struct stringop_strategy {
84 /* Several older compilers delete the default constructor because of the
85 const entries (see PR100246). Manually specifying a CTOR works around
86 this issue. Since this header is used by code compiled with the C
87 compiler we must guard the addition. */
88#ifdef __cplusplus
89 constexpr
90 stringop_strategy (int _max = -1, enum stringop_alg _alg = libcall,
91 int _noalign = false)
92 : max (_max), alg (_alg), noalign (_noalign) {}
93#endif
94 const int max;
95 const enum stringop_alg alg;
96 int noalign;
97 } size [MAX_STRINGOP_ALGS];
98};
99
100/* Analog of COSTS_N_INSNS when optimizing for size. */
101#ifndef COSTS_N_BYTES
102#define COSTS_N_BYTES(N) ((N) * 2)
103#endif
104
105
106enum ix86_reduc_unroll_factor{
107 X86_REDUC_FMA,
108 X86_REDUC_DOT_PROD,
109 X86_REDUC_SAD,
110
111 X86_REDUC_LAST
112};
113
114/* Define the specific costs for a given cpu. NB: hard_register is used
115 by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute
116 hard register move costs by register allocator. Relative costs of
117 pseudo register load and store versus pseudo register moves in RTL
118 expressions for TARGET_RTX_COSTS can be different from relative
119 costs of hard registers to get the most efficient operations with
120 pseudo registers. */
121
122struct processor_costs {
123 /* Costs used by register allocator. integer->integer register move
124 cost is 2. */
125 struct
126 {
127 const int movzbl_load; /* cost of loading using movzbl */
128 const int int_load[3]; /* cost of loading integer registers
129 in QImode, HImode and SImode relative
130 to reg-reg move (2). */
131 const int int_store[3]; /* cost of storing integer register
132 in QImode, HImode and SImode */
133 const int fp_move; /* cost of reg,reg fld/fst */
134 const int fp_load[3]; /* cost of loading FP register
135 in SFmode, DFmode and XFmode */
136 const int fp_store[3]; /* cost of storing FP register
137 in SFmode, DFmode and XFmode */
138 const int mmx_move; /* cost of moving MMX register. */
139 const int mmx_load[2]; /* cost of loading MMX register
140 in SImode and DImode */
141 const int mmx_store[2]; /* cost of storing MMX register
142 in SImode and DImode */
143 const int xmm_move; /* cost of moving XMM register. */
144 const int ymm_move; /* cost of moving XMM register. */
145 const int zmm_move; /* cost of moving XMM register. */
146 const int sse_load[5]; /* cost of loading SSE register
147 in 32bit, 64bit, 128bit, 256bit and 512bit */
148 const int sse_store[5]; /* cost of storing SSE register
149 in SImode, DImode and TImode. */
150 const int sse_to_integer; /* cost of moving SSE register to integer. */
151 const int integer_to_sse; /* cost of moving integer register to SSE. */
152 const int mask_to_integer; /* cost of moving mask register to integer. */
153 const int integer_to_mask; /* cost of moving integer register to mask. */
154 const int mask_load[3]; /* cost of loading mask registers
155 in QImode, HImode and SImode. */
156 const int mask_store[3]; /* cost of storing mask register
157 in QImode, HImode and SImode. */
158 const int mask_move; /* cost of moving mask register. */
159 } hard_register;
160
161 const int add; /* cost of an add instruction */
162 const int lea; /* cost of a lea instruction */
163 const int shift_var; /* variable shift costs */
164 const int shift_const; /* constant shift costs */
165 const int mult_init[5]; /* cost of starting a multiply
166 in QImode, HImode, SImode, DImode, TImode*/
167 const int mult_bit; /* cost of multiply per each bit set */
168 const int divide[5]; /* cost of a divide/mod
169 in QImode, HImode, SImode, DImode, TImode*/
170 int movsx; /* The cost of movsx operation. */
171 int movzx; /* The cost of movzx operation. */
172 const int large_insn; /* insns larger than this cost more */
173 const int move_ratio; /* The threshold of number of scalar
174 memory-to-memory move insns. */
175 const int clear_ratio; /* The threshold of number of scalar
176 memory clearing insns. */
177 const int int_load[3]; /* cost of loading integer registers
178 in QImode, HImode and SImode relative
179 to reg-reg move (2). */
180 const int int_store[3]; /* cost of storing integer register
181 in QImode, HImode and SImode */
182 const int sse_load[5]; /* cost of loading SSE register
183 in 32bit, 64bit, 128bit, 256bit and 512bit */
184 const int sse_store[5]; /* cost of storing SSE register
185 in 32bit, 64bit, 128bit, 256bit and 512bit */
186 const int sse_unaligned_load[5];/* cost of unaligned load. */
187 const int sse_unaligned_store[5];/* cost of unaligned store. */
188 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */
189 zmm_move;
190 const int sse_to_integer; /* cost of moving SSE register to integer. */
191 const int integer_to_sse; /* cost of moving integer register to SSE. */
192 const int gather_static, gather_per_elt; /* Cost of gather load is computed
193 as static + per_item * nelts. */
194 const int scatter_static, scatter_per_elt; /* Cost of gather store is
195 computed as static + per_item * nelts. */
196 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
197 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
198 const int prefetch_block; /* bytes moved to cache for prefetch. */
199 const int simultaneous_prefetches; /* number of parallel prefetch
200 operations. */
201 const int branch_cost; /* Default value for BRANCH_COST. */
202 const int fadd; /* cost of FADD and FSUB instructions. */
203 const int fmul; /* cost of FMUL instruction. */
204 const int fdiv; /* cost of FDIV instruction. */
205 const int fabs; /* cost of FABS instruction. */
206 const int fchs; /* cost of FCHS instruction. */
207 const int fsqrt; /* cost of FSQRT instruction. */
208 /* Specify what algorithm
209 to use for stringops on unknown size. */
210 const int sse_op; /* cost of cheap SSE instruction. */
211 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */
212 const int mulss; /* cost of MULSS instructions. */
213 const int mulsd; /* cost of MULSD instructions. */
214 const int fmass; /* cost of FMASS instructions. */
215 const int fmasd; /* cost of FMASD instructions. */
216 const int divss; /* cost of DIVSS instructions. */
217 const int divsd; /* cost of DIVSD instructions. */
218 const int sqrtss; /* cost of SQRTSS instructions. */
219 const int sqrtsd; /* cost of SQRTSD instructions. */
220 const int cvtss2sd; /* cost SSE FP conversions,
221 such as CVTSS2SD. */
222 const int vcvtps2pd256; /* cost 256bit packed FP conversions,
223 such as VCVTPD2PS with larger reg in ymm. */
224 const int vcvtps2pd512; /* cost 512bit packed FP conversions,
225 such as VCVTPD2PS with larger reg in zmm. */
226 const int cvtsi2ss; /* cost of CVTSI2SS instruction. */
227 const int cvtss2si; /* cost of CVT(T)SS2SI instruction. */
228 const int cvtpi2ps; /* cost of CVTPI2PS instruction. */
229 const int cvtps2pi; /* cost of CVT(T)PS2PI instruction. */
230 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp;
231 /* Specify reassociation width for integer,
232 fp, vector integer and vector fp
233 operations. Generally should correspond
234 to number of instructions executed in
235 parallel. See also
236 ix86_reassociation_width. */
237 const unsigned reduc_lat_mult_thr[X86_REDUC_LAST];
238 /* Latency times throughput of
239 FMA/DOT_PROD_EXPR/SAD_EXPR,
240 it's used to determine unroll
241 factor in the vectorizer. */
242 const unsigned vect_unroll_limit; /* Limit how much the autovectorizer
243 may unroll a loop. */
244 struct stringop_algs *memcpy, *memset;
245 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
246 cost model. */
247 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
248 vectorizer cost model. */
249
250 /* The "0:0:8" label alignment specified for some processors generates
251 secondary 8-byte alignment only for those label/jump/loop targets
252 which have primary alignment. */
253 const char *const align_loop; /* Loop alignment. */
254 const char *const align_jump; /* Jump alignment. */
255 const char *const align_label; /* Label alignment. */
256 const char *const align_func; /* Function alignment. */
257
258 const unsigned small_unroll_ninsns; /* Insn count limit for small loop
259 to be unrolled. */
260 const unsigned small_unroll_factor; /* Unroll factor for small loop to
261 be unrolled. */
262 const int br_mispredict_scale; /* Branch mispredict scale for ifcvt
263 threshold. */
264};
265
266extern const struct processor_costs *ix86_cost;
267extern const struct processor_costs ix86_size_cost;
268
269#define ix86_cur_cost() \
270 (optimize_insn_for_size_p () ? &ix86_size_cost : ix86_cost)
271
272/* Macros used in the machine description to test the flags. */
273
274/* configure can arrange to change it. */
275
276#ifndef TARGET_CPU_DEFAULT
277#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
278#endif
279
280#ifndef TARGET_FPMATH_DEFAULT
281#define TARGET_FPMATH_DEFAULT \
282 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
283#endif
284
285#ifndef TARGET_FPMATH_DEFAULT_P
286#define TARGET_FPMATH_DEFAULT_P(x) \
287 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
288#endif
289
290/* If the i387 is disabled or -miamcu is used , then do not return
291 values in it. */
292#define TARGET_FLOAT_RETURNS_IN_80387 \
293 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
294#define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
295 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
296
297/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
298 compile-time constant. */
299#ifdef IN_LIBGCC2
300#undef TARGET_64BIT
301#ifdef __x86_64__
302#define TARGET_64BIT 1
303#else
304#define TARGET_64BIT 0
305#endif
306#else
307#ifndef TARGET_BI_ARCH
308#undef TARGET_64BIT
309#undef TARGET_64BIT_P
310#if TARGET_64BIT_DEFAULT
311#define TARGET_64BIT 1
312#define TARGET_64BIT_P(x) 1
313#else
314#define TARGET_64BIT 0
315#define TARGET_64BIT_P(x) 0
316#endif
317#endif
318#endif
319
320#define HAS_LONG_COND_BRANCH 1
321#define HAS_LONG_UNCOND_BRANCH 1
322
323#define TARGET_CPU_P(CPU) (ix86_tune == PROCESSOR_ ## CPU)
324
325/* Feature tests against the various tunings. */
326enum ix86_tune_indices {
327#undef DEF_TUNE
328#define DEF_TUNE(tune, name, selector) tune,
329#include "x86-tune.def"
330#undef DEF_TUNE
331X86_TUNE_LAST
332};
333
334extern unsigned char ix86_tune_features[X86_TUNE_LAST];
335
336#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
337#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
338#define TARGET_ZERO_EXTEND_WITH_AND \
339 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
340#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
341#define TARGET_BRANCH_PREDICTION_HINTS_NOT_TAKEN \
342 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS_NOT_TAKEN]
343#define TARGET_BRANCH_PREDICTION_HINTS_TAKEN \
344 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS_TAKEN]
345#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
346#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
347#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
348#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
349#define TARGET_PARTIAL_MEMORY_READ_STALL \
350 ix86_tune_features[X86_TUNE_PARTIAL_MEMORY_READ_STALL]
351#define TARGET_PARTIAL_FLAG_REG_STALL \
352 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
353#define TARGET_LCP_STALL \
354 ix86_tune_features[X86_TUNE_LCP_STALL]
355#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
356#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
357#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
358#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
359#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
360#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
361#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
362#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
363#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
364#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
365#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
366#define TARGET_PREFER_KNOWN_REP_MOVSB_STOSB \
367 ix86_tune_features[X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB]
368#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
369 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
370#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
371#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
372#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
373#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
374#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
375#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
376#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
377#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
378#define TARGET_INTEGER_DFMODE_MOVES \
379 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
380#define TARGET_PARTIAL_REG_DEPENDENCY \
381 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
382#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
383 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
384#define TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY \
385 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY]
386#define TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY \
387 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY]
388#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
389 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
390#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
391 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
392#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
393 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
394#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
395#define TARGET_SSE_TYPELESS_STORES \
396 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
397#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
398#define TARGET_MEMORY_MISMATCH_STALL \
399 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
400#define TARGET_PROLOGUE_USING_MOVE \
401 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
402#define TARGET_EPILOGUE_USING_MOVE \
403 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
404#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
405#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
406#define TARGET_INTER_UNIT_MOVES_TO_VEC \
407 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
408#define TARGET_INTER_UNIT_MOVES_FROM_VEC \
409 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
410#define TARGET_INTER_UNIT_CONVERSIONS \
411 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
412#define TARGET_PREFER_BCST_FROM_INTEGER \
413 ix86_tune_features[X86_TUNE_PREFER_BCST_FROM_INTEGER]
414
415#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
416#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
417#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
418#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
419#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
420#define TARGET_PAD_SHORT_FUNCTION \
421 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
422#define TARGET_EXT_80387_CONSTANTS \
423 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
424#define TARGET_AVOID_VECTOR_DECODE \
425 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
426#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
427 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
428#define TARGET_SLOW_IMUL_IMM32_MEM \
429 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
430#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
431#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
432#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
433#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
434#define TARGET_USE_VECTOR_FP_CONVERTS \
435 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
436#define TARGET_USE_VECTOR_CONVERTS \
437 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
438#define TARGET_SLOW_PSHUFB \
439 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
440#define TARGET_AVOID_4BYTE_PREFIXES \
441 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
442#define TARGET_USE_GATHER_2PARTS \
443 ix86_tune_features[X86_TUNE_USE_GATHER_2PARTS]
444#define TARGET_USE_SCATTER_2PARTS \
445 ix86_tune_features[X86_TUNE_USE_SCATTER_2PARTS]
446#define TARGET_USE_GATHER_4PARTS \
447 ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS]
448#define TARGET_USE_SCATTER_4PARTS \
449 ix86_tune_features[X86_TUNE_USE_SCATTER_4PARTS]
450#define TARGET_USE_GATHER_8PARTS \
451 ix86_tune_features[X86_TUNE_USE_GATHER_8PARTS]
452#define TARGET_USE_SCATTER_8PARTS \
453 ix86_tune_features[X86_TUNE_USE_SCATTER_8PARTS]
454#define TARGET_FUSE_CMP_AND_BRANCH_32 \
455 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
456#define TARGET_FUSE_CMP_AND_BRANCH_64 \
457 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
458#define TARGET_FUSE_CMP_AND_BRANCH \
459 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
460 : TARGET_FUSE_CMP_AND_BRANCH_32)
461#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
462 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
463#define TARGET_FUSE_ALU_AND_BRANCH \
464 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
465#define TARGET_FUSE_ALU_AND_BRANCH_MEM \
466 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH_MEM]
467#define TARGET_FUSE_ALU_AND_BRANCH_MEM_IMM \
468 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH_MEM_IMM]
469#define TARGET_FUSE_ALU_AND_BRANCH_RIP_RELATIVE\
470 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH_RIP_RELATIVE]
471#define TARGET_FUSE_MOV_AND_ALU \
472 ix86_tune_features[X86_TUNE_FUSE_MOV_AND_ALU]
473#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
474#define TARGET_AVOID_LEA_FOR_ADDR \
475 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
476#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
477 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
478#define TARGET_AVX256_SPLIT_REGS \
479 ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS]
480#define TARGET_AVX256_AVOID_VEC_PERM \
481 ix86_tune_features[X86_TUNE_AVX256_AVOID_VEC_PERM]
482#define TARGET_AVX512_SPLIT_REGS \
483 ix86_tune_features[X86_TUNE_AVX512_SPLIT_REGS]
484#define TARGET_GENERAL_REGS_SSE_SPILL \
485 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
486#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
487 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
488#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
489 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
490#define TARGET_ADJUST_UNROLL \
491 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
492#define TARGET_AVOID_FALSE_DEP_FOR_BMI \
493 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
494#define TARGET_AVOID_FALSE_DEP_FOR_TZCNT \
495 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_TZCNT]
496#define TARGET_AVOID_FALSE_DEP_FOR_BLS \
497 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BLS]
498#define TARGET_ONE_IF_CONV_INSN \
499 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
500#define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE]
501#define TARGET_EXPAND_ABS \
502 ix86_tune_features[X86_TUNE_EXPAND_ABS]
503#define TARGET_V2DF_REDUCTION_PREFER_HADDPD \
504 ix86_tune_features[X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD]
505#define TARGET_DEST_FALSE_DEP_FOR_GLC \
506 ix86_tune_features[X86_TUNE_DEST_FALSE_DEP_FOR_GLC]
507#define TARGET_SLOW_STC ix86_tune_features[X86_TUNE_SLOW_STC]
508#define TARGET_USE_RCR ix86_tune_features[X86_TUNE_USE_RCR]
509#define TARGET_SSE_MOVCC_USE_BLENDV \
510 ix86_tune_features[X86_TUNE_SSE_MOVCC_USE_BLENDV]
511#define TARGET_ALIGN_TIGHT_LOOPS \
512 ix86_tune_features[X86_TUNE_ALIGN_TIGHT_LOOPS]
513#define TARGET_SSE_REDUCTION_PREFER_PSHUF \
514 ix86_tune_features[X86_TUNE_SSE_REDUCTION_PREFER_PSHUF]
515
516
517/* Feature tests against the various architecture variations. */
518enum ix86_arch_indices {
519 X86_ARCH_CMOV,
520 X86_ARCH_CMPXCHG,
521 X86_ARCH_CMPXCHG8B,
522 X86_ARCH_XADD,
523 X86_ARCH_BSWAP,
524
525 X86_ARCH_LAST
526};
527
528extern unsigned char ix86_arch_features[X86_ARCH_LAST];
529
530#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
531#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
532#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
533#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
534#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
535
536/* For sane SSE instruction set generation we need fcomi instruction.
537 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
538 expands to a sequence that includes conditional move. */
539#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
540
541#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
542
543extern unsigned char ix86_prefetch_sse;
544#define TARGET_PREFETCH_SSE ix86_prefetch_sse
545
546#define ASSEMBLER_DIALECT (ix86_asm_dialect)
547
548#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
549#define TARGET_MIX_SSE_I387 \
550 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
551
552#define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
553#define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE)
554#define TARGET_HARD_XF_REGS (TARGET_80387)
555
556#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
557#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
558#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
559#define TARGET_SUN_TLS 0
560#define TARGET_WIN32_TLS 0
561
562#ifndef TARGET_64BIT_DEFAULT
563#define TARGET_64BIT_DEFAULT 0
564#endif
565#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
566#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
567#endif
568
569#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
570#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
571
572/* Fence to use after loop using storent. */
573
574extern GTY(()) tree x86_mfence;
575#define FENCE_FOLLOWING_MOVNT x86_mfence
576
577/* Once GDB has been enhanced to deal with functions without frame
578 pointers, we can change this to allow for elimination of
579 the frame pointer in leaf functions. */
580#define TARGET_DEFAULT 0
581
582/* Extra bits to force. */
583#define TARGET_SUBTARGET_DEFAULT 0
584#define TARGET_SUBTARGET_ISA_DEFAULT 0
585
586/* Extra bits to force on w/ 32-bit mode. */
587#define TARGET_SUBTARGET32_DEFAULT 0
588#define TARGET_SUBTARGET32_ISA_DEFAULT 0
589
590/* Extra bits to force on w/ 64-bit mode. */
591#define TARGET_SUBTARGET64_DEFAULT 0
592/* Enable MMX, SSE and SSE2 by default. */
593#define TARGET_SUBTARGET64_ISA_DEFAULT \
594 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
595
596/* Replace MACH-O, ifdefs by in-line tests, where possible.
597 (a) Macros defined in config/i386/darwin.h */
598#define TARGET_MACHO 0
599#define TARGET_MACHO_SYMBOL_STUBS 0
600#define MACHOPIC_ATT_STUB 0
601/* (b) Macros defined in config/darwin.h */
602#define MACHO_DYNAMIC_NO_PIC_P 0
603#define MACHOPIC_INDIRECT 0
604#define MACHOPIC_PURE 0
605
606/* For the RDOS */
607#define TARGET_RDOS 0
608
609/* For the Windows 64-bit ABI. */
610#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
611
612/* For the Windows 32-bit ABI. */
613#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
614
615/* This is re-defined by cygming.h. */
616#define TARGET_SEH 0
617
618/* The default abi used by target. */
619#define DEFAULT_ABI SYSV_ABI
620
621/* The default TLS segment register used by target. */
622#define DEFAULT_TLS_SEG_REG \
623 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS)
624
625/* The default TLS segment offset used by target. */
626#define DEFAULT_TLS_SEG_OFFSET 0
627
628/* Subtargets may reset this to 1 in order to enable 96-bit long double
629 with the rounding mode forced to 53 bits. */
630#define TARGET_96_ROUND_53_LONG_DOUBLE 0
631
632#ifndef SUBTARGET_DRIVER_SELF_SPECS
633# define SUBTARGET_DRIVER_SELF_SPECS ""
634#endif
635
636#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS
637
638/* -march=native handling only makes sense with compiler running on
639 an x86 or x86_64 chip. If changing this condition, also change
640 the condition in driver-i386.cc. */
641#if defined(__i386__) || defined(__x86_64__)
642/* In driver-i386.cc. */
643extern const char *host_detect_local_cpu (int argc, const char **argv);
644#define EXTRA_SPEC_FUNCTIONS \
645 { "local_cpu_detect", host_detect_local_cpu },
646#define HAVE_LOCAL_CPU_DETECT
647#endif
648
649#if TARGET_64BIT_DEFAULT
650#define OPT_ARCH64 "!m32"
651#define OPT_ARCH32 "m32"
652#else
653#define OPT_ARCH64 "m64|mx32"
654#define OPT_ARCH32 "m64|mx32:;"
655#endif
656
657/* Support for configure-time defaults of some command line options.
658 The order here is important so that -march doesn't squash the
659 tune or cpu values. */
660#define OPTION_DEFAULT_SPECS \
661 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
662 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
663 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
664 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
665 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
666 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
667 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
668 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
669 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, \
670 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
671
672/* Specs for the compiler proper */
673
674#ifndef CC1_CPU_SPEC
675#define CC1_CPU_SPEC_1 ""
676
677#ifndef HAVE_LOCAL_CPU_DETECT
678#define CC1_CPU_SPEC CC1_CPU_SPEC_1
679#else
680#define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}"
681#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
682"%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \
683 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \
684%{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}"
685#endif
686#endif
687
688/* Target CPU builtins. */
689#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
690
691/* Target Pragmas. */
692#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
693
694#ifndef CC1_SPEC
695#define CC1_SPEC "%(cc1_cpu) "
696#endif
697
698/* This macro defines names of additional specifications to put in the
699 specs that can be used in various specifications like CC1_SPEC. Its
700 definition is an initializer with a subgrouping for each command option.
701
702 Each subgrouping contains a string constant, that defines the
703 specification name, and a string constant that used by the GCC driver
704 program.
705
706 Do not define this macro if it does not need to do anything. */
707
708#ifndef SUBTARGET_EXTRA_SPECS
709#define SUBTARGET_EXTRA_SPECS
710#endif
711
712#define EXTRA_SPECS \
713 { "cc1_cpu", CC1_CPU_SPEC }, \
714 SUBTARGET_EXTRA_SPECS
715
716
717/* Whether to allow x87 floating-point arithmetic on MODE (one of
718 SFmode, DFmode and XFmode) in the current excess precision
719 configuration. */
720#define X87_ENABLE_ARITH(MODE) \
721 (ix86_unsafe_math_optimizations \
722 || ix86_excess_precision == EXCESS_PRECISION_FAST \
723 || (MODE) == XFmode)
724
725/* Likewise, whether to allow direct conversions from integer mode
726 IMODE (HImode, SImode or DImode) to MODE. */
727#define X87_ENABLE_FLOAT(MODE, IMODE) \
728 (ix86_unsafe_math_optimizations \
729 || ix86_excess_precision == EXCESS_PRECISION_FAST \
730 || (MODE) == XFmode \
731 || ((MODE) == DFmode && (IMODE) == SImode) \
732 || (IMODE) == HImode)
733
734/* target machine storage layout */
735
736#define SHORT_TYPE_SIZE 16
737#define INT_TYPE_SIZE 32
738#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
739#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
740#define LONG_LONG_TYPE_SIZE 64
741
742#define WIDEST_HARDWARE_FP_SIZE 80
743
744#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
745#define MAX_BITS_PER_WORD 64
746#else
747#define MAX_BITS_PER_WORD 32
748#endif
749
750/* Define this if most significant byte of a word is the lowest numbered. */
751/* That is true on the 80386. */
752
753#define BITS_BIG_ENDIAN 0
754
755/* Define this if most significant byte of a word is the lowest numbered. */
756/* That is not true on the 80386. */
757#define BYTES_BIG_ENDIAN 0
758
759/* Define this if most significant word of a multiword number is the lowest
760 numbered. */
761/* Not true for 80386 */
762#define WORDS_BIG_ENDIAN 0
763
764/* Width of a word, in units (bytes). */
765#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
766
767#ifndef IN_LIBGCC2
768#define MIN_UNITS_PER_WORD 4
769#endif
770
771/* Allocation boundary (in *bits*) for storing arguments in argument list. */
772#define PARM_BOUNDARY BITS_PER_WORD
773
774/* Boundary (in *bits*) on which stack pointer should be aligned. */
775#define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD)
776
777/* Stack boundary of the main function guaranteed by OS. */
778#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
779
780/* Minimum stack boundary. */
781#define MIN_STACK_BOUNDARY BITS_PER_WORD
782
783/* Boundary (in *bits*) on which the stack pointer prefers to be
784 aligned; the compiler cannot rely on having this alignment. */
785#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
786
787/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
788 both 32bit and 64bit, to support codes that need 128 bit stack
789 alignment for SSE instructions, but can't realign the stack. */
790#define PREFERRED_STACK_BOUNDARY_DEFAULT \
791 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
792
793/* 1 if -mstackrealign should be turned on by default. It will
794 generate an alternate prologue and epilogue that realigns the
795 runtime stack if nessary. This supports mixing codes that keep a
796 4-byte aligned stack, as specified by i386 psABI, with codes that
797 need a 16-byte aligned stack, as required by SSE instructions. */
798#define STACK_REALIGN_DEFAULT 0
799
800/* Boundary (in *bits*) on which the incoming stack is aligned. */
801#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
802
803/* According to Windows x64 software convention, the maximum stack allocatable
804 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
805 instructions allowed to adjust the stack pointer in the epilog, forcing the
806 use of frame pointer for frames larger than 2 GB. This theorical limit
807 is reduced by 256, an over-estimated upper bound for the stack use by the
808 prologue.
809 We define only one threshold for both the prolog and the epilog. When the
810 frame size is larger than this threshold, we allocate the area to save SSE
811 regs, then save them, and then allocate the remaining. There is no SEH
812 unwind info for this later allocation. */
813#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
814
815/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
816 mandatory for the 64-bit ABI, and may or may not be true for other
817 operating systems. */
818#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
819
820/* Minimum allocation boundary for the code of a function. */
821#define FUNCTION_BOUNDARY 8
822
823/* We will and with this value to test if a custom function descriptor needs
824 a static chain. The function boundary must the adjusted so that the bit
825 this represents is no longer part of the address. 0 Disables the custom
826 function descriptors. */
827#define X86_CUSTOM_FUNCTION_TEST 1
828
829/* C++ stores the virtual bit in the lowest bit of function pointers. */
830#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
831
832/* Minimum size in bits of the largest boundary to which any
833 and all fundamental data types supported by the hardware
834 might need to be aligned. No data type wants to be aligned
835 rounder than this.
836
837 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
838 and Pentium Pro XFmode values at 128 bit boundaries.
839
840 When increasing the maximum, also update
841 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
842
843#define BIGGEST_ALIGNMENT \
844 (TARGET_IAMCU ? 32 : (TARGET_AVX512F \
845 ? 512 : (TARGET_AVX ? 256 : 128)))
846
847/* Maximum stack alignment. */
848#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
849
850/* Alignment value for attribute ((aligned)). It is a constant since
851 it is the part of the ABI. We shouldn't change it with -mavx. */
852#define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
853
854/* Decide whether a variable of mode MODE should be 128 bit aligned. */
855#define ALIGN_MODE_128(MODE) \
856 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
857
858/* The published ABIs say that doubles should be aligned on word
859 boundaries, so lower the alignment for structure fields unless
860 -malign-double is set. */
861
862/* ??? Blah -- this macro is used directly by libobjc. Since it
863 supports no vector modes, cut out the complexity and fall back
864 on BIGGEST_FIELD_ALIGNMENT. */
865#ifdef IN_TARGET_LIBS
866#ifdef __x86_64__
867#define BIGGEST_FIELD_ALIGNMENT 128
868#else
869#define BIGGEST_FIELD_ALIGNMENT 32
870#endif
871#else
872#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
873 x86_field_alignment ((TYPE), (COMPUTED))
874#endif
875
876/* If defined, a C expression to compute the alignment for a static
877 variable. TYPE is the data type, and ALIGN is the alignment that
878 the object would ordinarily have. The value of this macro is used
879 instead of that alignment to align the object.
880
881 If this macro is not defined, then ALIGN is used.
882
883 One use of this macro is to increase alignment of medium-size
884 data to make it all fit in fewer cache lines. Another is to
885 cause character arrays to be word-aligned so that `strcpy' calls
886 that copy constants to character arrays can be done inline. */
887
888#define DATA_ALIGNMENT(TYPE, ALIGN) \
889 ix86_data_alignment ((TYPE), (ALIGN), true)
890
891/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
892 some alignment increase, instead of optimization only purposes. E.g.
893 AMD x86-64 psABI says that variables with array type larger than 15 bytes
894 must be aligned to 16 byte boundaries.
895
896 If this macro is not defined, then ALIGN is used. */
897
898#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
899 ix86_data_alignment ((TYPE), (ALIGN), false)
900
901/* If defined, a C expression to compute the alignment for a local
902 variable. TYPE is the data type, and ALIGN is the alignment that
903 the object would ordinarily have. The value of this macro is used
904 instead of that alignment to align the object.
905
906 If this macro is not defined, then ALIGN is used.
907
908 One use of this macro is to increase alignment of medium-size
909 data to make it all fit in fewer cache lines. */
910
911#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
912 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
913
914/* If defined, a C expression to compute the alignment for stack slot.
915 TYPE is the data type, MODE is the widest mode available, and ALIGN
916 is the alignment that the slot would ordinarily have. The value of
917 this macro is used instead of that alignment to align the slot.
918
919 If this macro is not defined, then ALIGN is used when TYPE is NULL,
920 Otherwise, LOCAL_ALIGNMENT will be used.
921
922 One use of this macro is to set alignment of stack slot to the
923 maximum alignment of all possible modes which the slot may have. */
924
925#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
926 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
927
928/* If defined, a C expression to compute the alignment for a local
929 variable DECL.
930
931 If this macro is not defined, then
932 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
933
934 One use of this macro is to increase alignment of medium-size
935 data to make it all fit in fewer cache lines. */
936
937#define LOCAL_DECL_ALIGNMENT(DECL) \
938 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
939
940/* If defined, a C expression to compute the minimum required alignment
941 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
942 MODE, assuming normal alignment ALIGN.
943
944 If this macro is not defined, then (ALIGN) will be used. */
945
946#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
947 ix86_minimum_alignment ((EXP), (MODE), (ALIGN))
948
949
950/* Set this nonzero if move instructions will actually fail to work
951 when given unaligned data. */
952#define STRICT_ALIGNMENT 0
953
954/* If bit field type is int, don't let it cross an int,
955 and give entire struct the alignment of an int. */
956/* Required on the 386 since it doesn't have bit-field insns. */
957#define PCC_BITFIELD_TYPE_MATTERS 1
958
959#define VECTOR_STORE_FLAG_VALUE(MODE) \
960 (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX)
961
962/* Standard register usage. */
963
964/* This processor has special stack-like registers. See reg-stack.cc
965 for details. */
966
967#define STACK_REGS
968
969#define IS_STACK_MODE(MODE) \
970 (X87_FLOAT_MODE_P (MODE) \
971 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
972 || TARGET_MIX_SSE_I387))
973
974/* Number of actual hardware registers.
975 The hardware registers are assigned numbers for the compiler
976 from 0 to just below FIRST_PSEUDO_REGISTER.
977 All registers that the compiler knows about must be given numbers,
978 even those that are not normally considered general registers.
979
980 In the 80386 we give the 8 general purpose registers the numbers 0-7.
981 We number the floating point registers 8-15.
982 Note that registers 0-7 can be accessed as a short or int,
983 while only 0-3 may be used with byte `mov' instructions.
984
985 Reg 16 does not correspond to any hardware register, but instead
986 appears in the RTL as an argument pointer prior to reload, and is
987 eliminated during reloading in favor of either the stack or frame
988 pointer. */
989
990#define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
991
992/* Number of hardware registers that go into the DWARF-2 unwind info.
993 If not defined, equals FIRST_PSEUDO_REGISTER. */
994
995#define DWARF_FRAME_REGISTERS 17
996
997/* 1 for registers that have pervasive standard uses
998 and are not available for the register allocator.
999 On the 80386, the stack pointer is such, as is the arg pointer.
1000
1001 REX registers are disabled for 32bit targets in
1002 TARGET_CONDITIONAL_REGISTER_USAGE. */
1003
1004#define FIXED_REGISTERS \
1005/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1006{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
1007/*arg,flags,fpsr,frame*/ \
1008 1, 1, 1, 1, \
1009/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1010 0, 0, 0, 0, 0, 0, 0, 0, \
1011/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1012 0, 0, 0, 0, 0, 0, 0, 0, \
1013/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1014 0, 0, 0, 0, 0, 0, 0, 0, \
1015/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1016 0, 0, 0, 0, 0, 0, 0, 0, \
1017/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1018 0, 0, 0, 0, 0, 0, 0, 0, \
1019/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1020 0, 0, 0, 0, 0, 0, 0, 0, \
1021/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1022 0, 0, 0, 0, 0, 0, 0, 0, \
1023/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
1024 0, 0, 0, 0, 0, 0, 0, 0, \
1025/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
1026 0, 0, 0, 0, 0, 0, 0, 0} \
1027
1028/* 1 for registers not available across function calls.
1029 These must include the FIXED_REGISTERS and also any
1030 registers that can be used without being saved.
1031 The latter must include the registers where values are returned
1032 and the register where structure-value addresses are passed.
1033 Aside from that, you can include as many other registers as you like.
1034
1035 Value is set to 1 if the register is call used unconditionally.
1036 Bit one is set if the register is call used on TARGET_32BIT ABI.
1037 Bit two is set if the register is call used on TARGET_64BIT ABI.
1038 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
1039
1040 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
1041
1042#define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \
1043 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
1044
1045#define CALL_USED_REGISTERS \
1046/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1047{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1048/*arg,flags,fpsr,frame*/ \
1049 1, 1, 1, 1, \
1050/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1051 1, 1, 1, 1, 1, 1, 6, 6, \
1052/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1053 1, 1, 1, 1, 1, 1, 1, 1, \
1054/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1055 1, 1, 1, 1, 2, 2, 2, 2, \
1056/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1057 6, 6, 6, 6, 6, 6, 6, 6, \
1058/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1059 1, 1, 1, 1, 1, 1, 1, 1, \
1060/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1061 1, 1, 1, 1, 1, 1, 1, 1, \
1062 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1063 1, 1, 1, 1, 1, 1, 1, 1, \
1064/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
1065 1, 1, 1, 1, 1, 1, 1, 1, \
1066/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
1067 1, 1, 1, 1, 1, 1, 1, 1} \
1068
1069/* Order in which to allocate registers. Each register must be
1070 listed once, even those in FIXED_REGISTERS. List frame pointer
1071 late and fixed registers last. Note that, in general, we prefer
1072 registers listed in CALL_USED_REGISTERS, keeping the others
1073 available for storage of persistent values.
1074
1075 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
1076 so this is just empty initializer for array. */
1077
1078#define REG_ALLOC_ORDER \
1079{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1080 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1081 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1082 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1083 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1084 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91}
1085
1086/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1087 to be rearranged based on a particular function. When using sse math,
1088 we want to allocate SSE before x87 registers and vice versa. */
1089
1090#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1091
1092#define INSN_BASE_REG_CLASS(INSN) \
1093 ix86_insn_base_reg_class (INSN)
1094
1095#define REGNO_OK_FOR_INSN_BASE_P(NUM, INSN) \
1096 ix86_regno_ok_for_insn_base_p (NUM, INSN)
1097
1098#define INSN_INDEX_REG_CLASS(INSN) \
1099 ix86_insn_index_reg_class (INSN)
1100
1101#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1102
1103#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1104 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \
1105 && GENERAL_REGNO_P (REGNO) \
1106 && ((MODE) == XFmode || (MODE) == XCmode))
1107
1108#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1109
1110#define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE)
1111
1112#define VALID_AVX256_REG_MODE(MODE) \
1113 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1114 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1115 || (MODE) == V4DFmode || (MODE) == V16HFmode || (MODE) == V16BFmode)
1116
1117#define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1118 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1119
1120#define VALID_AVX512F_SCALAR_MODE(MODE) \
1121 ((MODE) == DImode || (MODE) == DFmode \
1122 || (MODE) == SImode || (MODE) == SFmode \
1123 || (MODE) == HImode || (MODE) == HFmode || (MODE) == BFmode)
1124
1125#define VALID_AVX512F_REG_MODE(MODE) \
1126 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1127 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1128 || (MODE) == V4TImode || (MODE) == V32HFmode || (MODE) == V32BFmode)
1129
1130#define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1131 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1132
1133#define VALID_AVX512VL_128_REG_MODE(MODE) \
1134 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1135 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1136 || (MODE) == TFmode || (MODE) == V1TImode || (MODE) == V8HFmode \
1137 || (MODE) == V8BFmode || (MODE) == TImode)
1138
1139#define VALID_AVX512FP16_REG_MODE(MODE) \
1140 ((MODE) == V8HFmode || (MODE) == V16HFmode || (MODE) == V32HFmode)
1141
1142#define VALID_SSE2_TYPE_MODE(MODE) \
1143 ((MODE) == HFmode || (MODE) == BFmode \
1144 || (MODE) == HCmode || (MODE) == BCmode)
1145
1146#define VALID_SSE2_REG_MODE(MODE) \
1147 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1148 || (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \
1149 || (MODE) == V8BFmode || (MODE) == V4BFmode || (MODE) == V2BFmode \
1150 || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
1151 || (MODE) == V2DImode || (MODE) == V2QImode || (MODE) == HImode \
1152 || (MODE) == DFmode || (MODE) == DImode \
1153 || (MODE) == HFmode || (MODE) == BFmode)
1154
1155#define VALID_SSE_REG_MODE(MODE) \
1156 ((MODE) == V1TImode || (MODE) == TImode \
1157 || (MODE) == V4SFmode || (MODE) == V4SImode \
1158 || (MODE) == SFmode || (MODE) == SImode \
1159 || (MODE) == TFmode || (MODE) == TDmode)
1160
1161#define VALID_MMX_REG_MODE_3DNOW(MODE) \
1162 ((MODE) == V2SFmode || (MODE) == SFmode)
1163
1164/* To match ia32 psABI, V4HFmode should be added here. */
1165#define VALID_MMX_REG_MODE(MODE) \
1166 ((MODE) == V1DImode || (MODE) == DImode \
1167 || (MODE) == V2SImode || (MODE) == SImode \
1168 || (MODE) == V4HImode || (MODE) == V8QImode \
1169 || (MODE) == V4HFmode || (MODE) == V4BFmode)
1170
1171#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1172
1173#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1174
1175#define VALID_FP_MODE_P(MODE) \
1176 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1177 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)
1178
1179#define VALID_INT_MODE_P(MODE) \
1180 ((MODE) == QImode || (MODE) == HImode \
1181 || (MODE) == SImode || (MODE) == DImode \
1182 || (MODE) == CQImode || (MODE) == CHImode \
1183 || (MODE) == CSImode || (MODE) == CDImode \
1184 || (MODE) == SDmode || (MODE) == DDmode \
1185 || (MODE) == HFmode || (MODE) == HCmode || (MODE) == BFmode \
1186 || (MODE) == V2HImode || (MODE) == V2HFmode || (MODE) == V2BFmode \
1187 || (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \
1188 || (TARGET_64BIT \
1189 && ((MODE) == TImode || (MODE) == CTImode \
1190 || (MODE) == TFmode || (MODE) == TCmode \
1191 || (MODE) == V8QImode || (MODE) == V4HImode \
1192 || (MODE) == V2SImode || (MODE) == TDmode)))
1193
1194/* Return true for modes passed in SSE registers. */
1195#define SSE_REG_MODE_P(MODE) \
1196 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1197 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1198 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1199 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1200 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1201 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1202 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1203 || (MODE) == V16SFmode \
1204 || (MODE) == V32HFmode || (MODE) == V16HFmode || (MODE) == V8HFmode \
1205 || (MODE) == V32BFmode || (MODE) == V16BFmode || (MODE) == V8BFmode)
1206
1207#define X87_FLOAT_MODE_P(MODE) \
1208 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1209
1210#define SSE_FLOAT_MODE_P(MODE) \
1211 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1212
1213#define SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P(MODE) \
1214 ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
1215 || (TARGET_AVX512FP16 && (MODE) == HFmode) \
1216 || (TARGET_AVX10_2 && (MODE) == BFmode))
1217
1218#define FMA4_VEC_FLOAT_MODE_P(MODE) \
1219 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1220 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1221
1222#define VALID_BCST_MODE_P(MODE) \
1223 ((MODE) == SFmode || (MODE) == DFmode \
1224 || (MODE) == SImode || (MODE) == DImode \
1225 || (MODE) == HFmode)
1226
1227/* It is possible to write patterns to move flags; but until someone
1228 does it, */
1229#define AVOID_CCMODE_COPIES
1230
1231/* Specify the modes required to caller save a given hard regno.
1232 We do this on i386 to prevent flags from being saved at all.
1233
1234 Kill any attempts to combine saving of modes. */
1235
1236#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1237 (CC_REGNO_P (REGNO) ? VOIDmode \
1238 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1239 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \
1240 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \
1241 && TARGET_PARTIAL_REG_STALL) \
1242 || MASK_REGNO_P (REGNO)) ? SImode \
1243 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \
1244 || MASK_REGNO_P (REGNO)) ? SImode \
1245 : (MODE))
1246
1247/* Specify the registers used for certain standard purposes.
1248 The values of these macros are register numbers. */
1249
1250/* on the 386 the pc register is %eip, and is not usable as a general
1251 register. The ordinary mov instructions won't work */
1252/* #define PC_REGNUM */
1253
1254/* Base register for access to arguments of the function. */
1255#define ARG_POINTER_REGNUM ARGP_REG
1256
1257/* Register to use for pushing function arguments. */
1258#define STACK_POINTER_REGNUM SP_REG
1259
1260/* Base register for access to local variables of the function. */
1261#define FRAME_POINTER_REGNUM FRAME_REG
1262#define HARD_FRAME_POINTER_REGNUM BP_REG
1263
1264#define FIRST_INT_REG AX_REG
1265#define LAST_INT_REG SP_REG
1266
1267#define FIRST_INDEX_REG AX_REG
1268#define LAST_INDEX_REG BP_REG
1269
1270#define FIRST_QI_REG AX_REG
1271#define LAST_QI_REG BX_REG
1272
1273/* First & last stack-like regs */
1274#define FIRST_STACK_REG ST0_REG
1275#define LAST_STACK_REG ST7_REG
1276
1277#define FIRST_SSE_REG XMM0_REG
1278#define LAST_SSE_REG XMM7_REG
1279
1280#define FIRST_MMX_REG MM0_REG
1281#define LAST_MMX_REG MM7_REG
1282
1283#define FIRST_REX_INT_REG R8_REG
1284#define LAST_REX_INT_REG R15_REG
1285
1286#define FIRST_REX_SSE_REG XMM8_REG
1287#define LAST_REX_SSE_REG XMM15_REG
1288
1289#define FIRST_EXT_REX_SSE_REG XMM16_REG
1290#define LAST_EXT_REX_SSE_REG XMM31_REG
1291
1292#define FIRST_MASK_REG MASK0_REG
1293#define LAST_MASK_REG MASK7_REG
1294
1295#define FIRST_REX2_INT_REG R16_REG
1296#define LAST_REX2_INT_REG R31_REG
1297
1298/* Override this in other tm.h files to cope with various OS lossage
1299 requiring a frame pointer. */
1300#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1301#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1302#endif
1303
1304/* Define the shadow offset for asan. Other OS's can override in the
1305 respective tm.h files. */
1306#ifndef SUBTARGET_SHADOW_OFFSET
1307#define SUBTARGET_SHADOW_OFFSET \
1308 (TARGET_LP64 ? HOST_WIDE_INT_C (0x7fff8000) : HOST_WIDE_INT_1 << 29)
1309#endif
1310
1311/* Make sure we can access arbitrary call frames. */
1312#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1313
1314/* Register to hold the addressing base for position independent
1315 code access to data items. We don't use PIC pointer for 64bit
1316 mode. Define the regnum to dummy value to prevent gcc from
1317 pessimizing code dealing with EBX.
1318
1319 To avoid clobbering a call-saved register unnecessarily, we renumber
1320 the pic register when possible. The change is visible after the
1321 prologue has been emitted. */
1322
1323#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
1324
1325#define PIC_OFFSET_TABLE_REGNUM \
1326 (ix86_use_pseudo_pic_reg () \
1327 ? (pic_offset_table_rtx \
1328 ? INVALID_REGNUM \
1329 : REAL_PIC_OFFSET_TABLE_REGNUM) \
1330 : INVALID_REGNUM)
1331
1332#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1333
1334/* This is overridden by <cygwin.h>. */
1335#define MS_AGGREGATE_RETURN 0
1336
1337#define KEEP_AGGREGATE_RETURN_POINTER 0
1338
1339/* Define the classes of registers for register constraints in the
1340 machine description. Also define ranges of constants.
1341
1342 One of the classes must always be named ALL_REGS and include all hard regs.
1343 If there is more than one class, another class must be named NO_REGS
1344 and contain no registers.
1345
1346 The name GENERAL_REGS must be the name of a class (or an alias for
1347 another name such as ALL_REGS). This is the class of registers
1348 that is allowed by "g" or "r" in a register constraint.
1349 Also, registers outside this class are allocated only when
1350 instructions express preferences for them.
1351
1352 The classes must be numbered in nondecreasing order; that is,
1353 a larger-numbered class must never be contained completely
1354 in a smaller-numbered class. This is why CLOBBERED_REGS class
1355 is listed early, even though in 64-bit mode it contains more
1356 registers than just %eax, %ecx, %edx.
1357
1358 For any two classes, it is very desirable that there be another
1359 class that represents their union.
1360
1361 The flags and fpsr registers are in no class. */
1362
1363enum reg_class
1364{
1365 NO_REGS,
1366 AREG, DREG, CREG, BREG, SIREG, DIREG,
1367 AD_REGS, /* %eax/%edx for DImode */
1368 CLOBBERED_REGS, /* call-clobbered integer registers */
1369 Q_REGS, /* %eax %ebx %ecx %edx */
1370 NON_Q_REGS, /* %esi %edi %ebp %esp */
1371 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */
1372 LEGACY_GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1373 LEGACY_INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1374 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1375 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
1376 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
1377 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
1378 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp
1379 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
1380 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
1381 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
1382 GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1383 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1384 INDEX_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp
1385 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1386 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1387 FLOAT_REGS,
1388 SSE_FIRST_REG,
1389 NO_REX_SSE_REGS,
1390 SSE_REGS,
1391 ALL_SSE_REGS,
1392 MMX_REGS,
1393 FLOAT_SSE_REGS,
1394 FLOAT_INT_REGS,
1395 INT_SSE_REGS,
1396 FLOAT_INT_SSE_REGS,
1397 MASK_REGS,
1398 ALL_MASK_REGS,
1399 INT_MASK_REGS,
1400 ALL_REGS,
1401 LIM_REG_CLASSES
1402};
1403
1404#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1405
1406#define INTEGER_CLASS_P(CLASS) \
1407 reg_class_subset_p ((CLASS), GENERAL_REGS)
1408#define FLOAT_CLASS_P(CLASS) \
1409 reg_class_subset_p ((CLASS), FLOAT_REGS)
1410#define SSE_CLASS_P(CLASS) \
1411 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1412#define INT_SSE_CLASS_P(CLASS) \
1413 reg_class_subset_p ((CLASS), INT_SSE_REGS)
1414#define MMX_CLASS_P(CLASS) \
1415 ((CLASS) == MMX_REGS)
1416#define MASK_CLASS_P(CLASS) \
1417 reg_class_subset_p ((CLASS), ALL_MASK_REGS)
1418#define MAYBE_INTEGER_CLASS_P(CLASS) \
1419 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1420#define MAYBE_FLOAT_CLASS_P(CLASS) \
1421 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1422#define MAYBE_SSE_CLASS_P(CLASS) \
1423 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1424#define MAYBE_MMX_CLASS_P(CLASS) \
1425 reg_classes_intersect_p ((CLASS), MMX_REGS)
1426#define MAYBE_MASK_CLASS_P(CLASS) \
1427 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS)
1428
1429#define Q_CLASS_P(CLASS) \
1430 reg_class_subset_p ((CLASS), Q_REGS)
1431
1432#define MAYBE_NON_Q_CLASS_P(CLASS) \
1433 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1434
1435/* Give names of register classes as strings for dump file. */
1436
1437#define REG_CLASS_NAMES \
1438{ "NO_REGS", \
1439 "AREG", "DREG", "CREG", "BREG", \
1440 "SIREG", "DIREG", \
1441 "AD_REGS", \
1442 "CLOBBERED_REGS", \
1443 "Q_REGS", "NON_Q_REGS", \
1444 "TLS_GOTBASE_REGS", \
1445 "LEGACY_GENERAL_REGS", \
1446 "LEGACY_INDEX_REGS", \
1447 "GENERAL_REGS", \
1448 "INDEX_REGS", \
1449 "GENERAL_GPR16", \
1450 "INDEX_GPR16", \
1451 "FP_TOP_REG", "FP_SECOND_REG", \
1452 "FLOAT_REGS", \
1453 "SSE_FIRST_REG", \
1454 "NO_REX_SSE_REGS", \
1455 "SSE_REGS", \
1456 "ALL_SSE_REGS", \
1457 "MMX_REGS", \
1458 "FLOAT_SSE_REGS", \
1459 "FLOAT_INT_REGS", \
1460 "INT_SSE_REGS", \
1461 "FLOAT_INT_SSE_REGS", \
1462 "MASK_REGS", \
1463 "ALL_MASK_REGS", \
1464 "INT_MASK_REGS", \
1465 "ALL_REGS" }
1466
1467/* Define which registers fit in which classes. This is an initializer
1468 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1469
1470 Note that CLOBBERED_REGS are calculated by
1471 TARGET_CONDITIONAL_REGISTER_USAGE. */
1472
1473#define REG_CLASS_CONTENTS \
1474{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
1475 { 0x01, 0x0, 0x0 }, /* AREG */ \
1476 { 0x02, 0x0, 0x0 }, /* DREG */ \
1477 { 0x04, 0x0, 0x0 }, /* CREG */ \
1478 { 0x08, 0x0, 0x0 }, /* BREG */ \
1479 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1480 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1481 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1482 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1483 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1484 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
1485 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1486 { 0x900ff, 0x0, 0x0 }, /* LEGACY_GENERAL_REGS */ \
1487 { 0x7f, 0x0, 0x0 }, /* LEGACY_INDEX_REGS */ \
1488 { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \
1489 { 0x7f, 0xff0, 0xffff000 }, /* INDEX_REGS */ \
1490 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \
1491 { 0x7f, 0xff0, 0x0 }, /* INDEX_GPR16 */ \
1492 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1493 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1494 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1495 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1496 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
1497 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
1498 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
1499{ 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
1500 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
1501 { 0x9ffff, 0xff0, 0xffff000 }, /* FLOAT_INT_REGS */ \
1502 { 0xff900ff, 0xfffffff0, 0xffff00f }, /* INT_SSE_REGS */ \
1503 { 0xff9ffff, 0xfffffff0, 0xffff00f }, /* FLOAT_INT_SSE_REGS */ \
1504 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
1505 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
1506 { 0x900ff, 0xff0, 0xffffff0 }, /* INT_MASK_REGS */ \
1507{ 0xffffffff, 0xffffffff, 0xfffffff } /* ALL_REGS */ \
1508}
1509
1510/* The same information, inverted:
1511 Return the class number of the smallest class containing
1512 reg number REGNO. This could be a conditional expression
1513 or could index an array. */
1514
1515#define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)])
1516
1517#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1518#define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
1519
1520#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
1521#define LEGACY_INT_REGNO_P(N) IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)
1522
1523#define LEGACY_INDEX_REG_P(X) (REG_P (X) && LEGACY_INDEX_REGNO_P (REGNO (X)))
1524#define LEGACY_INDEX_REGNO_P(N) \
1525 IN_RANGE ((N), FIRST_INDEX_REG, LAST_INDEX_REG)
1526
1527#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1528#define REX_INT_REGNO_P(N) \
1529 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1530
1531#define REX2_INT_REG_P(X) (REG_P (X) && REX2_INT_REGNO_P (REGNO (X)))
1532#define REX2_INT_REGNO_P(N) \
1533 IN_RANGE ((N), FIRST_REX2_INT_REG, LAST_REX2_INT_REG)
1534
1535#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1536#define GENERAL_REGNO_P(N) \
1537 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
1538
1539#define INDEX_REG_P(X) (REG_P (X) && INDEX_REGNO_P (REGNO (X)))
1540#define INDEX_REGNO_P(N) \
1541 (LEGACY_INDEX_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
1542
1543#define GENERAL_GPR16_REGNO_P(N) \
1544 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
1545
1546#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1547#define ANY_QI_REGNO_P(N) \
1548 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1549
1550#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1551#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1552
1553#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1554#define SSE_REGNO_P(N) \
1555 (LEGACY_SSE_REGNO_P (N) \
1556 || REX_SSE_REGNO_P (N) \
1557 || EXT_REX_SSE_REGNO_P (N))
1558
1559#define LEGACY_SSE_REGNO_P(N) \
1560 IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG)
1561
1562#define REX_SSE_REGNO_P(N) \
1563 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1564
1565#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
1566
1567#define EXT_REX_SSE_REGNO_P(N) \
1568 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1569
1570#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1571#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1572
1573#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1574#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1575#define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0)
1576
1577#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1578#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1579
1580#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1581#define CC_REGNO_P(X) ((X) == FLAGS_REG)
1582
1583#define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1584#define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1585 || (N) == XMM4_REG \
1586 || (N) == XMM8_REG \
1587 || (N) == XMM12_REG \
1588 || (N) == XMM16_REG \
1589 || (N) == XMM20_REG \
1590 || (N) == XMM24_REG \
1591 || (N) == XMM28_REG)
1592
1593/* First floating point reg */
1594#define FIRST_FLOAT_REG FIRST_STACK_REG
1595#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1596
1597#define GET_SSE_REGNO(N) \
1598 ((N) < 8 ? FIRST_SSE_REG + (N) \
1599 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \
1600 : FIRST_EXT_REX_SSE_REG + (N) - 16)
1601
1602/* The class value for index registers, and the one for base regs. */
1603
1604#define INDEX_REG_CLASS INDEX_REGS
1605#define BASE_REG_CLASS GENERAL_REGS
1606
1607/* Stack layout; function entry, exit and calling. */
1608
1609/* Define this if pushing a word on the stack
1610 makes the stack pointer a smaller address. */
1611#define STACK_GROWS_DOWNWARD 1
1612
1613/* Define this to nonzero if the nominal address of the stack frame
1614 is at the high-address end of the local variables;
1615 that is, each additional local variable allocated
1616 goes at a more negative offset in the frame. */
1617#define FRAME_GROWS_DOWNWARD 1
1618
1619#define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES)
1620
1621/* If defined, the maximum amount of space required for outgoing arguments
1622 will be computed and placed into the variable `crtl->outgoing_args_size'.
1623 No space will be pushed onto the stack for each call; instead, the
1624 function prologue should increase the stack frame size by this amount.
1625
1626 In 32bit mode enabling argument accumulation results in about 5% code size
1627 growth because move instructions are less compact than push. In 64bit
1628 mode the difference is less drastic but visible.
1629
1630 FIXME: Unlike earlier implementations, the size of unwind info seems to
1631 actually grow with accumulation. Is that because accumulated args
1632 unwind info became unnecesarily bloated?
1633
1634 With the 64-bit MS ABI, we can generate correct code with or without
1635 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
1636 generated without accumulated args is terrible.
1637
1638 If stack probes are required, the space used for large function
1639 arguments on the stack must also be probed, so enable
1640 -maccumulate-outgoing-args so this happens in the prologue.
1641
1642 We must use argument accumulation in interrupt function if stack
1643 may be realigned to avoid DRAP. */
1644
1645#define ACCUMULATE_OUTGOING_ARGS \
1646 ((TARGET_ACCUMULATE_OUTGOING_ARGS \
1647 && optimize_function_for_speed_p (cfun)) \
1648 || (cfun->machine->func_type != TYPE_NORMAL \
1649 && crtl->stack_realign_needed) \
1650 || TARGET_STACK_PROBE \
1651 || TARGET_64BIT_MS_ABI \
1652 || (TARGET_MACHO && crtl->profile))
1653
1654/* We want the stack and args grow in opposite directions, even if
1655 targetm.calls.push_argument returns false. */
1656#define PUSH_ARGS_REVERSED 1
1657
1658/* Offset of first parameter from the argument pointer register value. */
1659#define FIRST_PARM_OFFSET(FNDECL) 0
1660
1661/* Define this macro if functions should assume that stack space has been
1662 allocated for arguments even when their values are passed in registers.
1663
1664 The value of this macro is the size, in bytes, of the area reserved for
1665 arguments passed in registers for the function represented by FNDECL.
1666
1667 This space can be allocated by the caller, or be a part of the
1668 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1669 which. */
1670#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1671
1672#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1673 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1674
1675/* Define how to find the value returned by a library function
1676 assuming the value has mode MODE. */
1677
1678#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1679
1680/* Define the size of the result block used for communication between
1681 untyped_call and untyped_return. The block contains a DImode value
1682 followed by the block used by fnsave and frstor. */
1683
1684#define APPLY_RESULT_SIZE (8+108)
1685
1686/* 1 if N is a possible register number for function argument passing. */
1687#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1688
1689/* Define a data type for recording info about an argument list
1690 during the scan of that argument list. This data type should
1691 hold all necessary information about the function itself
1692 and about the args processed so far, enough to enable macros
1693 such as FUNCTION_ARG to determine where the next arg should go. */
1694
1695typedef struct ix86_args {
1696 int words; /* # words passed so far */
1697 int nregs; /* # registers available for passing */
1698 int regno; /* next available register number */
1699 int fastcall; /* fastcall or thiscall calling convention
1700 is used */
1701 int sse_words; /* # sse words passed so far */
1702 int sse_nregs; /* # sse registers available for passing */
1703 int warn_avx512f; /* True when we want to warn
1704 about AVX512F ABI. */
1705 int warn_avx; /* True when we want to warn about AVX ABI. */
1706 int warn_sse; /* True when we want to warn about SSE ABI. */
1707 int warn_mmx; /* True when we want to warn about MMX ABI. */
1708 int warn_empty; /* True when we want to warn about empty classes
1709 passing ABI change. */
1710 int sse_regno; /* next available sse register number */
1711 int mmx_words; /* # mmx words passed so far */
1712 int mmx_nregs; /* # mmx registers available for passing */
1713 int mmx_regno; /* next available mmx register number */
1714 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1715 int caller; /* true if it is caller. */
1716 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1717 SFmode/DFmode arguments should be passed
1718 in SSE registers. Otherwise 0. */
1719 int stdarg; /* Set to 1 if function is stdarg. */
1720 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1721 MS_ABI for ms abi. */
1722 bool preserve_none_abi; /* Set to true if the preserve_none ABI is
1723 used. */
1724 tree decl; /* Callee decl. */
1725} CUMULATIVE_ARGS;
1726
1727/* Initialize a variable CUM of type CUMULATIVE_ARGS
1728 for a call to a function whose data type is FNTYPE.
1729 For a library call, FNTYPE is 0. */
1730
1731#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1732 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1733 (N_NAMED_ARGS) != -1)
1734
1735/* Output assembler code to FILE to increment profiler label # LABELNO
1736 for profiling a function entry. */
1737
1738#define FUNCTION_PROFILER(FILE, LABELNO) \
1739 x86_function_profiler ((FILE), (LABELNO))
1740
1741#define MCOUNT_NAME "_mcount"
1742
1743#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1744
1745#define PROFILE_COUNT_REGISTER "edx"
1746
1747/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1748 the stack pointer does not matter. The value is tested only in
1749 functions that have frame pointers.
1750 No definition is equivalent to always zero. */
1751/* Note on the 386 it might be more efficient not to define this since
1752 we have to restore it ourselves from the frame pointer, in order to
1753 use pop */
1754
1755#define EXIT_IGNORE_STACK 1
1756
1757/* Define this macro as a C expression that is nonzero for registers
1758 used by the epilogue or the `return' pattern. */
1759
1760#define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO)
1761
1762/* Output assembler code for a block containing the constant parts
1763 of a trampoline, leaving space for the variable parts. */
1764
1765/* On the 386, the trampoline contains two instructions:
1766 mov #STATIC,ecx
1767 jmp FUNCTION
1768 The trampoline is generated entirely at runtime. The operand of JMP
1769 is the address of FUNCTION relative to the instruction following the
1770 JMP (which is 5 bytes long). */
1771
1772/* Length in units of the trampoline for entering a nested function. */
1773
1774#define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14)
1775
1776/* Definitions for register eliminations.
1777
1778 This is an array of structures. Each structure initializes one pair
1779 of eliminable registers. The "from" register number is given first,
1780 followed by "to". Eliminations of the same "from" register are listed
1781 in order of preference.
1782
1783 There are two registers that can always be eliminated on the i386.
1784 The frame pointer and the arg pointer can be replaced by either the
1785 hard frame pointer or to the stack pointer, depending upon the
1786 circumstances. The hard frame pointer is not used before reload and
1787 so it is not eligible for elimination. */
1788
1789#define ELIMINABLE_REGS \
1790{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1791 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1792 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1793 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1794
1795/* Define the offset between two registers, one to be eliminated, and the other
1796 its replacement, at the start of a routine. */
1797
1798#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1799 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1800
1801/* Addressing modes, and classification of registers for them. */
1802
1803/* Macros to check register numbers against specific register classes. */
1804
1805/* These assume that REGNO is a hard or pseudo reg number.
1806 They give nonzero only if REGNO is a hard reg of the suitable class
1807 or a pseudo reg currently allocated to a suitable hard reg.
1808 Since they use reg_renumber, they are safe only once reg_renumber
1809 has been allocated, which happens in reginfo.cc during register
1810 allocation. */
1811
1812#define REGNO_OK_FOR_INDEX_P(REGNO) \
1813 (INDEX_REGNO_P (REGNO) \
1814 || INDEX_REGNO_P (reg_renumber[(REGNO)]))
1815
1816#define REGNO_OK_FOR_BASE_P(REGNO) \
1817 (GENERAL_REGNO_P (REGNO) \
1818 || (REGNO) == ARG_POINTER_REGNUM \
1819 || (REGNO) == FRAME_POINTER_REGNUM \
1820 || GENERAL_REGNO_P (reg_renumber[(REGNO)]))
1821
1822/* Non strict versions, pseudos are ok. */
1823#define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
1824 (INDEX_REGNO_P (REGNO) \
1825 || !HARD_REGISTER_NUM_P (REGNO))
1826
1827#define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
1828 (GENERAL_REGNO_P (REGNO) \
1829 || (REGNO) == ARG_POINTER_REGNUM \
1830 || (REGNO) == FRAME_POINTER_REGNUM \
1831 || !HARD_REGISTER_NUM_P (REGNO))
1832
1833/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1834 that is a valid memory address for an instruction.
1835 The MODE argument is the machine mode for the MEM expression
1836 that wants to use this address.
1837
1838 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1839 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1840
1841 See legitimize_pic_address in i386.cc for details as to what
1842 constitutes a legitimate address when -fpic is used. */
1843
1844#define MAX_REGS_PER_ADDRESS 2
1845
1846#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1847
1848/* If defined, a C expression to determine the base term of address X.
1849 This macro is used in only one place: `find_base_term' in alias.cc.
1850
1851 It is always safe for this macro to not be defined. It exists so
1852 that alias analysis can understand machine-dependent addresses.
1853
1854 The typical use of this macro is to handle addresses containing
1855 a label_ref or symbol_ref within an UNSPEC. */
1856
1857#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1858
1859/* Nonzero if the constant value X is a legitimate general operand
1860 when generating PIC code. It is given that flag_pic is on and
1861 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1862
1863#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1864
1865#define STRIP_UNARY(X) (UNARY_P (X) ? XEXP (X, 0) : X)
1866
1867#define SYMBOLIC_CONST(X) \
1868 (SYMBOL_REF_P (X) \
1869 || LABEL_REF_P (X) \
1870 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1871
1872/* Max number of args passed in registers. If this is more than 3, we will
1873 have problems with ebx (register #4), since it is a caller save register and
1874 is also used as the pic register in ELF. So for now, don't allow more than
1875 3 registers to be passed in registers. */
1876
1877/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1878#define X86_64_REGPARM_MAX 6
1879#define X86_64_MS_REGPARM_MAX 4
1880
1881#define X86_32_REGPARM_MAX 3
1882
1883#define REGPARM_MAX \
1884 (TARGET_64BIT \
1885 ? (TARGET_64BIT_MS_ABI \
1886 ? X86_64_MS_REGPARM_MAX \
1887 : X86_64_REGPARM_MAX) \
1888 : X86_32_REGPARM_MAX)
1889
1890#define X86_64_SSE_REGPARM_MAX 8
1891#define X86_64_MS_SSE_REGPARM_MAX 4
1892
1893#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1894
1895#define SSE_REGPARM_MAX \
1896 (TARGET_64BIT \
1897 ? (TARGET_64BIT_MS_ABI \
1898 ? X86_64_MS_SSE_REGPARM_MAX \
1899 : X86_64_SSE_REGPARM_MAX) \
1900 : X86_32_SSE_REGPARM_MAX)
1901
1902#define X86_32_MMX_REGPARM_MAX (TARGET_MMX ? (TARGET_MACHO ? 0 : 3) : 0)
1903
1904#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : X86_32_MMX_REGPARM_MAX)
1905
1906/* Specify the machine mode that this machine uses
1907 for the index in the tablejump instruction. */
1908#define CASE_VECTOR_MODE \
1909 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1910
1911/* Define this as 1 if `char' should by default be signed; else as 0. */
1912#define DEFAULT_SIGNED_CHAR 1
1913
1914/* The constant maximum number of bytes that a single instruction can
1915 move quickly between memory and registers or between two memory
1916 locations. */
1917#define MAX_MOVE_MAX 64
1918
1919/* Max number of bytes we can move from memory to memory in one
1920 reasonably fast instruction, as opposed to MOVE_MAX_PIECES which
1921 is the number of bytes at a time which we can move efficiently.
1922 MOVE_MAX_PIECES defaults to MOVE_MAX. */
1923
1924#define MOVE_MAX \
1925 ((TARGET_AVX512F && ix86_move_max == PVW_AVX512) \
1926 ? 64 \
1927 : ((TARGET_AVX && ix86_move_max >= PVW_AVX256) \
1928 ? 32 \
1929 : ((TARGET_SSE2 \
1930 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
1931 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1932 ? 16 : UNITS_PER_WORD)))
1933
1934/* STORE_MAX_PIECES is the number of bytes at a time that we can store
1935 efficiently. Allow 16/32/64 bytes only if inter-unit move is enabled
1936 since vec_duplicate enabled by inter-unit move is used to implement
1937 store_by_pieces of 16/32/64 bytes. */
1938#define STORE_MAX_PIECES \
1939 (TARGET_INTER_UNIT_MOVES_TO_VEC \
1940 ? ((TARGET_AVX512F && ix86_move_max == PVW_AVX512) \
1941 ? 64 \
1942 : ((TARGET_AVX && ix86_move_max >= PVW_AVX256) \
1943 ? 32 \
1944 : ((TARGET_SSE2 \
1945 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1946 ? 16 : UNITS_PER_WORD))) \
1947 : UNITS_PER_WORD)
1948
1949/* If a memory-to-memory move would take MOVE_RATIO or more simple
1950 move-instruction pairs, we will do a cpymem or libcall instead.
1951 Increasing the value will always make code faster, but eventually
1952 incurs high cost in increased code size.
1953
1954 If you don't define this, a reasonable default is used. */
1955
1956#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1957
1958/* If a clear memory operation would take CLEAR_RATIO or more simple
1959 move-instruction sequences, we will do a clrmem or libcall instead. */
1960
1961#define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2)
1962
1963/* Define if shifts truncate the shift count which implies one can
1964 omit a sign-extension or zero-extension of a shift count.
1965
1966 On i386, shifts do truncate the count. But bit test instructions
1967 take the modulo of the bit offset operand. */
1968
1969/* #define SHIFT_COUNT_TRUNCATED */
1970
1971/* A macro to update M and UNSIGNEDP when an object whose type is
1972 TYPE and which has the specified mode and signedness is to be
1973 stored in a register. This macro is only called when TYPE is a
1974 scalar type.
1975
1976 On i386 it is sometimes useful to promote HImode and QImode
1977 quantities to SImode. The choice depends on target type. */
1978
1979#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1980do { \
1981 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1982 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1983 (MODE) = SImode; \
1984} while (0)
1985
1986/* Specify the machine mode that pointers have.
1987 After generation of rtl, the compiler makes no further distinction
1988 between pointers and any other objects of this machine mode. */
1989#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1990
1991/* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save.
1992 NONLOCAL needs space to save both shadow stack and stack pointers.
1993
1994 FIXME: We only need to save and restore stack pointer in ptr_mode.
1995 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode
1996 to save and restore stack pointer. See
1997 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150
1998 */
1999#define STACK_SAVEAREA_MODE(LEVEL) \
2000 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
2001
2002/* Specify the machine_mode of the size increment
2003 operand of an 'allocate_stack' named pattern. */
2004#define STACK_SIZE_MODE Pmode
2005
2006/* A C expression whose value is zero if pointers that need to be extended
2007 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
2008 greater then zero if they are zero-extended and less then zero if the
2009 ptr_extend instruction should be used. */
2010
2011#define POINTERS_EXTEND_UNSIGNED 1
2012
2013/* A function address in a call instruction
2014 is a byte address (for indexing purposes)
2015 so give the MEM rtx a byte's mode. */
2016#define FUNCTION_MODE QImode
2017
2018
2019/* A C expression for the cost of a branch instruction. A value of 1
2020 is the default; other values are interpreted relative to that. */
2021
2022#define BRANCH_COST(speed_p, predictable_p) \
2023 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
2024
2025/* An integer expression for the size in bits of the largest integer machine
2026 mode that should actually be used. We allow pairs of registers. */
2027#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
2028
2029/* Define this macro as a C expression which is nonzero if accessing
2030 less than a word of memory (i.e. a `char' or a `short') is no
2031 faster than accessing a word of memory, i.e., if such access
2032 require more than one instruction or if there is no difference in
2033 cost between byte and (aligned) word loads.
2034
2035 When this macro is not defined, the compiler will access a field by
2036 finding the smallest containing object; when it is defined, a
2037 fullword load will be used if alignment permits. Unless bytes
2038 accesses are faster than word accesses, using word accesses is
2039 preferable since it may eliminate subsequent memory access if
2040 subsequent accesses occur to other fields in the same word of the
2041 structure, but to different bytes. */
2042
2043#define SLOW_BYTE_ACCESS 0
2044
2045/* Define this macro if it is as good or better to call a constant
2046 function address than to call an address kept in a register.
2047
2048 Desirable on the 386 because a CALL with a constant address is
2049 faster than one with a register address. */
2050
2051#define NO_FUNCTION_CSE 1
2052
2053/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2054 return the mode to be used for the comparison.
2055
2056 For floating-point equality comparisons, CCFPEQmode should be used.
2057 VOIDmode should be used in all other cases.
2058
2059 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2060 possible, to allow for more combinations. */
2061
2062#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2063
2064/* Return nonzero if MODE implies a floating point inequality can be
2065 reversed. */
2066
2067#define REVERSIBLE_CC_MODE(MODE) 1
2068
2069/* A C expression whose value is reversed condition code of the CODE for
2070 comparison done in CC_MODE mode. */
2071#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2072
2073
2074/* Control the assembler format that we output, to the extent
2075 this does not vary between assemblers. */
2076
2077/* How to refer to registers in assembler output.
2078 This sequence is indexed by compiler's hard-register-number (see above). */
2079
2080/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2081 For non floating point regs, the following are the HImode names.
2082
2083 For float regs, the stack top is sometimes referred to as "%st(0)"
2084 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
2085 "y" code. */
2086
2087#define HI_REGISTER_NAMES \
2088{"ax","dx","cx","bx","si","di","bp","sp", \
2089 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2090 "argp", "flags", "fpsr", "frame", \
2091 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2092 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2093 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2094 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
2095 "xmm16", "xmm17", "xmm18", "xmm19", \
2096 "xmm20", "xmm21", "xmm22", "xmm23", \
2097 "xmm24", "xmm25", "xmm26", "xmm27", \
2098 "xmm28", "xmm29", "xmm30", "xmm31", \
2099 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
2100 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2101 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }
2102
2103#define REGISTER_NAMES HI_REGISTER_NAMES
2104
2105#define QI_REGISTER_NAMES \
2106{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"}
2107
2108#define QI_HIGH_REGISTER_NAMES \
2109{"ah", "dh", "ch", "bh"}
2110
2111/* Table of additional register names to use in user input. */
2112
2113#define ADDITIONAL_REGISTER_NAMES \
2114{ \
2115 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \
2116 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \
2117 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
2118 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
2119 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
2120 { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \
2121 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
2122 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
2123 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
2124 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \
2125 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \
2126 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \
2127 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \
2128 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \
2129 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \
2130 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \
2131 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \
2132 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \
2133 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \
2134 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \
2135 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \
2136 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \
2137 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
2138}
2139
2140/* How to renumber registers for gdb. */
2141
2142#define DEBUGGER_REGNO(N) \
2143 (TARGET_64BIT ? debugger64_register_map[(N)] : debugger_register_map[(N)])
2144
2145extern unsigned int const debugger_register_map[FIRST_PSEUDO_REGISTER];
2146extern unsigned int const debugger64_register_map[FIRST_PSEUDO_REGISTER];
2147extern unsigned int const svr4_debugger_register_map[FIRST_PSEUDO_REGISTER];
2148
2149/* Before the prologue, RA is at 0(%esp). */
2150#define INCOMING_RETURN_ADDR_RTX \
2151 gen_rtx_MEM (Pmode, stack_pointer_rtx)
2152
2153/* After the prologue, RA is at -4(AP) in the current frame. */
2154#define RETURN_ADDR_RTX(COUNT, FRAME) \
2155 ((COUNT) == 0 \
2156 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2157 -UNITS_PER_WORD)) \
2158 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD)))
2159
2160/* PC is dbx register 8; let's use that column for RA. */
2161#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2162
2163/* Before the prologue, there are return address and error code for
2164 exception handler on the top of the frame. */
2165#define INCOMING_FRAME_SP_OFFSET \
2166 (cfun->machine->func_type == TYPE_EXCEPTION \
2167 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2168
2169/* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in
2170 .cfi_startproc. */
2171#define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2172
2173/* Describe how we implement __builtin_eh_return. */
2174#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2175#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2176
2177
2178/* Select a format to encode pointers in exception handling data. CODE
2179 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2180 true if the symbol may be affected by dynamic relocations.
2181
2182 ??? All x86 object file formats are capable of representing this.
2183 After all, the relocation needed is the same as for the call insn.
2184 Whether or not a particular assembler allows us to enter such, I
2185 guess we'll have to see. */
2186#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2187 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2188
2189/* These are a couple of extensions to the formats accepted
2190 by asm_fprintf:
2191 %z prints out opcode suffix for word-mode instruction
2192 %r prints out word-mode name for reg_names[arg] */
2193#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
2194 case 'z': \
2195 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \
2196 break; \
2197 \
2198 case 'r': \
2199 { \
2200 unsigned int regno = va_arg ((ARGS), int); \
2201 if (LEGACY_INT_REGNO_P (regno)) \
2202 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \
2203 fputs (reg_names[regno], (FILE)); \
2204 break; \
2205 }
2206
2207/* This is how to output an insn to push a register on the stack. */
2208
2209#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2210 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO))
2211
2212/* This is how to output an insn to pop a register from the stack. */
2213
2214#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2215 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO))
2216
2217/* This is how to output an element of a case-vector that is absolute. */
2218
2219#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2220 ix86_output_addr_vec_elt ((FILE), (VALUE))
2221
2222/* This is how to output an element of a case-vector that is relative. */
2223
2224#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2225 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2226
2227/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2228
2229#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2230{ \
2231 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2232 (PTR) += TARGET_AVX ? 1 : 2; \
2233}
2234
2235/* A C statement or statements which output an assembler instruction
2236 opcode to the stdio stream STREAM. The macro-operand PTR is a
2237 variable of type `char *' which points to the opcode name in
2238 its "internal" form--the form that is written in the machine
2239 description. */
2240
2241#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2242 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2243
2244/* A C statement to output to the stdio stream FILE an assembler
2245 command to pad the location counter to a multiple of 1<<LOG
2246 bytes if it is within MAX_SKIP bytes. */
2247
2248#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2249# define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2250 do { \
2251 if ((LOG) != 0) { \
2252 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \
2253 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2254 else \
2255 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2256 } \
2257 } while (0)
2258#endif
2259
2260/* Write the extra assembler code needed to declare a function
2261 properly. */
2262
2263#undef ASM_OUTPUT_FUNCTION_LABEL
2264#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2265 ix86_asm_output_function_label ((FILE), (NAME), (DECL))
2266
2267/* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM.
2268 If not defined, assemble_name will be used to output the name of the
2269 symbol. This macro may be used to modify the way a symbol is referenced
2270 depending on information encoded by TARGET_ENCODE_SECTION_INFO. */
2271
2272#ifndef ASM_OUTPUT_SYMBOL_REF
2273#define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \
2274 do { \
2275 const char *name \
2276 = assemble_name_resolve (XSTR (SYM, 0)); \
2277 /* In -masm=att wrap identifiers that start with $ \
2278 into parens. */ \
2279 if (ASSEMBLER_DIALECT == ASM_ATT \
2280 && name[0] == '$' \
2281 && user_label_prefix[0] == '\0') \
2282 { \
2283 fputc ('(', (FILE)); \
2284 assemble_name_raw ((FILE), name); \
2285 fputc (')', (FILE)); \
2286 } \
2287 else \
2288 assemble_name_raw ((FILE), name); \
2289 } while (0)
2290#endif
2291
2292/* In Intel syntax, we have to quote user-defined labels that would
2293 match (unprefixed) registers or operators. */
2294
2295#undef ASM_OUTPUT_LABELREF
2296#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
2297 ix86_asm_output_labelref ((STREAM), user_label_prefix, (NAME))
2298
2299/* Under some conditions we need jump tables in the text section,
2300 because the assembler cannot handle label differences between
2301 sections. */
2302
2303#define JUMP_TABLES_IN_TEXT_SECTION \
2304 (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA))
2305
2306/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2307 and switch back. For x86 we do this only to save a few bytes that
2308 would otherwise be unused in the text section. */
2309#define CRT_MKSTR2(VAL) #VAL
2310#define CRT_MKSTR(x) CRT_MKSTR2(x)
2311
2312#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2313 asm (SECTION_OP "\n\t" \
2314 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2315 TEXT_SECTION_ASM_OP);
2316
2317/* Default threshold for putting data in large sections
2318 with x86-64 medium memory model */
2319#define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2320
2321/* Which processor to tune code generation for. These must be in sync
2322 with processor_cost_table in i386-options.cc. */
2323
2324#define GOT_ALIAS_SET ix86_GOT_alias_set ()
2325
2326enum processor_type
2327{
2328 PROCESSOR_GENERIC = 0,
2329 PROCESSOR_I386, /* 80386 */
2330 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2331 PROCESSOR_PENTIUM,
2332 PROCESSOR_LAKEMONT,
2333 PROCESSOR_PENTIUMPRO,
2334 PROCESSOR_PENTIUM4,
2335 PROCESSOR_NOCONA,
2336 PROCESSOR_CORE2,
2337 PROCESSOR_NEHALEM,
2338 PROCESSOR_SANDYBRIDGE,
2339 PROCESSOR_HASWELL,
2340 PROCESSOR_BONNELL,
2341 PROCESSOR_SILVERMONT,
2342 PROCESSOR_GOLDMONT,
2343 PROCESSOR_GOLDMONT_PLUS,
2344 PROCESSOR_TREMONT,
2345 PROCESSOR_SIERRAFOREST,
2346 PROCESSOR_GRANDRIDGE,
2347 PROCESSOR_CLEARWATERFOREST,
2348 PROCESSOR_SKYLAKE,
2349 PROCESSOR_SKYLAKE_AVX512,
2350 PROCESSOR_CANNONLAKE,
2351 PROCESSOR_ICELAKE_CLIENT,
2352 PROCESSOR_ICELAKE_SERVER,
2353 PROCESSOR_CASCADELAKE,
2354 PROCESSOR_TIGERLAKE,
2355 PROCESSOR_COOPERLAKE,
2356 PROCESSOR_SAPPHIRERAPIDS,
2357 PROCESSOR_ALDERLAKE,
2358 PROCESSOR_ROCKETLAKE,
2359 PROCESSOR_GRANITERAPIDS,
2360 PROCESSOR_GRANITERAPIDS_D,
2361 PROCESSOR_ARROWLAKE,
2362 PROCESSOR_ARROWLAKE_S,
2363 PROCESSOR_PANTHERLAKE,
2364 PROCESSOR_DIAMONDRAPIDS,
2365 PROCESSOR_NOVALAKE,
2366 PROCESSOR_INTEL,
2367 PROCESSOR_LUJIAZUI,
2368 PROCESSOR_YONGFENG,
2369 PROCESSOR_SHIJIDADAO,
2370 PROCESSOR_GEODE,
2371 PROCESSOR_K6,
2372 PROCESSOR_ATHLON,
2373 PROCESSOR_K8,
2374 PROCESSOR_AMDFAM10,
2375 PROCESSOR_BDVER1,
2376 PROCESSOR_BDVER2,
2377 PROCESSOR_BDVER3,
2378 PROCESSOR_BDVER4,
2379 PROCESSOR_BTVER1,
2380 PROCESSOR_BTVER2,
2381 PROCESSOR_ZNVER1,
2382 PROCESSOR_ZNVER2,
2383 PROCESSOR_ZNVER3,
2384 PROCESSOR_ZNVER4,
2385 PROCESSOR_ZNVER5,
2386 PROCESSOR_ZNVER6,
2387 PROCESSOR_max
2388};
2389
2390#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
2391extern const char *const processor_names[];
2392
2393#include "wide-int-bitmask.h"
2394
2395enum pta_flag
2396{
2397#define DEF_PTA(NAME) _ ## NAME,
2398#include "i386-isa.def"
2399#undef DEF_PTA
2400 END_PTA
2401};
2402
2403/* wide_int_bitmask can handle only 128 flags. */
2404STATIC_ASSERT (END_PTA <= 128);
2405
2406#define WIDE_INT_BITMASK_FROM_NTH(N) (N < 64 ? wide_int_bitmask (0, 1ULL << N) \
2407 : wide_int_bitmask (1ULL << (N - 64), 0))
2408
2409#define DEF_PTA(NAME) constexpr wide_int_bitmask PTA_ ## NAME \
2410 = WIDE_INT_BITMASK_FROM_NTH ((pta_flag) _ ## NAME);
2411#include "i386-isa.def"
2412#undef DEF_PTA
2413
2414constexpr wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE
2415 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR;
2416constexpr wide_int_bitmask PTA_X86_64_V2 = (PTA_X86_64_BASELINE
2417 & (~PTA_NO_SAHF))
2418 | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_SSSE3;
2419constexpr wide_int_bitmask PTA_X86_64_V3 = PTA_X86_64_V2
2420 | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2421 | PTA_MOVBE | PTA_XSAVE;
2422constexpr wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3
2423 | PTA_AVX512F | PTA_AVX512BW | PTA_AVX512CD | PTA_AVX512DQ | PTA_AVX512VL;
2424
2425constexpr wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2426 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
2427constexpr wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
2428 | PTA_POPCNT;
2429constexpr wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
2430constexpr wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
2431 | PTA_XSAVEOPT;
2432constexpr wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
2433 | PTA_RDRND | PTA_F16C;
2434constexpr wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
2435 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
2436constexpr wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
2437 | PTA_PRFCHW;
2438constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES
2439 | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
2440constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
2441 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2442 | PTA_CLWB;
2443constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512
2444 | PTA_AVX512VNNI;
2445constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
2446constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
2447 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2448 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
2449constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
2450 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
2451 | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
2452constexpr wide_int_bitmask PTA_ROCKETLAKE = PTA_ICELAKE_CLIENT & ~PTA_SGX;
2453constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT
2454 | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB;
2455constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
2456 | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL | PTA_WIDEKL;
2457constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_ICELAKE_SERVER | PTA_MOVDIRI
2458 | PTA_MOVDIR64B | PTA_ENQCMD | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG
2459 | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16
2460 | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16 | PTA_AVX512BF16;
2461constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
2462constexpr wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE
2463 | PTA_RDRND | PTA_PRFCHW;
2464constexpr wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA
2465 | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT
2466 | PTA_XSAVEOPT | PTA_FSGSBASE;
2467constexpr wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
2468 | PTA_SGX | PTA_PTWRITE;
2469constexpr wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
2470 | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
2471constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_GOLDMONT_PLUS | PTA_CLWB
2472 | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_WAITPKG | PTA_ADX | PTA_AVX
2473 | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2474 | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
2475 | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
2476constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_CLDEMOTE
2477 | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD
2478 | PTA_ENQCMD | PTA_UINTR;
2479constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
2480 | PTA_PREFETCHI | PTA_AVX10_1;
2481constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS
2482 | PTA_AMX_COMPLEX;
2483constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST;
2484constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA
2485 | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR;
2486constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16
2487 | PTA_SHA512 | PTA_SM3 | PTA_SM4;
2488constexpr wide_int_bitmask PTA_CLEARWATERFOREST =
2489 (PTA_SIERRAFOREST & (~(PTA_KL | PTA_WIDEKL))) | PTA_AVXVNNIINT16 | PTA_SHA512
2490 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI;
2491constexpr wide_int_bitmask PTA_PANTHERLAKE =
2492 (PTA_ARROWLAKE_S & (~(PTA_KL | PTA_WIDEKL)));
2493constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D
2494 | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8
2495 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
2496 | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_MOVRS
2497 | PTA_AMX_MOVRS;
2498constexpr wide_int_bitmask PTA_NOVALAKE = PTA_PANTHERLAKE | PTA_PREFETCHI
2499 | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ
2500 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_AVX512VNNI | PTA_AVX512VBMI2
2501 | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ | PTA_AVX512FP16 | PTA_AVX512BF16
2502 | PTA_AVX10_1 | PTA_AVX10_2 | PTA_APX_F | PTA_MOVRS;
2503
2504constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
2505 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_POPCNT | PTA_LZCNT
2506 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL
2507 | PTA_AVX | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE;
2508constexpr wide_int_bitmask PTA_BDVER2 = PTA_BDVER1 | PTA_BMI | PTA_TBM
2509 | PTA_F16C | PTA_FMA;
2510constexpr wide_int_bitmask PTA_BDVER3 = PTA_BDVER2 | PTA_XSAVEOPT
2511 | PTA_FSGSBASE;
2512constexpr wide_int_bitmask PTA_BDVER4 = PTA_BDVER3 | PTA_AVX2 | PTA_BMI2
2513 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX;
2514
2515constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
2516 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_POPCNT | PTA_LZCNT
2517 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL
2518 | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
2519 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE
2520 | PTA_MWAITX | PTA_ADX | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT
2521 | PTA_XSAVEC | PTA_XSAVES | PTA_SHA;
2522constexpr wide_int_bitmask PTA_ZNVER2 = PTA_ZNVER1 | PTA_CLWB | PTA_RDPID
2523 | PTA_WBNOINVD;
2524constexpr wide_int_bitmask PTA_ZNVER3 = PTA_ZNVER2 | PTA_VAES | PTA_VPCLMULQDQ
2525 | PTA_PKU;
2526constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ
2527 | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
2528 | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
2529 | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ;
2530constexpr wide_int_bitmask PTA_ZNVER5 = PTA_ZNVER4 | PTA_AVXVNNI
2531 | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_PREFETCHI;
2532constexpr wide_int_bitmask PTA_ZNVER6 = PTA_ZNVER5 | PTA_AVXVNNIINT8
2533 | PTA_AVXNECONVERT | PTA_AVX512BMM | PTA_AVXIFMA | PTA_AVX512FP16;
2534
2535constexpr wide_int_bitmask PTA_BTVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
2536 | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A | PTA_LZCNT | PTA_POPCNT
2537 | PTA_ABM | PTA_CX16 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE;
2538constexpr wide_int_bitmask PTA_BTVER2 = PTA_BTVER1 | PTA_SSE4_1 | PTA_SSE4_2
2539 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_BMI | PTA_F16C | PTA_MOVBE
2540 | PTA_XSAVEOPT;
2541
2542constexpr wide_int_bitmask PTA_LUJIAZUI = PTA_64BIT | PTA_MMX | PTA_SSE
2543 | PTA_SSE2 | PTA_SSE3 | PTA_CX16 | PTA_LZCNT | PTA_POPCNT | PTA_ABM
2544 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_BMI
2545 | PTA_BMI2 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
2546 | PTA_RDRND | PTA_MOVBE | PTA_ADX | PTA_RDSEED;
2547constexpr wide_int_bitmask PTA_YONGFENG = PTA_LUJIAZUI | PTA_AVX | PTA_AVX2
2548 | PTA_F16C | PTA_FMA | PTA_SHA;
2549
2550#ifndef GENERATOR_FILE
2551
2552#include "insn-attr-common.h"
2553
2554#include "common/config/i386/i386-cpuinfo.h"
2555
2556class pta
2557{
2558public:
2559 const char *const name; /* processor name or nickname. */
2560 const enum processor_type processor;
2561 const enum attr_cpu schedule;
2562 const wide_int_bitmask flags;
2563 const int model;
2564 const enum feature_priority priority;
2565};
2566
2567extern const pta processor_alias_table[];
2568extern unsigned int const pta_size;
2569extern unsigned int const num_arch_names;
2570#endif
2571
2572#endif
2573
2574extern enum processor_type ix86_tune;
2575extern enum processor_type ix86_arch;
2576
2577/* Size of the RED_ZONE area. */
2578#define RED_ZONE_SIZE 128
2579/* Reserved area of the red zone for temporaries. */
2580#define RED_ZONE_RESERVE 8
2581
2582extern unsigned int ix86_preferred_stack_boundary;
2583extern unsigned int ix86_incoming_stack_boundary;
2584
2585/* Smallest class containing REGNO. */
2586extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2587
2588enum ix86_fpcmp_strategy {
2589 IX86_FPCMP_SAHF,
2590 IX86_FPCMP_COMI,
2591 IX86_FPCMP_ARITH
2592};
2593
2594/* To properly truncate FP values into integers, we need to set i387 control
2595 word. We can't emit proper mode switching code before reload, as spills
2596 generated by reload may truncate values incorrectly, but we still can avoid
2597 redundant computation of new control word by the mode switching pass.
2598 The fldcw instructions are still emitted redundantly, but this is probably
2599 not going to be noticeable problem, as most CPUs do have fast path for
2600 the sequence.
2601
2602 The machinery is to emit simple truncation instructions and split them
2603 before reload to instructions having USEs of two memory locations that
2604 are filled by this code to old and new control word.
2605
2606 Post-reload pass may be later used to eliminate the redundant fildcw if
2607 needed. */
2608
2609enum ix86_stack_slot
2610{
2611 SLOT_CW_STORED = 0,
2612 SLOT_CW_ROUNDEVEN,
2613 SLOT_CW_TRUNC,
2614 SLOT_CW_FLOOR,
2615 SLOT_CW_CEIL,
2616 SLOT_STV_TEMP,
2617 SLOT_FLOATxFDI_387,
2618 MAX_386_STACK_LOCALS
2619};
2620
2621enum ix86_entity
2622{
2623 X86_DIRFLAG = 0,
2624 AVX_U128,
2625 I387_ROUNDEVEN,
2626 I387_TRUNC,
2627 I387_FLOOR,
2628 I387_CEIL,
2629 MAX_386_ENTITIES
2630};
2631
2632enum x86_dirflag_state
2633{
2634 X86_DIRFLAG_RESET,
2635 X86_DIRFLAG_ANY
2636};
2637
2638enum avx_u128_state
2639{
2640 AVX_U128_CLEAN,
2641 AVX_U128_DIRTY,
2642 AVX_U128_ANY
2643};
2644
2645/* Define this macro if the port needs extra instructions inserted
2646 for mode switching in an optimizing compilation. */
2647
2648#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2649 ix86_optimize_mode_switching[(ENTITY)]
2650
2651/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2652 initializer for an array of integers. Each initializer element N
2653 refers to an entity that needs mode switching, and specifies the
2654 number of different modes that might need to be set for this
2655 entity. The position of the initializer in the initializer -
2656 starting counting at zero - determines the integer that is used to
2657 refer to the mode-switched entity in question. */
2658
2659#define NUM_MODES_FOR_MODE_SWITCHING \
2660 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2661 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2662
2663
2664/* Avoid renaming of stack registers, as doing so in combination with
2665 scheduling just increases amount of live registers at time and in
2666 the turn amount of fxch instructions needed.
2667
2668 ??? Maybe Pentium chips benefits from renaming, someone can try....
2669
2670 Don't rename evex to non-evex sse registers. */
2671
2672#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2673 (!STACK_REGNO_P (SRC) \
2674 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET))
2675
2676
2677#define FASTCALL_PREFIX '@'
2678
2679#ifndef USED_FOR_TARGET
2680/* Structure describing stack frame layout.
2681 Stack grows downward:
2682
2683 [arguments]
2684 <- ARG_POINTER
2685 saved pc
2686
2687 saved static chain if ix86_static_chain_on_stack
2688
2689 saved frame pointer if frame_pointer_needed
2690 <- HARD_FRAME_POINTER
2691 [saved regs]
2692 <- reg_save_offset
2693 [padding0]
2694 <- stack_realign_offset
2695 [saved SSE regs]
2696 OR
2697 [stub-saved registers for ms x64 --> sysv clobbers
2698 <- Start of out-of-line, stub-saved/restored regs
2699 (see libgcc/config/i386/(sav|res)ms64*.S)
2700 [XMM6-15]
2701 [RSI]
2702 [RDI]
2703 [?RBX] only if RBX is clobbered
2704 [?RBP] only if RBP and RBX are clobbered
2705 [?R12] only if R12 and all previous regs are clobbered
2706 [?R13] only if R13 and all previous regs are clobbered
2707 [?R14] only if R14 and all previous regs are clobbered
2708 [?R15] only if R15 and all previous regs are clobbered
2709 <- end of stub-saved/restored regs
2710 [padding1]
2711 ]
2712 <- sse_reg_save_offset
2713 [padding2]
2714 | <- FRAME_POINTER
2715 [va_arg registers] |
2716 |
2717 [frame] |
2718 |
2719 [padding2] | = to_allocate
2720 <- STACK_POINTER
2721 */
2722struct GTY(()) ix86_frame
2723{
2724 int nsseregs;
2725 int nregs;
2726 int va_arg_size;
2727 int red_zone_size;
2728 int outgoing_arguments_size;
2729
2730 /* The offsets relative to ARG_POINTER. */
2731 HOST_WIDE_INT frame_pointer_offset;
2732 HOST_WIDE_INT hard_frame_pointer_offset;
2733 HOST_WIDE_INT stack_pointer_offset;
2734 HOST_WIDE_INT hfp_save_offset;
2735 HOST_WIDE_INT reg_save_offset;
2736 HOST_WIDE_INT stack_realign_allocate;
2737 HOST_WIDE_INT stack_realign_offset;
2738 HOST_WIDE_INT sse_reg_save_offset;
2739
2740 /* When save_regs_using_mov is set, emit prologue using
2741 move instead of push instructions. */
2742 bool save_regs_using_mov;
2743
2744 /* Assume without checking that:
2745 EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */
2746 bool expensive_p;
2747 int expensive_count;
2748};
2749
2750/* Machine specific frame tracking during prologue/epilogue generation. All
2751 values are positive, but since the x86 stack grows downward, are subtratced
2752 from the CFA to produce a valid address. */
2753
2754struct GTY(()) machine_frame_state
2755{
2756 /* This pair tracks the currently active CFA as reg+offset. When reg
2757 is drap_reg, we don't bother trying to record here the real CFA when
2758 it might really be a DW_CFA_def_cfa_expression. */
2759 rtx cfa_reg;
2760 HOST_WIDE_INT cfa_offset;
2761
2762 /* The current offset (canonically from the CFA) of ESP and EBP.
2763 When stack frame re-alignment is active, these may not be relative
2764 to the CFA. However, in all cases they are relative to the offsets
2765 of the saved registers stored in ix86_frame. */
2766 HOST_WIDE_INT sp_offset;
2767 HOST_WIDE_INT fp_offset;
2768
2769 /* The size of the red-zone that may be assumed for the purposes of
2770 eliding register restore notes in the epilogue. This may be zero
2771 if no red-zone is in effect, or may be reduced from the real
2772 red-zone value by a maximum runtime stack re-alignment value. */
2773 int red_zone_offset;
2774
2775 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2776 value within the frame. If false then the offset above should be
2777 ignored. Note that DRAP, if valid, *always* points to the CFA and
2778 thus has an offset of zero. */
2779 BOOL_BITFIELD sp_valid : 1;
2780 BOOL_BITFIELD fp_valid : 1;
2781 BOOL_BITFIELD drap_valid : 1;
2782
2783 /* Indicate whether the local stack frame has been re-aligned. When
2784 set, the SP/FP offsets above are relative to the aligned frame
2785 and not the CFA. */
2786 BOOL_BITFIELD realigned : 1;
2787
2788 /* Indicates whether the stack pointer has been re-aligned. When set,
2789 SP/FP continue to be relative to the CFA, but the stack pointer
2790 should only be used for offsets > sp_realigned_offset, while
2791 the frame pointer should be used for offsets <= sp_realigned_fp_last.
2792 The flags realigned and sp_realigned are mutually exclusive. */
2793 BOOL_BITFIELD sp_realigned : 1;
2794
2795 /* When APX_PPX used in prologue, force epilogue to emit
2796 popp instead of move and leave. */
2797 BOOL_BITFIELD apx_ppx_used : 1;
2798
2799 /* If sp_realigned is set, this is the last valid offset from the CFA
2800 that can be used for access with the frame pointer. */
2801 HOST_WIDE_INT sp_realigned_fp_last;
2802
2803 /* If sp_realigned is set, this is the offset from the CFA that the stack
2804 pointer was realigned, and may or may not be equal to sp_realigned_fp_last.
2805 Access via the stack pointer is only valid for offsets that are greater than
2806 this value. */
2807 HOST_WIDE_INT sp_realigned_offset;
2808};
2809
2810/* Private to winnt.cc. */
2811struct seh_frame_state;
2812
2813enum function_type
2814{
2815 TYPE_UNKNOWN = 0,
2816 TYPE_NORMAL,
2817 /* The current function is an interrupt service routine with a
2818 pointer argument as specified by the "interrupt" attribute. */
2819 TYPE_INTERRUPT,
2820 /* The current function is an interrupt service routine with a
2821 pointer argument and an integer argument as specified by the
2822 "interrupt" attribute. */
2823 TYPE_EXCEPTION
2824};
2825
2826enum call_saved_registers_type
2827{
2828 TYPE_DEFAULT_CALL_SAVED_REGISTERS = 0,
2829 /* The current function is a function specified with the "interrupt"
2830 or "no_caller_saved_registers" attribute. */
2831 TYPE_NO_CALLER_SAVED_REGISTERS,
2832 /* The current function is a function specified with the
2833 "no_callee_saved_registers" attribute or a function specified with
2834 the "noreturn" attribute when compiled with
2835 "-mnoreturn-no-callee-saved-registers". */
2836 TYPE_NO_CALLEE_SAVED_REGISTERS,
2837 /* The current function is a function specified with the
2838 "preserve_none" attribute. */
2839 TYPE_PRESERVE_NONE,
2840};
2841
2842enum queued_insn_type
2843{
2844 TYPE_NONE = 0,
2845 TYPE_ENDBR,
2846 TYPE_PATCHABLE_AREA
2847};
2848
2849struct GTY(()) machine_function {
2850 struct stack_local_entry *stack_locals;
2851 int varargs_gpr_size;
2852 int varargs_fpr_size;
2853 int optimize_mode_switching[MAX_386_ENTITIES];
2854
2855 /* Cached initial frame layout for the current function. */
2856 struct ix86_frame frame;
2857
2858 /* The components already handled by separate shrink-wrapping, which should
2859 not be considered by the prologue and epilogue. */
2860 bool reg_is_wrapped_separately[FIRST_PSEUDO_REGISTER];
2861
2862 /* For -fsplit-stack support: A stack local which holds a pointer to
2863 the stack arguments for a function with a variable number of
2864 arguments. This is set at the start of the function and is used
2865 to initialize the overflow_arg_area field of the va_list
2866 structure. */
2867 rtx split_stack_varargs_pointer;
2868
2869 /* This value is used for amd64 targets and specifies the current abi
2870 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2871 ENUM_BITFIELD(calling_abi) call_abi : 8;
2872
2873 /* Nonzero if the function accesses a previous frame. */
2874 BOOL_BITFIELD accesses_prev_frame : 1;
2875
2876 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2877 expander to determine the style used. */
2878 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2879
2880 /* Nonzero if the current function calls pc thunk and
2881 must not use the red zone. */
2882 BOOL_BITFIELD pc_thunk_call_expanded : 1;
2883
2884 /* If true, the current function needs the default PIC register, not
2885 an alternate register (on x86) and must not use the red zone (on
2886 x86_64), even if it's a leaf function. We don't want the
2887 function to be regarded as non-leaf because TLS calls need not
2888 affect register allocation. This flag is set when a TLS call
2889 instruction is expanded within a function, and never reset, even
2890 if all such instructions are optimized away. Use the
2891 ix86_current_function_calls_tls_descriptor macro for a better
2892 approximation. */
2893 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2894
2895 /* True if TLS descriptor is called more than once. */
2896 BOOL_BITFIELD tls_descriptor_call_multiple_p : 1;
2897
2898 /* If true, the current function has a STATIC_CHAIN is placed on the
2899 stack below the return address. */
2900 BOOL_BITFIELD static_chain_on_stack : 1;
2901
2902 /* If true, it is safe to not save/restore DRAP register. */
2903 BOOL_BITFIELD no_drap_save_restore : 1;
2904
2905 /* Function type. */
2906 ENUM_BITFIELD(function_type) func_type : 2;
2907
2908 /* How to generate indirec branch. */
2909 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3;
2910
2911 /* If true, the current function has local indirect jumps, like
2912 "indirect_jump" or "tablejump". */
2913 BOOL_BITFIELD has_local_indirect_jump : 1;
2914
2915 /* How to generate function return. */
2916 ENUM_BITFIELD(indirect_branch) function_return_type : 3;
2917
2918 /* Call saved registers type. */
2919 ENUM_BITFIELD(call_saved_registers_type) call_saved_registers : 3;
2920
2921 /* If true, there is register available for argument passing. This
2922 is used only in ix86_function_ok_for_sibcall by 32-bit to determine
2923 if there is scratch register available for indirect sibcall. In
2924 64-bit, rax, r10 and r11 are scratch registers which aren't used to
2925 pass arguments and can be used for indirect sibcall. */
2926 BOOL_BITFIELD arg_reg_available : 1;
2927
2928 /* If true, we're out-of-lining reg save/restore for regs clobbered
2929 by 64-bit ms_abi functions calling a sysv_abi function. */
2930 BOOL_BITFIELD call_ms2sysv : 1;
2931
2932 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and
2933 needs padding prior to out-of-line stub save/restore area. */
2934 BOOL_BITFIELD call_ms2sysv_pad_in : 1;
2935
2936 /* This is the number of extra registers saved by stub (valid range is
2937 0-6). Each additional register is only saved/restored by the stubs
2938 if all successive ones are. (Will always be zero when using a hard
2939 frame pointer.) */
2940 unsigned int call_ms2sysv_extra_regs:3;
2941
2942 /* Nonzero if the function places outgoing arguments on stack. */
2943 BOOL_BITFIELD outgoing_args_on_stack : 1;
2944
2945 /* If true, ENDBR or patchable area is queued at function entrance. */
2946 ENUM_BITFIELD(queued_insn_type) insn_queued_at_entrance : 2;
2947
2948 /* If true, the function label has been emitted. */
2949 BOOL_BITFIELD function_label_emitted : 1;
2950
2951 /* True if the function needs a stack frame. */
2952 BOOL_BITFIELD stack_frame_required : 1;
2953
2954 /* True if we should act silently, rather than raise an error for
2955 invalid calls. */
2956 BOOL_BITFIELD silent_p : 1;
2957
2958 /* True if red zone is used. */
2959 BOOL_BITFIELD red_zone_used : 1;
2960
2961 /* True if inline asm with redzone clobber has been seen. */
2962 BOOL_BITFIELD asm_redzone_clobber_seen : 1;
2963
2964 /* True if this is a recursive function. */
2965 BOOL_BITFIELD recursive_function : 1;
2966
2967 /* True if by_pieces op is currently in use. */
2968 BOOL_BITFIELD by_pieces_in_use : 1;
2969
2970 /* The largest alignment, in bytes, of stack slot actually used. */
2971 unsigned int max_used_stack_alignment;
2972
2973 /* During prologue/epilogue generation, the current frame state.
2974 Otherwise, the frame state at the end of the prologue. */
2975 struct machine_frame_state fs;
2976
2977 /* During SEH output, this is non-null. */
2978 struct seh_frame_state * GTY((skip(""))) seh;
2979};
2980
2981extern GTY(()) tree sysv_va_list_type_node;
2982extern GTY(()) tree ms_va_list_type_node;
2983#endif
2984
2985#define ix86_stack_locals (cfun->machine->stack_locals)
2986#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2987#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2988#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2989#define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded)
2990#define ix86_tls_descriptor_calls_expanded_in_cfun \
2991 (cfun->machine->tls_descriptor_call_expanded_p)
2992/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2993 calls are optimized away, we try to detect cases in which it was
2994 optimized away. Since such instructions (use (reg REG_SP)), we can
2995 verify whether there's any such instruction live by testing that
2996 REG_SP is live. */
2997#define ix86_current_function_calls_tls_descriptor \
2998 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2999#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
3000#define ix86_red_zone_used (cfun->machine->red_zone_used)
3001
3002/* Control behavior of x86_file_start. */
3003#define X86_FILE_START_VERSION_DIRECTIVE false
3004#define X86_FILE_START_FLTUSED false
3005
3006/* Flag to mark data that is in the large address area. */
3007#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
3008#define SYMBOL_REF_FAR_ADDR_P(X) \
3009 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
3010
3011/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
3012 have defined always, to avoid ifdefing. */
3013#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
3014#define SYMBOL_REF_DLLIMPORT_P(X) \
3015 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
3016
3017#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
3018#define SYMBOL_REF_DLLEXPORT_P(X) \
3019 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
3020
3021#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
3022#define SYMBOL_REF_STUBVAR_P(X) \
3023 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
3024
3025extern void debug_ready_dispatch (void);
3026extern void debug_dispatch_window (int);
3027
3028/* The value at zero is only defined for the BMI instructions
3029 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
3030#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
3031 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 2 : 0)
3032#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
3033 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 2 : 0)
3034
3035
3036/* Flags returned by ix86_get_callcvt (). */
3037#define IX86_CALLCVT_CDECL 0x1
3038#define IX86_CALLCVT_STDCALL 0x2
3039#define IX86_CALLCVT_FASTCALL 0x4
3040#define IX86_CALLCVT_THISCALL 0x8
3041#define IX86_CALLCVT_REGPARM 0x10
3042#define IX86_CALLCVT_SSEREGPARM 0x20
3043
3044#define IX86_BASE_CALLCVT(FLAGS) \
3045 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
3046 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
3047
3048#define RECIP_MASK_NONE 0x00
3049#define RECIP_MASK_DIV 0x01
3050#define RECIP_MASK_SQRT 0x02
3051#define RECIP_MASK_VEC_DIV 0x04
3052#define RECIP_MASK_VEC_SQRT 0x08
3053#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
3054 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
3055#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
3056
3057#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
3058#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
3059#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
3060#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
3061
3062/* Use 128-bit AVX instructions in the auto-vectorizer. */
3063#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
3064/* Use 256-bit AVX instructions in the auto-vectorizer. */
3065#define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
3066 || prefer_vector_width_type == PVW_AVX256)
3067
3068#define TARGET_INDIRECT_BRANCH_REGISTER \
3069 (ix86_indirect_branch_register \
3070 || cfun->machine->indirect_branch_type != indirect_branch_keep)
3071
3072#define IX86_HLE_ACQUIRE (1 << 16)
3073#define IX86_HLE_RELEASE (1 << 17)
3074
3075/* For switching between functions with different target attributes. */
3076#define SWITCHABLE_TARGET 1
3077
3078#define TARGET_SUPPORTS_WIDE_INT 1
3079
3080#if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2)
3081extern enum attr_cpu ix86_schedule;
3082
3083#define NUM_X86_64_MS_CLOBBERED_REGS 12
3084#endif
3085
3086/* __builtin_eh_return can't handle stack realignment, so disable MMX/SSE
3087 in 32-bit libgcc functions that call it. */
3088#ifndef __x86_64__
3089#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((target ("no-mmx,no-sse")))
3090#endif
3091
3092/*
3093Local variables:
3094version-control: t
3095End:
3096*/
3097

source code of gcc/config/i386/i386.h