1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16Under Section 7 of GPL version 3, you are granted additional
17permissions described in the GCC Runtime Library Exception, version
183.1, as published by the Free Software Foundation.
19
20You should have received a copy of the GNU General Public License and
21a copy of the GCC Runtime Library Exception along with this program;
22see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23<http://www.gnu.org/licenses/>. */
24
25/* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
27
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
30
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
33
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
39
40/* Redefines for option macros. */
41
42#define TARGET_CMPXCHG16B TARGET_CX16
43#define TARGET_CMPXCHG16B_P(x) TARGET_CX16_P(x)
44
45#define TARGET_LP64 TARGET_ABI_64
46#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
47#define TARGET_X32 TARGET_ABI_X32
48#define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
49#define TARGET_16BIT TARGET_CODE16
50#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
51
52#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
53
54#define TARGET_APX_EGPR (ix86_apx_features & apx_egpr)
55#define TARGET_APX_PUSH2POP2 (ix86_apx_features & apx_push2pop2)
56#define TARGET_APX_NDD (ix86_apx_features & apx_ndd)
57#define TARGET_APX_PPX (ix86_apx_features & apx_ppx)
58
59#include "config/vxworks-dummy.h"
60
61#include "config/i386/i386-opts.h"
62
63#define MAX_STRINGOP_ALGS 4
64
65/* Specify what algorithm to use for stringops on known size.
66 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
67 known at compile time or estimated via feedback, the SIZE array
68 is walked in order until MAX is greater then the estimate (or -1
69 means infinity). Corresponding ALG is used then.
70 When NOALIGN is true the code guaranting the alignment of the memory
71 block is skipped.
72
73 For example initializer:
74 {{256, loop}, {-1, rep_prefix_4_byte}}
75 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
76 be used otherwise. */
77struct stringop_algs
78{
79 const enum stringop_alg unknown_size;
80 const struct stringop_strategy {
81 /* Several older compilers delete the default constructor because of the
82 const entries (see PR100246). Manually specifying a CTOR works around
83 this issue. Since this header is used by code compiled with the C
84 compiler we must guard the addition. */
85#ifdef __cplusplus
86 constexpr
87 stringop_strategy (int _max = -1, enum stringop_alg _alg = libcall,
88 int _noalign = false)
89 : max (_max), alg (_alg), noalign (_noalign) {}
90#endif
91 const int max;
92 const enum stringop_alg alg;
93 int noalign;
94 } size [MAX_STRINGOP_ALGS];
95};
96
97/* Analog of COSTS_N_INSNS when optimizing for size. */
98#ifndef COSTS_N_BYTES
99#define COSTS_N_BYTES(N) ((N) * 2)
100#endif
101
102/* Define the specific costs for a given cpu. NB: hard_register is used
103 by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute
104 hard register move costs by register allocator. Relative costs of
105 pseudo register load and store versus pseudo register moves in RTL
106 expressions for TARGET_RTX_COSTS can be different from relative
107 costs of hard registers to get the most efficient operations with
108 pseudo registers. */
109
110struct processor_costs {
111 /* Costs used by register allocator. integer->integer register move
112 cost is 2. */
113 struct
114 {
115 const int movzbl_load; /* cost of loading using movzbl */
116 const int int_load[3]; /* cost of loading integer registers
117 in QImode, HImode and SImode relative
118 to reg-reg move (2). */
119 const int int_store[3]; /* cost of storing integer register
120 in QImode, HImode and SImode */
121 const int fp_move; /* cost of reg,reg fld/fst */
122 const int fp_load[3]; /* cost of loading FP register
123 in SFmode, DFmode and XFmode */
124 const int fp_store[3]; /* cost of storing FP register
125 in SFmode, DFmode and XFmode */
126 const int mmx_move; /* cost of moving MMX register. */
127 const int mmx_load[2]; /* cost of loading MMX register
128 in SImode and DImode */
129 const int mmx_store[2]; /* cost of storing MMX register
130 in SImode and DImode */
131 const int xmm_move; /* cost of moving XMM register. */
132 const int ymm_move; /* cost of moving XMM register. */
133 const int zmm_move; /* cost of moving XMM register. */
134 const int sse_load[5]; /* cost of loading SSE register
135 in 32bit, 64bit, 128bit, 256bit and 512bit */
136 const int sse_store[5]; /* cost of storing SSE register
137 in SImode, DImode and TImode. */
138 const int sse_to_integer; /* cost of moving SSE register to integer. */
139 const int integer_to_sse; /* cost of moving integer register to SSE. */
140 const int mask_to_integer; /* cost of moving mask register to integer. */
141 const int integer_to_mask; /* cost of moving integer register to mask. */
142 const int mask_load[3]; /* cost of loading mask registers
143 in QImode, HImode and SImode. */
144 const int mask_store[3]; /* cost of storing mask register
145 in QImode, HImode and SImode. */
146 const int mask_move; /* cost of moving mask register. */
147 } hard_register;
148
149 const int add; /* cost of an add instruction */
150 const int lea; /* cost of a lea instruction */
151 const int shift_var; /* variable shift costs */
152 const int shift_const; /* constant shift costs */
153 const int mult_init[5]; /* cost of starting a multiply
154 in QImode, HImode, SImode, DImode, TImode*/
155 const int mult_bit; /* cost of multiply per each bit set */
156 const int divide[5]; /* cost of a divide/mod
157 in QImode, HImode, SImode, DImode, TImode*/
158 int movsx; /* The cost of movsx operation. */
159 int movzx; /* The cost of movzx operation. */
160 const int large_insn; /* insns larger than this cost more */
161 const int move_ratio; /* The threshold of number of scalar
162 memory-to-memory move insns. */
163 const int clear_ratio; /* The threshold of number of scalar
164 memory clearing insns. */
165 const int int_load[3]; /* cost of loading integer registers
166 in QImode, HImode and SImode relative
167 to reg-reg move (2). */
168 const int int_store[3]; /* cost of storing integer register
169 in QImode, HImode and SImode */
170 const int sse_load[5]; /* cost of loading SSE register
171 in 32bit, 64bit, 128bit, 256bit and 512bit */
172 const int sse_store[5]; /* cost of storing SSE register
173 in 32bit, 64bit, 128bit, 256bit and 512bit */
174 const int sse_unaligned_load[5];/* cost of unaligned load. */
175 const int sse_unaligned_store[5];/* cost of unaligned store. */
176 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */
177 zmm_move;
178 const int sse_to_integer; /* cost of moving SSE register to integer. */
179 const int gather_static, gather_per_elt; /* Cost of gather load is computed
180 as static + per_item * nelts. */
181 const int scatter_static, scatter_per_elt; /* Cost of gather store is
182 computed as static + per_item * nelts. */
183 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
184 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
185 const int prefetch_block; /* bytes moved to cache for prefetch. */
186 const int simultaneous_prefetches; /* number of parallel prefetch
187 operations. */
188 const int branch_cost; /* Default value for BRANCH_COST. */
189 const int fadd; /* cost of FADD and FSUB instructions. */
190 const int fmul; /* cost of FMUL instruction. */
191 const int fdiv; /* cost of FDIV instruction. */
192 const int fabs; /* cost of FABS instruction. */
193 const int fchs; /* cost of FCHS instruction. */
194 const int fsqrt; /* cost of FSQRT instruction. */
195 /* Specify what algorithm
196 to use for stringops on unknown size. */
197 const int sse_op; /* cost of cheap SSE instruction. */
198 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */
199 const int mulss; /* cost of MULSS instructions. */
200 const int mulsd; /* cost of MULSD instructions. */
201 const int fmass; /* cost of FMASS instructions. */
202 const int fmasd; /* cost of FMASD instructions. */
203 const int divss; /* cost of DIVSS instructions. */
204 const int divsd; /* cost of DIVSD instructions. */
205 const int sqrtss; /* cost of SQRTSS instructions. */
206 const int sqrtsd; /* cost of SQRTSD instructions. */
207 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp;
208 /* Specify reassociation width for integer,
209 fp, vector integer and vector fp
210 operations. Generally should correspond
211 to number of instructions executed in
212 parallel. See also
213 ix86_reassociation_width. */
214 struct stringop_algs *memcpy, *memset;
215 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
216 cost model. */
217 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
218 vectorizer cost model. */
219
220 /* The "0:0:8" label alignment specified for some processors generates
221 secondary 8-byte alignment only for those label/jump/loop targets
222 which have primary alignment. */
223 const char *const align_loop; /* Loop alignment. */
224 const char *const align_jump; /* Jump alignment. */
225 const char *const align_label; /* Label alignment. */
226 const char *const align_func; /* Function alignment. */
227
228 const unsigned small_unroll_ninsns; /* Insn count limit for small loop
229 to be unrolled. */
230 const unsigned small_unroll_factor; /* Unroll factor for small loop to
231 be unrolled. */
232};
233
234extern const struct processor_costs *ix86_cost;
235extern const struct processor_costs ix86_size_cost;
236
237#define ix86_cur_cost() \
238 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
239
240/* Macros used in the machine description to test the flags. */
241
242/* configure can arrange to change it. */
243
244#ifndef TARGET_CPU_DEFAULT
245#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
246#endif
247
248#ifndef TARGET_FPMATH_DEFAULT
249#define TARGET_FPMATH_DEFAULT \
250 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
251#endif
252
253#ifndef TARGET_FPMATH_DEFAULT_P
254#define TARGET_FPMATH_DEFAULT_P(x) \
255 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
256#endif
257
258/* If the i387 is disabled or -miamcu is used , then do not return
259 values in it. */
260#define TARGET_FLOAT_RETURNS_IN_80387 \
261 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
262#define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
263 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
264
265/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
266 compile-time constant. */
267#ifdef IN_LIBGCC2
268#undef TARGET_64BIT
269#ifdef __x86_64__
270#define TARGET_64BIT 1
271#else
272#define TARGET_64BIT 0
273#endif
274#else
275#ifndef TARGET_BI_ARCH
276#undef TARGET_64BIT
277#undef TARGET_64BIT_P
278#if TARGET_64BIT_DEFAULT
279#define TARGET_64BIT 1
280#define TARGET_64BIT_P(x) 1
281#else
282#define TARGET_64BIT 0
283#define TARGET_64BIT_P(x) 0
284#endif
285#endif
286#endif
287
288#define HAS_LONG_COND_BRANCH 1
289#define HAS_LONG_UNCOND_BRANCH 1
290
291#define TARGET_CPU_P(CPU) (ix86_tune == PROCESSOR_ ## CPU)
292
293/* Feature tests against the various tunings. */
294enum ix86_tune_indices {
295#undef DEF_TUNE
296#define DEF_TUNE(tune, name, selector) tune,
297#include "x86-tune.def"
298#undef DEF_TUNE
299X86_TUNE_LAST
300};
301
302extern unsigned char ix86_tune_features[X86_TUNE_LAST];
303
304#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
305#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
306#define TARGET_ZERO_EXTEND_WITH_AND \
307 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
308#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
309#define TARGET_BRANCH_PREDICTION_HINTS \
310 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
311#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
312#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
313#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
314#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
315#define TARGET_PARTIAL_MEMORY_READ_STALL \
316 ix86_tune_features[X86_TUNE_PARTIAL_MEMORY_READ_STALL]
317#define TARGET_PARTIAL_FLAG_REG_STALL \
318 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
319#define TARGET_LCP_STALL \
320 ix86_tune_features[X86_TUNE_LCP_STALL]
321#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
322#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
323#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
324#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
325#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
326#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
327#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
328#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
329#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
330#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
331#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
332#define TARGET_PREFER_KNOWN_REP_MOVSB_STOSB \
333 ix86_tune_features[X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB]
334#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
335 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
336#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
337#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
338#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
339#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
340#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
341#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
342#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
343#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
344#define TARGET_INTEGER_DFMODE_MOVES \
345 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
346#define TARGET_PARTIAL_REG_DEPENDENCY \
347 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
348#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
349 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
350#define TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY \
351 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY]
352#define TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY \
353 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY]
354#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
355 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
356#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
357 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
358#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
359 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
360#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
361#define TARGET_SSE_TYPELESS_STORES \
362 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
363#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
364#define TARGET_MEMORY_MISMATCH_STALL \
365 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
366#define TARGET_PROLOGUE_USING_MOVE \
367 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
368#define TARGET_EPILOGUE_USING_MOVE \
369 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
370#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
371#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
372#define TARGET_INTER_UNIT_MOVES_TO_VEC \
373 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
374#define TARGET_INTER_UNIT_MOVES_FROM_VEC \
375 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
376#define TARGET_INTER_UNIT_CONVERSIONS \
377 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
378#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
379#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
380#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
381#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
382#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
383#define TARGET_PAD_SHORT_FUNCTION \
384 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
385#define TARGET_EXT_80387_CONSTANTS \
386 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
387#define TARGET_AVOID_VECTOR_DECODE \
388 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
389#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
390 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
391#define TARGET_SLOW_IMUL_IMM32_MEM \
392 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
393#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
394#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
395#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
396#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
397#define TARGET_USE_VECTOR_FP_CONVERTS \
398 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
399#define TARGET_USE_VECTOR_CONVERTS \
400 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
401#define TARGET_SLOW_PSHUFB \
402 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
403#define TARGET_AVOID_4BYTE_PREFIXES \
404 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
405#define TARGET_USE_GATHER_2PARTS \
406 ix86_tune_features[X86_TUNE_USE_GATHER_2PARTS]
407#define TARGET_USE_SCATTER_2PARTS \
408 ix86_tune_features[X86_TUNE_USE_SCATTER_2PARTS]
409#define TARGET_USE_GATHER_4PARTS \
410 ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS]
411#define TARGET_USE_SCATTER_4PARTS \
412 ix86_tune_features[X86_TUNE_USE_SCATTER_4PARTS]
413#define TARGET_USE_GATHER_8PARTS \
414 ix86_tune_features[X86_TUNE_USE_GATHER_8PARTS]
415#define TARGET_USE_SCATTER_8PARTS \
416 ix86_tune_features[X86_TUNE_USE_SCATTER_8PARTS]
417#define TARGET_FUSE_CMP_AND_BRANCH_32 \
418 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
419#define TARGET_FUSE_CMP_AND_BRANCH_64 \
420 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
421#define TARGET_FUSE_CMP_AND_BRANCH \
422 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
423 : TARGET_FUSE_CMP_AND_BRANCH_32)
424#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
425 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
426#define TARGET_FUSE_ALU_AND_BRANCH \
427 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
428#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
429#define TARGET_AVOID_LEA_FOR_ADDR \
430 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
431#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
432 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
433#define TARGET_AVX256_SPLIT_REGS \
434 ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS]
435#define TARGET_AVX512_SPLIT_REGS \
436 ix86_tune_features[X86_TUNE_AVX512_SPLIT_REGS]
437#define TARGET_GENERAL_REGS_SSE_SPILL \
438 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
439#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
440 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
441#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
442 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
443#define TARGET_ADJUST_UNROLL \
444 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
445#define TARGET_AVOID_FALSE_DEP_FOR_BMI \
446 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
447#define TARGET_ONE_IF_CONV_INSN \
448 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
449#define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE]
450#define TARGET_EMIT_VZEROUPPER \
451 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
452#define TARGET_EXPAND_ABS \
453 ix86_tune_features[X86_TUNE_EXPAND_ABS]
454#define TARGET_V2DF_REDUCTION_PREFER_HADDPD \
455 ix86_tune_features[X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD]
456#define TARGET_DEST_FALSE_DEP_FOR_GLC \
457 ix86_tune_features[X86_TUNE_DEST_FALSE_DEP_FOR_GLC]
458#define TARGET_SLOW_STC ix86_tune_features[X86_TUNE_SLOW_STC]
459#define TARGET_USE_RCR ix86_tune_features[X86_TUNE_USE_RCR]
460
461/* Feature tests against the various architecture variations. */
462enum ix86_arch_indices {
463 X86_ARCH_CMOV,
464 X86_ARCH_CMPXCHG,
465 X86_ARCH_CMPXCHG8B,
466 X86_ARCH_XADD,
467 X86_ARCH_BSWAP,
468
469 X86_ARCH_LAST
470};
471
472extern unsigned char ix86_arch_features[X86_ARCH_LAST];
473
474#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
475#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
476#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
477#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
478#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
479
480/* For sane SSE instruction set generation we need fcomi instruction.
481 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
482 expands to a sequence that includes conditional move. */
483#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
484
485#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
486
487extern unsigned char ix86_prefetch_sse;
488#define TARGET_PREFETCH_SSE ix86_prefetch_sse
489
490#define ASSEMBLER_DIALECT (ix86_asm_dialect)
491
492#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
493#define TARGET_MIX_SSE_I387 \
494 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
495
496#define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
497#define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE)
498#define TARGET_HARD_XF_REGS (TARGET_80387)
499
500#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
501#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
502#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
503#define TARGET_SUN_TLS 0
504
505#ifndef TARGET_64BIT_DEFAULT
506#define TARGET_64BIT_DEFAULT 0
507#endif
508#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
509#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
510#endif
511
512#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
513#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
514
515/* Fence to use after loop using storent. */
516
517extern GTY(()) tree x86_mfence;
518#define FENCE_FOLLOWING_MOVNT x86_mfence
519
520/* Once GDB has been enhanced to deal with functions without frame
521 pointers, we can change this to allow for elimination of
522 the frame pointer in leaf functions. */
523#define TARGET_DEFAULT 0
524
525/* Extra bits to force. */
526#define TARGET_SUBTARGET_DEFAULT 0
527#define TARGET_SUBTARGET_ISA_DEFAULT 0
528
529/* Extra bits to force on w/ 32-bit mode. */
530#define TARGET_SUBTARGET32_DEFAULT 0
531#define TARGET_SUBTARGET32_ISA_DEFAULT 0
532
533/* Extra bits to force on w/ 64-bit mode. */
534#define TARGET_SUBTARGET64_DEFAULT 0
535/* Enable MMX, SSE and SSE2 by default. */
536#define TARGET_SUBTARGET64_ISA_DEFAULT \
537 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
538
539/* Replace MACH-O, ifdefs by in-line tests, where possible.
540 (a) Macros defined in config/i386/darwin.h */
541#define TARGET_MACHO 0
542#define TARGET_MACHO_SYMBOL_STUBS 0
543#define MACHOPIC_ATT_STUB 0
544/* (b) Macros defined in config/darwin.h */
545#define MACHO_DYNAMIC_NO_PIC_P 0
546#define MACHOPIC_INDIRECT 0
547#define MACHOPIC_PURE 0
548
549/* For the RDOS */
550#define TARGET_RDOS 0
551
552/* For the Windows 64-bit ABI. */
553#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
554
555/* For the Windows 32-bit ABI. */
556#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
557
558/* This is re-defined by cygming.h. */
559#define TARGET_SEH 0
560
561/* The default abi used by target. */
562#define DEFAULT_ABI SYSV_ABI
563
564/* The default TLS segment register used by target. */
565#define DEFAULT_TLS_SEG_REG \
566 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS)
567
568/* Subtargets may reset this to 1 in order to enable 96-bit long double
569 with the rounding mode forced to 53 bits. */
570#define TARGET_96_ROUND_53_LONG_DOUBLE 0
571
572#ifndef SUBTARGET_DRIVER_SELF_SPECS
573# define SUBTARGET_DRIVER_SELF_SPECS ""
574#endif
575
576#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS
577
578/* -march=native handling only makes sense with compiler running on
579 an x86 or x86_64 chip. If changing this condition, also change
580 the condition in driver-i386.cc. */
581#if defined(__i386__) || defined(__x86_64__)
582/* In driver-i386.cc. */
583extern const char *host_detect_local_cpu (int argc, const char **argv);
584#define EXTRA_SPEC_FUNCTIONS \
585 { "local_cpu_detect", host_detect_local_cpu },
586#define HAVE_LOCAL_CPU_DETECT
587#endif
588
589#if TARGET_64BIT_DEFAULT
590#define OPT_ARCH64 "!m32"
591#define OPT_ARCH32 "m32"
592#else
593#define OPT_ARCH64 "m64|mx32"
594#define OPT_ARCH32 "m64|mx32:;"
595#endif
596
597/* Support for configure-time defaults of some command line options.
598 The order here is important so that -march doesn't squash the
599 tune or cpu values. */
600#define OPTION_DEFAULT_SPECS \
601 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
602 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
603 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
604 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
605 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
606 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
607 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
608 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
609 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
610
611/* Specs for the compiler proper */
612
613#ifndef CC1_CPU_SPEC
614#define CC1_CPU_SPEC_1 ""
615
616#ifndef HAVE_LOCAL_CPU_DETECT
617#define CC1_CPU_SPEC CC1_CPU_SPEC_1
618#else
619#define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}"
620#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
621"%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \
622 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \
623%{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}"
624#endif
625#endif
626
627/* Target CPU builtins. */
628#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
629
630/* Target Pragmas. */
631#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
632
633#ifndef CC1_SPEC
634#define CC1_SPEC "%(cc1_cpu) "
635#endif
636
637/* This macro defines names of additional specifications to put in the
638 specs that can be used in various specifications like CC1_SPEC. Its
639 definition is an initializer with a subgrouping for each command option.
640
641 Each subgrouping contains a string constant, that defines the
642 specification name, and a string constant that used by the GCC driver
643 program.
644
645 Do not define this macro if it does not need to do anything. */
646
647#ifndef SUBTARGET_EXTRA_SPECS
648#define SUBTARGET_EXTRA_SPECS
649#endif
650
651#define EXTRA_SPECS \
652 { "cc1_cpu", CC1_CPU_SPEC }, \
653 SUBTARGET_EXTRA_SPECS
654
655
656/* Whether to allow x87 floating-point arithmetic on MODE (one of
657 SFmode, DFmode and XFmode) in the current excess precision
658 configuration. */
659#define X87_ENABLE_ARITH(MODE) \
660 (ix86_unsafe_math_optimizations \
661 || ix86_excess_precision == EXCESS_PRECISION_FAST \
662 || (MODE) == XFmode)
663
664/* Likewise, whether to allow direct conversions from integer mode
665 IMODE (HImode, SImode or DImode) to MODE. */
666#define X87_ENABLE_FLOAT(MODE, IMODE) \
667 (ix86_unsafe_math_optimizations \
668 || ix86_excess_precision == EXCESS_PRECISION_FAST \
669 || (MODE) == XFmode \
670 || ((MODE) == DFmode && (IMODE) == SImode) \
671 || (IMODE) == HImode)
672
673/* target machine storage layout */
674
675#define SHORT_TYPE_SIZE 16
676#define INT_TYPE_SIZE 32
677#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
678#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
679#define LONG_LONG_TYPE_SIZE 64
680#define FLOAT_TYPE_SIZE 32
681#define DOUBLE_TYPE_SIZE 64
682#define LONG_DOUBLE_TYPE_SIZE \
683 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))
684
685#define WIDEST_HARDWARE_FP_SIZE 80
686
687#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
688#define MAX_BITS_PER_WORD 64
689#else
690#define MAX_BITS_PER_WORD 32
691#endif
692
693/* Define this if most significant byte of a word is the lowest numbered. */
694/* That is true on the 80386. */
695
696#define BITS_BIG_ENDIAN 0
697
698/* Define this if most significant byte of a word is the lowest numbered. */
699/* That is not true on the 80386. */
700#define BYTES_BIG_ENDIAN 0
701
702/* Define this if most significant word of a multiword number is the lowest
703 numbered. */
704/* Not true for 80386 */
705#define WORDS_BIG_ENDIAN 0
706
707/* Width of a word, in units (bytes). */
708#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
709
710#ifndef IN_LIBGCC2
711#define MIN_UNITS_PER_WORD 4
712#endif
713
714/* Allocation boundary (in *bits*) for storing arguments in argument list. */
715#define PARM_BOUNDARY BITS_PER_WORD
716
717/* Boundary (in *bits*) on which stack pointer should be aligned. */
718#define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD)
719
720/* Stack boundary of the main function guaranteed by OS. */
721#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
722
723/* Minimum stack boundary. */
724#define MIN_STACK_BOUNDARY BITS_PER_WORD
725
726/* Boundary (in *bits*) on which the stack pointer prefers to be
727 aligned; the compiler cannot rely on having this alignment. */
728#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
729
730/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
731 both 32bit and 64bit, to support codes that need 128 bit stack
732 alignment for SSE instructions, but can't realign the stack. */
733#define PREFERRED_STACK_BOUNDARY_DEFAULT \
734 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
735
736/* 1 if -mstackrealign should be turned on by default. It will
737 generate an alternate prologue and epilogue that realigns the
738 runtime stack if nessary. This supports mixing codes that keep a
739 4-byte aligned stack, as specified by i386 psABI, with codes that
740 need a 16-byte aligned stack, as required by SSE instructions. */
741#define STACK_REALIGN_DEFAULT 0
742
743/* Boundary (in *bits*) on which the incoming stack is aligned. */
744#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
745
746/* According to Windows x64 software convention, the maximum stack allocatable
747 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
748 instructions allowed to adjust the stack pointer in the epilog, forcing the
749 use of frame pointer for frames larger than 2 GB. This theorical limit
750 is reduced by 256, an over-estimated upper bound for the stack use by the
751 prologue.
752 We define only one threshold for both the prolog and the epilog. When the
753 frame size is larger than this threshold, we allocate the area to save SSE
754 regs, then save them, and then allocate the remaining. There is no SEH
755 unwind info for this later allocation. */
756#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
757
758/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
759 mandatory for the 64-bit ABI, and may or may not be true for other
760 operating systems. */
761#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
762
763/* Minimum allocation boundary for the code of a function. */
764#define FUNCTION_BOUNDARY 8
765
766/* We will and with this value to test if a custom function descriptor needs
767 a static chain. The function boundary must the adjusted so that the bit
768 this represents is no longer part of the address. 0 Disables the custom
769 function descriptors. */
770#define X86_CUSTOM_FUNCTION_TEST 1
771
772/* C++ stores the virtual bit in the lowest bit of function pointers. */
773#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
774
775/* Minimum size in bits of the largest boundary to which any
776 and all fundamental data types supported by the hardware
777 might need to be aligned. No data type wants to be aligned
778 rounder than this.
779
780 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
781 and Pentium Pro XFmode values at 128 bit boundaries.
782
783 When increasing the maximum, also update
784 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
785
786#define BIGGEST_ALIGNMENT \
787 (TARGET_IAMCU ? 32 : ((TARGET_AVX512F && TARGET_EVEX512) \
788 ? 512 : (TARGET_AVX ? 256 : 128)))
789
790/* Maximum stack alignment. */
791#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
792
793/* Alignment value for attribute ((aligned)). It is a constant since
794 it is the part of the ABI. We shouldn't change it with -mavx. */
795#define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
796
797/* Decide whether a variable of mode MODE should be 128 bit aligned. */
798#define ALIGN_MODE_128(MODE) \
799 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
800
801/* The published ABIs say that doubles should be aligned on word
802 boundaries, so lower the alignment for structure fields unless
803 -malign-double is set. */
804
805/* ??? Blah -- this macro is used directly by libobjc. Since it
806 supports no vector modes, cut out the complexity and fall back
807 on BIGGEST_FIELD_ALIGNMENT. */
808#ifdef IN_TARGET_LIBS
809#ifdef __x86_64__
810#define BIGGEST_FIELD_ALIGNMENT 128
811#else
812#define BIGGEST_FIELD_ALIGNMENT 32
813#endif
814#else
815#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
816 x86_field_alignment ((TYPE), (COMPUTED))
817#endif
818
819/* If defined, a C expression to compute the alignment for a static
820 variable. TYPE is the data type, and ALIGN is the alignment that
821 the object would ordinarily have. The value of this macro is used
822 instead of that alignment to align the object.
823
824 If this macro is not defined, then ALIGN is used.
825
826 One use of this macro is to increase alignment of medium-size
827 data to make it all fit in fewer cache lines. Another is to
828 cause character arrays to be word-aligned so that `strcpy' calls
829 that copy constants to character arrays can be done inline. */
830
831#define DATA_ALIGNMENT(TYPE, ALIGN) \
832 ix86_data_alignment ((TYPE), (ALIGN), true)
833
834/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
835 some alignment increase, instead of optimization only purposes. E.g.
836 AMD x86-64 psABI says that variables with array type larger than 15 bytes
837 must be aligned to 16 byte boundaries.
838
839 If this macro is not defined, then ALIGN is used. */
840
841#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
842 ix86_data_alignment ((TYPE), (ALIGN), false)
843
844/* If defined, a C expression to compute the alignment for a local
845 variable. TYPE is the data type, and ALIGN is the alignment that
846 the object would ordinarily have. The value of this macro is used
847 instead of that alignment to align the object.
848
849 If this macro is not defined, then ALIGN is used.
850
851 One use of this macro is to increase alignment of medium-size
852 data to make it all fit in fewer cache lines. */
853
854#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
855 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
856
857/* If defined, a C expression to compute the alignment for stack slot.
858 TYPE is the data type, MODE is the widest mode available, and ALIGN
859 is the alignment that the slot would ordinarily have. The value of
860 this macro is used instead of that alignment to align the slot.
861
862 If this macro is not defined, then ALIGN is used when TYPE is NULL,
863 Otherwise, LOCAL_ALIGNMENT will be used.
864
865 One use of this macro is to set alignment of stack slot to the
866 maximum alignment of all possible modes which the slot may have. */
867
868#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
869 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
870
871/* If defined, a C expression to compute the alignment for a local
872 variable DECL.
873
874 If this macro is not defined, then
875 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
876
877 One use of this macro is to increase alignment of medium-size
878 data to make it all fit in fewer cache lines. */
879
880#define LOCAL_DECL_ALIGNMENT(DECL) \
881 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
882
883/* If defined, a C expression to compute the minimum required alignment
884 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
885 MODE, assuming normal alignment ALIGN.
886
887 If this macro is not defined, then (ALIGN) will be used. */
888
889#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
890 ix86_minimum_alignment ((EXP), (MODE), (ALIGN))
891
892
893/* Set this nonzero if move instructions will actually fail to work
894 when given unaligned data. */
895#define STRICT_ALIGNMENT 0
896
897/* If bit field type is int, don't let it cross an int,
898 and give entire struct the alignment of an int. */
899/* Required on the 386 since it doesn't have bit-field insns. */
900#define PCC_BITFIELD_TYPE_MATTERS 1
901
902/* Standard register usage. */
903
904/* This processor has special stack-like registers. See reg-stack.cc
905 for details. */
906
907#define STACK_REGS
908
909#define IS_STACK_MODE(MODE) \
910 (X87_FLOAT_MODE_P (MODE) \
911 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
912 || TARGET_MIX_SSE_I387))
913
914/* Number of actual hardware registers.
915 The hardware registers are assigned numbers for the compiler
916 from 0 to just below FIRST_PSEUDO_REGISTER.
917 All registers that the compiler knows about must be given numbers,
918 even those that are not normally considered general registers.
919
920 In the 80386 we give the 8 general purpose registers the numbers 0-7.
921 We number the floating point registers 8-15.
922 Note that registers 0-7 can be accessed as a short or int,
923 while only 0-3 may be used with byte `mov' instructions.
924
925 Reg 16 does not correspond to any hardware register, but instead
926 appears in the RTL as an argument pointer prior to reload, and is
927 eliminated during reloading in favor of either the stack or frame
928 pointer. */
929
930#define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
931
932/* Number of hardware registers that go into the DWARF-2 unwind info.
933 If not defined, equals FIRST_PSEUDO_REGISTER. */
934
935#define DWARF_FRAME_REGISTERS 17
936
937/* 1 for registers that have pervasive standard uses
938 and are not available for the register allocator.
939 On the 80386, the stack pointer is such, as is the arg pointer.
940
941 REX registers are disabled for 32bit targets in
942 TARGET_CONDITIONAL_REGISTER_USAGE. */
943
944#define FIXED_REGISTERS \
945/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
946{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
947/*arg,flags,fpsr,frame*/ \
948 1, 1, 1, 1, \
949/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
950 0, 0, 0, 0, 0, 0, 0, 0, \
951/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
952 0, 0, 0, 0, 0, 0, 0, 0, \
953/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
954 0, 0, 0, 0, 0, 0, 0, 0, \
955/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
956 0, 0, 0, 0, 0, 0, 0, 0, \
957/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
958 0, 0, 0, 0, 0, 0, 0, 0, \
959/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
960 0, 0, 0, 0, 0, 0, 0, 0, \
961/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
962 0, 0, 0, 0, 0, 0, 0, 0, \
963/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
964 0, 0, 0, 0, 0, 0, 0, 0, \
965/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
966 0, 0, 0, 0, 0, 0, 0, 0} \
967
968/* 1 for registers not available across function calls.
969 These must include the FIXED_REGISTERS and also any
970 registers that can be used without being saved.
971 The latter must include the registers where values are returned
972 and the register where structure-value addresses are passed.
973 Aside from that, you can include as many other registers as you like.
974
975 Value is set to 1 if the register is call used unconditionally.
976 Bit one is set if the register is call used on TARGET_32BIT ABI.
977 Bit two is set if the register is call used on TARGET_64BIT ABI.
978 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
979
980 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
981
982#define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \
983 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
984
985#define CALL_USED_REGISTERS \
986/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
987{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
988/*arg,flags,fpsr,frame*/ \
989 1, 1, 1, 1, \
990/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
991 1, 1, 1, 1, 1, 1, 6, 6, \
992/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
993 1, 1, 1, 1, 1, 1, 1, 1, \
994/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
995 1, 1, 1, 1, 2, 2, 2, 2, \
996/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
997 6, 6, 6, 6, 6, 6, 6, 6, \
998/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
999 1, 1, 1, 1, 1, 1, 1, 1, \
1000/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1001 1, 1, 1, 1, 1, 1, 1, 1, \
1002 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1003 1, 1, 1, 1, 1, 1, 1, 1, \
1004/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
1005 1, 1, 1, 1, 1, 1, 1, 1, \
1006/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
1007 1, 1, 1, 1, 1, 1, 1, 1} \
1008
1009/* Order in which to allocate registers. Each register must be
1010 listed once, even those in FIXED_REGISTERS. List frame pointer
1011 late and fixed registers last. Note that, in general, we prefer
1012 registers listed in CALL_USED_REGISTERS, keeping the others
1013 available for storage of persistent values.
1014
1015 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
1016 so this is just empty initializer for array. */
1017
1018#define REG_ALLOC_ORDER \
1019{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1020 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1021 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1022 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1023 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1024 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91}
1025
1026/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1027 to be rearranged based on a particular function. When using sse math,
1028 we want to allocate SSE before x87 registers and vice versa. */
1029
1030#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1031
1032#define INSN_BASE_REG_CLASS(INSN) \
1033 ix86_insn_base_reg_class (INSN)
1034
1035#define REGNO_OK_FOR_INSN_BASE_P(NUM, INSN) \
1036 ix86_regno_ok_for_insn_base_p (NUM, INSN)
1037
1038#define INSN_INDEX_REG_CLASS(INSN) \
1039 ix86_insn_index_reg_class (INSN)
1040
1041#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1042
1043#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1044 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \
1045 && GENERAL_REGNO_P (REGNO) \
1046 && ((MODE) == XFmode || (MODE) == XCmode))
1047
1048#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1049
1050#define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE)
1051
1052#define VALID_AVX256_REG_MODE(MODE) \
1053 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1054 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1055 || (MODE) == V4DFmode || (MODE) == V16HFmode || (MODE) == V16BFmode)
1056
1057#define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1058 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1059
1060#define VALID_AVX512F_SCALAR_MODE(MODE) \
1061 ((MODE) == DImode || (MODE) == DFmode \
1062 || (MODE) == SImode || (MODE) == SFmode \
1063 || (MODE) == HImode || (MODE) == HFmode || (MODE) == BFmode)
1064
1065#define VALID_AVX512F_REG_MODE(MODE) \
1066 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1067 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1068 || (MODE) == V4TImode || (MODE) == V32HFmode || (MODE) == V32BFmode)
1069
1070#define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1071 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1072
1073#define VALID_AVX512VL_128_REG_MODE(MODE) \
1074 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1075 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1076 || (MODE) == TFmode || (MODE) == V1TImode || (MODE) == V8HFmode \
1077 || (MODE) == V8BFmode || (MODE) == TImode)
1078
1079#define VALID_AVX512FP16_REG_MODE(MODE) \
1080 ((MODE) == V8HFmode || (MODE) == V16HFmode || (MODE) == V32HFmode)
1081
1082#define VALID_SSE2_TYPE_MODE(MODE) \
1083 ((MODE) == HFmode || (MODE) == BFmode \
1084 || (MODE) == HCmode || (MODE) == BCmode)
1085
1086#define VALID_SSE2_REG_MODE(MODE) \
1087 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1088 || (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \
1089 || (MODE) == V8BFmode || (MODE) == V4BFmode || (MODE) == V2BFmode \
1090 || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
1091 || (MODE) == V2DImode || (MODE) == V2QImode \
1092 || (MODE) == DFmode || (MODE) == DImode \
1093 || (MODE) == HFmode || (MODE) == BFmode)
1094
1095#define VALID_SSE_REG_MODE(MODE) \
1096 ((MODE) == V1TImode || (MODE) == TImode \
1097 || (MODE) == V4SFmode || (MODE) == V4SImode \
1098 || (MODE) == SFmode || (MODE) == SImode \
1099 || (MODE) == TFmode || (MODE) == TDmode)
1100
1101#define VALID_MMX_REG_MODE_3DNOW(MODE) \
1102 ((MODE) == V2SFmode || (MODE) == SFmode)
1103
1104/* To match ia32 psABI, V4HFmode should be added here. */
1105#define VALID_MMX_REG_MODE(MODE) \
1106 ((MODE) == V1DImode || (MODE) == DImode \
1107 || (MODE) == V2SImode || (MODE) == SImode \
1108 || (MODE) == V4HImode || (MODE) == V8QImode \
1109 || (MODE) == V4HFmode || (MODE) == V4BFmode)
1110
1111#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1112
1113#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1114
1115#define VALID_FP_MODE_P(MODE) \
1116 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1117 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)
1118
1119#define VALID_INT_MODE_P(MODE) \
1120 ((MODE) == QImode || (MODE) == HImode \
1121 || (MODE) == SImode || (MODE) == DImode \
1122 || (MODE) == CQImode || (MODE) == CHImode \
1123 || (MODE) == CSImode || (MODE) == CDImode \
1124 || (MODE) == SDmode || (MODE) == DDmode \
1125 || (MODE) == HFmode || (MODE) == HCmode || (MODE) == BFmode \
1126 || (MODE) == V2HImode || (MODE) == V2HFmode || (MODE) == V2BFmode \
1127 || (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \
1128 || (TARGET_64BIT \
1129 && ((MODE) == TImode || (MODE) == CTImode \
1130 || (MODE) == TFmode || (MODE) == TCmode \
1131 || (MODE) == V8QImode || (MODE) == V4HImode \
1132 || (MODE) == V2SImode || (MODE) == TDmode)))
1133
1134/* Return true for modes passed in SSE registers. */
1135#define SSE_REG_MODE_P(MODE) \
1136 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1137 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1138 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1139 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1140 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1141 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1142 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1143 || (MODE) == V16SFmode \
1144 || (MODE) == V32HFmode || (MODE) == V16HFmode || (MODE) == V8HFmode \
1145 || (MODE) == V32BFmode || (MODE) == V16BFmode || (MODE) == V8BFmode)
1146
1147#define X87_FLOAT_MODE_P(MODE) \
1148 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1149
1150#define SSE_FLOAT_MODE_P(MODE) \
1151 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1152
1153#define SSE_FLOAT_MODE_SSEMATH_OR_HF_P(MODE) \
1154 ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
1155 || (TARGET_AVX512FP16 && (MODE) == HFmode))
1156
1157#define FMA4_VEC_FLOAT_MODE_P(MODE) \
1158 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1159 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1160
1161#define VALID_BCST_MODE_P(MODE) \
1162 ((MODE) == SFmode || (MODE) == DFmode \
1163 || (MODE) == SImode || (MODE) == DImode \
1164 || (MODE) == HFmode)
1165
1166/* It is possible to write patterns to move flags; but until someone
1167 does it, */
1168#define AVOID_CCMODE_COPIES
1169
1170/* Specify the modes required to caller save a given hard regno.
1171 We do this on i386 to prevent flags from being saved at all.
1172
1173 Kill any attempts to combine saving of modes. */
1174
1175#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1176 (CC_REGNO_P (REGNO) ? VOIDmode \
1177 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1178 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \
1179 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \
1180 && TARGET_PARTIAL_REG_STALL) \
1181 || MASK_REGNO_P (REGNO)) ? SImode \
1182 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \
1183 || MASK_REGNO_P (REGNO)) ? SImode \
1184 : (MODE))
1185
1186/* Specify the registers used for certain standard purposes.
1187 The values of these macros are register numbers. */
1188
1189/* on the 386 the pc register is %eip, and is not usable as a general
1190 register. The ordinary mov instructions won't work */
1191/* #define PC_REGNUM */
1192
1193/* Base register for access to arguments of the function. */
1194#define ARG_POINTER_REGNUM ARGP_REG
1195
1196/* Register to use for pushing function arguments. */
1197#define STACK_POINTER_REGNUM SP_REG
1198
1199/* Base register for access to local variables of the function. */
1200#define FRAME_POINTER_REGNUM FRAME_REG
1201#define HARD_FRAME_POINTER_REGNUM BP_REG
1202
1203#define FIRST_INT_REG AX_REG
1204#define LAST_INT_REG SP_REG
1205
1206#define FIRST_INDEX_REG AX_REG
1207#define LAST_INDEX_REG BP_REG
1208
1209#define FIRST_QI_REG AX_REG
1210#define LAST_QI_REG BX_REG
1211
1212/* First & last stack-like regs */
1213#define FIRST_STACK_REG ST0_REG
1214#define LAST_STACK_REG ST7_REG
1215
1216#define FIRST_SSE_REG XMM0_REG
1217#define LAST_SSE_REG XMM7_REG
1218
1219#define FIRST_MMX_REG MM0_REG
1220#define LAST_MMX_REG MM7_REG
1221
1222#define FIRST_REX_INT_REG R8_REG
1223#define LAST_REX_INT_REG R15_REG
1224
1225#define FIRST_REX_SSE_REG XMM8_REG
1226#define LAST_REX_SSE_REG XMM15_REG
1227
1228#define FIRST_EXT_REX_SSE_REG XMM16_REG
1229#define LAST_EXT_REX_SSE_REG XMM31_REG
1230
1231#define FIRST_MASK_REG MASK0_REG
1232#define LAST_MASK_REG MASK7_REG
1233
1234#define FIRST_REX2_INT_REG R16_REG
1235#define LAST_REX2_INT_REG R31_REG
1236
1237/* Override this in other tm.h files to cope with various OS lossage
1238 requiring a frame pointer. */
1239#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1240#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1241#endif
1242
1243/* Define the shadow offset for asan. Other OS's can override in the
1244 respective tm.h files. */
1245#ifndef SUBTARGET_SHADOW_OFFSET
1246#define SUBTARGET_SHADOW_OFFSET \
1247 (TARGET_LP64 ? HOST_WIDE_INT_C (0x7fff8000) : HOST_WIDE_INT_1 << 29)
1248#endif
1249
1250/* Make sure we can access arbitrary call frames. */
1251#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1252
1253/* Register to hold the addressing base for position independent
1254 code access to data items. We don't use PIC pointer for 64bit
1255 mode. Define the regnum to dummy value to prevent gcc from
1256 pessimizing code dealing with EBX.
1257
1258 To avoid clobbering a call-saved register unnecessarily, we renumber
1259 the pic register when possible. The change is visible after the
1260 prologue has been emitted. */
1261
1262#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
1263
1264#define PIC_OFFSET_TABLE_REGNUM \
1265 (ix86_use_pseudo_pic_reg () \
1266 ? (pic_offset_table_rtx \
1267 ? INVALID_REGNUM \
1268 : REAL_PIC_OFFSET_TABLE_REGNUM) \
1269 : INVALID_REGNUM)
1270
1271#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1272
1273/* This is overridden by <cygwin.h>. */
1274#define MS_AGGREGATE_RETURN 0
1275
1276#define KEEP_AGGREGATE_RETURN_POINTER 0
1277
1278/* Define the classes of registers for register constraints in the
1279 machine description. Also define ranges of constants.
1280
1281 One of the classes must always be named ALL_REGS and include all hard regs.
1282 If there is more than one class, another class must be named NO_REGS
1283 and contain no registers.
1284
1285 The name GENERAL_REGS must be the name of a class (or an alias for
1286 another name such as ALL_REGS). This is the class of registers
1287 that is allowed by "g" or "r" in a register constraint.
1288 Also, registers outside this class are allocated only when
1289 instructions express preferences for them.
1290
1291 The classes must be numbered in nondecreasing order; that is,
1292 a larger-numbered class must never be contained completely
1293 in a smaller-numbered class. This is why CLOBBERED_REGS class
1294 is listed early, even though in 64-bit mode it contains more
1295 registers than just %eax, %ecx, %edx.
1296
1297 For any two classes, it is very desirable that there be another
1298 class that represents their union.
1299
1300 The flags and fpsr registers are in no class. */
1301
1302enum reg_class
1303{
1304 NO_REGS,
1305 AREG, DREG, CREG, BREG, SIREG, DIREG,
1306 AD_REGS, /* %eax/%edx for DImode */
1307 CLOBBERED_REGS, /* call-clobbered integer registers */
1308 Q_REGS, /* %eax %ebx %ecx %edx */
1309 NON_Q_REGS, /* %esi %edi %ebp %esp */
1310 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */
1311 LEGACY_GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1312 LEGACY_INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1313 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1314 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
1315 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
1316 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
1317 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp
1318 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
1319 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
1320 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
1321 GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1322 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1323 INDEX_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp
1324 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1325 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1326 FLOAT_REGS,
1327 SSE_FIRST_REG,
1328 NO_REX_SSE_REGS,
1329 SSE_REGS,
1330 ALL_SSE_REGS,
1331 MMX_REGS,
1332 FLOAT_SSE_REGS,
1333 FLOAT_INT_REGS,
1334 INT_SSE_REGS,
1335 FLOAT_INT_SSE_REGS,
1336 MASK_REGS,
1337 ALL_MASK_REGS,
1338 INT_MASK_REGS,
1339 ALL_REGS,
1340 LIM_REG_CLASSES
1341};
1342
1343#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1344
1345#define INTEGER_CLASS_P(CLASS) \
1346 reg_class_subset_p ((CLASS), GENERAL_REGS)
1347#define FLOAT_CLASS_P(CLASS) \
1348 reg_class_subset_p ((CLASS), FLOAT_REGS)
1349#define SSE_CLASS_P(CLASS) \
1350 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1351#define INT_SSE_CLASS_P(CLASS) \
1352 reg_class_subset_p ((CLASS), INT_SSE_REGS)
1353#define MMX_CLASS_P(CLASS) \
1354 ((CLASS) == MMX_REGS)
1355#define MASK_CLASS_P(CLASS) \
1356 reg_class_subset_p ((CLASS), ALL_MASK_REGS)
1357#define MAYBE_INTEGER_CLASS_P(CLASS) \
1358 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1359#define MAYBE_FLOAT_CLASS_P(CLASS) \
1360 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1361#define MAYBE_SSE_CLASS_P(CLASS) \
1362 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1363#define MAYBE_MMX_CLASS_P(CLASS) \
1364 reg_classes_intersect_p ((CLASS), MMX_REGS)
1365#define MAYBE_MASK_CLASS_P(CLASS) \
1366 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS)
1367
1368#define Q_CLASS_P(CLASS) \
1369 reg_class_subset_p ((CLASS), Q_REGS)
1370
1371#define MAYBE_NON_Q_CLASS_P(CLASS) \
1372 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1373
1374/* Give names of register classes as strings for dump file. */
1375
1376#define REG_CLASS_NAMES \
1377{ "NO_REGS", \
1378 "AREG", "DREG", "CREG", "BREG", \
1379 "SIREG", "DIREG", \
1380 "AD_REGS", \
1381 "CLOBBERED_REGS", \
1382 "Q_REGS", "NON_Q_REGS", \
1383 "TLS_GOTBASE_REGS", \
1384 "LEGACY_GENERAL_REGS", \
1385 "LEGACY_INDEX_REGS", \
1386 "GENERAL_REGS", \
1387 "INDEX_REGS", \
1388 "GENERAL_GPR16", \
1389 "INDEX_GPR16", \
1390 "FP_TOP_REG", "FP_SECOND_REG", \
1391 "FLOAT_REGS", \
1392 "SSE_FIRST_REG", \
1393 "NO_REX_SSE_REGS", \
1394 "SSE_REGS", \
1395 "ALL_SSE_REGS", \
1396 "MMX_REGS", \
1397 "FLOAT_SSE_REGS", \
1398 "FLOAT_INT_REGS", \
1399 "INT_SSE_REGS", \
1400 "FLOAT_INT_SSE_REGS", \
1401 "MASK_REGS", \
1402 "ALL_MASK_REGS", \
1403 "INT_MASK_REGS", \
1404 "ALL_REGS" }
1405
1406/* Define which registers fit in which classes. This is an initializer
1407 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1408
1409 Note that CLOBBERED_REGS are calculated by
1410 TARGET_CONDITIONAL_REGISTER_USAGE. */
1411
1412#define REG_CLASS_CONTENTS \
1413{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
1414 { 0x01, 0x0, 0x0 }, /* AREG */ \
1415 { 0x02, 0x0, 0x0 }, /* DREG */ \
1416 { 0x04, 0x0, 0x0 }, /* CREG */ \
1417 { 0x08, 0x0, 0x0 }, /* BREG */ \
1418 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1419 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1420 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1421 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1422 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1423 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
1424 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1425 { 0x900ff, 0x0, 0x0 }, /* LEGACY_GENERAL_REGS */ \
1426 { 0x7f, 0x0, 0x0 }, /* LEGACY_INDEX_REGS */ \
1427 { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \
1428 { 0x7f, 0xff0, 0xffff000 }, /* INDEX_REGS */ \
1429 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \
1430 { 0x7f, 0xff0, 0x0 }, /* INDEX_GPR16 */ \
1431 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1432 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1433 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1434 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1435 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
1436 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
1437 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
1438{ 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
1439 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
1440 { 0x9ffff, 0xff0, 0xffff000 }, /* FLOAT_INT_REGS */ \
1441 { 0xff900ff, 0xfffffff0, 0xffff00f }, /* INT_SSE_REGS */ \
1442 { 0xff9ffff, 0xfffffff0, 0xffff00f }, /* FLOAT_INT_SSE_REGS */ \
1443 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
1444 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
1445 { 0x900ff, 0xff0, 0xffffff0 }, /* INT_MASK_REGS */ \
1446{ 0xffffffff, 0xffffffff, 0xfffffff } /* ALL_REGS */ \
1447}
1448
1449/* The same information, inverted:
1450 Return the class number of the smallest class containing
1451 reg number REGNO. This could be a conditional expression
1452 or could index an array. */
1453
1454#define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)])
1455
1456/* When this hook returns true for MODE, the compiler allows
1457 registers explicitly used in the rtl to be used as spill registers
1458 but prevents the compiler from extending the lifetime of these
1459 registers. */
1460#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1461
1462#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1463#define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
1464
1465#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
1466#define LEGACY_INT_REGNO_P(N) IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)
1467
1468#define LEGACY_INDEX_REG_P(X) (REG_P (X) && LEGACY_INDEX_REGNO_P (REGNO (X)))
1469#define LEGACY_INDEX_REGNO_P(N) \
1470 IN_RANGE ((N), FIRST_INDEX_REG, LAST_INDEX_REG)
1471
1472#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1473#define REX_INT_REGNO_P(N) \
1474 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1475
1476#define REX2_INT_REG_P(X) (REG_P (X) && REX2_INT_REGNO_P (REGNO (X)))
1477#define REX2_INT_REGNO_P(N) \
1478 IN_RANGE ((N), FIRST_REX2_INT_REG, LAST_REX2_INT_REG)
1479
1480#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1481#define GENERAL_REGNO_P(N) \
1482 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
1483
1484#define INDEX_REG_P(X) (REG_P (X) && INDEX_REGNO_P (REGNO (X)))
1485#define INDEX_REGNO_P(N) \
1486 (LEGACY_INDEX_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N))
1487
1488#define GENERAL_GPR16_REGNO_P(N) \
1489 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
1490
1491#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1492#define ANY_QI_REGNO_P(N) \
1493 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1494
1495#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1496#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1497
1498#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1499#define SSE_REGNO_P(N) \
1500 (LEGACY_SSE_REGNO_P (N) \
1501 || REX_SSE_REGNO_P (N) \
1502 || EXT_REX_SSE_REGNO_P (N))
1503
1504#define LEGACY_SSE_REGNO_P(N) \
1505 IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG)
1506
1507#define REX_SSE_REGNO_P(N) \
1508 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1509
1510#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
1511
1512#define EXT_REX_SSE_REGNO_P(N) \
1513 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1514
1515#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1516#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1517
1518#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1519#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1520#define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0)
1521
1522#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1523#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1524
1525#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1526#define CC_REGNO_P(X) ((X) == FLAGS_REG)
1527
1528#define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1529#define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1530 || (N) == XMM4_REG \
1531 || (N) == XMM8_REG \
1532 || (N) == XMM12_REG \
1533 || (N) == XMM16_REG \
1534 || (N) == XMM20_REG \
1535 || (N) == XMM24_REG \
1536 || (N) == XMM28_REG)
1537
1538/* First floating point reg */
1539#define FIRST_FLOAT_REG FIRST_STACK_REG
1540#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1541
1542#define GET_SSE_REGNO(N) \
1543 ((N) < 8 ? FIRST_SSE_REG + (N) \
1544 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \
1545 : FIRST_EXT_REX_SSE_REG + (N) - 16)
1546
1547/* The class value for index registers, and the one for base regs. */
1548
1549#define INDEX_REG_CLASS INDEX_REGS
1550#define BASE_REG_CLASS GENERAL_REGS
1551
1552/* Stack layout; function entry, exit and calling. */
1553
1554/* Define this if pushing a word on the stack
1555 makes the stack pointer a smaller address. */
1556#define STACK_GROWS_DOWNWARD 1
1557
1558/* Define this to nonzero if the nominal address of the stack frame
1559 is at the high-address end of the local variables;
1560 that is, each additional local variable allocated
1561 goes at a more negative offset in the frame. */
1562#define FRAME_GROWS_DOWNWARD 1
1563
1564#define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES)
1565
1566/* If defined, the maximum amount of space required for outgoing arguments
1567 will be computed and placed into the variable `crtl->outgoing_args_size'.
1568 No space will be pushed onto the stack for each call; instead, the
1569 function prologue should increase the stack frame size by this amount.
1570
1571 In 32bit mode enabling argument accumulation results in about 5% code size
1572 growth because move instructions are less compact than push. In 64bit
1573 mode the difference is less drastic but visible.
1574
1575 FIXME: Unlike earlier implementations, the size of unwind info seems to
1576 actually grow with accumulation. Is that because accumulated args
1577 unwind info became unnecesarily bloated?
1578
1579 With the 64-bit MS ABI, we can generate correct code with or without
1580 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
1581 generated without accumulated args is terrible.
1582
1583 If stack probes are required, the space used for large function
1584 arguments on the stack must also be probed, so enable
1585 -maccumulate-outgoing-args so this happens in the prologue.
1586
1587 We must use argument accumulation in interrupt function if stack
1588 may be realigned to avoid DRAP. */
1589
1590#define ACCUMULATE_OUTGOING_ARGS \
1591 ((TARGET_ACCUMULATE_OUTGOING_ARGS \
1592 && optimize_function_for_speed_p (cfun)) \
1593 || (cfun->machine->func_type != TYPE_NORMAL \
1594 && crtl->stack_realign_needed) \
1595 || TARGET_STACK_PROBE \
1596 || TARGET_64BIT_MS_ABI \
1597 || (TARGET_MACHO && crtl->profile))
1598
1599/* We want the stack and args grow in opposite directions, even if
1600 targetm.calls.push_argument returns false. */
1601#define PUSH_ARGS_REVERSED 1
1602
1603/* Offset of first parameter from the argument pointer register value. */
1604#define FIRST_PARM_OFFSET(FNDECL) 0
1605
1606/* Define this macro if functions should assume that stack space has been
1607 allocated for arguments even when their values are passed in registers.
1608
1609 The value of this macro is the size, in bytes, of the area reserved for
1610 arguments passed in registers for the function represented by FNDECL.
1611
1612 This space can be allocated by the caller, or be a part of the
1613 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1614 which. */
1615#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1616
1617#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1618 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1619
1620/* Define how to find the value returned by a library function
1621 assuming the value has mode MODE. */
1622
1623#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1624
1625/* Define the size of the result block used for communication between
1626 untyped_call and untyped_return. The block contains a DImode value
1627 followed by the block used by fnsave and frstor. */
1628
1629#define APPLY_RESULT_SIZE (8+108)
1630
1631/* 1 if N is a possible register number for function argument passing. */
1632#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1633
1634/* Define a data type for recording info about an argument list
1635 during the scan of that argument list. This data type should
1636 hold all necessary information about the function itself
1637 and about the args processed so far, enough to enable macros
1638 such as FUNCTION_ARG to determine where the next arg should go. */
1639
1640typedef struct ix86_args {
1641 int words; /* # words passed so far */
1642 int nregs; /* # registers available for passing */
1643 int regno; /* next available register number */
1644 int fastcall; /* fastcall or thiscall calling convention
1645 is used */
1646 int sse_words; /* # sse words passed so far */
1647 int sse_nregs; /* # sse registers available for passing */
1648 int warn_avx512f; /* True when we want to warn
1649 about AVX512F ABI. */
1650 int warn_avx; /* True when we want to warn about AVX ABI. */
1651 int warn_sse; /* True when we want to warn about SSE ABI. */
1652 int warn_mmx; /* True when we want to warn about MMX ABI. */
1653 int warn_empty; /* True when we want to warn about empty classes
1654 passing ABI change. */
1655 int sse_regno; /* next available sse register number */
1656 int mmx_words; /* # mmx words passed so far */
1657 int mmx_nregs; /* # mmx registers available for passing */
1658 int mmx_regno; /* next available mmx register number */
1659 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1660 int caller; /* true if it is caller. */
1661 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1662 SFmode/DFmode arguments should be passed
1663 in SSE registers. Otherwise 0. */
1664 int stdarg; /* Set to 1 if function is stdarg. */
1665 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1666 MS_ABI for ms abi. */
1667 tree decl; /* Callee decl. */
1668} CUMULATIVE_ARGS;
1669
1670/* Initialize a variable CUM of type CUMULATIVE_ARGS
1671 for a call to a function whose data type is FNTYPE.
1672 For a library call, FNTYPE is 0. */
1673
1674#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1675 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1676 (N_NAMED_ARGS) != -1)
1677
1678/* Output assembler code to FILE to increment profiler label # LABELNO
1679 for profiling a function entry. */
1680
1681#define FUNCTION_PROFILER(FILE, LABELNO) \
1682 x86_function_profiler ((FILE), (LABELNO))
1683
1684#define MCOUNT_NAME "_mcount"
1685
1686#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1687
1688#define PROFILE_COUNT_REGISTER "edx"
1689
1690/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1691 the stack pointer does not matter. The value is tested only in
1692 functions that have frame pointers.
1693 No definition is equivalent to always zero. */
1694/* Note on the 386 it might be more efficient not to define this since
1695 we have to restore it ourselves from the frame pointer, in order to
1696 use pop */
1697
1698#define EXIT_IGNORE_STACK 1
1699
1700/* Define this macro as a C expression that is nonzero for registers
1701 used by the epilogue or the `return' pattern. */
1702
1703#define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO)
1704
1705/* Output assembler code for a block containing the constant parts
1706 of a trampoline, leaving space for the variable parts. */
1707
1708/* On the 386, the trampoline contains two instructions:
1709 mov #STATIC,ecx
1710 jmp FUNCTION
1711 The trampoline is generated entirely at runtime. The operand of JMP
1712 is the address of FUNCTION relative to the instruction following the
1713 JMP (which is 5 bytes long). */
1714
1715/* Length in units of the trampoline for entering a nested function. */
1716
1717#define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14)
1718
1719/* Definitions for register eliminations.
1720
1721 This is an array of structures. Each structure initializes one pair
1722 of eliminable registers. The "from" register number is given first,
1723 followed by "to". Eliminations of the same "from" register are listed
1724 in order of preference.
1725
1726 There are two registers that can always be eliminated on the i386.
1727 The frame pointer and the arg pointer can be replaced by either the
1728 hard frame pointer or to the stack pointer, depending upon the
1729 circumstances. The hard frame pointer is not used before reload and
1730 so it is not eligible for elimination. */
1731
1732#define ELIMINABLE_REGS \
1733{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1734 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1735 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1736 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1737
1738/* Define the offset between two registers, one to be eliminated, and the other
1739 its replacement, at the start of a routine. */
1740
1741#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1742 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1743
1744/* Addressing modes, and classification of registers for them. */
1745
1746/* Macros to check register numbers against specific register classes. */
1747
1748/* These assume that REGNO is a hard or pseudo reg number.
1749 They give nonzero only if REGNO is a hard reg of the suitable class
1750 or a pseudo reg currently allocated to a suitable hard reg.
1751 Since they use reg_renumber, they are safe only once reg_renumber
1752 has been allocated, which happens in reginfo.cc during register
1753 allocation. */
1754
1755#define REGNO_OK_FOR_INDEX_P(REGNO) \
1756 (INDEX_REGNO_P (REGNO) \
1757 || INDEX_REGNO_P (reg_renumber[(REGNO)]))
1758
1759#define REGNO_OK_FOR_BASE_P(REGNO) \
1760 (GENERAL_REGNO_P (REGNO) \
1761 || (REGNO) == ARG_POINTER_REGNUM \
1762 || (REGNO) == FRAME_POINTER_REGNUM \
1763 || GENERAL_REGNO_P (reg_renumber[(REGNO)]))
1764
1765/* Non strict versions, pseudos are ok. */
1766#define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
1767 (INDEX_REGNO_P (REGNO) \
1768 || !HARD_REGISTER_NUM_P (REGNO))
1769
1770#define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
1771 (GENERAL_REGNO_P (REGNO) \
1772 || (REGNO) == ARG_POINTER_REGNUM \
1773 || (REGNO) == FRAME_POINTER_REGNUM \
1774 || !HARD_REGISTER_NUM_P (REGNO))
1775
1776/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1777 that is a valid memory address for an instruction.
1778 The MODE argument is the machine mode for the MEM expression
1779 that wants to use this address.
1780
1781 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1782 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1783
1784 See legitimize_pic_address in i386.cc for details as to what
1785 constitutes a legitimate address when -fpic is used. */
1786
1787#define MAX_REGS_PER_ADDRESS 2
1788
1789#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1790
1791/* If defined, a C expression to determine the base term of address X.
1792 This macro is used in only one place: `find_base_term' in alias.cc.
1793
1794 It is always safe for this macro to not be defined. It exists so
1795 that alias analysis can understand machine-dependent addresses.
1796
1797 The typical use of this macro is to handle addresses containing
1798 a label_ref or symbol_ref within an UNSPEC. */
1799
1800#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1801
1802/* Nonzero if the constant value X is a legitimate general operand
1803 when generating PIC code. It is given that flag_pic is on and
1804 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1805
1806#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1807
1808#define STRIP_UNARY(X) (UNARY_P (X) ? XEXP (X, 0) : X)
1809
1810#define SYMBOLIC_CONST(X) \
1811 (GET_CODE (X) == SYMBOL_REF \
1812 || GET_CODE (X) == LABEL_REF \
1813 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1814
1815/* Max number of args passed in registers. If this is more than 3, we will
1816 have problems with ebx (register #4), since it is a caller save register and
1817 is also used as the pic register in ELF. So for now, don't allow more than
1818 3 registers to be passed in registers. */
1819
1820/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1821#define X86_64_REGPARM_MAX 6
1822#define X86_64_MS_REGPARM_MAX 4
1823
1824#define X86_32_REGPARM_MAX 3
1825
1826#define REGPARM_MAX \
1827 (TARGET_64BIT \
1828 ? (TARGET_64BIT_MS_ABI \
1829 ? X86_64_MS_REGPARM_MAX \
1830 : X86_64_REGPARM_MAX) \
1831 : X86_32_REGPARM_MAX)
1832
1833#define X86_64_SSE_REGPARM_MAX 8
1834#define X86_64_MS_SSE_REGPARM_MAX 4
1835
1836#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1837
1838#define SSE_REGPARM_MAX \
1839 (TARGET_64BIT \
1840 ? (TARGET_64BIT_MS_ABI \
1841 ? X86_64_MS_SSE_REGPARM_MAX \
1842 : X86_64_SSE_REGPARM_MAX) \
1843 : X86_32_SSE_REGPARM_MAX)
1844
1845#define X86_32_MMX_REGPARM_MAX (TARGET_MMX ? (TARGET_MACHO ? 0 : 3) : 0)
1846
1847#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : X86_32_MMX_REGPARM_MAX)
1848
1849/* Specify the machine mode that this machine uses
1850 for the index in the tablejump instruction. */
1851#define CASE_VECTOR_MODE \
1852 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1853
1854/* Define this as 1 if `char' should by default be signed; else as 0. */
1855#define DEFAULT_SIGNED_CHAR 1
1856
1857/* The constant maximum number of bytes that a single instruction can
1858 move quickly between memory and registers or between two memory
1859 locations. */
1860#define MAX_MOVE_MAX 64
1861
1862/* Max number of bytes we can move from memory to memory in one
1863 reasonably fast instruction, as opposed to MOVE_MAX_PIECES which
1864 is the number of bytes at a time which we can move efficiently.
1865 MOVE_MAX_PIECES defaults to MOVE_MAX. */
1866
1867#define MOVE_MAX \
1868 ((TARGET_AVX512F && TARGET_EVEX512\
1869 && (ix86_move_max == PVW_AVX512 \
1870 || ix86_store_max == PVW_AVX512)) \
1871 ? 64 \
1872 : ((TARGET_AVX \
1873 && (ix86_move_max >= PVW_AVX256 \
1874 || ix86_store_max >= PVW_AVX256)) \
1875 ? 32 \
1876 : ((TARGET_SSE2 \
1877 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
1878 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1879 ? 16 : UNITS_PER_WORD)))
1880
1881/* STORE_MAX_PIECES is the number of bytes at a time that we can store
1882 efficiently. Allow 16/32/64 bytes only if inter-unit move is enabled
1883 since vec_duplicate enabled by inter-unit move is used to implement
1884 store_by_pieces of 16/32/64 bytes. */
1885#define STORE_MAX_PIECES \
1886 (TARGET_INTER_UNIT_MOVES_TO_VEC \
1887 ? ((TARGET_AVX512F && TARGET_EVEX512 && ix86_store_max == PVW_AVX512) \
1888 ? 64 \
1889 : ((TARGET_AVX \
1890 && ix86_store_max >= PVW_AVX256) \
1891 ? 32 \
1892 : ((TARGET_SSE2 \
1893 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1894 ? 16 : UNITS_PER_WORD))) \
1895 : UNITS_PER_WORD)
1896
1897/* If a memory-to-memory move would take MOVE_RATIO or more simple
1898 move-instruction pairs, we will do a cpymem or libcall instead.
1899 Increasing the value will always make code faster, but eventually
1900 incurs high cost in increased code size.
1901
1902 If you don't define this, a reasonable default is used. */
1903
1904#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1905
1906/* If a clear memory operation would take CLEAR_RATIO or more simple
1907 move-instruction sequences, we will do a clrmem or libcall instead. */
1908
1909#define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2)
1910
1911/* Define if shifts truncate the shift count which implies one can
1912 omit a sign-extension or zero-extension of a shift count.
1913
1914 On i386, shifts do truncate the count. But bit test instructions
1915 take the modulo of the bit offset operand. */
1916
1917/* #define SHIFT_COUNT_TRUNCATED */
1918
1919/* A macro to update M and UNSIGNEDP when an object whose type is
1920 TYPE and which has the specified mode and signedness is to be
1921 stored in a register. This macro is only called when TYPE is a
1922 scalar type.
1923
1924 On i386 it is sometimes useful to promote HImode and QImode
1925 quantities to SImode. The choice depends on target type. */
1926
1927#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1928do { \
1929 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1930 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1931 (MODE) = SImode; \
1932} while (0)
1933
1934/* Specify the machine mode that pointers have.
1935 After generation of rtl, the compiler makes no further distinction
1936 between pointers and any other objects of this machine mode. */
1937#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1938
1939/* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save.
1940 NONLOCAL needs space to save both shadow stack and stack pointers.
1941
1942 FIXME: We only need to save and restore stack pointer in ptr_mode.
1943 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode
1944 to save and restore stack pointer. See
1945 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150
1946 */
1947#define STACK_SAVEAREA_MODE(LEVEL) \
1948 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
1949
1950/* Specify the machine_mode of the size increment
1951 operand of an 'allocate_stack' named pattern. */
1952#define STACK_SIZE_MODE Pmode
1953
1954/* A C expression whose value is zero if pointers that need to be extended
1955 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1956 greater then zero if they are zero-extended and less then zero if the
1957 ptr_extend instruction should be used. */
1958
1959#define POINTERS_EXTEND_UNSIGNED 1
1960
1961/* A function address in a call instruction
1962 is a byte address (for indexing purposes)
1963 so give the MEM rtx a byte's mode. */
1964#define FUNCTION_MODE QImode
1965
1966
1967/* A C expression for the cost of a branch instruction. A value of 1
1968 is the default; other values are interpreted relative to that. */
1969
1970#define BRANCH_COST(speed_p, predictable_p) \
1971 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1972
1973/* An integer expression for the size in bits of the largest integer machine
1974 mode that should actually be used. We allow pairs of registers. */
1975#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1976
1977/* Define this macro as a C expression which is nonzero if accessing
1978 less than a word of memory (i.e. a `char' or a `short') is no
1979 faster than accessing a word of memory, i.e., if such access
1980 require more than one instruction or if there is no difference in
1981 cost between byte and (aligned) word loads.
1982
1983 When this macro is not defined, the compiler will access a field by
1984 finding the smallest containing object; when it is defined, a
1985 fullword load will be used if alignment permits. Unless bytes
1986 accesses are faster than word accesses, using word accesses is
1987 preferable since it may eliminate subsequent memory access if
1988 subsequent accesses occur to other fields in the same word of the
1989 structure, but to different bytes. */
1990
1991#define SLOW_BYTE_ACCESS 0
1992
1993/* Define this macro if it is as good or better to call a constant
1994 function address than to call an address kept in a register.
1995
1996 Desirable on the 386 because a CALL with a constant address is
1997 faster than one with a register address. */
1998
1999#define NO_FUNCTION_CSE 1
2000
2001/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2002 return the mode to be used for the comparison.
2003
2004 For floating-point equality comparisons, CCFPEQmode should be used.
2005 VOIDmode should be used in all other cases.
2006
2007 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2008 possible, to allow for more combinations. */
2009
2010#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2011
2012/* Return nonzero if MODE implies a floating point inequality can be
2013 reversed. */
2014
2015#define REVERSIBLE_CC_MODE(MODE) 1
2016
2017/* A C expression whose value is reversed condition code of the CODE for
2018 comparison done in CC_MODE mode. */
2019#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2020
2021
2022/* Control the assembler format that we output, to the extent
2023 this does not vary between assemblers. */
2024
2025/* How to refer to registers in assembler output.
2026 This sequence is indexed by compiler's hard-register-number (see above). */
2027
2028/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2029 For non floating point regs, the following are the HImode names.
2030
2031 For float regs, the stack top is sometimes referred to as "%st(0)"
2032 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
2033 "y" code. */
2034
2035#define HI_REGISTER_NAMES \
2036{"ax","dx","cx","bx","si","di","bp","sp", \
2037 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2038 "argp", "flags", "fpsr", "frame", \
2039 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2040 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2041 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2042 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
2043 "xmm16", "xmm17", "xmm18", "xmm19", \
2044 "xmm20", "xmm21", "xmm22", "xmm23", \
2045 "xmm24", "xmm25", "xmm26", "xmm27", \
2046 "xmm28", "xmm29", "xmm30", "xmm31", \
2047 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
2048 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2049 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }
2050
2051#define REGISTER_NAMES HI_REGISTER_NAMES
2052
2053#define QI_REGISTER_NAMES \
2054{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"}
2055
2056#define QI_HIGH_REGISTER_NAMES \
2057{"ah", "dh", "ch", "bh"}
2058
2059/* Table of additional register names to use in user input. */
2060
2061#define ADDITIONAL_REGISTER_NAMES \
2062{ \
2063 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \
2064 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \
2065 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
2066 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
2067 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
2068 { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \
2069 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
2070 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
2071 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
2072 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \
2073 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \
2074 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \
2075 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \
2076 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \
2077 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \
2078 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \
2079 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \
2080 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \
2081 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \
2082 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \
2083 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \
2084 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \
2085 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
2086}
2087
2088/* How to renumber registers for gdb. */
2089
2090#define DEBUGGER_REGNO(N) \
2091 (TARGET_64BIT ? debugger64_register_map[(N)] : debugger_register_map[(N)])
2092
2093extern int const debugger_register_map[FIRST_PSEUDO_REGISTER];
2094extern int const debugger64_register_map[FIRST_PSEUDO_REGISTER];
2095extern int const svr4_debugger_register_map[FIRST_PSEUDO_REGISTER];
2096
2097/* Before the prologue, RA is at 0(%esp). */
2098#define INCOMING_RETURN_ADDR_RTX \
2099 gen_rtx_MEM (Pmode, stack_pointer_rtx)
2100
2101/* After the prologue, RA is at -4(AP) in the current frame. */
2102#define RETURN_ADDR_RTX(COUNT, FRAME) \
2103 ((COUNT) == 0 \
2104 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2105 -UNITS_PER_WORD)) \
2106 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD)))
2107
2108/* PC is dbx register 8; let's use that column for RA. */
2109#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2110
2111/* Before the prologue, there are return address and error code for
2112 exception handler on the top of the frame. */
2113#define INCOMING_FRAME_SP_OFFSET \
2114 (cfun->machine->func_type == TYPE_EXCEPTION \
2115 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2116
2117/* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in
2118 .cfi_startproc. */
2119#define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2120
2121/* Describe how we implement __builtin_eh_return. */
2122#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2123#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2124
2125
2126/* Select a format to encode pointers in exception handling data. CODE
2127 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2128 true if the symbol may be affected by dynamic relocations.
2129
2130 ??? All x86 object file formats are capable of representing this.
2131 After all, the relocation needed is the same as for the call insn.
2132 Whether or not a particular assembler allows us to enter such, I
2133 guess we'll have to see. */
2134#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2135 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2136
2137/* These are a couple of extensions to the formats accepted
2138 by asm_fprintf:
2139 %z prints out opcode suffix for word-mode instruction
2140 %r prints out word-mode name for reg_names[arg] */
2141#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
2142 case 'z': \
2143 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \
2144 break; \
2145 \
2146 case 'r': \
2147 { \
2148 unsigned int regno = va_arg ((ARGS), int); \
2149 if (LEGACY_INT_REGNO_P (regno)) \
2150 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \
2151 fputs (reg_names[regno], (FILE)); \
2152 break; \
2153 }
2154
2155/* This is how to output an insn to push a register on the stack. */
2156
2157#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2158 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO))
2159
2160/* This is how to output an insn to pop a register from the stack. */
2161
2162#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2163 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO))
2164
2165/* This is how to output an element of a case-vector that is absolute. */
2166
2167#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2168 ix86_output_addr_vec_elt ((FILE), (VALUE))
2169
2170/* This is how to output an element of a case-vector that is relative. */
2171
2172#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2173 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2174
2175/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2176
2177#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2178{ \
2179 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2180 (PTR) += TARGET_AVX ? 1 : 2; \
2181}
2182
2183/* A C statement or statements which output an assembler instruction
2184 opcode to the stdio stream STREAM. The macro-operand PTR is a
2185 variable of type `char *' which points to the opcode name in
2186 its "internal" form--the form that is written in the machine
2187 description. */
2188
2189#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2190 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2191
2192/* A C statement to output to the stdio stream FILE an assembler
2193 command to pad the location counter to a multiple of 1<<LOG
2194 bytes if it is within MAX_SKIP bytes. */
2195
2196#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2197# define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2198 do { \
2199 if ((LOG) != 0) { \
2200 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \
2201 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2202 else \
2203 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2204 } \
2205 } while (0)
2206#endif
2207
2208/* Write the extra assembler code needed to declare a function
2209 properly. */
2210
2211#undef ASM_OUTPUT_FUNCTION_LABEL
2212#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2213 ix86_asm_output_function_label ((FILE), (NAME), (DECL))
2214
2215/* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM.
2216 If not defined, assemble_name will be used to output the name of the
2217 symbol. This macro may be used to modify the way a symbol is referenced
2218 depending on information encoded by TARGET_ENCODE_SECTION_INFO. */
2219
2220#ifndef ASM_OUTPUT_SYMBOL_REF
2221#define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \
2222 do { \
2223 const char *name \
2224 = assemble_name_resolve (XSTR (x, 0)); \
2225 /* In -masm=att wrap identifiers that start with $ \
2226 into parens. */ \
2227 if (ASSEMBLER_DIALECT == ASM_ATT \
2228 && name[0] == '$' \
2229 && user_label_prefix[0] == '\0') \
2230 { \
2231 fputc ('(', (FILE)); \
2232 assemble_name_raw ((FILE), name); \
2233 fputc (')', (FILE)); \
2234 } \
2235 else \
2236 assemble_name_raw ((FILE), name); \
2237 } while (0)
2238#endif
2239
2240/* Under some conditions we need jump tables in the text section,
2241 because the assembler cannot handle label differences between
2242 sections. */
2243
2244#define JUMP_TABLES_IN_TEXT_SECTION \
2245 (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA))
2246
2247/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2248 and switch back. For x86 we do this only to save a few bytes that
2249 would otherwise be unused in the text section. */
2250#define CRT_MKSTR2(VAL) #VAL
2251#define CRT_MKSTR(x) CRT_MKSTR2(x)
2252
2253#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2254 asm (SECTION_OP "\n\t" \
2255 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2256 TEXT_SECTION_ASM_OP);
2257
2258/* Default threshold for putting data in large sections
2259 with x86-64 medium memory model */
2260#define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2261
2262/* Which processor to tune code generation for. These must be in sync
2263 with processor_cost_table in i386-options.cc. */
2264
2265enum processor_type
2266{
2267 PROCESSOR_GENERIC = 0,
2268 PROCESSOR_I386, /* 80386 */
2269 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2270 PROCESSOR_PENTIUM,
2271 PROCESSOR_LAKEMONT,
2272 PROCESSOR_PENTIUMPRO,
2273 PROCESSOR_PENTIUM4,
2274 PROCESSOR_NOCONA,
2275 PROCESSOR_CORE2,
2276 PROCESSOR_NEHALEM,
2277 PROCESSOR_SANDYBRIDGE,
2278 PROCESSOR_HASWELL,
2279 PROCESSOR_BONNELL,
2280 PROCESSOR_SILVERMONT,
2281 PROCESSOR_GOLDMONT,
2282 PROCESSOR_GOLDMONT_PLUS,
2283 PROCESSOR_TREMONT,
2284 PROCESSOR_SIERRAFOREST,
2285 PROCESSOR_GRANDRIDGE,
2286 PROCESSOR_CLEARWATERFOREST,
2287 PROCESSOR_KNL,
2288 PROCESSOR_KNM,
2289 PROCESSOR_SKYLAKE,
2290 PROCESSOR_SKYLAKE_AVX512,
2291 PROCESSOR_CANNONLAKE,
2292 PROCESSOR_ICELAKE_CLIENT,
2293 PROCESSOR_ICELAKE_SERVER,
2294 PROCESSOR_CASCADELAKE,
2295 PROCESSOR_TIGERLAKE,
2296 PROCESSOR_COOPERLAKE,
2297 PROCESSOR_SAPPHIRERAPIDS,
2298 PROCESSOR_ALDERLAKE,
2299 PROCESSOR_ROCKETLAKE,
2300 PROCESSOR_GRANITERAPIDS,
2301 PROCESSOR_GRANITERAPIDS_D,
2302 PROCESSOR_ARROWLAKE,
2303 PROCESSOR_ARROWLAKE_S,
2304 PROCESSOR_PANTHERLAKE,
2305 PROCESSOR_INTEL,
2306 PROCESSOR_LUJIAZUI,
2307 PROCESSOR_YONGFENG,
2308 PROCESSOR_GEODE,
2309 PROCESSOR_K6,
2310 PROCESSOR_ATHLON,
2311 PROCESSOR_K8,
2312 PROCESSOR_AMDFAM10,
2313 PROCESSOR_BDVER1,
2314 PROCESSOR_BDVER2,
2315 PROCESSOR_BDVER3,
2316 PROCESSOR_BDVER4,
2317 PROCESSOR_BTVER1,
2318 PROCESSOR_BTVER2,
2319 PROCESSOR_ZNVER1,
2320 PROCESSOR_ZNVER2,
2321 PROCESSOR_ZNVER3,
2322 PROCESSOR_ZNVER4,
2323 PROCESSOR_ZNVER5,
2324 PROCESSOR_max
2325};
2326
2327#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
2328extern const char *const processor_names[];
2329
2330#include "wide-int-bitmask.h"
2331
2332enum pta_flag
2333{
2334#define DEF_PTA(NAME) _ ## NAME,
2335#include "i386-isa.def"
2336#undef DEF_PTA
2337 END_PTA
2338};
2339
2340/* wide_int_bitmask can handle only 128 flags. */
2341STATIC_ASSERT (END_PTA <= 128);
2342
2343#define WIDE_INT_BITMASK_FROM_NTH(N) (N < 64 ? wide_int_bitmask (0, 1ULL << N) \
2344 : wide_int_bitmask (1ULL << (N - 64), 0))
2345
2346#define DEF_PTA(NAME) constexpr wide_int_bitmask PTA_ ## NAME \
2347 = WIDE_INT_BITMASK_FROM_NTH ((pta_flag) _ ## NAME);
2348#include "i386-isa.def"
2349#undef DEF_PTA
2350
2351constexpr wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE
2352 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR;
2353constexpr wide_int_bitmask PTA_X86_64_V2 = (PTA_X86_64_BASELINE
2354 & (~PTA_NO_SAHF))
2355 | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_SSSE3;
2356constexpr wide_int_bitmask PTA_X86_64_V3 = PTA_X86_64_V2
2357 | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2358 | PTA_MOVBE | PTA_XSAVE;
2359constexpr wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3
2360 | PTA_AVX512F | PTA_AVX512BW | PTA_AVX512CD | PTA_AVX512DQ | PTA_AVX512VL;
2361
2362constexpr wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2363 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
2364constexpr wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
2365 | PTA_POPCNT;
2366constexpr wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
2367constexpr wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
2368 | PTA_XSAVEOPT;
2369constexpr wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
2370 | PTA_RDRND | PTA_F16C;
2371constexpr wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
2372 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
2373constexpr wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
2374 | PTA_PRFCHW;
2375constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES
2376 | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
2377constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
2378 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2379 | PTA_CLWB | PTA_EVEX512;
2380constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512
2381 | PTA_AVX512VNNI;
2382constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
2383constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
2384 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2385 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_EVEX512;
2386constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
2387 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
2388 | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
2389constexpr wide_int_bitmask PTA_ROCKETLAKE = PTA_ICELAKE_CLIENT & ~PTA_SGX;
2390constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT
2391 | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB;
2392constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
2393 | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL | PTA_WIDEKL;
2394constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_ICELAKE_SERVER | PTA_MOVDIRI
2395 | PTA_MOVDIR64B | PTA_ENQCMD | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG
2396 | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16
2397 | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16 | PTA_AVX512BF16;
2398constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF
2399 | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
2400constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
2401constexpr wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE
2402 | PTA_RDRND | PTA_PRFCHW;
2403constexpr wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA
2404 | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT
2405 | PTA_XSAVEOPT | PTA_FSGSBASE;
2406constexpr wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
2407 | PTA_SGX | PTA_PTWRITE;
2408constexpr wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
2409 | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
2410constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX
2411 | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2412 | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
2413 | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
2414constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
2415 | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD | PTA_UINTR;
2416constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
2417 | PTA_PREFETCHI;
2418constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS
2419 | PTA_AMX_COMPLEX;
2420constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST;
2421constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA
2422 | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR;
2423constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16
2424 | PTA_SHA512 | PTA_SM3 | PTA_SM4;
2425constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST
2426 | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR
2427 | PTA_PREFETCHI;
2428constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI;
2429constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
2430 | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
2431constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2432 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2433 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2
2434 | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT
2435 | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
2436 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SHA | PTA_LZCNT
2437 | PTA_POPCNT;
2438constexpr wide_int_bitmask PTA_ZNVER2 = PTA_ZNVER1 | PTA_CLWB | PTA_RDPID
2439 | PTA_WBNOINVD;
2440constexpr wide_int_bitmask PTA_ZNVER3 = PTA_ZNVER2 | PTA_VAES | PTA_VPCLMULQDQ
2441 | PTA_PKU;
2442constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ
2443 | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
2444 | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
2445 | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ | PTA_EVEX512;
2446constexpr wide_int_bitmask PTA_ZNVER5 = PTA_ZNVER4 | PTA_AVXVNNI
2447 | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_PREFETCHI;
2448constexpr wide_int_bitmask PTA_LUJIAZUI = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2449 | PTA_SSE3 | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES
2450 | PTA_PCLMUL | PTA_BMI | PTA_BMI2 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT
2451 | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_ADX | PTA_RDSEED | PTA_POPCNT;
2452
2453constexpr wide_int_bitmask PTA_YONGFENG = PTA_LUJIAZUI | PTA_AVX | PTA_AVX2 | PTA_F16C
2454 | PTA_FMA | PTA_SHA | PTA_LZCNT;
2455
2456#ifndef GENERATOR_FILE
2457
2458#include "insn-attr-common.h"
2459
2460#include "common/config/i386/i386-cpuinfo.h"
2461
2462class pta
2463{
2464public:
2465 const char *const name; /* processor name or nickname. */
2466 const enum processor_type processor;
2467 const enum attr_cpu schedule;
2468 const wide_int_bitmask flags;
2469 const int model;
2470 const enum feature_priority priority;
2471};
2472
2473extern const pta processor_alias_table[];
2474extern unsigned int const pta_size;
2475extern unsigned int const num_arch_names;
2476#endif
2477
2478#endif
2479
2480extern enum processor_type ix86_tune;
2481extern enum processor_type ix86_arch;
2482
2483/* Size of the RED_ZONE area. */
2484#define RED_ZONE_SIZE 128
2485/* Reserved area of the red zone for temporaries. */
2486#define RED_ZONE_RESERVE 8
2487
2488extern unsigned int ix86_preferred_stack_boundary;
2489extern unsigned int ix86_incoming_stack_boundary;
2490
2491/* Smallest class containing REGNO. */
2492extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2493
2494enum ix86_fpcmp_strategy {
2495 IX86_FPCMP_SAHF,
2496 IX86_FPCMP_COMI,
2497 IX86_FPCMP_ARITH
2498};
2499
2500/* To properly truncate FP values into integers, we need to set i387 control
2501 word. We can't emit proper mode switching code before reload, as spills
2502 generated by reload may truncate values incorrectly, but we still can avoid
2503 redundant computation of new control word by the mode switching pass.
2504 The fldcw instructions are still emitted redundantly, but this is probably
2505 not going to be noticeable problem, as most CPUs do have fast path for
2506 the sequence.
2507
2508 The machinery is to emit simple truncation instructions and split them
2509 before reload to instructions having USEs of two memory locations that
2510 are filled by this code to old and new control word.
2511
2512 Post-reload pass may be later used to eliminate the redundant fildcw if
2513 needed. */
2514
2515enum ix86_stack_slot
2516{
2517 SLOT_TEMP = 0,
2518 SLOT_CW_STORED,
2519 SLOT_CW_ROUNDEVEN,
2520 SLOT_CW_TRUNC,
2521 SLOT_CW_FLOOR,
2522 SLOT_CW_CEIL,
2523 SLOT_STV_TEMP,
2524 SLOT_FLOATxFDI_387,
2525 MAX_386_STACK_LOCALS
2526};
2527
2528enum ix86_entity
2529{
2530 X86_DIRFLAG = 0,
2531 AVX_U128,
2532 I387_ROUNDEVEN,
2533 I387_TRUNC,
2534 I387_FLOOR,
2535 I387_CEIL,
2536 MAX_386_ENTITIES
2537};
2538
2539enum x86_dirflag_state
2540{
2541 X86_DIRFLAG_RESET,
2542 X86_DIRFLAG_ANY
2543};
2544
2545enum avx_u128_state
2546{
2547 AVX_U128_CLEAN,
2548 AVX_U128_DIRTY,
2549 AVX_U128_ANY
2550};
2551
2552/* Define this macro if the port needs extra instructions inserted
2553 for mode switching in an optimizing compilation. */
2554
2555#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2556 ix86_optimize_mode_switching[(ENTITY)]
2557
2558/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2559 initializer for an array of integers. Each initializer element N
2560 refers to an entity that needs mode switching, and specifies the
2561 number of different modes that might need to be set for this
2562 entity. The position of the initializer in the initializer -
2563 starting counting at zero - determines the integer that is used to
2564 refer to the mode-switched entity in question. */
2565
2566#define NUM_MODES_FOR_MODE_SWITCHING \
2567 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2568 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2569
2570
2571/* Avoid renaming of stack registers, as doing so in combination with
2572 scheduling just increases amount of live registers at time and in
2573 the turn amount of fxch instructions needed.
2574
2575 ??? Maybe Pentium chips benefits from renaming, someone can try....
2576
2577 Don't rename evex to non-evex sse registers. */
2578
2579#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2580 (!STACK_REGNO_P (SRC) \
2581 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET))
2582
2583
2584#define FASTCALL_PREFIX '@'
2585
2586#ifndef USED_FOR_TARGET
2587/* Structure describing stack frame layout.
2588 Stack grows downward:
2589
2590 [arguments]
2591 <- ARG_POINTER
2592 saved pc
2593
2594 saved static chain if ix86_static_chain_on_stack
2595
2596 saved frame pointer if frame_pointer_needed
2597 <- HARD_FRAME_POINTER
2598 [saved regs]
2599 <- reg_save_offset
2600 [padding0]
2601 <- stack_realign_offset
2602 [saved SSE regs]
2603 OR
2604 [stub-saved registers for ms x64 --> sysv clobbers
2605 <- Start of out-of-line, stub-saved/restored regs
2606 (see libgcc/config/i386/(sav|res)ms64*.S)
2607 [XMM6-15]
2608 [RSI]
2609 [RDI]
2610 [?RBX] only if RBX is clobbered
2611 [?RBP] only if RBP and RBX are clobbered
2612 [?R12] only if R12 and all previous regs are clobbered
2613 [?R13] only if R13 and all previous regs are clobbered
2614 [?R14] only if R14 and all previous regs are clobbered
2615 [?R15] only if R15 and all previous regs are clobbered
2616 <- end of stub-saved/restored regs
2617 [padding1]
2618 ]
2619 <- sse_reg_save_offset
2620 [padding2]
2621 | <- FRAME_POINTER
2622 [va_arg registers] |
2623 |
2624 [frame] |
2625 |
2626 [padding2] | = to_allocate
2627 <- STACK_POINTER
2628 */
2629struct GTY(()) ix86_frame
2630{
2631 int nsseregs;
2632 int nregs;
2633 int va_arg_size;
2634 int red_zone_size;
2635 int outgoing_arguments_size;
2636
2637 /* The offsets relative to ARG_POINTER. */
2638 HOST_WIDE_INT frame_pointer_offset;
2639 HOST_WIDE_INT hard_frame_pointer_offset;
2640 HOST_WIDE_INT stack_pointer_offset;
2641 HOST_WIDE_INT hfp_save_offset;
2642 HOST_WIDE_INT reg_save_offset;
2643 HOST_WIDE_INT stack_realign_allocate;
2644 HOST_WIDE_INT stack_realign_offset;
2645 HOST_WIDE_INT sse_reg_save_offset;
2646
2647 /* When save_regs_using_mov is set, emit prologue using
2648 move instead of push instructions. */
2649 bool save_regs_using_mov;
2650
2651 /* Assume without checking that:
2652 EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */
2653 bool expensive_p;
2654 int expensive_count;
2655};
2656
2657/* Machine specific frame tracking during prologue/epilogue generation. All
2658 values are positive, but since the x86 stack grows downward, are subtratced
2659 from the CFA to produce a valid address. */
2660
2661struct GTY(()) machine_frame_state
2662{
2663 /* This pair tracks the currently active CFA as reg+offset. When reg
2664 is drap_reg, we don't bother trying to record here the real CFA when
2665 it might really be a DW_CFA_def_cfa_expression. */
2666 rtx cfa_reg;
2667 HOST_WIDE_INT cfa_offset;
2668
2669 /* The current offset (canonically from the CFA) of ESP and EBP.
2670 When stack frame re-alignment is active, these may not be relative
2671 to the CFA. However, in all cases they are relative to the offsets
2672 of the saved registers stored in ix86_frame. */
2673 HOST_WIDE_INT sp_offset;
2674 HOST_WIDE_INT fp_offset;
2675
2676 /* The size of the red-zone that may be assumed for the purposes of
2677 eliding register restore notes in the epilogue. This may be zero
2678 if no red-zone is in effect, or may be reduced from the real
2679 red-zone value by a maximum runtime stack re-alignment value. */
2680 int red_zone_offset;
2681
2682 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2683 value within the frame. If false then the offset above should be
2684 ignored. Note that DRAP, if valid, *always* points to the CFA and
2685 thus has an offset of zero. */
2686 BOOL_BITFIELD sp_valid : 1;
2687 BOOL_BITFIELD fp_valid : 1;
2688 BOOL_BITFIELD drap_valid : 1;
2689
2690 /* Indicate whether the local stack frame has been re-aligned. When
2691 set, the SP/FP offsets above are relative to the aligned frame
2692 and not the CFA. */
2693 BOOL_BITFIELD realigned : 1;
2694
2695 /* Indicates whether the stack pointer has been re-aligned. When set,
2696 SP/FP continue to be relative to the CFA, but the stack pointer
2697 should only be used for offsets > sp_realigned_offset, while
2698 the frame pointer should be used for offsets <= sp_realigned_fp_last.
2699 The flags realigned and sp_realigned are mutually exclusive. */
2700 BOOL_BITFIELD sp_realigned : 1;
2701
2702 /* If sp_realigned is set, this is the last valid offset from the CFA
2703 that can be used for access with the frame pointer. */
2704 HOST_WIDE_INT sp_realigned_fp_last;
2705
2706 /* If sp_realigned is set, this is the offset from the CFA that the stack
2707 pointer was realigned, and may or may not be equal to sp_realigned_fp_last.
2708 Access via the stack pointer is only valid for offsets that are greater than
2709 this value. */
2710 HOST_WIDE_INT sp_realigned_offset;
2711};
2712
2713/* Private to winnt.cc. */
2714struct seh_frame_state;
2715
2716enum function_type
2717{
2718 TYPE_UNKNOWN = 0,
2719 TYPE_NORMAL,
2720 /* The current function is an interrupt service routine with a
2721 pointer argument as specified by the "interrupt" attribute. */
2722 TYPE_INTERRUPT,
2723 /* The current function is an interrupt service routine with a
2724 pointer argument and an integer argument as specified by the
2725 "interrupt" attribute. */
2726 TYPE_EXCEPTION
2727};
2728
2729enum call_saved_registers_type
2730{
2731 TYPE_DEFAULT_CALL_SAVED_REGISTERS = 0,
2732 /* The current function is a function specified with the "interrupt"
2733 or "no_caller_saved_registers" attribute. */
2734 TYPE_NO_CALLER_SAVED_REGISTERS,
2735 /* The current function is a function specified with the
2736 "no_callee_saved_registers" attribute. */
2737 TYPE_NO_CALLEE_SAVED_REGISTERS,
2738 /* The current function is a function specified with the "noreturn"
2739 attribute. */
2740 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP,
2741};
2742
2743enum queued_insn_type
2744{
2745 TYPE_NONE = 0,
2746 TYPE_ENDBR,
2747 TYPE_PATCHABLE_AREA
2748};
2749
2750struct GTY(()) machine_function {
2751 struct stack_local_entry *stack_locals;
2752 int varargs_gpr_size;
2753 int varargs_fpr_size;
2754 int optimize_mode_switching[MAX_386_ENTITIES];
2755
2756 /* Cached initial frame layout for the current function. */
2757 struct ix86_frame frame;
2758
2759 /* For -fsplit-stack support: A stack local which holds a pointer to
2760 the stack arguments for a function with a variable number of
2761 arguments. This is set at the start of the function and is used
2762 to initialize the overflow_arg_area field of the va_list
2763 structure. */
2764 rtx split_stack_varargs_pointer;
2765
2766 /* This value is used for amd64 targets and specifies the current abi
2767 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2768 ENUM_BITFIELD(calling_abi) call_abi : 8;
2769
2770 /* Nonzero if the function accesses a previous frame. */
2771 BOOL_BITFIELD accesses_prev_frame : 1;
2772
2773 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2774 expander to determine the style used. */
2775 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2776
2777 /* Nonzero if the current function calls pc thunk and
2778 must not use the red zone. */
2779 BOOL_BITFIELD pc_thunk_call_expanded : 1;
2780
2781 /* If true, the current function needs the default PIC register, not
2782 an alternate register (on x86) and must not use the red zone (on
2783 x86_64), even if it's a leaf function. We don't want the
2784 function to be regarded as non-leaf because TLS calls need not
2785 affect register allocation. This flag is set when a TLS call
2786 instruction is expanded within a function, and never reset, even
2787 if all such instructions are optimized away. Use the
2788 ix86_current_function_calls_tls_descriptor macro for a better
2789 approximation. */
2790 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2791
2792 /* If true, the current function has a STATIC_CHAIN is placed on the
2793 stack below the return address. */
2794 BOOL_BITFIELD static_chain_on_stack : 1;
2795
2796 /* If true, it is safe to not save/restore DRAP register. */
2797 BOOL_BITFIELD no_drap_save_restore : 1;
2798
2799 /* Function type. */
2800 ENUM_BITFIELD(function_type) func_type : 2;
2801
2802 /* How to generate indirec branch. */
2803 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3;
2804
2805 /* If true, the current function has local indirect jumps, like
2806 "indirect_jump" or "tablejump". */
2807 BOOL_BITFIELD has_local_indirect_jump : 1;
2808
2809 /* How to generate function return. */
2810 ENUM_BITFIELD(indirect_branch) function_return_type : 3;
2811
2812 /* Call saved registers type. */
2813 ENUM_BITFIELD(call_saved_registers_type) call_saved_registers : 2;
2814
2815 /* If true, there is register available for argument passing. This
2816 is used only in ix86_function_ok_for_sibcall by 32-bit to determine
2817 if there is scratch register available for indirect sibcall. In
2818 64-bit, rax, r10 and r11 are scratch registers which aren't used to
2819 pass arguments and can be used for indirect sibcall. */
2820 BOOL_BITFIELD arg_reg_available : 1;
2821
2822 /* If true, we're out-of-lining reg save/restore for regs clobbered
2823 by 64-bit ms_abi functions calling a sysv_abi function. */
2824 BOOL_BITFIELD call_ms2sysv : 1;
2825
2826 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and
2827 needs padding prior to out-of-line stub save/restore area. */
2828 BOOL_BITFIELD call_ms2sysv_pad_in : 1;
2829
2830 /* This is the number of extra registers saved by stub (valid range is
2831 0-6). Each additional register is only saved/restored by the stubs
2832 if all successive ones are. (Will always be zero when using a hard
2833 frame pointer.) */
2834 unsigned int call_ms2sysv_extra_regs:3;
2835
2836 /* Nonzero if the function places outgoing arguments on stack. */
2837 BOOL_BITFIELD outgoing_args_on_stack : 1;
2838
2839 /* If true, ENDBR or patchable area is queued at function entrance. */
2840 ENUM_BITFIELD(queued_insn_type) insn_queued_at_entrance : 2;
2841
2842 /* If true, the function label has been emitted. */
2843 BOOL_BITFIELD function_label_emitted : 1;
2844
2845 /* True if the function needs a stack frame. */
2846 BOOL_BITFIELD stack_frame_required : 1;
2847
2848 /* True if we should act silently, rather than raise an error for
2849 invalid calls. */
2850 BOOL_BITFIELD silent_p : 1;
2851
2852 /* True if red zone is used. */
2853 BOOL_BITFIELD red_zone_used : 1;
2854
2855 /* The largest alignment, in bytes, of stack slot actually used. */
2856 unsigned int max_used_stack_alignment;
2857
2858 /* During prologue/epilogue generation, the current frame state.
2859 Otherwise, the frame state at the end of the prologue. */
2860 struct machine_frame_state fs;
2861
2862 /* During SEH output, this is non-null. */
2863 struct seh_frame_state * GTY((skip(""))) seh;
2864};
2865
2866extern GTY(()) tree sysv_va_list_type_node;
2867extern GTY(()) tree ms_va_list_type_node;
2868#endif
2869
2870#define ix86_stack_locals (cfun->machine->stack_locals)
2871#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2872#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2873#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2874#define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded)
2875#define ix86_tls_descriptor_calls_expanded_in_cfun \
2876 (cfun->machine->tls_descriptor_call_expanded_p)
2877/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2878 calls are optimized away, we try to detect cases in which it was
2879 optimized away. Since such instructions (use (reg REG_SP)), we can
2880 verify whether there's any such instruction live by testing that
2881 REG_SP is live. */
2882#define ix86_current_function_calls_tls_descriptor \
2883 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2884#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2885#define ix86_red_zone_used (cfun->machine->red_zone_used)
2886
2887/* Control behavior of x86_file_start. */
2888#define X86_FILE_START_VERSION_DIRECTIVE false
2889#define X86_FILE_START_FLTUSED false
2890
2891/* Flag to mark data that is in the large address area. */
2892#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2893#define SYMBOL_REF_FAR_ADDR_P(X) \
2894 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2895
2896/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2897 have defined always, to avoid ifdefing. */
2898#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2899#define SYMBOL_REF_DLLIMPORT_P(X) \
2900 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2901
2902#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2903#define SYMBOL_REF_DLLEXPORT_P(X) \
2904 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2905
2906#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
2907#define SYMBOL_REF_STUBVAR_P(X) \
2908 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
2909
2910extern void debug_ready_dispatch (void);
2911extern void debug_dispatch_window (int);
2912
2913/* The value at zero is only defined for the BMI instructions
2914 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2915#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2916 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 2 : 0)
2917#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2918 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 2 : 0)
2919
2920
2921/* Flags returned by ix86_get_callcvt (). */
2922#define IX86_CALLCVT_CDECL 0x1
2923#define IX86_CALLCVT_STDCALL 0x2
2924#define IX86_CALLCVT_FASTCALL 0x4
2925#define IX86_CALLCVT_THISCALL 0x8
2926#define IX86_CALLCVT_REGPARM 0x10
2927#define IX86_CALLCVT_SSEREGPARM 0x20
2928
2929#define IX86_BASE_CALLCVT(FLAGS) \
2930 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2931 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2932
2933#define RECIP_MASK_NONE 0x00
2934#define RECIP_MASK_DIV 0x01
2935#define RECIP_MASK_SQRT 0x02
2936#define RECIP_MASK_VEC_DIV 0x04
2937#define RECIP_MASK_VEC_SQRT 0x08
2938#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2939 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2940#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2941
2942#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2943#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2944#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2945#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2946
2947/* Use 128-bit AVX instructions in the auto-vectorizer. */
2948#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
2949/* Use 256-bit AVX instructions in the auto-vectorizer. */
2950#define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
2951 || prefer_vector_width_type == PVW_AVX256)
2952
2953#define TARGET_INDIRECT_BRANCH_REGISTER \
2954 (ix86_indirect_branch_register \
2955 || cfun->machine->indirect_branch_type != indirect_branch_keep)
2956
2957#define IX86_HLE_ACQUIRE (1 << 16)
2958#define IX86_HLE_RELEASE (1 << 17)
2959
2960/* For switching between functions with different target attributes. */
2961#define SWITCHABLE_TARGET 1
2962
2963#define TARGET_SUPPORTS_WIDE_INT 1
2964
2965#if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2)
2966extern enum attr_cpu ix86_schedule;
2967
2968#define NUM_X86_64_MS_CLOBBERED_REGS 12
2969#endif
2970
2971/* __builtin_eh_return can't handle stack realignment, so disable MMX/SSE
2972 in 32-bit libgcc functions that call it. */
2973#ifndef __x86_64__
2974#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((target ("no-mmx,no-sse")))
2975#endif
2976
2977/*
2978Local variables:
2979version-control: t
2980End:
2981*/
2982

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source code of gcc/config/i386/i386.h