1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2022 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16Under Section 7 of GPL version 3, you are granted additional
17permissions described in the GCC Runtime Library Exception, version
183.1, as published by the Free Software Foundation.
19
20You should have received a copy of the GNU General Public License and
21a copy of the GCC Runtime Library Exception along with this program;
22see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23<http://www.gnu.org/licenses/>. */
24
25/* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
27
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
30
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
33
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
39
40/* Redefines for option macros. */
41
42#define TARGET_CMPXCHG16B TARGET_CX16
43#define TARGET_CMPXCHG16B_P(x) TARGET_CX16_P(x)
44
45#define TARGET_LP64 TARGET_ABI_64
46#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
47#define TARGET_X32 TARGET_ABI_X32
48#define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
49#define TARGET_16BIT TARGET_CODE16
50#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
51
52#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
53
54#include "config/vxworks-dummy.h"
55
56#include "config/i386/i386-opts.h"
57
58#define MAX_STRINGOP_ALGS 4
59
60/* Specify what algorithm to use for stringops on known size.
61 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
62 known at compile time or estimated via feedback, the SIZE array
63 is walked in order until MAX is greater then the estimate (or -1
64 means infinity). Corresponding ALG is used then.
65 When NOALIGN is true the code guaranting the alignment of the memory
66 block is skipped.
67
68 For example initializer:
69 {{256, loop}, {-1, rep_prefix_4_byte}}
70 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
71 be used otherwise. */
72struct stringop_algs
73{
74 const enum stringop_alg unknown_size;
75 const struct stringop_strategy {
76 /* Several older compilers delete the default constructor because of the
77 const entries (see PR100246). Manually specifying a CTOR works around
78 this issue. Since this header is used by code compiled with the C
79 compiler we must guard the addition. */
80#ifdef __cplusplus
81 constexpr
82 stringop_strategy (int _max = -1, enum stringop_alg _alg = libcall,
83 int _noalign = false)
84 : max (_max), alg (_alg), noalign (_noalign) {}
85#endif
86 const int max;
87 const enum stringop_alg alg;
88 int noalign;
89 } size [MAX_STRINGOP_ALGS];
90};
91
92/* Analog of COSTS_N_INSNS when optimizing for size. */
93#ifndef COSTS_N_BYTES
94#define COSTS_N_BYTES(N) ((N) * 2)
95#endif
96
97/* Define the specific costs for a given cpu. NB: hard_register is used
98 by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute
99 hard register move costs by register allocator. Relative costs of
100 pseudo register load and store versus pseudo register moves in RTL
101 expressions for TARGET_RTX_COSTS can be different from relative
102 costs of hard registers to get the most efficient operations with
103 pseudo registers. */
104
105struct processor_costs {
106 /* Costs used by register allocator. integer->integer register move
107 cost is 2. */
108 struct
109 {
110 const int movzbl_load; /* cost of loading using movzbl */
111 const int int_load[3]; /* cost of loading integer registers
112 in QImode, HImode and SImode relative
113 to reg-reg move (2). */
114 const int int_store[3]; /* cost of storing integer register
115 in QImode, HImode and SImode */
116 const int fp_move; /* cost of reg,reg fld/fst */
117 const int fp_load[3]; /* cost of loading FP register
118 in SFmode, DFmode and XFmode */
119 const int fp_store[3]; /* cost of storing FP register
120 in SFmode, DFmode and XFmode */
121 const int mmx_move; /* cost of moving MMX register. */
122 const int mmx_load[2]; /* cost of loading MMX register
123 in SImode and DImode */
124 const int mmx_store[2]; /* cost of storing MMX register
125 in SImode and DImode */
126 const int xmm_move; /* cost of moving XMM register. */
127 const int ymm_move; /* cost of moving XMM register. */
128 const int zmm_move; /* cost of moving XMM register. */
129 const int sse_load[5]; /* cost of loading SSE register
130 in 32bit, 64bit, 128bit, 256bit and 512bit */
131 const int sse_store[5]; /* cost of storing SSE register
132 in SImode, DImode and TImode. */
133 const int sse_to_integer; /* cost of moving SSE register to integer. */
134 const int integer_to_sse; /* cost of moving integer register to SSE. */
135 const int mask_to_integer; /* cost of moving mask register to integer. */
136 const int integer_to_mask; /* cost of moving integer register to mask. */
137 const int mask_load[3]; /* cost of loading mask registers
138 in QImode, HImode and SImode. */
139 const int mask_store[3]; /* cost of storing mask register
140 in QImode, HImode and SImode. */
141 const int mask_move; /* cost of moving mask register. */
142 } hard_register;
143
144 const int add; /* cost of an add instruction */
145 const int lea; /* cost of a lea instruction */
146 const int shift_var; /* variable shift costs */
147 const int shift_const; /* constant shift costs */
148 const int mult_init[5]; /* cost of starting a multiply
149 in QImode, HImode, SImode, DImode, TImode*/
150 const int mult_bit; /* cost of multiply per each bit set */
151 const int divide[5]; /* cost of a divide/mod
152 in QImode, HImode, SImode, DImode, TImode*/
153 int movsx; /* The cost of movsx operation. */
154 int movzx; /* The cost of movzx operation. */
155 const int large_insn; /* insns larger than this cost more */
156 const int move_ratio; /* The threshold of number of scalar
157 memory-to-memory move insns. */
158 const int clear_ratio; /* The threshold of number of scalar
159 memory clearing insns. */
160 const int int_load[3]; /* cost of loading integer registers
161 in QImode, HImode and SImode relative
162 to reg-reg move (2). */
163 const int int_store[3]; /* cost of storing integer register
164 in QImode, HImode and SImode */
165 const int sse_load[5]; /* cost of loading SSE register
166 in 32bit, 64bit, 128bit, 256bit and 512bit */
167 const int sse_store[5]; /* cost of storing SSE register
168 in 32bit, 64bit, 128bit, 256bit and 512bit */
169 const int sse_unaligned_load[5];/* cost of unaligned load. */
170 const int sse_unaligned_store[5];/* cost of unaligned store. */
171 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */
172 zmm_move;
173 const int sse_to_integer; /* cost of moving SSE register to integer. */
174 const int gather_static, gather_per_elt; /* Cost of gather load is computed
175 as static + per_item * nelts. */
176 const int scatter_static, scatter_per_elt; /* Cost of gather store is
177 computed as static + per_item * nelts. */
178 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
179 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
180 const int prefetch_block; /* bytes moved to cache for prefetch. */
181 const int simultaneous_prefetches; /* number of parallel prefetch
182 operations. */
183 const int branch_cost; /* Default value for BRANCH_COST. */
184 const int fadd; /* cost of FADD and FSUB instructions. */
185 const int fmul; /* cost of FMUL instruction. */
186 const int fdiv; /* cost of FDIV instruction. */
187 const int fabs; /* cost of FABS instruction. */
188 const int fchs; /* cost of FCHS instruction. */
189 const int fsqrt; /* cost of FSQRT instruction. */
190 /* Specify what algorithm
191 to use for stringops on unknown size. */
192 const int sse_op; /* cost of cheap SSE instruction. */
193 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */
194 const int mulss; /* cost of MULSS instructions. */
195 const int mulsd; /* cost of MULSD instructions. */
196 const int fmass; /* cost of FMASS instructions. */
197 const int fmasd; /* cost of FMASD instructions. */
198 const int divss; /* cost of DIVSS instructions. */
199 const int divsd; /* cost of DIVSD instructions. */
200 const int sqrtss; /* cost of SQRTSS instructions. */
201 const int sqrtsd; /* cost of SQRTSD instructions. */
202 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp;
203 /* Specify reassociation width for integer,
204 fp, vector integer and vector fp
205 operations. Generally should correspond
206 to number of instructions executed in
207 parallel. See also
208 ix86_reassociation_width. */
209 struct stringop_algs *memcpy, *memset;
210 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
211 cost model. */
212 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
213 vectorizer cost model. */
214
215 /* The "0:0:8" label alignment specified for some processors generates
216 secondary 8-byte alignment only for those label/jump/loop targets
217 which have primary alignment. */
218 const char *const align_loop; /* Loop alignment. */
219 const char *const align_jump; /* Jump alignment. */
220 const char *const align_label; /* Label alignment. */
221 const char *const align_func; /* Function alignment. */
222};
223
224extern const struct processor_costs *ix86_cost;
225extern const struct processor_costs ix86_size_cost;
226
227#define ix86_cur_cost() \
228 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
229
230/* Macros used in the machine description to test the flags. */
231
232/* configure can arrange to change it. */
233
234#ifndef TARGET_CPU_DEFAULT
235#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
236#endif
237
238#ifndef TARGET_FPMATH_DEFAULT
239#define TARGET_FPMATH_DEFAULT \
240 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
241#endif
242
243#ifndef TARGET_FPMATH_DEFAULT_P
244#define TARGET_FPMATH_DEFAULT_P(x) \
245 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
246#endif
247
248/* If the i387 is disabled or -miamcu is used , then do not return
249 values in it. */
250#define TARGET_FLOAT_RETURNS_IN_80387 \
251 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
252#define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
253 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
254
255/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
256 compile-time constant. */
257#ifdef IN_LIBGCC2
258#undef TARGET_64BIT
259#ifdef __x86_64__
260#define TARGET_64BIT 1
261#else
262#define TARGET_64BIT 0
263#endif
264#else
265#ifndef TARGET_BI_ARCH
266#undef TARGET_64BIT
267#undef TARGET_64BIT_P
268#if TARGET_64BIT_DEFAULT
269#define TARGET_64BIT 1
270#define TARGET_64BIT_P(x) 1
271#else
272#define TARGET_64BIT 0
273#define TARGET_64BIT_P(x) 0
274#endif
275#endif
276#endif
277
278#define HAS_LONG_COND_BRANCH 1
279#define HAS_LONG_UNCOND_BRANCH 1
280
281#define TARGET_CPU_P(CPU) (ix86_tune == PROCESSOR_ ## CPU)
282
283/* Feature tests against the various tunings. */
284enum ix86_tune_indices {
285#undef DEF_TUNE
286#define DEF_TUNE(tune, name, selector) tune,
287#include "x86-tune.def"
288#undef DEF_TUNE
289X86_TUNE_LAST
290};
291
292extern unsigned char ix86_tune_features[X86_TUNE_LAST];
293
294#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
295#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
296#define TARGET_ZERO_EXTEND_WITH_AND \
297 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
298#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
299#define TARGET_BRANCH_PREDICTION_HINTS \
300 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
301#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
302#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
303#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
304#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
305#define TARGET_PARTIAL_FLAG_REG_STALL \
306 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
307#define TARGET_LCP_STALL \
308 ix86_tune_features[X86_TUNE_LCP_STALL]
309#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
310#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
311#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
312#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
313#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
314#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
315#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
316#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
317#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
318#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
319#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
320#define TARGET_PREFER_KNOWN_REP_MOVSB_STOSB \
321 ix86_tune_features[X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB]
322#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
323 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
324#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
325#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
326#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
327#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
328#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
329#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
330#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
331#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
332#define TARGET_INTEGER_DFMODE_MOVES \
333 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
334#define TARGET_PARTIAL_REG_DEPENDENCY \
335 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
336#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
337 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
338#define TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY \
339 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY]
340#define TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY \
341 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY]
342#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
343 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
344#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
345 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
346#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
347 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
348#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
349#define TARGET_SSE_TYPELESS_STORES \
350 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
351#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
352#define TARGET_MEMORY_MISMATCH_STALL \
353 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
354#define TARGET_PROLOGUE_USING_MOVE \
355 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
356#define TARGET_EPILOGUE_USING_MOVE \
357 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
358#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
359#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
360#define TARGET_INTER_UNIT_MOVES_TO_VEC \
361 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
362#define TARGET_INTER_UNIT_MOVES_FROM_VEC \
363 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
364#define TARGET_INTER_UNIT_CONVERSIONS \
365 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
366#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
367#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
368#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
369#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
370#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
371#define TARGET_PAD_SHORT_FUNCTION \
372 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
373#define TARGET_EXT_80387_CONSTANTS \
374 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
375#define TARGET_AVOID_VECTOR_DECODE \
376 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
377#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
378 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
379#define TARGET_SLOW_IMUL_IMM32_MEM \
380 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
381#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
382#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
383#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
384#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
385#define TARGET_USE_VECTOR_FP_CONVERTS \
386 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
387#define TARGET_USE_VECTOR_CONVERTS \
388 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
389#define TARGET_SLOW_PSHUFB \
390 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
391#define TARGET_AVOID_4BYTE_PREFIXES \
392 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
393#define TARGET_USE_GATHER_2PARTS \
394 ix86_tune_features[X86_TUNE_USE_GATHER_2PARTS]
395#define TARGET_USE_GATHER_4PARTS \
396 ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS]
397#define TARGET_USE_GATHER \
398 ix86_tune_features[X86_TUNE_USE_GATHER]
399#define TARGET_FUSE_CMP_AND_BRANCH_32 \
400 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
401#define TARGET_FUSE_CMP_AND_BRANCH_64 \
402 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
403#define TARGET_FUSE_CMP_AND_BRANCH \
404 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
405 : TARGET_FUSE_CMP_AND_BRANCH_32)
406#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
407 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
408#define TARGET_FUSE_ALU_AND_BRANCH \
409 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
410#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
411#define TARGET_AVOID_LEA_FOR_ADDR \
412 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
413#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
414 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
415#define TARGET_AVX256_SPLIT_REGS \
416 ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS]
417#define TARGET_GENERAL_REGS_SSE_SPILL \
418 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
419#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
420 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
421#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
422 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
423#define TARGET_ADJUST_UNROLL \
424 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
425#define TARGET_AVOID_FALSE_DEP_FOR_BMI \
426 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
427#define TARGET_ONE_IF_CONV_INSN \
428 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
429#define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE]
430#define TARGET_EMIT_VZEROUPPER \
431 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
432#define TARGET_EXPAND_ABS \
433 ix86_tune_features[X86_TUNE_EXPAND_ABS]
434#define TARGET_V2DF_REDUCTION_PREFER_HADDPD \
435 ix86_tune_features[X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD]
436#define TARGET_DEST_FALSE_DEP_FOR_GLC \
437 ix86_tune_features[X86_TUNE_DEST_FALSE_DEP_FOR_GLC]
438
439/* Feature tests against the various architecture variations. */
440enum ix86_arch_indices {
441 X86_ARCH_CMOV,
442 X86_ARCH_CMPXCHG,
443 X86_ARCH_CMPXCHG8B,
444 X86_ARCH_XADD,
445 X86_ARCH_BSWAP,
446
447 X86_ARCH_LAST
448};
449
450extern unsigned char ix86_arch_features[X86_ARCH_LAST];
451
452#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
453#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
454#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
455#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
456#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
457
458/* For sane SSE instruction set generation we need fcomi instruction.
459 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
460 expands to a sequence that includes conditional move. */
461#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
462
463#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
464
465extern unsigned char ix86_prefetch_sse;
466#define TARGET_PREFETCH_SSE ix86_prefetch_sse
467
468#define ASSEMBLER_DIALECT (ix86_asm_dialect)
469
470#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
471#define TARGET_MIX_SSE_I387 \
472 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
473
474#define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
475#define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE)
476#define TARGET_HARD_XF_REGS (TARGET_80387)
477
478#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
479#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
480#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
481#define TARGET_SUN_TLS 0
482
483#ifndef TARGET_64BIT_DEFAULT
484#define TARGET_64BIT_DEFAULT 0
485#endif
486#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
487#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
488#endif
489
490#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
491#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
492
493/* Fence to use after loop using storent. */
494
495extern GTY(()) tree x86_mfence;
496#define FENCE_FOLLOWING_MOVNT x86_mfence
497
498/* Once GDB has been enhanced to deal with functions without frame
499 pointers, we can change this to allow for elimination of
500 the frame pointer in leaf functions. */
501#define TARGET_DEFAULT 0
502
503/* Extra bits to force. */
504#define TARGET_SUBTARGET_DEFAULT 0
505#define TARGET_SUBTARGET_ISA_DEFAULT 0
506
507/* Extra bits to force on w/ 32-bit mode. */
508#define TARGET_SUBTARGET32_DEFAULT 0
509#define TARGET_SUBTARGET32_ISA_DEFAULT 0
510
511/* Extra bits to force on w/ 64-bit mode. */
512#define TARGET_SUBTARGET64_DEFAULT 0
513/* Enable MMX, SSE and SSE2 by default. */
514#define TARGET_SUBTARGET64_ISA_DEFAULT \
515 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
516
517/* Replace MACH-O, ifdefs by in-line tests, where possible.
518 (a) Macros defined in config/i386/darwin.h */
519#define TARGET_MACHO 0
520#define TARGET_MACHO_SYMBOL_STUBS 0
521#define MACHOPIC_ATT_STUB 0
522/* (b) Macros defined in config/darwin.h */
523#define MACHO_DYNAMIC_NO_PIC_P 0
524#define MACHOPIC_INDIRECT 0
525#define MACHOPIC_PURE 0
526
527/* For the RDOS */
528#define TARGET_RDOS 0
529
530/* For the Windows 64-bit ABI. */
531#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
532
533/* For the Windows 32-bit ABI. */
534#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
535
536/* This is re-defined by cygming.h. */
537#define TARGET_SEH 0
538
539/* The default abi used by target. */
540#define DEFAULT_ABI SYSV_ABI
541
542/* The default TLS segment register used by target. */
543#define DEFAULT_TLS_SEG_REG \
544 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS)
545
546/* Subtargets may reset this to 1 in order to enable 96-bit long double
547 with the rounding mode forced to 53 bits. */
548#define TARGET_96_ROUND_53_LONG_DOUBLE 0
549
550#ifndef SUBTARGET_DRIVER_SELF_SPECS
551# define SUBTARGET_DRIVER_SELF_SPECS ""
552#endif
553
554#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS
555
556/* -march=native handling only makes sense with compiler running on
557 an x86 or x86_64 chip. If changing this condition, also change
558 the condition in driver-i386.cc. */
559#if defined(__i386__) || defined(__x86_64__)
560/* In driver-i386.cc. */
561extern const char *host_detect_local_cpu (int argc, const char **argv);
562#define EXTRA_SPEC_FUNCTIONS \
563 { "local_cpu_detect", host_detect_local_cpu },
564#define HAVE_LOCAL_CPU_DETECT
565#endif
566
567#if TARGET_64BIT_DEFAULT
568#define OPT_ARCH64 "!m32"
569#define OPT_ARCH32 "m32"
570#else
571#define OPT_ARCH64 "m64|mx32"
572#define OPT_ARCH32 "m64|mx32:;"
573#endif
574
575/* Support for configure-time defaults of some command line options.
576 The order here is important so that -march doesn't squash the
577 tune or cpu values. */
578#define OPTION_DEFAULT_SPECS \
579 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
580 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
581 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
582 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
583 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
584 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
585 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
586 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
587 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
588
589/* Specs for the compiler proper */
590
591#ifndef CC1_CPU_SPEC
592#define CC1_CPU_SPEC_1 ""
593
594#ifndef HAVE_LOCAL_CPU_DETECT
595#define CC1_CPU_SPEC CC1_CPU_SPEC_1
596#else
597#define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}"
598#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
599"%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \
600 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \
601%{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}"
602#endif
603#endif
604
605/* Target CPU builtins. */
606#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
607
608/* Target Pragmas. */
609#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
610
611/* Target hooks for D language. */
612#define TARGET_D_CPU_VERSIONS ix86_d_target_versions
613#define TARGET_D_REGISTER_CPU_TARGET_INFO ix86_d_register_target_info
614#define TARGET_D_HAS_STDCALL_CONVENTION ix86_d_has_stdcall_convention
615
616#ifndef CC1_SPEC
617#define CC1_SPEC "%(cc1_cpu) "
618#endif
619
620/* This macro defines names of additional specifications to put in the
621 specs that can be used in various specifications like CC1_SPEC. Its
622 definition is an initializer with a subgrouping for each command option.
623
624 Each subgrouping contains a string constant, that defines the
625 specification name, and a string constant that used by the GCC driver
626 program.
627
628 Do not define this macro if it does not need to do anything. */
629
630#ifndef SUBTARGET_EXTRA_SPECS
631#define SUBTARGET_EXTRA_SPECS
632#endif
633
634#define EXTRA_SPECS \
635 { "cc1_cpu", CC1_CPU_SPEC }, \
636 SUBTARGET_EXTRA_SPECS
637
638
639/* Whether to allow x87 floating-point arithmetic on MODE (one of
640 SFmode, DFmode and XFmode) in the current excess precision
641 configuration. */
642#define X87_ENABLE_ARITH(MODE) \
643 (ix86_unsafe_math_optimizations \
644 || ix86_excess_precision == EXCESS_PRECISION_FAST \
645 || (MODE) == XFmode)
646
647/* Likewise, whether to allow direct conversions from integer mode
648 IMODE (HImode, SImode or DImode) to MODE. */
649#define X87_ENABLE_FLOAT(MODE, IMODE) \
650 (ix86_unsafe_math_optimizations \
651 || ix86_excess_precision == EXCESS_PRECISION_FAST \
652 || (MODE) == XFmode \
653 || ((MODE) == DFmode && (IMODE) == SImode) \
654 || (IMODE) == HImode)
655
656/* target machine storage layout */
657
658#define SHORT_TYPE_SIZE 16
659#define INT_TYPE_SIZE 32
660#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
661#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
662#define LONG_LONG_TYPE_SIZE 64
663#define FLOAT_TYPE_SIZE 32
664#define DOUBLE_TYPE_SIZE 64
665#define LONG_DOUBLE_TYPE_SIZE \
666 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))
667
668#define WIDEST_HARDWARE_FP_SIZE 80
669
670#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
671#define MAX_BITS_PER_WORD 64
672#else
673#define MAX_BITS_PER_WORD 32
674#endif
675
676/* Define this if most significant byte of a word is the lowest numbered. */
677/* That is true on the 80386. */
678
679#define BITS_BIG_ENDIAN 0
680
681/* Define this if most significant byte of a word is the lowest numbered. */
682/* That is not true on the 80386. */
683#define BYTES_BIG_ENDIAN 0
684
685/* Define this if most significant word of a multiword number is the lowest
686 numbered. */
687/* Not true for 80386 */
688#define WORDS_BIG_ENDIAN 0
689
690/* Width of a word, in units (bytes). */
691#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
692
693#ifndef IN_LIBGCC2
694#define MIN_UNITS_PER_WORD 4
695#endif
696
697/* Allocation boundary (in *bits*) for storing arguments in argument list. */
698#define PARM_BOUNDARY BITS_PER_WORD
699
700/* Boundary (in *bits*) on which stack pointer should be aligned. */
701#define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD)
702
703/* Stack boundary of the main function guaranteed by OS. */
704#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
705
706/* Minimum stack boundary. */
707#define MIN_STACK_BOUNDARY BITS_PER_WORD
708
709/* Boundary (in *bits*) on which the stack pointer prefers to be
710 aligned; the compiler cannot rely on having this alignment. */
711#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
712
713/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
714 both 32bit and 64bit, to support codes that need 128 bit stack
715 alignment for SSE instructions, but can't realign the stack. */
716#define PREFERRED_STACK_BOUNDARY_DEFAULT \
717 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
718
719/* 1 if -mstackrealign should be turned on by default. It will
720 generate an alternate prologue and epilogue that realigns the
721 runtime stack if nessary. This supports mixing codes that keep a
722 4-byte aligned stack, as specified by i386 psABI, with codes that
723 need a 16-byte aligned stack, as required by SSE instructions. */
724#define STACK_REALIGN_DEFAULT 0
725
726/* Boundary (in *bits*) on which the incoming stack is aligned. */
727#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
728
729/* According to Windows x64 software convention, the maximum stack allocatable
730 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
731 instructions allowed to adjust the stack pointer in the epilog, forcing the
732 use of frame pointer for frames larger than 2 GB. This theorical limit
733 is reduced by 256, an over-estimated upper bound for the stack use by the
734 prologue.
735 We define only one threshold for both the prolog and the epilog. When the
736 frame size is larger than this threshold, we allocate the area to save SSE
737 regs, then save them, and then allocate the remaining. There is no SEH
738 unwind info for this later allocation. */
739#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
740
741/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
742 mandatory for the 64-bit ABI, and may or may not be true for other
743 operating systems. */
744#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
745
746/* Minimum allocation boundary for the code of a function. */
747#define FUNCTION_BOUNDARY 8
748
749/* C++ stores the virtual bit in the lowest bit of function pointers. */
750#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
751
752/* Minimum size in bits of the largest boundary to which any
753 and all fundamental data types supported by the hardware
754 might need to be aligned. No data type wants to be aligned
755 rounder than this.
756
757 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
758 and Pentium Pro XFmode values at 128 bit boundaries.
759
760 When increasing the maximum, also update
761 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
762
763#define BIGGEST_ALIGNMENT \
764 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)))
765
766/* Maximum stack alignment. */
767#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
768
769/* Alignment value for attribute ((aligned)). It is a constant since
770 it is the part of the ABI. We shouldn't change it with -mavx. */
771#define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
772
773/* Decide whether a variable of mode MODE should be 128 bit aligned. */
774#define ALIGN_MODE_128(MODE) \
775 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
776
777/* The published ABIs say that doubles should be aligned on word
778 boundaries, so lower the alignment for structure fields unless
779 -malign-double is set. */
780
781/* ??? Blah -- this macro is used directly by libobjc. Since it
782 supports no vector modes, cut out the complexity and fall back
783 on BIGGEST_FIELD_ALIGNMENT. */
784#ifdef IN_TARGET_LIBS
785#ifdef __x86_64__
786#define BIGGEST_FIELD_ALIGNMENT 128
787#else
788#define BIGGEST_FIELD_ALIGNMENT 32
789#endif
790#else
791#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
792 x86_field_alignment ((TYPE), (COMPUTED))
793#endif
794
795/* If defined, a C expression to compute the alignment for a static
796 variable. TYPE is the data type, and ALIGN is the alignment that
797 the object would ordinarily have. The value of this macro is used
798 instead of that alignment to align the object.
799
800 If this macro is not defined, then ALIGN is used.
801
802 One use of this macro is to increase alignment of medium-size
803 data to make it all fit in fewer cache lines. Another is to
804 cause character arrays to be word-aligned so that `strcpy' calls
805 that copy constants to character arrays can be done inline. */
806
807#define DATA_ALIGNMENT(TYPE, ALIGN) \
808 ix86_data_alignment ((TYPE), (ALIGN), true)
809
810/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
811 some alignment increase, instead of optimization only purposes. E.g.
812 AMD x86-64 psABI says that variables with array type larger than 15 bytes
813 must be aligned to 16 byte boundaries.
814
815 If this macro is not defined, then ALIGN is used. */
816
817#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
818 ix86_data_alignment ((TYPE), (ALIGN), false)
819
820/* If defined, a C expression to compute the alignment for a local
821 variable. TYPE is the data type, and ALIGN is the alignment that
822 the object would ordinarily have. The value of this macro is used
823 instead of that alignment to align the object.
824
825 If this macro is not defined, then ALIGN is used.
826
827 One use of this macro is to increase alignment of medium-size
828 data to make it all fit in fewer cache lines. */
829
830#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
831 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
832
833/* If defined, a C expression to compute the alignment for stack slot.
834 TYPE is the data type, MODE is the widest mode available, and ALIGN
835 is the alignment that the slot would ordinarily have. The value of
836 this macro is used instead of that alignment to align the slot.
837
838 If this macro is not defined, then ALIGN is used when TYPE is NULL,
839 Otherwise, LOCAL_ALIGNMENT will be used.
840
841 One use of this macro is to set alignment of stack slot to the
842 maximum alignment of all possible modes which the slot may have. */
843
844#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
845 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
846
847/* If defined, a C expression to compute the alignment for a local
848 variable DECL.
849
850 If this macro is not defined, then
851 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
852
853 One use of this macro is to increase alignment of medium-size
854 data to make it all fit in fewer cache lines. */
855
856#define LOCAL_DECL_ALIGNMENT(DECL) \
857 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
858
859/* If defined, a C expression to compute the minimum required alignment
860 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
861 MODE, assuming normal alignment ALIGN.
862
863 If this macro is not defined, then (ALIGN) will be used. */
864
865#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
866 ix86_minimum_alignment ((EXP), (MODE), (ALIGN))
867
868
869/* Set this nonzero if move instructions will actually fail to work
870 when given unaligned data. */
871#define STRICT_ALIGNMENT 0
872
873/* If bit field type is int, don't let it cross an int,
874 and give entire struct the alignment of an int. */
875/* Required on the 386 since it doesn't have bit-field insns. */
876#define PCC_BITFIELD_TYPE_MATTERS 1
877
878/* Standard register usage. */
879
880/* This processor has special stack-like registers. See reg-stack.cc
881 for details. */
882
883#define STACK_REGS
884
885#define IS_STACK_MODE(MODE) \
886 (X87_FLOAT_MODE_P (MODE) \
887 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
888 || TARGET_MIX_SSE_I387))
889
890/* Number of actual hardware registers.
891 The hardware registers are assigned numbers for the compiler
892 from 0 to just below FIRST_PSEUDO_REGISTER.
893 All registers that the compiler knows about must be given numbers,
894 even those that are not normally considered general registers.
895
896 In the 80386 we give the 8 general purpose registers the numbers 0-7.
897 We number the floating point registers 8-15.
898 Note that registers 0-7 can be accessed as a short or int,
899 while only 0-3 may be used with byte `mov' instructions.
900
901 Reg 16 does not correspond to any hardware register, but instead
902 appears in the RTL as an argument pointer prior to reload, and is
903 eliminated during reloading in favor of either the stack or frame
904 pointer. */
905
906#define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
907
908/* Number of hardware registers that go into the DWARF-2 unwind info.
909 If not defined, equals FIRST_PSEUDO_REGISTER. */
910
911#define DWARF_FRAME_REGISTERS 17
912
913/* 1 for registers that have pervasive standard uses
914 and are not available for the register allocator.
915 On the 80386, the stack pointer is such, as is the arg pointer.
916
917 REX registers are disabled for 32bit targets in
918 TARGET_CONDITIONAL_REGISTER_USAGE. */
919
920#define FIXED_REGISTERS \
921/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
922{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
923/*arg,flags,fpsr,frame*/ \
924 1, 1, 1, 1, \
925/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
926 0, 0, 0, 0, 0, 0, 0, 0, \
927/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
928 0, 0, 0, 0, 0, 0, 0, 0, \
929/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
930 0, 0, 0, 0, 0, 0, 0, 0, \
931/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
932 0, 0, 0, 0, 0, 0, 0, 0, \
933/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
934 0, 0, 0, 0, 0, 0, 0, 0, \
935/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
936 0, 0, 0, 0, 0, 0, 0, 0, \
937/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
938 0, 0, 0, 0, 0, 0, 0, 0 }
939
940/* 1 for registers not available across function calls.
941 These must include the FIXED_REGISTERS and also any
942 registers that can be used without being saved.
943 The latter must include the registers where values are returned
944 and the register where structure-value addresses are passed.
945 Aside from that, you can include as many other registers as you like.
946
947 Value is set to 1 if the register is call used unconditionally.
948 Bit one is set if the register is call used on TARGET_32BIT ABI.
949 Bit two is set if the register is call used on TARGET_64BIT ABI.
950 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
951
952 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
953
954#define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \
955 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
956
957#define CALL_USED_REGISTERS \
958/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
959{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
960/*arg,flags,fpsr,frame*/ \
961 1, 1, 1, 1, \
962/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
963 1, 1, 1, 1, 1, 1, 6, 6, \
964/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
965 1, 1, 1, 1, 1, 1, 1, 1, \
966/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
967 1, 1, 1, 1, 2, 2, 2, 2, \
968/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
969 6, 6, 6, 6, 6, 6, 6, 6, \
970/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
971 1, 1, 1, 1, 1, 1, 1, 1, \
972/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
973 1, 1, 1, 1, 1, 1, 1, 1, \
974 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
975 1, 1, 1, 1, 1, 1, 1, 1 }
976
977/* Order in which to allocate registers. Each register must be
978 listed once, even those in FIXED_REGISTERS. List frame pointer
979 late and fixed registers last. Note that, in general, we prefer
980 registers listed in CALL_USED_REGISTERS, keeping the others
981 available for storage of persistent values.
982
983 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
984 so this is just empty initializer for array. */
985
986#define REG_ALLOC_ORDER \
987{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
988 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
989 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
990 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
991 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
992
993/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
994 to be rearranged based on a particular function. When using sse math,
995 we want to allocate SSE before x87 registers and vice versa. */
996
997#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
998
999
1000#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1001
1002#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1003 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \
1004 && GENERAL_REGNO_P (REGNO) \
1005 && ((MODE) == XFmode || (MODE) == XCmode))
1006
1007#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1008
1009#define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE)
1010
1011#define VALID_AVX256_REG_MODE(MODE) \
1012 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1013 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1014 || (MODE) == V4DFmode || (MODE) == V16HFmode)
1015
1016#define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1017 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1018
1019#define VALID_AVX512F_SCALAR_MODE(MODE) \
1020 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \
1021 || (MODE) == SFmode)
1022
1023#define VALID_AVX512FP16_SCALAR_MODE(MODE) \
1024 ((MODE) == HImode || (MODE) == HFmode)
1025
1026#define VALID_AVX512F_REG_MODE(MODE) \
1027 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1028 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1029 || (MODE) == V4TImode || (MODE) == V32HFmode)
1030
1031#define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1032 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1033
1034#define VALID_AVX512VL_128_REG_MODE(MODE) \
1035 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1036 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1037 || (MODE) == TFmode || (MODE) == V1TImode || (MODE) == V8HFmode \
1038 || (MODE) == TImode)
1039
1040#define VALID_AVX512FP16_REG_MODE(MODE) \
1041 ((MODE) == V8HFmode || (MODE) == V16HFmode || (MODE) == V32HFmode \
1042 || (MODE) == V2HFmode)
1043
1044#define VALID_SSE2_REG_MODE(MODE) \
1045 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1046 || (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \
1047 || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
1048 || (MODE) == V2DImode || (MODE) == V2QImode || (MODE) == DFmode \
1049 || (MODE) == HFmode || (MODE) == BFmode)
1050
1051#define VALID_SSE_REG_MODE(MODE) \
1052 ((MODE) == V1TImode || (MODE) == TImode \
1053 || (MODE) == V4SFmode || (MODE) == V4SImode \
1054 || (MODE) == SFmode || (MODE) == TFmode || (MODE) == TDmode)
1055
1056#define VALID_MMX_REG_MODE_3DNOW(MODE) \
1057 ((MODE) == V2SFmode || (MODE) == SFmode)
1058
1059/* To match ia32 psABI, V4HFmode should be added here. */
1060#define VALID_MMX_REG_MODE(MODE) \
1061 ((MODE) == V1DImode || (MODE) == DImode \
1062 || (MODE) == V2SImode || (MODE) == SImode \
1063 || (MODE) == V4HImode || (MODE) == V8QImode \
1064 || (MODE) == V4HFmode)
1065
1066#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1067
1068#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1069
1070#define VALID_FP_MODE_P(MODE) \
1071 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1072 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)
1073
1074#define VALID_INT_MODE_P(MODE) \
1075 ((MODE) == QImode || (MODE) == HImode \
1076 || (MODE) == SImode || (MODE) == DImode \
1077 || (MODE) == CQImode || (MODE) == CHImode \
1078 || (MODE) == CSImode || (MODE) == CDImode \
1079 || (MODE) == SDmode || (MODE) == DDmode \
1080 || (MODE) == HFmode || (MODE) == HCmode || (MODE) == BFmode \
1081 || (MODE) == V2HImode || (MODE) == V2HFmode \
1082 || (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \
1083 || (TARGET_64BIT \
1084 && ((MODE) == TImode || (MODE) == CTImode \
1085 || (MODE) == TFmode || (MODE) == TCmode \
1086 || (MODE) == V8QImode || (MODE) == V4HImode \
1087 || (MODE) == V2SImode || (MODE) == TDmode)))
1088
1089/* Return true for modes passed in SSE registers. */
1090#define SSE_REG_MODE_P(MODE) \
1091 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1092 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1093 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1094 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1095 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1096 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1097 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1098 || (MODE) == V16SFmode || (MODE) == V32HFmode || (MODE) == V16HFmode \
1099 || (MODE) == V8HFmode)
1100
1101#define X87_FLOAT_MODE_P(MODE) \
1102 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1103
1104#define SSE_FLOAT_MODE_P(MODE) \
1105 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1106
1107#define SSE_FLOAT_MODE_SSEMATH_OR_HF_P(MODE) \
1108 ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
1109 || (TARGET_AVX512FP16 && (MODE) == HFmode))
1110
1111#define FMA4_VEC_FLOAT_MODE_P(MODE) \
1112 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1113 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1114
1115#define VALID_BCST_MODE_P(MODE) \
1116 ((MODE) == SFmode || (MODE) == DFmode \
1117 || (MODE) == SImode || (MODE) == DImode \
1118 || (MODE) == HFmode)
1119
1120/* It is possible to write patterns to move flags; but until someone
1121 does it, */
1122#define AVOID_CCMODE_COPIES
1123
1124/* Specify the modes required to caller save a given hard regno.
1125 We do this on i386 to prevent flags from being saved at all.
1126
1127 Kill any attempts to combine saving of modes. */
1128
1129#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1130 (CC_REGNO_P (REGNO) ? VOIDmode \
1131 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1132 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \
1133 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \
1134 && TARGET_PARTIAL_REG_STALL) \
1135 || MASK_REGNO_P (REGNO)) ? SImode \
1136 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \
1137 || MASK_REGNO_P (REGNO)) ? SImode \
1138 : (MODE))
1139
1140/* Specify the registers used for certain standard purposes.
1141 The values of these macros are register numbers. */
1142
1143/* on the 386 the pc register is %eip, and is not usable as a general
1144 register. The ordinary mov instructions won't work */
1145/* #define PC_REGNUM */
1146
1147/* Base register for access to arguments of the function. */
1148#define ARG_POINTER_REGNUM ARGP_REG
1149
1150/* Register to use for pushing function arguments. */
1151#define STACK_POINTER_REGNUM SP_REG
1152
1153/* Base register for access to local variables of the function. */
1154#define FRAME_POINTER_REGNUM FRAME_REG
1155#define HARD_FRAME_POINTER_REGNUM BP_REG
1156
1157#define FIRST_INT_REG AX_REG
1158#define LAST_INT_REG SP_REG
1159
1160#define FIRST_QI_REG AX_REG
1161#define LAST_QI_REG BX_REG
1162
1163/* First & last stack-like regs */
1164#define FIRST_STACK_REG ST0_REG
1165#define LAST_STACK_REG ST7_REG
1166
1167#define FIRST_SSE_REG XMM0_REG
1168#define LAST_SSE_REG XMM7_REG
1169
1170#define FIRST_MMX_REG MM0_REG
1171#define LAST_MMX_REG MM7_REG
1172
1173#define FIRST_REX_INT_REG R8_REG
1174#define LAST_REX_INT_REG R15_REG
1175
1176#define FIRST_REX_SSE_REG XMM8_REG
1177#define LAST_REX_SSE_REG XMM15_REG
1178
1179#define FIRST_EXT_REX_SSE_REG XMM16_REG
1180#define LAST_EXT_REX_SSE_REG XMM31_REG
1181
1182#define FIRST_MASK_REG MASK0_REG
1183#define LAST_MASK_REG MASK7_REG
1184
1185/* Override this in other tm.h files to cope with various OS lossage
1186 requiring a frame pointer. */
1187#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1188#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1189#endif
1190
1191/* Define the shadow offset for asan. Other OS's can override in the
1192 respective tm.h files. */
1193#ifndef SUBTARGET_SHADOW_OFFSET
1194#define SUBTARGET_SHADOW_OFFSET \
1195 (TARGET_LP64 ? HOST_WIDE_INT_C (0x7fff8000) : HOST_WIDE_INT_1 << 29)
1196#endif
1197
1198/* Make sure we can access arbitrary call frames. */
1199#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1200
1201/* Register to hold the addressing base for position independent
1202 code access to data items. We don't use PIC pointer for 64bit
1203 mode. Define the regnum to dummy value to prevent gcc from
1204 pessimizing code dealing with EBX.
1205
1206 To avoid clobbering a call-saved register unnecessarily, we renumber
1207 the pic register when possible. The change is visible after the
1208 prologue has been emitted. */
1209
1210#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
1211
1212#define PIC_OFFSET_TABLE_REGNUM \
1213 (ix86_use_pseudo_pic_reg () \
1214 ? (pic_offset_table_rtx \
1215 ? INVALID_REGNUM \
1216 : REAL_PIC_OFFSET_TABLE_REGNUM) \
1217 : INVALID_REGNUM)
1218
1219#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1220
1221/* This is overridden by <cygwin.h>. */
1222#define MS_AGGREGATE_RETURN 0
1223
1224#define KEEP_AGGREGATE_RETURN_POINTER 0
1225
1226/* Define the classes of registers for register constraints in the
1227 machine description. Also define ranges of constants.
1228
1229 One of the classes must always be named ALL_REGS and include all hard regs.
1230 If there is more than one class, another class must be named NO_REGS
1231 and contain no registers.
1232
1233 The name GENERAL_REGS must be the name of a class (or an alias for
1234 another name such as ALL_REGS). This is the class of registers
1235 that is allowed by "g" or "r" in a register constraint.
1236 Also, registers outside this class are allocated only when
1237 instructions express preferences for them.
1238
1239 The classes must be numbered in nondecreasing order; that is,
1240 a larger-numbered class must never be contained completely
1241 in a smaller-numbered class. This is why CLOBBERED_REGS class
1242 is listed early, even though in 64-bit mode it contains more
1243 registers than just %eax, %ecx, %edx.
1244
1245 For any two classes, it is very desirable that there be another
1246 class that represents their union.
1247
1248 The flags and fpsr registers are in no class. */
1249
1250enum reg_class
1251{
1252 NO_REGS,
1253 AREG, DREG, CREG, BREG, SIREG, DIREG,
1254 AD_REGS, /* %eax/%edx for DImode */
1255 CLOBBERED_REGS, /* call-clobbered integer registers */
1256 Q_REGS, /* %eax %ebx %ecx %edx */
1257 NON_Q_REGS, /* %esi %edi %ebp %esp */
1258 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */
1259 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1260 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1261 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1262 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1263 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1264 FLOAT_REGS,
1265 SSE_FIRST_REG,
1266 NO_REX_SSE_REGS,
1267 SSE_REGS,
1268 ALL_SSE_REGS,
1269 MMX_REGS,
1270 FLOAT_SSE_REGS,
1271 FLOAT_INT_REGS,
1272 INT_SSE_REGS,
1273 FLOAT_INT_SSE_REGS,
1274 MASK_REGS,
1275 ALL_MASK_REGS,
1276 INT_MASK_REGS,
1277 ALL_REGS,
1278 LIM_REG_CLASSES
1279};
1280
1281#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1282
1283#define INTEGER_CLASS_P(CLASS) \
1284 reg_class_subset_p ((CLASS), GENERAL_REGS)
1285#define FLOAT_CLASS_P(CLASS) \
1286 reg_class_subset_p ((CLASS), FLOAT_REGS)
1287#define SSE_CLASS_P(CLASS) \
1288 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1289#define INT_SSE_CLASS_P(CLASS) \
1290 reg_class_subset_p ((CLASS), INT_SSE_REGS)
1291#define MMX_CLASS_P(CLASS) \
1292 ((CLASS) == MMX_REGS)
1293#define MASK_CLASS_P(CLASS) \
1294 reg_class_subset_p ((CLASS), ALL_MASK_REGS)
1295#define MAYBE_INTEGER_CLASS_P(CLASS) \
1296 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1297#define MAYBE_FLOAT_CLASS_P(CLASS) \
1298 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1299#define MAYBE_SSE_CLASS_P(CLASS) \
1300 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1301#define MAYBE_MMX_CLASS_P(CLASS) \
1302 reg_classes_intersect_p ((CLASS), MMX_REGS)
1303#define MAYBE_MASK_CLASS_P(CLASS) \
1304 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS)
1305
1306#define Q_CLASS_P(CLASS) \
1307 reg_class_subset_p ((CLASS), Q_REGS)
1308
1309#define MAYBE_NON_Q_CLASS_P(CLASS) \
1310 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1311
1312/* Give names of register classes as strings for dump file. */
1313
1314#define REG_CLASS_NAMES \
1315{ "NO_REGS", \
1316 "AREG", "DREG", "CREG", "BREG", \
1317 "SIREG", "DIREG", \
1318 "AD_REGS", \
1319 "CLOBBERED_REGS", \
1320 "Q_REGS", "NON_Q_REGS", \
1321 "TLS_GOTBASE_REGS", \
1322 "INDEX_REGS", \
1323 "LEGACY_REGS", \
1324 "GENERAL_REGS", \
1325 "FP_TOP_REG", "FP_SECOND_REG", \
1326 "FLOAT_REGS", \
1327 "SSE_FIRST_REG", \
1328 "NO_REX_SSE_REGS", \
1329 "SSE_REGS", \
1330 "ALL_SSE_REGS", \
1331 "MMX_REGS", \
1332 "FLOAT_SSE_REGS", \
1333 "FLOAT_INT_REGS", \
1334 "INT_SSE_REGS", \
1335 "FLOAT_INT_SSE_REGS", \
1336 "MASK_REGS", \
1337 "ALL_MASK_REGS", \
1338 "INT_MASK_REGS", \
1339 "ALL_REGS" }
1340
1341/* Define which registers fit in which classes. This is an initializer
1342 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1343
1344 Note that CLOBBERED_REGS are calculated by
1345 TARGET_CONDITIONAL_REGISTER_USAGE. */
1346
1347#define REG_CLASS_CONTENTS \
1348{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
1349 { 0x01, 0x0, 0x0 }, /* AREG */ \
1350 { 0x02, 0x0, 0x0 }, /* DREG */ \
1351 { 0x04, 0x0, 0x0 }, /* CREG */ \
1352 { 0x08, 0x0, 0x0 }, /* BREG */ \
1353 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1354 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1355 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1356 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1357 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1358 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
1359 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1360 { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
1361 { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
1362 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \
1363 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1364 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1365 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1366 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1367 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
1368 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
1369 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
1370{ 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
1371 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
1372 { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \
1373 { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \
1374 { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \
1375 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
1376 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
1377 { 0x900ff, 0xff0, 0xff0 }, /* INT_MASK_REGS */ \
1378{ 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \
1379}
1380
1381/* The same information, inverted:
1382 Return the class number of the smallest class containing
1383 reg number REGNO. This could be a conditional expression
1384 or could index an array. */
1385
1386#define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)])
1387
1388/* When this hook returns true for MODE, the compiler allows
1389 registers explicitly used in the rtl to be used as spill registers
1390 but prevents the compiler from extending the lifetime of these
1391 registers. */
1392#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1393
1394#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1395#define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
1396
1397#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
1398#define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG))
1399
1400#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1401#define REX_INT_REGNO_P(N) \
1402 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1403
1404#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1405#define GENERAL_REGNO_P(N) \
1406 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
1407
1408#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1409#define ANY_QI_REGNO_P(N) \
1410 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1411
1412#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1413#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1414
1415#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1416#define SSE_REGNO_P(N) \
1417 (LEGACY_SSE_REGNO_P (N) \
1418 || REX_SSE_REGNO_P (N) \
1419 || EXT_REX_SSE_REGNO_P (N))
1420
1421#define LEGACY_SSE_REGNO_P(N) \
1422 IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG)
1423
1424#define REX_SSE_REGNO_P(N) \
1425 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1426
1427#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
1428
1429#define EXT_REX_SSE_REGNO_P(N) \
1430 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1431
1432#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1433#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1434
1435#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1436#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1437#define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0)
1438
1439#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1440#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1441
1442#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1443#define CC_REGNO_P(X) ((X) == FLAGS_REG)
1444
1445#define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1446#define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1447 || (N) == XMM4_REG \
1448 || (N) == XMM8_REG \
1449 || (N) == XMM12_REG \
1450 || (N) == XMM16_REG \
1451 || (N) == XMM20_REG \
1452 || (N) == XMM24_REG \
1453 || (N) == XMM28_REG)
1454
1455/* First floating point reg */
1456#define FIRST_FLOAT_REG FIRST_STACK_REG
1457#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1458
1459#define GET_SSE_REGNO(N) \
1460 ((N) < 8 ? FIRST_SSE_REG + (N) \
1461 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \
1462 : FIRST_EXT_REX_SSE_REG + (N) - 16)
1463
1464/* The class value for index registers, and the one for base regs. */
1465
1466#define INDEX_REG_CLASS INDEX_REGS
1467#define BASE_REG_CLASS GENERAL_REGS
1468
1469/* Stack layout; function entry, exit and calling. */
1470
1471/* Define this if pushing a word on the stack
1472 makes the stack pointer a smaller address. */
1473#define STACK_GROWS_DOWNWARD 1
1474
1475/* Define this to nonzero if the nominal address of the stack frame
1476 is at the high-address end of the local variables;
1477 that is, each additional local variable allocated
1478 goes at a more negative offset in the frame. */
1479#define FRAME_GROWS_DOWNWARD 1
1480
1481#define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES)
1482
1483/* If defined, the maximum amount of space required for outgoing arguments
1484 will be computed and placed into the variable `crtl->outgoing_args_size'.
1485 No space will be pushed onto the stack for each call; instead, the
1486 function prologue should increase the stack frame size by this amount.
1487
1488 In 32bit mode enabling argument accumulation results in about 5% code size
1489 growth because move instructions are less compact than push. In 64bit
1490 mode the difference is less drastic but visible.
1491
1492 FIXME: Unlike earlier implementations, the size of unwind info seems to
1493 actually grow with accumulation. Is that because accumulated args
1494 unwind info became unnecesarily bloated?
1495
1496 With the 64-bit MS ABI, we can generate correct code with or without
1497 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
1498 generated without accumulated args is terrible.
1499
1500 If stack probes are required, the space used for large function
1501 arguments on the stack must also be probed, so enable
1502 -maccumulate-outgoing-args so this happens in the prologue.
1503
1504 We must use argument accumulation in interrupt function if stack
1505 may be realigned to avoid DRAP. */
1506
1507#define ACCUMULATE_OUTGOING_ARGS \
1508 ((TARGET_ACCUMULATE_OUTGOING_ARGS \
1509 && optimize_function_for_speed_p (cfun)) \
1510 || (cfun->machine->func_type != TYPE_NORMAL \
1511 && crtl->stack_realign_needed) \
1512 || TARGET_STACK_PROBE \
1513 || TARGET_64BIT_MS_ABI \
1514 || (TARGET_MACHO && crtl->profile))
1515
1516/* We want the stack and args grow in opposite directions, even if
1517 targetm.calls.push_argument returns false. */
1518#define PUSH_ARGS_REVERSED 1
1519
1520/* Offset of first parameter from the argument pointer register value. */
1521#define FIRST_PARM_OFFSET(FNDECL) 0
1522
1523/* Define this macro if functions should assume that stack space has been
1524 allocated for arguments even when their values are passed in registers.
1525
1526 The value of this macro is the size, in bytes, of the area reserved for
1527 arguments passed in registers for the function represented by FNDECL.
1528
1529 This space can be allocated by the caller, or be a part of the
1530 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1531 which. */
1532#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1533
1534#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1535 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1536
1537/* Define how to find the value returned by a library function
1538 assuming the value has mode MODE. */
1539
1540#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1541
1542/* Define the size of the result block used for communication between
1543 untyped_call and untyped_return. The block contains a DImode value
1544 followed by the block used by fnsave and frstor. */
1545
1546#define APPLY_RESULT_SIZE (8+108)
1547
1548/* 1 if N is a possible register number for function argument passing. */
1549#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1550
1551/* Define a data type for recording info about an argument list
1552 during the scan of that argument list. This data type should
1553 hold all necessary information about the function itself
1554 and about the args processed so far, enough to enable macros
1555 such as FUNCTION_ARG to determine where the next arg should go. */
1556
1557typedef struct ix86_args {
1558 int words; /* # words passed so far */
1559 int nregs; /* # registers available for passing */
1560 int regno; /* next available register number */
1561 int fastcall; /* fastcall or thiscall calling convention
1562 is used */
1563 int sse_words; /* # sse words passed so far */
1564 int sse_nregs; /* # sse registers available for passing */
1565 int warn_avx512f; /* True when we want to warn
1566 about AVX512F ABI. */
1567 int warn_avx; /* True when we want to warn about AVX ABI. */
1568 int warn_sse; /* True when we want to warn about SSE ABI. */
1569 int warn_mmx; /* True when we want to warn about MMX ABI. */
1570 int warn_empty; /* True when we want to warn about empty classes
1571 passing ABI change. */
1572 int sse_regno; /* next available sse register number */
1573 int mmx_words; /* # mmx words passed so far */
1574 int mmx_nregs; /* # mmx registers available for passing */
1575 int mmx_regno; /* next available mmx register number */
1576 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1577 int caller; /* true if it is caller. */
1578 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1579 SFmode/DFmode arguments should be passed
1580 in SSE registers. Otherwise 0. */
1581 int stdarg; /* Set to 1 if function is stdarg. */
1582 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1583 MS_ABI for ms abi. */
1584 tree decl; /* Callee decl. */
1585} CUMULATIVE_ARGS;
1586
1587/* Initialize a variable CUM of type CUMULATIVE_ARGS
1588 for a call to a function whose data type is FNTYPE.
1589 For a library call, FNTYPE is 0. */
1590
1591#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1592 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1593 (N_NAMED_ARGS) != -1)
1594
1595/* Output assembler code to FILE to increment profiler label # LABELNO
1596 for profiling a function entry. */
1597
1598#define FUNCTION_PROFILER(FILE, LABELNO) \
1599 x86_function_profiler ((FILE), (LABELNO))
1600
1601#define MCOUNT_NAME "_mcount"
1602
1603#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1604
1605#define PROFILE_COUNT_REGISTER "edx"
1606
1607/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1608 the stack pointer does not matter. The value is tested only in
1609 functions that have frame pointers.
1610 No definition is equivalent to always zero. */
1611/* Note on the 386 it might be more efficient not to define this since
1612 we have to restore it ourselves from the frame pointer, in order to
1613 use pop */
1614
1615#define EXIT_IGNORE_STACK 1
1616
1617/* Define this macro as a C expression that is nonzero for registers
1618 used by the epilogue or the `return' pattern. */
1619
1620#define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO)
1621
1622/* Output assembler code for a block containing the constant parts
1623 of a trampoline, leaving space for the variable parts. */
1624
1625/* On the 386, the trampoline contains two instructions:
1626 mov #STATIC,ecx
1627 jmp FUNCTION
1628 The trampoline is generated entirely at runtime. The operand of JMP
1629 is the address of FUNCTION relative to the instruction following the
1630 JMP (which is 5 bytes long). */
1631
1632/* Length in units of the trampoline for entering a nested function. */
1633
1634#define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14)
1635
1636/* Definitions for register eliminations.
1637
1638 This is an array of structures. Each structure initializes one pair
1639 of eliminable registers. The "from" register number is given first,
1640 followed by "to". Eliminations of the same "from" register are listed
1641 in order of preference.
1642
1643 There are two registers that can always be eliminated on the i386.
1644 The frame pointer and the arg pointer can be replaced by either the
1645 hard frame pointer or to the stack pointer, depending upon the
1646 circumstances. The hard frame pointer is not used before reload and
1647 so it is not eligible for elimination. */
1648
1649#define ELIMINABLE_REGS \
1650{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1651 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1652 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1653 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1654
1655/* Define the offset between two registers, one to be eliminated, and the other
1656 its replacement, at the start of a routine. */
1657
1658#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1659 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1660
1661/* Addressing modes, and classification of registers for them. */
1662
1663/* Macros to check register numbers against specific register classes. */
1664
1665/* These assume that REGNO is a hard or pseudo reg number.
1666 They give nonzero only if REGNO is a hard reg of the suitable class
1667 or a pseudo reg currently allocated to a suitable hard reg.
1668 Since they use reg_renumber, they are safe only once reg_renumber
1669 has been allocated, which happens in reginfo.cc during register
1670 allocation. */
1671
1672#define REGNO_OK_FOR_INDEX_P(REGNO) \
1673 ((REGNO) < STACK_POINTER_REGNUM \
1674 || REX_INT_REGNO_P (REGNO) \
1675 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1676 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1677
1678#define REGNO_OK_FOR_BASE_P(REGNO) \
1679 (GENERAL_REGNO_P (REGNO) \
1680 || (REGNO) == ARG_POINTER_REGNUM \
1681 || (REGNO) == FRAME_POINTER_REGNUM \
1682 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1683
1684/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1685 and check its validity for a certain class.
1686 We have two alternate definitions for each of them.
1687 The usual definition accepts all pseudo regs; the other rejects
1688 them unless they have been allocated suitable hard regs.
1689 The symbol REG_OK_STRICT causes the latter definition to be used.
1690
1691 Most source files want to accept pseudo regs in the hope that
1692 they will get allocated to the class that the insn wants them to be in.
1693 Source files for reload pass need to be strict.
1694 After reload, it makes no difference, since pseudo regs have
1695 been eliminated by then. */
1696
1697
1698/* Non strict versions, pseudos are ok. */
1699#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1700 (REGNO (X) < STACK_POINTER_REGNUM \
1701 || REX_INT_REGNO_P (REGNO (X)) \
1702 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1703
1704#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1705 (GENERAL_REGNO_P (REGNO (X)) \
1706 || REGNO (X) == ARG_POINTER_REGNUM \
1707 || REGNO (X) == FRAME_POINTER_REGNUM \
1708 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1709
1710/* Strict versions, hard registers only */
1711#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1712#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1713
1714#ifndef REG_OK_STRICT
1715#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1716#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1717
1718#else
1719#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1720#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1721#endif
1722
1723/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1724 that is a valid memory address for an instruction.
1725 The MODE argument is the machine mode for the MEM expression
1726 that wants to use this address.
1727
1728 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1729 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1730
1731 See legitimize_pic_address in i386.cc for details as to what
1732 constitutes a legitimate address when -fpic is used. */
1733
1734#define MAX_REGS_PER_ADDRESS 2
1735
1736#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1737
1738/* If defined, a C expression to determine the base term of address X.
1739 This macro is used in only one place: `find_base_term' in alias.cc.
1740
1741 It is always safe for this macro to not be defined. It exists so
1742 that alias analysis can understand machine-dependent addresses.
1743
1744 The typical use of this macro is to handle addresses containing
1745 a label_ref or symbol_ref within an UNSPEC. */
1746
1747#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1748
1749/* Nonzero if the constant value X is a legitimate general operand
1750 when generating PIC code. It is given that flag_pic is on and
1751 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1752
1753#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1754
1755#define STRIP_UNARY(X) (UNARY_P (X) ? XEXP (X, 0) : X)
1756
1757#define SYMBOLIC_CONST(X) \
1758 (GET_CODE (X) == SYMBOL_REF \
1759 || GET_CODE (X) == LABEL_REF \
1760 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1761
1762/* Max number of args passed in registers. If this is more than 3, we will
1763 have problems with ebx (register #4), since it is a caller save register and
1764 is also used as the pic register in ELF. So for now, don't allow more than
1765 3 registers to be passed in registers. */
1766
1767/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1768#define X86_64_REGPARM_MAX 6
1769#define X86_64_MS_REGPARM_MAX 4
1770
1771#define X86_32_REGPARM_MAX 3
1772
1773#define REGPARM_MAX \
1774 (TARGET_64BIT \
1775 ? (TARGET_64BIT_MS_ABI \
1776 ? X86_64_MS_REGPARM_MAX \
1777 : X86_64_REGPARM_MAX) \
1778 : X86_32_REGPARM_MAX)
1779
1780#define X86_64_SSE_REGPARM_MAX 8
1781#define X86_64_MS_SSE_REGPARM_MAX 4
1782
1783#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1784
1785#define SSE_REGPARM_MAX \
1786 (TARGET_64BIT \
1787 ? (TARGET_64BIT_MS_ABI \
1788 ? X86_64_MS_SSE_REGPARM_MAX \
1789 : X86_64_SSE_REGPARM_MAX) \
1790 : X86_32_SSE_REGPARM_MAX)
1791
1792#define X86_32_MMX_REGPARM_MAX (TARGET_MMX ? (TARGET_MACHO ? 0 : 3) : 0)
1793
1794#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : X86_32_MMX_REGPARM_MAX)
1795
1796/* Specify the machine mode that this machine uses
1797 for the index in the tablejump instruction. */
1798#define CASE_VECTOR_MODE \
1799 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1800
1801/* Define this as 1 if `char' should by default be signed; else as 0. */
1802#define DEFAULT_SIGNED_CHAR 1
1803
1804/* The constant maximum number of bytes that a single instruction can
1805 move quickly between memory and registers or between two memory
1806 locations. */
1807#define MAX_MOVE_MAX 64
1808
1809/* Max number of bytes we can move from memory to memory in one
1810 reasonably fast instruction, as opposed to MOVE_MAX_PIECES which
1811 is the number of bytes at a time which we can move efficiently.
1812 MOVE_MAX_PIECES defaults to MOVE_MAX. */
1813
1814#define MOVE_MAX \
1815 ((TARGET_AVX512F \
1816 && (ix86_move_max == PVW_AVX512 \
1817 || ix86_store_max == PVW_AVX512)) \
1818 ? 64 \
1819 : ((TARGET_AVX \
1820 && (ix86_move_max >= PVW_AVX256 \
1821 || ix86_store_max >= PVW_AVX256)) \
1822 ? 32 \
1823 : ((TARGET_SSE2 \
1824 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
1825 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1826 ? 16 : UNITS_PER_WORD)))
1827
1828/* STORE_MAX_PIECES is the number of bytes at a time that we can store
1829 efficiently. Allow 16/32/64 bytes only if inter-unit move is enabled
1830 since vec_duplicate enabled by inter-unit move is used to implement
1831 store_by_pieces of 16/32/64 bytes. */
1832#define STORE_MAX_PIECES \
1833 (TARGET_INTER_UNIT_MOVES_TO_VEC \
1834 ? ((TARGET_AVX512F && ix86_store_max == PVW_AVX512) \
1835 ? 64 \
1836 : ((TARGET_AVX \
1837 && ix86_store_max >= PVW_AVX256) \
1838 ? 32 \
1839 : ((TARGET_SSE2 \
1840 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1841 ? 16 : UNITS_PER_WORD))) \
1842 : UNITS_PER_WORD)
1843
1844/* If a memory-to-memory move would take MOVE_RATIO or more simple
1845 move-instruction pairs, we will do a cpymem or libcall instead.
1846 Increasing the value will always make code faster, but eventually
1847 incurs high cost in increased code size.
1848
1849 If you don't define this, a reasonable default is used. */
1850
1851#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1852
1853/* If a clear memory operation would take CLEAR_RATIO or more simple
1854 move-instruction sequences, we will do a clrmem or libcall instead. */
1855
1856#define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2)
1857
1858/* Define if shifts truncate the shift count which implies one can
1859 omit a sign-extension or zero-extension of a shift count.
1860
1861 On i386, shifts do truncate the count. But bit test instructions
1862 take the modulo of the bit offset operand. */
1863
1864/* #define SHIFT_COUNT_TRUNCATED */
1865
1866/* A macro to update M and UNSIGNEDP when an object whose type is
1867 TYPE and which has the specified mode and signedness is to be
1868 stored in a register. This macro is only called when TYPE is a
1869 scalar type.
1870
1871 On i386 it is sometimes useful to promote HImode and QImode
1872 quantities to SImode. The choice depends on target type. */
1873
1874#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1875do { \
1876 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1877 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1878 (MODE) = SImode; \
1879} while (0)
1880
1881/* Specify the machine mode that pointers have.
1882 After generation of rtl, the compiler makes no further distinction
1883 between pointers and any other objects of this machine mode. */
1884#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1885
1886/* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save.
1887 NONLOCAL needs space to save both shadow stack and stack pointers.
1888
1889 FIXME: We only need to save and restore stack pointer in ptr_mode.
1890 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode
1891 to save and restore stack pointer. See
1892 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150
1893 */
1894#define STACK_SAVEAREA_MODE(LEVEL) \
1895 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
1896
1897/* Specify the machine_mode of the size increment
1898 operand of an 'allocate_stack' named pattern. */
1899#define STACK_SIZE_MODE Pmode
1900
1901/* A C expression whose value is zero if pointers that need to be extended
1902 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1903 greater then zero if they are zero-extended and less then zero if the
1904 ptr_extend instruction should be used. */
1905
1906#define POINTERS_EXTEND_UNSIGNED 1
1907
1908/* A function address in a call instruction
1909 is a byte address (for indexing purposes)
1910 so give the MEM rtx a byte's mode. */
1911#define FUNCTION_MODE QImode
1912
1913
1914/* A C expression for the cost of a branch instruction. A value of 1
1915 is the default; other values are interpreted relative to that. */
1916
1917#define BRANCH_COST(speed_p, predictable_p) \
1918 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1919
1920/* An integer expression for the size in bits of the largest integer machine
1921 mode that should actually be used. We allow pairs of registers. */
1922#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1923
1924/* Define this macro as a C expression which is nonzero if accessing
1925 less than a word of memory (i.e. a `char' or a `short') is no
1926 faster than accessing a word of memory, i.e., if such access
1927 require more than one instruction or if there is no difference in
1928 cost between byte and (aligned) word loads.
1929
1930 When this macro is not defined, the compiler will access a field by
1931 finding the smallest containing object; when it is defined, a
1932 fullword load will be used if alignment permits. Unless bytes
1933 accesses are faster than word accesses, using word accesses is
1934 preferable since it may eliminate subsequent memory access if
1935 subsequent accesses occur to other fields in the same word of the
1936 structure, but to different bytes. */
1937
1938#define SLOW_BYTE_ACCESS 0
1939
1940/* Nonzero if access to memory by shorts is slow and undesirable. */
1941#define SLOW_SHORT_ACCESS 0
1942
1943/* Define this macro if it is as good or better to call a constant
1944 function address than to call an address kept in a register.
1945
1946 Desirable on the 386 because a CALL with a constant address is
1947 faster than one with a register address. */
1948
1949#define NO_FUNCTION_CSE 1
1950
1951/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1952 return the mode to be used for the comparison.
1953
1954 For floating-point equality comparisons, CCFPEQmode should be used.
1955 VOIDmode should be used in all other cases.
1956
1957 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1958 possible, to allow for more combinations. */
1959
1960#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1961
1962/* Return nonzero if MODE implies a floating point inequality can be
1963 reversed. */
1964
1965#define REVERSIBLE_CC_MODE(MODE) 1
1966
1967/* A C expression whose value is reversed condition code of the CODE for
1968 comparison done in CC_MODE mode. */
1969#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1970
1971
1972/* Control the assembler format that we output, to the extent
1973 this does not vary between assemblers. */
1974
1975/* How to refer to registers in assembler output.
1976 This sequence is indexed by compiler's hard-register-number (see above). */
1977
1978/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1979 For non floating point regs, the following are the HImode names.
1980
1981 For float regs, the stack top is sometimes referred to as "%st(0)"
1982 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1983 "y" code. */
1984
1985#define HI_REGISTER_NAMES \
1986{"ax","dx","cx","bx","si","di","bp","sp", \
1987 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1988 "argp", "flags", "fpsr", "frame", \
1989 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1990 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1991 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1992 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
1993 "xmm16", "xmm17", "xmm18", "xmm19", \
1994 "xmm20", "xmm21", "xmm22", "xmm23", \
1995 "xmm24", "xmm25", "xmm26", "xmm27", \
1996 "xmm28", "xmm29", "xmm30", "xmm31", \
1997 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }
1998
1999#define REGISTER_NAMES HI_REGISTER_NAMES
2000
2001#define QI_REGISTER_NAMES \
2002{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"}
2003
2004#define QI_HIGH_REGISTER_NAMES \
2005{"ah", "dh", "ch", "bh"}
2006
2007/* Table of additional register names to use in user input. */
2008
2009#define ADDITIONAL_REGISTER_NAMES \
2010{ \
2011 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \
2012 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \
2013 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
2014 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
2015 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
2016 { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \
2017 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
2018 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
2019 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
2020 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \
2021 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \
2022 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \
2023 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \
2024 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \
2025 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \
2026 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \
2027 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \
2028 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \
2029 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \
2030 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \
2031 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \
2032 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \
2033 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
2034}
2035
2036/* How to renumber registers for dbx and gdb. */
2037
2038#define DBX_REGISTER_NUMBER(N) \
2039 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2040
2041extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2042extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2043extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2044
2045/* Before the prologue, RA is at 0(%esp). */
2046#define INCOMING_RETURN_ADDR_RTX \
2047 gen_rtx_MEM (Pmode, stack_pointer_rtx)
2048
2049/* After the prologue, RA is at -4(AP) in the current frame. */
2050#define RETURN_ADDR_RTX(COUNT, FRAME) \
2051 ((COUNT) == 0 \
2052 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2053 -UNITS_PER_WORD)) \
2054 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD)))
2055
2056/* PC is dbx register 8; let's use that column for RA. */
2057#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2058
2059/* Before the prologue, there are return address and error code for
2060 exception handler on the top of the frame. */
2061#define INCOMING_FRAME_SP_OFFSET \
2062 (cfun->machine->func_type == TYPE_EXCEPTION \
2063 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2064
2065/* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in
2066 .cfi_startproc. */
2067#define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2068
2069/* Describe how we implement __builtin_eh_return. */
2070#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2071#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2072
2073
2074/* Select a format to encode pointers in exception handling data. CODE
2075 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2076 true if the symbol may be affected by dynamic relocations.
2077
2078 ??? All x86 object file formats are capable of representing this.
2079 After all, the relocation needed is the same as for the call insn.
2080 Whether or not a particular assembler allows us to enter such, I
2081 guess we'll have to see. */
2082#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2083 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2084
2085/* These are a couple of extensions to the formats accepted
2086 by asm_fprintf:
2087 %z prints out opcode suffix for word-mode instruction
2088 %r prints out word-mode name for reg_names[arg] */
2089#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
2090 case 'z': \
2091 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \
2092 break; \
2093 \
2094 case 'r': \
2095 { \
2096 unsigned int regno = va_arg ((ARGS), int); \
2097 if (LEGACY_INT_REGNO_P (regno)) \
2098 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \
2099 fputs (reg_names[regno], (FILE)); \
2100 break; \
2101 }
2102
2103/* This is how to output an insn to push a register on the stack. */
2104
2105#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2106 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO))
2107
2108/* This is how to output an insn to pop a register from the stack. */
2109
2110#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2111 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO))
2112
2113/* This is how to output an element of a case-vector that is absolute. */
2114
2115#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2116 ix86_output_addr_vec_elt ((FILE), (VALUE))
2117
2118/* This is how to output an element of a case-vector that is relative. */
2119
2120#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2121 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2122
2123/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2124
2125#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2126{ \
2127 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2128 (PTR) += TARGET_AVX ? 1 : 2; \
2129}
2130
2131/* A C statement or statements which output an assembler instruction
2132 opcode to the stdio stream STREAM. The macro-operand PTR is a
2133 variable of type `char *' which points to the opcode name in
2134 its "internal" form--the form that is written in the machine
2135 description. */
2136
2137#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2138 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2139
2140/* A C statement to output to the stdio stream FILE an assembler
2141 command to pad the location counter to a multiple of 1<<LOG
2142 bytes if it is within MAX_SKIP bytes. */
2143
2144#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2145# define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2146 do { \
2147 if ((LOG) != 0) { \
2148 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \
2149 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2150 else \
2151 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2152 } \
2153 } while (0)
2154#endif
2155
2156/* Write the extra assembler code needed to declare a function
2157 properly. */
2158
2159#undef ASM_OUTPUT_FUNCTION_LABEL
2160#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2161 ix86_asm_output_function_label ((FILE), (NAME), (DECL))
2162
2163/* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM.
2164 If not defined, assemble_name will be used to output the name of the
2165 symbol. This macro may be used to modify the way a symbol is referenced
2166 depending on information encoded by TARGET_ENCODE_SECTION_INFO. */
2167
2168#ifndef ASM_OUTPUT_SYMBOL_REF
2169#define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \
2170 do { \
2171 const char *name \
2172 = assemble_name_resolve (XSTR (x, 0)); \
2173 /* In -masm=att wrap identifiers that start with $ \
2174 into parens. */ \
2175 if (ASSEMBLER_DIALECT == ASM_ATT \
2176 && name[0] == '$' \
2177 && user_label_prefix[0] == '\0') \
2178 { \
2179 fputc ('(', (FILE)); \
2180 assemble_name_raw ((FILE), name); \
2181 fputc (')', (FILE)); \
2182 } \
2183 else \
2184 assemble_name_raw ((FILE), name); \
2185 } while (0)
2186#endif
2187
2188/* Under some conditions we need jump tables in the text section,
2189 because the assembler cannot handle label differences between
2190 sections. */
2191
2192#define JUMP_TABLES_IN_TEXT_SECTION \
2193 (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA))
2194
2195/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2196 and switch back. For x86 we do this only to save a few bytes that
2197 would otherwise be unused in the text section. */
2198#define CRT_MKSTR2(VAL) #VAL
2199#define CRT_MKSTR(x) CRT_MKSTR2(x)
2200
2201#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2202 asm (SECTION_OP "\n\t" \
2203 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2204 TEXT_SECTION_ASM_OP);
2205
2206/* Default threshold for putting data in large sections
2207 with x86-64 medium memory model */
2208#define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2209
2210/* Which processor to tune code generation for. These must be in sync
2211 with processor_target_table in i386.cc. */
2212
2213enum processor_type
2214{
2215 PROCESSOR_GENERIC = 0,
2216 PROCESSOR_I386, /* 80386 */
2217 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2218 PROCESSOR_PENTIUM,
2219 PROCESSOR_LAKEMONT,
2220 PROCESSOR_PENTIUMPRO,
2221 PROCESSOR_PENTIUM4,
2222 PROCESSOR_NOCONA,
2223 PROCESSOR_CORE2,
2224 PROCESSOR_NEHALEM,
2225 PROCESSOR_SANDYBRIDGE,
2226 PROCESSOR_HASWELL,
2227 PROCESSOR_BONNELL,
2228 PROCESSOR_SILVERMONT,
2229 PROCESSOR_GOLDMONT,
2230 PROCESSOR_GOLDMONT_PLUS,
2231 PROCESSOR_TREMONT,
2232 PROCESSOR_KNL,
2233 PROCESSOR_KNM,
2234 PROCESSOR_SKYLAKE,
2235 PROCESSOR_SKYLAKE_AVX512,
2236 PROCESSOR_CANNONLAKE,
2237 PROCESSOR_ICELAKE_CLIENT,
2238 PROCESSOR_ICELAKE_SERVER,
2239 PROCESSOR_CASCADELAKE,
2240 PROCESSOR_TIGERLAKE,
2241 PROCESSOR_COOPERLAKE,
2242 PROCESSOR_SAPPHIRERAPIDS,
2243 PROCESSOR_ALDERLAKE,
2244 PROCESSOR_ROCKETLAKE,
2245 PROCESSOR_INTEL,
2246 PROCESSOR_LUJIAZUI,
2247 PROCESSOR_GEODE,
2248 PROCESSOR_K6,
2249 PROCESSOR_ATHLON,
2250 PROCESSOR_K8,
2251 PROCESSOR_AMDFAM10,
2252 PROCESSOR_BDVER1,
2253 PROCESSOR_BDVER2,
2254 PROCESSOR_BDVER3,
2255 PROCESSOR_BDVER4,
2256 PROCESSOR_BTVER1,
2257 PROCESSOR_BTVER2,
2258 PROCESSOR_ZNVER1,
2259 PROCESSOR_ZNVER2,
2260 PROCESSOR_ZNVER3,
2261 PROCESSOR_max
2262};
2263
2264#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
2265extern const char *const processor_names[];
2266
2267#include "wide-int-bitmask.h"
2268
2269enum pta_flag
2270{
2271#define DEF_PTA(NAME) _ ## NAME,
2272#include "i386-isa.def"
2273#undef DEF_PTA
2274 END_PTA
2275};
2276
2277/* wide_int_bitmask can handle only 128 flags. */
2278STATIC_ASSERT (END_PTA <= 128);
2279
2280#define WIDE_INT_BITMASK_FROM_NTH(N) (N < 64 ? wide_int_bitmask (0, 1ULL << N) \
2281 : wide_int_bitmask (1ULL << (N - 64), 0))
2282
2283#define DEF_PTA(NAME) constexpr wide_int_bitmask PTA_ ## NAME \
2284 = WIDE_INT_BITMASK_FROM_NTH ((pta_flag) _ ## NAME);
2285#include "i386-isa.def"
2286#undef DEF_PTA
2287
2288constexpr wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE
2289 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR;
2290constexpr wide_int_bitmask PTA_X86_64_V2 = (PTA_X86_64_BASELINE
2291 & (~PTA_NO_SAHF))
2292 | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_SSSE3;
2293constexpr wide_int_bitmask PTA_X86_64_V3 = PTA_X86_64_V2
2294 | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2295 | PTA_MOVBE | PTA_XSAVE;
2296constexpr wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3
2297 | PTA_AVX512F | PTA_AVX512BW | PTA_AVX512CD | PTA_AVX512DQ | PTA_AVX512VL;
2298
2299constexpr wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2300 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
2301constexpr wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
2302 | PTA_POPCNT;
2303constexpr wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
2304constexpr wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
2305 | PTA_XSAVEOPT;
2306constexpr wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
2307 | PTA_RDRND | PTA_F16C;
2308constexpr wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
2309 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
2310constexpr wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
2311 | PTA_PRFCHW;
2312constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES
2313 | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
2314constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
2315 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2316 | PTA_CLWB;
2317constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512
2318 | PTA_AVX512VNNI;
2319constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
2320constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
2321 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2322 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
2323constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
2324 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
2325 | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
2326constexpr wide_int_bitmask PTA_ROCKETLAKE = PTA_ICELAKE_CLIENT & ~PTA_SGX;
2327constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT
2328 | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB;
2329constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
2330 | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL | PTA_WIDEKL;
2331constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_ICELAKE_SERVER | PTA_MOVDIRI
2332 | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_ENQCMD | PTA_CLDEMOTE
2333 | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE
2334 | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16
2335 | PTA_AVX512BF16;
2336constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF
2337 | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
2338constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
2339constexpr wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE
2340 | PTA_RDRND | PTA_PRFCHW;
2341constexpr wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA
2342 | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT
2343 | PTA_XSAVEOPT | PTA_FSGSBASE;
2344constexpr wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
2345 | PTA_SGX | PTA_PTWRITE;
2346constexpr wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
2347 | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
2348constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX
2349 | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2350 | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
2351 | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
2352constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
2353 | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
2354
2355#ifndef GENERATOR_FILE
2356
2357#include "insn-attr-common.h"
2358
2359#include "common/config/i386/i386-cpuinfo.h"
2360
2361class pta
2362{
2363public:
2364 const char *const name; /* processor name or nickname. */
2365 const enum processor_type processor;
2366 const enum attr_cpu schedule;
2367 const wide_int_bitmask flags;
2368 const int model;
2369 const enum feature_priority priority;
2370};
2371
2372extern const pta processor_alias_table[];
2373extern unsigned int const pta_size;
2374extern unsigned int const num_arch_names;
2375#endif
2376
2377#endif
2378
2379extern enum processor_type ix86_tune;
2380extern enum processor_type ix86_arch;
2381
2382/* Size of the RED_ZONE area. */
2383#define RED_ZONE_SIZE 128
2384/* Reserved area of the red zone for temporaries. */
2385#define RED_ZONE_RESERVE 8
2386
2387extern unsigned int ix86_preferred_stack_boundary;
2388extern unsigned int ix86_incoming_stack_boundary;
2389
2390/* Smallest class containing REGNO. */
2391extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2392
2393enum ix86_fpcmp_strategy {
2394 IX86_FPCMP_SAHF,
2395 IX86_FPCMP_COMI,
2396 IX86_FPCMP_ARITH
2397};
2398
2399/* To properly truncate FP values into integers, we need to set i387 control
2400 word. We can't emit proper mode switching code before reload, as spills
2401 generated by reload may truncate values incorrectly, but we still can avoid
2402 redundant computation of new control word by the mode switching pass.
2403 The fldcw instructions are still emitted redundantly, but this is probably
2404 not going to be noticeable problem, as most CPUs do have fast path for
2405 the sequence.
2406
2407 The machinery is to emit simple truncation instructions and split them
2408 before reload to instructions having USEs of two memory locations that
2409 are filled by this code to old and new control word.
2410
2411 Post-reload pass may be later used to eliminate the redundant fildcw if
2412 needed. */
2413
2414enum ix86_stack_slot
2415{
2416 SLOT_TEMP = 0,
2417 SLOT_CW_STORED,
2418 SLOT_CW_ROUNDEVEN,
2419 SLOT_CW_TRUNC,
2420 SLOT_CW_FLOOR,
2421 SLOT_CW_CEIL,
2422 SLOT_STV_TEMP,
2423 SLOT_FLOATxFDI_387,
2424 MAX_386_STACK_LOCALS
2425};
2426
2427enum ix86_entity
2428{
2429 X86_DIRFLAG = 0,
2430 AVX_U128,
2431 I387_ROUNDEVEN,
2432 I387_TRUNC,
2433 I387_FLOOR,
2434 I387_CEIL,
2435 MAX_386_ENTITIES
2436};
2437
2438enum x86_dirflag_state
2439{
2440 X86_DIRFLAG_RESET,
2441 X86_DIRFLAG_ANY
2442};
2443
2444enum avx_u128_state
2445{
2446 AVX_U128_CLEAN,
2447 AVX_U128_DIRTY,
2448 AVX_U128_ANY
2449};
2450
2451/* Define this macro if the port needs extra instructions inserted
2452 for mode switching in an optimizing compilation. */
2453
2454#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2455 ix86_optimize_mode_switching[(ENTITY)]
2456
2457/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2458 initializer for an array of integers. Each initializer element N
2459 refers to an entity that needs mode switching, and specifies the
2460 number of different modes that might need to be set for this
2461 entity. The position of the initializer in the initializer -
2462 starting counting at zero - determines the integer that is used to
2463 refer to the mode-switched entity in question. */
2464
2465#define NUM_MODES_FOR_MODE_SWITCHING \
2466 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2467 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2468
2469
2470/* Avoid renaming of stack registers, as doing so in combination with
2471 scheduling just increases amount of live registers at time and in
2472 the turn amount of fxch instructions needed.
2473
2474 ??? Maybe Pentium chips benefits from renaming, someone can try....
2475
2476 Don't rename evex to non-evex sse registers. */
2477
2478#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2479 (!STACK_REGNO_P (SRC) \
2480 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET))
2481
2482
2483#define FASTCALL_PREFIX '@'
2484
2485#ifndef USED_FOR_TARGET
2486/* Structure describing stack frame layout.
2487 Stack grows downward:
2488
2489 [arguments]
2490 <- ARG_POINTER
2491 saved pc
2492
2493 saved static chain if ix86_static_chain_on_stack
2494
2495 saved frame pointer if frame_pointer_needed
2496 <- HARD_FRAME_POINTER
2497 [saved regs]
2498 <- reg_save_offset
2499 [padding0]
2500 <- stack_realign_offset
2501 [saved SSE regs]
2502 OR
2503 [stub-saved registers for ms x64 --> sysv clobbers
2504 <- Start of out-of-line, stub-saved/restored regs
2505 (see libgcc/config/i386/(sav|res)ms64*.S)
2506 [XMM6-15]
2507 [RSI]
2508 [RDI]
2509 [?RBX] only if RBX is clobbered
2510 [?RBP] only if RBP and RBX are clobbered
2511 [?R12] only if R12 and all previous regs are clobbered
2512 [?R13] only if R13 and all previous regs are clobbered
2513 [?R14] only if R14 and all previous regs are clobbered
2514 [?R15] only if R15 and all previous regs are clobbered
2515 <- end of stub-saved/restored regs
2516 [padding1]
2517 ]
2518 <- sse_reg_save_offset
2519 [padding2]
2520 | <- FRAME_POINTER
2521 [va_arg registers] |
2522 |
2523 [frame] |
2524 |
2525 [padding2] | = to_allocate
2526 <- STACK_POINTER
2527 */
2528struct GTY(()) ix86_frame
2529{
2530 int nsseregs;
2531 int nregs;
2532 int va_arg_size;
2533 int red_zone_size;
2534 int outgoing_arguments_size;
2535
2536 /* The offsets relative to ARG_POINTER. */
2537 HOST_WIDE_INT frame_pointer_offset;
2538 HOST_WIDE_INT hard_frame_pointer_offset;
2539 HOST_WIDE_INT stack_pointer_offset;
2540 HOST_WIDE_INT hfp_save_offset;
2541 HOST_WIDE_INT reg_save_offset;
2542 HOST_WIDE_INT stack_realign_allocate;
2543 HOST_WIDE_INT stack_realign_offset;
2544 HOST_WIDE_INT sse_reg_save_offset;
2545
2546 /* When save_regs_using_mov is set, emit prologue using
2547 move instead of push instructions. */
2548 bool save_regs_using_mov;
2549
2550 /* Assume without checking that:
2551 EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */
2552 bool expensive_p;
2553 int expensive_count;
2554};
2555
2556/* Machine specific frame tracking during prologue/epilogue generation. All
2557 values are positive, but since the x86 stack grows downward, are subtratced
2558 from the CFA to produce a valid address. */
2559
2560struct GTY(()) machine_frame_state
2561{
2562 /* This pair tracks the currently active CFA as reg+offset. When reg
2563 is drap_reg, we don't bother trying to record here the real CFA when
2564 it might really be a DW_CFA_def_cfa_expression. */
2565 rtx cfa_reg;
2566 HOST_WIDE_INT cfa_offset;
2567
2568 /* The current offset (canonically from the CFA) of ESP and EBP.
2569 When stack frame re-alignment is active, these may not be relative
2570 to the CFA. However, in all cases they are relative to the offsets
2571 of the saved registers stored in ix86_frame. */
2572 HOST_WIDE_INT sp_offset;
2573 HOST_WIDE_INT fp_offset;
2574
2575 /* The size of the red-zone that may be assumed for the purposes of
2576 eliding register restore notes in the epilogue. This may be zero
2577 if no red-zone is in effect, or may be reduced from the real
2578 red-zone value by a maximum runtime stack re-alignment value. */
2579 int red_zone_offset;
2580
2581 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2582 value within the frame. If false then the offset above should be
2583 ignored. Note that DRAP, if valid, *always* points to the CFA and
2584 thus has an offset of zero. */
2585 BOOL_BITFIELD sp_valid : 1;
2586 BOOL_BITFIELD fp_valid : 1;
2587 BOOL_BITFIELD drap_valid : 1;
2588
2589 /* Indicate whether the local stack frame has been re-aligned. When
2590 set, the SP/FP offsets above are relative to the aligned frame
2591 and not the CFA. */
2592 BOOL_BITFIELD realigned : 1;
2593
2594 /* Indicates whether the stack pointer has been re-aligned. When set,
2595 SP/FP continue to be relative to the CFA, but the stack pointer
2596 should only be used for offsets > sp_realigned_offset, while
2597 the frame pointer should be used for offsets <= sp_realigned_fp_last.
2598 The flags realigned and sp_realigned are mutually exclusive. */
2599 BOOL_BITFIELD sp_realigned : 1;
2600
2601 /* If sp_realigned is set, this is the last valid offset from the CFA
2602 that can be used for access with the frame pointer. */
2603 HOST_WIDE_INT sp_realigned_fp_last;
2604
2605 /* If sp_realigned is set, this is the offset from the CFA that the stack
2606 pointer was realigned, and may or may not be equal to sp_realigned_fp_last.
2607 Access via the stack pointer is only valid for offsets that are greater than
2608 this value. */
2609 HOST_WIDE_INT sp_realigned_offset;
2610};
2611
2612/* Private to winnt.cc. */
2613struct seh_frame_state;
2614
2615enum function_type
2616{
2617 TYPE_UNKNOWN = 0,
2618 TYPE_NORMAL,
2619 /* The current function is an interrupt service routine with a
2620 pointer argument as specified by the "interrupt" attribute. */
2621 TYPE_INTERRUPT,
2622 /* The current function is an interrupt service routine with a
2623 pointer argument and an integer argument as specified by the
2624 "interrupt" attribute. */
2625 TYPE_EXCEPTION
2626};
2627
2628enum queued_insn_type
2629{
2630 TYPE_NONE = 0,
2631 TYPE_ENDBR,
2632 TYPE_PATCHABLE_AREA
2633};
2634
2635struct GTY(()) machine_function {
2636 struct stack_local_entry *stack_locals;
2637 int varargs_gpr_size;
2638 int varargs_fpr_size;
2639 int optimize_mode_switching[MAX_386_ENTITIES];
2640
2641 /* Cached initial frame layout for the current function. */
2642 struct ix86_frame frame;
2643
2644 /* For -fsplit-stack support: A stack local which holds a pointer to
2645 the stack arguments for a function with a variable number of
2646 arguments. This is set at the start of the function and is used
2647 to initialize the overflow_arg_area field of the va_list
2648 structure. */
2649 rtx split_stack_varargs_pointer;
2650
2651 /* This value is used for amd64 targets and specifies the current abi
2652 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2653 ENUM_BITFIELD(calling_abi) call_abi : 8;
2654
2655 /* Nonzero if the function accesses a previous frame. */
2656 BOOL_BITFIELD accesses_prev_frame : 1;
2657
2658 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2659 expander to determine the style used. */
2660 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2661
2662 /* Nonzero if the current function calls pc thunk and
2663 must not use the red zone. */
2664 BOOL_BITFIELD pc_thunk_call_expanded : 1;
2665
2666 /* If true, the current function needs the default PIC register, not
2667 an alternate register (on x86) and must not use the red zone (on
2668 x86_64), even if it's a leaf function. We don't want the
2669 function to be regarded as non-leaf because TLS calls need not
2670 affect register allocation. This flag is set when a TLS call
2671 instruction is expanded within a function, and never reset, even
2672 if all such instructions are optimized away. Use the
2673 ix86_current_function_calls_tls_descriptor macro for a better
2674 approximation. */
2675 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2676
2677 /* If true, the current function has a STATIC_CHAIN is placed on the
2678 stack below the return address. */
2679 BOOL_BITFIELD static_chain_on_stack : 1;
2680
2681 /* If true, it is safe to not save/restore DRAP register. */
2682 BOOL_BITFIELD no_drap_save_restore : 1;
2683
2684 /* Function type. */
2685 ENUM_BITFIELD(function_type) func_type : 2;
2686
2687 /* How to generate indirec branch. */
2688 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3;
2689
2690 /* If true, the current function has local indirect jumps, like
2691 "indirect_jump" or "tablejump". */
2692 BOOL_BITFIELD has_local_indirect_jump : 1;
2693
2694 /* How to generate function return. */
2695 ENUM_BITFIELD(indirect_branch) function_return_type : 3;
2696
2697 /* If true, the current function is a function specified with
2698 the "interrupt" or "no_caller_saved_registers" attribute. */
2699 BOOL_BITFIELD no_caller_saved_registers : 1;
2700
2701 /* If true, there is register available for argument passing. This
2702 is used only in ix86_function_ok_for_sibcall by 32-bit to determine
2703 if there is scratch register available for indirect sibcall. In
2704 64-bit, rax, r10 and r11 are scratch registers which aren't used to
2705 pass arguments and can be used for indirect sibcall. */
2706 BOOL_BITFIELD arg_reg_available : 1;
2707
2708 /* If true, we're out-of-lining reg save/restore for regs clobbered
2709 by 64-bit ms_abi functions calling a sysv_abi function. */
2710 BOOL_BITFIELD call_ms2sysv : 1;
2711
2712 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and
2713 needs padding prior to out-of-line stub save/restore area. */
2714 BOOL_BITFIELD call_ms2sysv_pad_in : 1;
2715
2716 /* This is the number of extra registers saved by stub (valid range is
2717 0-6). Each additional register is only saved/restored by the stubs
2718 if all successive ones are. (Will always be zero when using a hard
2719 frame pointer.) */
2720 unsigned int call_ms2sysv_extra_regs:3;
2721
2722 /* Nonzero if the function places outgoing arguments on stack. */
2723 BOOL_BITFIELD outgoing_args_on_stack : 1;
2724
2725 /* If true, ENDBR or patchable area is queued at function entrance. */
2726 ENUM_BITFIELD(queued_insn_type) insn_queued_at_entrance : 2;
2727
2728 /* If true, the function label has been emitted. */
2729 BOOL_BITFIELD function_label_emitted : 1;
2730
2731 /* True if the function needs a stack frame. */
2732 BOOL_BITFIELD stack_frame_required : 1;
2733
2734 /* True if we should act silently, rather than raise an error for
2735 invalid calls. */
2736 BOOL_BITFIELD silent_p : 1;
2737
2738 /* True if red zone is used. */
2739 BOOL_BITFIELD red_zone_used : 1;
2740
2741 /* The largest alignment, in bytes, of stack slot actually used. */
2742 unsigned int max_used_stack_alignment;
2743
2744 /* During prologue/epilogue generation, the current frame state.
2745 Otherwise, the frame state at the end of the prologue. */
2746 struct machine_frame_state fs;
2747
2748 /* During SEH output, this is non-null. */
2749 struct seh_frame_state * GTY((skip(""))) seh;
2750};
2751
2752extern GTY(()) tree sysv_va_list_type_node;
2753extern GTY(()) tree ms_va_list_type_node;
2754#endif
2755
2756#define ix86_stack_locals (cfun->machine->stack_locals)
2757#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2758#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2759#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2760#define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded)
2761#define ix86_tls_descriptor_calls_expanded_in_cfun \
2762 (cfun->machine->tls_descriptor_call_expanded_p)
2763/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2764 calls are optimized away, we try to detect cases in which it was
2765 optimized away. Since such instructions (use (reg REG_SP)), we can
2766 verify whether there's any such instruction live by testing that
2767 REG_SP is live. */
2768#define ix86_current_function_calls_tls_descriptor \
2769 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2770#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2771#define ix86_red_zone_used (cfun->machine->red_zone_used)
2772
2773/* Control behavior of x86_file_start. */
2774#define X86_FILE_START_VERSION_DIRECTIVE false
2775#define X86_FILE_START_FLTUSED false
2776
2777/* Flag to mark data that is in the large address area. */
2778#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2779#define SYMBOL_REF_FAR_ADDR_P(X) \
2780 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2781
2782/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2783 have defined always, to avoid ifdefing. */
2784#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2785#define SYMBOL_REF_DLLIMPORT_P(X) \
2786 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2787
2788#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2789#define SYMBOL_REF_DLLEXPORT_P(X) \
2790 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2791
2792#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
2793#define SYMBOL_REF_STUBVAR_P(X) \
2794 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
2795
2796extern void debug_ready_dispatch (void);
2797extern void debug_dispatch_window (int);
2798
2799/* The value at zero is only defined for the BMI instructions
2800 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2801#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2802 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 2 : 0)
2803#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2804 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 2 : 0)
2805
2806
2807/* Flags returned by ix86_get_callcvt (). */
2808#define IX86_CALLCVT_CDECL 0x1
2809#define IX86_CALLCVT_STDCALL 0x2
2810#define IX86_CALLCVT_FASTCALL 0x4
2811#define IX86_CALLCVT_THISCALL 0x8
2812#define IX86_CALLCVT_REGPARM 0x10
2813#define IX86_CALLCVT_SSEREGPARM 0x20
2814
2815#define IX86_BASE_CALLCVT(FLAGS) \
2816 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2817 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2818
2819#define RECIP_MASK_NONE 0x00
2820#define RECIP_MASK_DIV 0x01
2821#define RECIP_MASK_SQRT 0x02
2822#define RECIP_MASK_VEC_DIV 0x04
2823#define RECIP_MASK_VEC_SQRT 0x08
2824#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2825 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2826#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2827
2828#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2829#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2830#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2831#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2832
2833/* Use 128-bit AVX instructions in the auto-vectorizer. */
2834#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
2835/* Use 256-bit AVX instructions in the auto-vectorizer. */
2836#define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
2837 || prefer_vector_width_type == PVW_AVX256)
2838
2839#define TARGET_INDIRECT_BRANCH_REGISTER \
2840 (ix86_indirect_branch_register \
2841 || cfun->machine->indirect_branch_type != indirect_branch_keep)
2842
2843#define IX86_HLE_ACQUIRE (1 << 16)
2844#define IX86_HLE_RELEASE (1 << 17)
2845
2846/* For switching between functions with different target attributes. */
2847#define SWITCHABLE_TARGET 1
2848
2849#define TARGET_SUPPORTS_WIDE_INT 1
2850
2851#if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2)
2852extern enum attr_cpu ix86_schedule;
2853
2854#define NUM_X86_64_MS_CLOBBERED_REGS 12
2855#endif
2856
2857/* __builtin_eh_return can't handle stack realignment, so disable MMX/SSE
2858 in 32-bit libgcc functions that call it. */
2859#ifndef __x86_64__
2860#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((target ("no-mmx,no-sse")))
2861#endif
2862
2863/*
2864Local variables:
2865version-control: t
2866End:
2867*/
2868

source code of gcc/config/i386/i386.h