1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* intel_pstate.c: Native P state management for Intel processors
4	*
5	* (C) Copyright 2012 Intel Corporation
6	* Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7	*/
8
9	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11	#include <linux/kernel.h>
12	#include <linux/kernel_stat.h>
13	#include <linux/module.h>
14	#include <linux/ktime.h>
15	#include <linux/hrtimer.h>
16	#include <linux/tick.h>
17	#include <linux/slab.h>
18	#include <linux/sched/cpufreq.h>
19	#include <linux/list.h>
20	#include <linux/cpu.h>
21	#include <linux/cpufreq.h>
22	#include <linux/sysfs.h>
23	#include <linux/types.h>
24	#include <linux/fs.h>
25	#include <linux/acpi.h>
26	#include <linux/vmalloc.h>
27	#include <linux/pm_qos.h>
28	#include <linux/bitfield.h>
29	#include <trace/events/power.h>
30
31	#include <asm/cpu.h>
32	#include <asm/div64.h>
33	#include <asm/msr.h>
34	#include <asm/cpu_device_id.h>
35	#include <asm/cpufeature.h>
36	#include <asm/intel-family.h>
37	#include "../drivers/thermal/intel/thermal_interrupt.h"
38
39	#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
40
41	#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42	#define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
43	#define INTEL_CPUFREQ_TRANSITION_DELAY 500
44
45	#ifdef CONFIG_ACPI
46	#include <acpi/processor.h>
47	#include <acpi/cppc_acpi.h>
48	#endif
49
50	#define FRAC_BITS 8
51	#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52	#define fp_toint(X) ((X) >> FRAC_BITS)
53
54	#define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
55
56	#define EXT_BITS 6
57	#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
58	#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
59	#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60
61	static inline int32_t mul_fp(int32_t x, int32_t y)
62	{
63	return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
64	}
65
66	static inline int32_t div_fp(s64 x, s64 y)
67	{
68	return div64_s64(dividend: (int64_t)x << FRAC_BITS, divisor: y);
69	}
70
71	static inline int ceiling_fp(int32_t x)
72	{
73	int mask, ret;
74
75	ret = fp_toint(x);
76	mask = (1 << FRAC_BITS) - 1;
77	if (x & mask)
78	ret += 1;
79	return ret;
80	}
81
82	static inline u64 mul_ext_fp(u64 x, u64 y)
83	{
84	return (x * y) >> EXT_FRAC_BITS;
85	}
86
87	static inline u64 div_ext_fp(u64 x, u64 y)
88	{
89	return div64_u64(dividend: x << EXT_FRAC_BITS, divisor: y);
90	}
91
92	/**
93	* struct sample - Store performance sample
94	* @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95	* performance during last sample period
96	* @busy_scaled: Scaled busy value which is used to calculate next
97	* P state. This can be different than core_avg_perf
98	* to account for cpu idle period
99	* @aperf: Difference of actual performance frequency clock count
100	* read from APERF MSR between last and current sample
101	* @mperf: Difference of maximum performance frequency clock count
102	* read from MPERF MSR between last and current sample
103	* @tsc: Difference of time stamp counter between last and
104	* current sample
105	* @time: Current time from scheduler
106	*
107	* This structure is used in the cpudata structure to store performance sample
108	* data for choosing next P State.
109	*/
110	struct sample {
111	int32_t core_avg_perf;
112	int32_t busy_scaled;
113	u64 aperf;
114	u64 mperf;
115	u64 tsc;
116	u64 time;
117	};
118
119	/**
120	* struct pstate_data - Store P state data
121	* @current_pstate: Current requested P state
122	* @min_pstate: Min P state possible for this platform
123	* @max_pstate: Max P state possible for this platform
124	* @max_pstate_physical:This is physical Max P state for a processor
125	* This can be higher than the max_pstate which can
126	* be limited by platform thermal design power limits
127	* @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
128	* @scaling: Scaling factor between performance and frequency
129	* @turbo_pstate: Max Turbo P state possible for this platform
130	* @min_freq: @min_pstate frequency in cpufreq units
131	* @max_freq: @max_pstate frequency in cpufreq units
132	* @turbo_freq: @turbo_pstate frequency in cpufreq units
133	*
134	* Stores the per cpu model P state limits and current P state.
135	*/
136	struct pstate_data {
137	int current_pstate;
138	int min_pstate;
139	int max_pstate;
140	int max_pstate_physical;
141	int perf_ctl_scaling;
142	int scaling;
143	int turbo_pstate;
144	unsigned int min_freq;
145	unsigned int max_freq;
146	unsigned int turbo_freq;
147	};
148
149	/**
150	* struct vid_data - Stores voltage information data
151	* @min: VID data for this platform corresponding to
152	* the lowest P state
153	* @max: VID data corresponding to the highest P State.
154	* @turbo: VID data for turbo P state
155	* @ratio: Ratio of (vid max - vid min) /
156	* (max P state - Min P State)
157	*
158	* Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
159	* This data is used in Atom platforms, where in addition to target P state,
160	* the voltage data needs to be specified to select next P State.
161	*/
162	struct vid_data {
163	int min;
164	int max;
165	int turbo;
166	int32_t ratio;
167	};
168
169	/**
170	* struct global_params - Global parameters, mostly tunable via sysfs.
171	* @no_turbo: Whether or not to use turbo P-states.
172	* @turbo_disabled: Whether or not turbo P-states are available at all,
173	* based on the MSR_IA32_MISC_ENABLE value and whether or
174	* not the maximum reported turbo P-state is different from
175	* the maximum reported non-turbo one.
176	* @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
177	* @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178	* P-state capacity.
179	* @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
180	* P-state capacity.
181	*/
182	struct global_params {
183	bool no_turbo;
184	bool turbo_disabled;
185	bool turbo_disabled_mf;
186	int max_perf_pct;
187	int min_perf_pct;
188	};
189
190	/**
191	* struct cpudata - Per CPU instance data storage
192	* @cpu: CPU number for this instance data
193	* @policy: CPUFreq policy value
194	* @update_util: CPUFreq utility callback information
195	* @update_util_set: CPUFreq utility callback is set
196	* @iowait_boost: iowait-related boost fraction
197	* @last_update: Time of the last update.
198	* @pstate: Stores P state limits for this CPU
199	* @vid: Stores VID limits for this CPU
200	* @last_sample_time: Last Sample time
201	* @aperf_mperf_shift: APERF vs MPERF counting frequency difference
202	* @prev_aperf: Last APERF value read from APERF MSR
203	* @prev_mperf: Last MPERF value read from MPERF MSR
204	* @prev_tsc: Last timestamp counter (TSC) value
205	* @sample: Storage for storing last Sample data
206	* @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
207	* @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
208	* @acpi_perf_data: Stores ACPI perf information read from _PSS
209	* @valid_pss_table: Set to true for valid ACPI _PSS entries found
210	* @epp_powersave: Last saved HWP energy performance preference
211	* (EPP) or energy performance bias (EPB),
212	* when policy switched to performance
213	* @epp_policy: Last saved policy used to set EPP/EPB
214	* @epp_default: Power on default HWP energy performance
215	* preference/bias
216	* @epp_cached Cached HWP energy-performance preference value
217	* @hwp_req_cached: Cached value of the last HWP Request MSR
218	* @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
219	* @last_io_update: Last time when IO wake flag was set
220	* @sched_flags: Store scheduler flags for possible cross CPU update
221	* @hwp_boost_min: Last HWP boosted min performance
222	* @suspended: Whether or not the driver has been suspended.
223	* @hwp_notify_work: workqueue for HWP notifications.
224	*
225	* This structure stores per CPU instance data for all CPUs.
226	*/
227	struct cpudata {
228	int cpu;
229
230	unsigned int policy;
231	struct update_util_data update_util;
232	bool update_util_set;
233
234	struct pstate_data pstate;
235	struct vid_data vid;
236
237	u64 last_update;
238	u64 last_sample_time;
239	u64 aperf_mperf_shift;
240	u64 prev_aperf;
241	u64 prev_mperf;
242	u64 prev_tsc;
243	struct sample sample;
244	int32_t min_perf_ratio;
245	int32_t max_perf_ratio;
246	#ifdef CONFIG_ACPI
247	struct acpi_processor_performance acpi_perf_data;
248	bool valid_pss_table;
249	#endif
250	unsigned int iowait_boost;
251	s16 epp_powersave;
252	s16 epp_policy;
253	s16 epp_default;
254	s16 epp_cached;
255	u64 hwp_req_cached;
256	u64 hwp_cap_cached;
257	u64 last_io_update;
258	unsigned int sched_flags;
259	u32 hwp_boost_min;
260	bool suspended;
261	struct delayed_work hwp_notify_work;
262	};
263
264	static struct cpudata **all_cpu_data;
265
266	/**
267	* struct pstate_funcs - Per CPU model specific callbacks
268	* @get_max: Callback to get maximum non turbo effective P state
269	* @get_max_physical: Callback to get maximum non turbo physical P state
270	* @get_min: Callback to get minimum P state
271	* @get_turbo: Callback to get turbo P state
272	* @get_scaling: Callback to get frequency scaling factor
273	* @get_cpu_scaling: Get frequency scaling factor for a given cpu
274	* @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
275	* @get_val: Callback to convert P state to actual MSR write value
276	* @get_vid: Callback to get VID data for Atom platforms
277	*
278	* Core and Atom CPU models have different way to get P State limits. This
279	* structure is used to store those callbacks.
280	*/
281	struct pstate_funcs {
282	int (*get_max)(int cpu);
283	int (*get_max_physical)(int cpu);
284	int (*get_min)(int cpu);
285	int (*get_turbo)(int cpu);
286	int (*get_scaling)(void);
287	int (*get_cpu_scaling)(int cpu);
288	int (*get_aperf_mperf_shift)(void);
289	u64 (*get_val)(struct cpudata*, int pstate);
290	void (*get_vid)(struct cpudata *);
291	};
292
293	static struct pstate_funcs pstate_funcs __read_mostly;
294
295	static int hwp_active __read_mostly;
296	static int hwp_mode_bdw __read_mostly;
297	static bool per_cpu_limits __read_mostly;
298	static bool hwp_boost __read_mostly;
299	static bool hwp_forced __read_mostly;
300
301	static struct cpufreq_driver *intel_pstate_driver __read_mostly;
302
303	#define HYBRID_SCALING_FACTOR 78741
304	#define HYBRID_SCALING_FACTOR_MTL 80000
305
306	static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
307
308	static inline int core_get_scaling(void)
309	{
310	return 100000;
311	}
312
313	#ifdef CONFIG_ACPI
314	static bool acpi_ppc;
315	#endif
316
317	static struct global_params global;
318
319	static DEFINE_MUTEX(intel_pstate_driver_lock);
320	static DEFINE_MUTEX(intel_pstate_limits_lock);
321
322	#ifdef CONFIG_ACPI
323
324	static bool intel_pstate_acpi_pm_profile_server(void)
325	{
326	if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
327	acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
328	return true;
329
330	return false;
331	}
332
333	static bool intel_pstate_get_ppc_enable_status(void)
334	{
335	if (intel_pstate_acpi_pm_profile_server())
336	return true;
337
338	return acpi_ppc;
339	}
340
341	#ifdef CONFIG_ACPI_CPPC_LIB
342
343	/* The work item is needed to avoid CPU hotplug locking issues */
344	static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
345	{
346	sched_set_itmt_support();
347	}
348
349	static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
350
351	#define CPPC_MAX_PERF U8_MAX
352
353	static void intel_pstate_set_itmt_prio(int cpu)
354	{
355	struct cppc_perf_caps cppc_perf;
356	static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
357	int ret;
358
359	ret = cppc_get_perf_caps(cpu, caps: &cppc_perf);
360	if (ret)
361	return;
362
363	/*
364	* On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
365	* In this case we can't use CPPC.highest_perf to enable ITMT.
366	* In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
367	*/
368	if (cppc_perf.highest_perf == CPPC_MAX_PERF)
369	cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
370
371	/*
372	* The priorities can be set regardless of whether or not
373	* sched_set_itmt_support(true) has been called and it is valid to
374	* update them at any time after it has been called.
375	*/
376	sched_set_itmt_core_prio(prio: cppc_perf.highest_perf, core_cpu: cpu);
377
378	if (max_highest_perf <= min_highest_perf) {
379	if (cppc_perf.highest_perf > max_highest_perf)
380	max_highest_perf = cppc_perf.highest_perf;
381
382	if (cppc_perf.highest_perf < min_highest_perf)
383	min_highest_perf = cppc_perf.highest_perf;
384
385	if (max_highest_perf > min_highest_perf) {
386	/*
387	* This code can be run during CPU online under the
388	* CPU hotplug locks, so sched_set_itmt_support()
389	* cannot be called from here. Queue up a work item
390	* to invoke it.
391	*/
392	schedule_work(work: &sched_itmt_work);
393	}
394	}
395	}
396
397	static int intel_pstate_get_cppc_guaranteed(int cpu)
398	{
399	struct cppc_perf_caps cppc_perf;
400	int ret;
401
402	ret = cppc_get_perf_caps(cpu, caps: &cppc_perf);
403	if (ret)
404	return ret;
405
406	if (cppc_perf.guaranteed_perf)
407	return cppc_perf.guaranteed_perf;
408
409	return cppc_perf.nominal_perf;
410	}
411
412	static int intel_pstate_cppc_get_scaling(int cpu)
413	{
414	struct cppc_perf_caps cppc_perf;
415	int ret;
416
417	ret = cppc_get_perf_caps(cpu, caps: &cppc_perf);
418
419	/*
420	* If the nominal frequency and the nominal performance are not
421	* zero and the ratio between them is not 100, return the hybrid
422	* scaling factor.
423	*/
424	if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
425	cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
426	return hybrid_scaling_factor;
427
428	return core_get_scaling();
429	}
430
431	#else /* CONFIG_ACPI_CPPC_LIB */
432	static inline void intel_pstate_set_itmt_prio(int cpu)
433	{
434	}
435	#endif /* CONFIG_ACPI_CPPC_LIB */
436
437	static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
438	{
439	struct cpudata *cpu;
440	int ret;
441	int i;
442
443	if (hwp_active) {
444	intel_pstate_set_itmt_prio(cpu: policy->cpu);
445	return;
446	}
447
448	if (!intel_pstate_get_ppc_enable_status())
449	return;
450
451	cpu = all_cpu_data[policy->cpu];
452
453	ret = acpi_processor_register_performance(performance: &cpu->acpi_perf_data,
454	cpu: policy->cpu);
455	if (ret)
456	return;
457
458	/*
459	* Check if the control value in _PSS is for PERF_CTL MSR, which should
460	* guarantee that the states returned by it map to the states in our
461	* list directly.
462	*/
463	if (cpu->acpi_perf_data.control_register.space_id !=
464	ACPI_ADR_SPACE_FIXED_HARDWARE)
465	goto err;
466
467	/*
468	* If there is only one entry _PSS, simply ignore _PSS and continue as
469	* usual without taking _PSS into account
470	*/
471	if (cpu->acpi_perf_data.state_count < 2)
472	goto err;
473
474	pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
475	for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
476	pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
477	(i == cpu->acpi_perf_data.state ? '*' : ' '), i,
478	(u32) cpu->acpi_perf_data.states[i].core_frequency,
479	(u32) cpu->acpi_perf_data.states[i].power,
480	(u32) cpu->acpi_perf_data.states[i].control);
481	}
482
483	cpu->valid_pss_table = true;
484	pr_debug("_PPC limits will be enforced\n");
485
486	return;
487
488	err:
489	cpu->valid_pss_table = false;
490	acpi_processor_unregister_performance(cpu: policy->cpu);
491	}
492
493	static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
494	{
495	struct cpudata *cpu;
496
497	cpu = all_cpu_data[policy->cpu];
498	if (!cpu->valid_pss_table)
499	return;
500
501	acpi_processor_unregister_performance(cpu: policy->cpu);
502	}
503	#else /* CONFIG_ACPI */
504	static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
505	{
506	}
507
508	static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
509	{
510	}
511
512	static inline bool intel_pstate_acpi_pm_profile_server(void)
513	{
514	return false;
515	}
516	#endif /* CONFIG_ACPI */
517
518	#ifndef CONFIG_ACPI_CPPC_LIB
519	static inline int intel_pstate_get_cppc_guaranteed(int cpu)
520	{
521	return -ENOTSUPP;
522	}
523
524	static int intel_pstate_cppc_get_scaling(int cpu)
525	{
526	return core_get_scaling();
527	}
528	#endif /* CONFIG_ACPI_CPPC_LIB */
529
530	static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
531	unsigned int relation)
532	{
533	if (freq == cpu->pstate.turbo_freq)
534	return cpu->pstate.turbo_pstate;
535
536	if (freq == cpu->pstate.max_freq)
537	return cpu->pstate.max_pstate;
538
539	switch (relation) {
540	case CPUFREQ_RELATION_H:
541	return freq / cpu->pstate.scaling;
542	case CPUFREQ_RELATION_C:
543	return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
544	}
545
546	return DIV_ROUND_UP(freq, cpu->pstate.scaling);
547	}
548
549	static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
550	{
551	return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
552	}
553
554	/**
555	* intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
556	* @cpu: Target CPU.
557	*
558	* On hybrid processors, HWP may expose more performance levels than there are
559	* P-states accessible through the PERF_CTL interface. If that happens, the
560	* scaling factor between HWP performance levels and CPU frequency will be less
561	* than the scaling factor between P-state values and CPU frequency.
562	*
563	* In that case, adjust the CPU parameters used in computations accordingly.
564	*/
565	static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
566	{
567	int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
568	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
569	int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
570	int scaling = cpu->pstate.scaling;
571	int freq;
572
573	pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
574	pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
575	pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
576	pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
577	pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
578	pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
579
580	cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
581	perf_ctl_scaling);
582	cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
583	perf_ctl_scaling);
584
585	freq = perf_ctl_max_phys * perf_ctl_scaling;
586	cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
587
588	freq = cpu->pstate.min_pstate * perf_ctl_scaling;
589	cpu->pstate.min_freq = freq;
590	/*
591	* Cast the min P-state value retrieved via pstate_funcs.get_min() to
592	* the effective range of HWP performance levels.
593	*/
594	cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
595	}
596
597	static inline void update_turbo_state(void)
598	{
599	u64 misc_en;
600
601	rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
602	global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
603	}
604
605	static int min_perf_pct_min(void)
606	{
607	struct cpudata *cpu = all_cpu_data[0];
608	int turbo_pstate = cpu->pstate.turbo_pstate;
609
610	return turbo_pstate ?
611	(cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
612	}
613
614	static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
615	{
616	u64 epb;
617	int ret;
618
619	if (!boot_cpu_has(X86_FEATURE_EPB))
620	return -ENXIO;
621
622	ret = rdmsrl_on_cpu(cpu: cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, q: &epb);
623	if (ret)
624	return (s16)ret;
625
626	return (s16)(epb & 0x0f);
627	}
628
629	static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
630	{
631	s16 epp;
632
633	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
634	/*
635	* When hwp_req_data is 0, means that caller didn't read
636	* MSR_HWP_REQUEST, so need to read and get EPP.
637	*/
638	if (!hwp_req_data) {
639	epp = rdmsrl_on_cpu(cpu: cpu_data->cpu, MSR_HWP_REQUEST,
640	q: &hwp_req_data);
641	if (epp)
642	return epp;
643	}
644	epp = (hwp_req_data >> 24) & 0xff;
645	} else {
646	/* When there is no EPP present, HWP uses EPB settings */
647	epp = intel_pstate_get_epb(cpu_data);
648	}
649
650	return epp;
651	}
652
653	static int intel_pstate_set_epb(int cpu, s16 pref)
654	{
655	u64 epb;
656	int ret;
657
658	if (!boot_cpu_has(X86_FEATURE_EPB))
659	return -ENXIO;
660
661	ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, q: &epb);
662	if (ret)
663	return ret;
664
665	epb = (epb & ~0x0f) | pref;
666	wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, q: epb);
667
668	return 0;
669	}
670
671	/*
672	* EPP/EPB display strings corresponding to EPP index in the
673	* energy_perf_strings[]
674	* index String
675	*-------------------------------------
676	* 0 default
677	* 1 performance
678	* 2 balance_performance
679	* 3 balance_power
680	* 4 power
681	*/
682
683	enum energy_perf_value_index {
684	EPP_INDEX_DEFAULT = 0,
685	EPP_INDEX_PERFORMANCE,
686	EPP_INDEX_BALANCE_PERFORMANCE,
687	EPP_INDEX_BALANCE_POWERSAVE,
688	EPP_INDEX_POWERSAVE,
689	};
690
691	static const char * const energy_perf_strings[] = {
692	[EPP_INDEX_DEFAULT] = "default",
693	[EPP_INDEX_PERFORMANCE] = "performance",
694	[EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
695	[EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
696	[EPP_INDEX_POWERSAVE] = "power",
697	NULL
698	};
699	static unsigned int epp_values[] = {
700	[EPP_INDEX_DEFAULT] = 0, /* Unused index */
701	[EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
702	[EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
703	[EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
704	[EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
705	};
706
707	static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
708	{
709	s16 epp;
710	int index = -EINVAL;
711
712	*raw_epp = 0;
713	epp = intel_pstate_get_epp(cpu_data, hwp_req_data: 0);
714	if (epp < 0)
715	return epp;
716
717	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
718	if (epp == epp_values[EPP_INDEX_PERFORMANCE])
719	return EPP_INDEX_PERFORMANCE;
720	if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
721	return EPP_INDEX_BALANCE_PERFORMANCE;
722	if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
723	return EPP_INDEX_BALANCE_POWERSAVE;
724	if (epp == epp_values[EPP_INDEX_POWERSAVE])
725	return EPP_INDEX_POWERSAVE;
726	*raw_epp = epp;
727	return 0;
728	} else if (boot_cpu_has(X86_FEATURE_EPB)) {
729	/*
730	* Range:
731	* 0x00-0x03 : Performance
732	* 0x04-0x07 : Balance performance
733	* 0x08-0x0B : Balance power
734	* 0x0C-0x0F : Power
735	* The EPB is a 4 bit value, but our ranges restrict the
736	* value which can be set. Here only using top two bits
737	* effectively.
738	*/
739	index = (epp >> 2) + 1;
740	}
741
742	return index;
743	}
744
745	static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
746	{
747	int ret;
748
749	/*
750	* Use the cached HWP Request MSR value, because in the active mode the
751	* register itself may be updated by intel_pstate_hwp_boost_up() or
752	* intel_pstate_hwp_boost_down() at any time.
753	*/
754	u64 value = READ_ONCE(cpu->hwp_req_cached);
755
756	value &= ~GENMASK_ULL(31, 24);
757	value |= (u64)epp << 24;
758	/*
759	* The only other updater of hwp_req_cached in the active mode,
760	* intel_pstate_hwp_set(), is called under the same lock as this
761	* function, so it cannot run in parallel with the update below.
762	*/
763	WRITE_ONCE(cpu->hwp_req_cached, value);
764	ret = wrmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_REQUEST, q: value);
765	if (!ret)
766	cpu->epp_cached = epp;
767
768	return ret;
769	}
770
771	static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
772	int pref_index, bool use_raw,
773	u32 raw_epp)
774	{
775	int epp = -EINVAL;
776	int ret;
777
778	if (!pref_index)
779	epp = cpu_data->epp_default;
780
781	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
782	if (use_raw)
783	epp = raw_epp;
784	else if (epp == -EINVAL)
785	epp = epp_values[pref_index];
786
787	/*
788	* To avoid confusion, refuse to set EPP to any values different
789	* from 0 (performance) if the current policy is "performance",
790	* because those values would be overridden.
791	*/
792	if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
793	return -EBUSY;
794
795	ret = intel_pstate_set_epp(cpu: cpu_data, epp);
796	} else {
797	if (epp == -EINVAL)
798	epp = (pref_index - 1) << 2;
799	ret = intel_pstate_set_epb(cpu: cpu_data->cpu, pref: epp);
800	}
801
802	return ret;
803	}
804
805	static ssize_t show_energy_performance_available_preferences(
806	struct cpufreq_policy *policy, char *buf)
807	{
808	int i = 0;
809	int ret = 0;
810
811	while (energy_perf_strings[i] != NULL)
812	ret += sprintf(buf: &buf[ret], fmt: "%s ", energy_perf_strings[i++]);
813
814	ret += sprintf(buf: &buf[ret], fmt: "\n");
815
816	return ret;
817	}
818
819	cpufreq_freq_attr_ro(energy_performance_available_preferences);
820
821	static struct cpufreq_driver intel_pstate;
822
823	static ssize_t store_energy_performance_preference(
824	struct cpufreq_policy *policy, const char *buf, size_t count)
825	{
826	struct cpudata *cpu = all_cpu_data[policy->cpu];
827	char str_preference[21];
828	bool raw = false;
829	ssize_t ret;
830	u32 epp = 0;
831
832	ret = sscanf(buf, "%20s", str_preference);
833	if (ret != 1)
834	return -EINVAL;
835
836	ret = match_string(array: energy_perf_strings, n: -1, string: str_preference);
837	if (ret < 0) {
838	if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
839	return ret;
840
841	ret = kstrtouint(s: buf, base: 10, res: &epp);
842	if (ret)
843	return ret;
844
845	if (epp > 255)
846	return -EINVAL;
847
848	raw = true;
849	}
850
851	/*
852	* This function runs with the policy R/W semaphore held, which
853	* guarantees that the driver pointer will not change while it is
854	* running.
855	*/
856	if (!intel_pstate_driver)
857	return -EAGAIN;
858
859	mutex_lock(&intel_pstate_limits_lock);
860
861	if (intel_pstate_driver == &intel_pstate) {
862	ret = intel_pstate_set_energy_pref_index(cpu_data: cpu, pref_index: ret, use_raw: raw, raw_epp: epp);
863	} else {
864	/*
865	* In the passive mode the governor needs to be stopped on the
866	* target CPU before the EPP update and restarted after it,
867	* which is super-heavy-weight, so make sure it is worth doing
868	* upfront.
869	*/
870	if (!raw)
871	epp = ret ? epp_values[ret] : cpu->epp_default;
872
873	if (cpu->epp_cached != epp) {
874	int err;
875
876	cpufreq_stop_governor(policy);
877	ret = intel_pstate_set_epp(cpu, epp);
878	err = cpufreq_start_governor(policy);
879	if (!ret)
880	ret = err;
881	} else {
882	ret = 0;
883	}
884	}
885
886	mutex_unlock(lock: &intel_pstate_limits_lock);
887
888	return ret ?: count;
889	}
890
891	static ssize_t show_energy_performance_preference(
892	struct cpufreq_policy *policy, char *buf)
893	{
894	struct cpudata *cpu_data = all_cpu_data[policy->cpu];
895	int preference, raw_epp;
896
897	preference = intel_pstate_get_energy_pref_index(cpu_data, raw_epp: &raw_epp);
898	if (preference < 0)
899	return preference;
900
901	if (raw_epp)
902	return sprintf(buf, fmt: "%d\n", raw_epp);
903	else
904	return sprintf(buf, fmt: "%s\n", energy_perf_strings[preference]);
905	}
906
907	cpufreq_freq_attr_rw(energy_performance_preference);
908
909	static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
910	{
911	struct cpudata *cpu = all_cpu_data[policy->cpu];
912	int ratio, freq;
913
914	ratio = intel_pstate_get_cppc_guaranteed(cpu: policy->cpu);
915	if (ratio <= 0) {
916	u64 cap;
917
918	rdmsrl_on_cpu(cpu: policy->cpu, MSR_HWP_CAPABILITIES, q: &cap);
919	ratio = HWP_GUARANTEED_PERF(cap);
920	}
921
922	freq = ratio * cpu->pstate.scaling;
923	if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
924	freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
925
926	return sprintf(buf, fmt: "%d\n", freq);
927	}
928
929	cpufreq_freq_attr_ro(base_frequency);
930
931	static struct freq_attr *hwp_cpufreq_attrs[] = {
932	&energy_performance_preference,
933	&energy_performance_available_preferences,
934	&base_frequency,
935	NULL,
936	};
937
938	static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
939	{
940	u64 cap;
941
942	rdmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_CAPABILITIES, q: &cap);
943	WRITE_ONCE(cpu->hwp_cap_cached, cap);
944	cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
945	cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
946	}
947
948	static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
949	{
950	int scaling = cpu->pstate.scaling;
951
952	__intel_pstate_get_hwp_cap(cpu);
953
954	cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
955	cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
956	if (scaling != cpu->pstate.perf_ctl_scaling) {
957	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
958
959	cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
960	perf_ctl_scaling);
961	cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
962	perf_ctl_scaling);
963	}
964	}
965
966	static void intel_pstate_hwp_set(unsigned int cpu)
967	{
968	struct cpudata *cpu_data = all_cpu_data[cpu];
969	int max, min;
970	u64 value;
971	s16 epp;
972
973	max = cpu_data->max_perf_ratio;
974	min = cpu_data->min_perf_ratio;
975
976	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
977	min = max;
978
979	rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, q: &value);
980
981	value &= ~HWP_MIN_PERF(~0L);
982	value |= HWP_MIN_PERF(min);
983
984	value &= ~HWP_MAX_PERF(~0L);
985	value |= HWP_MAX_PERF(max);
986
987	if (cpu_data->epp_policy == cpu_data->policy)
988	goto skip_epp;
989
990	cpu_data->epp_policy = cpu_data->policy;
991
992	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
993	epp = intel_pstate_get_epp(cpu_data, hwp_req_data: value);
994	cpu_data->epp_powersave = epp;
995	/* If EPP read was failed, then don't try to write */
996	if (epp < 0)
997	goto skip_epp;
998
999	epp = 0;
1000	} else {
1001	/* skip setting EPP, when saved value is invalid */
1002	if (cpu_data->epp_powersave < 0)
1003	goto skip_epp;
1004
1005	/*
1006	* No need to restore EPP when it is not zero. This
1007	* means:
1008	* - Policy is not changed
1009	* - user has manually changed
1010	* - Error reading EPB
1011	*/
1012	epp = intel_pstate_get_epp(cpu_data, hwp_req_data: value);
1013	if (epp)
1014	goto skip_epp;
1015
1016	epp = cpu_data->epp_powersave;
1017	}
1018	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1019	value &= ~GENMASK_ULL(31, 24);
1020	value |= (u64)epp << 24;
1021	} else {
1022	intel_pstate_set_epb(cpu, pref: epp);
1023	}
1024	skip_epp:
1025	WRITE_ONCE(cpu_data->hwp_req_cached, value);
1026	wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, q: value);
1027	}
1028
1029	static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1030
1031	static void intel_pstate_hwp_offline(struct cpudata *cpu)
1032	{
1033	u64 value = READ_ONCE(cpu->hwp_req_cached);
1034	int min_perf;
1035
1036	intel_pstate_disable_hwp_interrupt(cpudata: cpu);
1037
1038	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1039	/*
1040	* In case the EPP has been set to "performance" by the
1041	* active mode "performance" scaling algorithm, replace that
1042	* temporary value with the cached EPP one.
1043	*/
1044	value &= ~GENMASK_ULL(31, 24);
1045	value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1046	/*
1047	* However, make sure that EPP will be set to "performance" when
1048	* the CPU is brought back online again and the "performance"
1049	* scaling algorithm is still in effect.
1050	*/
1051	cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1052	}
1053
1054	/*
1055	* Clear the desired perf field in the cached HWP request value to
1056	* prevent nonzero desired values from being leaked into the active
1057	* mode.
1058	*/
1059	value &= ~HWP_DESIRED_PERF(~0L);
1060	WRITE_ONCE(cpu->hwp_req_cached, value);
1061
1062	value &= ~GENMASK_ULL(31, 0);
1063	min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1064
1065	/* Set hwp_max = hwp_min */
1066	value |= HWP_MAX_PERF(min_perf);
1067	value |= HWP_MIN_PERF(min_perf);
1068
1069	/* Set EPP to min */
1070	if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1071	value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1072
1073	wrmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_REQUEST, q: value);
1074	}
1075
1076	#define POWER_CTL_EE_ENABLE 1
1077	#define POWER_CTL_EE_DISABLE 2
1078
1079	static int power_ctl_ee_state;
1080
1081	static void set_power_ctl_ee_state(bool input)
1082	{
1083	u64 power_ctl;
1084
1085	mutex_lock(&intel_pstate_driver_lock);
1086	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1087	if (input) {
1088	power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1089	power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1090	} else {
1091	power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1092	power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1093	}
1094	wrmsrl(MSR_IA32_POWER_CTL, val: power_ctl);
1095	mutex_unlock(lock: &intel_pstate_driver_lock);
1096	}
1097
1098	static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1099
1100	static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1101	{
1102	intel_pstate_hwp_enable(cpudata: cpu);
1103	wrmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1104	}
1105
1106	static int intel_pstate_suspend(struct cpufreq_policy *policy)
1107	{
1108	struct cpudata *cpu = all_cpu_data[policy->cpu];
1109
1110	pr_debug("CPU %d suspending\n", cpu->cpu);
1111
1112	cpu->suspended = true;
1113
1114	/* disable HWP interrupt and cancel any pending work */
1115	intel_pstate_disable_hwp_interrupt(cpudata: cpu);
1116
1117	return 0;
1118	}
1119
1120	static int intel_pstate_resume(struct cpufreq_policy *policy)
1121	{
1122	struct cpudata *cpu = all_cpu_data[policy->cpu];
1123
1124	pr_debug("CPU %d resuming\n", cpu->cpu);
1125
1126	/* Only restore if the system default is changed */
1127	if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1128	set_power_ctl_ee_state(true);
1129	else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1130	set_power_ctl_ee_state(false);
1131
1132	if (cpu->suspended && hwp_active) {
1133	mutex_lock(&intel_pstate_limits_lock);
1134
1135	/* Re-enable HWP, because "online" has not done that. */
1136	intel_pstate_hwp_reenable(cpu);
1137
1138	mutex_unlock(lock: &intel_pstate_limits_lock);
1139	}
1140
1141	cpu->suspended = false;
1142
1143	return 0;
1144	}
1145
1146	static void intel_pstate_update_policies(void)
1147	{
1148	int cpu;
1149
1150	for_each_possible_cpu(cpu)
1151	cpufreq_update_policy(cpu);
1152	}
1153
1154	static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1155	struct cpufreq_policy *policy)
1156	{
1157	policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1158	cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1159	refresh_frequency_limits(policy);
1160	}
1161
1162	static void intel_pstate_update_max_freq(unsigned int cpu)
1163	{
1164	struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1165
1166	if (!policy)
1167	return;
1168
1169	__intel_pstate_update_max_freq(cpudata: all_cpu_data[cpu], policy);
1170
1171	cpufreq_cpu_release(policy);
1172	}
1173
1174	static void intel_pstate_update_limits(unsigned int cpu)
1175	{
1176	mutex_lock(&intel_pstate_driver_lock);
1177
1178	update_turbo_state();
1179	/*
1180	* If turbo has been turned on or off globally, policy limits for
1181	* all CPUs need to be updated to reflect that.
1182	*/
1183	if (global.turbo_disabled_mf != global.turbo_disabled) {
1184	global.turbo_disabled_mf = global.turbo_disabled;
1185	arch_set_max_freq_ratio(turbo_disabled: global.turbo_disabled);
1186	for_each_possible_cpu(cpu)
1187	intel_pstate_update_max_freq(cpu);
1188	} else {
1189	cpufreq_update_policy(cpu);
1190	}
1191
1192	mutex_unlock(lock: &intel_pstate_driver_lock);
1193	}
1194
1195	/************************** sysfs begin ************************/
1196	#define show_one(file_name, object) \
1197	static ssize_t show_##file_name \
1198	(struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1199	{ \
1200	return sprintf(buf, "%u\n", global.object); \
1201	}
1202
1203	static ssize_t intel_pstate_show_status(char *buf);
1204	static int intel_pstate_update_status(const char *buf, size_t size);
1205
1206	static ssize_t show_status(struct kobject *kobj,
1207	struct kobj_attribute *attr, char *buf)
1208	{
1209	ssize_t ret;
1210
1211	mutex_lock(&intel_pstate_driver_lock);
1212	ret = intel_pstate_show_status(buf);
1213	mutex_unlock(lock: &intel_pstate_driver_lock);
1214
1215	return ret;
1216	}
1217
1218	static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1219	const char *buf, size_t count)
1220	{
1221	char *p = memchr(p: buf, c: '\n', size: count);
1222	int ret;
1223
1224	mutex_lock(&intel_pstate_driver_lock);
1225	ret = intel_pstate_update_status(buf, size: p ? p - buf : count);
1226	mutex_unlock(lock: &intel_pstate_driver_lock);
1227
1228	return ret < 0 ? ret : count;
1229	}
1230
1231	static ssize_t show_turbo_pct(struct kobject *kobj,
1232	struct kobj_attribute *attr, char *buf)
1233	{
1234	struct cpudata *cpu;
1235	int total, no_turbo, turbo_pct;
1236	uint32_t turbo_fp;
1237
1238	mutex_lock(&intel_pstate_driver_lock);
1239
1240	if (!intel_pstate_driver) {
1241	mutex_unlock(lock: &intel_pstate_driver_lock);
1242	return -EAGAIN;
1243	}
1244
1245	cpu = all_cpu_data[0];
1246
1247	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1248	no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1249	turbo_fp = div_fp(x: no_turbo, y: total);
1250	turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1251
1252	mutex_unlock(lock: &intel_pstate_driver_lock);
1253
1254	return sprintf(buf, fmt: "%u\n", turbo_pct);
1255	}
1256
1257	static ssize_t show_num_pstates(struct kobject *kobj,
1258	struct kobj_attribute *attr, char *buf)
1259	{
1260	struct cpudata *cpu;
1261	int total;
1262
1263	mutex_lock(&intel_pstate_driver_lock);
1264
1265	if (!intel_pstate_driver) {
1266	mutex_unlock(lock: &intel_pstate_driver_lock);
1267	return -EAGAIN;
1268	}
1269
1270	cpu = all_cpu_data[0];
1271	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1272
1273	mutex_unlock(lock: &intel_pstate_driver_lock);
1274
1275	return sprintf(buf, fmt: "%u\n", total);
1276	}
1277
1278	static ssize_t show_no_turbo(struct kobject *kobj,
1279	struct kobj_attribute *attr, char *buf)
1280	{
1281	ssize_t ret;
1282
1283	mutex_lock(&intel_pstate_driver_lock);
1284
1285	if (!intel_pstate_driver) {
1286	mutex_unlock(lock: &intel_pstate_driver_lock);
1287	return -EAGAIN;
1288	}
1289
1290	update_turbo_state();
1291	if (global.turbo_disabled)
1292	ret = sprintf(buf, fmt: "%u\n", global.turbo_disabled);
1293	else
1294	ret = sprintf(buf, fmt: "%u\n", global.no_turbo);
1295
1296	mutex_unlock(lock: &intel_pstate_driver_lock);
1297
1298	return ret;
1299	}
1300
1301	static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1302	const char *buf, size_t count)
1303	{
1304	unsigned int input;
1305	int ret;
1306
1307	ret = sscanf(buf, "%u", &input);
1308	if (ret != 1)
1309	return -EINVAL;
1310
1311	mutex_lock(&intel_pstate_driver_lock);
1312
1313	if (!intel_pstate_driver) {
1314	mutex_unlock(lock: &intel_pstate_driver_lock);
1315	return -EAGAIN;
1316	}
1317
1318	mutex_lock(&intel_pstate_limits_lock);
1319
1320	update_turbo_state();
1321	if (global.turbo_disabled) {
1322	pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1323	mutex_unlock(lock: &intel_pstate_limits_lock);
1324	mutex_unlock(lock: &intel_pstate_driver_lock);
1325	return -EPERM;
1326	}
1327
1328	global.no_turbo = clamp_t(int, input, 0, 1);
1329
1330	if (global.no_turbo) {
1331	struct cpudata *cpu = all_cpu_data[0];
1332	int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1333
1334	/* Squash the global minimum into the permitted range. */
1335	if (global.min_perf_pct > pct)
1336	global.min_perf_pct = pct;
1337	}
1338
1339	mutex_unlock(lock: &intel_pstate_limits_lock);
1340
1341	intel_pstate_update_policies();
1342	arch_set_max_freq_ratio(turbo_disabled: global.no_turbo);
1343
1344	mutex_unlock(lock: &intel_pstate_driver_lock);
1345
1346	return count;
1347	}
1348
1349	static void update_qos_request(enum freq_qos_req_type type)
1350	{
1351	struct freq_qos_request *req;
1352	struct cpufreq_policy *policy;
1353	int i;
1354
1355	for_each_possible_cpu(i) {
1356	struct cpudata *cpu = all_cpu_data[i];
1357	unsigned int freq, perf_pct;
1358
1359	policy = cpufreq_cpu_get(cpu: i);
1360	if (!policy)
1361	continue;
1362
1363	req = policy->driver_data;
1364	cpufreq_cpu_put(policy);
1365
1366	if (!req)
1367	continue;
1368
1369	if (hwp_active)
1370	intel_pstate_get_hwp_cap(cpu);
1371
1372	if (type == FREQ_QOS_MIN) {
1373	perf_pct = global.min_perf_pct;
1374	} else {
1375	req++;
1376	perf_pct = global.max_perf_pct;
1377	}
1378
1379	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1380
1381	if (freq_qos_update_request(req, new_value: freq) < 0)
1382	pr_warn("Failed to update freq constraint: CPU%d\n", i);
1383	}
1384	}
1385
1386	static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1387	const char *buf, size_t count)
1388	{
1389	unsigned int input;
1390	int ret;
1391
1392	ret = sscanf(buf, "%u", &input);
1393	if (ret != 1)
1394	return -EINVAL;
1395
1396	mutex_lock(&intel_pstate_driver_lock);
1397
1398	if (!intel_pstate_driver) {
1399	mutex_unlock(lock: &intel_pstate_driver_lock);
1400	return -EAGAIN;
1401	}
1402
1403	mutex_lock(&intel_pstate_limits_lock);
1404
1405	global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1406
1407	mutex_unlock(lock: &intel_pstate_limits_lock);
1408
1409	if (intel_pstate_driver == &intel_pstate)
1410	intel_pstate_update_policies();
1411	else
1412	update_qos_request(type: FREQ_QOS_MAX);
1413
1414	mutex_unlock(lock: &intel_pstate_driver_lock);
1415
1416	return count;
1417	}
1418
1419	static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1420	const char *buf, size_t count)
1421	{
1422	unsigned int input;
1423	int ret;
1424
1425	ret = sscanf(buf, "%u", &input);
1426	if (ret != 1)
1427	return -EINVAL;
1428
1429	mutex_lock(&intel_pstate_driver_lock);
1430
1431	if (!intel_pstate_driver) {
1432	mutex_unlock(lock: &intel_pstate_driver_lock);
1433	return -EAGAIN;
1434	}
1435
1436	mutex_lock(&intel_pstate_limits_lock);
1437
1438	global.min_perf_pct = clamp_t(int, input,
1439	min_perf_pct_min(), global.max_perf_pct);
1440
1441	mutex_unlock(lock: &intel_pstate_limits_lock);
1442
1443	if (intel_pstate_driver == &intel_pstate)
1444	intel_pstate_update_policies();
1445	else
1446	update_qos_request(type: FREQ_QOS_MIN);
1447
1448	mutex_unlock(lock: &intel_pstate_driver_lock);
1449
1450	return count;
1451	}
1452
1453	static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1454	struct kobj_attribute *attr, char *buf)
1455	{
1456	return sprintf(buf, fmt: "%u\n", hwp_boost);
1457	}
1458
1459	static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1460	struct kobj_attribute *b,
1461	const char *buf, size_t count)
1462	{
1463	unsigned int input;
1464	int ret;
1465
1466	ret = kstrtouint(s: buf, base: 10, res: &input);
1467	if (ret)
1468	return ret;
1469
1470	mutex_lock(&intel_pstate_driver_lock);
1471	hwp_boost = !!input;
1472	intel_pstate_update_policies();
1473	mutex_unlock(lock: &intel_pstate_driver_lock);
1474
1475	return count;
1476	}
1477
1478	static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1479	char *buf)
1480	{
1481	u64 power_ctl;
1482	int enable;
1483
1484	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1485	enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1486	return sprintf(buf, fmt: "%d\n", !enable);
1487	}
1488
1489	static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1490	const char *buf, size_t count)
1491	{
1492	bool input;
1493	int ret;
1494
1495	ret = kstrtobool(s: buf, res: &input);
1496	if (ret)
1497	return ret;
1498
1499	set_power_ctl_ee_state(input);
1500
1501	return count;
1502	}
1503
1504	show_one(max_perf_pct, max_perf_pct);
1505	show_one(min_perf_pct, min_perf_pct);
1506
1507	define_one_global_rw(status);
1508	define_one_global_rw(no_turbo);
1509	define_one_global_rw(max_perf_pct);
1510	define_one_global_rw(min_perf_pct);
1511	define_one_global_ro(turbo_pct);
1512	define_one_global_ro(num_pstates);
1513	define_one_global_rw(hwp_dynamic_boost);
1514	define_one_global_rw(energy_efficiency);
1515
1516	static struct attribute *intel_pstate_attributes[] = {
1517	&status.attr,
1518	&no_turbo.attr,
1519	NULL
1520	};
1521
1522	static const struct attribute_group intel_pstate_attr_group = {
1523	.attrs = intel_pstate_attributes,
1524	};
1525
1526	static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1527
1528	static struct kobject *intel_pstate_kobject;
1529
1530	static void __init intel_pstate_sysfs_expose_params(void)
1531	{
1532	struct device *dev_root = bus_get_dev_root(bus: &cpu_subsys);
1533	int rc;
1534
1535	if (dev_root) {
1536	intel_pstate_kobject = kobject_create_and_add(name: "intel_pstate", parent: &dev_root->kobj);
1537	put_device(dev: dev_root);
1538	}
1539	if (WARN_ON(!intel_pstate_kobject))
1540	return;
1541
1542	rc = sysfs_create_group(kobj: intel_pstate_kobject, grp: &intel_pstate_attr_group);
1543	if (WARN_ON(rc))
1544	return;
1545
1546	if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1547	rc = sysfs_create_file(kobj: intel_pstate_kobject, attr: &turbo_pct.attr);
1548	WARN_ON(rc);
1549
1550	rc = sysfs_create_file(kobj: intel_pstate_kobject, attr: &num_pstates.attr);
1551	WARN_ON(rc);
1552	}
1553
1554	/*
1555	* If per cpu limits are enforced there are no global limits, so
1556	* return without creating max/min_perf_pct attributes
1557	*/
1558	if (per_cpu_limits)
1559	return;
1560
1561	rc = sysfs_create_file(kobj: intel_pstate_kobject, attr: &max_perf_pct.attr);
1562	WARN_ON(rc);
1563
1564	rc = sysfs_create_file(kobj: intel_pstate_kobject, attr: &min_perf_pct.attr);
1565	WARN_ON(rc);
1566
1567	if (x86_match_cpu(match: intel_pstate_cpu_ee_disable_ids)) {
1568	rc = sysfs_create_file(kobj: intel_pstate_kobject, attr: &energy_efficiency.attr);
1569	WARN_ON(rc);
1570	}
1571	}
1572
1573	static void __init intel_pstate_sysfs_remove(void)
1574	{
1575	if (!intel_pstate_kobject)
1576	return;
1577
1578	sysfs_remove_group(kobj: intel_pstate_kobject, grp: &intel_pstate_attr_group);
1579
1580	if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1581	sysfs_remove_file(kobj: intel_pstate_kobject, attr: &num_pstates.attr);
1582	sysfs_remove_file(kobj: intel_pstate_kobject, attr: &turbo_pct.attr);
1583	}
1584
1585	if (!per_cpu_limits) {
1586	sysfs_remove_file(kobj: intel_pstate_kobject, attr: &max_perf_pct.attr);
1587	sysfs_remove_file(kobj: intel_pstate_kobject, attr: &min_perf_pct.attr);
1588
1589	if (x86_match_cpu(match: intel_pstate_cpu_ee_disable_ids))
1590	sysfs_remove_file(kobj: intel_pstate_kobject, attr: &energy_efficiency.attr);
1591	}
1592
1593	kobject_put(kobj: intel_pstate_kobject);
1594	}
1595
1596	static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1597	{
1598	int rc;
1599
1600	if (!hwp_active)
1601	return;
1602
1603	rc = sysfs_create_file(kobj: intel_pstate_kobject, attr: &hwp_dynamic_boost.attr);
1604	WARN_ON_ONCE(rc);
1605	}
1606
1607	static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1608	{
1609	if (!hwp_active)
1610	return;
1611
1612	sysfs_remove_file(kobj: intel_pstate_kobject, attr: &hwp_dynamic_boost.attr);
1613	}
1614
1615	/************************** sysfs end ************************/
1616
1617	static void intel_pstate_notify_work(struct work_struct *work)
1618	{
1619	struct cpudata *cpudata =
1620	container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1621	struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu: cpudata->cpu);
1622
1623	if (policy) {
1624	intel_pstate_get_hwp_cap(cpu: cpudata);
1625	__intel_pstate_update_max_freq(cpudata, policy);
1626
1627	cpufreq_cpu_release(policy);
1628	}
1629
1630	wrmsrl_on_cpu(cpu: cpudata->cpu, MSR_HWP_STATUS, q: 0);
1631	}
1632
1633	static DEFINE_SPINLOCK(hwp_notify_lock);
1634	static cpumask_t hwp_intr_enable_mask;
1635
1636	void notify_hwp_interrupt(void)
1637	{
1638	unsigned int this_cpu = smp_processor_id();
1639	struct cpudata *cpudata;
1640	unsigned long flags;
1641	u64 value;
1642
1643	if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1644	return;
1645
1646	rdmsrl_safe(MSR_HWP_STATUS, p: &value);
1647	if (!(value & 0x01))
1648	return;
1649
1650	spin_lock_irqsave(&hwp_notify_lock, flags);
1651
1652	if (!cpumask_test_cpu(cpu: this_cpu, cpumask: &hwp_intr_enable_mask))
1653	goto ack_intr;
1654
1655	/*
1656	* Currently we never free all_cpu_data. And we can't reach here
1657	* without this allocated. But for safety for future changes, added
1658	* check.
1659	*/
1660	if (unlikely(!READ_ONCE(all_cpu_data)))
1661	goto ack_intr;
1662
1663	/*
1664	* The free is done during cleanup, when cpufreq registry is failed.
1665	* We wouldn't be here if it fails on init or switch status. But for
1666	* future changes, added check.
1667	*/
1668	cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1669	if (unlikely(!cpudata))
1670	goto ack_intr;
1671
1672	schedule_delayed_work(dwork: &cpudata->hwp_notify_work, delay: msecs_to_jiffies(m: 10));
1673
1674	spin_unlock_irqrestore(lock: &hwp_notify_lock, flags);
1675
1676	return;
1677
1678	ack_intr:
1679	wrmsrl_safe(MSR_HWP_STATUS, val: 0);
1680	spin_unlock_irqrestore(lock: &hwp_notify_lock, flags);
1681	}
1682
1683	static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1684	{
1685	unsigned long flags;
1686
1687	if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1688	return;
1689
1690	/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1691	wrmsrl_on_cpu(cpu: cpudata->cpu, MSR_HWP_INTERRUPT, q: 0x00);
1692
1693	spin_lock_irqsave(&hwp_notify_lock, flags);
1694	if (cpumask_test_and_clear_cpu(cpu: cpudata->cpu, cpumask: &hwp_intr_enable_mask))
1695	cancel_delayed_work(dwork: &cpudata->hwp_notify_work);
1696	spin_unlock_irqrestore(lock: &hwp_notify_lock, flags);
1697	}
1698
1699	static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1700	{
1701	/* Enable HWP notification interrupt for guaranteed performance change */
1702	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1703	unsigned long flags;
1704
1705	spin_lock_irqsave(&hwp_notify_lock, flags);
1706	INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1707	cpumask_set_cpu(cpu: cpudata->cpu, dstp: &hwp_intr_enable_mask);
1708	spin_unlock_irqrestore(lock: &hwp_notify_lock, flags);
1709
1710	/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1711	wrmsrl_on_cpu(cpu: cpudata->cpu, MSR_HWP_INTERRUPT, q: 0x01);
1712	wrmsrl_on_cpu(cpu: cpudata->cpu, MSR_HWP_STATUS, q: 0);
1713	}
1714	}
1715
1716	static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1717	{
1718	cpudata->epp_default = intel_pstate_get_epp(cpu_data: cpudata, hwp_req_data: 0);
1719
1720	/*
1721	* If the EPP is set by firmware, which means that firmware enabled HWP
1722	* - Is equal or less than 0x80 (default balance_perf EPP)
1723	* - But less performance oriented than performance EPP
1724	* then use this as new balance_perf EPP.
1725	*/
1726	if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1727	cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1728	epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1729	return;
1730	}
1731
1732	/*
1733	* If this CPU gen doesn't call for change in balance_perf
1734	* EPP return.
1735	*/
1736	if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1737	return;
1738
1739	/*
1740	* Use hard coded value per gen to update the balance_perf
1741	* and default EPP.
1742	*/
1743	cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1744	intel_pstate_set_epp(cpu: cpudata, epp: cpudata->epp_default);
1745	}
1746
1747	static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1748	{
1749	/* First disable HWP notification interrupt till we activate again */
1750	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1751	wrmsrl_on_cpu(cpu: cpudata->cpu, MSR_HWP_INTERRUPT, q: 0x00);
1752
1753	wrmsrl_on_cpu(cpu: cpudata->cpu, MSR_PM_ENABLE, q: 0x1);
1754
1755	intel_pstate_enable_hwp_interrupt(cpudata);
1756
1757	if (cpudata->epp_default >= 0)
1758	return;
1759
1760	intel_pstate_update_epp_defaults(cpudata);
1761	}
1762
1763	static int atom_get_min_pstate(int not_used)
1764	{
1765	u64 value;
1766
1767	rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1768	return (value >> 8) & 0x7F;
1769	}
1770
1771	static int atom_get_max_pstate(int not_used)
1772	{
1773	u64 value;
1774
1775	rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1776	return (value >> 16) & 0x7F;
1777	}
1778
1779	static int atom_get_turbo_pstate(int not_used)
1780	{
1781	u64 value;
1782
1783	rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1784	return value & 0x7F;
1785	}
1786
1787	static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1788	{
1789	u64 val;
1790	int32_t vid_fp;
1791	u32 vid;
1792
1793	val = (u64)pstate << 8;
1794	if (global.no_turbo && !global.turbo_disabled)
1795	val |= (u64)1 << 32;
1796
1797	vid_fp = cpudata->vid.min + mul_fp(
1798	int_tofp(pstate - cpudata->pstate.min_pstate),
1799	y: cpudata->vid.ratio);
1800
1801	vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1802	vid = ceiling_fp(x: vid_fp);
1803
1804	if (pstate > cpudata->pstate.max_pstate)
1805	vid = cpudata->vid.turbo;
1806
1807	return val | vid;
1808	}
1809
1810	static int silvermont_get_scaling(void)
1811	{
1812	u64 value;
1813	int i;
1814	/* Defined in Table 35-6 from SDM (Sept 2015) */
1815	static int silvermont_freq_table[] = {
1816	83300, 100000, 133300, 116700, 80000};
1817
1818	rdmsrl(MSR_FSB_FREQ, value);
1819	i = value & 0x7;
1820	WARN_ON(i > 4);
1821
1822	return silvermont_freq_table[i];
1823	}
1824
1825	static int airmont_get_scaling(void)
1826	{
1827	u64 value;
1828	int i;
1829	/* Defined in Table 35-10 from SDM (Sept 2015) */
1830	static int airmont_freq_table[] = {
1831	83300, 100000, 133300, 116700, 80000,
1832	93300, 90000, 88900, 87500};
1833
1834	rdmsrl(MSR_FSB_FREQ, value);
1835	i = value & 0xF;
1836	WARN_ON(i > 8);
1837
1838	return airmont_freq_table[i];
1839	}
1840
1841	static void atom_get_vid(struct cpudata *cpudata)
1842	{
1843	u64 value;
1844
1845	rdmsrl(MSR_ATOM_CORE_VIDS, value);
1846	cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1847	cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1848	cpudata->vid.ratio = div_fp(
1849	x: cpudata->vid.max - cpudata->vid.min,
1850	int_tofp(cpudata->pstate.max_pstate -
1851	cpudata->pstate.min_pstate));
1852
1853	rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1854	cpudata->vid.turbo = value & 0x7f;
1855	}
1856
1857	static int core_get_min_pstate(int cpu)
1858	{
1859	u64 value;
1860
1861	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, q: &value);
1862	return (value >> 40) & 0xFF;
1863	}
1864
1865	static int core_get_max_pstate_physical(int cpu)
1866	{
1867	u64 value;
1868
1869	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, q: &value);
1870	return (value >> 8) & 0xFF;
1871	}
1872
1873	static int core_get_tdp_ratio(int cpu, u64 plat_info)
1874	{
1875	/* Check how many TDP levels present */
1876	if (plat_info & 0x600000000) {
1877	u64 tdp_ctrl;
1878	u64 tdp_ratio;
1879	int tdp_msr;
1880	int err;
1881
1882	/* Get the TDP level (0, 1, 2) to get ratios */
1883	err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, q: &tdp_ctrl);
1884	if (err)
1885	return err;
1886
1887	/* TDP MSR are continuous starting at 0x648 */
1888	tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1889	err = rdmsrl_safe_on_cpu(cpu, msr_no: tdp_msr, q: &tdp_ratio);
1890	if (err)
1891	return err;
1892
1893	/* For level 1 and 2, bits[23:16] contain the ratio */
1894	if (tdp_ctrl & 0x03)
1895	tdp_ratio >>= 16;
1896
1897	tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1898	pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1899
1900	return (int)tdp_ratio;
1901	}
1902
1903	return -ENXIO;
1904	}
1905
1906	static int core_get_max_pstate(int cpu)
1907	{
1908	u64 tar;
1909	u64 plat_info;
1910	int max_pstate;
1911	int tdp_ratio;
1912	int err;
1913
1914	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, q: &plat_info);
1915	max_pstate = (plat_info >> 8) & 0xFF;
1916
1917	tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1918	if (tdp_ratio <= 0)
1919	return max_pstate;
1920
1921	if (hwp_active) {
1922	/* Turbo activation ratio is not used on HWP platforms */
1923	return tdp_ratio;
1924	}
1925
1926	err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, q: &tar);
1927	if (!err) {
1928	int tar_levels;
1929
1930	/* Do some sanity checking for safety */
1931	tar_levels = tar & 0xff;
1932	if (tdp_ratio - 1 == tar_levels) {
1933	max_pstate = tar_levels;
1934	pr_debug("max_pstate=TAC %x\n", max_pstate);
1935	}
1936	}
1937
1938	return max_pstate;
1939	}
1940
1941	static int core_get_turbo_pstate(int cpu)
1942	{
1943	u64 value;
1944	int nont, ret;
1945
1946	rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, q: &value);
1947	nont = core_get_max_pstate(cpu);
1948	ret = (value) & 255;
1949	if (ret <= nont)
1950	ret = nont;
1951	return ret;
1952	}
1953
1954	static u64 core_get_val(struct cpudata *cpudata, int pstate)
1955	{
1956	u64 val;
1957
1958	val = (u64)pstate << 8;
1959	if (global.no_turbo && !global.turbo_disabled)
1960	val |= (u64)1 << 32;
1961
1962	return val;
1963	}
1964
1965	static int knl_get_aperf_mperf_shift(void)
1966	{
1967	return 10;
1968	}
1969
1970	static int knl_get_turbo_pstate(int cpu)
1971	{
1972	u64 value;
1973	int nont, ret;
1974
1975	rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, q: &value);
1976	nont = core_get_max_pstate(cpu);
1977	ret = (((value) >> 8) & 0xFF);
1978	if (ret <= nont)
1979	ret = nont;
1980	return ret;
1981	}
1982
1983	static void hybrid_get_type(void *data)
1984	{
1985	u8 *cpu_type = data;
1986
1987	*cpu_type = get_this_hybrid_cpu_type();
1988	}
1989
1990	static int hwp_get_cpu_scaling(int cpu)
1991	{
1992	u8 cpu_type = 0;
1993
1994	smp_call_function_single(cpuid: cpu, func: hybrid_get_type, info: &cpu_type, wait: 1);
1995	/* P-cores have a smaller perf level-to-freqency scaling factor. */
1996	if (cpu_type == 0x40)
1997	return hybrid_scaling_factor;
1998
1999	/* Use default core scaling for E-cores */
2000	if (cpu_type == 0x20)
2001	return core_get_scaling();
2002
2003	/*
2004	* If reached here, this system is either non-hybrid (like Tiger
2005	* Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2006	* no E cores (in which case CPUID for hybrid support is 0).
2007	*
2008	* The CPPC nominal_frequency field is 0 for non-hybrid systems,
2009	* so the default core scaling will be used for them.
2010	*/
2011	return intel_pstate_cppc_get_scaling(cpu);
2012	}
2013
2014	static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2015	{
2016	trace_cpu_frequency(frequency: pstate * cpu->pstate.scaling, cpu_id: cpu->cpu);
2017	cpu->pstate.current_pstate = pstate;
2018	/*
2019	* Generally, there is no guarantee that this code will always run on
2020	* the CPU being updated, so force the register update to run on the
2021	* right CPU.
2022	*/
2023	wrmsrl_on_cpu(cpu: cpu->cpu, MSR_IA32_PERF_CTL,
2024	q: pstate_funcs.get_val(cpu, pstate));
2025	}
2026
2027	static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2028	{
2029	intel_pstate_set_pstate(cpu, pstate: cpu->pstate.min_pstate);
2030	}
2031
2032	static void intel_pstate_max_within_limits(struct cpudata *cpu)
2033	{
2034	int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2035
2036	update_turbo_state();
2037	intel_pstate_set_pstate(cpu, pstate);
2038	}
2039
2040	static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2041	{
2042	int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2043	int perf_ctl_scaling = pstate_funcs.get_scaling();
2044
2045	cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2046	cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2047	cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2048
2049	if (hwp_active && !hwp_mode_bdw) {
2050	__intel_pstate_get_hwp_cap(cpu);
2051
2052	if (pstate_funcs.get_cpu_scaling) {
2053	cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2054	if (cpu->pstate.scaling != perf_ctl_scaling)
2055	intel_pstate_hybrid_hwp_adjust(cpu);
2056	} else {
2057	cpu->pstate.scaling = perf_ctl_scaling;
2058	}
2059	} else {
2060	cpu->pstate.scaling = perf_ctl_scaling;
2061	cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2062	cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2063	}
2064
2065	if (cpu->pstate.scaling == perf_ctl_scaling) {
2066	cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2067	cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2068	cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2069	}
2070
2071	if (pstate_funcs.get_aperf_mperf_shift)
2072	cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2073
2074	if (pstate_funcs.get_vid)
2075	pstate_funcs.get_vid(cpu);
2076
2077	intel_pstate_set_min_pstate(cpu);
2078	}
2079
2080	/*
2081	* Long hold time will keep high perf limits for long time,
2082	* which negatively impacts perf/watt for some workloads,
2083	* like specpower. 3ms is based on experiements on some
2084	* workoads.
2085	*/
2086	static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2087
2088	static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2089	{
2090	u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2091	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2092	u32 max_limit = (hwp_req & 0xff00) >> 8;
2093	u32 min_limit = (hwp_req & 0xff);
2094	u32 boost_level1;
2095
2096	/*
2097	* Cases to consider (User changes via sysfs or boot time):
2098	* If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2099	* No boost, return.
2100	* If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2101	* Should result in one level boost only for P0.
2102	* If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2103	* Should result in two level boost:
2104	* (min + p1)/2 and P1.
2105	* If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2106	* Should result in three level boost:
2107	* (min + p1)/2, P1 and P0.
2108	*/
2109
2110	/* If max and min are equal or already at max, nothing to boost */
2111	if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2112	return;
2113
2114	if (!cpu->hwp_boost_min)
2115	cpu->hwp_boost_min = min_limit;
2116
2117	/* level at half way mark between min and guranteed */
2118	boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2119
2120	if (cpu->hwp_boost_min < boost_level1)
2121	cpu->hwp_boost_min = boost_level1;
2122	else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2123	cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2124	else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2125	max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2126	cpu->hwp_boost_min = max_limit;
2127	else
2128	return;
2129
2130	hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2131	wrmsrl(MSR_HWP_REQUEST, val: hwp_req);
2132	cpu->last_update = cpu->sample.time;
2133	}
2134
2135	static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2136	{
2137	if (cpu->hwp_boost_min) {
2138	bool expired;
2139
2140	/* Check if we are idle for hold time to boost down */
2141	expired = time_after64(cpu->sample.time, cpu->last_update +
2142	hwp_boost_hold_time_ns);
2143	if (expired) {
2144	wrmsrl(MSR_HWP_REQUEST, val: cpu->hwp_req_cached);
2145	cpu->hwp_boost_min = 0;
2146	}
2147	}
2148	cpu->last_update = cpu->sample.time;
2149	}
2150
2151	static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2152	u64 time)
2153	{
2154	cpu->sample.time = time;
2155
2156	if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2157	bool do_io = false;
2158
2159	cpu->sched_flags = 0;
2160	/*
2161	* Set iowait_boost flag and update time. Since IO WAIT flag
2162	* is set all the time, we can't just conclude that there is
2163	* some IO bound activity is scheduled on this CPU with just
2164	* one occurrence. If we receive at least two in two
2165	* consecutive ticks, then we treat as boost candidate.
2166	*/
2167	if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2168	do_io = true;
2169
2170	cpu->last_io_update = time;
2171
2172	if (do_io)
2173	intel_pstate_hwp_boost_up(cpu);
2174
2175	} else {
2176	intel_pstate_hwp_boost_down(cpu);
2177	}
2178	}
2179
2180	static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2181	u64 time, unsigned int flags)
2182	{
2183	struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2184
2185	cpu->sched_flags |= flags;
2186
2187	if (smp_processor_id() == cpu->cpu)
2188	intel_pstate_update_util_hwp_local(cpu, time);
2189	}
2190
2191	static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2192	{
2193	struct sample *sample = &cpu->sample;
2194
2195	sample->core_avg_perf = div_ext_fp(x: sample->aperf, y: sample->mperf);
2196	}
2197
2198	static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2199	{
2200	u64 aperf, mperf;
2201	unsigned long flags;
2202	u64 tsc;
2203
2204	local_irq_save(flags);
2205	rdmsrl(MSR_IA32_APERF, aperf);
2206	rdmsrl(MSR_IA32_MPERF, mperf);
2207	tsc = rdtsc();
2208	if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2209	local_irq_restore(flags);
2210	return false;
2211	}
2212	local_irq_restore(flags);
2213
2214	cpu->last_sample_time = cpu->sample.time;
2215	cpu->sample.time = time;
2216	cpu->sample.aperf = aperf;
2217	cpu->sample.mperf = mperf;
2218	cpu->sample.tsc = tsc;
2219	cpu->sample.aperf -= cpu->prev_aperf;
2220	cpu->sample.mperf -= cpu->prev_mperf;
2221	cpu->sample.tsc -= cpu->prev_tsc;
2222
2223	cpu->prev_aperf = aperf;
2224	cpu->prev_mperf = mperf;
2225	cpu->prev_tsc = tsc;
2226	/*
2227	* First time this function is invoked in a given cycle, all of the
2228	* previous sample data fields are equal to zero or stale and they must
2229	* be populated with meaningful numbers for things to work, so assume
2230	* that sample.time will always be reset before setting the utilization
2231	* update hook and make the caller skip the sample then.
2232	*/
2233	if (cpu->last_sample_time) {
2234	intel_pstate_calc_avg_perf(cpu);
2235	return true;
2236	}
2237	return false;
2238	}
2239
2240	static inline int32_t get_avg_frequency(struct cpudata *cpu)
2241	{
2242	return mul_ext_fp(x: cpu->sample.core_avg_perf, y: cpu_khz);
2243	}
2244
2245	static inline int32_t get_avg_pstate(struct cpudata *cpu)
2246	{
2247	return mul_ext_fp(x: cpu->pstate.max_pstate_physical,
2248	y: cpu->sample.core_avg_perf);
2249	}
2250
2251	static inline int32_t get_target_pstate(struct cpudata *cpu)
2252	{
2253	struct sample *sample = &cpu->sample;
2254	int32_t busy_frac;
2255	int target, avg_pstate;
2256
2257	busy_frac = div_fp(x: sample->mperf << cpu->aperf_mperf_shift,
2258	y: sample->tsc);
2259
2260	if (busy_frac < cpu->iowait_boost)
2261	busy_frac = cpu->iowait_boost;
2262
2263	sample->busy_scaled = busy_frac * 100;
2264
2265	target = global.no_turbo || global.turbo_disabled ?
2266	cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2267	target += target >> 2;
2268	target = mul_fp(x: target, y: busy_frac);
2269	if (target < cpu->pstate.min_pstate)
2270	target = cpu->pstate.min_pstate;
2271
2272	/*
2273	* If the average P-state during the previous cycle was higher than the
2274	* current target, add 50% of the difference to the target to reduce
2275	* possible performance oscillations and offset possible performance
2276	* loss related to moving the workload from one CPU to another within
2277	* a package/module.
2278	*/
2279	avg_pstate = get_avg_pstate(cpu);
2280	if (avg_pstate > target)
2281	target += (avg_pstate - target) >> 1;
2282
2283	return target;
2284	}
2285
2286	static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2287	{
2288	int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2289	int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2290
2291	return clamp_t(int, pstate, min_pstate, max_pstate);
2292	}
2293
2294	static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2295	{
2296	if (pstate == cpu->pstate.current_pstate)
2297	return;
2298
2299	cpu->pstate.current_pstate = pstate;
2300	wrmsrl(MSR_IA32_PERF_CTL, val: pstate_funcs.get_val(cpu, pstate));
2301	}
2302
2303	static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2304	{
2305	int from = cpu->pstate.current_pstate;
2306	struct sample *sample;
2307	int target_pstate;
2308
2309	update_turbo_state();
2310
2311	target_pstate = get_target_pstate(cpu);
2312	target_pstate = intel_pstate_prepare_request(cpu, pstate: target_pstate);
2313	trace_cpu_frequency(frequency: target_pstate * cpu->pstate.scaling, cpu_id: cpu->cpu);
2314	intel_pstate_update_pstate(cpu, pstate: target_pstate);
2315
2316	sample = &cpu->sample;
2317	trace_pstate_sample(core_busy: mul_ext_fp(x: 100, y: sample->core_avg_perf),
2318	fp_toint(sample->busy_scaled),
2319	from,
2320	to: cpu->pstate.current_pstate,
2321	mperf: sample->mperf,
2322	aperf: sample->aperf,
2323	tsc: sample->tsc,
2324	freq: get_avg_frequency(cpu),
2325	fp_toint(cpu->iowait_boost * 100));
2326	}
2327
2328	static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2329	unsigned int flags)
2330	{
2331	struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2332	u64 delta_ns;
2333
2334	/* Don't allow remote callbacks */
2335	if (smp_processor_id() != cpu->cpu)
2336	return;
2337
2338	delta_ns = time - cpu->last_update;
2339	if (flags & SCHED_CPUFREQ_IOWAIT) {
2340	/* Start over if the CPU may have been idle. */
2341	if (delta_ns > TICK_NSEC) {
2342	cpu->iowait_boost = ONE_EIGHTH_FP;
2343	} else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2344	cpu->iowait_boost <<= 1;
2345	if (cpu->iowait_boost > int_tofp(1))
2346	cpu->iowait_boost = int_tofp(1);
2347	} else {
2348	cpu->iowait_boost = ONE_EIGHTH_FP;
2349	}
2350	} else if (cpu->iowait_boost) {
2351	/* Clear iowait_boost if the CPU may have been idle. */
2352	if (delta_ns > TICK_NSEC)
2353	cpu->iowait_boost = 0;
2354	else
2355	cpu->iowait_boost >>= 1;
2356	}
2357	cpu->last_update = time;
2358	delta_ns = time - cpu->sample.time;
2359	if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2360	return;
2361
2362	if (intel_pstate_sample(cpu, time))
2363	intel_pstate_adjust_pstate(cpu);
2364	}
2365
2366	static struct pstate_funcs core_funcs = {
2367	.get_max = core_get_max_pstate,
2368	.get_max_physical = core_get_max_pstate_physical,
2369	.get_min = core_get_min_pstate,
2370	.get_turbo = core_get_turbo_pstate,
2371	.get_scaling = core_get_scaling,
2372	.get_val = core_get_val,
2373	};
2374
2375	static const struct pstate_funcs silvermont_funcs = {
2376	.get_max = atom_get_max_pstate,
2377	.get_max_physical = atom_get_max_pstate,
2378	.get_min = atom_get_min_pstate,
2379	.get_turbo = atom_get_turbo_pstate,
2380	.get_val = atom_get_val,
2381	.get_scaling = silvermont_get_scaling,
2382	.get_vid = atom_get_vid,
2383	};
2384
2385	static const struct pstate_funcs airmont_funcs = {
2386	.get_max = atom_get_max_pstate,
2387	.get_max_physical = atom_get_max_pstate,
2388	.get_min = atom_get_min_pstate,
2389	.get_turbo = atom_get_turbo_pstate,
2390	.get_val = atom_get_val,
2391	.get_scaling = airmont_get_scaling,
2392	.get_vid = atom_get_vid,
2393	};
2394
2395	static const struct pstate_funcs knl_funcs = {
2396	.get_max = core_get_max_pstate,
2397	.get_max_physical = core_get_max_pstate_physical,
2398	.get_min = core_get_min_pstate,
2399	.get_turbo = knl_get_turbo_pstate,
2400	.get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2401	.get_scaling = core_get_scaling,
2402	.get_val = core_get_val,
2403	};
2404
2405	#define X86_MATCH(model, policy) \
2406	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2407	X86_FEATURE_APERFMPERF, &policy)
2408
2409	static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2410	X86_MATCH(SANDYBRIDGE, core_funcs),
2411	X86_MATCH(SANDYBRIDGE_X, core_funcs),
2412	X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2413	X86_MATCH(IVYBRIDGE, core_funcs),
2414	X86_MATCH(HASWELL, core_funcs),
2415	X86_MATCH(BROADWELL, core_funcs),
2416	X86_MATCH(IVYBRIDGE_X, core_funcs),
2417	X86_MATCH(HASWELL_X, core_funcs),
2418	X86_MATCH(HASWELL_L, core_funcs),
2419	X86_MATCH(HASWELL_G, core_funcs),
2420	X86_MATCH(BROADWELL_G, core_funcs),
2421	X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2422	X86_MATCH(SKYLAKE_L, core_funcs),
2423	X86_MATCH(BROADWELL_X, core_funcs),
2424	X86_MATCH(SKYLAKE, core_funcs),
2425	X86_MATCH(BROADWELL_D, core_funcs),
2426	X86_MATCH(XEON_PHI_KNL, knl_funcs),
2427	X86_MATCH(XEON_PHI_KNM, knl_funcs),
2428	X86_MATCH(ATOM_GOLDMONT, core_funcs),
2429	X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2430	X86_MATCH(SKYLAKE_X, core_funcs),
2431	X86_MATCH(COMETLAKE, core_funcs),
2432	X86_MATCH(ICELAKE_X, core_funcs),
2433	X86_MATCH(TIGERLAKE, core_funcs),
2434	X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2435	X86_MATCH(EMERALDRAPIDS_X, core_funcs),
2436	{}
2437	};
2438	MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2439
2440	static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2441	X86_MATCH(BROADWELL_D, core_funcs),
2442	X86_MATCH(BROADWELL_X, core_funcs),
2443	X86_MATCH(SKYLAKE_X, core_funcs),
2444	X86_MATCH(ICELAKE_X, core_funcs),
2445	X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2446	{}
2447	};
2448
2449	static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2450	X86_MATCH(KABYLAKE, core_funcs),
2451	{}
2452	};
2453
2454	static int intel_pstate_init_cpu(unsigned int cpunum)
2455	{
2456	struct cpudata *cpu;
2457
2458	cpu = all_cpu_data[cpunum];
2459
2460	if (!cpu) {
2461	cpu = kzalloc(size: sizeof(*cpu), GFP_KERNEL);
2462	if (!cpu)
2463	return -ENOMEM;
2464
2465	WRITE_ONCE(all_cpu_data[cpunum], cpu);
2466
2467	cpu->cpu = cpunum;
2468
2469	cpu->epp_default = -EINVAL;
2470
2471	if (hwp_active) {
2472	intel_pstate_hwp_enable(cpudata: cpu);
2473
2474	if (intel_pstate_acpi_pm_profile_server())
2475	hwp_boost = true;
2476	}
2477	} else if (hwp_active) {
2478	/*
2479	* Re-enable HWP in case this happens after a resume from ACPI
2480	* S3 if the CPU was offline during the whole system/resume
2481	* cycle.
2482	*/
2483	intel_pstate_hwp_reenable(cpu);
2484	}
2485
2486	cpu->epp_powersave = -EINVAL;
2487	cpu->epp_policy = 0;
2488
2489	intel_pstate_get_cpu_pstates(cpu);
2490
2491	pr_debug("controlling: cpu %d\n", cpunum);
2492
2493	return 0;
2494	}
2495
2496	static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2497	{
2498	struct cpudata *cpu = all_cpu_data[cpu_num];
2499
2500	if (hwp_active && !hwp_boost)
2501	return;
2502
2503	if (cpu->update_util_set)
2504	return;
2505
2506	/* Prevent intel_pstate_update_util() from using stale data. */
2507	cpu->sample.time = 0;
2508	cpufreq_add_update_util_hook(cpu: cpu_num, data: &cpu->update_util,
2509	func: (hwp_active ?
2510	intel_pstate_update_util_hwp :
2511	intel_pstate_update_util));
2512	cpu->update_util_set = true;
2513	}
2514
2515	static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2516	{
2517	struct cpudata *cpu_data = all_cpu_data[cpu];
2518
2519	if (!cpu_data->update_util_set)
2520	return;
2521
2522	cpufreq_remove_update_util_hook(cpu);
2523	cpu_data->update_util_set = false;
2524	synchronize_rcu();
2525	}
2526
2527	static int intel_pstate_get_max_freq(struct cpudata *cpu)
2528	{
2529	return global.turbo_disabled || global.no_turbo ?
2530	cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2531	}
2532
2533	static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2534	unsigned int policy_min,
2535	unsigned int policy_max)
2536	{
2537	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2538	int32_t max_policy_perf, min_policy_perf;
2539
2540	max_policy_perf = policy_max / perf_ctl_scaling;
2541	if (policy_max == policy_min) {
2542	min_policy_perf = max_policy_perf;
2543	} else {
2544	min_policy_perf = policy_min / perf_ctl_scaling;
2545	min_policy_perf = clamp_t(int32_t, min_policy_perf,
2546	0, max_policy_perf);
2547	}
2548
2549	/*
2550	* HWP needs some special consideration, because HWP_REQUEST uses
2551	* abstract values to represent performance rather than pure ratios.
2552	*/
2553	if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2554	int freq;
2555
2556	freq = max_policy_perf * perf_ctl_scaling;
2557	max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2558	freq = min_policy_perf * perf_ctl_scaling;
2559	min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2560	}
2561
2562	pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2563	cpu->cpu, min_policy_perf, max_policy_perf);
2564
2565	/* Normalize user input to [min_perf, max_perf] */
2566	if (per_cpu_limits) {
2567	cpu->min_perf_ratio = min_policy_perf;
2568	cpu->max_perf_ratio = max_policy_perf;
2569	} else {
2570	int turbo_max = cpu->pstate.turbo_pstate;
2571	int32_t global_min, global_max;
2572
2573	/* Global limits are in percent of the maximum turbo P-state. */
2574	global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2575	global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2576	global_min = clamp_t(int32_t, global_min, 0, global_max);
2577
2578	pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2579	global_min, global_max);
2580
2581	cpu->min_perf_ratio = max(min_policy_perf, global_min);
2582	cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2583	cpu->max_perf_ratio = min(max_policy_perf, global_max);
2584	cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2585
2586	/* Make sure min_perf <= max_perf */
2587	cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2588	cpu->max_perf_ratio);
2589
2590	}
2591	pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2592	cpu->max_perf_ratio,
2593	cpu->min_perf_ratio);
2594	}
2595
2596	static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2597	{
2598	struct cpudata *cpu;
2599
2600	if (!policy->cpuinfo.max_freq)
2601	return -ENODEV;
2602
2603	pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2604	policy->cpuinfo.max_freq, policy->max);
2605
2606	cpu = all_cpu_data[policy->cpu];
2607	cpu->policy = policy->policy;
2608
2609	mutex_lock(&intel_pstate_limits_lock);
2610
2611	intel_pstate_update_perf_limits(cpu, policy_min: policy->min, policy_max: policy->max);
2612
2613	if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2614	/*
2615	* NOHZ_FULL CPUs need this as the governor callback may not
2616	* be invoked on them.
2617	*/
2618	intel_pstate_clear_update_util_hook(cpu: policy->cpu);
2619	intel_pstate_max_within_limits(cpu);
2620	} else {
2621	intel_pstate_set_update_util_hook(cpu_num: policy->cpu);
2622	}
2623
2624	if (hwp_active) {
2625	/*
2626	* When hwp_boost was active before and dynamically it
2627	* was turned off, in that case we need to clear the
2628	* update util hook.
2629	*/
2630	if (!hwp_boost)
2631	intel_pstate_clear_update_util_hook(cpu: policy->cpu);
2632	intel_pstate_hwp_set(cpu: policy->cpu);
2633	}
2634	/*
2635	* policy->cur is never updated with the intel_pstate driver, but it
2636	* is used as a stale frequency value. So, keep it within limits.
2637	*/
2638	policy->cur = policy->min;
2639
2640	mutex_unlock(lock: &intel_pstate_limits_lock);
2641
2642	return 0;
2643	}
2644
2645	static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2646	struct cpufreq_policy_data *policy)
2647	{
2648	if (!hwp_active &&
2649	cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2650	policy->max < policy->cpuinfo.max_freq &&
2651	policy->max > cpu->pstate.max_freq) {
2652	pr_debug("policy->max > max non turbo frequency\n");
2653	policy->max = policy->cpuinfo.max_freq;
2654	}
2655	}
2656
2657	static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2658	struct cpufreq_policy_data *policy)
2659	{
2660	int max_freq;
2661
2662	update_turbo_state();
2663	if (hwp_active) {
2664	intel_pstate_get_hwp_cap(cpu);
2665	max_freq = global.no_turbo || global.turbo_disabled ?
2666	cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2667	} else {
2668	max_freq = intel_pstate_get_max_freq(cpu);
2669	}
2670	cpufreq_verify_within_limits(policy, min: policy->cpuinfo.min_freq, max: max_freq);
2671
2672	intel_pstate_adjust_policy_max(cpu, policy);
2673	}
2674
2675	static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2676	{
2677	intel_pstate_verify_cpu_policy(cpu: all_cpu_data[policy->cpu], policy);
2678
2679	return 0;
2680	}
2681
2682	static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2683	{
2684	struct cpudata *cpu = all_cpu_data[policy->cpu];
2685
2686	pr_debug("CPU %d going offline\n", cpu->cpu);
2687
2688	if (cpu->suspended)
2689	return 0;
2690
2691	/*
2692	* If the CPU is an SMT thread and it goes offline with the performance
2693	* settings different from the minimum, it will prevent its sibling
2694	* from getting to lower performance levels, so force the minimum
2695	* performance on CPU offline to prevent that from happening.
2696	*/
2697	if (hwp_active)
2698	intel_pstate_hwp_offline(cpu);
2699	else
2700	intel_pstate_set_min_pstate(cpu);
2701
2702	intel_pstate_exit_perf_limits(policy);
2703
2704	return 0;
2705	}
2706
2707	static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2708	{
2709	struct cpudata *cpu = all_cpu_data[policy->cpu];
2710
2711	pr_debug("CPU %d going online\n", cpu->cpu);
2712
2713	intel_pstate_init_acpi_perf_limits(policy);
2714
2715	if (hwp_active) {
2716	/*
2717	* Re-enable HWP and clear the "suspended" flag to let "resume"
2718	* know that it need not do that.
2719	*/
2720	intel_pstate_hwp_reenable(cpu);
2721	cpu->suspended = false;
2722	}
2723
2724	return 0;
2725	}
2726
2727	static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2728	{
2729	intel_pstate_clear_update_util_hook(cpu: policy->cpu);
2730
2731	return intel_cpufreq_cpu_offline(policy);
2732	}
2733
2734	static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2735	{
2736	pr_debug("CPU %d exiting\n", policy->cpu);
2737
2738	policy->fast_switch_possible = false;
2739
2740	return 0;
2741	}
2742
2743	static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2744	{
2745	struct cpudata *cpu;
2746	int rc;
2747
2748	rc = intel_pstate_init_cpu(cpunum: policy->cpu);
2749	if (rc)
2750	return rc;
2751
2752	cpu = all_cpu_data[policy->cpu];
2753
2754	cpu->max_perf_ratio = 0xFF;
2755	cpu->min_perf_ratio = 0;
2756
2757	/* cpuinfo and default policy values */
2758	policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2759	update_turbo_state();
2760	global.turbo_disabled_mf = global.turbo_disabled;
2761	policy->cpuinfo.max_freq = global.turbo_disabled ?
2762	cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2763
2764	policy->min = policy->cpuinfo.min_freq;
2765	policy->max = policy->cpuinfo.max_freq;
2766
2767	intel_pstate_init_acpi_perf_limits(policy);
2768
2769	policy->fast_switch_possible = true;
2770
2771	return 0;
2772	}
2773
2774	static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2775	{
2776	int ret = __intel_pstate_cpu_init(policy);
2777
2778	if (ret)
2779	return ret;
2780
2781	/*
2782	* Set the policy to powersave to provide a valid fallback value in case
2783	* the default cpufreq governor is neither powersave nor performance.
2784	*/
2785	policy->policy = CPUFREQ_POLICY_POWERSAVE;
2786
2787	if (hwp_active) {
2788	struct cpudata *cpu = all_cpu_data[policy->cpu];
2789
2790	cpu->epp_cached = intel_pstate_get_epp(cpu_data: cpu, hwp_req_data: 0);
2791	}
2792
2793	return 0;
2794	}
2795
2796	static struct cpufreq_driver intel_pstate = {
2797	.flags = CPUFREQ_CONST_LOOPS,
2798	.verify = intel_pstate_verify_policy,
2799	.setpolicy = intel_pstate_set_policy,
2800	.suspend = intel_pstate_suspend,
2801	.resume = intel_pstate_resume,
2802	.init = intel_pstate_cpu_init,
2803	.exit = intel_pstate_cpu_exit,
2804	.offline = intel_pstate_cpu_offline,
2805	.online = intel_pstate_cpu_online,
2806	.update_limits = intel_pstate_update_limits,
2807	.name = "intel_pstate",
2808	};
2809
2810	static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2811	{
2812	struct cpudata *cpu = all_cpu_data[policy->cpu];
2813
2814	intel_pstate_verify_cpu_policy(cpu, policy);
2815	intel_pstate_update_perf_limits(cpu, policy_min: policy->min, policy_max: policy->max);
2816
2817	return 0;
2818	}
2819
2820	/* Use of trace in passive mode:
2821	*
2822	* In passive mode the trace core_busy field (also known as the
2823	* performance field, and lablelled as such on the graphs; also known as
2824	* core_avg_perf) is not needed and so is re-assigned to indicate if the
2825	* driver call was via the normal or fast switch path. Various graphs
2826	* output from the intel_pstate_tracer.py utility that include core_busy
2827	* (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2828	* so we use 10 to indicate the normal path through the driver, and
2829	* 90 to indicate the fast switch path through the driver.
2830	* The scaled_busy field is not used, and is set to 0.
2831	*/
2832
2833	#define INTEL_PSTATE_TRACE_TARGET 10
2834	#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2835
2836	static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2837	{
2838	struct sample *sample;
2839
2840	if (!trace_pstate_sample_enabled())
2841	return;
2842
2843	if (!intel_pstate_sample(cpu, time: ktime_get()))
2844	return;
2845
2846	sample = &cpu->sample;
2847	trace_pstate_sample(core_busy: trace_type,
2848	scaled_busy: 0,
2849	from: old_pstate,
2850	to: cpu->pstate.current_pstate,
2851	mperf: sample->mperf,
2852	aperf: sample->aperf,
2853	tsc: sample->tsc,
2854	freq: get_avg_frequency(cpu),
2855	fp_toint(cpu->iowait_boost * 100));
2856	}
2857
2858	static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2859	u32 desired, bool fast_switch)
2860	{
2861	u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2862
2863	value &= ~HWP_MIN_PERF(~0L);
2864	value |= HWP_MIN_PERF(min);
2865
2866	value &= ~HWP_MAX_PERF(~0L);
2867	value |= HWP_MAX_PERF(max);
2868
2869	value &= ~HWP_DESIRED_PERF(~0L);
2870	value |= HWP_DESIRED_PERF(desired);
2871
2872	if (value == prev)
2873	return;
2874
2875	WRITE_ONCE(cpu->hwp_req_cached, value);
2876	if (fast_switch)
2877	wrmsrl(MSR_HWP_REQUEST, val: value);
2878	else
2879	wrmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_REQUEST, q: value);
2880	}
2881
2882	static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2883	u32 target_pstate, bool fast_switch)
2884	{
2885	if (fast_switch)
2886	wrmsrl(MSR_IA32_PERF_CTL,
2887	val: pstate_funcs.get_val(cpu, target_pstate));
2888	else
2889	wrmsrl_on_cpu(cpu: cpu->cpu, MSR_IA32_PERF_CTL,
2890	q: pstate_funcs.get_val(cpu, target_pstate));
2891	}
2892
2893	static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2894	int target_pstate, bool fast_switch)
2895	{
2896	struct cpudata *cpu = all_cpu_data[policy->cpu];
2897	int old_pstate = cpu->pstate.current_pstate;
2898
2899	target_pstate = intel_pstate_prepare_request(cpu, pstate: target_pstate);
2900	if (hwp_active) {
2901	int max_pstate = policy->strict_target ?
2902	target_pstate : cpu->max_perf_ratio;
2903
2904	intel_cpufreq_hwp_update(cpu, min: target_pstate, max: max_pstate, desired: 0,
2905	fast_switch);
2906	} else if (target_pstate != old_pstate) {
2907	intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2908	}
2909
2910	cpu->pstate.current_pstate = target_pstate;
2911
2912	intel_cpufreq_trace(cpu, trace_type: fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2913	INTEL_PSTATE_TRACE_TARGET, old_pstate);
2914
2915	return target_pstate;
2916	}
2917
2918	static int intel_cpufreq_target(struct cpufreq_policy *policy,
2919	unsigned int target_freq,
2920	unsigned int relation)
2921	{
2922	struct cpudata *cpu = all_cpu_data[policy->cpu];
2923	struct cpufreq_freqs freqs;
2924	int target_pstate;
2925
2926	update_turbo_state();
2927
2928	freqs.old = policy->cur;
2929	freqs.new = target_freq;
2930
2931	cpufreq_freq_transition_begin(policy, freqs: &freqs);
2932
2933	target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freq: freqs.new, relation);
2934	target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, fast_switch: false);
2935
2936	freqs.new = target_pstate * cpu->pstate.scaling;
2937
2938	cpufreq_freq_transition_end(policy, freqs: &freqs, transition_failed: false);
2939
2940	return 0;
2941	}
2942
2943	static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2944	unsigned int target_freq)
2945	{
2946	struct cpudata *cpu = all_cpu_data[policy->cpu];
2947	int target_pstate;
2948
2949	update_turbo_state();
2950
2951	target_pstate = intel_pstate_freq_to_hwp(cpu, freq: target_freq);
2952
2953	target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, fast_switch: true);
2954
2955	return target_pstate * cpu->pstate.scaling;
2956	}
2957
2958	static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2959	unsigned long min_perf,
2960	unsigned long target_perf,
2961	unsigned long capacity)
2962	{
2963	struct cpudata *cpu = all_cpu_data[cpunum];
2964	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2965	int old_pstate = cpu->pstate.current_pstate;
2966	int cap_pstate, min_pstate, max_pstate, target_pstate;
2967
2968	update_turbo_state();
2969	cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2970	HWP_HIGHEST_PERF(hwp_cap);
2971
2972	/* Optimization: Avoid unnecessary divisions. */
2973
2974	target_pstate = cap_pstate;
2975	if (target_perf < capacity)
2976	target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2977
2978	min_pstate = cap_pstate;
2979	if (min_perf < capacity)
2980	min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2981
2982	if (min_pstate < cpu->pstate.min_pstate)
2983	min_pstate = cpu->pstate.min_pstate;
2984
2985	if (min_pstate < cpu->min_perf_ratio)
2986	min_pstate = cpu->min_perf_ratio;
2987
2988	if (min_pstate > cpu->max_perf_ratio)
2989	min_pstate = cpu->max_perf_ratio;
2990
2991	max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2992	if (max_pstate < min_pstate)
2993	max_pstate = min_pstate;
2994
2995	target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2996
2997	intel_cpufreq_hwp_update(cpu, min: min_pstate, max: max_pstate, desired: target_pstate, fast_switch: true);
2998
2999	cpu->pstate.current_pstate = target_pstate;
3000	intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3001	}
3002
3003	static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3004	{
3005	struct freq_qos_request *req;
3006	struct cpudata *cpu;
3007	struct device *dev;
3008	int ret, freq;
3009
3010	dev = get_cpu_device(cpu: policy->cpu);
3011	if (!dev)
3012	return -ENODEV;
3013
3014	ret = __intel_pstate_cpu_init(policy);
3015	if (ret)
3016	return ret;
3017
3018	policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3019	/* This reflects the intel_pstate_get_cpu_pstates() setting. */
3020	policy->cur = policy->cpuinfo.min_freq;
3021
3022	req = kcalloc(n: 2, size: sizeof(*req), GFP_KERNEL);
3023	if (!req) {
3024	ret = -ENOMEM;
3025	goto pstate_exit;
3026	}
3027
3028	cpu = all_cpu_data[policy->cpu];
3029
3030	if (hwp_active) {
3031	u64 value;
3032
3033	policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3034
3035	intel_pstate_get_hwp_cap(cpu);
3036
3037	rdmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_REQUEST, q: &value);
3038	WRITE_ONCE(cpu->hwp_req_cached, value);
3039
3040	cpu->epp_cached = intel_pstate_get_epp(cpu_data: cpu, hwp_req_data: value);
3041	} else {
3042	policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3043	}
3044
3045	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3046
3047	ret = freq_qos_add_request(qos: &policy->constraints, req, type: FREQ_QOS_MIN,
3048	value: freq);
3049	if (ret < 0) {
3050	dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3051	goto free_req;
3052	}
3053
3054	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3055
3056	ret = freq_qos_add_request(qos: &policy->constraints, req: req + 1, type: FREQ_QOS_MAX,
3057	value: freq);
3058	if (ret < 0) {
3059	dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3060	goto remove_min_req;
3061	}
3062
3063	policy->driver_data = req;
3064
3065	return 0;
3066
3067	remove_min_req:
3068	freq_qos_remove_request(req);
3069	free_req:
3070	kfree(objp: req);
3071	pstate_exit:
3072	intel_pstate_exit_perf_limits(policy);
3073
3074	return ret;
3075	}
3076
3077	static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3078	{
3079	struct freq_qos_request *req;
3080
3081	req = policy->driver_data;
3082
3083	freq_qos_remove_request(req: req + 1);
3084	freq_qos_remove_request(req);
3085	kfree(objp: req);
3086
3087	return intel_pstate_cpu_exit(policy);
3088	}
3089
3090	static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3091	{
3092	intel_pstate_suspend(policy);
3093
3094	if (hwp_active) {
3095	struct cpudata *cpu = all_cpu_data[policy->cpu];
3096	u64 value = READ_ONCE(cpu->hwp_req_cached);
3097
3098	/*
3099	* Clear the desired perf field in MSR_HWP_REQUEST in case
3100	* intel_cpufreq_adjust_perf() is in use and the last value
3101	* written by it may not be suitable.
3102	*/
3103	value &= ~HWP_DESIRED_PERF(~0L);
3104	wrmsrl_on_cpu(cpu: cpu->cpu, MSR_HWP_REQUEST, q: value);
3105	WRITE_ONCE(cpu->hwp_req_cached, value);
3106	}
3107
3108	return 0;
3109	}
3110
3111	static struct cpufreq_driver intel_cpufreq = {
3112	.flags = CPUFREQ_CONST_LOOPS,
3113	.verify = intel_cpufreq_verify_policy,
3114	.target = intel_cpufreq_target,
3115	.fast_switch = intel_cpufreq_fast_switch,
3116	.init = intel_cpufreq_cpu_init,
3117	.exit = intel_cpufreq_cpu_exit,
3118	.offline = intel_cpufreq_cpu_offline,
3119	.online = intel_pstate_cpu_online,
3120	.suspend = intel_cpufreq_suspend,
3121	.resume = intel_pstate_resume,
3122	.update_limits = intel_pstate_update_limits,
3123	.name = "intel_cpufreq",
3124	};
3125
3126	static struct cpufreq_driver *default_driver;
3127
3128	static void intel_pstate_driver_cleanup(void)
3129	{
3130	unsigned int cpu;
3131
3132	cpus_read_lock();
3133	for_each_online_cpu(cpu) {
3134	if (all_cpu_data[cpu]) {
3135	if (intel_pstate_driver == &intel_pstate)
3136	intel_pstate_clear_update_util_hook(cpu);
3137
3138	spin_lock(lock: &hwp_notify_lock);
3139	kfree(objp: all_cpu_data[cpu]);
3140	WRITE_ONCE(all_cpu_data[cpu], NULL);
3141	spin_unlock(lock: &hwp_notify_lock);
3142	}
3143	}
3144	cpus_read_unlock();
3145
3146	intel_pstate_driver = NULL;
3147	}
3148
3149	static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3150	{
3151	int ret;
3152
3153	if (driver == &intel_pstate)
3154	intel_pstate_sysfs_expose_hwp_dynamic_boost();
3155
3156	memset(&global, 0, sizeof(global));
3157	global.max_perf_pct = 100;
3158
3159	intel_pstate_driver = driver;
3160	ret = cpufreq_register_driver(driver_data: intel_pstate_driver);
3161	if (ret) {
3162	intel_pstate_driver_cleanup();
3163	return ret;
3164	}
3165
3166	global.min_perf_pct = min_perf_pct_min();
3167
3168	return 0;
3169	}
3170
3171	static ssize_t intel_pstate_show_status(char *buf)
3172	{
3173	if (!intel_pstate_driver)
3174	return sprintf(buf, fmt: "off\n");
3175
3176	return sprintf(buf, fmt: "%s\n", intel_pstate_driver == &intel_pstate ?
3177	"active" : "passive");
3178	}
3179
3180	static int intel_pstate_update_status(const char *buf, size_t size)
3181	{
3182	if (size == 3 && !strncmp(buf, "off", size)) {
3183	if (!intel_pstate_driver)
3184	return -EINVAL;
3185
3186	if (hwp_active)
3187	return -EBUSY;
3188
3189	cpufreq_unregister_driver(driver_data: intel_pstate_driver);
3190	intel_pstate_driver_cleanup();
3191	return 0;
3192	}
3193
3194	if (size == 6 && !strncmp(buf, "active", size)) {
3195	if (intel_pstate_driver) {
3196	if (intel_pstate_driver == &intel_pstate)
3197	return 0;
3198
3199	cpufreq_unregister_driver(driver_data: intel_pstate_driver);
3200	}
3201
3202	return intel_pstate_register_driver(driver: &intel_pstate);
3203	}
3204
3205	if (size == 7 && !strncmp(buf, "passive", size)) {
3206	if (intel_pstate_driver) {
3207	if (intel_pstate_driver == &intel_cpufreq)
3208	return 0;
3209
3210	cpufreq_unregister_driver(driver_data: intel_pstate_driver);
3211	intel_pstate_sysfs_hide_hwp_dynamic_boost();
3212	}
3213
3214	return intel_pstate_register_driver(driver: &intel_cpufreq);
3215	}
3216
3217	return -EINVAL;
3218	}
3219
3220	static int no_load __initdata;
3221	static int no_hwp __initdata;
3222	static int hwp_only __initdata;
3223	static unsigned int force_load __initdata;
3224
3225	static int __init intel_pstate_msrs_not_valid(void)
3226	{
3227	if (!pstate_funcs.get_max(0) ||
3228	!pstate_funcs.get_min(0) ||
3229	!pstate_funcs.get_turbo(0))
3230	return -ENODEV;
3231
3232	return 0;
3233	}
3234
3235	static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3236	{
3237	pstate_funcs.get_max = funcs->get_max;
3238	pstate_funcs.get_max_physical = funcs->get_max_physical;
3239	pstate_funcs.get_min = funcs->get_min;
3240	pstate_funcs.get_turbo = funcs->get_turbo;
3241	pstate_funcs.get_scaling = funcs->get_scaling;
3242	pstate_funcs.get_val = funcs->get_val;
3243	pstate_funcs.get_vid = funcs->get_vid;
3244	pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3245	}
3246
3247	#ifdef CONFIG_ACPI
3248
3249	static bool __init intel_pstate_no_acpi_pss(void)
3250	{
3251	int i;
3252
3253	for_each_possible_cpu(i) {
3254	acpi_status status;
3255	union acpi_object *pss;
3256	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3257	struct acpi_processor *pr = per_cpu(processors, i);
3258
3259	if (!pr)
3260	continue;
3261
3262	status = acpi_evaluate_object(object: pr->handle, pathname: "_PSS", NULL, return_object_buffer: &buffer);
3263	if (ACPI_FAILURE(status))
3264	continue;
3265
3266	pss = buffer.pointer;
3267	if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3268	kfree(objp: pss);
3269	return false;
3270	}
3271
3272	kfree(objp: pss);
3273	}
3274
3275	pr_debug("ACPI _PSS not found\n");
3276	return true;
3277	}
3278
3279	static bool __init intel_pstate_no_acpi_pcch(void)
3280	{
3281	acpi_status status;
3282	acpi_handle handle;
3283
3284	status = acpi_get_handle(NULL, pathname: "\\_SB", ret_handle: &handle);
3285	if (ACPI_FAILURE(status))
3286	goto not_found;
3287
3288	if (acpi_has_method(handle, name: "PCCH"))
3289	return false;
3290
3291	not_found:
3292	pr_debug("ACPI PCCH not found\n");
3293	return true;
3294	}
3295
3296	static bool __init intel_pstate_has_acpi_ppc(void)
3297	{
3298	int i;
3299
3300	for_each_possible_cpu(i) {
3301	struct acpi_processor *pr = per_cpu(processors, i);
3302
3303	if (!pr)
3304	continue;
3305	if (acpi_has_method(handle: pr->handle, name: "_PPC"))
3306	return true;
3307	}
3308	pr_debug("ACPI _PPC not found\n");
3309	return false;
3310	}
3311
3312	enum {
3313	PSS,
3314	PPC,
3315	};
3316
3317	/* Hardware vendor-specific info that has its own power management modes */
3318	static struct acpi_platform_list plat_info[] __initdata = {
3319	{"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3320	{"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3321	{"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322	{"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323	{"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324	{"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325	{"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326	{"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327	{"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328	{"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329	{"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330	{"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331	{"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332	{"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333	{"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3334	{ } /* End */
3335	};
3336
3337	#define BITMASK_OOB (BIT(8) | BIT(18))
3338
3339	static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3340	{
3341	const struct x86_cpu_id *id;
3342	u64 misc_pwr;
3343	int idx;
3344
3345	id = x86_match_cpu(match: intel_pstate_cpu_oob_ids);
3346	if (id) {
3347	rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3348	if (misc_pwr & BITMASK_OOB) {
3349	pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3350	pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3351	return true;
3352	}
3353	}
3354
3355	idx = acpi_match_platform_list(plat: plat_info);
3356	if (idx < 0)
3357	return false;
3358
3359	switch (plat_info[idx].data) {
3360	case PSS:
3361	if (!intel_pstate_no_acpi_pss())
3362	return false;
3363
3364	return intel_pstate_no_acpi_pcch();
3365	case PPC:
3366	return intel_pstate_has_acpi_ppc() && !force_load;
3367	}
3368
3369	return false;
3370	}
3371
3372	static void intel_pstate_request_control_from_smm(void)
3373	{
3374	/*
3375	* It may be unsafe to request P-states control from SMM if _PPC support
3376	* has not been enabled.
3377	*/
3378	if (acpi_ppc)
3379	acpi_processor_pstate_control();
3380	}
3381	#else /* CONFIG_ACPI not enabled */
3382	static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3383	static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3384	static inline void intel_pstate_request_control_from_smm(void) {}
3385	#endif /* CONFIG_ACPI */
3386
3387	#define INTEL_PSTATE_HWP_BROADWELL 0x01
3388
3389	#define X86_MATCH_HWP(model, hwp_mode) \
3390	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3391	X86_FEATURE_HWP, hwp_mode)
3392
3393	static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3394	X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3395	X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3396	X86_MATCH_HWP(ANY, 0),
3397	{}
3398	};
3399
3400	static bool intel_pstate_hwp_is_enabled(void)
3401	{
3402	u64 value;
3403
3404	rdmsrl(MSR_PM_ENABLE, value);
3405	return !!(value & 0x1);
3406	}
3407
3408	#define POWERSAVE_MASK GENMASK(7, 0)
3409	#define BALANCE_POWER_MASK GENMASK(15, 8)
3410	#define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3411	#define PERFORMANCE_MASK GENMASK(31, 24)
3412
3413	#define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3414	(FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3415	FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3416	FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3417	FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3418
3419	#define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3420	(HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3421	balance_perf, HWP_EPP_PERFORMANCE))
3422
3423	static const struct x86_cpu_id intel_epp_default[] = {
3424	/*
3425	* Set EPP value as 102, this is the max suggested EPP
3426	* which can result in one core turbo frequency for
3427	* AlderLake Mobile CPUs.
3428	*/
3429	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3430	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3431	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3432	HWP_EPP_BALANCE_POWERSAVE, 115, 16)),
3433	{}
3434	};
3435
3436	static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3437	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3438	{}
3439	};
3440
3441	static int __init intel_pstate_init(void)
3442	{
3443	static struct cpudata **_all_cpu_data;
3444	const struct x86_cpu_id *id;
3445	int rc;
3446
3447	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3448	return -ENODEV;
3449
3450	id = x86_match_cpu(match: hwp_support_ids);
3451	if (id) {
3452	hwp_forced = intel_pstate_hwp_is_enabled();
3453
3454	if (hwp_forced)
3455	pr_info("HWP enabled by BIOS\n");
3456	else if (no_load)
3457	return -ENODEV;
3458
3459	copy_cpu_funcs(funcs: &core_funcs);
3460	/*
3461	* Avoid enabling HWP for processors without EPP support,
3462	* because that means incomplete HWP implementation which is a
3463	* corner case and supporting it is generally problematic.
3464	*
3465	* If HWP is enabled already, though, there is no choice but to
3466	* deal with it.
3467	*/
3468	if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3469	WRITE_ONCE(hwp_active, 1);
3470	hwp_mode_bdw = id->driver_data;
3471	intel_pstate.attr = hwp_cpufreq_attrs;
3472	intel_cpufreq.attr = hwp_cpufreq_attrs;
3473	intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3474	intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3475	if (!default_driver)
3476	default_driver = &intel_pstate;
3477
3478	pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3479
3480	goto hwp_cpu_matched;
3481	}
3482	pr_info("HWP not enabled\n");
3483	} else {
3484	if (no_load)
3485	return -ENODEV;
3486
3487	id = x86_match_cpu(match: intel_pstate_cpu_ids);
3488	if (!id) {
3489	pr_info("CPU model not supported\n");
3490	return -ENODEV;
3491	}
3492
3493	copy_cpu_funcs(funcs: (struct pstate_funcs *)id->driver_data);
3494	}
3495
3496	if (intel_pstate_msrs_not_valid()) {
3497	pr_info("Invalid MSRs\n");
3498	return -ENODEV;
3499	}
3500	/* Without HWP start in the passive mode. */
3501	if (!default_driver)
3502	default_driver = &intel_cpufreq;
3503
3504	hwp_cpu_matched:
3505	/*
3506	* The Intel pstate driver will be ignored if the platform
3507	* firmware has its own power management modes.
3508	*/
3509	if (intel_pstate_platform_pwr_mgmt_exists()) {
3510	pr_info("P-states controlled by the platform\n");
3511	return -ENODEV;
3512	}
3513
3514	if (!hwp_active && hwp_only)
3515	return -ENOTSUPP;
3516
3517	pr_info("Intel P-state driver initializing\n");
3518
3519	_all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3520	if (!_all_cpu_data)
3521	return -ENOMEM;
3522
3523	WRITE_ONCE(all_cpu_data, _all_cpu_data);
3524
3525	intel_pstate_request_control_from_smm();
3526
3527	intel_pstate_sysfs_expose_params();
3528
3529	if (hwp_active) {
3530	const struct x86_cpu_id *id = x86_match_cpu(match: intel_epp_default);
3531	const struct x86_cpu_id *hybrid_id = x86_match_cpu(match: intel_hybrid_scaling_factor);
3532
3533	if (id) {
3534	epp_values[EPP_INDEX_POWERSAVE] =
3535	FIELD_GET(POWERSAVE_MASK, id->driver_data);
3536	epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3537	FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3538	epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3539	FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3540	epp_values[EPP_INDEX_PERFORMANCE] =
3541	FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3542	pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3543	epp_values[EPP_INDEX_POWERSAVE],
3544	epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3545	epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3546	epp_values[EPP_INDEX_PERFORMANCE]);
3547	}
3548
3549	if (hybrid_id) {
3550	hybrid_scaling_factor = hybrid_id->driver_data;
3551	pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3552	}
3553
3554	}
3555
3556	mutex_lock(&intel_pstate_driver_lock);
3557	rc = intel_pstate_register_driver(driver: default_driver);
3558	mutex_unlock(lock: &intel_pstate_driver_lock);
3559	if (rc) {
3560	intel_pstate_sysfs_remove();
3561	return rc;
3562	}
3563
3564	if (hwp_active) {
3565	const struct x86_cpu_id *id;
3566
3567	id = x86_match_cpu(match: intel_pstate_cpu_ee_disable_ids);
3568	if (id) {
3569	set_power_ctl_ee_state(false);
3570	pr_info("Disabling energy efficiency optimization\n");
3571	}
3572
3573	pr_info("HWP enabled\n");
3574	} else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3575	pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3576	}
3577
3578	return 0;
3579	}
3580	device_initcall(intel_pstate_init);
3581
3582	static int __init intel_pstate_setup(char *str)
3583	{
3584	if (!str)
3585	return -EINVAL;
3586
3587	if (!strcmp(str, "disable"))
3588	no_load = 1;
3589	else if (!strcmp(str, "active"))
3590	default_driver = &intel_pstate;
3591	else if (!strcmp(str, "passive"))
3592	default_driver = &intel_cpufreq;
3593
3594	if (!strcmp(str, "no_hwp"))
3595	no_hwp = 1;
3596
3597	if (!strcmp(str, "force"))
3598	force_load = 1;
3599	if (!strcmp(str, "hwp_only"))
3600	hwp_only = 1;
3601	if (!strcmp(str, "per_cpu_perf_limits"))
3602	per_cpu_limits = true;
3603
3604	#ifdef CONFIG_ACPI
3605	if (!strcmp(str, "support_acpi_ppc"))
3606	acpi_ppc = true;
3607	#endif
3608
3609	return 0;
3610	}
3611	early_param("intel_pstate", intel_pstate_setup);
3612
3613	MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3614	MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3615