1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Driver for Audio DMA Controller (ADMAC) on t8103 (M1) and other Apple chips |
4 | * |
5 | * Copyright (C) The Asahi Linux Contributors |
6 | */ |
7 | |
8 | #include <linux/bits.h> |
9 | #include <linux/bitfield.h> |
10 | #include <linux/device.h> |
11 | #include <linux/init.h> |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> |
14 | #include <linux/of_dma.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/reset.h> |
17 | #include <linux/spinlock.h> |
18 | #include <linux/interrupt.h> |
19 | |
20 | #include "dmaengine.h" |
21 | |
22 | #define NCHANNELS_MAX 64 |
23 | #define IRQ_NOUTPUTS 4 |
24 | |
25 | /* |
26 | * For allocation purposes we split the cache |
27 | * memory into blocks of fixed size (given in bytes). |
28 | */ |
29 | #define SRAM_BLOCK 2048 |
30 | |
31 | #define RING_WRITE_SLOT GENMASK(1, 0) |
32 | #define RING_READ_SLOT GENMASK(5, 4) |
33 | #define RING_FULL BIT(9) |
34 | #define RING_EMPTY BIT(8) |
35 | #define RING_ERR BIT(10) |
36 | |
37 | #define STATUS_DESC_DONE BIT(0) |
38 | #define STATUS_ERR BIT(6) |
39 | |
40 | #define FLAG_DESC_NOTIFY BIT(16) |
41 | |
42 | #define REG_TX_START 0x0000 |
43 | #define REG_TX_STOP 0x0004 |
44 | #define REG_RX_START 0x0008 |
45 | #define REG_RX_STOP 0x000c |
46 | #define REG_IMPRINT 0x0090 |
47 | #define REG_TX_SRAM_SIZE 0x0094 |
48 | #define REG_RX_SRAM_SIZE 0x0098 |
49 | |
50 | #define REG_CHAN_CTL(ch) (0x8000 + (ch) * 0x200) |
51 | #define REG_CHAN_CTL_RST_RINGS BIT(0) |
52 | |
53 | #define REG_DESC_RING(ch) (0x8070 + (ch) * 0x200) |
54 | #define REG_REPORT_RING(ch) (0x8074 + (ch) * 0x200) |
55 | |
56 | #define REG_RESIDUE(ch) (0x8064 + (ch) * 0x200) |
57 | |
58 | #define REG_BUS_WIDTH(ch) (0x8040 + (ch) * 0x200) |
59 | |
60 | #define BUS_WIDTH_WORD_SIZE GENMASK(3, 0) |
61 | #define BUS_WIDTH_FRAME_SIZE GENMASK(7, 4) |
62 | #define BUS_WIDTH_8BIT 0x00 |
63 | #define BUS_WIDTH_16BIT 0x01 |
64 | #define BUS_WIDTH_32BIT 0x02 |
65 | #define BUS_WIDTH_FRAME_2_WORDS 0x10 |
66 | #define BUS_WIDTH_FRAME_4_WORDS 0x20 |
67 | |
68 | #define REG_CHAN_SRAM_CARVEOUT(ch) (0x8050 + (ch) * 0x200) |
69 | #define CHAN_SRAM_CARVEOUT_SIZE GENMASK(31, 16) |
70 | #define CHAN_SRAM_CARVEOUT_BASE GENMASK(15, 0) |
71 | |
72 | #define REG_CHAN_FIFOCTL(ch) (0x8054 + (ch) * 0x200) |
73 | #define CHAN_FIFOCTL_LIMIT GENMASK(31, 16) |
74 | #define CHAN_FIFOCTL_THRESHOLD GENMASK(15, 0) |
75 | |
76 | #define REG_DESC_WRITE(ch) (0x10000 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000) |
77 | #define REG_REPORT_READ(ch) (0x10100 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000) |
78 | |
79 | #define REG_TX_INTSTATE(idx) (0x0030 + (idx) * 4) |
80 | #define REG_RX_INTSTATE(idx) (0x0040 + (idx) * 4) |
81 | #define REG_GLOBAL_INTSTATE(idx) (0x0050 + (idx) * 4) |
82 | #define REG_CHAN_INTSTATUS(ch, idx) (0x8010 + (ch) * 0x200 + (idx) * 4) |
83 | #define REG_CHAN_INTMASK(ch, idx) (0x8020 + (ch) * 0x200 + (idx) * 4) |
84 | |
85 | struct admac_data; |
86 | struct admac_tx; |
87 | |
88 | struct admac_chan { |
89 | unsigned int no; |
90 | struct admac_data *host; |
91 | struct dma_chan chan; |
92 | struct tasklet_struct tasklet; |
93 | |
94 | u32 carveout; |
95 | |
96 | spinlock_t lock; |
97 | struct admac_tx *current_tx; |
98 | int nperiod_acks; |
99 | |
100 | /* |
101 | * We maintain a 'submitted' and 'issued' list mainly for interface |
102 | * correctness. Typical use of the driver (per channel) will be |
103 | * prepping, submitting and issuing a single cyclic transaction which |
104 | * will stay current until terminate_all is called. |
105 | */ |
106 | struct list_head submitted; |
107 | struct list_head issued; |
108 | |
109 | struct list_head to_free; |
110 | }; |
111 | |
112 | struct admac_sram { |
113 | u32 size; |
114 | /* |
115 | * SRAM_CARVEOUT has 16-bit fields, so the SRAM cannot be larger than |
116 | * 64K and a 32-bit bitfield over 2K blocks covers it. |
117 | */ |
118 | u32 allocated; |
119 | }; |
120 | |
121 | struct admac_data { |
122 | struct dma_device dma; |
123 | struct device *dev; |
124 | __iomem void *base; |
125 | struct reset_control *rstc; |
126 | |
127 | struct mutex cache_alloc_lock; |
128 | struct admac_sram txcache, rxcache; |
129 | |
130 | int irq; |
131 | int irq_index; |
132 | int nchannels; |
133 | struct admac_chan channels[] __counted_by(nchannels); |
134 | }; |
135 | |
136 | struct admac_tx { |
137 | struct dma_async_tx_descriptor tx; |
138 | bool cyclic; |
139 | dma_addr_t buf_addr; |
140 | dma_addr_t buf_end; |
141 | size_t buf_len; |
142 | size_t period_len; |
143 | |
144 | size_t submitted_pos; |
145 | size_t reclaimed_pos; |
146 | |
147 | struct list_head node; |
148 | }; |
149 | |
150 | static int admac_alloc_sram_carveout(struct admac_data *ad, |
151 | enum dma_transfer_direction dir, |
152 | u32 *out) |
153 | { |
154 | struct admac_sram *sram; |
155 | int i, ret = 0, nblocks; |
156 | |
157 | if (dir == DMA_MEM_TO_DEV) |
158 | sram = &ad->txcache; |
159 | else |
160 | sram = &ad->rxcache; |
161 | |
162 | mutex_lock(&ad->cache_alloc_lock); |
163 | |
164 | nblocks = sram->size / SRAM_BLOCK; |
165 | for (i = 0; i < nblocks; i++) |
166 | if (!(sram->allocated & BIT(i))) |
167 | break; |
168 | |
169 | if (i < nblocks) { |
170 | *out = FIELD_PREP(CHAN_SRAM_CARVEOUT_BASE, i * SRAM_BLOCK) | |
171 | FIELD_PREP(CHAN_SRAM_CARVEOUT_SIZE, SRAM_BLOCK); |
172 | sram->allocated |= BIT(i); |
173 | } else { |
174 | ret = -EBUSY; |
175 | } |
176 | |
177 | mutex_unlock(lock: &ad->cache_alloc_lock); |
178 | |
179 | return ret; |
180 | } |
181 | |
182 | static void admac_free_sram_carveout(struct admac_data *ad, |
183 | enum dma_transfer_direction dir, |
184 | u32 carveout) |
185 | { |
186 | struct admac_sram *sram; |
187 | u32 base = FIELD_GET(CHAN_SRAM_CARVEOUT_BASE, carveout); |
188 | int i; |
189 | |
190 | if (dir == DMA_MEM_TO_DEV) |
191 | sram = &ad->txcache; |
192 | else |
193 | sram = &ad->rxcache; |
194 | |
195 | if (WARN_ON(base >= sram->size)) |
196 | return; |
197 | |
198 | mutex_lock(&ad->cache_alloc_lock); |
199 | i = base / SRAM_BLOCK; |
200 | sram->allocated &= ~BIT(i); |
201 | mutex_unlock(lock: &ad->cache_alloc_lock); |
202 | } |
203 | |
204 | static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val) |
205 | { |
206 | void __iomem *addr = ad->base + reg; |
207 | u32 curr = readl_relaxed(addr); |
208 | |
209 | writel_relaxed((curr & ~mask) | (val & mask), addr); |
210 | } |
211 | |
212 | static struct admac_chan *to_admac_chan(struct dma_chan *chan) |
213 | { |
214 | return container_of(chan, struct admac_chan, chan); |
215 | } |
216 | |
217 | static struct admac_tx *to_admac_tx(struct dma_async_tx_descriptor *tx) |
218 | { |
219 | return container_of(tx, struct admac_tx, tx); |
220 | } |
221 | |
222 | static enum dma_transfer_direction admac_chan_direction(int channo) |
223 | { |
224 | /* Channel directions are hardwired */ |
225 | return (channo & 1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; |
226 | } |
227 | |
228 | static dma_cookie_t admac_tx_submit(struct dma_async_tx_descriptor *tx) |
229 | { |
230 | struct admac_tx *adtx = to_admac_tx(tx); |
231 | struct admac_chan *adchan = to_admac_chan(chan: tx->chan); |
232 | unsigned long flags; |
233 | dma_cookie_t cookie; |
234 | |
235 | spin_lock_irqsave(&adchan->lock, flags); |
236 | cookie = dma_cookie_assign(tx); |
237 | list_add_tail(new: &adtx->node, head: &adchan->submitted); |
238 | spin_unlock_irqrestore(lock: &adchan->lock, flags); |
239 | |
240 | return cookie; |
241 | } |
242 | |
243 | static int admac_desc_free(struct dma_async_tx_descriptor *tx) |
244 | { |
245 | kfree(objp: to_admac_tx(tx)); |
246 | |
247 | return 0; |
248 | } |
249 | |
250 | static struct dma_async_tx_descriptor *admac_prep_dma_cyclic( |
251 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
252 | size_t period_len, enum dma_transfer_direction direction, |
253 | unsigned long flags) |
254 | { |
255 | struct admac_chan *adchan = container_of(chan, struct admac_chan, chan); |
256 | struct admac_tx *adtx; |
257 | |
258 | if (direction != admac_chan_direction(channo: adchan->no)) |
259 | return NULL; |
260 | |
261 | adtx = kzalloc(size: sizeof(*adtx), GFP_NOWAIT); |
262 | if (!adtx) |
263 | return NULL; |
264 | |
265 | adtx->cyclic = true; |
266 | |
267 | adtx->buf_addr = buf_addr; |
268 | adtx->buf_len = buf_len; |
269 | adtx->buf_end = buf_addr + buf_len; |
270 | adtx->period_len = period_len; |
271 | |
272 | adtx->submitted_pos = 0; |
273 | adtx->reclaimed_pos = 0; |
274 | |
275 | dma_async_tx_descriptor_init(tx: &adtx->tx, chan); |
276 | adtx->tx.tx_submit = admac_tx_submit; |
277 | adtx->tx.desc_free = admac_desc_free; |
278 | |
279 | return &adtx->tx; |
280 | } |
281 | |
282 | /* |
283 | * Write one hardware descriptor for a dmaengine cyclic transaction. |
284 | */ |
285 | static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo, |
286 | struct admac_tx *tx) |
287 | { |
288 | dma_addr_t addr; |
289 | |
290 | addr = tx->buf_addr + (tx->submitted_pos % tx->buf_len); |
291 | |
292 | /* If happens means we have buggy code */ |
293 | WARN_ON_ONCE(addr + tx->period_len > tx->buf_end); |
294 | |
295 | dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n" , |
296 | channo, &addr, tx->period_len, FLAG_DESC_NOTIFY); |
297 | |
298 | writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo)); |
299 | writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo)); |
300 | writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo)); |
301 | writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo)); |
302 | |
303 | tx->submitted_pos += tx->period_len; |
304 | tx->submitted_pos %= 2 * tx->buf_len; |
305 | } |
306 | |
307 | /* |
308 | * Write all the hardware descriptors for a dmaengine cyclic |
309 | * transaction there is space for. |
310 | */ |
311 | static void admac_cyclic_write_desc(struct admac_data *ad, int channo, |
312 | struct admac_tx *tx) |
313 | { |
314 | int i; |
315 | |
316 | for (i = 0; i < 4; i++) { |
317 | if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL) |
318 | break; |
319 | admac_cyclic_write_one_desc(ad, channo, tx); |
320 | } |
321 | } |
322 | |
323 | static int admac_ring_noccupied_slots(int ringval) |
324 | { |
325 | int wrslot = FIELD_GET(RING_WRITE_SLOT, ringval); |
326 | int rdslot = FIELD_GET(RING_READ_SLOT, ringval); |
327 | |
328 | if (wrslot != rdslot) { |
329 | return (wrslot + 4 - rdslot) % 4; |
330 | } else { |
331 | WARN_ON((ringval & (RING_FULL | RING_EMPTY)) == 0); |
332 | |
333 | if (ringval & RING_FULL) |
334 | return 4; |
335 | else |
336 | return 0; |
337 | } |
338 | } |
339 | |
340 | /* |
341 | * Read from hardware the residue of a cyclic dmaengine transaction. |
342 | */ |
343 | static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo, |
344 | struct admac_tx *adtx) |
345 | { |
346 | u32 ring1, ring2; |
347 | u32 residue1, residue2; |
348 | int nreports; |
349 | size_t pos; |
350 | |
351 | ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo)); |
352 | residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo)); |
353 | ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo)); |
354 | residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo)); |
355 | |
356 | if (residue2 > residue1) { |
357 | /* |
358 | * Controller must have loaded next descriptor between |
359 | * the two residue reads |
360 | */ |
361 | nreports = admac_ring_noccupied_slots(ringval: ring1) + 1; |
362 | } else { |
363 | /* No descriptor load between the two reads, ring2 is safe to use */ |
364 | nreports = admac_ring_noccupied_slots(ringval: ring2); |
365 | } |
366 | |
367 | pos = adtx->reclaimed_pos + adtx->period_len * (nreports + 1) - residue2; |
368 | |
369 | return adtx->buf_len - pos % adtx->buf_len; |
370 | } |
371 | |
372 | static enum dma_status admac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
373 | struct dma_tx_state *txstate) |
374 | { |
375 | struct admac_chan *adchan = to_admac_chan(chan); |
376 | struct admac_data *ad = adchan->host; |
377 | struct admac_tx *adtx; |
378 | |
379 | enum dma_status ret; |
380 | size_t residue; |
381 | unsigned long flags; |
382 | |
383 | ret = dma_cookie_status(chan, cookie, state: txstate); |
384 | if (ret == DMA_COMPLETE || !txstate) |
385 | return ret; |
386 | |
387 | spin_lock_irqsave(&adchan->lock, flags); |
388 | adtx = adchan->current_tx; |
389 | |
390 | if (adtx && adtx->tx.cookie == cookie) { |
391 | ret = DMA_IN_PROGRESS; |
392 | residue = admac_cyclic_read_residue(ad, channo: adchan->no, adtx); |
393 | } else { |
394 | ret = DMA_IN_PROGRESS; |
395 | residue = 0; |
396 | list_for_each_entry(adtx, &adchan->issued, node) { |
397 | if (adtx->tx.cookie == cookie) { |
398 | residue = adtx->buf_len; |
399 | break; |
400 | } |
401 | } |
402 | } |
403 | spin_unlock_irqrestore(lock: &adchan->lock, flags); |
404 | |
405 | dma_set_residue(state: txstate, residue); |
406 | return ret; |
407 | } |
408 | |
409 | static void admac_start_chan(struct admac_chan *adchan) |
410 | { |
411 | struct admac_data *ad = adchan->host; |
412 | u32 startbit = 1 << (adchan->no / 2); |
413 | |
414 | writel_relaxed(STATUS_DESC_DONE | STATUS_ERR, |
415 | ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index)); |
416 | writel_relaxed(STATUS_DESC_DONE | STATUS_ERR, |
417 | ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index)); |
418 | |
419 | switch (admac_chan_direction(channo: adchan->no)) { |
420 | case DMA_MEM_TO_DEV: |
421 | writel_relaxed(startbit, ad->base + REG_TX_START); |
422 | break; |
423 | case DMA_DEV_TO_MEM: |
424 | writel_relaxed(startbit, ad->base + REG_RX_START); |
425 | break; |
426 | default: |
427 | break; |
428 | } |
429 | dev_dbg(adchan->host->dev, "ch%d start\n" , adchan->no); |
430 | } |
431 | |
432 | static void admac_stop_chan(struct admac_chan *adchan) |
433 | { |
434 | struct admac_data *ad = adchan->host; |
435 | u32 stopbit = 1 << (adchan->no / 2); |
436 | |
437 | switch (admac_chan_direction(channo: adchan->no)) { |
438 | case DMA_MEM_TO_DEV: |
439 | writel_relaxed(stopbit, ad->base + REG_TX_STOP); |
440 | break; |
441 | case DMA_DEV_TO_MEM: |
442 | writel_relaxed(stopbit, ad->base + REG_RX_STOP); |
443 | break; |
444 | default: |
445 | break; |
446 | } |
447 | dev_dbg(adchan->host->dev, "ch%d stop\n" , adchan->no); |
448 | } |
449 | |
450 | static void admac_reset_rings(struct admac_chan *adchan) |
451 | { |
452 | struct admac_data *ad = adchan->host; |
453 | |
454 | writel_relaxed(REG_CHAN_CTL_RST_RINGS, |
455 | ad->base + REG_CHAN_CTL(adchan->no)); |
456 | writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no)); |
457 | } |
458 | |
459 | static void admac_start_current_tx(struct admac_chan *adchan) |
460 | { |
461 | struct admac_data *ad = adchan->host; |
462 | int ch = adchan->no; |
463 | |
464 | admac_reset_rings(adchan); |
465 | writel_relaxed(0, ad->base + REG_CHAN_CTL(ch)); |
466 | |
467 | admac_cyclic_write_one_desc(ad, channo: ch, tx: adchan->current_tx); |
468 | admac_start_chan(adchan); |
469 | admac_cyclic_write_desc(ad, channo: ch, tx: adchan->current_tx); |
470 | } |
471 | |
472 | static void admac_issue_pending(struct dma_chan *chan) |
473 | { |
474 | struct admac_chan *adchan = to_admac_chan(chan); |
475 | struct admac_tx *tx; |
476 | unsigned long flags; |
477 | |
478 | spin_lock_irqsave(&adchan->lock, flags); |
479 | list_splice_tail_init(list: &adchan->submitted, head: &adchan->issued); |
480 | if (!list_empty(head: &adchan->issued) && !adchan->current_tx) { |
481 | tx = list_first_entry(&adchan->issued, struct admac_tx, node); |
482 | list_del(entry: &tx->node); |
483 | |
484 | adchan->current_tx = tx; |
485 | adchan->nperiod_acks = 0; |
486 | admac_start_current_tx(adchan); |
487 | } |
488 | spin_unlock_irqrestore(lock: &adchan->lock, flags); |
489 | } |
490 | |
491 | static int admac_pause(struct dma_chan *chan) |
492 | { |
493 | struct admac_chan *adchan = to_admac_chan(chan); |
494 | |
495 | admac_stop_chan(adchan); |
496 | |
497 | return 0; |
498 | } |
499 | |
500 | static int admac_resume(struct dma_chan *chan) |
501 | { |
502 | struct admac_chan *adchan = to_admac_chan(chan); |
503 | |
504 | admac_start_chan(adchan); |
505 | |
506 | return 0; |
507 | } |
508 | |
509 | static int admac_terminate_all(struct dma_chan *chan) |
510 | { |
511 | struct admac_chan *adchan = to_admac_chan(chan); |
512 | unsigned long flags; |
513 | |
514 | spin_lock_irqsave(&adchan->lock, flags); |
515 | admac_stop_chan(adchan); |
516 | admac_reset_rings(adchan); |
517 | |
518 | if (adchan->current_tx) { |
519 | list_add_tail(new: &adchan->current_tx->node, head: &adchan->to_free); |
520 | adchan->current_tx = NULL; |
521 | } |
522 | /* |
523 | * Descriptors can only be freed after the tasklet |
524 | * has been killed (in admac_synchronize). |
525 | */ |
526 | list_splice_tail_init(list: &adchan->submitted, head: &adchan->to_free); |
527 | list_splice_tail_init(list: &adchan->issued, head: &adchan->to_free); |
528 | spin_unlock_irqrestore(lock: &adchan->lock, flags); |
529 | |
530 | return 0; |
531 | } |
532 | |
533 | static void admac_synchronize(struct dma_chan *chan) |
534 | { |
535 | struct admac_chan *adchan = to_admac_chan(chan); |
536 | struct admac_tx *adtx, *_adtx; |
537 | unsigned long flags; |
538 | LIST_HEAD(head); |
539 | |
540 | spin_lock_irqsave(&adchan->lock, flags); |
541 | list_splice_tail_init(list: &adchan->to_free, head: &head); |
542 | spin_unlock_irqrestore(lock: &adchan->lock, flags); |
543 | |
544 | tasklet_kill(t: &adchan->tasklet); |
545 | |
546 | list_for_each_entry_safe(adtx, _adtx, &head, node) { |
547 | list_del(entry: &adtx->node); |
548 | admac_desc_free(tx: &adtx->tx); |
549 | } |
550 | } |
551 | |
552 | static int admac_alloc_chan_resources(struct dma_chan *chan) |
553 | { |
554 | struct admac_chan *adchan = to_admac_chan(chan); |
555 | struct admac_data *ad = adchan->host; |
556 | int ret; |
557 | |
558 | dma_cookie_init(chan: &adchan->chan); |
559 | ret = admac_alloc_sram_carveout(ad, dir: admac_chan_direction(channo: adchan->no), |
560 | out: &adchan->carveout); |
561 | if (ret < 0) |
562 | return ret; |
563 | |
564 | writel_relaxed(adchan->carveout, |
565 | ad->base + REG_CHAN_SRAM_CARVEOUT(adchan->no)); |
566 | return 0; |
567 | } |
568 | |
569 | static void admac_free_chan_resources(struct dma_chan *chan) |
570 | { |
571 | struct admac_chan *adchan = to_admac_chan(chan); |
572 | |
573 | admac_terminate_all(chan); |
574 | admac_synchronize(chan); |
575 | admac_free_sram_carveout(ad: adchan->host, dir: admac_chan_direction(channo: adchan->no), |
576 | carveout: adchan->carveout); |
577 | } |
578 | |
579 | static struct dma_chan *admac_dma_of_xlate(struct of_phandle_args *dma_spec, |
580 | struct of_dma *ofdma) |
581 | { |
582 | struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data; |
583 | unsigned int index; |
584 | |
585 | if (dma_spec->args_count != 1) |
586 | return NULL; |
587 | |
588 | index = dma_spec->args[0]; |
589 | |
590 | if (index >= ad->nchannels) { |
591 | dev_err(ad->dev, "channel index %u out of bounds\n" , index); |
592 | return NULL; |
593 | } |
594 | |
595 | return dma_get_slave_channel(chan: &ad->channels[index].chan); |
596 | } |
597 | |
598 | static int admac_drain_reports(struct admac_data *ad, int channo) |
599 | { |
600 | int count; |
601 | |
602 | for (count = 0; count < 4; count++) { |
603 | u32 countval_hi, countval_lo, unk1, flags; |
604 | |
605 | if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY) |
606 | break; |
607 | |
608 | countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo)); |
609 | countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo)); |
610 | unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo)); |
611 | flags = readl_relaxed(ad->base + REG_REPORT_READ(channo)); |
612 | |
613 | dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n" , |
614 | channo, ((u64) countval_hi) << 32 | countval_lo, unk1, flags); |
615 | } |
616 | |
617 | return count; |
618 | } |
619 | |
620 | static void admac_handle_status_err(struct admac_data *ad, int channo) |
621 | { |
622 | bool handled = false; |
623 | |
624 | if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) { |
625 | writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo)); |
626 | dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n" , channo); |
627 | handled = true; |
628 | } |
629 | |
630 | if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) { |
631 | writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo)); |
632 | dev_err_ratelimited(ad->dev, "ch%d report ring error\n" , channo); |
633 | handled = true; |
634 | } |
635 | |
636 | if (unlikely(!handled)) { |
637 | dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n" , channo); |
638 | admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index), |
639 | STATUS_ERR, val: 0); |
640 | } |
641 | } |
642 | |
643 | static void admac_handle_status_desc_done(struct admac_data *ad, int channo) |
644 | { |
645 | struct admac_chan *adchan = &ad->channels[channo]; |
646 | unsigned long flags; |
647 | int nreports; |
648 | |
649 | writel_relaxed(STATUS_DESC_DONE, |
650 | ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index)); |
651 | |
652 | spin_lock_irqsave(&adchan->lock, flags); |
653 | nreports = admac_drain_reports(ad, channo); |
654 | |
655 | if (adchan->current_tx) { |
656 | struct admac_tx *tx = adchan->current_tx; |
657 | |
658 | adchan->nperiod_acks += nreports; |
659 | tx->reclaimed_pos += nreports * tx->period_len; |
660 | tx->reclaimed_pos %= 2 * tx->buf_len; |
661 | |
662 | admac_cyclic_write_desc(ad, channo, tx); |
663 | tasklet_schedule(t: &adchan->tasklet); |
664 | } |
665 | spin_unlock_irqrestore(lock: &adchan->lock, flags); |
666 | } |
667 | |
668 | static void admac_handle_chan_int(struct admac_data *ad, int no) |
669 | { |
670 | u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index)); |
671 | |
672 | if (cause & STATUS_ERR) |
673 | admac_handle_status_err(ad, channo: no); |
674 | |
675 | if (cause & STATUS_DESC_DONE) |
676 | admac_handle_status_desc_done(ad, channo: no); |
677 | } |
678 | |
679 | static irqreturn_t admac_interrupt(int irq, void *devid) |
680 | { |
681 | struct admac_data *ad = devid; |
682 | u32 rx_intstate, tx_intstate, global_intstate; |
683 | int i; |
684 | |
685 | rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index)); |
686 | tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index)); |
687 | global_intstate = readl_relaxed(ad->base + REG_GLOBAL_INTSTATE(ad->irq_index)); |
688 | |
689 | if (!tx_intstate && !rx_intstate && !global_intstate) |
690 | return IRQ_NONE; |
691 | |
692 | for (i = 0; i < ad->nchannels; i += 2) { |
693 | if (tx_intstate & 1) |
694 | admac_handle_chan_int(ad, no: i); |
695 | tx_intstate >>= 1; |
696 | } |
697 | |
698 | for (i = 1; i < ad->nchannels; i += 2) { |
699 | if (rx_intstate & 1) |
700 | admac_handle_chan_int(ad, no: i); |
701 | rx_intstate >>= 1; |
702 | } |
703 | |
704 | if (global_intstate) { |
705 | dev_warn(ad->dev, "clearing unknown global interrupt flag: %x\n" , |
706 | global_intstate); |
707 | writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index)); |
708 | } |
709 | |
710 | return IRQ_HANDLED; |
711 | } |
712 | |
713 | static void admac_chan_tasklet(struct tasklet_struct *t) |
714 | { |
715 | struct admac_chan *adchan = from_tasklet(adchan, t, tasklet); |
716 | struct admac_tx *adtx; |
717 | struct dmaengine_desc_callback cb; |
718 | struct dmaengine_result tx_result; |
719 | int nacks; |
720 | |
721 | spin_lock_irq(lock: &adchan->lock); |
722 | adtx = adchan->current_tx; |
723 | nacks = adchan->nperiod_acks; |
724 | adchan->nperiod_acks = 0; |
725 | spin_unlock_irq(lock: &adchan->lock); |
726 | |
727 | if (!adtx || !nacks) |
728 | return; |
729 | |
730 | tx_result.result = DMA_TRANS_NOERROR; |
731 | tx_result.residue = 0; |
732 | |
733 | dmaengine_desc_get_callback(tx: &adtx->tx, cb: &cb); |
734 | while (nacks--) |
735 | dmaengine_desc_callback_invoke(cb: &cb, result: &tx_result); |
736 | } |
737 | |
738 | static int admac_device_config(struct dma_chan *chan, |
739 | struct dma_slave_config *config) |
740 | { |
741 | struct admac_chan *adchan = to_admac_chan(chan); |
742 | struct admac_data *ad = adchan->host; |
743 | bool is_tx = admac_chan_direction(channo: adchan->no) == DMA_MEM_TO_DEV; |
744 | int wordsize = 0; |
745 | u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) & |
746 | ~(BUS_WIDTH_WORD_SIZE | BUS_WIDTH_FRAME_SIZE); |
747 | |
748 | switch (is_tx ? config->dst_addr_width : config->src_addr_width) { |
749 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
750 | wordsize = 1; |
751 | bus_width |= BUS_WIDTH_8BIT; |
752 | break; |
753 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
754 | wordsize = 2; |
755 | bus_width |= BUS_WIDTH_16BIT; |
756 | break; |
757 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
758 | wordsize = 4; |
759 | bus_width |= BUS_WIDTH_32BIT; |
760 | break; |
761 | default: |
762 | return -EINVAL; |
763 | } |
764 | |
765 | /* |
766 | * We take port_window_size to be the number of words in a frame. |
767 | * |
768 | * The controller has some means of out-of-band signalling, to the peripheral, |
769 | * of words position in a frame. That's where the importance of this control |
770 | * comes from. |
771 | */ |
772 | switch (is_tx ? config->dst_port_window_size : config->src_port_window_size) { |
773 | case 0 ... 1: |
774 | break; |
775 | case 2: |
776 | bus_width |= BUS_WIDTH_FRAME_2_WORDS; |
777 | break; |
778 | case 4: |
779 | bus_width |= BUS_WIDTH_FRAME_4_WORDS; |
780 | break; |
781 | default: |
782 | return -EINVAL; |
783 | } |
784 | |
785 | writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no)); |
786 | |
787 | /* |
788 | * By FIFOCTL_LIMIT we seem to set the maximal number of bytes allowed to be |
789 | * held in controller's per-channel FIFO. Transfers seem to be triggered |
790 | * around the time FIFO occupancy touches FIFOCTL_THRESHOLD. |
791 | * |
792 | * The numbers we set are more or less arbitrary. |
793 | */ |
794 | writel_relaxed(FIELD_PREP(CHAN_FIFOCTL_LIMIT, 0x30 * wordsize) |
795 | | FIELD_PREP(CHAN_FIFOCTL_THRESHOLD, 0x18 * wordsize), |
796 | ad->base + REG_CHAN_FIFOCTL(adchan->no)); |
797 | |
798 | return 0; |
799 | } |
800 | |
801 | static int admac_probe(struct platform_device *pdev) |
802 | { |
803 | struct device_node *np = pdev->dev.of_node; |
804 | struct admac_data *ad; |
805 | struct dma_device *dma; |
806 | int nchannels; |
807 | int err, irq, i; |
808 | |
809 | err = of_property_read_u32(np, propname: "dma-channels" , out_value: &nchannels); |
810 | if (err || nchannels > NCHANNELS_MAX) { |
811 | dev_err(&pdev->dev, "missing or invalid dma-channels property\n" ); |
812 | return -EINVAL; |
813 | } |
814 | |
815 | ad = devm_kzalloc(dev: &pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL); |
816 | if (!ad) |
817 | return -ENOMEM; |
818 | |
819 | platform_set_drvdata(pdev, data: ad); |
820 | ad->dev = &pdev->dev; |
821 | ad->nchannels = nchannels; |
822 | mutex_init(&ad->cache_alloc_lock); |
823 | |
824 | /* |
825 | * The controller has 4 IRQ outputs. Try them all until |
826 | * we find one we can use. |
827 | */ |
828 | for (i = 0; i < IRQ_NOUTPUTS; i++) { |
829 | irq = platform_get_irq_optional(pdev, i); |
830 | if (irq >= 0) { |
831 | ad->irq_index = i; |
832 | break; |
833 | } |
834 | } |
835 | |
836 | if (irq < 0) |
837 | return dev_err_probe(dev: &pdev->dev, err: irq, fmt: "no usable interrupt\n" ); |
838 | ad->irq = irq; |
839 | |
840 | ad->base = devm_platform_ioremap_resource(pdev, index: 0); |
841 | if (IS_ERR(ptr: ad->base)) |
842 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: ad->base), |
843 | fmt: "unable to obtain MMIO resource\n" ); |
844 | |
845 | ad->rstc = devm_reset_control_get_optional_shared(dev: &pdev->dev, NULL); |
846 | if (IS_ERR(ptr: ad->rstc)) |
847 | return PTR_ERR(ptr: ad->rstc); |
848 | |
849 | dma = &ad->dma; |
850 | |
851 | dma_cap_set(DMA_PRIVATE, dma->cap_mask); |
852 | dma_cap_set(DMA_CYCLIC, dma->cap_mask); |
853 | |
854 | dma->dev = &pdev->dev; |
855 | dma->device_alloc_chan_resources = admac_alloc_chan_resources; |
856 | dma->device_free_chan_resources = admac_free_chan_resources; |
857 | dma->device_tx_status = admac_tx_status; |
858 | dma->device_issue_pending = admac_issue_pending; |
859 | dma->device_terminate_all = admac_terminate_all; |
860 | dma->device_synchronize = admac_synchronize; |
861 | dma->device_prep_dma_cyclic = admac_prep_dma_cyclic; |
862 | dma->device_config = admac_device_config; |
863 | dma->device_pause = admac_pause; |
864 | dma->device_resume = admac_resume; |
865 | |
866 | dma->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); |
867 | dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
868 | dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | |
869 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | |
870 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
871 | dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | |
872 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | |
873 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
874 | |
875 | INIT_LIST_HEAD(list: &dma->channels); |
876 | for (i = 0; i < nchannels; i++) { |
877 | struct admac_chan *adchan = &ad->channels[i]; |
878 | |
879 | adchan->host = ad; |
880 | adchan->no = i; |
881 | adchan->chan.device = &ad->dma; |
882 | spin_lock_init(&adchan->lock); |
883 | INIT_LIST_HEAD(list: &adchan->submitted); |
884 | INIT_LIST_HEAD(list: &adchan->issued); |
885 | INIT_LIST_HEAD(list: &adchan->to_free); |
886 | list_add_tail(new: &adchan->chan.device_node, head: &dma->channels); |
887 | tasklet_setup(t: &adchan->tasklet, callback: admac_chan_tasklet); |
888 | } |
889 | |
890 | err = reset_control_reset(rstc: ad->rstc); |
891 | if (err) |
892 | return dev_err_probe(dev: &pdev->dev, err, |
893 | fmt: "unable to trigger reset\n" ); |
894 | |
895 | err = request_irq(irq, handler: admac_interrupt, flags: 0, name: dev_name(dev: &pdev->dev), dev: ad); |
896 | if (err) { |
897 | dev_err_probe(dev: &pdev->dev, err, |
898 | fmt: "unable to register interrupt\n" ); |
899 | goto free_reset; |
900 | } |
901 | |
902 | err = dma_async_device_register(device: &ad->dma); |
903 | if (err) { |
904 | dev_err_probe(dev: &pdev->dev, err, fmt: "failed to register DMA device\n" ); |
905 | goto free_irq; |
906 | } |
907 | |
908 | err = of_dma_controller_register(np: pdev->dev.of_node, of_dma_xlate: admac_dma_of_xlate, data: ad); |
909 | if (err) { |
910 | dma_async_device_unregister(device: &ad->dma); |
911 | dev_err_probe(dev: &pdev->dev, err, fmt: "failed to register with OF\n" ); |
912 | goto free_irq; |
913 | } |
914 | |
915 | ad->txcache.size = readl_relaxed(ad->base + REG_TX_SRAM_SIZE); |
916 | ad->rxcache.size = readl_relaxed(ad->base + REG_RX_SRAM_SIZE); |
917 | |
918 | dev_info(&pdev->dev, "Audio DMA Controller\n" ); |
919 | dev_info(&pdev->dev, "imprint %x TX cache %u RX cache %u\n" , |
920 | readl_relaxed(ad->base + REG_IMPRINT), ad->txcache.size, ad->rxcache.size); |
921 | |
922 | return 0; |
923 | |
924 | free_irq: |
925 | free_irq(ad->irq, ad); |
926 | free_reset: |
927 | reset_control_rearm(rstc: ad->rstc); |
928 | return err; |
929 | } |
930 | |
931 | static void admac_remove(struct platform_device *pdev) |
932 | { |
933 | struct admac_data *ad = platform_get_drvdata(pdev); |
934 | |
935 | of_dma_controller_free(np: pdev->dev.of_node); |
936 | dma_async_device_unregister(device: &ad->dma); |
937 | free_irq(ad->irq, ad); |
938 | reset_control_rearm(rstc: ad->rstc); |
939 | } |
940 | |
941 | static const struct of_device_id admac_of_match[] = { |
942 | { .compatible = "apple,admac" , }, |
943 | { } |
944 | }; |
945 | MODULE_DEVICE_TABLE(of, admac_of_match); |
946 | |
947 | static struct platform_driver apple_admac_driver = { |
948 | .driver = { |
949 | .name = "apple-admac" , |
950 | .of_match_table = admac_of_match, |
951 | }, |
952 | .probe = admac_probe, |
953 | .remove_new = admac_remove, |
954 | }; |
955 | module_platform_driver(apple_admac_driver); |
956 | |
957 | MODULE_AUTHOR("Martin Povišer <povik+lin@cutebit.org>" ); |
958 | MODULE_DESCRIPTION("Driver for Audio DMA Controller (ADMAC) on Apple SoCs" ); |
959 | MODULE_LICENSE("GPL" ); |
960 | |