1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Intel(R) 10nm server memory controller.
4 * Copyright (c) 2019, Intel Corporation.
5 *
6 */
7
8#include <linux/kernel.h>
9#include <linux/io.h>
10#include <asm/cpu_device_id.h>
11#include <asm/intel-family.h>
12#include <asm/mce.h>
13#include "edac_module.h"
14#include "skx_common.h"
15
16#define I10NM_REVISION "v0.0.6"
17#define EDAC_MOD_STR "i10nm_edac"
18
19/* Debug macros */
20#define i10nm_printk(level, fmt, arg...) \
21 edac_printk(level, "i10nm", fmt, ##arg)
22
23#define I10NM_GET_SCK_BAR(d, reg) \
24 pci_read_config_dword((d)->uracu, 0xd0, &(reg))
25#define I10NM_GET_IMC_BAR(d, i, reg) \
26 pci_read_config_dword((d)->uracu, \
27 (res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg))
28#define I10NM_GET_SAD(d, offset, i, reg)\
29 pci_read_config_dword((d)->sad_all, (offset) + (i) * \
30 (res_cfg->type == GNR ? 12 : 8), &(reg))
31#define I10NM_GET_HBM_IMC_BAR(d, reg) \
32 pci_read_config_dword((d)->uracu, 0xd4, &(reg))
33#define I10NM_GET_CAPID3_CFG(d, reg) \
34 pci_read_config_dword((d)->pcu_cr3, \
35 res_cfg->type == GNR ? 0x290 : 0x90, &(reg))
36#define I10NM_GET_CAPID5_CFG(d, reg) \
37 pci_read_config_dword((d)->pcu_cr3, \
38 res_cfg->type == GNR ? 0x298 : 0x98, &(reg))
39#define I10NM_GET_DIMMMTR(m, i, j) \
40 readl((m)->mbase + ((m)->hbm_mc ? 0x80c : \
41 (res_cfg->type == GNR ? 0xc0c : 0x2080c)) + \
42 (i) * (m)->chan_mmio_sz + (j) * 4)
43#define I10NM_GET_MCDDRTCFG(m, i) \
44 readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
45 (i) * (m)->chan_mmio_sz)
46#define I10NM_GET_MCMTR(m, i) \
47 readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : \
48 (res_cfg->type == GNR ? 0xaf8 : 0x20ef8)) + \
49 (i) * (m)->chan_mmio_sz)
50#define I10NM_GET_REG32(m, i, offset) \
51 readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
52#define I10NM_GET_REG64(m, i, offset) \
53 readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
54#define I10NM_SET_REG32(m, i, offset, v) \
55 writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
56
57#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
58#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
59#define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
60 GET_BITFIELD(reg, 0, 10) + 1) << 12)
61#define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \
62 ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
63
64#define I10NM_GNR_IMC_MMIO_OFFSET 0x24c000
65#define I10NM_GNR_D_IMC_MMIO_OFFSET 0x206000
66#define I10NM_GNR_IMC_MMIO_SIZE 0x4000
67#define I10NM_HBM_IMC_MMIO_SIZE 0x9000
68#define I10NM_DDR_IMC_CH_CNT(reg) GET_BITFIELD(reg, 21, 24)
69#define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30)
70#define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29)
71
72#define I10NM_MAX_SAD 16
73#define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
74#define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5)
75
76static struct list_head *i10nm_edac_list;
77
78static struct res_config *res_cfg;
79static int retry_rd_err_log;
80static int decoding_via_mca;
81static bool mem_cfg_2lm;
82
83static struct reg_rrl icx_reg_rrl_ddr = {
84 .set_num = 2,
85 .reg_num = 6,
86 .modes = {LRE_SCRUB, LRE_DEMAND},
87 .offsets = {
88 {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8},
89 {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0},
90 },
91 .widths = {4, 4, 4, 4, 4, 8},
92 .v_mask = BIT(0),
93 .uc_mask = BIT(1),
94 .over_mask = BIT(2),
95 .en_patspr_mask = BIT(13),
96 .noover_mask = BIT(14),
97 .en_mask = BIT(15),
98
99 .cecnt_num = 4,
100 .cecnt_offsets = {0x22c18, 0x22c1c, 0x22c20, 0x22c24},
101 .cecnt_widths = {4, 4, 4, 4},
102};
103
104static struct reg_rrl spr_reg_rrl_ddr = {
105 .set_num = 3,
106 .reg_num = 6,
107 .modes = {LRE_SCRUB, LRE_DEMAND, FRE_DEMAND},
108 .offsets = {
109 {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8},
110 {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0},
111 {0x22c70, 0x22d80, 0x22f18, 0x22d58, 0x22c64, 0x20f10},
112 },
113 .widths = {4, 4, 8, 4, 4, 8},
114 .v_mask = BIT(0),
115 .uc_mask = BIT(1),
116 .over_mask = BIT(2),
117 .en_patspr_mask = BIT(13),
118 .noover_mask = BIT(14),
119 .en_mask = BIT(15),
120
121 .cecnt_num = 4,
122 .cecnt_offsets = {0x22c18, 0x22c1c, 0x22c20, 0x22c24},
123 .cecnt_widths = {4, 4, 4, 4},
124};
125
126static struct reg_rrl spr_reg_rrl_hbm_pch0 = {
127 .set_num = 2,
128 .reg_num = 6,
129 .modes = {LRE_SCRUB, LRE_DEMAND},
130 .offsets = {
131 {0x2860, 0x2854, 0x2b08, 0x2858, 0x2828, 0x0ed8},
132 {0x2a54, 0x2a60, 0x2b10, 0x2a58, 0x2a5c, 0x0ee0},
133 },
134 .widths = {4, 4, 8, 4, 4, 8},
135 .v_mask = BIT(0),
136 .uc_mask = BIT(1),
137 .over_mask = BIT(2),
138 .en_patspr_mask = BIT(13),
139 .noover_mask = BIT(14),
140 .en_mask = BIT(15),
141
142 .cecnt_num = 4,
143 .cecnt_offsets = {0x2818, 0x281c, 0x2820, 0x2824},
144 .cecnt_widths = {4, 4, 4, 4},
145};
146
147static struct reg_rrl spr_reg_rrl_hbm_pch1 = {
148 .set_num = 2,
149 .reg_num = 6,
150 .modes = {LRE_SCRUB, LRE_DEMAND},
151 .offsets = {
152 {0x2c60, 0x2c54, 0x2f08, 0x2c58, 0x2c28, 0x0fa8},
153 {0x2e54, 0x2e60, 0x2f10, 0x2e58, 0x2e5c, 0x0fb0},
154 },
155 .widths = {4, 4, 8, 4, 4, 8},
156 .v_mask = BIT(0),
157 .uc_mask = BIT(1),
158 .over_mask = BIT(2),
159 .en_patspr_mask = BIT(13),
160 .noover_mask = BIT(14),
161 .en_mask = BIT(15),
162
163 .cecnt_num = 4,
164 .cecnt_offsets = {0x2c18, 0x2c1c, 0x2c20, 0x2c24},
165 .cecnt_widths = {4, 4, 4, 4},
166};
167
168static struct reg_rrl gnr_reg_rrl_ddr = {
169 .set_num = 4,
170 .reg_num = 6,
171 .modes = {FRE_SCRUB, FRE_DEMAND, LRE_SCRUB, LRE_DEMAND},
172 .offsets = {
173 {0x2f10, 0x2f20, 0x2f30, 0x2f50, 0x2f60, 0xba0},
174 {0x2f14, 0x2f24, 0x2f38, 0x2f54, 0x2f64, 0xba8},
175 {0x2f18, 0x2f28, 0x2f40, 0x2f58, 0x2f68, 0xbb0},
176 {0x2f1c, 0x2f2c, 0x2f48, 0x2f5c, 0x2f6c, 0xbb8},
177 },
178 .widths = {4, 4, 8, 4, 4, 8},
179 .v_mask = BIT(0),
180 .uc_mask = BIT(1),
181 .over_mask = BIT(2),
182 .en_patspr_mask = BIT(14),
183 .noover_mask = BIT(15),
184 .en_mask = BIT(12),
185
186 .cecnt_num = 8,
187 .cecnt_offsets = {0x2c10, 0x2c14, 0x2c18, 0x2c1c, 0x2c20, 0x2c24, 0x2c28, 0x2c2c},
188 .cecnt_widths = {4, 4, 4, 4, 4, 4, 4, 4},
189};
190
191static u64 read_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width)
192{
193 switch (width) {
194 case 4:
195 return I10NM_GET_REG32(imc, chan, offset);
196 case 8:
197 return I10NM_GET_REG64(imc, chan, offset);
198 default:
199 i10nm_printk(KERN_ERR, "Invalid readd RRL 0x%x width %d\n", offset, width);
200 return 0;
201 }
202}
203
204static void write_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width, u64 val)
205{
206 switch (width) {
207 case 4:
208 return I10NM_SET_REG32(imc, chan, offset, (u32)val);
209 default:
210 i10nm_printk(KERN_ERR, "Invalid write RRL 0x%x width %d\n", offset, width);
211 }
212}
213
214static void enable_rrl(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
215 int rrl_set, bool enable, u32 *rrl_ctl)
216{
217 enum rrl_mode mode = rrl->modes[rrl_set];
218 u32 offset = rrl->offsets[rrl_set][0], v;
219 u8 width = rrl->widths[0];
220 bool first, scrub;
221
222 /* First or last read error. */
223 first = (mode == FRE_SCRUB || mode == FRE_DEMAND);
224 /* Patrol scrub or on-demand read error. */
225 scrub = (mode == FRE_SCRUB || mode == LRE_SCRUB);
226
227 v = read_imc_reg(imc, chan, offset, width);
228
229 if (enable) {
230 /* Save default configurations. */
231 *rrl_ctl = v;
232 v &= ~rrl->uc_mask;
233
234 if (first)
235 v |= rrl->noover_mask;
236 else
237 v &= ~rrl->noover_mask;
238
239 if (scrub)
240 v |= rrl->en_patspr_mask;
241 else
242 v &= ~rrl->en_patspr_mask;
243
244 v |= rrl->en_mask;
245 } else {
246 /* Restore default configurations. */
247 if (*rrl_ctl & rrl->uc_mask)
248 v |= rrl->uc_mask;
249
250 if (first) {
251 if (!(*rrl_ctl & rrl->noover_mask))
252 v &= ~rrl->noover_mask;
253 } else {
254 if (*rrl_ctl & rrl->noover_mask)
255 v |= rrl->noover_mask;
256 }
257
258 if (scrub) {
259 if (!(*rrl_ctl & rrl->en_patspr_mask))
260 v &= ~rrl->en_patspr_mask;
261 } else {
262 if (*rrl_ctl & rrl->en_patspr_mask)
263 v |= rrl->en_patspr_mask;
264 }
265
266 if (!(*rrl_ctl & rrl->en_mask))
267 v &= ~rrl->en_mask;
268 }
269
270 write_imc_reg(imc, chan, offset, width, val: v);
271}
272
273static void enable_rrls(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
274 bool enable, u32 *rrl_ctl)
275{
276 for (int i = 0; i < rrl->set_num; i++)
277 enable_rrl(imc, chan, rrl, rrl_set: i, enable, rrl_ctl: rrl_ctl + i);
278}
279
280static void enable_rrls_ddr(struct skx_imc *imc, bool enable)
281{
282 struct reg_rrl *rrl_ddr = res_cfg->reg_rrl_ddr;
283 int i, chan_num = res_cfg->ddr_chan_num;
284 struct skx_channel *chan = imc->chan;
285
286 if (!imc->mbase)
287 return;
288
289 for (i = 0; i < chan_num; i++)
290 enable_rrls(imc, chan: i, rrl: rrl_ddr, enable, rrl_ctl: chan[i].rrl_ctl[0]);
291}
292
293static void enable_rrls_hbm(struct skx_imc *imc, bool enable)
294{
295 struct reg_rrl **rrl_hbm = res_cfg->reg_rrl_hbm;
296 int i, chan_num = res_cfg->hbm_chan_num;
297 struct skx_channel *chan = imc->chan;
298
299 if (!imc->mbase || !imc->hbm_mc || !rrl_hbm[0] || !rrl_hbm[1])
300 return;
301
302 for (i = 0; i < chan_num; i++) {
303 enable_rrls(imc, chan: i, rrl: rrl_hbm[0], enable, rrl_ctl: chan[i].rrl_ctl[0]);
304 enable_rrls(imc, chan: i, rrl: rrl_hbm[1], enable, rrl_ctl: chan[i].rrl_ctl[1]);
305 }
306}
307
308static void enable_retry_rd_err_log(bool enable)
309{
310 struct skx_dev *d;
311 int i, imc_num;
312
313 edac_dbg(2, "\n");
314
315 list_for_each_entry(d, i10nm_edac_list, list) {
316 imc_num = res_cfg->ddr_imc_num;
317 for (i = 0; i < imc_num; i++)
318 enable_rrls_ddr(imc: &d->imc[i], enable);
319
320 imc_num += res_cfg->hbm_imc_num;
321 for (; i < imc_num; i++)
322 enable_rrls_hbm(imc: &d->imc[i], enable);
323 }
324}
325
326static void show_retry_rd_err_log(struct decoded_addr *res, char *msg,
327 int len, bool scrub_err)
328{
329 int i, j, n, ch = res->channel, pch = res->cs & 1;
330 struct skx_imc *imc = &res->dev->imc[res->imc];
331 u64 log, corr, status_mask;
332 struct reg_rrl *rrl;
333 bool scrub;
334 u32 offset;
335 u8 width;
336
337 if (!imc->mbase)
338 return;
339
340 rrl = imc->hbm_mc ? res_cfg->reg_rrl_hbm[pch] : res_cfg->reg_rrl_ddr;
341
342 if (!rrl)
343 return;
344
345 status_mask = rrl->over_mask | rrl->uc_mask | rrl->v_mask;
346
347 n = scnprintf(buf: msg, size: len, fmt: " retry_rd_err_log[");
348 for (i = 0; i < rrl->set_num; i++) {
349 scrub = (rrl->modes[i] == FRE_SCRUB || rrl->modes[i] == LRE_SCRUB);
350 if (scrub_err != scrub)
351 continue;
352
353 for (j = 0; j < rrl->reg_num && len - n > 0; j++) {
354 offset = rrl->offsets[i][j];
355 width = rrl->widths[j];
356 log = read_imc_reg(imc, chan: ch, offset, width);
357
358 if (width == 4)
359 n += scnprintf(buf: msg + n, size: len - n, fmt: "%.8llx ", log);
360 else
361 n += scnprintf(buf: msg + n, size: len - n, fmt: "%.16llx ", log);
362
363 /* Clear RRL status if RRL in Linux control mode. */
364 if (retry_rd_err_log == 2 && !j && (log & status_mask))
365 write_imc_reg(imc, chan: ch, offset, width, val: log & ~status_mask);
366 }
367 }
368
369 /* Move back one space. */
370 n--;
371 n += scnprintf(buf: msg + n, size: len - n, fmt: "]");
372
373 if (len - n > 0) {
374 n += scnprintf(buf: msg + n, size: len - n, fmt: " correrrcnt[");
375 for (i = 0; i < rrl->cecnt_num && len - n > 0; i++) {
376 offset = rrl->cecnt_offsets[i];
377 width = rrl->cecnt_widths[i];
378 corr = read_imc_reg(imc, chan: ch, offset, width);
379
380 /* CPUs {ICX,SPR} encode two counters per 4-byte CORRERRCNT register. */
381 if (res_cfg->type <= SPR) {
382 n += scnprintf(buf: msg + n, size: len - n, fmt: "%.4llx %.4llx ",
383 corr & 0xffff, corr >> 16);
384 } else {
385 /* CPUs {GNR} encode one counter per CORRERRCNT register. */
386 if (width == 4)
387 n += scnprintf(buf: msg + n, size: len - n, fmt: "%.8llx ", corr);
388 else
389 n += scnprintf(buf: msg + n, size: len - n, fmt: "%.16llx ", corr);
390 }
391 }
392
393 /* Move back one space. */
394 n--;
395 n += scnprintf(buf: msg + n, size: len - n, fmt: "]");
396 }
397}
398
399static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
400 unsigned int dev, unsigned int fun)
401{
402 struct pci_dev *pdev;
403
404 pdev = pci_get_domain_bus_and_slot(domain: dom, bus, PCI_DEVFN(dev, fun));
405 if (!pdev) {
406 edac_dbg(2, "No device %02x:%02x.%x\n",
407 bus, dev, fun);
408 return NULL;
409 }
410
411 if (unlikely(pci_enable_device(pdev) < 0)) {
412 edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
413 bus, dev, fun);
414 pci_dev_put(dev: pdev);
415 return NULL;
416 }
417
418 return pdev;
419}
420
421/**
422 * i10nm_get_imc_num() - Get the number of present DDR memory controllers.
423 *
424 * @cfg : The pointer to the structure of EDAC resource configurations.
425 *
426 * For Granite Rapids CPUs, the number of present DDR memory controllers read
427 * at runtime overwrites the value statically configured in @cfg->ddr_imc_num.
428 * For other CPUs, the number of present DDR memory controllers is statically
429 * configured in @cfg->ddr_imc_num.
430 *
431 * RETURNS : 0 on success, < 0 on failure.
432 */
433static int i10nm_get_imc_num(struct res_config *cfg)
434{
435 int n, imc_num, chan_num = 0;
436 struct skx_dev *d;
437 u32 reg;
438
439 list_for_each_entry(d, i10nm_edac_list, list) {
440 d->pcu_cr3 = pci_get_dev_wrapper(dom: d->seg, bus: d->bus[res_cfg->pcu_cr3_bdf.bus],
441 dev: res_cfg->pcu_cr3_bdf.dev,
442 fun: res_cfg->pcu_cr3_bdf.fun);
443 if (!d->pcu_cr3)
444 continue;
445
446 if (I10NM_GET_CAPID5_CFG(d, reg))
447 continue;
448
449 n = I10NM_DDR_IMC_CH_CNT(reg);
450
451 if (!chan_num) {
452 chan_num = n;
453 edac_dbg(2, "Get DDR CH number: %d\n", chan_num);
454 } else if (chan_num != n) {
455 i10nm_printk(KERN_NOTICE, "Get DDR CH numbers: %d, %d\n", chan_num, n);
456 }
457 }
458
459 switch (cfg->type) {
460 case GNR:
461 /*
462 * One channel per DDR memory controller for Granite Rapids CPUs.
463 */
464 imc_num = chan_num;
465
466 if (!imc_num) {
467 i10nm_printk(KERN_ERR, "Invalid DDR MC number\n");
468 return -ENODEV;
469 }
470
471 if (cfg->ddr_imc_num != imc_num) {
472 /*
473 * Update the configuration data to reflect the number of
474 * present DDR memory controllers.
475 */
476 cfg->ddr_imc_num = imc_num;
477 edac_dbg(2, "Set DDR MC number: %d", imc_num);
478
479 /* Release and reallocate skx_dev list with the updated number. */
480 skx_remove();
481 if (skx_get_all_bus_mappings(cfg, list: &i10nm_edac_list) <= 0)
482 return -ENODEV;
483 }
484
485 return 0;
486 default:
487 /*
488 * For other CPUs, the number of present DDR memory controllers
489 * is statically pre-configured in cfg->ddr_imc_num.
490 */
491 return 0;
492 }
493}
494
495static bool i10nm_check_2lm(struct res_config *cfg)
496{
497 struct skx_dev *d;
498 u32 reg;
499 int i;
500
501 list_for_each_entry(d, i10nm_edac_list, list) {
502 d->sad_all = pci_get_dev_wrapper(dom: d->seg, bus: d->bus[res_cfg->sad_all_bdf.bus],
503 dev: res_cfg->sad_all_bdf.dev,
504 fun: res_cfg->sad_all_bdf.fun);
505 if (!d->sad_all)
506 continue;
507
508 for (i = 0; i < I10NM_MAX_SAD; i++) {
509 I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg);
510 if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) {
511 edac_dbg(2, "2-level memory configuration.\n");
512 return true;
513 }
514 }
515 }
516
517 return false;
518}
519
520/*
521 * Check whether the error comes from DDRT by ICX/Tremont/SPR model specific error code.
522 * Refer to SDM vol3B 17.11.3/17.13.2 Intel IMC MC error codes for IA32_MCi_STATUS.
523 */
524static bool i10nm_mscod_is_ddrt(u32 mscod)
525{
526 switch (res_cfg->type) {
527 case I10NM:
528 switch (mscod) {
529 case 0x0106: case 0x0107:
530 case 0x0800: case 0x0804:
531 case 0x0806 ... 0x0808:
532 case 0x080a ... 0x080e:
533 case 0x0810: case 0x0811:
534 case 0x0816: case 0x081e:
535 case 0x081f:
536 return true;
537 }
538
539 break;
540 case SPR:
541 switch (mscod) {
542 case 0x0800: case 0x0804:
543 case 0x0806 ... 0x0808:
544 case 0x080a ... 0x080e:
545 case 0x0810: case 0x0811:
546 case 0x0816: case 0x081e:
547 case 0x081f:
548 return true;
549 }
550
551 break;
552 default:
553 return false;
554 }
555
556 return false;
557}
558
559static bool i10nm_mc_decode_available(struct mce *mce)
560{
561#define ICX_IMCx_CHy 0x06666000
562 u8 bank;
563
564 if (!decoding_via_mca || mem_cfg_2lm)
565 return false;
566
567 if ((mce->status & (MCI_STATUS_MISCV | MCI_STATUS_ADDRV))
568 != (MCI_STATUS_MISCV | MCI_STATUS_ADDRV))
569 return false;
570
571 bank = mce->bank;
572
573 switch (res_cfg->type) {
574 case I10NM:
575 /* Check whether the bank is one of {13,14,17,18,21,22,25,26} */
576 if (!(ICX_IMCx_CHy & (1 << bank)))
577 return false;
578 break;
579 case SPR:
580 if (bank < 13 || bank > 20)
581 return false;
582 break;
583 default:
584 return false;
585 }
586
587 /* DDRT errors can't be decoded from MCA bank registers */
588 if (MCI_MISC_ECC_MODE(mce->misc) == MCI_MISC_ECC_DDRT)
589 return false;
590
591 if (i10nm_mscod_is_ddrt(MCI_STATUS_MSCOD(mce->status)))
592 return false;
593
594 return true;
595}
596
597static bool i10nm_mc_decode(struct decoded_addr *res)
598{
599 struct mce *m = res->mce;
600 struct skx_dev *d;
601 u8 bank;
602
603 if (!i10nm_mc_decode_available(mce: m))
604 return false;
605
606 list_for_each_entry(d, i10nm_edac_list, list) {
607 if (d->imc[0].src_id == m->socketid) {
608 res->socket = m->socketid;
609 res->dev = d;
610 break;
611 }
612 }
613
614 switch (res_cfg->type) {
615 case I10NM:
616 bank = m->bank - 13;
617 res->imc = bank / 4;
618 res->channel = bank % 2;
619 res->column = GET_BITFIELD(m->misc, 9, 18) << 2;
620 res->row = GET_BITFIELD(m->misc, 19, 39);
621 res->bank_group = GET_BITFIELD(m->misc, 40, 41);
622 res->bank_address = GET_BITFIELD(m->misc, 42, 43);
623 res->bank_group |= GET_BITFIELD(m->misc, 44, 44) << 2;
624 res->rank = GET_BITFIELD(m->misc, 56, 58);
625 res->dimm = res->rank >> 2;
626 res->rank = res->rank % 4;
627 break;
628 case SPR:
629 bank = m->bank - 13;
630 res->imc = bank / 2;
631 res->channel = bank % 2;
632 res->column = GET_BITFIELD(m->misc, 9, 18) << 2;
633 res->row = GET_BITFIELD(m->misc, 19, 36);
634 res->bank_group = GET_BITFIELD(m->misc, 37, 38);
635 res->bank_address = GET_BITFIELD(m->misc, 39, 40);
636 res->bank_group |= GET_BITFIELD(m->misc, 41, 41) << 2;
637 res->rank = GET_BITFIELD(m->misc, 57, 57);
638 res->dimm = GET_BITFIELD(m->misc, 58, 58);
639 break;
640 default:
641 return false;
642 }
643
644 if (!res->dev) {
645 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
646 m->socketid, res->imc);
647 return false;
648 }
649
650 return true;
651}
652
653/**
654 * get_gnr_mdev() - Get the PCI device of the @logical_idx-th DDR memory controller.
655 *
656 * @d : The pointer to the structure of CPU socket EDAC device.
657 * @logical_idx : The logical index of the present memory controller (0 ~ max present MC# - 1).
658 * @physical_idx : To store the corresponding physical index of @logical_idx.
659 *
660 * RETURNS : The PCI device of the @logical_idx-th DDR memory controller, NULL on failure.
661 */
662static struct pci_dev *get_gnr_mdev(struct skx_dev *d, int logical_idx, int *physical_idx)
663{
664#define GNR_MAX_IMC_PCI_CNT 28
665
666 struct pci_dev *mdev;
667 int i, logical = 0;
668
669 /*
670 * Detect present memory controllers from { PCI device: 8-5, function 7-1 }
671 */
672 for (i = 0; i < GNR_MAX_IMC_PCI_CNT; i++) {
673 mdev = pci_get_dev_wrapper(dom: d->seg,
674 bus: d->bus[res_cfg->ddr_mdev_bdf.bus],
675 dev: res_cfg->ddr_mdev_bdf.dev + i / 7,
676 fun: res_cfg->ddr_mdev_bdf.fun + i % 7);
677
678 if (mdev) {
679 if (logical == logical_idx) {
680 *physical_idx = i;
681 return mdev;
682 }
683
684 pci_dev_put(dev: mdev);
685 logical++;
686 }
687 }
688
689 return NULL;
690}
691
692static u32 get_gnr_imc_mmio_offset(void)
693{
694 if (boot_cpu_data.x86_vfm == INTEL_GRANITERAPIDS_D)
695 return I10NM_GNR_D_IMC_MMIO_OFFSET;
696
697 return I10NM_GNR_IMC_MMIO_OFFSET;
698}
699
700/**
701 * get_ddr_munit() - Get the resource of the i-th DDR memory controller.
702 *
703 * @d : The pointer to the structure of CPU socket EDAC device.
704 * @i : The index of the CPU socket relative DDR memory controller.
705 * @offset : To store the MMIO offset of the i-th DDR memory controller.
706 * @size : To store the MMIO size of the i-th DDR memory controller.
707 *
708 * RETURNS : The PCI device of the i-th DDR memory controller, NULL on failure.
709 */
710static struct pci_dev *get_ddr_munit(struct skx_dev *d, int i, u32 *offset, unsigned long *size)
711{
712 struct pci_dev *mdev;
713 int physical_idx;
714 u32 reg;
715
716 switch (res_cfg->type) {
717 case GNR:
718 if (I10NM_GET_IMC_BAR(d, 0, reg)) {
719 i10nm_printk(KERN_ERR, "Failed to get mc0 bar\n");
720 return NULL;
721 }
722
723 mdev = get_gnr_mdev(d, logical_idx: i, physical_idx: &physical_idx);
724 if (!mdev)
725 return NULL;
726
727 *offset = I10NM_GET_IMC_MMIO_OFFSET(reg) +
728 get_gnr_imc_mmio_offset() +
729 physical_idx * I10NM_GNR_IMC_MMIO_SIZE;
730 *size = I10NM_GNR_IMC_MMIO_SIZE;
731
732 break;
733 default:
734 if (I10NM_GET_IMC_BAR(d, i, reg)) {
735 i10nm_printk(KERN_ERR, "Failed to get mc%d bar\n", i);
736 return NULL;
737 }
738
739 mdev = pci_get_dev_wrapper(dom: d->seg,
740 bus: d->bus[res_cfg->ddr_mdev_bdf.bus],
741 dev: res_cfg->ddr_mdev_bdf.dev + i,
742 fun: res_cfg->ddr_mdev_bdf.fun);
743 if (!mdev)
744 return NULL;
745
746 *offset = I10NM_GET_IMC_MMIO_OFFSET(reg);
747 *size = I10NM_GET_IMC_MMIO_SIZE(reg);
748 }
749
750 return mdev;
751}
752
753/**
754 * i10nm_imc_absent() - Check whether the memory controller @imc is absent
755 *
756 * @imc : The pointer to the structure of memory controller EDAC device.
757 *
758 * RETURNS : true if the memory controller EDAC device is absent, false otherwise.
759 */
760static bool i10nm_imc_absent(struct skx_imc *imc)
761{
762 u32 mcmtr;
763 int i;
764
765 switch (res_cfg->type) {
766 case SPR:
767 for (i = 0; i < res_cfg->ddr_chan_num; i++) {
768 mcmtr = I10NM_GET_MCMTR(imc, i);
769 edac_dbg(1, "ch%d mcmtr reg %x\n", i, mcmtr);
770 if (mcmtr != ~0)
771 return false;
772 }
773
774 /*
775 * Some workstations' absent memory controllers still
776 * appear as PCIe devices, misleading the EDAC driver.
777 * By observing that the MMIO registers of these absent
778 * memory controllers consistently hold the value of ~0.
779 *
780 * We identify a memory controller as absent by checking
781 * if its MMIO register "mcmtr" == ~0 in all its channels.
782 */
783 return true;
784 default:
785 return false;
786 }
787}
788
789static int i10nm_get_ddr_munits(void)
790{
791 struct pci_dev *mdev;
792 void __iomem *mbase;
793 unsigned long size;
794 struct skx_dev *d;
795 int i, lmc, j = 0;
796 u32 reg, off;
797 u64 base;
798
799 list_for_each_entry(d, i10nm_edac_list, list) {
800 d->util_all = pci_get_dev_wrapper(dom: d->seg, bus: d->bus[res_cfg->util_all_bdf.bus],
801 dev: res_cfg->util_all_bdf.dev,
802 fun: res_cfg->util_all_bdf.fun);
803 if (!d->util_all)
804 return -ENODEV;
805
806 d->uracu = pci_get_dev_wrapper(dom: d->seg, bus: d->bus[res_cfg->uracu_bdf.bus],
807 dev: res_cfg->uracu_bdf.dev,
808 fun: res_cfg->uracu_bdf.fun);
809 if (!d->uracu)
810 return -ENODEV;
811
812 if (I10NM_GET_SCK_BAR(d, reg)) {
813 i10nm_printk(KERN_ERR, "Failed to socket bar\n");
814 return -ENODEV;
815 }
816
817 base = I10NM_GET_SCK_MMIO_BASE(reg);
818 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
819 j++, base, reg);
820
821 for (lmc = 0, i = 0; i < res_cfg->ddr_imc_num; i++) {
822 mdev = get_ddr_munit(d, i, offset: &off, size: &size);
823
824 if (i == 0 && !mdev) {
825 i10nm_printk(KERN_ERR, "No IMC found\n");
826 return -ENODEV;
827 }
828 if (!mdev)
829 continue;
830
831 edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
832 i, base + off, size, reg);
833
834 mbase = ioremap(offset: base + off, size);
835 if (!mbase) {
836 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
837 base + off);
838 return -ENODEV;
839 }
840
841 d->imc[lmc].mbase = mbase;
842 if (i10nm_imc_absent(imc: &d->imc[lmc])) {
843 pci_dev_put(dev: mdev);
844 iounmap(addr: mbase);
845 d->imc[lmc].mbase = NULL;
846 edac_dbg(2, "Skip absent mc%d\n", i);
847 continue;
848 } else {
849 d->imc[lmc].mdev = mdev;
850 if (res_cfg->type == SPR)
851 skx_set_mc_mapping(d, pmc: i, lmc);
852 lmc++;
853 }
854 }
855 }
856
857 return 0;
858}
859
860static bool i10nm_check_hbm_imc(struct skx_dev *d)
861{
862 u32 reg;
863
864 if (I10NM_GET_CAPID3_CFG(d, reg)) {
865 i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n");
866 return false;
867 }
868
869 return I10NM_IS_HBM_PRESENT(reg) != 0;
870}
871
872static int i10nm_get_hbm_munits(void)
873{
874 struct pci_dev *mdev;
875 void __iomem *mbase;
876 u32 reg, off, mcmtr;
877 struct skx_dev *d;
878 int i, lmc;
879 u64 base;
880
881 list_for_each_entry(d, i10nm_edac_list, list) {
882 if (!d->pcu_cr3)
883 return -ENODEV;
884
885 if (!i10nm_check_hbm_imc(d)) {
886 i10nm_printk(KERN_DEBUG, "No hbm memory\n");
887 return -ENODEV;
888 }
889
890 if (I10NM_GET_SCK_BAR(d, reg)) {
891 i10nm_printk(KERN_ERR, "Failed to get socket bar\n");
892 return -ENODEV;
893 }
894 base = I10NM_GET_SCK_MMIO_BASE(reg);
895
896 if (I10NM_GET_HBM_IMC_BAR(d, reg)) {
897 i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n");
898 return -ENODEV;
899 }
900 base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg);
901
902 lmc = res_cfg->ddr_imc_num;
903
904 for (i = 0; i < res_cfg->hbm_imc_num; i++) {
905 mdev = pci_get_dev_wrapper(dom: d->seg, bus: d->bus[res_cfg->hbm_mdev_bdf.bus],
906 dev: res_cfg->hbm_mdev_bdf.dev + i / 4,
907 fun: res_cfg->hbm_mdev_bdf.fun + i % 4);
908
909 if (i == 0 && !mdev) {
910 i10nm_printk(KERN_ERR, "No hbm mc found\n");
911 return -ENODEV;
912 }
913 if (!mdev)
914 continue;
915
916 d->imc[lmc].mdev = mdev;
917 off = i * I10NM_HBM_IMC_MMIO_SIZE;
918
919 edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",
920 lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE);
921
922 mbase = ioremap(offset: base + off, I10NM_HBM_IMC_MMIO_SIZE);
923 if (!mbase) {
924 pci_dev_put(dev: d->imc[lmc].mdev);
925 d->imc[lmc].mdev = NULL;
926
927 i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n",
928 base + off);
929 return -ENOMEM;
930 }
931
932 d->imc[lmc].mbase = mbase;
933 d->imc[lmc].hbm_mc = true;
934
935 mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
936 if (!I10NM_IS_HBM_IMC(mcmtr)) {
937 iounmap(addr: d->imc[lmc].mbase);
938 d->imc[lmc].mbase = NULL;
939 d->imc[lmc].hbm_mc = false;
940 pci_dev_put(dev: d->imc[lmc].mdev);
941 d->imc[lmc].mdev = NULL;
942
943 i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n");
944 return -ENODEV;
945 }
946
947 lmc++;
948 }
949 }
950
951 return 0;
952}
953
954static struct res_config i10nm_cfg0 = {
955 .type = I10NM,
956 .decs_did = 0x3452,
957 .busno_cfg_offset = 0xcc,
958 .ddr_imc_num = 4,
959 .ddr_chan_num = 2,
960 .ddr_dimm_num = 2,
961 .ddr_chan_mmio_sz = 0x4000,
962 .sad_all_bdf = {1, 29, 0},
963 .pcu_cr3_bdf = {1, 30, 3},
964 .util_all_bdf = {1, 29, 1},
965 .uracu_bdf = {0, 0, 1},
966 .ddr_mdev_bdf = {0, 12, 0},
967 .hbm_mdev_bdf = {0, 12, 1},
968 .sad_all_offset = 0x108,
969 .reg_rrl_ddr = &icx_reg_rrl_ddr,
970};
971
972static struct res_config i10nm_cfg1 = {
973 .type = I10NM,
974 .decs_did = 0x3452,
975 .busno_cfg_offset = 0xd0,
976 .ddr_imc_num = 4,
977 .ddr_chan_num = 2,
978 .ddr_dimm_num = 2,
979 .ddr_chan_mmio_sz = 0x4000,
980 .sad_all_bdf = {1, 29, 0},
981 .pcu_cr3_bdf = {1, 30, 3},
982 .util_all_bdf = {1, 29, 1},
983 .uracu_bdf = {0, 0, 1},
984 .ddr_mdev_bdf = {0, 12, 0},
985 .hbm_mdev_bdf = {0, 12, 1},
986 .sad_all_offset = 0x108,
987 .reg_rrl_ddr = &icx_reg_rrl_ddr,
988};
989
990static struct res_config spr_cfg = {
991 .type = SPR,
992 .decs_did = 0x3252,
993 .busno_cfg_offset = 0xd0,
994 .ddr_imc_num = 4,
995 .ddr_chan_num = 2,
996 .ddr_dimm_num = 2,
997 .hbm_imc_num = 16,
998 .hbm_chan_num = 2,
999 .hbm_dimm_num = 1,
1000 .ddr_chan_mmio_sz = 0x8000,
1001 .hbm_chan_mmio_sz = 0x4000,
1002 .support_ddr5 = true,
1003 .sad_all_bdf = {1, 10, 0},
1004 .pcu_cr3_bdf = {1, 30, 3},
1005 .util_all_bdf = {1, 29, 1},
1006 .uracu_bdf = {0, 0, 1},
1007 .ddr_mdev_bdf = {0, 12, 0},
1008 .hbm_mdev_bdf = {0, 12, 1},
1009 .sad_all_offset = 0x300,
1010 .reg_rrl_ddr = &spr_reg_rrl_ddr,
1011 .reg_rrl_hbm[0] = &spr_reg_rrl_hbm_pch0,
1012 .reg_rrl_hbm[1] = &spr_reg_rrl_hbm_pch1,
1013};
1014
1015static struct res_config gnr_cfg = {
1016 .type = GNR,
1017 .decs_did = 0x3252,
1018 .busno_cfg_offset = 0xd0,
1019 .ddr_imc_num = 12,
1020 .ddr_chan_num = 1,
1021 .ddr_dimm_num = 2,
1022 .ddr_chan_mmio_sz = 0x4000,
1023 .support_ddr5 = true,
1024 .sad_all_bdf = {0, 13, 0},
1025 .pcu_cr3_bdf = {0, 5, 0},
1026 .util_all_bdf = {0, 13, 1},
1027 .uracu_bdf = {0, 0, 1},
1028 .ddr_mdev_bdf = {0, 5, 1},
1029 .sad_all_offset = 0x300,
1030 .reg_rrl_ddr = &gnr_reg_rrl_ddr,
1031};
1032
1033static const struct x86_cpu_id i10nm_cpuids[] = {
1034 X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MIN, 0x3, &i10nm_cfg0),
1035 X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 0x4, X86_STEP_MAX, &i10nm_cfg1),
1036 X86_MATCH_VFM_STEPS(INTEL_ICELAKE_X, X86_STEP_MIN, 0x3, &i10nm_cfg0),
1037 X86_MATCH_VFM_STEPS(INTEL_ICELAKE_X, 0x4, X86_STEP_MAX, &i10nm_cfg1),
1038 X86_MATCH_VFM( INTEL_ICELAKE_D, &i10nm_cfg1),
1039
1040 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_cfg),
1041 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_cfg),
1042 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_cfg),
1043 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, &gnr_cfg),
1044 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_cfg),
1045 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_cfg),
1046 X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_cfg),
1047 {}
1048};
1049MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
1050
1051static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
1052{
1053 u32 mcmtr;
1054
1055 mcmtr = I10NM_GET_MCMTR(imc, chan);
1056 edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
1057
1058 return !!GET_BITFIELD(mcmtr, 2, 2);
1059}
1060
1061static bool i10nm_channel_disabled(struct skx_imc *imc, int chan)
1062{
1063 u32 mcmtr = I10NM_GET_MCMTR(imc, chan);
1064
1065 edac_dbg(1, "mc%d ch%d mcmtr reg %x\n", imc->mc, chan, mcmtr);
1066
1067 return (mcmtr == ~0 || GET_BITFIELD(mcmtr, 18, 18));
1068}
1069
1070static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
1071 struct res_config *cfg)
1072{
1073 struct skx_pvt *pvt = mci->pvt_info;
1074 struct skx_imc *imc = pvt->imc;
1075 u32 mtr, mcddrtcfg = 0;
1076 struct dimm_info *dimm;
1077 int i, j, ndimms;
1078
1079 for (i = 0; i < imc->num_channels; i++) {
1080 if (!imc->mbase)
1081 continue;
1082
1083 if (i10nm_channel_disabled(imc, chan: i)) {
1084 edac_dbg(1, "mc%d ch%d is disabled.\n", imc->mc, i);
1085 continue;
1086 }
1087
1088 ndimms = 0;
1089
1090 if (res_cfg->type != GNR)
1091 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
1092
1093 for (j = 0; j < imc->num_dimms; j++) {
1094 dimm = edac_get_dimm(mci, layer0: i, layer1: j, layer2: 0);
1095 mtr = I10NM_GET_DIMMMTR(imc, i, j);
1096 edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
1097 mtr, mcddrtcfg, imc->mc, i, j);
1098
1099 if (IS_DIMM_PRESENT(mtr))
1100 ndimms += skx_get_dimm_info(mtr, mcmtr: 0, amap: 0, dimm,
1101 imc, chan: i, dimmno: j, cfg);
1102 else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
1103 ndimms += skx_get_nvdimm_info(dimm, imc, chan: i, dimmno: j,
1104 EDAC_MOD_STR);
1105 }
1106 if (ndimms && !i10nm_check_ecc(imc, chan: i)) {
1107 i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
1108 imc->mc, i);
1109 return -ENODEV;
1110 }
1111 }
1112
1113 return 0;
1114}
1115
1116static struct notifier_block i10nm_mce_dec = {
1117 .notifier_call = skx_mce_check_error,
1118 .priority = MCE_PRIO_EDAC,
1119};
1120
1121static int __init i10nm_init(void)
1122{
1123 u8 mc = 0, src_id = 0;
1124 const struct x86_cpu_id *id;
1125 struct res_config *cfg;
1126 const char *owner;
1127 struct skx_dev *d;
1128 int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
1129 u64 tolm, tohm;
1130 int imc_num;
1131
1132 edac_dbg(2, "\n");
1133
1134 if (ghes_get_devices())
1135 return -EBUSY;
1136
1137 owner = edac_get_owner();
1138 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
1139 return -EBUSY;
1140
1141 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
1142 return -ENODEV;
1143
1144 id = x86_match_cpu(match: i10nm_cpuids);
1145 if (!id)
1146 return -ENODEV;
1147
1148 cfg = (struct res_config *)id->driver_data;
1149 skx_set_res_cfg(cfg);
1150 res_cfg = cfg;
1151
1152 rc = skx_get_hi_lo(did: 0x09a2, off, tolm: &tolm, tohm: &tohm);
1153 if (rc)
1154 return rc;
1155
1156 rc = skx_get_all_bus_mappings(cfg, list: &i10nm_edac_list);
1157 if (rc < 0)
1158 goto fail;
1159 if (rc == 0) {
1160 i10nm_printk(KERN_ERR, "No memory controllers found\n");
1161 return -ENODEV;
1162 }
1163
1164 rc = i10nm_get_imc_num(cfg);
1165 if (rc < 0)
1166 goto fail;
1167
1168 mem_cfg_2lm = i10nm_check_2lm(cfg);
1169 skx_set_mem_cfg(mem_cfg_2lm);
1170
1171 rc = i10nm_get_ddr_munits();
1172
1173 if (i10nm_get_hbm_munits() && rc)
1174 goto fail;
1175
1176 imc_num = res_cfg->ddr_imc_num + res_cfg->hbm_imc_num;
1177
1178 list_for_each_entry(d, i10nm_edac_list, list) {
1179 rc = skx_get_src_id(d, off: 0xf8, id: &src_id);
1180 if (rc < 0)
1181 goto fail;
1182
1183 edac_dbg(2, "src_id = %d\n", src_id);
1184 for (i = 0; i < imc_num; i++) {
1185 if (!d->imc[i].mdev)
1186 continue;
1187
1188 d->imc[i].mc = mc++;
1189 d->imc[i].lmc = i;
1190 d->imc[i].src_id = src_id;
1191 if (d->imc[i].hbm_mc) {
1192 d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
1193 d->imc[i].num_channels = cfg->hbm_chan_num;
1194 d->imc[i].num_dimms = cfg->hbm_dimm_num;
1195 } else {
1196 d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
1197 d->imc[i].num_channels = cfg->ddr_chan_num;
1198 d->imc[i].num_dimms = cfg->ddr_dimm_num;
1199 }
1200
1201 rc = skx_register_mci(imc: &d->imc[i], dev: &d->imc[i].mdev->dev,
1202 dev_name: pci_name(pdev: d->imc[i].mdev),
1203 ctl_name: "Intel_10nm Socket", EDAC_MOD_STR,
1204 get_dimm_config: i10nm_get_dimm_config, cfg);
1205 if (rc < 0)
1206 goto fail;
1207 }
1208 }
1209
1210 rc = skx_adxl_get();
1211 if (rc)
1212 goto fail;
1213
1214 opstate_init();
1215 mce_register_decode_chain(nb: &i10nm_mce_dec);
1216 skx_setup_debug(name: "i10nm_test");
1217
1218 if (retry_rd_err_log && res_cfg->reg_rrl_ddr) {
1219 skx_set_decode(decode: i10nm_mc_decode, show_retry_log: show_retry_rd_err_log);
1220 if (retry_rd_err_log == 2)
1221 enable_retry_rd_err_log(enable: true);
1222 } else {
1223 skx_set_decode(decode: i10nm_mc_decode, NULL);
1224 }
1225
1226 i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
1227
1228 return 0;
1229fail:
1230 skx_remove();
1231 return rc;
1232}
1233
1234static void __exit i10nm_exit(void)
1235{
1236 edac_dbg(2, "\n");
1237
1238 if (retry_rd_err_log && res_cfg->reg_rrl_ddr) {
1239 skx_set_decode(NULL, NULL);
1240 if (retry_rd_err_log == 2)
1241 enable_retry_rd_err_log(enable: false);
1242 }
1243
1244 skx_teardown_debug();
1245 mce_unregister_decode_chain(nb: &i10nm_mce_dec);
1246 skx_adxl_put();
1247 skx_remove();
1248}
1249
1250module_init(i10nm_init);
1251module_exit(i10nm_exit);
1252
1253static int set_decoding_via_mca(const char *buf, const struct kernel_param *kp)
1254{
1255 unsigned long val;
1256 int ret;
1257
1258 ret = kstrtoul(s: buf, base: 0, res: &val);
1259
1260 if (ret || val > 1)
1261 return -EINVAL;
1262
1263 if (val && mem_cfg_2lm) {
1264 i10nm_printk(KERN_NOTICE, "Decoding errors via MCA banks for 2LM isn't supported yet\n");
1265 return -EIO;
1266 }
1267
1268 ret = param_set_int(val: buf, kp);
1269
1270 return ret;
1271}
1272
1273static const struct kernel_param_ops decoding_via_mca_param_ops = {
1274 .set = set_decoding_via_mca,
1275 .get = param_get_int,
1276};
1277
1278module_param_cb(decoding_via_mca, &decoding_via_mca_param_ops, &decoding_via_mca, 0644);
1279MODULE_PARM_DESC(decoding_via_mca, "decoding_via_mca: 0=off(default), 1=enable");
1280
1281module_param(retry_rd_err_log, int, 0444);
1282MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)");
1283
1284MODULE_LICENSE("GPL v2");
1285MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");
1286

source code of linux/drivers/edac/i10nm_base.c