1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (C) 2020 Daniel Palmer<daniel@thingy.jp> */ |
3 | |
4 | #include <linux/bitops.h> |
5 | #include <linux/kernel.h> |
6 | #include <linux/types.h> |
7 | #include <linux/io.h> |
8 | #include <linux/of.h> |
9 | #include <linux/of_irq.h> |
10 | #include <linux/gpio/driver.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | |
14 | #include <dt-bindings/gpio/msc313-gpio.h> |
15 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
16 | |
17 | #define DRIVER_NAME "gpio-msc313" |
18 | |
19 | #define MSC313_GPIO_IN BIT(0) |
20 | #define MSC313_GPIO_OUT BIT(4) |
21 | #define MSC313_GPIO_OEN BIT(5) |
22 | |
23 | /* |
24 | * These bits need to be saved to correctly restore the |
25 | * gpio state when resuming from suspend to memory. |
26 | */ |
27 | #define MSC313_GPIO_BITSTOSAVE (MSC313_GPIO_OUT | MSC313_GPIO_OEN) |
28 | |
29 | /* pad names for fuart, same for all SoCs so far */ |
30 | #define MSC313_PINNAME_FUART_RX "fuart_rx" |
31 | #define MSC313_PINNAME_FUART_TX "fuart_tx" |
32 | #define MSC313_PINNAME_FUART_CTS "fuart_cts" |
33 | #define MSC313_PINNAME_FUART_RTS "fuart_rts" |
34 | |
35 | /* pad names for sr, mercury5 is different */ |
36 | #define MSC313_PINNAME_SR_IO2 "sr_io2" |
37 | #define MSC313_PINNAME_SR_IO3 "sr_io3" |
38 | #define MSC313_PINNAME_SR_IO4 "sr_io4" |
39 | #define MSC313_PINNAME_SR_IO5 "sr_io5" |
40 | #define MSC313_PINNAME_SR_IO6 "sr_io6" |
41 | #define MSC313_PINNAME_SR_IO7 "sr_io7" |
42 | #define MSC313_PINNAME_SR_IO8 "sr_io8" |
43 | #define MSC313_PINNAME_SR_IO9 "sr_io9" |
44 | #define MSC313_PINNAME_SR_IO10 "sr_io10" |
45 | #define MSC313_PINNAME_SR_IO11 "sr_io11" |
46 | #define MSC313_PINNAME_SR_IO12 "sr_io12" |
47 | #define MSC313_PINNAME_SR_IO13 "sr_io13" |
48 | #define MSC313_PINNAME_SR_IO14 "sr_io14" |
49 | #define MSC313_PINNAME_SR_IO15 "sr_io15" |
50 | #define MSC313_PINNAME_SR_IO16 "sr_io16" |
51 | #define MSC313_PINNAME_SR_IO17 "sr_io17" |
52 | |
53 | /* pad names for sd, same for all SoCs so far */ |
54 | #define MSC313_PINNAME_SD_CLK "sd_clk" |
55 | #define MSC313_PINNAME_SD_CMD "sd_cmd" |
56 | #define MSC313_PINNAME_SD_D0 "sd_d0" |
57 | #define MSC313_PINNAME_SD_D1 "sd_d1" |
58 | #define MSC313_PINNAME_SD_D2 "sd_d2" |
59 | #define MSC313_PINNAME_SD_D3 "sd_d3" |
60 | |
61 | /* pad names for i2c1, same for all SoCs so for */ |
62 | #define MSC313_PINNAME_I2C1_SCL "i2c1_scl" |
63 | #define MSC313_PINNAME_I2C1_SCA "i2c1_sda" |
64 | |
65 | /* pad names for spi0, same for all SoCs so far */ |
66 | #define MSC313_PINNAME_SPI0_CZ "spi0_cz" |
67 | #define MSC313_PINNAME_SPI0_CK "spi0_ck" |
68 | #define MSC313_PINNAME_SPI0_DI "spi0_di" |
69 | #define MSC313_PINNAME_SPI0_DO "spi0_do" |
70 | |
71 | #define FUART_NAMES \ |
72 | MSC313_PINNAME_FUART_RX, \ |
73 | MSC313_PINNAME_FUART_TX, \ |
74 | MSC313_PINNAME_FUART_CTS, \ |
75 | MSC313_PINNAME_FUART_RTS |
76 | |
77 | #define OFF_FUART_RX 0x50 |
78 | #define OFF_FUART_TX 0x54 |
79 | #define OFF_FUART_CTS 0x58 |
80 | #define OFF_FUART_RTS 0x5c |
81 | |
82 | #define FUART_OFFSETS \ |
83 | OFF_FUART_RX, \ |
84 | OFF_FUART_TX, \ |
85 | OFF_FUART_CTS, \ |
86 | OFF_FUART_RTS |
87 | |
88 | #define SR_NAMES \ |
89 | MSC313_PINNAME_SR_IO2, \ |
90 | MSC313_PINNAME_SR_IO3, \ |
91 | MSC313_PINNAME_SR_IO4, \ |
92 | MSC313_PINNAME_SR_IO5, \ |
93 | MSC313_PINNAME_SR_IO6, \ |
94 | MSC313_PINNAME_SR_IO7, \ |
95 | MSC313_PINNAME_SR_IO8, \ |
96 | MSC313_PINNAME_SR_IO9, \ |
97 | MSC313_PINNAME_SR_IO10, \ |
98 | MSC313_PINNAME_SR_IO11, \ |
99 | MSC313_PINNAME_SR_IO12, \ |
100 | MSC313_PINNAME_SR_IO13, \ |
101 | MSC313_PINNAME_SR_IO14, \ |
102 | MSC313_PINNAME_SR_IO15, \ |
103 | MSC313_PINNAME_SR_IO16, \ |
104 | MSC313_PINNAME_SR_IO17 |
105 | |
106 | #define OFF_SR_IO2 0x88 |
107 | #define OFF_SR_IO3 0x8c |
108 | #define OFF_SR_IO4 0x90 |
109 | #define OFF_SR_IO5 0x94 |
110 | #define OFF_SR_IO6 0x98 |
111 | #define OFF_SR_IO7 0x9c |
112 | #define OFF_SR_IO8 0xa0 |
113 | #define OFF_SR_IO9 0xa4 |
114 | #define OFF_SR_IO10 0xa8 |
115 | #define OFF_SR_IO11 0xac |
116 | #define OFF_SR_IO12 0xb0 |
117 | #define OFF_SR_IO13 0xb4 |
118 | #define OFF_SR_IO14 0xb8 |
119 | #define OFF_SR_IO15 0xbc |
120 | #define OFF_SR_IO16 0xc0 |
121 | #define OFF_SR_IO17 0xc4 |
122 | |
123 | #define SR_OFFSETS \ |
124 | OFF_SR_IO2, \ |
125 | OFF_SR_IO3, \ |
126 | OFF_SR_IO4, \ |
127 | OFF_SR_IO5, \ |
128 | OFF_SR_IO6, \ |
129 | OFF_SR_IO7, \ |
130 | OFF_SR_IO8, \ |
131 | OFF_SR_IO9, \ |
132 | OFF_SR_IO10, \ |
133 | OFF_SR_IO11, \ |
134 | OFF_SR_IO12, \ |
135 | OFF_SR_IO13, \ |
136 | OFF_SR_IO14, \ |
137 | OFF_SR_IO15, \ |
138 | OFF_SR_IO16, \ |
139 | OFF_SR_IO17 |
140 | |
141 | #define SD_NAMES \ |
142 | MSC313_PINNAME_SD_CLK, \ |
143 | MSC313_PINNAME_SD_CMD, \ |
144 | MSC313_PINNAME_SD_D0, \ |
145 | MSC313_PINNAME_SD_D1, \ |
146 | MSC313_PINNAME_SD_D2, \ |
147 | MSC313_PINNAME_SD_D3 |
148 | |
149 | #define OFF_SD_CLK 0x140 |
150 | #define OFF_SD_CMD 0x144 |
151 | #define OFF_SD_D0 0x148 |
152 | #define OFF_SD_D1 0x14c |
153 | #define OFF_SD_D2 0x150 |
154 | #define OFF_SD_D3 0x154 |
155 | |
156 | #define SD_OFFSETS \ |
157 | OFF_SD_CLK, \ |
158 | OFF_SD_CMD, \ |
159 | OFF_SD_D0, \ |
160 | OFF_SD_D1, \ |
161 | OFF_SD_D2, \ |
162 | OFF_SD_D3 |
163 | |
164 | #define I2C1_NAMES \ |
165 | MSC313_PINNAME_I2C1_SCL, \ |
166 | MSC313_PINNAME_I2C1_SCA |
167 | |
168 | #define OFF_I2C1_SCL 0x188 |
169 | #define OFF_I2C1_SCA 0x18c |
170 | |
171 | #define I2C1_OFFSETS \ |
172 | OFF_I2C1_SCL, \ |
173 | OFF_I2C1_SCA |
174 | |
175 | #define SPI0_NAMES \ |
176 | MSC313_PINNAME_SPI0_CZ, \ |
177 | MSC313_PINNAME_SPI0_CK, \ |
178 | MSC313_PINNAME_SPI0_DI, \ |
179 | MSC313_PINNAME_SPI0_DO |
180 | |
181 | #define OFF_SPI0_CZ 0x1c0 |
182 | #define OFF_SPI0_CK 0x1c4 |
183 | #define OFF_SPI0_DI 0x1c8 |
184 | #define OFF_SPI0_DO 0x1cc |
185 | |
186 | #define SPI0_OFFSETS \ |
187 | OFF_SPI0_CZ, \ |
188 | OFF_SPI0_CK, \ |
189 | OFF_SPI0_DI, \ |
190 | OFF_SPI0_DO |
191 | |
192 | struct msc313_gpio_data { |
193 | const char * const *names; |
194 | const unsigned int *offsets; |
195 | const unsigned int num; |
196 | }; |
197 | |
198 | #define MSC313_GPIO_CHIPDATA(_chip) \ |
199 | static const struct msc313_gpio_data _chip##_data = { \ |
200 | .names = _chip##_names, \ |
201 | .offsets = _chip##_offsets, \ |
202 | .num = ARRAY_SIZE(_chip##_offsets), \ |
203 | } |
204 | |
205 | #ifdef CONFIG_MACH_INFINITY |
206 | static const char * const msc313_names[] = { |
207 | FUART_NAMES, |
208 | SR_NAMES, |
209 | SD_NAMES, |
210 | I2C1_NAMES, |
211 | SPI0_NAMES, |
212 | }; |
213 | |
214 | static const unsigned int msc313_offsets[] = { |
215 | FUART_OFFSETS, |
216 | SR_OFFSETS, |
217 | SD_OFFSETS, |
218 | I2C1_OFFSETS, |
219 | SPI0_OFFSETS, |
220 | }; |
221 | |
222 | MSC313_GPIO_CHIPDATA(msc313); |
223 | |
224 | /* |
225 | * Unlike the msc313(e) the ssd20xd have a bunch of pins |
226 | * that are actually called gpio probably because they |
227 | * have no dedicated function. |
228 | */ |
229 | #define SSD20XD_PINNAME_GPIO0 "gpio0" |
230 | #define SSD20XD_PINNAME_GPIO1 "gpio1" |
231 | #define SSD20XD_PINNAME_GPIO2 "gpio2" |
232 | #define SSD20XD_PINNAME_GPIO3 "gpio3" |
233 | #define SSD20XD_PINNAME_GPIO4 "gpio4" |
234 | #define SSD20XD_PINNAME_GPIO5 "gpio5" |
235 | #define SSD20XD_PINNAME_GPIO6 "gpio6" |
236 | #define SSD20XD_PINNAME_GPIO7 "gpio7" |
237 | #define SSD20XD_PINNAME_GPIO10 "gpio10" |
238 | #define SSD20XD_PINNAME_GPIO11 "gpio11" |
239 | #define SSD20XD_PINNAME_GPIO12 "gpio12" |
240 | #define SSD20XD_PINNAME_GPIO13 "gpio13" |
241 | #define SSD20XD_PINNAME_GPIO14 "gpio14" |
242 | #define SSD20XD_PINNAME_GPIO85 "gpio85" |
243 | #define SSD20XD_PINNAME_GPIO86 "gpio86" |
244 | #define SSD20XD_PINNAME_GPIO90 "gpio90" |
245 | |
246 | #define SSD20XD_GPIO_NAMES SSD20XD_PINNAME_GPIO0, \ |
247 | SSD20XD_PINNAME_GPIO1, \ |
248 | SSD20XD_PINNAME_GPIO2, \ |
249 | SSD20XD_PINNAME_GPIO3, \ |
250 | SSD20XD_PINNAME_GPIO4, \ |
251 | SSD20XD_PINNAME_GPIO5, \ |
252 | SSD20XD_PINNAME_GPIO6, \ |
253 | SSD20XD_PINNAME_GPIO7, \ |
254 | SSD20XD_PINNAME_GPIO10, \ |
255 | SSD20XD_PINNAME_GPIO11, \ |
256 | SSD20XD_PINNAME_GPIO12, \ |
257 | SSD20XD_PINNAME_GPIO13, \ |
258 | SSD20XD_PINNAME_GPIO14, \ |
259 | SSD20XD_PINNAME_GPIO85, \ |
260 | SSD20XD_PINNAME_GPIO86, \ |
261 | SSD20XD_PINNAME_GPIO90 |
262 | |
263 | #define SSD20XD_GPIO_OFF_GPIO0 0x0 |
264 | #define SSD20XD_GPIO_OFF_GPIO1 0x4 |
265 | #define SSD20XD_GPIO_OFF_GPIO2 0x8 |
266 | #define SSD20XD_GPIO_OFF_GPIO3 0xc |
267 | #define SSD20XD_GPIO_OFF_GPIO4 0x10 |
268 | #define SSD20XD_GPIO_OFF_GPIO5 0x14 |
269 | #define SSD20XD_GPIO_OFF_GPIO6 0x18 |
270 | #define SSD20XD_GPIO_OFF_GPIO7 0x1c |
271 | #define SSD20XD_GPIO_OFF_GPIO10 0x28 |
272 | #define SSD20XD_GPIO_OFF_GPIO11 0x2c |
273 | #define SSD20XD_GPIO_OFF_GPIO12 0x30 |
274 | #define SSD20XD_GPIO_OFF_GPIO13 0x34 |
275 | #define SSD20XD_GPIO_OFF_GPIO14 0x38 |
276 | #define SSD20XD_GPIO_OFF_GPIO85 0x100 |
277 | #define SSD20XD_GPIO_OFF_GPIO86 0x104 |
278 | #define SSD20XD_GPIO_OFF_GPIO90 0x114 |
279 | |
280 | #define SSD20XD_GPIO_OFFSETS SSD20XD_GPIO_OFF_GPIO0, \ |
281 | SSD20XD_GPIO_OFF_GPIO1, \ |
282 | SSD20XD_GPIO_OFF_GPIO2, \ |
283 | SSD20XD_GPIO_OFF_GPIO3, \ |
284 | SSD20XD_GPIO_OFF_GPIO4, \ |
285 | SSD20XD_GPIO_OFF_GPIO5, \ |
286 | SSD20XD_GPIO_OFF_GPIO6, \ |
287 | SSD20XD_GPIO_OFF_GPIO7, \ |
288 | SSD20XD_GPIO_OFF_GPIO10, \ |
289 | SSD20XD_GPIO_OFF_GPIO11, \ |
290 | SSD20XD_GPIO_OFF_GPIO12, \ |
291 | SSD20XD_GPIO_OFF_GPIO13, \ |
292 | SSD20XD_GPIO_OFF_GPIO14, \ |
293 | SSD20XD_GPIO_OFF_GPIO85, \ |
294 | SSD20XD_GPIO_OFF_GPIO86, \ |
295 | SSD20XD_GPIO_OFF_GPIO90 |
296 | |
297 | /* "ttl" pins lcd interface pins */ |
298 | #define SSD20XD_PINNAME_TTL0 "ttl0" |
299 | #define SSD20XD_PINNAME_TTL1 "ttl1" |
300 | #define SSD20XD_PINNAME_TTL2 "ttl2" |
301 | #define SSD20XD_PINNAME_TTL3 "ttl3" |
302 | #define SSD20XD_PINNAME_TTL4 "ttl4" |
303 | #define SSD20XD_PINNAME_TTL5 "ttl5" |
304 | #define SSD20XD_PINNAME_TTL6 "ttl6" |
305 | #define SSD20XD_PINNAME_TTL7 "ttl7" |
306 | #define SSD20XD_PINNAME_TTL8 "ttl8" |
307 | #define SSD20XD_PINNAME_TTL9 "ttl9" |
308 | #define SSD20XD_PINNAME_TTL10 "ttl10" |
309 | #define SSD20XD_PINNAME_TTL11 "ttl11" |
310 | #define SSD20XD_PINNAME_TTL12 "ttl12" |
311 | #define SSD20XD_PINNAME_TTL13 "ttl13" |
312 | #define SSD20XD_PINNAME_TTL14 "ttl14" |
313 | #define SSD20XD_PINNAME_TTL15 "ttl15" |
314 | #define SSD20XD_PINNAME_TTL16 "ttl16" |
315 | #define SSD20XD_PINNAME_TTL17 "ttl17" |
316 | #define SSD20XD_PINNAME_TTL18 "ttl18" |
317 | #define SSD20XD_PINNAME_TTL19 "ttl19" |
318 | #define SSD20XD_PINNAME_TTL20 "ttl20" |
319 | #define SSD20XD_PINNAME_TTL21 "ttl21" |
320 | #define SSD20XD_PINNAME_TTL22 "ttl22" |
321 | #define SSD20XD_PINNAME_TTL23 "ttl23" |
322 | #define SSD20XD_PINNAME_TTL24 "ttl24" |
323 | #define SSD20XD_PINNAME_TTL25 "ttl25" |
324 | #define SSD20XD_PINNAME_TTL26 "ttl26" |
325 | #define SSD20XD_PINNAME_TTL27 "ttl27" |
326 | |
327 | #define SSD20XD_TTL_PINNAMES SSD20XD_PINNAME_TTL0, \ |
328 | SSD20XD_PINNAME_TTL1, \ |
329 | SSD20XD_PINNAME_TTL2, \ |
330 | SSD20XD_PINNAME_TTL3, \ |
331 | SSD20XD_PINNAME_TTL4, \ |
332 | SSD20XD_PINNAME_TTL5, \ |
333 | SSD20XD_PINNAME_TTL6, \ |
334 | SSD20XD_PINNAME_TTL7, \ |
335 | SSD20XD_PINNAME_TTL8, \ |
336 | SSD20XD_PINNAME_TTL9, \ |
337 | SSD20XD_PINNAME_TTL10, \ |
338 | SSD20XD_PINNAME_TTL11, \ |
339 | SSD20XD_PINNAME_TTL12, \ |
340 | SSD20XD_PINNAME_TTL13, \ |
341 | SSD20XD_PINNAME_TTL14, \ |
342 | SSD20XD_PINNAME_TTL15, \ |
343 | SSD20XD_PINNAME_TTL16, \ |
344 | SSD20XD_PINNAME_TTL17, \ |
345 | SSD20XD_PINNAME_TTL18, \ |
346 | SSD20XD_PINNAME_TTL19, \ |
347 | SSD20XD_PINNAME_TTL20, \ |
348 | SSD20XD_PINNAME_TTL21, \ |
349 | SSD20XD_PINNAME_TTL22, \ |
350 | SSD20XD_PINNAME_TTL23, \ |
351 | SSD20XD_PINNAME_TTL24, \ |
352 | SSD20XD_PINNAME_TTL25, \ |
353 | SSD20XD_PINNAME_TTL26, \ |
354 | SSD20XD_PINNAME_TTL27 |
355 | |
356 | #define SSD20XD_TTL_OFFSET_TTL0 0x80 |
357 | #define SSD20XD_TTL_OFFSET_TTL1 0x84 |
358 | #define SSD20XD_TTL_OFFSET_TTL2 0x88 |
359 | #define SSD20XD_TTL_OFFSET_TTL3 0x8c |
360 | #define SSD20XD_TTL_OFFSET_TTL4 0x90 |
361 | #define SSD20XD_TTL_OFFSET_TTL5 0x94 |
362 | #define SSD20XD_TTL_OFFSET_TTL6 0x98 |
363 | #define SSD20XD_TTL_OFFSET_TTL7 0x9c |
364 | #define SSD20XD_TTL_OFFSET_TTL8 0xa0 |
365 | #define SSD20XD_TTL_OFFSET_TTL9 0xa4 |
366 | #define SSD20XD_TTL_OFFSET_TTL10 0xa8 |
367 | #define SSD20XD_TTL_OFFSET_TTL11 0xac |
368 | #define SSD20XD_TTL_OFFSET_TTL12 0xb0 |
369 | #define SSD20XD_TTL_OFFSET_TTL13 0xb4 |
370 | #define SSD20XD_TTL_OFFSET_TTL14 0xb8 |
371 | #define SSD20XD_TTL_OFFSET_TTL15 0xbc |
372 | #define SSD20XD_TTL_OFFSET_TTL16 0xc0 |
373 | #define SSD20XD_TTL_OFFSET_TTL17 0xc4 |
374 | #define SSD20XD_TTL_OFFSET_TTL18 0xc8 |
375 | #define SSD20XD_TTL_OFFSET_TTL19 0xcc |
376 | #define SSD20XD_TTL_OFFSET_TTL20 0xd0 |
377 | #define SSD20XD_TTL_OFFSET_TTL21 0xd4 |
378 | #define SSD20XD_TTL_OFFSET_TTL22 0xd8 |
379 | #define SSD20XD_TTL_OFFSET_TTL23 0xdc |
380 | #define SSD20XD_TTL_OFFSET_TTL24 0xe0 |
381 | #define SSD20XD_TTL_OFFSET_TTL25 0xe4 |
382 | #define SSD20XD_TTL_OFFSET_TTL26 0xe8 |
383 | #define SSD20XD_TTL_OFFSET_TTL27 0xec |
384 | |
385 | #define SSD20XD_TTL_OFFSETS SSD20XD_TTL_OFFSET_TTL0, \ |
386 | SSD20XD_TTL_OFFSET_TTL1, \ |
387 | SSD20XD_TTL_OFFSET_TTL2, \ |
388 | SSD20XD_TTL_OFFSET_TTL3, \ |
389 | SSD20XD_TTL_OFFSET_TTL4, \ |
390 | SSD20XD_TTL_OFFSET_TTL5, \ |
391 | SSD20XD_TTL_OFFSET_TTL6, \ |
392 | SSD20XD_TTL_OFFSET_TTL7, \ |
393 | SSD20XD_TTL_OFFSET_TTL8, \ |
394 | SSD20XD_TTL_OFFSET_TTL9, \ |
395 | SSD20XD_TTL_OFFSET_TTL10, \ |
396 | SSD20XD_TTL_OFFSET_TTL11, \ |
397 | SSD20XD_TTL_OFFSET_TTL12, \ |
398 | SSD20XD_TTL_OFFSET_TTL13, \ |
399 | SSD20XD_TTL_OFFSET_TTL14, \ |
400 | SSD20XD_TTL_OFFSET_TTL15, \ |
401 | SSD20XD_TTL_OFFSET_TTL16, \ |
402 | SSD20XD_TTL_OFFSET_TTL17, \ |
403 | SSD20XD_TTL_OFFSET_TTL18, \ |
404 | SSD20XD_TTL_OFFSET_TTL19, \ |
405 | SSD20XD_TTL_OFFSET_TTL20, \ |
406 | SSD20XD_TTL_OFFSET_TTL21, \ |
407 | SSD20XD_TTL_OFFSET_TTL22, \ |
408 | SSD20XD_TTL_OFFSET_TTL23, \ |
409 | SSD20XD_TTL_OFFSET_TTL24, \ |
410 | SSD20XD_TTL_OFFSET_TTL25, \ |
411 | SSD20XD_TTL_OFFSET_TTL26, \ |
412 | SSD20XD_TTL_OFFSET_TTL27 |
413 | |
414 | /* On the ssd20xd the two normal uarts have dedicated pins */ |
415 | #define SSD20XD_PINNAME_UART0_RX "uart0_rx" |
416 | #define SSD20XD_PINNAME_UART0_TX "uart0_tx" |
417 | |
418 | #define SSD20XD_UART0_NAMES \ |
419 | SSD20XD_PINNAME_UART0_RX, \ |
420 | SSD20XD_PINNAME_UART0_TX |
421 | |
422 | #define SSD20XD_PINNAME_UART1_RX "uart1_rx" |
423 | #define SSD20XD_PINNAME_UART1_TX "uart1_tx" |
424 | |
425 | #define SSD20XD_UART1_NAMES \ |
426 | SSD20XD_PINNAME_UART1_RX, \ |
427 | SSD20XD_PINNAME_UART1_TX |
428 | |
429 | #define SSD20XD_OFF_UART0_RX 0x60 |
430 | #define SSD20XD_OFF_UART0_TX 0x64 |
431 | |
432 | #define SSD20XD_UART0_OFFSETS \ |
433 | SSD20XD_OFF_UART0_RX, \ |
434 | SSD20XD_OFF_UART0_TX |
435 | |
436 | #define SSD20XD_OFF_UART1_RX 0x68 |
437 | #define SSD20XD_OFF_UART1_TX 0x6c |
438 | |
439 | #define SSD20XD_UART1_OFFSETS \ |
440 | SSD20XD_OFF_UART1_RX, \ |
441 | SSD20XD_OFF_UART1_TX |
442 | |
443 | /* |
444 | * ssd20x has the same pin names but different ordering |
445 | * of the registers that control the gpio. |
446 | */ |
447 | #define SSD20XD_OFF_SD_D0 0x140 |
448 | #define SSD20XD_OFF_SD_D1 0x144 |
449 | #define SSD20XD_OFF_SD_D2 0x148 |
450 | #define SSD20XD_OFF_SD_D3 0x14c |
451 | #define SSD20XD_OFF_SD_CMD 0x150 |
452 | #define SSD20XD_OFF_SD_CLK 0x154 |
453 | |
454 | #define SSD20XD_SD_OFFSETS SSD20XD_OFF_SD_CLK, \ |
455 | SSD20XD_OFF_SD_CMD, \ |
456 | SSD20XD_OFF_SD_D0, \ |
457 | SSD20XD_OFF_SD_D1, \ |
458 | SSD20XD_OFF_SD_D2, \ |
459 | SSD20XD_OFF_SD_D3 |
460 | |
461 | static const char * const ssd20xd_names[] = { |
462 | FUART_NAMES, |
463 | SD_NAMES, |
464 | SSD20XD_UART0_NAMES, |
465 | SSD20XD_UART1_NAMES, |
466 | SSD20XD_TTL_PINNAMES, |
467 | SSD20XD_GPIO_NAMES, |
468 | }; |
469 | |
470 | static const unsigned int ssd20xd_offsets[] = { |
471 | FUART_OFFSETS, |
472 | SSD20XD_SD_OFFSETS, |
473 | SSD20XD_UART0_OFFSETS, |
474 | SSD20XD_UART1_OFFSETS, |
475 | SSD20XD_TTL_OFFSETS, |
476 | SSD20XD_GPIO_OFFSETS, |
477 | }; |
478 | |
479 | MSC313_GPIO_CHIPDATA(ssd20xd); |
480 | #endif |
481 | |
482 | struct msc313_gpio { |
483 | void __iomem *base; |
484 | const struct msc313_gpio_data *gpio_data; |
485 | u8 *saved; |
486 | }; |
487 | |
488 | static void msc313_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) |
489 | { |
490 | struct msc313_gpio *gpio = gpiochip_get_data(gc: chip); |
491 | u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); |
492 | |
493 | if (value) |
494 | gpioreg |= MSC313_GPIO_OUT; |
495 | else |
496 | gpioreg &= ~MSC313_GPIO_OUT; |
497 | |
498 | writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); |
499 | } |
500 | |
501 | static int msc313_gpio_get(struct gpio_chip *chip, unsigned int offset) |
502 | { |
503 | struct msc313_gpio *gpio = gpiochip_get_data(gc: chip); |
504 | |
505 | return readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]) & MSC313_GPIO_IN; |
506 | } |
507 | |
508 | static int msc313_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
509 | { |
510 | struct msc313_gpio *gpio = gpiochip_get_data(gc: chip); |
511 | u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); |
512 | |
513 | gpioreg |= MSC313_GPIO_OEN; |
514 | writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); |
515 | |
516 | return 0; |
517 | } |
518 | |
519 | static int msc313_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) |
520 | { |
521 | struct msc313_gpio *gpio = gpiochip_get_data(gc: chip); |
522 | u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); |
523 | |
524 | gpioreg &= ~MSC313_GPIO_OEN; |
525 | if (value) |
526 | gpioreg |= MSC313_GPIO_OUT; |
527 | else |
528 | gpioreg &= ~MSC313_GPIO_OUT; |
529 | writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); |
530 | |
531 | return 0; |
532 | } |
533 | |
534 | static void msc313_gpio_irq_mask(struct irq_data *d) |
535 | { |
536 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
537 | |
538 | irq_chip_mask_parent(data: d); |
539 | gpiochip_disable_irq(gc, offset: d->hwirq); |
540 | } |
541 | |
542 | static void msc313_gpio_irq_unmask(struct irq_data *d) |
543 | { |
544 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
545 | |
546 | gpiochip_enable_irq(gc, offset: d->hwirq); |
547 | irq_chip_unmask_parent(data: d); |
548 | } |
549 | |
550 | /* |
551 | * The interrupt handling happens in the parent interrupt controller, |
552 | * we don't do anything here. |
553 | */ |
554 | static const struct irq_chip msc313_gpio_irqchip = { |
555 | .name = "GPIO" , |
556 | .irq_eoi = irq_chip_eoi_parent, |
557 | .irq_mask = msc313_gpio_irq_mask, |
558 | .irq_unmask = msc313_gpio_irq_unmask, |
559 | .irq_set_type = irq_chip_set_type_parent, |
560 | .irq_set_affinity = irq_chip_set_affinity_parent, |
561 | .flags = IRQCHIP_IMMUTABLE, |
562 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
563 | }; |
564 | |
565 | /* |
566 | * The parent interrupt controller needs the GIC interrupt type set to GIC_SPI |
567 | * so we need to provide the fwspec. Essentially gpiochip_populate_parent_fwspec_twocell |
568 | * that puts GIC_SPI into the first cell. |
569 | */ |
570 | static int msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc, |
571 | union gpio_irq_fwspec *gfwspec, |
572 | unsigned int parent_hwirq, |
573 | unsigned int parent_type) |
574 | { |
575 | struct irq_fwspec *fwspec = &gfwspec->fwspec; |
576 | |
577 | fwspec->fwnode = gc->irq.parent_domain->fwnode; |
578 | fwspec->param_count = 3; |
579 | fwspec->param[0] = GIC_SPI; |
580 | fwspec->param[1] = parent_hwirq; |
581 | fwspec->param[2] = parent_type; |
582 | |
583 | return 0; |
584 | } |
585 | |
586 | static int msc313e_gpio_child_to_parent_hwirq(struct gpio_chip *chip, |
587 | unsigned int child, |
588 | unsigned int child_type, |
589 | unsigned int *parent, |
590 | unsigned int *parent_type) |
591 | { |
592 | struct msc313_gpio *priv = gpiochip_get_data(gc: chip); |
593 | unsigned int offset = priv->gpio_data->offsets[child]; |
594 | |
595 | /* |
596 | * only the spi0 pins have interrupts on the parent |
597 | * on all of the known chips and so far they are all |
598 | * mapped to the same place |
599 | */ |
600 | if (offset >= OFF_SPI0_CZ && offset <= OFF_SPI0_DO) { |
601 | *parent_type = child_type; |
602 | *parent = ((offset - OFF_SPI0_CZ) >> 2) + 28; |
603 | return 0; |
604 | } |
605 | |
606 | return -EINVAL; |
607 | } |
608 | |
609 | static int msc313_gpio_probe(struct platform_device *pdev) |
610 | { |
611 | const struct msc313_gpio_data *match_data; |
612 | struct msc313_gpio *gpio; |
613 | struct gpio_chip *gpiochip; |
614 | struct gpio_irq_chip *gpioirqchip; |
615 | struct irq_domain *parent_domain; |
616 | struct device_node *parent_node; |
617 | struct device *dev = &pdev->dev; |
618 | |
619 | match_data = of_device_get_match_data(dev); |
620 | if (!match_data) |
621 | return -EINVAL; |
622 | |
623 | parent_node = of_irq_find_parent(child: dev->of_node); |
624 | if (!parent_node) |
625 | return -ENODEV; |
626 | |
627 | parent_domain = irq_find_host(node: parent_node); |
628 | if (!parent_domain) |
629 | return -ENODEV; |
630 | |
631 | gpio = devm_kzalloc(dev, size: sizeof(*gpio), GFP_KERNEL); |
632 | if (!gpio) |
633 | return -ENOMEM; |
634 | |
635 | gpio->gpio_data = match_data; |
636 | |
637 | gpio->saved = devm_kcalloc(dev, n: gpio->gpio_data->num, size: sizeof(*gpio->saved), GFP_KERNEL); |
638 | if (!gpio->saved) |
639 | return -ENOMEM; |
640 | |
641 | gpio->base = devm_platform_ioremap_resource(pdev, index: 0); |
642 | if (IS_ERR(ptr: gpio->base)) |
643 | return PTR_ERR(ptr: gpio->base); |
644 | |
645 | platform_set_drvdata(pdev, data: gpio); |
646 | |
647 | gpiochip = devm_kzalloc(dev, size: sizeof(*gpiochip), GFP_KERNEL); |
648 | if (!gpiochip) |
649 | return -ENOMEM; |
650 | |
651 | gpiochip->label = DRIVER_NAME; |
652 | gpiochip->parent = dev; |
653 | gpiochip->request = gpiochip_generic_request; |
654 | gpiochip->free = gpiochip_generic_free; |
655 | gpiochip->direction_input = msc313_gpio_direction_input; |
656 | gpiochip->direction_output = msc313_gpio_direction_output; |
657 | gpiochip->get = msc313_gpio_get; |
658 | gpiochip->set = msc313_gpio_set; |
659 | gpiochip->base = -1; |
660 | gpiochip->ngpio = gpio->gpio_data->num; |
661 | gpiochip->names = gpio->gpio_data->names; |
662 | |
663 | gpioirqchip = &gpiochip->irq; |
664 | gpio_irq_chip_set_chip(girq: gpioirqchip, chip: &msc313_gpio_irqchip); |
665 | gpioirqchip->fwnode = of_node_to_fwnode(node: dev->of_node); |
666 | gpioirqchip->parent_domain = parent_domain; |
667 | gpioirqchip->child_to_parent_hwirq = msc313e_gpio_child_to_parent_hwirq; |
668 | gpioirqchip->populate_parent_alloc_arg = msc313_gpio_populate_parent_fwspec; |
669 | gpioirqchip->handler = handle_bad_irq; |
670 | gpioirqchip->default_type = IRQ_TYPE_NONE; |
671 | |
672 | return devm_gpiochip_add_data(dev, gpiochip, gpio); |
673 | } |
674 | |
675 | static const struct of_device_id msc313_gpio_of_match[] = { |
676 | #ifdef CONFIG_MACH_INFINITY |
677 | { |
678 | .compatible = "mstar,msc313-gpio" , |
679 | .data = &msc313_data, |
680 | }, |
681 | { |
682 | .compatible = "sstar,ssd20xd-gpio" , |
683 | .data = &ssd20xd_data, |
684 | }, |
685 | #endif |
686 | { } |
687 | }; |
688 | |
689 | /* |
690 | * The GPIO controller loses the state of the registers when the |
691 | * SoC goes into suspend to memory mode so we need to save some |
692 | * of the register bits before suspending and put it back when resuming |
693 | */ |
694 | static int __maybe_unused msc313_gpio_suspend(struct device *dev) |
695 | { |
696 | struct msc313_gpio *gpio = dev_get_drvdata(dev); |
697 | int i; |
698 | |
699 | for (i = 0; i < gpio->gpio_data->num; i++) |
700 | gpio->saved[i] = readb_relaxed(gpio->base + gpio->gpio_data->offsets[i]) & MSC313_GPIO_BITSTOSAVE; |
701 | |
702 | return 0; |
703 | } |
704 | |
705 | static int __maybe_unused msc313_gpio_resume(struct device *dev) |
706 | { |
707 | struct msc313_gpio *gpio = dev_get_drvdata(dev); |
708 | int i; |
709 | |
710 | for (i = 0; i < gpio->gpio_data->num; i++) |
711 | writeb_relaxed(gpio->saved[i], gpio->base + gpio->gpio_data->offsets[i]); |
712 | |
713 | return 0; |
714 | } |
715 | |
716 | static SIMPLE_DEV_PM_OPS(msc313_gpio_ops, msc313_gpio_suspend, msc313_gpio_resume); |
717 | |
718 | static struct platform_driver msc313_gpio_driver = { |
719 | .driver = { |
720 | .name = DRIVER_NAME, |
721 | .of_match_table = msc313_gpio_of_match, |
722 | .pm = &msc313_gpio_ops, |
723 | }, |
724 | .probe = msc313_gpio_probe, |
725 | }; |
726 | builtin_platform_driver(msc313_gpio_driver); |
727 | |