1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Freescale vf610 GPIO support through PORT and GPIO |
4 | * |
5 | * Copyright (c) 2014 Toradex AG. |
6 | * |
7 | * Author: Stefan Agner <stefan@agner.ch>. |
8 | */ |
9 | #include <linux/bitops.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/err.h> |
12 | #include <linux/gpio/driver.h> |
13 | #include <linux/init.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/io.h> |
16 | #include <linux/ioport.h> |
17 | #include <linux/irq.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/of.h> |
20 | #include <linux/of_irq.h> |
21 | #include <linux/pinctrl/consumer.h> |
22 | |
23 | #define VF610_GPIO_PER_PORT 32 |
24 | |
25 | struct fsl_gpio_soc_data { |
26 | /* SoCs has a Port Data Direction Register (PDDR) */ |
27 | bool have_paddr; |
28 | bool have_dual_base; |
29 | }; |
30 | |
31 | struct vf610_gpio_port { |
32 | struct gpio_chip gc; |
33 | void __iomem *base; |
34 | void __iomem *gpio_base; |
35 | const struct fsl_gpio_soc_data *sdata; |
36 | u8 irqc[VF610_GPIO_PER_PORT]; |
37 | struct clk *clk_port; |
38 | struct clk *clk_gpio; |
39 | int irq; |
40 | }; |
41 | |
42 | #define GPIO_PDOR 0x00 |
43 | #define GPIO_PSOR 0x04 |
44 | #define GPIO_PCOR 0x08 |
45 | #define GPIO_PTOR 0x0c |
46 | #define GPIO_PDIR 0x10 |
47 | #define GPIO_PDDR 0x14 |
48 | |
49 | #define PORT_PCR(n) ((n) * 0x4) |
50 | #define PORT_PCR_IRQC_OFFSET 16 |
51 | |
52 | #define PORT_ISFR 0xa0 |
53 | #define PORT_DFER 0xc0 |
54 | #define PORT_DFCR 0xc4 |
55 | #define PORT_DFWR 0xc8 |
56 | |
57 | #define PORT_INT_OFF 0x0 |
58 | #define PORT_INT_LOGIC_ZERO 0x8 |
59 | #define PORT_INT_RISING_EDGE 0x9 |
60 | #define PORT_INT_FALLING_EDGE 0xa |
61 | #define PORT_INT_EITHER_EDGE 0xb |
62 | #define PORT_INT_LOGIC_ONE 0xc |
63 | |
64 | #define IMX8ULP_GPIO_BASE_OFF 0x40 |
65 | #define IMX8ULP_BASE_OFF 0x80 |
66 | |
67 | static const struct fsl_gpio_soc_data vf610_data = { |
68 | .have_dual_base = true, |
69 | }; |
70 | |
71 | static const struct fsl_gpio_soc_data imx_data = { |
72 | .have_paddr = true, |
73 | .have_dual_base = true, |
74 | }; |
75 | |
76 | static const struct fsl_gpio_soc_data imx8ulp_data = { |
77 | .have_paddr = true, |
78 | }; |
79 | |
80 | static const struct of_device_id vf610_gpio_dt_ids[] = { |
81 | { .compatible = "fsl,vf610-gpio" , .data = &vf610_data }, |
82 | { .compatible = "fsl,imx7ulp-gpio" , .data = &imx_data, }, |
83 | { .compatible = "fsl,imx8ulp-gpio" , .data = &imx8ulp_data, }, |
84 | { /* sentinel */ } |
85 | }; |
86 | |
87 | static inline void vf610_gpio_writel(u32 val, void __iomem *reg) |
88 | { |
89 | writel_relaxed(val, reg); |
90 | } |
91 | |
92 | static inline u32 vf610_gpio_readl(void __iomem *reg) |
93 | { |
94 | return readl_relaxed(reg); |
95 | } |
96 | |
97 | static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
98 | { |
99 | struct vf610_gpio_port *port = gpiochip_get_data(gc); |
100 | unsigned long mask = BIT(gpio); |
101 | unsigned long offset = GPIO_PDIR; |
102 | |
103 | if (port->sdata->have_paddr) { |
104 | mask &= vf610_gpio_readl(reg: port->gpio_base + GPIO_PDDR); |
105 | if (mask) |
106 | offset = GPIO_PDOR; |
107 | } |
108 | |
109 | return !!(vf610_gpio_readl(reg: port->gpio_base + offset) & BIT(gpio)); |
110 | } |
111 | |
112 | static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
113 | { |
114 | struct vf610_gpio_port *port = gpiochip_get_data(gc); |
115 | unsigned long mask = BIT(gpio); |
116 | unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR; |
117 | |
118 | vf610_gpio_writel(val: mask, reg: port->gpio_base + offset); |
119 | } |
120 | |
121 | static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
122 | { |
123 | struct vf610_gpio_port *port = gpiochip_get_data(gc: chip); |
124 | unsigned long mask = BIT(gpio); |
125 | u32 val; |
126 | |
127 | if (port->sdata->have_paddr) { |
128 | val = vf610_gpio_readl(reg: port->gpio_base + GPIO_PDDR); |
129 | val &= ~mask; |
130 | vf610_gpio_writel(val, reg: port->gpio_base + GPIO_PDDR); |
131 | } |
132 | |
133 | return pinctrl_gpio_direction_input(gc: chip, offset: gpio); |
134 | } |
135 | |
136 | static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
137 | int value) |
138 | { |
139 | struct vf610_gpio_port *port = gpiochip_get_data(gc: chip); |
140 | unsigned long mask = BIT(gpio); |
141 | u32 val; |
142 | |
143 | vf610_gpio_set(gc: chip, gpio, val: value); |
144 | |
145 | if (port->sdata->have_paddr) { |
146 | val = vf610_gpio_readl(reg: port->gpio_base + GPIO_PDDR); |
147 | val |= mask; |
148 | vf610_gpio_writel(val, reg: port->gpio_base + GPIO_PDDR); |
149 | } |
150 | |
151 | return pinctrl_gpio_direction_output(gc: chip, offset: gpio); |
152 | } |
153 | |
154 | static void vf610_gpio_irq_handler(struct irq_desc *desc) |
155 | { |
156 | struct vf610_gpio_port *port = |
157 | gpiochip_get_data(gc: irq_desc_get_handler_data(desc)); |
158 | struct irq_chip *chip = irq_desc_get_chip(desc); |
159 | int pin; |
160 | unsigned long irq_isfr; |
161 | |
162 | chained_irq_enter(chip, desc); |
163 | |
164 | irq_isfr = vf610_gpio_readl(reg: port->base + PORT_ISFR); |
165 | |
166 | for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { |
167 | vf610_gpio_writel(BIT(pin), reg: port->base + PORT_ISFR); |
168 | |
169 | generic_handle_domain_irq(domain: port->gc.irq.domain, hwirq: pin); |
170 | } |
171 | |
172 | chained_irq_exit(chip, desc); |
173 | } |
174 | |
175 | static void vf610_gpio_irq_ack(struct irq_data *d) |
176 | { |
177 | struct vf610_gpio_port *port = |
178 | gpiochip_get_data(gc: irq_data_get_irq_chip_data(d)); |
179 | int gpio = d->hwirq; |
180 | |
181 | vf610_gpio_writel(BIT(gpio), reg: port->base + PORT_ISFR); |
182 | } |
183 | |
184 | static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) |
185 | { |
186 | struct vf610_gpio_port *port = |
187 | gpiochip_get_data(gc: irq_data_get_irq_chip_data(d)); |
188 | u8 irqc; |
189 | |
190 | switch (type) { |
191 | case IRQ_TYPE_EDGE_RISING: |
192 | irqc = PORT_INT_RISING_EDGE; |
193 | break; |
194 | case IRQ_TYPE_EDGE_FALLING: |
195 | irqc = PORT_INT_FALLING_EDGE; |
196 | break; |
197 | case IRQ_TYPE_EDGE_BOTH: |
198 | irqc = PORT_INT_EITHER_EDGE; |
199 | break; |
200 | case IRQ_TYPE_LEVEL_LOW: |
201 | irqc = PORT_INT_LOGIC_ZERO; |
202 | break; |
203 | case IRQ_TYPE_LEVEL_HIGH: |
204 | irqc = PORT_INT_LOGIC_ONE; |
205 | break; |
206 | default: |
207 | return -EINVAL; |
208 | } |
209 | |
210 | port->irqc[d->hwirq] = irqc; |
211 | |
212 | if (type & IRQ_TYPE_LEVEL_MASK) |
213 | irq_set_handler_locked(data: d, handler: handle_level_irq); |
214 | else |
215 | irq_set_handler_locked(data: d, handler: handle_edge_irq); |
216 | |
217 | return 0; |
218 | } |
219 | |
220 | static void vf610_gpio_irq_mask(struct irq_data *d) |
221 | { |
222 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
223 | struct vf610_gpio_port *port = gpiochip_get_data(gc); |
224 | irq_hw_number_t gpio_num = irqd_to_hwirq(d); |
225 | void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); |
226 | |
227 | vf610_gpio_writel(val: 0, reg: pcr_base); |
228 | gpiochip_disable_irq(gc, offset: gpio_num); |
229 | } |
230 | |
231 | static void vf610_gpio_irq_unmask(struct irq_data *d) |
232 | { |
233 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
234 | struct vf610_gpio_port *port = gpiochip_get_data(gc); |
235 | irq_hw_number_t gpio_num = irqd_to_hwirq(d); |
236 | void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); |
237 | |
238 | gpiochip_enable_irq(gc, offset: gpio_num); |
239 | vf610_gpio_writel(val: port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET, |
240 | reg: pcr_base); |
241 | } |
242 | |
243 | static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) |
244 | { |
245 | struct vf610_gpio_port *port = |
246 | gpiochip_get_data(gc: irq_data_get_irq_chip_data(d)); |
247 | |
248 | if (enable) |
249 | enable_irq_wake(irq: port->irq); |
250 | else |
251 | disable_irq_wake(irq: port->irq); |
252 | |
253 | return 0; |
254 | } |
255 | |
256 | static const struct irq_chip vf610_irqchip = { |
257 | .name = "gpio-vf610" , |
258 | .irq_ack = vf610_gpio_irq_ack, |
259 | .irq_mask = vf610_gpio_irq_mask, |
260 | .irq_unmask = vf610_gpio_irq_unmask, |
261 | .irq_set_type = vf610_gpio_irq_set_type, |
262 | .irq_set_wake = vf610_gpio_irq_set_wake, |
263 | .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND |
264 | | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, |
265 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
266 | }; |
267 | |
268 | static void vf610_gpio_disable_clk(void *data) |
269 | { |
270 | clk_disable_unprepare(clk: data); |
271 | } |
272 | |
273 | static int vf610_gpio_probe(struct platform_device *pdev) |
274 | { |
275 | struct device *dev = &pdev->dev; |
276 | struct vf610_gpio_port *port; |
277 | struct gpio_chip *gc; |
278 | struct gpio_irq_chip *girq; |
279 | int i; |
280 | int ret; |
281 | bool dual_base; |
282 | |
283 | port = devm_kzalloc(dev, size: sizeof(*port), GFP_KERNEL); |
284 | if (!port) |
285 | return -ENOMEM; |
286 | |
287 | port->sdata = of_device_get_match_data(dev); |
288 | |
289 | dual_base = port->sdata->have_dual_base; |
290 | |
291 | /* |
292 | * Handle legacy compatible combinations which used two reg values |
293 | * for the i.MX8ULP and i.MX93. |
294 | */ |
295 | if (device_is_compatible(dev, compat: "fsl,imx7ulp-gpio" ) && |
296 | (device_is_compatible(dev, compat: "fsl,imx93-gpio" ) || |
297 | (device_is_compatible(dev, compat: "fsl,imx8ulp-gpio" )))) |
298 | dual_base = true; |
299 | |
300 | if (dual_base) { |
301 | port->base = devm_platform_ioremap_resource(pdev, index: 0); |
302 | if (IS_ERR(ptr: port->base)) |
303 | return PTR_ERR(ptr: port->base); |
304 | |
305 | port->gpio_base = devm_platform_ioremap_resource(pdev, index: 1); |
306 | if (IS_ERR(ptr: port->gpio_base)) |
307 | return PTR_ERR(ptr: port->gpio_base); |
308 | } else { |
309 | port->base = devm_platform_ioremap_resource(pdev, index: 0); |
310 | if (IS_ERR(ptr: port->base)) |
311 | return PTR_ERR(ptr: port->base); |
312 | |
313 | port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF; |
314 | port->base = port->base + IMX8ULP_BASE_OFF; |
315 | } |
316 | |
317 | port->irq = platform_get_irq(pdev, 0); |
318 | if (port->irq < 0) |
319 | return port->irq; |
320 | |
321 | port->clk_port = devm_clk_get(dev, id: "port" ); |
322 | ret = PTR_ERR_OR_ZERO(ptr: port->clk_port); |
323 | if (!ret) { |
324 | ret = clk_prepare_enable(clk: port->clk_port); |
325 | if (ret) |
326 | return ret; |
327 | ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, |
328 | port->clk_port); |
329 | if (ret) |
330 | return ret; |
331 | } else if (ret == -EPROBE_DEFER) { |
332 | /* |
333 | * Percolate deferrals, for anything else, |
334 | * just live without the clocking. |
335 | */ |
336 | return ret; |
337 | } |
338 | |
339 | port->clk_gpio = devm_clk_get(dev, id: "gpio" ); |
340 | ret = PTR_ERR_OR_ZERO(ptr: port->clk_gpio); |
341 | if (!ret) { |
342 | ret = clk_prepare_enable(clk: port->clk_gpio); |
343 | if (ret) |
344 | return ret; |
345 | ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, |
346 | port->clk_gpio); |
347 | if (ret) |
348 | return ret; |
349 | } else if (ret == -EPROBE_DEFER) { |
350 | return ret; |
351 | } |
352 | |
353 | gc = &port->gc; |
354 | gc->parent = dev; |
355 | gc->label = dev_name(dev); |
356 | gc->ngpio = VF610_GPIO_PER_PORT; |
357 | gc->base = -1; |
358 | |
359 | gc->request = gpiochip_generic_request; |
360 | gc->free = gpiochip_generic_free; |
361 | gc->direction_input = vf610_gpio_direction_input; |
362 | gc->get = vf610_gpio_get; |
363 | gc->direction_output = vf610_gpio_direction_output; |
364 | gc->set = vf610_gpio_set; |
365 | |
366 | /* Mask all GPIO interrupts */ |
367 | for (i = 0; i < gc->ngpio; i++) |
368 | vf610_gpio_writel(val: 0, reg: port->base + PORT_PCR(i)); |
369 | |
370 | /* Clear the interrupt status register for all GPIO's */ |
371 | vf610_gpio_writel(val: ~0, reg: port->base + PORT_ISFR); |
372 | |
373 | girq = &gc->irq; |
374 | gpio_irq_chip_set_chip(girq, chip: &vf610_irqchip); |
375 | girq->parent_handler = vf610_gpio_irq_handler; |
376 | girq->num_parents = 1; |
377 | girq->parents = devm_kcalloc(dev: &pdev->dev, n: 1, |
378 | size: sizeof(*girq->parents), |
379 | GFP_KERNEL); |
380 | if (!girq->parents) |
381 | return -ENOMEM; |
382 | girq->parents[0] = port->irq; |
383 | girq->default_type = IRQ_TYPE_NONE; |
384 | girq->handler = handle_edge_irq; |
385 | |
386 | return devm_gpiochip_add_data(dev, gc, port); |
387 | } |
388 | |
389 | static struct platform_driver vf610_gpio_driver = { |
390 | .driver = { |
391 | .name = "gpio-vf610" , |
392 | .of_match_table = vf610_gpio_dt_ids, |
393 | }, |
394 | .probe = vf610_gpio_probe, |
395 | }; |
396 | |
397 | builtin_platform_driver(vf610_gpio_driver); |
398 | |