1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/pci.h> |
25 | |
26 | #include "amdgpu.h" |
27 | #include "amdgpu_ih.h" |
28 | #include "vid.h" |
29 | |
30 | #include "oss/oss_3_0_d.h" |
31 | #include "oss/oss_3_0_sh_mask.h" |
32 | |
33 | #include "bif/bif_5_1_d.h" |
34 | #include "bif/bif_5_1_sh_mask.h" |
35 | |
36 | /* |
37 | * Interrupts |
38 | * Starting with r6xx, interrupts are handled via a ring buffer. |
39 | * Ring buffers are areas of GPU accessible memory that the GPU |
40 | * writes interrupt vectors into and the host reads vectors out of. |
41 | * There is a rptr (read pointer) that determines where the |
42 | * host is currently reading, and a wptr (write pointer) |
43 | * which determines where the GPU has written. When the |
44 | * pointers are equal, the ring is idle. When the GPU |
45 | * writes vectors to the ring buffer, it increments the |
46 | * wptr. When there is an interrupt, the host then starts |
47 | * fetching commands and processing them until the pointers are |
48 | * equal again at which point it updates the rptr. |
49 | */ |
50 | |
51 | static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev); |
52 | |
53 | /** |
54 | * tonga_ih_enable_interrupts - Enable the interrupt ring buffer |
55 | * |
56 | * @adev: amdgpu_device pointer |
57 | * |
58 | * Enable the interrupt ring buffer (VI). |
59 | */ |
60 | static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) |
61 | { |
62 | u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); |
63 | |
64 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); |
65 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); |
66 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
67 | adev->irq.ih.enabled = true; |
68 | } |
69 | |
70 | /** |
71 | * tonga_ih_disable_interrupts - Disable the interrupt ring buffer |
72 | * |
73 | * @adev: amdgpu_device pointer |
74 | * |
75 | * Disable the interrupt ring buffer (VI). |
76 | */ |
77 | static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) |
78 | { |
79 | u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); |
80 | |
81 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); |
82 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); |
83 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
84 | /* set rptr, wptr to 0 */ |
85 | WREG32(mmIH_RB_RPTR, 0); |
86 | WREG32(mmIH_RB_WPTR, 0); |
87 | adev->irq.ih.enabled = false; |
88 | adev->irq.ih.rptr = 0; |
89 | } |
90 | |
91 | /** |
92 | * tonga_ih_irq_init - init and enable the interrupt ring |
93 | * |
94 | * @adev: amdgpu_device pointer |
95 | * |
96 | * Allocate a ring buffer for the interrupt controller, |
97 | * enable the RLC, disable interrupts, enable the IH |
98 | * ring buffer and enable it (VI). |
99 | * Called at device load and reume. |
100 | * Returns 0 for success, errors for failure. |
101 | */ |
102 | static int tonga_ih_irq_init(struct amdgpu_device *adev) |
103 | { |
104 | u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; |
105 | struct amdgpu_ih_ring *ih = &adev->irq.ih; |
106 | int rb_bufsz; |
107 | |
108 | /* disable irqs */ |
109 | tonga_ih_disable_interrupts(adev); |
110 | |
111 | /* setup interrupt control */ |
112 | WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); |
113 | interrupt_cntl = RREG32(mmINTERRUPT_CNTL); |
114 | /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi |
115 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN |
116 | */ |
117 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); |
118 | /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ |
119 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); |
120 | WREG32(mmINTERRUPT_CNTL, interrupt_cntl); |
121 | |
122 | /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ |
123 | WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); |
124 | |
125 | rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); |
126 | ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
127 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); |
128 | /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ |
129 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); |
130 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); |
131 | |
132 | if (adev->irq.msi_enabled) |
133 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); |
134 | |
135 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
136 | |
137 | /* set the writeback address whether it's enabled or not */ |
138 | WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); |
139 | WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); |
140 | |
141 | /* set rptr, wptr to 0 */ |
142 | WREG32(mmIH_RB_RPTR, 0); |
143 | WREG32(mmIH_RB_WPTR, 0); |
144 | |
145 | ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); |
146 | if (adev->irq.ih.use_doorbell) { |
147 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, |
148 | OFFSET, adev->irq.ih.doorbell_index); |
149 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, |
150 | ENABLE, 1); |
151 | } else { |
152 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, |
153 | ENABLE, 0); |
154 | } |
155 | WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); |
156 | |
157 | pci_set_master(dev: adev->pdev); |
158 | |
159 | /* enable interrupts */ |
160 | tonga_ih_enable_interrupts(adev); |
161 | |
162 | return 0; |
163 | } |
164 | |
165 | /** |
166 | * tonga_ih_irq_disable - disable interrupts |
167 | * |
168 | * @adev: amdgpu_device pointer |
169 | * |
170 | * Disable interrupts on the hw (VI). |
171 | */ |
172 | static void tonga_ih_irq_disable(struct amdgpu_device *adev) |
173 | { |
174 | tonga_ih_disable_interrupts(adev); |
175 | |
176 | /* Wait and acknowledge irq */ |
177 | mdelay(1); |
178 | } |
179 | |
180 | /** |
181 | * tonga_ih_get_wptr - get the IH ring buffer wptr |
182 | * |
183 | * @adev: amdgpu_device pointer |
184 | * @ih: IH ring buffer to fetch wptr |
185 | * |
186 | * Get the IH ring buffer wptr from either the register |
187 | * or the writeback memory buffer (VI). Also check for |
188 | * ring buffer overflow and deal with it. |
189 | * Used by cz_irq_process(VI). |
190 | * Returns the value of the wptr. |
191 | */ |
192 | static u32 tonga_ih_get_wptr(struct amdgpu_device *adev, |
193 | struct amdgpu_ih_ring *ih) |
194 | { |
195 | u32 wptr, tmp; |
196 | |
197 | wptr = le32_to_cpu(*ih->wptr_cpu); |
198 | |
199 | if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) |
200 | goto out; |
201 | |
202 | /* Double check that the overflow wasn't already cleared. */ |
203 | wptr = RREG32(mmIH_RB_WPTR); |
204 | |
205 | if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) |
206 | goto out; |
207 | |
208 | wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); |
209 | |
210 | /* When a ring buffer overflow happen start parsing interrupt |
211 | * from the last not overwritten vector (wptr + 16). Hopefully |
212 | * this should allow us to catchup. |
213 | */ |
214 | |
215 | dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n" , |
216 | wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); |
217 | ih->rptr = (wptr + 16) & ih->ptr_mask; |
218 | tmp = RREG32(mmIH_RB_CNTL); |
219 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
220 | WREG32(mmIH_RB_CNTL, tmp); |
221 | |
222 | /* Unset the CLEAR_OVERFLOW bit immediately so new overflows |
223 | * can be detected. |
224 | */ |
225 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); |
226 | WREG32(mmIH_RB_CNTL, tmp); |
227 | |
228 | out: |
229 | return (wptr & ih->ptr_mask); |
230 | } |
231 | |
232 | /** |
233 | * tonga_ih_decode_iv - decode an interrupt vector |
234 | * |
235 | * @adev: amdgpu_device pointer |
236 | * @ih: IH ring buffer to decode |
237 | * @entry: IV entry to place decoded information into |
238 | * |
239 | * Decodes the interrupt vector at the current rptr |
240 | * position and also advance the position. |
241 | */ |
242 | static void tonga_ih_decode_iv(struct amdgpu_device *adev, |
243 | struct amdgpu_ih_ring *ih, |
244 | struct amdgpu_iv_entry *entry) |
245 | { |
246 | /* wptr/rptr are in bytes! */ |
247 | u32 ring_index = ih->rptr >> 2; |
248 | uint32_t dw[4]; |
249 | |
250 | dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); |
251 | dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); |
252 | dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); |
253 | dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); |
254 | |
255 | entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
256 | entry->src_id = dw[0] & 0xff; |
257 | entry->src_data[0] = dw[1] & 0xfffffff; |
258 | entry->ring_id = dw[2] & 0xff; |
259 | entry->vmid = (dw[2] >> 8) & 0xff; |
260 | entry->pasid = (dw[2] >> 16) & 0xffff; |
261 | |
262 | /* wptr/rptr are in bytes! */ |
263 | ih->rptr += 16; |
264 | } |
265 | |
266 | /** |
267 | * tonga_ih_set_rptr - set the IH ring buffer rptr |
268 | * |
269 | * @adev: amdgpu_device pointer |
270 | * @ih: IH ring buffer to set rptr |
271 | * |
272 | * Set the IH ring buffer rptr. |
273 | */ |
274 | static void tonga_ih_set_rptr(struct amdgpu_device *adev, |
275 | struct amdgpu_ih_ring *ih) |
276 | { |
277 | if (ih->use_doorbell) { |
278 | /* XXX check if swapping is necessary on BE */ |
279 | *ih->rptr_cpu = ih->rptr; |
280 | WDOORBELL32(ih->doorbell_index, ih->rptr); |
281 | } else { |
282 | WREG32(mmIH_RB_RPTR, ih->rptr); |
283 | } |
284 | } |
285 | |
286 | static int tonga_ih_early_init(void *handle) |
287 | { |
288 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
289 | int ret; |
290 | |
291 | ret = amdgpu_irq_add_domain(adev); |
292 | if (ret) |
293 | return ret; |
294 | |
295 | tonga_ih_set_interrupt_funcs(adev); |
296 | |
297 | return 0; |
298 | } |
299 | |
300 | static int tonga_ih_sw_init(void *handle) |
301 | { |
302 | int r; |
303 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
304 | |
305 | r = amdgpu_ih_ring_init(adev, ih: &adev->irq.ih, ring_size: 64 * 1024, use_bus_addr: true); |
306 | if (r) |
307 | return r; |
308 | |
309 | adev->irq.ih.use_doorbell = true; |
310 | adev->irq.ih.doorbell_index = adev->doorbell_index.ih; |
311 | |
312 | r = amdgpu_irq_init(adev); |
313 | |
314 | return r; |
315 | } |
316 | |
317 | static int tonga_ih_sw_fini(void *handle) |
318 | { |
319 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
320 | |
321 | amdgpu_irq_fini_sw(adev); |
322 | amdgpu_irq_remove_domain(adev); |
323 | |
324 | return 0; |
325 | } |
326 | |
327 | static int tonga_ih_hw_init(void *handle) |
328 | { |
329 | int r; |
330 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
331 | |
332 | r = tonga_ih_irq_init(adev); |
333 | if (r) |
334 | return r; |
335 | |
336 | return 0; |
337 | } |
338 | |
339 | static int tonga_ih_hw_fini(void *handle) |
340 | { |
341 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
342 | |
343 | tonga_ih_irq_disable(adev); |
344 | |
345 | return 0; |
346 | } |
347 | |
348 | static int tonga_ih_suspend(void *handle) |
349 | { |
350 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
351 | |
352 | return tonga_ih_hw_fini(handle: adev); |
353 | } |
354 | |
355 | static int tonga_ih_resume(void *handle) |
356 | { |
357 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
358 | |
359 | return tonga_ih_hw_init(handle: adev); |
360 | } |
361 | |
362 | static bool tonga_ih_is_idle(void *handle) |
363 | { |
364 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
365 | u32 tmp = RREG32(mmSRBM_STATUS); |
366 | |
367 | if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) |
368 | return false; |
369 | |
370 | return true; |
371 | } |
372 | |
373 | static int tonga_ih_wait_for_idle(void *handle) |
374 | { |
375 | unsigned i; |
376 | u32 tmp; |
377 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
378 | |
379 | for (i = 0; i < adev->usec_timeout; i++) { |
380 | /* read MC_STATUS */ |
381 | tmp = RREG32(mmSRBM_STATUS); |
382 | if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) |
383 | return 0; |
384 | udelay(1); |
385 | } |
386 | return -ETIMEDOUT; |
387 | } |
388 | |
389 | static bool tonga_ih_check_soft_reset(void *handle) |
390 | { |
391 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
392 | u32 srbm_soft_reset = 0; |
393 | u32 tmp = RREG32(mmSRBM_STATUS); |
394 | |
395 | if (tmp & SRBM_STATUS__IH_BUSY_MASK) |
396 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, |
397 | SOFT_RESET_IH, 1); |
398 | |
399 | if (srbm_soft_reset) { |
400 | adev->irq.srbm_soft_reset = srbm_soft_reset; |
401 | return true; |
402 | } else { |
403 | adev->irq.srbm_soft_reset = 0; |
404 | return false; |
405 | } |
406 | } |
407 | |
408 | static int tonga_ih_pre_soft_reset(void *handle) |
409 | { |
410 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
411 | |
412 | if (!adev->irq.srbm_soft_reset) |
413 | return 0; |
414 | |
415 | return tonga_ih_hw_fini(handle: adev); |
416 | } |
417 | |
418 | static int tonga_ih_post_soft_reset(void *handle) |
419 | { |
420 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
421 | |
422 | if (!adev->irq.srbm_soft_reset) |
423 | return 0; |
424 | |
425 | return tonga_ih_hw_init(handle: adev); |
426 | } |
427 | |
428 | static int tonga_ih_soft_reset(void *handle) |
429 | { |
430 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
431 | u32 srbm_soft_reset; |
432 | |
433 | if (!adev->irq.srbm_soft_reset) |
434 | return 0; |
435 | srbm_soft_reset = adev->irq.srbm_soft_reset; |
436 | |
437 | if (srbm_soft_reset) { |
438 | u32 tmp; |
439 | |
440 | tmp = RREG32(mmSRBM_SOFT_RESET); |
441 | tmp |= srbm_soft_reset; |
442 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n" , tmp); |
443 | WREG32(mmSRBM_SOFT_RESET, tmp); |
444 | tmp = RREG32(mmSRBM_SOFT_RESET); |
445 | |
446 | udelay(50); |
447 | |
448 | tmp &= ~srbm_soft_reset; |
449 | WREG32(mmSRBM_SOFT_RESET, tmp); |
450 | tmp = RREG32(mmSRBM_SOFT_RESET); |
451 | |
452 | /* Wait a little for things to settle down */ |
453 | udelay(50); |
454 | } |
455 | |
456 | return 0; |
457 | } |
458 | |
459 | static int tonga_ih_set_clockgating_state(void *handle, |
460 | enum amd_clockgating_state state) |
461 | { |
462 | return 0; |
463 | } |
464 | |
465 | static int tonga_ih_set_powergating_state(void *handle, |
466 | enum amd_powergating_state state) |
467 | { |
468 | return 0; |
469 | } |
470 | |
471 | static const struct amd_ip_funcs tonga_ih_ip_funcs = { |
472 | .name = "tonga_ih" , |
473 | .early_init = tonga_ih_early_init, |
474 | .late_init = NULL, |
475 | .sw_init = tonga_ih_sw_init, |
476 | .sw_fini = tonga_ih_sw_fini, |
477 | .hw_init = tonga_ih_hw_init, |
478 | .hw_fini = tonga_ih_hw_fini, |
479 | .suspend = tonga_ih_suspend, |
480 | .resume = tonga_ih_resume, |
481 | .is_idle = tonga_ih_is_idle, |
482 | .wait_for_idle = tonga_ih_wait_for_idle, |
483 | .check_soft_reset = tonga_ih_check_soft_reset, |
484 | .pre_soft_reset = tonga_ih_pre_soft_reset, |
485 | .soft_reset = tonga_ih_soft_reset, |
486 | .post_soft_reset = tonga_ih_post_soft_reset, |
487 | .set_clockgating_state = tonga_ih_set_clockgating_state, |
488 | .set_powergating_state = tonga_ih_set_powergating_state, |
489 | }; |
490 | |
491 | static const struct amdgpu_ih_funcs tonga_ih_funcs = { |
492 | .get_wptr = tonga_ih_get_wptr, |
493 | .decode_iv = tonga_ih_decode_iv, |
494 | .set_rptr = tonga_ih_set_rptr |
495 | }; |
496 | |
497 | static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) |
498 | { |
499 | adev->irq.ih_funcs = &tonga_ih_funcs; |
500 | } |
501 | |
502 | const struct amdgpu_ip_block_version tonga_ih_ip_block = { |
503 | .type = AMD_IP_BLOCK_TYPE_IH, |
504 | .major = 3, |
505 | .minor = 0, |
506 | .rev = 0, |
507 | .funcs = &tonga_ih_ip_funcs, |
508 | }; |
509 | |