1 | /* |
2 | * Copyright 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | /* |
24 | * dc_debug.c |
25 | * |
26 | * Created on: Nov 3, 2016 |
27 | * Author: yonsun |
28 | */ |
29 | |
30 | #include "dm_services.h" |
31 | |
32 | #include "dc.h" |
33 | |
34 | #include "core_status.h" |
35 | #include "core_types.h" |
36 | |
37 | #include "resource.h" |
38 | |
39 | #define DC_LOGGER \ |
40 | dc->ctx->logger |
41 | #define DC_LOGGER_INIT(logger) |
42 | |
43 | |
44 | #define SURFACE_TRACE(...) do {\ |
45 | if (dc->debug.surface_trace) \ |
46 | DC_LOG_IF_TRACE(__VA_ARGS__); \ |
47 | } while (0) |
48 | |
49 | #define TIMING_TRACE(...) do {\ |
50 | if (dc->debug.timing_trace) \ |
51 | DC_LOG_SYNC(__VA_ARGS__); \ |
52 | } while (0) |
53 | |
54 | #define CLOCK_TRACE(...) do {\ |
55 | if (dc->debug.clock_trace) \ |
56 | DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \ |
57 | } while (0) |
58 | |
59 | void pre_surface_trace( |
60 | struct dc *dc, |
61 | const struct dc_plane_state *const *plane_states, |
62 | int surface_count) |
63 | { |
64 | int i; |
65 | DC_LOGGER_INIT(dc->ctx->logger); |
66 | |
67 | for (i = 0; i < surface_count; i++) { |
68 | const struct dc_plane_state *plane_state = plane_states[i]; |
69 | |
70 | SURFACE_TRACE("Planes %d:\n" , i); |
71 | |
72 | SURFACE_TRACE( |
73 | "plane_state->visible = %d;\n" |
74 | "plane_state->flip_immediate = %d;\n" |
75 | "plane_state->address.type = %d;\n" |
76 | "plane_state->address.grph.addr.quad_part = 0x%llX;\n" |
77 | "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n" |
78 | "plane_state->scaling_quality.h_taps = %d;\n" |
79 | "plane_state->scaling_quality.v_taps = %d;\n" |
80 | "plane_state->scaling_quality.h_taps_c = %d;\n" |
81 | "plane_state->scaling_quality.v_taps_c = %d;\n" , |
82 | plane_state->visible, |
83 | plane_state->flip_immediate, |
84 | plane_state->address.type, |
85 | plane_state->address.grph.addr.quad_part, |
86 | plane_state->address.grph.meta_addr.quad_part, |
87 | plane_state->scaling_quality.h_taps, |
88 | plane_state->scaling_quality.v_taps, |
89 | plane_state->scaling_quality.h_taps_c, |
90 | plane_state->scaling_quality.v_taps_c); |
91 | |
92 | SURFACE_TRACE( |
93 | "plane_state->src_rect.x = %d;\n" |
94 | "plane_state->src_rect.y = %d;\n" |
95 | "plane_state->src_rect.width = %d;\n" |
96 | "plane_state->src_rect.height = %d;\n" |
97 | "plane_state->dst_rect.x = %d;\n" |
98 | "plane_state->dst_rect.y = %d;\n" |
99 | "plane_state->dst_rect.width = %d;\n" |
100 | "plane_state->dst_rect.height = %d;\n" |
101 | "plane_state->clip_rect.x = %d;\n" |
102 | "plane_state->clip_rect.y = %d;\n" |
103 | "plane_state->clip_rect.width = %d;\n" |
104 | "plane_state->clip_rect.height = %d;\n" , |
105 | plane_state->src_rect.x, |
106 | plane_state->src_rect.y, |
107 | plane_state->src_rect.width, |
108 | plane_state->src_rect.height, |
109 | plane_state->dst_rect.x, |
110 | plane_state->dst_rect.y, |
111 | plane_state->dst_rect.width, |
112 | plane_state->dst_rect.height, |
113 | plane_state->clip_rect.x, |
114 | plane_state->clip_rect.y, |
115 | plane_state->clip_rect.width, |
116 | plane_state->clip_rect.height); |
117 | |
118 | SURFACE_TRACE( |
119 | "plane_state->plane_size.surface_size.x = %d;\n" |
120 | "plane_state->plane_size.surface_size.y = %d;\n" |
121 | "plane_state->plane_size.surface_size.width = %d;\n" |
122 | "plane_state->plane_size.surface_size.height = %d;\n" |
123 | "plane_state->plane_size.surface_pitch = %d;\n" , |
124 | plane_state->plane_size.surface_size.x, |
125 | plane_state->plane_size.surface_size.y, |
126 | plane_state->plane_size.surface_size.width, |
127 | plane_state->plane_size.surface_size.height, |
128 | plane_state->plane_size.surface_pitch); |
129 | |
130 | |
131 | SURFACE_TRACE( |
132 | "plane_state->tiling_info.gfx8.num_banks = %d;\n" |
133 | "plane_state->tiling_info.gfx8.bank_width = %d;\n" |
134 | "plane_state->tiling_info.gfx8.bank_width_c = %d;\n" |
135 | "plane_state->tiling_info.gfx8.bank_height = %d;\n" |
136 | "plane_state->tiling_info.gfx8.bank_height_c = %d;\n" |
137 | "plane_state->tiling_info.gfx8.tile_aspect = %d;\n" |
138 | "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n" |
139 | "plane_state->tiling_info.gfx8.tile_split = %d;\n" |
140 | "plane_state->tiling_info.gfx8.tile_split_c = %d;\n" |
141 | "plane_state->tiling_info.gfx8.tile_mode = %d;\n" |
142 | "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n" , |
143 | plane_state->tiling_info.gfx8.num_banks, |
144 | plane_state->tiling_info.gfx8.bank_width, |
145 | plane_state->tiling_info.gfx8.bank_width_c, |
146 | plane_state->tiling_info.gfx8.bank_height, |
147 | plane_state->tiling_info.gfx8.bank_height_c, |
148 | plane_state->tiling_info.gfx8.tile_aspect, |
149 | plane_state->tiling_info.gfx8.tile_aspect_c, |
150 | plane_state->tiling_info.gfx8.tile_split, |
151 | plane_state->tiling_info.gfx8.tile_split_c, |
152 | plane_state->tiling_info.gfx8.tile_mode, |
153 | plane_state->tiling_info.gfx8.tile_mode_c); |
154 | |
155 | SURFACE_TRACE( |
156 | "plane_state->tiling_info.gfx8.pipe_config = %d;\n" |
157 | "plane_state->tiling_info.gfx8.array_mode = %d;\n" |
158 | "plane_state->color_space = %d;\n" |
159 | "plane_state->dcc.enable = %d;\n" |
160 | "plane_state->format = %d;\n" |
161 | "plane_state->rotation = %d;\n" |
162 | "plane_state->stereo_format = %d;\n" , |
163 | plane_state->tiling_info.gfx8.pipe_config, |
164 | plane_state->tiling_info.gfx8.array_mode, |
165 | plane_state->color_space, |
166 | plane_state->dcc.enable, |
167 | plane_state->format, |
168 | plane_state->rotation, |
169 | plane_state->stereo_format); |
170 | |
171 | SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n" , |
172 | plane_state->tiling_info.gfx9.swizzle); |
173 | |
174 | SURFACE_TRACE("\n" ); |
175 | } |
176 | SURFACE_TRACE("\n" ); |
177 | } |
178 | |
179 | void update_surface_trace( |
180 | struct dc *dc, |
181 | const struct dc_surface_update *updates, |
182 | int surface_count) |
183 | { |
184 | int i; |
185 | DC_LOGGER_INIT(dc->ctx->logger); |
186 | |
187 | for (i = 0; i < surface_count; i++) { |
188 | const struct dc_surface_update *update = &updates[i]; |
189 | |
190 | SURFACE_TRACE("Update %d\n" , i); |
191 | if (update->flip_addr) { |
192 | SURFACE_TRACE("flip_addr->address.type = %d;\n" |
193 | "flip_addr->address.grph.addr.quad_part = 0x%llX;\n" |
194 | "flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n" |
195 | "flip_addr->flip_immediate = %d;\n" , |
196 | update->flip_addr->address.type, |
197 | update->flip_addr->address.grph.addr.quad_part, |
198 | update->flip_addr->address.grph.meta_addr.quad_part, |
199 | update->flip_addr->flip_immediate); |
200 | } |
201 | |
202 | if (update->plane_info) { |
203 | SURFACE_TRACE( |
204 | "plane_info->color_space = %d;\n" |
205 | "plane_info->format = %d;\n" |
206 | "plane_info->plane_size.surface_pitch = %d;\n" |
207 | "plane_info->plane_size.surface_size.height = %d;\n" |
208 | "plane_info->plane_size.surface_size.width = %d;\n" |
209 | "plane_info->plane_size.surface_size.x = %d;\n" |
210 | "plane_info->plane_size.surface_size.y = %d;\n" |
211 | "plane_info->rotation = %d;\n" |
212 | "plane_info->stereo_format = %d;\n" , |
213 | update->plane_info->color_space, |
214 | update->plane_info->format, |
215 | update->plane_info->plane_size.surface_pitch, |
216 | update->plane_info->plane_size.surface_size.height, |
217 | update->plane_info->plane_size.surface_size.width, |
218 | update->plane_info->plane_size.surface_size.x, |
219 | update->plane_info->plane_size.surface_size.y, |
220 | update->plane_info->rotation, |
221 | update->plane_info->stereo_format); |
222 | |
223 | SURFACE_TRACE( |
224 | "plane_info->tiling_info.gfx8.num_banks = %d;\n" |
225 | "plane_info->tiling_info.gfx8.bank_width = %d;\n" |
226 | "plane_info->tiling_info.gfx8.bank_width_c = %d;\n" |
227 | "plane_info->tiling_info.gfx8.bank_height = %d;\n" |
228 | "plane_info->tiling_info.gfx8.bank_height_c = %d;\n" |
229 | "plane_info->tiling_info.gfx8.tile_aspect = %d;\n" |
230 | "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n" |
231 | "plane_info->tiling_info.gfx8.tile_split = %d;\n" |
232 | "plane_info->tiling_info.gfx8.tile_split_c = %d;\n" |
233 | "plane_info->tiling_info.gfx8.tile_mode = %d;\n" |
234 | "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n" , |
235 | update->plane_info->tiling_info.gfx8.num_banks, |
236 | update->plane_info->tiling_info.gfx8.bank_width, |
237 | update->plane_info->tiling_info.gfx8.bank_width_c, |
238 | update->plane_info->tiling_info.gfx8.bank_height, |
239 | update->plane_info->tiling_info.gfx8.bank_height_c, |
240 | update->plane_info->tiling_info.gfx8.tile_aspect, |
241 | update->plane_info->tiling_info.gfx8.tile_aspect_c, |
242 | update->plane_info->tiling_info.gfx8.tile_split, |
243 | update->plane_info->tiling_info.gfx8.tile_split_c, |
244 | update->plane_info->tiling_info.gfx8.tile_mode, |
245 | update->plane_info->tiling_info.gfx8.tile_mode_c); |
246 | |
247 | SURFACE_TRACE( |
248 | "plane_info->tiling_info.gfx8.pipe_config = %d;\n" |
249 | "plane_info->tiling_info.gfx8.array_mode = %d;\n" |
250 | "plane_info->visible = %d;\n" |
251 | "plane_info->per_pixel_alpha = %d;\n" , |
252 | update->plane_info->tiling_info.gfx8.pipe_config, |
253 | update->plane_info->tiling_info.gfx8.array_mode, |
254 | update->plane_info->visible, |
255 | update->plane_info->per_pixel_alpha); |
256 | |
257 | SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n" , |
258 | update->plane_info->tiling_info.gfx9.swizzle); |
259 | } |
260 | |
261 | if (update->scaling_info) { |
262 | SURFACE_TRACE( |
263 | "scaling_info->src_rect.x = %d;\n" |
264 | "scaling_info->src_rect.y = %d;\n" |
265 | "scaling_info->src_rect.width = %d;\n" |
266 | "scaling_info->src_rect.height = %d;\n" |
267 | "scaling_info->dst_rect.x = %d;\n" |
268 | "scaling_info->dst_rect.y = %d;\n" |
269 | "scaling_info->dst_rect.width = %d;\n" |
270 | "scaling_info->dst_rect.height = %d;\n" |
271 | "scaling_info->clip_rect.x = %d;\n" |
272 | "scaling_info->clip_rect.y = %d;\n" |
273 | "scaling_info->clip_rect.width = %d;\n" |
274 | "scaling_info->clip_rect.height = %d;\n" |
275 | "scaling_info->scaling_quality.h_taps = %d;\n" |
276 | "scaling_info->scaling_quality.v_taps = %d;\n" |
277 | "scaling_info->scaling_quality.h_taps_c = %d;\n" |
278 | "scaling_info->scaling_quality.v_taps_c = %d;\n" , |
279 | update->scaling_info->src_rect.x, |
280 | update->scaling_info->src_rect.y, |
281 | update->scaling_info->src_rect.width, |
282 | update->scaling_info->src_rect.height, |
283 | update->scaling_info->dst_rect.x, |
284 | update->scaling_info->dst_rect.y, |
285 | update->scaling_info->dst_rect.width, |
286 | update->scaling_info->dst_rect.height, |
287 | update->scaling_info->clip_rect.x, |
288 | update->scaling_info->clip_rect.y, |
289 | update->scaling_info->clip_rect.width, |
290 | update->scaling_info->clip_rect.height, |
291 | update->scaling_info->scaling_quality.h_taps, |
292 | update->scaling_info->scaling_quality.v_taps, |
293 | update->scaling_info->scaling_quality.h_taps_c, |
294 | update->scaling_info->scaling_quality.v_taps_c); |
295 | } |
296 | SURFACE_TRACE("\n" ); |
297 | } |
298 | SURFACE_TRACE("\n" ); |
299 | } |
300 | |
301 | void post_surface_trace(struct dc *dc) |
302 | { |
303 | DC_LOGGER_INIT(dc->ctx->logger); |
304 | |
305 | SURFACE_TRACE("post surface process.\n" ); |
306 | |
307 | } |
308 | |
309 | void context_timing_trace( |
310 | struct dc *dc, |
311 | struct resource_context *res_ctx) |
312 | { |
313 | int i; |
314 | int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; |
315 | struct crtc_position position; |
316 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; |
317 | DC_LOGGER_INIT(dc->ctx->logger); |
318 | |
319 | |
320 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
321 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; |
322 | /* get_position() returns CRTC vertical/horizontal counter |
323 | * hence not applicable for underlay pipe |
324 | */ |
325 | if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) |
326 | continue; |
327 | |
328 | pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); |
329 | h_pos[i] = position.horizontal_count; |
330 | v_pos[i] = position.vertical_count; |
331 | } |
332 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
333 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; |
334 | |
335 | if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) |
336 | continue; |
337 | |
338 | TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n" , |
339 | pipe_ctx->stream_res.tg->inst, |
340 | pipe_ctx->stream->timing.h_total, |
341 | pipe_ctx->stream->timing.v_total, |
342 | h_pos[i], v_pos[i]); |
343 | } |
344 | } |
345 | |
346 | void context_clock_trace( |
347 | struct dc *dc, |
348 | struct dc_state *context) |
349 | { |
350 | DC_LOGGER_INIT(dc->ctx->logger); |
351 | CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" |
352 | "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n" , |
353 | context->bw_ctx.bw.dcn.clk.dispclk_khz, |
354 | context->bw_ctx.bw.dcn.clk.dppclk_khz, |
355 | context->bw_ctx.bw.dcn.clk.dcfclk_khz, |
356 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, |
357 | context->bw_ctx.bw.dcn.clk.fclk_khz, |
358 | context->bw_ctx.bw.dcn.clk.socclk_khz); |
359 | CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" |
360 | "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n" , |
361 | context->bw_ctx.bw.dcn.clk.dispclk_khz, |
362 | context->bw_ctx.bw.dcn.clk.dppclk_khz, |
363 | context->bw_ctx.bw.dcn.clk.dcfclk_khz, |
364 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, |
365 | context->bw_ctx.bw.dcn.clk.fclk_khz, |
366 | context->bw_ctx.bw.dcn.clk.socclk_khz); |
367 | } |
368 | |
369 | /** |
370 | * dc_status_to_str - convert dc_status to a human readable string |
371 | * @status: dc_status to be converted |
372 | * |
373 | * Return: |
374 | * A string describing the DC status. |
375 | */ |
376 | char *dc_status_to_str(enum dc_status status) |
377 | { |
378 | switch (status) { |
379 | case DC_OK: |
380 | return "DC OK" ; |
381 | case DC_NO_CONTROLLER_RESOURCE: |
382 | return "No controller resource" ; |
383 | case DC_NO_STREAM_ENC_RESOURCE: |
384 | return "No stream encoder" ; |
385 | case DC_NO_CLOCK_SOURCE_RESOURCE: |
386 | return "No clock source" ; |
387 | case DC_FAIL_CONTROLLER_VALIDATE: |
388 | return "Controller validation failure" ; |
389 | case DC_FAIL_ENC_VALIDATE: |
390 | return "Encoder validation failure" ; |
391 | case DC_FAIL_ATTACH_SURFACES: |
392 | return "Surfaces attachment failure" ; |
393 | case DC_FAIL_DETACH_SURFACES: |
394 | return "Surfaces detachment failure" ; |
395 | case DC_FAIL_SURFACE_VALIDATE: |
396 | return "Surface validation failure" ; |
397 | case DC_NO_DP_LINK_BANDWIDTH: |
398 | return "No DP link bandwidth" ; |
399 | case DC_EXCEED_DONGLE_CAP: |
400 | return "Exceed dongle capability" ; |
401 | case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED: |
402 | return "Unsupported pixel format" ; |
403 | case DC_FAIL_BANDWIDTH_VALIDATE: |
404 | return "Bandwidth validation failure (BW and Watermark)" ; |
405 | case DC_FAIL_SCALING: |
406 | return "Scaling failure" ; |
407 | case DC_FAIL_DP_LINK_TRAINING: |
408 | return "DP link training failure" ; |
409 | case DC_FAIL_DSC_VALIDATE: |
410 | return "DSC validation failure" ; |
411 | case DC_NO_DSC_RESOURCE: |
412 | return "No DSC resource" ; |
413 | case DC_FAIL_UNSUPPORTED_1: |
414 | return "Unsupported" ; |
415 | case DC_FAIL_CLK_EXCEED_MAX: |
416 | return "Clk exceed max failure" ; |
417 | case DC_FAIL_CLK_BELOW_MIN: |
418 | return "Fail clk below minimum" ; |
419 | case DC_FAIL_CLK_BELOW_CFG_REQUIRED: |
420 | return "Fail clk below required CFG (hard_min in PPLIB)" ; |
421 | case DC_NOT_SUPPORTED: |
422 | return "The operation is not supported." ; |
423 | case DC_UNSUPPORTED_VALUE: |
424 | return "The value specified is not supported." ; |
425 | case DC_NO_LINK_ENC_RESOURCE: |
426 | return "No link encoder resource" ; |
427 | case DC_FAIL_DP_PAYLOAD_ALLOCATION: |
428 | return "Fail dp payload allocation" ; |
429 | case DC_FAIL_DP_LINK_BANDWIDTH: |
430 | return "Insufficient DP link bandwidth" ; |
431 | case DC_ERROR_UNEXPECTED: |
432 | return "Unexpected error" ; |
433 | } |
434 | |
435 | return "Unexpected status error" ; |
436 | } |
437 | |