1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "dm_services.h" |
27 | #include "dc_bios_types.h" |
28 | #include "dcn10_stream_encoder.h" |
29 | #include "reg_helper.h" |
30 | #include "hw_shared.h" |
31 | #include "link.h" |
32 | #include "dpcd_defs.h" |
33 | #include "dcn30/dcn30_afmt.h" |
34 | |
35 | #define DC_LOGGER \ |
36 | enc1->base.ctx->logger |
37 | |
38 | #define REG(reg)\ |
39 | (enc1->regs->reg) |
40 | |
41 | #undef FN |
42 | #define FN(reg_name, field_name) \ |
43 | enc1->se_shift->field_name, enc1->se_mask->field_name |
44 | |
45 | #define VBI_LINE_0 0 |
46 | #define DP_BLANK_MAX_RETRY 20 |
47 | #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 |
48 | |
49 | |
50 | enum { |
51 | DP_MST_UPDATE_MAX_RETRY = 50 |
52 | }; |
53 | |
54 | #define CTX \ |
55 | enc1->base.ctx |
56 | |
57 | void enc1_update_generic_info_packet( |
58 | struct dcn10_stream_encoder *enc1, |
59 | uint32_t packet_index, |
60 | const struct dc_info_packet *info_packet) |
61 | { |
62 | /* TODOFPGA Figure out a proper number for max_retries polling for lock |
63 | * use 50 for now. |
64 | */ |
65 | uint32_t max_retries = 50; |
66 | |
67 | /*we need turn on clock before programming AFMT block*/ |
68 | REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); |
69 | |
70 | if (packet_index >= 8) |
71 | ASSERT(0); |
72 | |
73 | /* poll dig_update_lock is not locked -> asic internal signal |
74 | * assume otg master lock will unlock it |
75 | */ |
76 | /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, |
77 | 0, 10, max_retries);*/ |
78 | |
79 | /* check if HW reading GSP memory */ |
80 | REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, |
81 | 0, 10, max_retries); |
82 | |
83 | /* HW does is not reading GSP memory not reading too long -> |
84 | * something wrong. clear GPS memory access and notify? |
85 | * hw SW is writing to GSP memory |
86 | */ |
87 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); |
88 | |
89 | /* choose which generic packet to use */ |
90 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL, |
91 | AFMT_GENERIC_INDEX, packet_index); |
92 | |
93 | /* write generic packet header |
94 | * (4th byte is for GENERIC0 only) |
95 | */ |
96 | REG_SET_4(AFMT_GENERIC_HDR, 0, |
97 | AFMT_GENERIC_HB0, info_packet->hb0, |
98 | AFMT_GENERIC_HB1, info_packet->hb1, |
99 | AFMT_GENERIC_HB2, info_packet->hb2, |
100 | AFMT_GENERIC_HB3, info_packet->hb3); |
101 | |
102 | /* write generic packet contents |
103 | * (we never use last 4 bytes) |
104 | * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers |
105 | */ |
106 | { |
107 | const uint32_t *content = |
108 | (const uint32_t *) &info_packet->sb[0]; |
109 | |
110 | REG_WRITE(AFMT_GENERIC_0, *content++); |
111 | REG_WRITE(AFMT_GENERIC_1, *content++); |
112 | REG_WRITE(AFMT_GENERIC_2, *content++); |
113 | REG_WRITE(AFMT_GENERIC_3, *content++); |
114 | REG_WRITE(AFMT_GENERIC_4, *content++); |
115 | REG_WRITE(AFMT_GENERIC_5, *content++); |
116 | REG_WRITE(AFMT_GENERIC_6, *content++); |
117 | REG_WRITE(AFMT_GENERIC_7, *content); |
118 | } |
119 | |
120 | switch (packet_index) { |
121 | case 0: |
122 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
123 | AFMT_GENERIC0_IMMEDIATE_UPDATE, 1); |
124 | break; |
125 | case 1: |
126 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
127 | AFMT_GENERIC1_IMMEDIATE_UPDATE, 1); |
128 | break; |
129 | case 2: |
130 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
131 | AFMT_GENERIC2_IMMEDIATE_UPDATE, 1); |
132 | break; |
133 | case 3: |
134 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
135 | AFMT_GENERIC3_IMMEDIATE_UPDATE, 1); |
136 | break; |
137 | case 4: |
138 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
139 | AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); |
140 | break; |
141 | case 5: |
142 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
143 | AFMT_GENERIC5_IMMEDIATE_UPDATE, 1); |
144 | break; |
145 | case 6: |
146 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
147 | AFMT_GENERIC6_IMMEDIATE_UPDATE, 1); |
148 | break; |
149 | case 7: |
150 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
151 | AFMT_GENERIC7_IMMEDIATE_UPDATE, 1); |
152 | break; |
153 | default: |
154 | break; |
155 | } |
156 | } |
157 | |
158 | static void enc1_update_hdmi_info_packet( |
159 | struct dcn10_stream_encoder *enc1, |
160 | uint32_t packet_index, |
161 | const struct dc_info_packet *info_packet) |
162 | { |
163 | uint32_t cont, send, line; |
164 | |
165 | if (info_packet->valid) { |
166 | enc1_update_generic_info_packet( |
167 | enc1, |
168 | packet_index, |
169 | info_packet); |
170 | |
171 | /* enable transmission of packet(s) - |
172 | * packet transmission begins on the next frame |
173 | */ |
174 | cont = 1; |
175 | /* send packet(s) every frame */ |
176 | send = 1; |
177 | /* select line number to send packets on */ |
178 | line = 2; |
179 | } else { |
180 | cont = 0; |
181 | send = 0; |
182 | line = 0; |
183 | } |
184 | |
185 | /* choose which generic packet control to use */ |
186 | switch (packet_index) { |
187 | case 0: |
188 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, |
189 | HDMI_GENERIC0_CONT, cont, |
190 | HDMI_GENERIC0_SEND, send, |
191 | HDMI_GENERIC0_LINE, line); |
192 | break; |
193 | case 1: |
194 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, |
195 | HDMI_GENERIC1_CONT, cont, |
196 | HDMI_GENERIC1_SEND, send, |
197 | HDMI_GENERIC1_LINE, line); |
198 | break; |
199 | case 2: |
200 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, |
201 | HDMI_GENERIC0_CONT, cont, |
202 | HDMI_GENERIC0_SEND, send, |
203 | HDMI_GENERIC0_LINE, line); |
204 | break; |
205 | case 3: |
206 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, |
207 | HDMI_GENERIC1_CONT, cont, |
208 | HDMI_GENERIC1_SEND, send, |
209 | HDMI_GENERIC1_LINE, line); |
210 | break; |
211 | case 4: |
212 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, |
213 | HDMI_GENERIC0_CONT, cont, |
214 | HDMI_GENERIC0_SEND, send, |
215 | HDMI_GENERIC0_LINE, line); |
216 | break; |
217 | case 5: |
218 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, |
219 | HDMI_GENERIC1_CONT, cont, |
220 | HDMI_GENERIC1_SEND, send, |
221 | HDMI_GENERIC1_LINE, line); |
222 | break; |
223 | case 6: |
224 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, |
225 | HDMI_GENERIC0_CONT, cont, |
226 | HDMI_GENERIC0_SEND, send, |
227 | HDMI_GENERIC0_LINE, line); |
228 | break; |
229 | case 7: |
230 | REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, |
231 | HDMI_GENERIC1_CONT, cont, |
232 | HDMI_GENERIC1_SEND, send, |
233 | HDMI_GENERIC1_LINE, line); |
234 | break; |
235 | default: |
236 | /* invalid HW packet index */ |
237 | DC_LOG_WARNING( |
238 | "Invalid HW packet index: %s()\n" , |
239 | __func__); |
240 | return; |
241 | } |
242 | } |
243 | |
244 | /* setup stream encoder in dp mode */ |
245 | void enc1_stream_encoder_dp_set_stream_attribute( |
246 | struct stream_encoder *enc, |
247 | struct dc_crtc_timing *crtc_timing, |
248 | enum dc_color_space output_color_space, |
249 | bool use_vsc_sdp_for_colorimetry, |
250 | uint32_t enable_sdp_splitting) |
251 | { |
252 | uint32_t h_active_start; |
253 | uint32_t v_active_start; |
254 | uint32_t misc0 = 0; |
255 | uint32_t misc1 = 0; |
256 | uint32_t h_blank; |
257 | uint32_t h_back_porch; |
258 | uint8_t synchronous_clock = 0; /* asynchronous mode */ |
259 | uint8_t colorimetry_bpc; |
260 | uint8_t dp_pixel_encoding = 0; |
261 | uint8_t dp_component_depth = 0; |
262 | |
263 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
264 | struct dc_crtc_timing hw_crtc_timing = *crtc_timing; |
265 | |
266 | if (hw_crtc_timing.flags.INTERLACE) { |
267 | /*the input timing is in VESA spec format with Interlace flag =1*/ |
268 | hw_crtc_timing.v_total /= 2; |
269 | hw_crtc_timing.v_border_top /= 2; |
270 | hw_crtc_timing.v_addressable /= 2; |
271 | hw_crtc_timing.v_border_bottom /= 2; |
272 | hw_crtc_timing.v_front_porch /= 2; |
273 | hw_crtc_timing.v_sync_width /= 2; |
274 | } |
275 | |
276 | |
277 | /* set pixel encoding */ |
278 | switch (hw_crtc_timing.pixel_encoding) { |
279 | case PIXEL_ENCODING_YCBCR422: |
280 | dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; |
281 | break; |
282 | case PIXEL_ENCODING_YCBCR444: |
283 | dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; |
284 | |
285 | if (hw_crtc_timing.flags.Y_ONLY) |
286 | if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) |
287 | /* HW testing only, no use case yet. |
288 | * Color depth of Y-only could be |
289 | * 8, 10, 12, 16 bits |
290 | */ |
291 | dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; |
292 | |
293 | /* Note: DP_MSA_MISC1 bit 7 is the indicator |
294 | * of Y-only mode. |
295 | * This bit is set in HW if register |
296 | * DP_PIXEL_ENCODING is programmed to 0x4 |
297 | */ |
298 | break; |
299 | case PIXEL_ENCODING_YCBCR420: |
300 | dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; |
301 | break; |
302 | default: |
303 | dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; |
304 | break; |
305 | } |
306 | |
307 | misc1 = REG_READ(DP_MSA_MISC); |
308 | /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. |
309 | * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the |
310 | * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, |
311 | * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). |
312 | */ |
313 | if (use_vsc_sdp_for_colorimetry) |
314 | misc1 = misc1 | 0x40; |
315 | else |
316 | misc1 = misc1 & ~0x40; |
317 | |
318 | /* set color depth */ |
319 | switch (hw_crtc_timing.display_color_depth) { |
320 | case COLOR_DEPTH_666: |
321 | dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; |
322 | break; |
323 | case COLOR_DEPTH_888: |
324 | dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; |
325 | break; |
326 | case COLOR_DEPTH_101010: |
327 | dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; |
328 | break; |
329 | case COLOR_DEPTH_121212: |
330 | dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; |
331 | break; |
332 | case COLOR_DEPTH_161616: |
333 | dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; |
334 | break; |
335 | default: |
336 | dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; |
337 | break; |
338 | } |
339 | |
340 | /* Set DP pixel encoding and component depth */ |
341 | REG_UPDATE_2(DP_PIXEL_FORMAT, |
342 | DP_PIXEL_ENCODING, dp_pixel_encoding, |
343 | DP_COMPONENT_DEPTH, dp_component_depth); |
344 | |
345 | /* set dynamic range and YCbCr range */ |
346 | |
347 | switch (hw_crtc_timing.display_color_depth) { |
348 | case COLOR_DEPTH_666: |
349 | colorimetry_bpc = 0; |
350 | break; |
351 | case COLOR_DEPTH_888: |
352 | colorimetry_bpc = 1; |
353 | break; |
354 | case COLOR_DEPTH_101010: |
355 | colorimetry_bpc = 2; |
356 | break; |
357 | case COLOR_DEPTH_121212: |
358 | colorimetry_bpc = 3; |
359 | break; |
360 | default: |
361 | colorimetry_bpc = 0; |
362 | break; |
363 | } |
364 | |
365 | misc0 = misc0 | synchronous_clock; |
366 | misc0 = colorimetry_bpc << 5; |
367 | |
368 | switch (output_color_space) { |
369 | case COLOR_SPACE_SRGB: |
370 | misc1 = misc1 & ~0x80; /* bit7 = 0*/ |
371 | break; |
372 | case COLOR_SPACE_SRGB_LIMITED: |
373 | misc0 = misc0 | 0x8; /* bit3=1 */ |
374 | misc1 = misc1 & ~0x80; /* bit7 = 0*/ |
375 | break; |
376 | case COLOR_SPACE_YCBCR601: |
377 | case COLOR_SPACE_YCBCR601_LIMITED: |
378 | misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ |
379 | misc1 = misc1 & ~0x80; /* bit7 = 0*/ |
380 | if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) |
381 | misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ |
382 | else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) |
383 | misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ |
384 | break; |
385 | case COLOR_SPACE_YCBCR709: |
386 | case COLOR_SPACE_YCBCR709_LIMITED: |
387 | misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ |
388 | misc1 = misc1 & ~0x80; /* bit7 = 0*/ |
389 | if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) |
390 | misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ |
391 | else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) |
392 | misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ |
393 | break; |
394 | case COLOR_SPACE_2020_RGB_LIMITEDRANGE: |
395 | case COLOR_SPACE_2020_RGB_FULLRANGE: |
396 | case COLOR_SPACE_2020_YCBCR: |
397 | case COLOR_SPACE_XR_RGB: |
398 | case COLOR_SPACE_MSREF_SCRGB: |
399 | case COLOR_SPACE_ADOBERGB: |
400 | case COLOR_SPACE_DCIP3: |
401 | case COLOR_SPACE_XV_YCC_709: |
402 | case COLOR_SPACE_XV_YCC_601: |
403 | case COLOR_SPACE_DISPLAYNATIVE: |
404 | case COLOR_SPACE_DOLBYVISION: |
405 | case COLOR_SPACE_APPCTRL: |
406 | case COLOR_SPACE_CUSTOMPOINTS: |
407 | case COLOR_SPACE_UNKNOWN: |
408 | case COLOR_SPACE_YCBCR709_BLACK: |
409 | /* do nothing */ |
410 | break; |
411 | } |
412 | |
413 | REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); |
414 | REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ |
415 | |
416 | /* dcn new register |
417 | * dc_crtc_timing is vesa dmt struct. data from edid |
418 | */ |
419 | REG_SET_2(DP_MSA_TIMING_PARAM1, 0, |
420 | DP_MSA_HTOTAL, hw_crtc_timing.h_total, |
421 | DP_MSA_VTOTAL, hw_crtc_timing.v_total); |
422 | |
423 | /* calculate from vesa timing parameters |
424 | * h_active_start related to leading edge of sync |
425 | */ |
426 | |
427 | h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - |
428 | hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; |
429 | |
430 | h_back_porch = h_blank - hw_crtc_timing.h_front_porch - |
431 | hw_crtc_timing.h_sync_width; |
432 | |
433 | /* start at beginning of left border */ |
434 | h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; |
435 | |
436 | |
437 | v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - |
438 | hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - |
439 | hw_crtc_timing.v_front_porch; |
440 | |
441 | |
442 | /* start at beginning of left border */ |
443 | REG_SET_2(DP_MSA_TIMING_PARAM2, 0, |
444 | DP_MSA_HSTART, h_active_start, |
445 | DP_MSA_VSTART, v_active_start); |
446 | |
447 | REG_SET_4(DP_MSA_TIMING_PARAM3, 0, |
448 | DP_MSA_HSYNCWIDTH, |
449 | hw_crtc_timing.h_sync_width, |
450 | DP_MSA_HSYNCPOLARITY, |
451 | !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, |
452 | DP_MSA_VSYNCWIDTH, |
453 | hw_crtc_timing.v_sync_width, |
454 | DP_MSA_VSYNCPOLARITY, |
455 | !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); |
456 | |
457 | /* HWDITH include border or overscan */ |
458 | REG_SET_2(DP_MSA_TIMING_PARAM4, 0, |
459 | DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + |
460 | hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, |
461 | DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + |
462 | hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); |
463 | } |
464 | |
465 | void enc1_stream_encoder_set_stream_attribute_helper( |
466 | struct dcn10_stream_encoder *enc1, |
467 | struct dc_crtc_timing *crtc_timing) |
468 | { |
469 | switch (crtc_timing->pixel_encoding) { |
470 | case PIXEL_ENCODING_YCBCR422: |
471 | REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); |
472 | break; |
473 | default: |
474 | REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); |
475 | break; |
476 | } |
477 | REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); |
478 | } |
479 | |
480 | /* setup stream encoder in hdmi mode */ |
481 | void enc1_stream_encoder_hdmi_set_stream_attribute( |
482 | struct stream_encoder *enc, |
483 | struct dc_crtc_timing *crtc_timing, |
484 | int actual_pix_clk_khz, |
485 | bool enable_audio) |
486 | { |
487 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
488 | struct bp_encoder_control cntl = {0}; |
489 | |
490 | cntl.action = ENCODER_CONTROL_SETUP; |
491 | cntl.engine_id = enc1->base.id; |
492 | cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; |
493 | cntl.enable_dp_audio = enable_audio; |
494 | cntl.pixel_clock = actual_pix_clk_khz; |
495 | cntl.lanes_number = LANE_COUNT_FOUR; |
496 | |
497 | if (enc1->base.bp->funcs->encoder_control( |
498 | enc1->base.bp, &cntl) != BP_RESULT_OK) |
499 | return; |
500 | |
501 | enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); |
502 | |
503 | /* setup HDMI engine */ |
504 | REG_UPDATE_6(HDMI_CONTROL, |
505 | HDMI_PACKET_GEN_VERSION, 1, |
506 | HDMI_KEEPOUT_MODE, 1, |
507 | HDMI_DEEP_COLOR_ENABLE, 0, |
508 | HDMI_DATA_SCRAMBLE_EN, 0, |
509 | HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, |
510 | HDMI_CLOCK_CHANNEL_RATE, 0); |
511 | |
512 | |
513 | switch (crtc_timing->display_color_depth) { |
514 | case COLOR_DEPTH_888: |
515 | REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); |
516 | DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n" ); |
517 | break; |
518 | case COLOR_DEPTH_101010: |
519 | if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { |
520 | REG_UPDATE_2(HDMI_CONTROL, |
521 | HDMI_DEEP_COLOR_DEPTH, 1, |
522 | HDMI_DEEP_COLOR_ENABLE, 0); |
523 | DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \ |
524 | "disabled for YCBCR422 pixel encoding\n" ); |
525 | } else { |
526 | REG_UPDATE_2(HDMI_CONTROL, |
527 | HDMI_DEEP_COLOR_DEPTH, 1, |
528 | HDMI_DEEP_COLOR_ENABLE, 1); |
529 | DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \ |
530 | "enabled for YCBCR422 non-pixel encoding\n" ); |
531 | } |
532 | break; |
533 | case COLOR_DEPTH_121212: |
534 | if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { |
535 | REG_UPDATE_2(HDMI_CONTROL, |
536 | HDMI_DEEP_COLOR_DEPTH, 2, |
537 | HDMI_DEEP_COLOR_ENABLE, 0); |
538 | DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \ |
539 | "disabled for YCBCR422 pixel encoding\n" ); |
540 | } else { |
541 | REG_UPDATE_2(HDMI_CONTROL, |
542 | HDMI_DEEP_COLOR_DEPTH, 2, |
543 | HDMI_DEEP_COLOR_ENABLE, 1); |
544 | DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \ |
545 | "enabled for non-pixel YCBCR422 encoding\n" ); |
546 | } |
547 | break; |
548 | case COLOR_DEPTH_161616: |
549 | REG_UPDATE_2(HDMI_CONTROL, |
550 | HDMI_DEEP_COLOR_DEPTH, 3, |
551 | HDMI_DEEP_COLOR_ENABLE, 1); |
552 | DC_LOG_DEBUG("HDMI source deep color depth enabled in" \ |
553 | "reserved mode\n" ); |
554 | break; |
555 | default: |
556 | break; |
557 | } |
558 | |
559 | if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { |
560 | /* enable HDMI data scrambler |
561 | * HDMI_CLOCK_CHANNEL_RATE_MORE_340M |
562 | * Clock channel frequency is 1/4 of character rate. |
563 | */ |
564 | REG_UPDATE_2(HDMI_CONTROL, |
565 | HDMI_DATA_SCRAMBLE_EN, 1, |
566 | HDMI_CLOCK_CHANNEL_RATE, 1); |
567 | } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { |
568 | |
569 | /* TODO: New feature for DCE11, still need to implement */ |
570 | |
571 | /* enable HDMI data scrambler |
572 | * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE |
573 | * Clock channel frequency is the same |
574 | * as character rate |
575 | */ |
576 | REG_UPDATE_2(HDMI_CONTROL, |
577 | HDMI_DATA_SCRAMBLE_EN, 1, |
578 | HDMI_CLOCK_CHANNEL_RATE, 0); |
579 | } |
580 | |
581 | |
582 | REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, |
583 | HDMI_GC_CONT, 1, |
584 | HDMI_GC_SEND, 1, |
585 | HDMI_NULL_SEND, 1); |
586 | |
587 | REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); |
588 | |
589 | /* following belongs to audio */ |
590 | REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); |
591 | |
592 | REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); |
593 | |
594 | REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, |
595 | VBI_LINE_0 + 2); |
596 | |
597 | REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); |
598 | } |
599 | |
600 | /* setup stream encoder in dvi mode */ |
601 | void enc1_stream_encoder_dvi_set_stream_attribute( |
602 | struct stream_encoder *enc, |
603 | struct dc_crtc_timing *crtc_timing, |
604 | bool is_dual_link) |
605 | { |
606 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
607 | struct bp_encoder_control cntl = {0}; |
608 | |
609 | cntl.action = ENCODER_CONTROL_SETUP; |
610 | cntl.engine_id = enc1->base.id; |
611 | cntl.signal = is_dual_link ? |
612 | SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; |
613 | cntl.enable_dp_audio = false; |
614 | cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; |
615 | cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; |
616 | |
617 | if (enc1->base.bp->funcs->encoder_control( |
618 | enc1->base.bp, &cntl) != BP_RESULT_OK) |
619 | return; |
620 | |
621 | ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); |
622 | ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); |
623 | enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); |
624 | } |
625 | |
626 | void enc1_stream_encoder_set_throttled_vcp_size( |
627 | struct stream_encoder *enc, |
628 | struct fixed31_32 avg_time_slots_per_mtp) |
629 | { |
630 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
631 | uint32_t x = dc_fixpt_floor( |
632 | arg: avg_time_slots_per_mtp); |
633 | uint32_t y = dc_fixpt_ceil( |
634 | arg: dc_fixpt_shl( |
635 | arg: dc_fixpt_sub_int( |
636 | arg1: avg_time_slots_per_mtp, |
637 | arg2: x), |
638 | shift: 26)); |
639 | |
640 | // If y rounds up to integer, carry it over to x. |
641 | if (y >> 26) { |
642 | x += 1; |
643 | y = 0; |
644 | } |
645 | |
646 | REG_SET_2(DP_MSE_RATE_CNTL, 0, |
647 | DP_MSE_RATE_X, x, |
648 | DP_MSE_RATE_Y, y); |
649 | |
650 | /* wait for update to be completed on the link */ |
651 | /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ |
652 | /* is reset to 0 (not pending) */ |
653 | REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, |
654 | 0, |
655 | 10, DP_MST_UPDATE_MAX_RETRY); |
656 | } |
657 | |
658 | static void enc1_stream_encoder_update_hdmi_info_packets( |
659 | struct stream_encoder *enc, |
660 | const struct encoder_info_frame *info_frame) |
661 | { |
662 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
663 | |
664 | /* for bring up, disable dp double TODO */ |
665 | REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); |
666 | |
667 | /*Always add mandatory packets first followed by optional ones*/ |
668 | enc1_update_hdmi_info_packet(enc1, packet_index: 0, info_packet: &info_frame->avi); |
669 | enc1_update_hdmi_info_packet(enc1, packet_index: 1, info_packet: &info_frame->hfvsif); |
670 | enc1_update_hdmi_info_packet(enc1, packet_index: 2, info_packet: &info_frame->gamut); |
671 | enc1_update_hdmi_info_packet(enc1, packet_index: 3, info_packet: &info_frame->vendor); |
672 | enc1_update_hdmi_info_packet(enc1, packet_index: 4, info_packet: &info_frame->spd); |
673 | enc1_update_hdmi_info_packet(enc1, packet_index: 5, info_packet: &info_frame->hdrsmd); |
674 | } |
675 | |
676 | static void enc1_stream_encoder_stop_hdmi_info_packets( |
677 | struct stream_encoder *enc) |
678 | { |
679 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
680 | |
681 | /* stop generic packets 0 & 1 on HDMI */ |
682 | REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, |
683 | HDMI_GENERIC1_CONT, 0, |
684 | HDMI_GENERIC1_LINE, 0, |
685 | HDMI_GENERIC1_SEND, 0, |
686 | HDMI_GENERIC0_CONT, 0, |
687 | HDMI_GENERIC0_LINE, 0, |
688 | HDMI_GENERIC0_SEND, 0); |
689 | |
690 | /* stop generic packets 2 & 3 on HDMI */ |
691 | REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, |
692 | HDMI_GENERIC0_CONT, 0, |
693 | HDMI_GENERIC0_LINE, 0, |
694 | HDMI_GENERIC0_SEND, 0, |
695 | HDMI_GENERIC1_CONT, 0, |
696 | HDMI_GENERIC1_LINE, 0, |
697 | HDMI_GENERIC1_SEND, 0); |
698 | |
699 | /* stop generic packets 2 & 3 on HDMI */ |
700 | REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, |
701 | HDMI_GENERIC0_CONT, 0, |
702 | HDMI_GENERIC0_LINE, 0, |
703 | HDMI_GENERIC0_SEND, 0, |
704 | HDMI_GENERIC1_CONT, 0, |
705 | HDMI_GENERIC1_LINE, 0, |
706 | HDMI_GENERIC1_SEND, 0); |
707 | |
708 | REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, |
709 | HDMI_GENERIC0_CONT, 0, |
710 | HDMI_GENERIC0_LINE, 0, |
711 | HDMI_GENERIC0_SEND, 0, |
712 | HDMI_GENERIC1_CONT, 0, |
713 | HDMI_GENERIC1_LINE, 0, |
714 | HDMI_GENERIC1_SEND, 0); |
715 | } |
716 | |
717 | void enc1_stream_encoder_update_dp_info_packets( |
718 | struct stream_encoder *enc, |
719 | const struct encoder_info_frame *info_frame) |
720 | { |
721 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
722 | uint32_t value = 0; |
723 | |
724 | if (info_frame->vsc.valid) |
725 | enc1_update_generic_info_packet( |
726 | enc1, |
727 | packet_index: 0, /* packetIndex */ |
728 | info_packet: &info_frame->vsc); |
729 | |
730 | /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW. |
731 | * Note that the enablement of GSP1 is not done below, |
732 | * it's done in FW. |
733 | */ |
734 | if (info_frame->vsc.valid) |
735 | enc1_update_generic_info_packet( |
736 | enc1, |
737 | packet_index: 1, /* packetIndex */ |
738 | info_packet: &info_frame->vsc); |
739 | |
740 | if (info_frame->spd.valid) |
741 | enc1_update_generic_info_packet( |
742 | enc1, |
743 | packet_index: 2, /* packetIndex */ |
744 | info_packet: &info_frame->spd); |
745 | |
746 | if (info_frame->hdrsmd.valid) |
747 | enc1_update_generic_info_packet( |
748 | enc1, |
749 | packet_index: 3, /* packetIndex */ |
750 | info_packet: &info_frame->hdrsmd); |
751 | |
752 | /* packetIndex 4 is used for send immediate sdp message, and please |
753 | * use other packetIndex (such as 5,6) for other info packet |
754 | */ |
755 | |
756 | if (info_frame->adaptive_sync.valid) |
757 | enc1_update_generic_info_packet( |
758 | enc1, |
759 | packet_index: 5, /* packetIndex */ |
760 | info_packet: &info_frame->adaptive_sync); |
761 | |
762 | /* enable/disable transmission of packet(s). |
763 | * If enabled, packet transmission begins on the next frame |
764 | */ |
765 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); |
766 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); |
767 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); |
768 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid); |
769 | |
770 | /* This bit is the master enable bit. |
771 | * When enabling secondary stream engine, |
772 | * this master bit must also be set. |
773 | * This register shared with audio info frame. |
774 | * Therefore we need to enable master bit |
775 | * if at least on of the fields is not 0 |
776 | */ |
777 | value = REG_READ(DP_SEC_CNTL); |
778 | if (value) |
779 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); |
780 | } |
781 | |
782 | void enc1_stream_encoder_send_immediate_sdp_message( |
783 | struct stream_encoder *enc, |
784 | const uint8_t *custom_sdp_message, |
785 | unsigned int sdp_message_size) |
786 | { |
787 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
788 | uint32_t value = 0; |
789 | |
790 | /* TODOFPGA Figure out a proper number for max_retries polling for lock |
791 | * use 50 for now. |
792 | */ |
793 | uint32_t max_retries = 50; |
794 | |
795 | /* check if GSP4 is transmitted */ |
796 | REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, |
797 | 0, 10, max_retries); |
798 | |
799 | /* disable GSP4 transmitting */ |
800 | REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); |
801 | |
802 | /* transmit GSP4 at the earliest time in a frame */ |
803 | REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); |
804 | |
805 | /*we need turn on clock before programming AFMT block*/ |
806 | REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); |
807 | |
808 | /* check if HW reading GSP memory */ |
809 | REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, |
810 | 0, 10, max_retries); |
811 | |
812 | /* HW does is not reading GSP memory not reading too long -> |
813 | * something wrong. clear GPS memory access and notify? |
814 | * hw SW is writing to GSP memory |
815 | */ |
816 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); |
817 | |
818 | /* use generic packet 4 for immediate sdp message */ |
819 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL, |
820 | AFMT_GENERIC_INDEX, 4); |
821 | |
822 | /* write generic packet header |
823 | * (4th byte is for GENERIC0 only) |
824 | */ |
825 | REG_SET_4(AFMT_GENERIC_HDR, 0, |
826 | AFMT_GENERIC_HB0, custom_sdp_message[0], |
827 | AFMT_GENERIC_HB1, custom_sdp_message[1], |
828 | AFMT_GENERIC_HB2, custom_sdp_message[2], |
829 | AFMT_GENERIC_HB3, custom_sdp_message[3]); |
830 | |
831 | /* write generic packet contents |
832 | * (we never use last 4 bytes) |
833 | * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers |
834 | */ |
835 | { |
836 | const uint32_t *content = |
837 | (const uint32_t *) &custom_sdp_message[4]; |
838 | |
839 | REG_WRITE(AFMT_GENERIC_0, *content++); |
840 | REG_WRITE(AFMT_GENERIC_1, *content++); |
841 | REG_WRITE(AFMT_GENERIC_2, *content++); |
842 | REG_WRITE(AFMT_GENERIC_3, *content++); |
843 | REG_WRITE(AFMT_GENERIC_4, *content++); |
844 | REG_WRITE(AFMT_GENERIC_5, *content++); |
845 | REG_WRITE(AFMT_GENERIC_6, *content++); |
846 | REG_WRITE(AFMT_GENERIC_7, *content); |
847 | } |
848 | |
849 | /* check whether GENERIC4 registers double buffer update in immediate mode |
850 | * is pending |
851 | */ |
852 | REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, |
853 | 0, 10, max_retries); |
854 | |
855 | /* atomically update double-buffered GENERIC4 registers in immediate mode |
856 | * (update immediately) |
857 | */ |
858 | REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, |
859 | AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); |
860 | |
861 | /* enable GSP4 transmitting */ |
862 | REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); |
863 | |
864 | /* This bit is the master enable bit. |
865 | * When enabling secondary stream engine, |
866 | * this master bit must also be set. |
867 | * This register shared with audio info frame. |
868 | * Therefore we need to enable master bit |
869 | * if at least on of the fields is not 0 |
870 | */ |
871 | value = REG_READ(DP_SEC_CNTL); |
872 | if (value) |
873 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); |
874 | } |
875 | |
876 | void enc1_stream_encoder_stop_dp_info_packets( |
877 | struct stream_encoder *enc) |
878 | { |
879 | /* stop generic packets on DP */ |
880 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
881 | uint32_t value = 0; |
882 | |
883 | REG_SET_10(DP_SEC_CNTL, 0, |
884 | DP_SEC_GSP0_ENABLE, 0, |
885 | DP_SEC_GSP1_ENABLE, 0, |
886 | DP_SEC_GSP2_ENABLE, 0, |
887 | DP_SEC_GSP3_ENABLE, 0, |
888 | DP_SEC_GSP4_ENABLE, 0, |
889 | DP_SEC_GSP5_ENABLE, 0, |
890 | DP_SEC_GSP6_ENABLE, 0, |
891 | DP_SEC_GSP7_ENABLE, 0, |
892 | DP_SEC_MPG_ENABLE, 0, |
893 | DP_SEC_STREAM_ENABLE, 0); |
894 | |
895 | /* this register shared with audio info frame. |
896 | * therefore we need to keep master enabled |
897 | * if at least one of the fields is not 0 */ |
898 | value = REG_READ(DP_SEC_CNTL); |
899 | if (value) |
900 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); |
901 | |
902 | } |
903 | |
904 | void enc1_stream_encoder_dp_blank( |
905 | struct dc_link *link, |
906 | struct stream_encoder *enc) |
907 | { |
908 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
909 | uint32_t reg1 = 0; |
910 | uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; |
911 | |
912 | /* Note: For CZ, we are changing driver default to disable |
913 | * stream deferred to next VBLANK. If results are positive, we |
914 | * will make the same change to all DCE versions. There are a |
915 | * handful of panels that cannot handle disable stream at |
916 | * HBLANK and will result in a white line flash across the |
917 | * screen on stream disable. |
918 | */ |
919 | REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); |
920 | if ((reg1 & 0x1) == 0) |
921 | /*stream not enabled*/ |
922 | return; |
923 | /* Specify the video stream disable point |
924 | * (2 = start of the next vertical blank) |
925 | */ |
926 | REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); |
927 | /* Larger delay to wait until VBLANK - use max retry of |
928 | * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + |
929 | * a little more because we may not trust delay accuracy. |
930 | */ |
931 | max_retries = DP_BLANK_MAX_RETRY * 501; |
932 | |
933 | /* disable DP stream */ |
934 | REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); |
935 | |
936 | link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM); |
937 | |
938 | /* the encoder stops sending the video stream |
939 | * at the start of the vertical blanking. |
940 | * Poll for DP_VID_STREAM_STATUS == 0 |
941 | */ |
942 | |
943 | REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, |
944 | 0, |
945 | 10, max_retries); |
946 | |
947 | /* Tell the DP encoder to ignore timing from CRTC, must be done after |
948 | * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is |
949 | * complete, stream status will be stuck in video stream enabled state, |
950 | * i.e. DP_VID_STREAM_STATUS stuck at 1. |
951 | */ |
952 | |
953 | REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); |
954 | |
955 | link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET); |
956 | } |
957 | |
958 | /* output video stream to link encoder */ |
959 | void enc1_stream_encoder_dp_unblank( |
960 | struct dc_link *link, |
961 | struct stream_encoder *enc, |
962 | const struct encoder_unblank_param *param) |
963 | { |
964 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
965 | |
966 | if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { |
967 | uint32_t n_vid = 0x8000; |
968 | uint32_t m_vid; |
969 | uint32_t n_multiply = 0; |
970 | uint64_t m_vid_l = n_vid; |
971 | |
972 | /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ |
973 | if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { |
974 | /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ |
975 | n_multiply = 1; |
976 | } |
977 | /* M / N = Fstream / Flink |
978 | * m_vid / n_vid = pixel rate / link rate |
979 | */ |
980 | |
981 | m_vid_l *= param->timing.pix_clk_100hz / 10; |
982 | m_vid_l = div_u64(dividend: m_vid_l, |
983 | divisor: param->link_settings.link_rate |
984 | * LINK_RATE_REF_FREQ_IN_KHZ); |
985 | |
986 | m_vid = (uint32_t) m_vid_l; |
987 | |
988 | /* enable auto measurement */ |
989 | |
990 | REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); |
991 | |
992 | /* auto measurement need 1 full 0x8000 symbol cycle to kick in, |
993 | * therefore program initial value for Mvid and Nvid |
994 | */ |
995 | |
996 | REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); |
997 | |
998 | REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); |
999 | |
1000 | REG_UPDATE_2(DP_VID_TIMING, |
1001 | DP_VID_M_N_GEN_EN, 1, |
1002 | DP_VID_N_MUL, n_multiply); |
1003 | } |
1004 | |
1005 | /* set DIG_START to 0x1 to resync FIFO */ |
1006 | |
1007 | REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); |
1008 | |
1009 | /* switch DP encoder to CRTC data */ |
1010 | |
1011 | REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); |
1012 | |
1013 | /* wait 100us for DIG/DP logic to prime |
1014 | * (i.e. a few video lines) |
1015 | */ |
1016 | udelay(100); |
1017 | |
1018 | /* the hardware would start sending video at the start of the next DP |
1019 | * frame (i.e. rising edge of the vblank). |
1020 | * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this |
1021 | * register has no effect on enable transition! HW always guarantees |
1022 | * VID_STREAM enable at start of next frame, and this is not |
1023 | * programmable |
1024 | */ |
1025 | |
1026 | REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); |
1027 | |
1028 | link->dc->link_srv->dp_trace_source_sequence(link, |
1029 | DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); |
1030 | } |
1031 | |
1032 | void enc1_stream_encoder_set_avmute( |
1033 | struct stream_encoder *enc, |
1034 | bool enable) |
1035 | { |
1036 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1037 | unsigned int value = enable ? 1 : 0; |
1038 | |
1039 | REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); |
1040 | } |
1041 | |
1042 | void enc1_reset_hdmi_stream_attribute( |
1043 | struct stream_encoder *enc) |
1044 | { |
1045 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1046 | |
1047 | REG_UPDATE_5(HDMI_CONTROL, |
1048 | HDMI_PACKET_GEN_VERSION, 1, |
1049 | HDMI_KEEPOUT_MODE, 1, |
1050 | HDMI_DEEP_COLOR_ENABLE, 0, |
1051 | HDMI_DATA_SCRAMBLE_EN, 0, |
1052 | HDMI_CLOCK_CHANNEL_RATE, 0); |
1053 | } |
1054 | |
1055 | |
1056 | #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 |
1057 | #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 |
1058 | |
1059 | #include "include/audio_types.h" |
1060 | |
1061 | |
1062 | /* 25.2MHz/1.001*/ |
1063 | /* 25.2MHz/1.001*/ |
1064 | /* 25.2MHz*/ |
1065 | /* 27MHz */ |
1066 | /* 27MHz*1.001*/ |
1067 | /* 27MHz*1.001*/ |
1068 | /* 54MHz*/ |
1069 | /* 54MHz*1.001*/ |
1070 | /* 74.25MHz/1.001*/ |
1071 | /* 74.25MHz*/ |
1072 | /* 148.5MHz/1.001*/ |
1073 | /* 148.5MHz*/ |
1074 | |
1075 | static const struct audio_clock_info audio_clock_info_table[16] = { |
1076 | {2517, 4576, 28125, 7007, 31250, 6864, 28125}, |
1077 | {2518, 4576, 28125, 7007, 31250, 6864, 28125}, |
1078 | {2520, 4096, 25200, 6272, 28000, 6144, 25200}, |
1079 | {2700, 4096, 27000, 6272, 30000, 6144, 27000}, |
1080 | {2702, 4096, 27027, 6272, 30030, 6144, 27027}, |
1081 | {2703, 4096, 27027, 6272, 30030, 6144, 27027}, |
1082 | {5400, 4096, 54000, 6272, 60000, 6144, 54000}, |
1083 | {5405, 4096, 54054, 6272, 60060, 6144, 54054}, |
1084 | {7417, 11648, 210937, 17836, 234375, 11648, 140625}, |
1085 | {7425, 4096, 74250, 6272, 82500, 6144, 74250}, |
1086 | {14835, 11648, 421875, 8918, 234375, 5824, 140625}, |
1087 | {14850, 4096, 148500, 6272, 165000, 6144, 148500}, |
1088 | {29670, 5824, 421875, 4459, 234375, 5824, 281250}, |
1089 | {29700, 3072, 222750, 4704, 247500, 5120, 247500}, |
1090 | {59340, 5824, 843750, 8918, 937500, 5824, 562500}, |
1091 | {59400, 3072, 445500, 9408, 990000, 6144, 594000} |
1092 | }; |
1093 | |
1094 | static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { |
1095 | {2517, 9152, 84375, 7007, 48875, 9152, 56250}, |
1096 | {2518, 9152, 84375, 7007, 48875, 9152, 56250}, |
1097 | {2520, 4096, 37800, 6272, 42000, 6144, 37800}, |
1098 | {2700, 4096, 40500, 6272, 45000, 6144, 40500}, |
1099 | {2702, 8192, 81081, 6272, 45045, 8192, 54054}, |
1100 | {2703, 8192, 81081, 6272, 45045, 8192, 54054}, |
1101 | {5400, 4096, 81000, 6272, 90000, 6144, 81000}, |
1102 | {5405, 4096, 81081, 6272, 90090, 6144, 81081}, |
1103 | {7417, 11648, 316406, 17836, 351562, 11648, 210937}, |
1104 | {7425, 4096, 111375, 6272, 123750, 6144, 111375}, |
1105 | {14835, 11648, 632812, 17836, 703125, 11648, 421875}, |
1106 | {14850, 4096, 222750, 6272, 247500, 6144, 222750}, |
1107 | {29670, 5824, 632812, 8918, 703125, 5824, 421875}, |
1108 | {29700, 4096, 445500, 4704, 371250, 5120, 371250} |
1109 | }; |
1110 | |
1111 | static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { |
1112 | {2517, 4576, 56250, 7007, 62500, 6864, 56250}, |
1113 | {2518, 4576, 56250, 7007, 62500, 6864, 56250}, |
1114 | {2520, 4096, 50400, 6272, 56000, 6144, 50400}, |
1115 | {2700, 4096, 54000, 6272, 60000, 6144, 54000}, |
1116 | {2702, 4096, 54054, 6267, 60060, 8192, 54054}, |
1117 | {2703, 4096, 54054, 6272, 60060, 8192, 54054}, |
1118 | {5400, 4096, 108000, 6272, 120000, 6144, 108000}, |
1119 | {5405, 4096, 108108, 6272, 120120, 6144, 108108}, |
1120 | {7417, 11648, 421875, 17836, 468750, 11648, 281250}, |
1121 | {7425, 4096, 148500, 6272, 165000, 6144, 148500}, |
1122 | {14835, 11648, 843750, 8918, 468750, 11648, 281250}, |
1123 | {14850, 4096, 297000, 6272, 330000, 6144, 297000}, |
1124 | {29670, 5824, 843750, 4459, 468750, 5824, 562500}, |
1125 | {29700, 3072, 445500, 4704, 495000, 5120, 495000} |
1126 | |
1127 | |
1128 | }; |
1129 | |
1130 | static union audio_cea_channels speakers_to_channels( |
1131 | struct audio_speaker_flags speaker_flags) |
1132 | { |
1133 | union audio_cea_channels cea_channels = {0}; |
1134 | |
1135 | /* these are one to one */ |
1136 | cea_channels.channels.FL = speaker_flags.FL_FR; |
1137 | cea_channels.channels.FR = speaker_flags.FL_FR; |
1138 | cea_channels.channels.LFE = speaker_flags.LFE; |
1139 | cea_channels.channels.FC = speaker_flags.FC; |
1140 | |
1141 | /* if Rear Left and Right exist move RC speaker to channel 7 |
1142 | * otherwise to channel 5 |
1143 | */ |
1144 | if (speaker_flags.RL_RR) { |
1145 | cea_channels.channels.RL_RC = speaker_flags.RL_RR; |
1146 | cea_channels.channels.RR = speaker_flags.RL_RR; |
1147 | cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; |
1148 | } else { |
1149 | cea_channels.channels.RL_RC = speaker_flags.RC; |
1150 | } |
1151 | |
1152 | /* FRONT Left Right Center and REAR Left Right Center are exclusive */ |
1153 | if (speaker_flags.FLC_FRC) { |
1154 | cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; |
1155 | cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; |
1156 | } else { |
1157 | cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; |
1158 | cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; |
1159 | } |
1160 | |
1161 | return cea_channels; |
1162 | } |
1163 | |
1164 | void get_audio_clock_info( |
1165 | enum dc_color_depth color_depth, |
1166 | uint32_t crtc_pixel_clock_100Hz, |
1167 | uint32_t actual_pixel_clock_100Hz, |
1168 | struct audio_clock_info *audio_clock_info) |
1169 | { |
1170 | const struct audio_clock_info *clock_info; |
1171 | uint32_t index; |
1172 | uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; |
1173 | uint32_t audio_array_size; |
1174 | |
1175 | switch (color_depth) { |
1176 | case COLOR_DEPTH_161616: |
1177 | clock_info = audio_clock_info_table_48bpc; |
1178 | audio_array_size = ARRAY_SIZE( |
1179 | audio_clock_info_table_48bpc); |
1180 | break; |
1181 | case COLOR_DEPTH_121212: |
1182 | clock_info = audio_clock_info_table_36bpc; |
1183 | audio_array_size = ARRAY_SIZE( |
1184 | audio_clock_info_table_36bpc); |
1185 | break; |
1186 | default: |
1187 | clock_info = audio_clock_info_table; |
1188 | audio_array_size = ARRAY_SIZE( |
1189 | audio_clock_info_table); |
1190 | break; |
1191 | } |
1192 | |
1193 | if (clock_info != NULL) { |
1194 | /* search for exact pixel clock in table */ |
1195 | for (index = 0; index < audio_array_size; index++) { |
1196 | if (clock_info[index].pixel_clock_in_10khz > |
1197 | crtc_pixel_clock_in_10khz) |
1198 | break; /* not match */ |
1199 | else if (clock_info[index].pixel_clock_in_10khz == |
1200 | crtc_pixel_clock_in_10khz) { |
1201 | /* match found */ |
1202 | *audio_clock_info = clock_info[index]; |
1203 | return; |
1204 | } |
1205 | } |
1206 | } |
1207 | |
1208 | /* not found */ |
1209 | if (actual_pixel_clock_100Hz == 0) |
1210 | actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; |
1211 | |
1212 | /* See HDMI spec the table entry under |
1213 | * pixel clock of "Other". */ |
1214 | audio_clock_info->pixel_clock_in_10khz = |
1215 | actual_pixel_clock_100Hz / 100; |
1216 | audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; |
1217 | audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; |
1218 | audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; |
1219 | |
1220 | audio_clock_info->n_32khz = 4096; |
1221 | audio_clock_info->n_44khz = 6272; |
1222 | audio_clock_info->n_48khz = 6144; |
1223 | } |
1224 | |
1225 | static void enc1_se_audio_setup( |
1226 | struct stream_encoder *enc, |
1227 | unsigned int az_inst, |
1228 | struct audio_info *audio_info) |
1229 | { |
1230 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1231 | |
1232 | uint32_t channels = 0; |
1233 | |
1234 | ASSERT(audio_info); |
1235 | if (audio_info == NULL) |
1236 | /* This should not happen.it does so we don't get BSOD*/ |
1237 | return; |
1238 | |
1239 | channels = speakers_to_channels(speaker_flags: audio_info->flags.speaker_flags).all; |
1240 | |
1241 | /* setup the audio stream source select (audio -> dig mapping) */ |
1242 | REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); |
1243 | |
1244 | /* Channel allocation */ |
1245 | REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); |
1246 | } |
1247 | |
1248 | static void enc1_se_setup_hdmi_audio( |
1249 | struct stream_encoder *enc, |
1250 | const struct audio_crtc_info *crtc_info) |
1251 | { |
1252 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1253 | |
1254 | struct audio_clock_info audio_clock_info = {0}; |
1255 | |
1256 | /* HDMI_AUDIO_PACKET_CONTROL */ |
1257 | REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, |
1258 | HDMI_AUDIO_DELAY_EN, 1); |
1259 | |
1260 | /* AFMT_AUDIO_PACKET_CONTROL */ |
1261 | REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); |
1262 | |
1263 | /* AFMT_AUDIO_PACKET_CONTROL2 */ |
1264 | REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, |
1265 | AFMT_AUDIO_LAYOUT_OVRD, 0, |
1266 | AFMT_60958_OSF_OVRD, 0); |
1267 | |
1268 | /* HDMI_ACR_PACKET_CONTROL */ |
1269 | REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, |
1270 | HDMI_ACR_AUTO_SEND, 1, |
1271 | HDMI_ACR_SOURCE, 0, |
1272 | HDMI_ACR_AUDIO_PRIORITY, 0); |
1273 | |
1274 | /* Program audio clock sample/regeneration parameters */ |
1275 | get_audio_clock_info(color_depth: crtc_info->color_depth, |
1276 | crtc_pixel_clock_100Hz: crtc_info->requested_pixel_clock_100Hz, |
1277 | actual_pixel_clock_100Hz: crtc_info->calculated_pixel_clock_100Hz, |
1278 | audio_clock_info: &audio_clock_info); |
1279 | DC_LOG_HW_AUDIO( |
1280 | "\n%s:Input::requested_pixel_clock_100Hz = %d" \ |
1281 | "calculated_pixel_clock_100Hz = %d \n" , __func__, \ |
1282 | crtc_info->requested_pixel_clock_100Hz, \ |
1283 | crtc_info->calculated_pixel_clock_100Hz); |
1284 | |
1285 | /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ |
1286 | REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); |
1287 | |
1288 | /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ |
1289 | REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); |
1290 | |
1291 | /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ |
1292 | REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); |
1293 | |
1294 | /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ |
1295 | REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); |
1296 | |
1297 | /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ |
1298 | REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); |
1299 | |
1300 | /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ |
1301 | REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); |
1302 | |
1303 | /* Video driver cannot know in advance which sample rate will |
1304 | * be used by HD Audio driver |
1305 | * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is |
1306 | * programmed below in interruppt callback |
1307 | */ |
1308 | |
1309 | /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & |
1310 | * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK |
1311 | */ |
1312 | REG_UPDATE_2(AFMT_60958_0, |
1313 | AFMT_60958_CS_CHANNEL_NUMBER_L, 1, |
1314 | AFMT_60958_CS_CLOCK_ACCURACY, 0); |
1315 | |
1316 | /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ |
1317 | REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); |
1318 | |
1319 | /* AFMT_60958_2 now keep this settings until |
1320 | * Programming guide comes out |
1321 | */ |
1322 | REG_UPDATE_6(AFMT_60958_2, |
1323 | AFMT_60958_CS_CHANNEL_NUMBER_2, 3, |
1324 | AFMT_60958_CS_CHANNEL_NUMBER_3, 4, |
1325 | AFMT_60958_CS_CHANNEL_NUMBER_4, 5, |
1326 | AFMT_60958_CS_CHANNEL_NUMBER_5, 6, |
1327 | AFMT_60958_CS_CHANNEL_NUMBER_6, 7, |
1328 | AFMT_60958_CS_CHANNEL_NUMBER_7, 8); |
1329 | } |
1330 | |
1331 | static void enc1_se_setup_dp_audio( |
1332 | struct stream_encoder *enc) |
1333 | { |
1334 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1335 | |
1336 | /* --- DP Audio packet configurations --- */ |
1337 | |
1338 | /* ATP Configuration */ |
1339 | REG_SET(DP_SEC_AUD_N, 0, |
1340 | DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); |
1341 | |
1342 | /* Async/auto-calc timestamp mode */ |
1343 | REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, |
1344 | DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); |
1345 | |
1346 | /* --- The following are the registers |
1347 | * copied from the SetupHDMI --- |
1348 | */ |
1349 | |
1350 | /* AFMT_AUDIO_PACKET_CONTROL */ |
1351 | REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); |
1352 | |
1353 | /* AFMT_AUDIO_PACKET_CONTROL2 */ |
1354 | /* Program the ATP and AIP next */ |
1355 | REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, |
1356 | AFMT_AUDIO_LAYOUT_OVRD, 0, |
1357 | AFMT_60958_OSF_OVRD, 0); |
1358 | |
1359 | /* AFMT_INFOFRAME_CONTROL0 */ |
1360 | REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); |
1361 | |
1362 | /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ |
1363 | REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); |
1364 | } |
1365 | |
1366 | void enc1_se_enable_audio_clock( |
1367 | struct stream_encoder *enc, |
1368 | bool enable) |
1369 | { |
1370 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1371 | |
1372 | if (REG(AFMT_CNTL) == 0) |
1373 | return; /* DCE8/10 does not have this register */ |
1374 | |
1375 | REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); |
1376 | |
1377 | /* wait for AFMT clock to turn on, |
1378 | * expectation: this should complete in 1-2 reads |
1379 | * |
1380 | * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); |
1381 | * |
1382 | * TODO: wait for clock_on does not work well. May need HW |
1383 | * program sequence. But audio seems work normally even without wait |
1384 | * for clock_on status change |
1385 | */ |
1386 | } |
1387 | |
1388 | void enc1_se_enable_dp_audio( |
1389 | struct stream_encoder *enc) |
1390 | { |
1391 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1392 | |
1393 | /* Enable Audio packets */ |
1394 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); |
1395 | |
1396 | /* Program the ATP and AIP next */ |
1397 | REG_UPDATE_2(DP_SEC_CNTL, |
1398 | DP_SEC_ATP_ENABLE, 1, |
1399 | DP_SEC_AIP_ENABLE, 1); |
1400 | |
1401 | /* Program STREAM_ENABLE after all the other enables. */ |
1402 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); |
1403 | } |
1404 | |
1405 | static void enc1_se_disable_dp_audio( |
1406 | struct stream_encoder *enc) |
1407 | { |
1408 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1409 | uint32_t value = 0; |
1410 | |
1411 | /* Disable Audio packets */ |
1412 | REG_UPDATE_5(DP_SEC_CNTL, |
1413 | DP_SEC_ASP_ENABLE, 0, |
1414 | DP_SEC_ATP_ENABLE, 0, |
1415 | DP_SEC_AIP_ENABLE, 0, |
1416 | DP_SEC_ACM_ENABLE, 0, |
1417 | DP_SEC_STREAM_ENABLE, 0); |
1418 | |
1419 | /* This register shared with encoder info frame. Therefore we need to |
1420 | * keep master enabled if at least on of the fields is not 0 |
1421 | */ |
1422 | value = REG_READ(DP_SEC_CNTL); |
1423 | if (value != 0) |
1424 | REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); |
1425 | |
1426 | } |
1427 | |
1428 | void enc1_se_audio_mute_control( |
1429 | struct stream_encoder *enc, |
1430 | bool mute) |
1431 | { |
1432 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1433 | |
1434 | REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); |
1435 | } |
1436 | |
1437 | void enc1_se_dp_audio_setup( |
1438 | struct stream_encoder *enc, |
1439 | unsigned int az_inst, |
1440 | struct audio_info *info) |
1441 | { |
1442 | enc1_se_audio_setup(enc, az_inst, audio_info: info); |
1443 | } |
1444 | |
1445 | void enc1_se_dp_audio_enable( |
1446 | struct stream_encoder *enc) |
1447 | { |
1448 | enc1_se_enable_audio_clock(enc, enable: true); |
1449 | enc1_se_setup_dp_audio(enc); |
1450 | enc1_se_enable_dp_audio(enc); |
1451 | } |
1452 | |
1453 | void enc1_se_dp_audio_disable( |
1454 | struct stream_encoder *enc) |
1455 | { |
1456 | enc1_se_disable_dp_audio(enc); |
1457 | enc1_se_enable_audio_clock(enc, enable: false); |
1458 | } |
1459 | |
1460 | void enc1_se_hdmi_audio_setup( |
1461 | struct stream_encoder *enc, |
1462 | unsigned int az_inst, |
1463 | struct audio_info *info, |
1464 | struct audio_crtc_info *audio_crtc_info) |
1465 | { |
1466 | enc1_se_enable_audio_clock(enc, enable: true); |
1467 | enc1_se_setup_hdmi_audio(enc, crtc_info: audio_crtc_info); |
1468 | enc1_se_audio_setup(enc, az_inst, audio_info: info); |
1469 | } |
1470 | |
1471 | void enc1_se_hdmi_audio_disable( |
1472 | struct stream_encoder *enc) |
1473 | { |
1474 | if (enc->afmt && enc->afmt->funcs->afmt_powerdown) |
1475 | enc->afmt->funcs->afmt_powerdown(enc->afmt); |
1476 | |
1477 | enc1_se_enable_audio_clock(enc, enable: false); |
1478 | } |
1479 | |
1480 | |
1481 | void enc1_setup_stereo_sync( |
1482 | struct stream_encoder *enc, |
1483 | int tg_inst, bool enable) |
1484 | { |
1485 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1486 | REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); |
1487 | REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); |
1488 | } |
1489 | |
1490 | void enc1_dig_connect_to_otg( |
1491 | struct stream_encoder *enc, |
1492 | int tg_inst) |
1493 | { |
1494 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1495 | |
1496 | REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); |
1497 | } |
1498 | |
1499 | unsigned int enc1_dig_source_otg( |
1500 | struct stream_encoder *enc) |
1501 | { |
1502 | uint32_t tg_inst = 0; |
1503 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1504 | |
1505 | REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); |
1506 | |
1507 | return tg_inst; |
1508 | } |
1509 | |
1510 | bool enc1_stream_encoder_dp_get_pixel_format( |
1511 | struct stream_encoder *enc, |
1512 | enum dc_pixel_encoding *encoding, |
1513 | enum dc_color_depth *depth) |
1514 | { |
1515 | uint32_t hw_encoding = 0; |
1516 | uint32_t hw_depth = 0; |
1517 | struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); |
1518 | |
1519 | if (enc == NULL || |
1520 | encoding == NULL || |
1521 | depth == NULL) |
1522 | return false; |
1523 | |
1524 | REG_GET_2(DP_PIXEL_FORMAT, |
1525 | DP_PIXEL_ENCODING, &hw_encoding, |
1526 | DP_COMPONENT_DEPTH, &hw_depth); |
1527 | |
1528 | switch (hw_depth) { |
1529 | case DP_COMPONENT_PIXEL_DEPTH_6BPC: |
1530 | *depth = COLOR_DEPTH_666; |
1531 | break; |
1532 | case DP_COMPONENT_PIXEL_DEPTH_8BPC: |
1533 | *depth = COLOR_DEPTH_888; |
1534 | break; |
1535 | case DP_COMPONENT_PIXEL_DEPTH_10BPC: |
1536 | *depth = COLOR_DEPTH_101010; |
1537 | break; |
1538 | case DP_COMPONENT_PIXEL_DEPTH_12BPC: |
1539 | *depth = COLOR_DEPTH_121212; |
1540 | break; |
1541 | case DP_COMPONENT_PIXEL_DEPTH_16BPC: |
1542 | *depth = COLOR_DEPTH_161616; |
1543 | break; |
1544 | default: |
1545 | *depth = COLOR_DEPTH_UNDEFINED; |
1546 | break; |
1547 | } |
1548 | |
1549 | switch (hw_encoding) { |
1550 | case DP_PIXEL_ENCODING_TYPE_RGB444: |
1551 | *encoding = PIXEL_ENCODING_RGB; |
1552 | break; |
1553 | case DP_PIXEL_ENCODING_TYPE_YCBCR422: |
1554 | *encoding = PIXEL_ENCODING_YCBCR422; |
1555 | break; |
1556 | case DP_PIXEL_ENCODING_TYPE_YCBCR444: |
1557 | case DP_PIXEL_ENCODING_TYPE_Y_ONLY: |
1558 | *encoding = PIXEL_ENCODING_YCBCR444; |
1559 | break; |
1560 | case DP_PIXEL_ENCODING_TYPE_YCBCR420: |
1561 | *encoding = PIXEL_ENCODING_YCBCR420; |
1562 | break; |
1563 | default: |
1564 | *encoding = PIXEL_ENCODING_UNDEFINED; |
1565 | break; |
1566 | } |
1567 | return true; |
1568 | } |
1569 | |
1570 | static const struct stream_encoder_funcs dcn10_str_enc_funcs = { |
1571 | .dp_set_stream_attribute = |
1572 | enc1_stream_encoder_dp_set_stream_attribute, |
1573 | .hdmi_set_stream_attribute = |
1574 | enc1_stream_encoder_hdmi_set_stream_attribute, |
1575 | .dvi_set_stream_attribute = |
1576 | enc1_stream_encoder_dvi_set_stream_attribute, |
1577 | .set_throttled_vcp_size = |
1578 | enc1_stream_encoder_set_throttled_vcp_size, |
1579 | .update_hdmi_info_packets = |
1580 | enc1_stream_encoder_update_hdmi_info_packets, |
1581 | .stop_hdmi_info_packets = |
1582 | enc1_stream_encoder_stop_hdmi_info_packets, |
1583 | .update_dp_info_packets = |
1584 | enc1_stream_encoder_update_dp_info_packets, |
1585 | .send_immediate_sdp_message = |
1586 | enc1_stream_encoder_send_immediate_sdp_message, |
1587 | .stop_dp_info_packets = |
1588 | enc1_stream_encoder_stop_dp_info_packets, |
1589 | .dp_blank = |
1590 | enc1_stream_encoder_dp_blank, |
1591 | .dp_unblank = |
1592 | enc1_stream_encoder_dp_unblank, |
1593 | .audio_mute_control = enc1_se_audio_mute_control, |
1594 | |
1595 | .dp_audio_setup = enc1_se_dp_audio_setup, |
1596 | .dp_audio_enable = enc1_se_dp_audio_enable, |
1597 | .dp_audio_disable = enc1_se_dp_audio_disable, |
1598 | |
1599 | .hdmi_audio_setup = enc1_se_hdmi_audio_setup, |
1600 | .hdmi_audio_disable = enc1_se_hdmi_audio_disable, |
1601 | .setup_stereo_sync = enc1_setup_stereo_sync, |
1602 | .set_avmute = enc1_stream_encoder_set_avmute, |
1603 | .dig_connect_to_otg = enc1_dig_connect_to_otg, |
1604 | .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, |
1605 | .dig_source_otg = enc1_dig_source_otg, |
1606 | |
1607 | .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, |
1608 | }; |
1609 | |
1610 | void dcn10_stream_encoder_construct( |
1611 | struct dcn10_stream_encoder *enc1, |
1612 | struct dc_context *ctx, |
1613 | struct dc_bios *bp, |
1614 | enum engine_id eng_id, |
1615 | const struct dcn10_stream_enc_registers *regs, |
1616 | const struct dcn10_stream_encoder_shift *se_shift, |
1617 | const struct dcn10_stream_encoder_mask *se_mask) |
1618 | { |
1619 | enc1->base.funcs = &dcn10_str_enc_funcs; |
1620 | enc1->base.ctx = ctx; |
1621 | enc1->base.id = eng_id; |
1622 | enc1->base.bp = bp; |
1623 | enc1->regs = regs; |
1624 | enc1->se_shift = se_shift; |
1625 | enc1->se_mask = se_mask; |
1626 | enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA; |
1627 | } |
1628 | |
1629 | |