1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dm_services.h"
28#include "dm_helpers.h"
29#include "core_types.h"
30#include "resource.h"
31#include "dcn30_hwseq.h"
32#include "dccg.h"
33#include "dce/dce_hwseq.h"
34#include "dcn30/dcn30_mpc.h"
35#include "dcn30/dcn30_dpp.h"
36#include "dcn10/dcn10_cm_common.h"
37#include "dcn30/dcn30_cm_common.h"
38#include "reg_helper.h"
39#include "abm.h"
40#include "clk_mgr.h"
41#include "hubp.h"
42#include "dchubbub.h"
43#include "timing_generator.h"
44#include "opp.h"
45#include "ipp.h"
46#include "mpc.h"
47#include "mcif_wb.h"
48#include "dc_dmub_srv.h"
49#include "link_hwss.h"
50#include "dpcd_defs.h"
51#include "dcn20/dcn20_hwseq.h"
52#include "dcn30/dcn30_resource.h"
53#include "link.h"
54#include "dc_state_priv.h"
55
56
57
58#define DC_LOGGER_INIT(logger)
59
60#define CTX \
61 hws->ctx
62#define REG(reg)\
63 hws->regs->reg
64#define DC_LOGGER \
65 dc->ctx->logger
66
67
68#undef FN
69#define FN(reg_name, field_name) \
70 hws->shifts->field_name, hws->masks->field_name
71
72void dcn30_log_color_state(struct dc *dc,
73 struct dc_log_buffer_ctx *log_ctx)
74{
75 struct dc_context *dc_ctx = dc->ctx;
76 struct resource_pool *pool = dc->res_pool;
77 int i;
78
79 DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode"
80 " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode"
81 " GAMUT adjust "
82 "C11 C12 C13 C14 "
83 "C21 C22 C23 C24 "
84 "C31 C32 C33 C34 \n");
85
86 for (i = 0; i < pool->pipe_count; i++) {
87 struct dpp *dpp = pool->dpps[i];
88 struct dcn_dpp_state s = {0};
89
90 dpp->funcs->dpp_read_state(dpp, &s);
91 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
92
93 if (!s.is_enabled)
94 continue;
95
96 DTN_INFO("[%2d]: %7x %13s %8s %11s %10s %15s %10s %9s"
97 " %12s "
98 "%010lld %010lld %010lld %010lld "
99 "%010lld %010lld %010lld %010lld "
100 "%010lld %010lld %010lld %010lld",
101 dpp->inst,
102 s.pre_dgam_mode,
103 (s.pre_dgam_select == 0) ? "sRGB" :
104 ((s.pre_dgam_select == 1) ? "Gamma 2.2" :
105 ((s.pre_dgam_select == 2) ? "Gamma 2.4" :
106 ((s.pre_dgam_select == 3) ? "Gamma 2.6" :
107 ((s.pre_dgam_select == 4) ? "BT.709" :
108 ((s.pre_dgam_select == 5) ? "PQ" :
109 ((s.pre_dgam_select == 6) ? "HLG" :
110 "Unknown")))))),
111 (s.gamcor_mode == 0) ? "Bypass" :
112 ((s.gamcor_mode == 1) ? "RAM A" :
113 "RAM B"),
114 (s.shaper_lut_mode == 1) ? "RAM A" :
115 ((s.shaper_lut_mode == 2) ? "RAM B" :
116 "Bypass"),
117 (s.lut3d_mode == 1) ? "RAM A" :
118 ((s.lut3d_mode == 2) ? "RAM B" :
119 "Bypass"),
120 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
121 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
122 (s.rgam_lut_mode == 0) ? "Bypass" :
123 ((s.rgam_lut_mode == 1) ? "RAM A" :
124 "RAM B"),
125 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
126 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
127 "SW"),
128 s.gamut_remap.temperature_matrix[0].value,
129 s.gamut_remap.temperature_matrix[1].value,
130 s.gamut_remap.temperature_matrix[2].value,
131 s.gamut_remap.temperature_matrix[3].value,
132 s.gamut_remap.temperature_matrix[4].value,
133 s.gamut_remap.temperature_matrix[5].value,
134 s.gamut_remap.temperature_matrix[6].value,
135 s.gamut_remap.temperature_matrix[7].value,
136 s.gamut_remap.temperature_matrix[8].value,
137 s.gamut_remap.temperature_matrix[9].value,
138 s.gamut_remap.temperature_matrix[10].value,
139 s.gamut_remap.temperature_matrix[11].value);
140 DTN_INFO("\n");
141 }
142 DTN_INFO("\n");
143 DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"
144 " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
145 " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"
146 " blnd_lut:%d oscs:%d\n\n",
147 dc->caps.color.dpp.input_lut_shared,
148 dc->caps.color.dpp.icsc,
149 dc->caps.color.dpp.dgam_ram,
150 dc->caps.color.dpp.dgam_rom_caps.srgb,
151 dc->caps.color.dpp.dgam_rom_caps.bt2020,
152 dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
153 dc->caps.color.dpp.dgam_rom_caps.pq,
154 dc->caps.color.dpp.dgam_rom_caps.hlg,
155 dc->caps.color.dpp.post_csc,
156 dc->caps.color.dpp.gamma_corr,
157 dc->caps.color.dpp.dgam_rom_for_yuv,
158 dc->caps.color.dpp.hw_3d_lut,
159 dc->caps.color.dpp.ogam_ram,
160 dc->caps.color.dpp.ocsc);
161
162 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE"
163 " SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT"
164 " GAMUT adjust "
165 "C11 C12 C13 C14 "
166 "C21 C22 C23 C24 "
167 "C31 C32 C33 C34 \n");
168
169 for (i = 0; i < pool->pipe_count; i++) {
170 struct mpcc_state s = {0};
171
172 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
173 mpc3_get_gamut_remap(mpc: pool->mpc, mpcc_id: i, adjust: &s.gamut_remap);
174
175 if (s.opp_id != 0xf)
176 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %11s %11s %16s %11s %10s %9s"
177 " %-12s "
178 "%010lld %010lld %010lld %010lld "
179 "%010lld %010lld %010lld %010lld "
180 "%010lld %010lld %010lld %010lld\n",
181 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
182 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
183 s.idle,
184 (s.shaper_lut_mode == 1) ? "RAM A" :
185 ((s.shaper_lut_mode == 2) ? "RAM B" :
186 "Bypass"),
187 (s.lut3d_mode == 1) ? "RAM A" :
188 ((s.lut3d_mode == 2) ? "RAM B" :
189 "Bypass"),
190 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
191 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
192 (s.rgam_mode == 0) ? "Bypass" :
193 ((s.rgam_mode == 2) ? "RAM" :
194 "Unknown"),
195 (s.rgam_mode == 1) ? "B" : "A",
196 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
197 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
198 "SW"),
199 s.gamut_remap.temperature_matrix[0].value,
200 s.gamut_remap.temperature_matrix[1].value,
201 s.gamut_remap.temperature_matrix[2].value,
202 s.gamut_remap.temperature_matrix[3].value,
203 s.gamut_remap.temperature_matrix[4].value,
204 s.gamut_remap.temperature_matrix[5].value,
205 s.gamut_remap.temperature_matrix[6].value,
206 s.gamut_remap.temperature_matrix[7].value,
207 s.gamut_remap.temperature_matrix[8].value,
208 s.gamut_remap.temperature_matrix[9].value,
209 s.gamut_remap.temperature_matrix[10].value,
210 s.gamut_remap.temperature_matrix[11].value);
211
212 }
213 DTN_INFO("\n");
214 DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
215 dc->caps.color.mpc.gamut_remap,
216 dc->caps.color.mpc.num_3dluts,
217 dc->caps.color.mpc.ogam_ram,
218 dc->caps.color.mpc.ocsc);
219}
220
221bool dcn30_set_blend_lut(
222 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
223{
224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
225 bool result = true;
226 struct pwl_params *blend_lut = NULL;
227
228 if (plane_state->blend_tf) {
229 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
230 blend_lut = &plane_state->blend_tf->pwl;
231 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
232 cm3_helper_translate_curve_to_hw_format(
233 output_tf: plane_state->blend_tf, lut_params: &dpp_base->regamma_params, fixpoint: false);
234 blend_lut = &dpp_base->regamma_params;
235 }
236 }
237 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
238
239 return result;
240}
241
242static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
243 const struct dc_stream_state *stream)
244{
245 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
246 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
247 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
248 bool result = false;
249 int acquired_rmu = 0;
250 int mpcc_id_projected = 0;
251
252 const struct pwl_params *shaper_lut = NULL;
253 //get the shaper lut params
254 if (stream->func_shaper) {
255 if (stream->func_shaper->type == TF_TYPE_HWPWL) {
256 shaper_lut = &stream->func_shaper->pwl;
257 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
258 cm_helper_translate_curve_to_hw_format(ctx: stream->ctx, output_tf: stream->func_shaper,
259 lut_params: &dpp_base->shaper_params, fixpoint: true);
260 shaper_lut = &dpp_base->shaper_params;
261 }
262 }
263
264 if (stream->lut3d_func &&
265 stream->lut3d_func->state.bits.initialized == 1 &&
266 stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
267 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
268 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
269 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
270 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
271 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
272 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
273 if (mpcc_id_projected != mpcc_id)
274 BREAK_TO_DEBUGGER();
275 /* find the reason why logical layer assigned a different
276 * mpcc_id into acquire_post_bldn_3dlut
277 */
278 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
279 stream->lut3d_func->state.bits.rmu_mux_num);
280 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
281 BREAK_TO_DEBUGGER();
282
283 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
284 stream->lut3d_func->state.bits.rmu_mux_num);
285 result = mpc->funcs->program_shaper(mpc, shaper_lut,
286 stream->lut3d_func->state.bits.rmu_mux_num);
287 } else {
288 // loop through the available mux and release the requested mpcc_id
289 mpc->funcs->release_rmu(mpc, mpcc_id);
290 }
291
292 return result;
293}
294
295bool dcn30_set_input_transfer_func(struct dc *dc,
296 struct pipe_ctx *pipe_ctx,
297 const struct dc_plane_state *plane_state)
298{
299 struct dce_hwseq *hws = dc->hwseq;
300 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
301 enum dc_transfer_func_predefined tf;
302 bool result = true;
303 struct pwl_params *params = NULL;
304
305 if (dpp_base == NULL || plane_state == NULL)
306 return false;
307
308 tf = TRANSFER_FUNCTION_UNITY;
309
310 if (plane_state->in_transfer_func &&
311 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
312 tf = plane_state->in_transfer_func->tf;
313
314 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
315
316 if (plane_state->in_transfer_func) {
317 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
318 params = &plane_state->in_transfer_func->pwl;
319 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
320 cm3_helper_translate_curve_to_hw_format(output_tf: plane_state->in_transfer_func,
321 lut_params: &dpp_base->degamma_params, fixpoint: false))
322 params = &dpp_base->degamma_params;
323 }
324
325 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
326
327 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
328 if (dpp_base->funcs->dpp_program_blnd_lut)
329 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
330 if (dpp_base->funcs->dpp_program_shaper_lut &&
331 dpp_base->funcs->dpp_program_3dlut)
332 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
333 }
334
335 return result;
336}
337
338void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)
339{
340 int i = 0;
341 struct dpp_grph_csc_adjustment dpp_adjust;
342 struct mpc_grph_gamut_adjustment mpc_adjust;
343 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
344 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
345
346 memset(&dpp_adjust, 0, sizeof(dpp_adjust));
347 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
348
349 if (pipe_ctx->plane_state &&
350 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
351 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
352 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
353 dpp_adjust.temperature_matrix[i] =
354 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
355 }
356
357 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,
358 &dpp_adjust);
359
360 memset(&mpc_adjust, 0, sizeof(mpc_adjust));
361 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
362
363 if (pipe_ctx->top_pipe == NULL) {
364 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
365 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
366 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
367 mpc_adjust.temperature_matrix[i] =
368 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
369 }
370 }
371
372 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
373}
374
375bool dcn30_set_output_transfer_func(struct dc *dc,
376 struct pipe_ctx *pipe_ctx,
377 const struct dc_stream_state *stream)
378{
379 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
380 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
381 struct pwl_params *params = NULL;
382 bool ret = false;
383
384 /* program OGAM or 3DLUT only for the top pipe*/
385 if (pipe_ctx->top_pipe == NULL) {
386 /*program rmu shaper and 3dlut in MPC*/
387 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
388 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
389 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
390 params = &stream->out_transfer_func->pwl;
391 else if (pipe_ctx->stream->out_transfer_func->type ==
392 TF_TYPE_DISTRIBUTED_POINTS &&
393 cm3_helper_translate_curve_to_hw_format(
394 output_tf: stream->out_transfer_func,
395 lut_params: &mpc->blender_params, fixpoint: false))
396 params = &mpc->blender_params;
397 /* there are no ROM LUTs in OUTGAM */
398 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
399 BREAK_TO_DEBUGGER();
400 }
401 }
402
403 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
404 return ret;
405}
406
407static void dcn30_set_writeback(
408 struct dc *dc,
409 struct dc_writeback_info *wb_info,
410 struct dc_state *context)
411{
412 struct mcif_wb *mcif_wb;
413 struct mcif_buf_params *mcif_buf_params;
414
415 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
416 ASSERT(wb_info->wb_enabled);
417 ASSERT(wb_info->mpcc_inst >= 0);
418 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
419 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
420 mcif_buf_params = &wb_info->mcif_buf_params;
421
422 /* set DWB MPC mux */
423 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
424 wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
425 /* set MCIF_WB buffer and arbitration configuration */
426 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
427 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
428}
429
430void dcn30_update_writeback(
431 struct dc *dc,
432 struct dc_writeback_info *wb_info,
433 struct dc_state *context)
434{
435 struct dwbc *dwb;
436 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
437 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
438 __func__, wb_info->dwb_pipe_inst,\
439 wb_info->mpcc_inst);
440
441 dcn30_set_writeback(dc, wb_info, context);
442
443 /* update DWB */
444 dwb->funcs->update(dwb, &wb_info->dwb_params);
445}
446
447bool dcn30_mmhubbub_warmup(
448 struct dc *dc,
449 unsigned int num_dwb,
450 struct dc_writeback_info *wb_info)
451{
452 struct dwbc *dwb;
453 struct mcif_wb *mcif_wb;
454 struct mcif_warmup_params warmup_params = {0};
455 unsigned int i, i_buf;
456 /*make sure there is no active DWB eanbled */
457 for (i = 0; i < num_dwb; i++) {
458 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
459 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
460 /*can not do warmup while any dwb enabled*/
461 return false;
462 }
463 }
464
465 if (wb_info->mcif_warmup_params.p_vmid == 0)
466 return false;
467
468 /*check whether this is new interface: warmup big buffer once*/
469 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
470 wb_info->mcif_warmup_params.region_size != 0) {
471 /*mmhubbub is shared, so it does not matter which MCIF*/
472 mcif_wb = dc->res_pool->mcif_wb[0];
473 /*warmup a big chunk of VM buffer at once*/
474 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
475 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size;
476 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
477 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
478
479 if (warmup_params.address_increment == 0)
480 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
481
482 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
483 return true;
484 }
485 /*following is the original: warmup each DWB's mcif buffer*/
486 for (i = 0; i < num_dwb; i++) {
487 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
488 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
489 /*warmup is for VM mode only*/
490 if (wb_info[i].mcif_buf_params.p_vmid == 0)
491 return false;
492
493 /* Warmup MCIF_WB */
494 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
495 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
496 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
497 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
498 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
499 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
500 }
501 }
502 return true;
503}
504
505void dcn30_enable_writeback(
506 struct dc *dc,
507 struct dc_writeback_info *wb_info,
508 struct dc_state *context)
509{
510 struct dwbc *dwb;
511 struct mcif_wb *mcif_wb;
512
513 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
514 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
515
516 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
517 __func__, wb_info->dwb_pipe_inst,\
518 wb_info->mpcc_inst);
519
520 /* Warmup interface */
521 dcn30_mmhubbub_warmup(dc, num_dwb: 1, wb_info);
522
523 /* Update writeback pipe */
524 dcn30_set_writeback(dc, wb_info, context);
525
526 /* Enable MCIF_WB */
527 mcif_wb->funcs->enable_mcif(mcif_wb);
528 /* Enable DWB */
529 dwb->funcs->enable(dwb, &wb_info->dwb_params);
530}
531
532void dcn30_disable_writeback(
533 struct dc *dc,
534 unsigned int dwb_pipe_inst)
535{
536 struct dwbc *dwb;
537 struct mcif_wb *mcif_wb;
538
539 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
540 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
541 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
542 DC_LOG_DWB("%s dwb_pipe_inst = %d",\
543 __func__, dwb_pipe_inst);
544
545 /* disable DWB */
546 dwb->funcs->disable(dwb);
547 /* disable MCIF */
548 mcif_wb->funcs->disable_mcif(mcif_wb);
549 /* disable MPC DWB mux */
550 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
551}
552
553void dcn30_program_all_writeback_pipes_in_tree(
554 struct dc *dc,
555 const struct dc_stream_state *stream,
556 struct dc_state *context)
557{
558 struct dc_writeback_info wb_info;
559 struct dwbc *dwb;
560 struct dc_stream_status *stream_status = NULL;
561 int i_wb, i_pipe, i_stream;
562 DC_LOG_DWB("%s", __func__);
563
564 ASSERT(stream);
565 for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
566 if (context->streams[i_stream] == stream) {
567 stream_status = &context->stream_status[i_stream];
568 break;
569 }
570 }
571 ASSERT(stream_status);
572
573 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
574 /* For each writeback pipe */
575 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
576
577 /* copy writeback info to local non-const so mpcc_inst can be set */
578 wb_info = stream->writeback_info[i_wb];
579 if (wb_info.wb_enabled) {
580
581 /* get the MPCC instance for writeback_source_plane */
582 wb_info.mpcc_inst = -1;
583 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
584 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
585
586 if (!pipe_ctx->plane_state)
587 continue;
588
589 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
590 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
591 break;
592 }
593 }
594
595 if (wb_info.mpcc_inst == -1) {
596 /* Disable writeback pipe and disconnect from MPCC
597 * if source plane has been removed
598 */
599 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
600 continue;
601 }
602
603 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
604 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
605 if (dwb->funcs->is_enabled(dwb)) {
606 /* writeback pipe already enabled, only need to update */
607 dc->hwss.update_writeback(dc, &wb_info, context);
608 } else {
609 /* Enable writeback pipe and connect to MPCC */
610 dc->hwss.enable_writeback(dc, &wb_info, context);
611 }
612 } else {
613 /* Disable writeback pipe and disconnect from MPCC */
614 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
615 }
616 }
617}
618
619void dcn30_init_hw(struct dc *dc)
620{
621 struct abm **abms = dc->res_pool->multiple_abms;
622 struct dce_hwseq *hws = dc->hwseq;
623 struct dc_bios *dcb = dc->ctx->dc_bios;
624 struct resource_pool *res_pool = dc->res_pool;
625 int i;
626 int edp_num;
627 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
628 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
629
630 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
631 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
632
633 // Initialize the dccg
634 if (res_pool->dccg->funcs->dccg_init)
635 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
636
637 if (!dcb->funcs->is_accelerated_mode(dcb)) {
638 hws->funcs.bios_golden_init(dc);
639 hws->funcs.disable_vga(dc->hwseq);
640 }
641
642 if (dc->debug.enable_mem_low_power.bits.dmcu) {
643 // Force ERAM to shutdown if DMCU is not enabled
644 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
645 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
646 }
647 }
648
649 // Set default OPTC memory power states
650 if (dc->debug.enable_mem_low_power.bits.optc) {
651 // Shutdown when unassigned and light sleep in VBLANK
652 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
653 }
654
655 if (dc->debug.enable_mem_low_power.bits.vga) {
656 // Power down VGA memory
657 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
658 }
659
660 if (dc->ctx->dc_bios->fw_info_valid) {
661 res_pool->ref_clocks.xtalin_clock_inKhz =
662 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
663
664 if (res_pool->dccg && res_pool->hubbub) {
665
666 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
667 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
668 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
669
670 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
671 res_pool->ref_clocks.dccg_ref_clock_inKhz,
672 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
673 } else {
674 // Not all ASICs have DCCG sw component
675 res_pool->ref_clocks.dccg_ref_clock_inKhz =
676 res_pool->ref_clocks.xtalin_clock_inKhz;
677 res_pool->ref_clocks.dchub_ref_clock_inKhz =
678 res_pool->ref_clocks.xtalin_clock_inKhz;
679 }
680 } else
681 ASSERT_CRITICAL(false);
682
683 for (i = 0; i < dc->link_count; i++) {
684 /* Power up AND update implementation according to the
685 * required signal (which may be different from the
686 * default signal on connector).
687 */
688 struct dc_link *link = dc->links[i];
689
690 link->link_enc->funcs->hw_init(link->link_enc);
691
692 /* Check for enabled DIG to identify enabled display */
693 if (link->link_enc->funcs->is_dig_enabled &&
694 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
695 link->link_status.link_active = true;
696 if (link->link_enc->funcs->fec_is_active &&
697 link->link_enc->funcs->fec_is_active(link->link_enc))
698 link->fec_state = dc_link_fec_enabled;
699 }
700 }
701
702 /* we want to turn off all dp displays before doing detection */
703 dc->link_srv->blank_all_dp_displays(dc);
704
705 if (hws->funcs.enable_power_gating_plane)
706 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
707
708 /* If taking control over from VBIOS, we may want to optimize our first
709 * mode set, so we need to skip powering down pipes until we know which
710 * pipes we want to use.
711 * Otherwise, if taking control is not possible, we need to power
712 * everything down.
713 */
714 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
715 hws->funcs.init_pipes(dc, dc->current_state);
716 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
717 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
718 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
719 }
720
721 /* In headless boot cases, DIG may be turned
722 * on which causes HW/SW discrepancies.
723 * To avoid this, power down hardware on boot
724 * if DIG is turned on and seamless boot not enabled
725 */
726 if (!dc->config.seamless_boot_edp_requested) {
727 struct dc_link *edp_links[MAX_NUM_EDP];
728 struct dc_link *edp_link = NULL;
729
730 dc_get_edp_links(dc, edp_links, edp_num: &edp_num);
731 if (edp_num)
732 edp_link = edp_links[0];
733 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
734 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
735 dc->hwss.edp_backlight_control &&
736 dc->hwss.power_down &&
737 dc->hwss.edp_power_control) {
738 dc->hwss.edp_backlight_control(edp_link, false);
739 dc->hwss.power_down(dc);
740 dc->hwss.edp_power_control(edp_link, false);
741 } else {
742 for (i = 0; i < dc->link_count; i++) {
743 struct dc_link *link = dc->links[i];
744
745 if (link->link_enc->funcs->is_dig_enabled &&
746 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
747 dc->hwss.power_down) {
748 dc->hwss.power_down(dc);
749 break;
750 }
751
752 }
753 }
754 }
755
756 for (i = 0; i < res_pool->audio_count; i++) {
757 struct audio *audio = res_pool->audios[i];
758
759 audio->funcs->hw_init(audio);
760 }
761
762 for (i = 0; i < dc->link_count; i++) {
763 struct dc_link *link = dc->links[i];
764
765 if (link->panel_cntl) {
766 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
767 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
768 }
769 }
770
771 for (i = 0; i < dc->res_pool->pipe_count; i++) {
772 if (abms[i] != NULL)
773 abms[i]->funcs->abm_init(abms[i], backlight, user_level);
774 }
775
776 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
777 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
778
779 if (!dc->debug.disable_clock_gate) {
780 /* enable all DCN clock gating */
781 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
782
783 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
784
785 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
786 }
787
788 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
789 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
790
791 if (dc->clk_mgr->funcs->notify_wm_ranges)
792 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
793
794 //if softmax is enabled then hardmax will be set by a different call
795 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
796 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
797
798 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
799 dc->res_pool->hubbub->funcs->force_pstate_change_control(
800 dc->res_pool->hubbub, false, false);
801 if (dc->res_pool->hubbub->funcs->init_crb)
802 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
803
804 // Get DMCUB capabilities
805 dc_dmub_srv_query_caps_cmd(dc_dmub_srv: dc->ctx->dmub_srv);
806 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
807 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
808}
809
810void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
811{
812 if (pipe_ctx == NULL)
813 return;
814
815 if (dc_is_hdmi_signal(signal: pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {
816 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
817 pipe_ctx->stream_res.stream_enc,
818 enable);
819
820 /* Wait for two frame to make sure AV mute is sent out */
821 if (enable) {
822 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
823 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
824 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
825 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
826 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
827 }
828 }
829}
830
831void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
832{
833 bool is_hdmi_tmds;
834 bool is_dp;
835
836 ASSERT(pipe_ctx->stream);
837
838 if (pipe_ctx->stream_res.stream_enc == NULL)
839 return; /* this is not root pipe */
840
841 is_hdmi_tmds = dc_is_hdmi_tmds_signal(signal: pipe_ctx->stream->signal);
842 is_dp = dc_is_dp_signal(signal: pipe_ctx->stream->signal);
843
844 if (!is_hdmi_tmds && !is_dp)
845 return;
846
847 if (is_hdmi_tmds)
848 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
849 pipe_ctx->stream_res.stream_enc,
850 &pipe_ctx->stream_res.encoder_info_frame);
851 else {
852 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
853 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
854 pipe_ctx->stream_res.stream_enc,
855 &pipe_ctx->stream_res.encoder_info_frame);
856
857 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
858 pipe_ctx->stream_res.stream_enc,
859 &pipe_ctx->stream_res.encoder_info_frame);
860 }
861}
862
863void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
864{
865 struct dc_stream_state *stream = pipe_ctx->stream;
866 struct hubp *hubp = pipe_ctx->plane_res.hubp;
867 bool enable = false;
868 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
869 enum dynamic_metadata_mode mode = dc_is_dp_signal(signal: stream->signal)
870 ? dmdata_dp
871 : dmdata_hdmi;
872
873 /* if using dynamic meta, don't set up generic infopackets */
874 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
875 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
876 enable = true;
877 }
878
879 if (!hubp)
880 return;
881
882 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
883 return;
884
885 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
886 hubp->inst, mode);
887}
888
889bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
890{
891 union dmub_rb_cmd cmd;
892 uint32_t tmr_delay = 0, tmr_scale = 0;
893 struct dc_cursor_attributes cursor_attr;
894 bool cursor_cache_enable = false;
895 struct dc_stream_state *stream = NULL;
896 struct dc_plane_state *plane = NULL;
897
898 if (!dc->ctx->dmub_srv)
899 return false;
900
901 if (enable) {
902 if (dc->current_state) {
903 int i;
904
905 /* First, check no-memory-requests case */
906 for (i = 0; i < dc->current_state->stream_count; i++) {
907 if (dc->current_state->stream_status[i].plane_count)
908 /* Fail eligibility on a visible stream */
909 break;
910 }
911
912 if (i == dc->current_state->stream_count) {
913 /* Enable no-memory-requests case */
914 memset(&cmd, 0, sizeof(cmd));
915 cmd.mall.header.type = DMUB_CMD__MALL;
916 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
917 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
918
919 dc_wake_and_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_NO_WAIT);
920
921 return true;
922 }
923
924 stream = dc->current_state->streams[0];
925 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
926
927 if (stream && plane) {
928 cursor_cache_enable = stream->cursor_position.enable &&
929 plane->address.grph.cursor_cache_addr.quad_part;
930 cursor_attr = stream->cursor_attributes;
931 }
932
933 /*
934 * Second, check MALL eligibility
935 *
936 * single display only, single surface only, 8 and 16 bit formats only, no VM,
937 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
938 *
939 * TODO: When we implement multi-display, PSR displays will be allowed if there is
940 * a non-PSR display present, since in that case we can't do D0i3.2
941 */
942 if (dc->current_state->stream_count == 1 &&
943 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
944 dc->current_state->stream_status[0].plane_count == 1 &&
945 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
946 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
947 plane->address.page_table_base.quad_part == 0 &&
948 dc->hwss.does_plane_fit_in_mall &&
949 dc->hwss.does_plane_fit_in_mall(dc, plane,
950 cursor_cache_enable ? &cursor_attr : NULL)) {
951 unsigned int v_total = stream->adjust.v_total_max ?
952 stream->adjust.v_total_max : stream->timing.v_total;
953 unsigned int refresh_hz = div_u64(dividend: (unsigned long long) stream->timing.pix_clk_100hz *
954 100LL, divisor: (v_total * stream->timing.h_total));
955
956 /*
957 * one frame time in microsec:
958 * Delay_Us = 1000000 / refresh
959 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
960 *
961 * one frame time modified by 'additional timer percent' (p):
962 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
963 * = dynamic_delay_us * (1 + p / 100)
964 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
965 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
966 *
967 * formula for timer duration based on parameters, from regspec:
968 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
969 *
970 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
971 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
972 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
973 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
974 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
975 *
976 * need to round up the result of the division before the subtraction
977 */
978 unsigned int denom = refresh_hz * 6528;
979 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
980
981 tmr_delay = div_u64(dividend: ((1000000LL + 2 * stutter_period * refresh_hz) *
982 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
983 divisor: denom) - 64LL;
984
985 /* In some cases the stutter period is really big (tiny modes) in these
986 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
987 *
988 * We can check if stutter_period is more than 1/10th the frame time to
989 * consider if we can actually meet the range of hysteresis timer
990 */
991 if (stutter_period > 100000/refresh_hz)
992 return false;
993
994 /* scale should be increased until it fits into 6 bits */
995 while (tmr_delay & ~0x3F) {
996 tmr_scale++;
997
998 if (tmr_scale > 3) {
999 /* Delay exceeds range of hysteresis timer */
1000 ASSERT(false);
1001 return false;
1002 }
1003
1004 denom *= 2;
1005 tmr_delay = div_u64(dividend: ((1000000LL + 2 * stutter_period * refresh_hz) *
1006 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
1007 divisor: denom) - 64LL;
1008 }
1009
1010 /* Copy HW cursor */
1011 if (cursor_cache_enable) {
1012 memset(&cmd, 0, sizeof(cmd));
1013 cmd.mall.header.type = DMUB_CMD__MALL;
1014 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
1015 cmd.mall.header.payload_bytes =
1016 sizeof(cmd.mall) - sizeof(cmd.mall.header);
1017
1018 switch (cursor_attr.color_format) {
1019 case CURSOR_MODE_MONO:
1020 cmd.mall.cursor_bpp = 2;
1021 break;
1022 case CURSOR_MODE_COLOR_1BIT_AND:
1023 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
1024 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
1025 cmd.mall.cursor_bpp = 32;
1026 break;
1027
1028 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
1029 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
1030 cmd.mall.cursor_bpp = 64;
1031 break;
1032 }
1033
1034 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
1035 cmd.mall.cursor_copy_dst.quad_part =
1036 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
1037 cmd.mall.cursor_width = cursor_attr.width;
1038 cmd.mall.cursor_height = cursor_attr.height;
1039 cmd.mall.cursor_pitch = cursor_attr.pitch;
1040
1041 dc_wake_and_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
1042
1043 /* Use copied cursor, and it's okay to not switch back */
1044 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
1045 dc_stream_set_cursor_attributes(stream, attributes: &cursor_attr);
1046 }
1047
1048 /* Enable MALL */
1049 memset(&cmd, 0, sizeof(cmd));
1050 cmd.mall.header.type = DMUB_CMD__MALL;
1051 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
1052 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
1053 cmd.mall.tmr_delay = tmr_delay;
1054 cmd.mall.tmr_scale = tmr_scale;
1055 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
1056
1057 dc_wake_and_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_NO_WAIT);
1058
1059 return true;
1060 }
1061 }
1062
1063 /* No applicable optimizations */
1064 return false;
1065 }
1066
1067 /* Disable MALL */
1068 memset(&cmd, 0, sizeof(cmd));
1069 cmd.mall.header.type = DMUB_CMD__MALL;
1070 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
1071 cmd.mall.header.payload_bytes =
1072 sizeof(cmd.mall) - sizeof(cmd.mall.header);
1073
1074 dc_wake_and_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
1075
1076 return true;
1077}
1078
1079bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
1080{
1081 // add meta size?
1082 unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
1083 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
1084 unsigned int mall_size = dc->caps.mall_size_total;
1085 unsigned int cursor_size = 0;
1086
1087 if (dc->debug.mall_size_override)
1088 mall_size = 1024 * 1024 * dc->debug.mall_size_override;
1089
1090 if (cursor_attr) {
1091 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
1092
1093 switch (cursor_attr->color_format) {
1094 case CURSOR_MODE_MONO:
1095 cursor_size /= 2;
1096 break;
1097 case CURSOR_MODE_COLOR_1BIT_AND:
1098 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
1099 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
1100 cursor_size *= 4;
1101 break;
1102
1103 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
1104 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
1105 cursor_size *= 8;
1106 break;
1107 }
1108 }
1109
1110 return (surface_size + cursor_size) < mall_size;
1111}
1112
1113void dcn30_hardware_release(struct dc *dc)
1114{
1115 bool subvp_in_use = false;
1116 uint32_t i;
1117
1118 dc_dmub_srv_p_state_delegate(dc, enable_pstate: false, NULL);
1119 dc_dmub_setup_subvp_dmub_command(dc, context: dc->current_state, enable: false);
1120
1121 /* SubVP treated the same way as FPO. If driver disable and
1122 * we are using a SubVP config, disable and force on DCN side
1123 * to prevent P-State hang on driver enable.
1124 */
1125 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1126 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1127
1128 if (!pipe->stream)
1129 continue;
1130
1131 if (dc_state_get_pipe_subvp_type(state: dc->current_state, pipe_ctx: pipe) == SUBVP_MAIN) {
1132 subvp_in_use = true;
1133 break;
1134 }
1135 }
1136 /* If pstate unsupported, or still supported
1137 * by firmware, force it supported by dcn
1138 */
1139 if (dc->current_state)
1140 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
1141 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
1142 dc->res_pool->hubbub->funcs->force_pstate_change_control)
1143 dc->res_pool->hubbub->funcs->force_pstate_change_control(
1144 dc->res_pool->hubbub, true, true);
1145}
1146
1147void dcn30_set_disp_pattern_generator(const struct dc *dc,
1148 struct pipe_ctx *pipe_ctx,
1149 enum controller_dp_test_pattern test_pattern,
1150 enum controller_dp_color_space color_space,
1151 enum dc_color_depth color_depth,
1152 const struct tg_color *solid_color,
1153 int width, int height, int offset)
1154{
1155 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
1156 color_space, color_depth, solid_color, width, height, offset);
1157}
1158
1159void dcn30_prepare_bandwidth(struct dc *dc,
1160 struct dc_state *context)
1161{
1162 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {
1163 dc->optimized_required = true;
1164 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1165 }
1166
1167 if (dc->clk_mgr->dc_mode_softmax_enabled)
1168 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1169 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1170 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1171
1172 dcn20_prepare_bandwidth(dc, context);
1173
1174 if (!dc->clk_mgr->clks.fw_based_mclk_switching)
1175 dc_dmub_srv_p_state_delegate(dc, enable_pstate: false, context);
1176}
1177

source code of linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c