1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2009 Nokia Corporation |
4 | * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> |
5 | * |
6 | * Some code and ideas taken from drivers/video/omap/ driver |
7 | * by Imre Deak. |
8 | */ |
9 | |
10 | #define DSS_SUBSYS_NAME "DSS" |
11 | |
12 | #include <linux/debugfs.h> |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/module.h> |
16 | #include <linux/io.h> |
17 | #include <linux/export.h> |
18 | #include <linux/err.h> |
19 | #include <linux/delay.h> |
20 | #include <linux/seq_file.h> |
21 | #include <linux/clk.h> |
22 | #include <linux/pinctrl/consumer.h> |
23 | #include <linux/platform_device.h> |
24 | #include <linux/pm_runtime.h> |
25 | #include <linux/property.h> |
26 | #include <linux/gfp.h> |
27 | #include <linux/sizes.h> |
28 | #include <linux/mfd/syscon.h> |
29 | #include <linux/regmap.h> |
30 | #include <linux/of.h> |
31 | #include <linux/of_platform.h> |
32 | #include <linux/of_graph.h> |
33 | #include <linux/regulator/consumer.h> |
34 | #include <linux/suspend.h> |
35 | #include <linux/component.h> |
36 | #include <linux/sys_soc.h> |
37 | |
38 | #include "omapdss.h" |
39 | #include "dss.h" |
40 | |
41 | struct dss_reg { |
42 | u16 idx; |
43 | }; |
44 | |
45 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) |
46 | |
47 | #define DSS_REVISION DSS_REG(0x0000) |
48 | #define DSS_SYSCONFIG DSS_REG(0x0010) |
49 | #define DSS_SYSSTATUS DSS_REG(0x0014) |
50 | #define DSS_CONTROL DSS_REG(0x0040) |
51 | #define DSS_SDI_CONTROL DSS_REG(0x0044) |
52 | #define DSS_PLL_CONTROL DSS_REG(0x0048) |
53 | #define DSS_SDI_STATUS DSS_REG(0x005C) |
54 | |
55 | #define REG_GET(dss, idx, start, end) \ |
56 | FLD_GET(dss_read_reg(dss, idx), start, end) |
57 | |
58 | #define REG_FLD_MOD(dss, idx, val, start, end) \ |
59 | dss_write_reg(dss, idx, \ |
60 | FLD_MOD(dss_read_reg(dss, idx), val, start, end)) |
61 | |
62 | struct dss_ops { |
63 | int (*dpi_select_source)(struct dss_device *dss, int port, |
64 | enum omap_channel channel); |
65 | int (*select_lcd_source)(struct dss_device *dss, |
66 | enum omap_channel channel, |
67 | enum dss_clk_source clk_src); |
68 | }; |
69 | |
70 | struct dss_features { |
71 | enum dss_model model; |
72 | u8 fck_div_max; |
73 | unsigned int fck_freq_max; |
74 | u8 dss_fck_multiplier; |
75 | const char *parent_clk_name; |
76 | const enum omap_display_type *ports; |
77 | int num_ports; |
78 | const enum omap_dss_output_id *outputs; |
79 | const struct dss_ops *ops; |
80 | struct dss_reg_field dispc_clk_switch; |
81 | bool has_lcd_clk_src; |
82 | }; |
83 | |
84 | static const char * const dss_generic_clk_source_names[] = { |
85 | [DSS_CLK_SRC_FCK] = "FCK" , |
86 | [DSS_CLK_SRC_PLL1_1] = "PLL1:1" , |
87 | [DSS_CLK_SRC_PLL1_2] = "PLL1:2" , |
88 | [DSS_CLK_SRC_PLL1_3] = "PLL1:3" , |
89 | [DSS_CLK_SRC_PLL2_1] = "PLL2:1" , |
90 | [DSS_CLK_SRC_PLL2_2] = "PLL2:2" , |
91 | [DSS_CLK_SRC_PLL2_3] = "PLL2:3" , |
92 | [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL" , |
93 | }; |
94 | |
95 | static inline void dss_write_reg(struct dss_device *dss, |
96 | const struct dss_reg idx, u32 val) |
97 | { |
98 | __raw_writel(val, addr: dss->base + idx.idx); |
99 | } |
100 | |
101 | static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg idx) |
102 | { |
103 | return __raw_readl(addr: dss->base + idx.idx); |
104 | } |
105 | |
106 | #define SR(dss, reg) \ |
107 | dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg) |
108 | #define RR(dss, reg) \ |
109 | dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)]) |
110 | |
111 | static void dss_save_context(struct dss_device *dss) |
112 | { |
113 | DSSDBG("dss_save_context\n" ); |
114 | |
115 | SR(dss, CONTROL); |
116 | |
117 | if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { |
118 | SR(dss, SDI_CONTROL); |
119 | SR(dss, PLL_CONTROL); |
120 | } |
121 | |
122 | dss->ctx_valid = true; |
123 | |
124 | DSSDBG("context saved\n" ); |
125 | } |
126 | |
127 | static void dss_restore_context(struct dss_device *dss) |
128 | { |
129 | DSSDBG("dss_restore_context\n" ); |
130 | |
131 | if (!dss->ctx_valid) |
132 | return; |
133 | |
134 | RR(dss, CONTROL); |
135 | |
136 | if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { |
137 | RR(dss, SDI_CONTROL); |
138 | RR(dss, PLL_CONTROL); |
139 | } |
140 | |
141 | DSSDBG("context restored\n" ); |
142 | } |
143 | |
144 | #undef SR |
145 | #undef RR |
146 | |
147 | void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable) |
148 | { |
149 | unsigned int shift; |
150 | unsigned int val; |
151 | |
152 | if (!pll->dss->syscon_pll_ctrl) |
153 | return; |
154 | |
155 | val = !enable; |
156 | |
157 | switch (pll->id) { |
158 | case DSS_PLL_VIDEO1: |
159 | shift = 0; |
160 | break; |
161 | case DSS_PLL_VIDEO2: |
162 | shift = 1; |
163 | break; |
164 | case DSS_PLL_HDMI: |
165 | shift = 2; |
166 | break; |
167 | default: |
168 | DSSERR("illegal DSS PLL ID %d\n" , pll->id); |
169 | return; |
170 | } |
171 | |
172 | regmap_update_bits(map: pll->dss->syscon_pll_ctrl, |
173 | reg: pll->dss->syscon_pll_ctrl_offset, |
174 | mask: 1 << shift, val: val << shift); |
175 | } |
176 | |
177 | static int dss_ctrl_pll_set_control_mux(struct dss_device *dss, |
178 | enum dss_clk_source clk_src, |
179 | enum omap_channel channel) |
180 | { |
181 | unsigned int shift, val; |
182 | |
183 | if (!dss->syscon_pll_ctrl) |
184 | return -EINVAL; |
185 | |
186 | switch (channel) { |
187 | case OMAP_DSS_CHANNEL_LCD: |
188 | shift = 3; |
189 | |
190 | switch (clk_src) { |
191 | case DSS_CLK_SRC_PLL1_1: |
192 | val = 0; break; |
193 | case DSS_CLK_SRC_HDMI_PLL: |
194 | val = 1; break; |
195 | default: |
196 | DSSERR("error in PLL mux config for LCD\n" ); |
197 | return -EINVAL; |
198 | } |
199 | |
200 | break; |
201 | case OMAP_DSS_CHANNEL_LCD2: |
202 | shift = 5; |
203 | |
204 | switch (clk_src) { |
205 | case DSS_CLK_SRC_PLL1_3: |
206 | val = 0; break; |
207 | case DSS_CLK_SRC_PLL2_3: |
208 | val = 1; break; |
209 | case DSS_CLK_SRC_HDMI_PLL: |
210 | val = 2; break; |
211 | default: |
212 | DSSERR("error in PLL mux config for LCD2\n" ); |
213 | return -EINVAL; |
214 | } |
215 | |
216 | break; |
217 | case OMAP_DSS_CHANNEL_LCD3: |
218 | shift = 7; |
219 | |
220 | switch (clk_src) { |
221 | case DSS_CLK_SRC_PLL2_1: |
222 | val = 0; break; |
223 | case DSS_CLK_SRC_PLL1_3: |
224 | val = 1; break; |
225 | case DSS_CLK_SRC_HDMI_PLL: |
226 | val = 2; break; |
227 | default: |
228 | DSSERR("error in PLL mux config for LCD3\n" ); |
229 | return -EINVAL; |
230 | } |
231 | |
232 | break; |
233 | default: |
234 | DSSERR("error in PLL mux config\n" ); |
235 | return -EINVAL; |
236 | } |
237 | |
238 | regmap_update_bits(map: dss->syscon_pll_ctrl, reg: dss->syscon_pll_ctrl_offset, |
239 | mask: 0x3 << shift, val: val << shift); |
240 | |
241 | return 0; |
242 | } |
243 | |
244 | void dss_sdi_init(struct dss_device *dss, int datapairs) |
245 | { |
246 | u32 l; |
247 | |
248 | BUG_ON(datapairs > 3 || datapairs < 1); |
249 | |
250 | l = dss_read_reg(dss, DSS_SDI_CONTROL); |
251 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ |
252 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ |
253 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ |
254 | dss_write_reg(dss, DSS_SDI_CONTROL, val: l); |
255 | |
256 | l = dss_read_reg(dss, DSS_PLL_CONTROL); |
257 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ |
258 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ |
259 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ |
260 | dss_write_reg(dss, DSS_PLL_CONTROL, val: l); |
261 | } |
262 | |
263 | int dss_sdi_enable(struct dss_device *dss) |
264 | { |
265 | unsigned long timeout; |
266 | |
267 | dispc_pck_free_enable(dispc: dss->dispc, enable: 1); |
268 | |
269 | /* Reset SDI PLL */ |
270 | REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ |
271 | udelay(1); /* wait 2x PCLK */ |
272 | |
273 | /* Lock SDI PLL */ |
274 | REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ |
275 | |
276 | /* Waiting for PLL lock request to complete */ |
277 | timeout = jiffies + msecs_to_jiffies(m: 500); |
278 | while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) { |
279 | if (time_after_eq(jiffies, timeout)) { |
280 | DSSERR("PLL lock request timed out\n" ); |
281 | goto err1; |
282 | } |
283 | } |
284 | |
285 | /* Clearing PLL_GO bit */ |
286 | REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28); |
287 | |
288 | /* Waiting for PLL to lock */ |
289 | timeout = jiffies + msecs_to_jiffies(m: 500); |
290 | while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) { |
291 | if (time_after_eq(jiffies, timeout)) { |
292 | DSSERR("PLL lock timed out\n" ); |
293 | goto err1; |
294 | } |
295 | } |
296 | |
297 | dispc_lcd_enable_signal(dispc: dss->dispc, enable: 1); |
298 | |
299 | /* Waiting for SDI reset to complete */ |
300 | timeout = jiffies + msecs_to_jiffies(m: 500); |
301 | while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) { |
302 | if (time_after_eq(jiffies, timeout)) { |
303 | DSSERR("SDI reset timed out\n" ); |
304 | goto err2; |
305 | } |
306 | } |
307 | |
308 | return 0; |
309 | |
310 | err2: |
311 | dispc_lcd_enable_signal(dispc: dss->dispc, enable: 0); |
312 | err1: |
313 | /* Reset SDI PLL */ |
314 | REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
315 | |
316 | dispc_pck_free_enable(dispc: dss->dispc, enable: 0); |
317 | |
318 | return -ETIMEDOUT; |
319 | } |
320 | |
321 | void dss_sdi_disable(struct dss_device *dss) |
322 | { |
323 | dispc_lcd_enable_signal(dispc: dss->dispc, enable: 0); |
324 | |
325 | dispc_pck_free_enable(dispc: dss->dispc, enable: 0); |
326 | |
327 | /* Reset SDI PLL */ |
328 | REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
329 | } |
330 | |
331 | const char *dss_get_clk_source_name(enum dss_clk_source clk_src) |
332 | { |
333 | return dss_generic_clk_source_names[clk_src]; |
334 | } |
335 | |
336 | static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s) |
337 | { |
338 | const char *fclk_name; |
339 | unsigned long fclk_rate; |
340 | |
341 | if (dss_runtime_get(dss)) |
342 | return; |
343 | |
344 | seq_printf(m: s, fmt: "- DSS -\n" ); |
345 | |
346 | fclk_name = dss_get_clk_source_name(clk_src: DSS_CLK_SRC_FCK); |
347 | fclk_rate = clk_get_rate(clk: dss->dss_clk); |
348 | |
349 | seq_printf(m: s, fmt: "%s = %lu\n" , |
350 | fclk_name, |
351 | fclk_rate); |
352 | |
353 | dss_runtime_put(dss); |
354 | } |
355 | |
356 | static int dss_dump_regs(struct seq_file *s, void *p) |
357 | { |
358 | struct dss_device *dss = s->private; |
359 | |
360 | #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r)) |
361 | |
362 | if (dss_runtime_get(dss)) |
363 | return 0; |
364 | |
365 | DUMPREG(dss, DSS_REVISION); |
366 | DUMPREG(dss, DSS_SYSCONFIG); |
367 | DUMPREG(dss, DSS_SYSSTATUS); |
368 | DUMPREG(dss, DSS_CONTROL); |
369 | |
370 | if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { |
371 | DUMPREG(dss, DSS_SDI_CONTROL); |
372 | DUMPREG(dss, DSS_PLL_CONTROL); |
373 | DUMPREG(dss, DSS_SDI_STATUS); |
374 | } |
375 | |
376 | dss_runtime_put(dss); |
377 | #undef DUMPREG |
378 | return 0; |
379 | } |
380 | |
381 | static int dss_debug_dump_clocks(struct seq_file *s, void *p) |
382 | { |
383 | struct dss_device *dss = s->private; |
384 | |
385 | dss_dump_clocks(dss, s); |
386 | dispc_dump_clocks(dispc: dss->dispc, s); |
387 | return 0; |
388 | } |
389 | |
390 | static int dss_get_channel_index(enum omap_channel channel) |
391 | { |
392 | switch (channel) { |
393 | case OMAP_DSS_CHANNEL_LCD: |
394 | return 0; |
395 | case OMAP_DSS_CHANNEL_LCD2: |
396 | return 1; |
397 | case OMAP_DSS_CHANNEL_LCD3: |
398 | return 2; |
399 | default: |
400 | WARN_ON(1); |
401 | return 0; |
402 | } |
403 | } |
404 | |
405 | static void dss_select_dispc_clk_source(struct dss_device *dss, |
406 | enum dss_clk_source clk_src) |
407 | { |
408 | int b; |
409 | |
410 | /* |
411 | * We always use PRCM clock as the DISPC func clock, except on DSS3, |
412 | * where we don't have separate DISPC and LCD clock sources. |
413 | */ |
414 | if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK)) |
415 | return; |
416 | |
417 | switch (clk_src) { |
418 | case DSS_CLK_SRC_FCK: |
419 | b = 0; |
420 | break; |
421 | case DSS_CLK_SRC_PLL1_1: |
422 | b = 1; |
423 | break; |
424 | case DSS_CLK_SRC_PLL2_1: |
425 | b = 2; |
426 | break; |
427 | default: |
428 | BUG(); |
429 | return; |
430 | } |
431 | |
432 | REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ |
433 | dss->feat->dispc_clk_switch.start, |
434 | dss->feat->dispc_clk_switch.end); |
435 | |
436 | dss->dispc_clk_source = clk_src; |
437 | } |
438 | |
439 | void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module, |
440 | enum dss_clk_source clk_src) |
441 | { |
442 | int b, pos; |
443 | |
444 | switch (clk_src) { |
445 | case DSS_CLK_SRC_FCK: |
446 | b = 0; |
447 | break; |
448 | case DSS_CLK_SRC_PLL1_2: |
449 | BUG_ON(dsi_module != 0); |
450 | b = 1; |
451 | break; |
452 | case DSS_CLK_SRC_PLL2_2: |
453 | BUG_ON(dsi_module != 1); |
454 | b = 1; |
455 | break; |
456 | default: |
457 | BUG(); |
458 | return; |
459 | } |
460 | |
461 | pos = dsi_module == 0 ? 1 : 10; |
462 | REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ |
463 | |
464 | dss->dsi_clk_source[dsi_module] = clk_src; |
465 | } |
466 | |
467 | static int dss_lcd_clk_mux_dra7(struct dss_device *dss, |
468 | enum omap_channel channel, |
469 | enum dss_clk_source clk_src) |
470 | { |
471 | const u8 ctrl_bits[] = { |
472 | [OMAP_DSS_CHANNEL_LCD] = 0, |
473 | [OMAP_DSS_CHANNEL_LCD2] = 12, |
474 | [OMAP_DSS_CHANNEL_LCD3] = 19, |
475 | }; |
476 | |
477 | u8 ctrl_bit = ctrl_bits[channel]; |
478 | int r; |
479 | |
480 | if (clk_src == DSS_CLK_SRC_FCK) { |
481 | /* LCDx_CLK_SWITCH */ |
482 | REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); |
483 | return -EINVAL; |
484 | } |
485 | |
486 | r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel); |
487 | if (r) |
488 | return r; |
489 | |
490 | REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); |
491 | |
492 | return 0; |
493 | } |
494 | |
495 | static int dss_lcd_clk_mux_omap5(struct dss_device *dss, |
496 | enum omap_channel channel, |
497 | enum dss_clk_source clk_src) |
498 | { |
499 | const u8 ctrl_bits[] = { |
500 | [OMAP_DSS_CHANNEL_LCD] = 0, |
501 | [OMAP_DSS_CHANNEL_LCD2] = 12, |
502 | [OMAP_DSS_CHANNEL_LCD3] = 19, |
503 | }; |
504 | const enum dss_clk_source allowed_plls[] = { |
505 | [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, |
506 | [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, |
507 | [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, |
508 | }; |
509 | |
510 | u8 ctrl_bit = ctrl_bits[channel]; |
511 | |
512 | if (clk_src == DSS_CLK_SRC_FCK) { |
513 | /* LCDx_CLK_SWITCH */ |
514 | REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); |
515 | return -EINVAL; |
516 | } |
517 | |
518 | if (WARN_ON(allowed_plls[channel] != clk_src)) |
519 | return -EINVAL; |
520 | |
521 | REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); |
522 | |
523 | return 0; |
524 | } |
525 | |
526 | static int dss_lcd_clk_mux_omap4(struct dss_device *dss, |
527 | enum omap_channel channel, |
528 | enum dss_clk_source clk_src) |
529 | { |
530 | const u8 ctrl_bits[] = { |
531 | [OMAP_DSS_CHANNEL_LCD] = 0, |
532 | [OMAP_DSS_CHANNEL_LCD2] = 12, |
533 | }; |
534 | const enum dss_clk_source allowed_plls[] = { |
535 | [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, |
536 | [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, |
537 | }; |
538 | |
539 | u8 ctrl_bit = ctrl_bits[channel]; |
540 | |
541 | if (clk_src == DSS_CLK_SRC_FCK) { |
542 | /* LCDx_CLK_SWITCH */ |
543 | REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); |
544 | return 0; |
545 | } |
546 | |
547 | if (WARN_ON(allowed_plls[channel] != clk_src)) |
548 | return -EINVAL; |
549 | |
550 | REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); |
551 | |
552 | return 0; |
553 | } |
554 | |
555 | void dss_select_lcd_clk_source(struct dss_device *dss, |
556 | enum omap_channel channel, |
557 | enum dss_clk_source clk_src) |
558 | { |
559 | int idx = dss_get_channel_index(channel); |
560 | int r; |
561 | |
562 | if (!dss->feat->has_lcd_clk_src) { |
563 | dss_select_dispc_clk_source(dss, clk_src); |
564 | dss->lcd_clk_source[idx] = clk_src; |
565 | return; |
566 | } |
567 | |
568 | r = dss->feat->ops->select_lcd_source(dss, channel, clk_src); |
569 | if (r) |
570 | return; |
571 | |
572 | dss->lcd_clk_source[idx] = clk_src; |
573 | } |
574 | |
575 | enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss) |
576 | { |
577 | return dss->dispc_clk_source; |
578 | } |
579 | |
580 | enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss, |
581 | int dsi_module) |
582 | { |
583 | return dss->dsi_clk_source[dsi_module]; |
584 | } |
585 | |
586 | enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss, |
587 | enum omap_channel channel) |
588 | { |
589 | if (dss->feat->has_lcd_clk_src) { |
590 | int idx = dss_get_channel_index(channel); |
591 | return dss->lcd_clk_source[idx]; |
592 | } else { |
593 | /* LCD_CLK source is the same as DISPC_FCLK source for |
594 | * OMAP2 and OMAP3 */ |
595 | return dss->dispc_clk_source; |
596 | } |
597 | } |
598 | |
599 | bool dss_div_calc(struct dss_device *dss, unsigned long pck, |
600 | unsigned long fck_min, dss_div_calc_func func, void *data) |
601 | { |
602 | int fckd, fckd_start, fckd_stop; |
603 | unsigned long fck; |
604 | unsigned long fck_hw_max; |
605 | unsigned long fckd_hw_max; |
606 | unsigned long prate; |
607 | unsigned int m; |
608 | |
609 | fck_hw_max = dss->feat->fck_freq_max; |
610 | |
611 | if (dss->parent_clk == NULL) { |
612 | unsigned int pckd; |
613 | |
614 | pckd = fck_hw_max / pck; |
615 | |
616 | fck = pck * pckd; |
617 | |
618 | fck = clk_round_rate(clk: dss->dss_clk, rate: fck); |
619 | |
620 | return func(fck, data); |
621 | } |
622 | |
623 | fckd_hw_max = dss->feat->fck_div_max; |
624 | |
625 | m = dss->feat->dss_fck_multiplier; |
626 | prate = clk_get_rate(clk: dss->parent_clk); |
627 | |
628 | fck_min = fck_min ? fck_min : 1; |
629 | |
630 | fckd_start = min(prate * m / fck_min, fckd_hw_max); |
631 | fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); |
632 | |
633 | for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { |
634 | fck = DIV_ROUND_UP(prate, fckd) * m; |
635 | |
636 | if (func(fck, data)) |
637 | return true; |
638 | } |
639 | |
640 | return false; |
641 | } |
642 | |
643 | int dss_set_fck_rate(struct dss_device *dss, unsigned long rate) |
644 | { |
645 | int r; |
646 | |
647 | DSSDBG("set fck to %lu\n" , rate); |
648 | |
649 | r = clk_set_rate(clk: dss->dss_clk, rate); |
650 | if (r) |
651 | return r; |
652 | |
653 | dss->dss_clk_rate = clk_get_rate(clk: dss->dss_clk); |
654 | |
655 | WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu" , |
656 | dss->dss_clk_rate, rate); |
657 | |
658 | return 0; |
659 | } |
660 | |
661 | unsigned long dss_get_dispc_clk_rate(struct dss_device *dss) |
662 | { |
663 | return dss->dss_clk_rate; |
664 | } |
665 | |
666 | unsigned long dss_get_max_fck_rate(struct dss_device *dss) |
667 | { |
668 | return dss->feat->fck_freq_max; |
669 | } |
670 | |
671 | static int dss_setup_default_clock(struct dss_device *dss) |
672 | { |
673 | unsigned long max_dss_fck, prate; |
674 | unsigned long fck; |
675 | unsigned int fck_div; |
676 | int r; |
677 | |
678 | max_dss_fck = dss->feat->fck_freq_max; |
679 | |
680 | if (dss->parent_clk == NULL) { |
681 | fck = clk_round_rate(clk: dss->dss_clk, rate: max_dss_fck); |
682 | } else { |
683 | prate = clk_get_rate(clk: dss->parent_clk); |
684 | |
685 | fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier, |
686 | max_dss_fck); |
687 | fck = DIV_ROUND_UP(prate, fck_div) |
688 | * dss->feat->dss_fck_multiplier; |
689 | } |
690 | |
691 | r = dss_set_fck_rate(dss, rate: fck); |
692 | if (r) |
693 | return r; |
694 | |
695 | return 0; |
696 | } |
697 | |
698 | void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type) |
699 | { |
700 | int l = 0; |
701 | |
702 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) |
703 | l = 0; |
704 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) |
705 | l = 1; |
706 | else |
707 | BUG(); |
708 | |
709 | /* venc out selection. 0 = comp, 1 = svideo */ |
710 | REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6); |
711 | } |
712 | |
713 | void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable) |
714 | { |
715 | /* DAC Power-Down Control */ |
716 | REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5); |
717 | } |
718 | |
719 | void dss_select_hdmi_venc_clk_source(struct dss_device *dss, |
720 | enum dss_hdmi_venc_clk_source_select src) |
721 | { |
722 | enum omap_dss_output_id outputs; |
723 | |
724 | outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; |
725 | |
726 | /* Complain about invalid selections */ |
727 | WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC)); |
728 | WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI)); |
729 | |
730 | /* Select only if we have options */ |
731 | if ((outputs & OMAP_DSS_OUTPUT_VENC) && |
732 | (outputs & OMAP_DSS_OUTPUT_HDMI)) |
733 | /* VENC_HDMI_SWITCH */ |
734 | REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15); |
735 | } |
736 | |
737 | static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int port, |
738 | enum omap_channel channel) |
739 | { |
740 | if (channel != OMAP_DSS_CHANNEL_LCD) |
741 | return -EINVAL; |
742 | |
743 | return 0; |
744 | } |
745 | |
746 | static int dss_dpi_select_source_omap4(struct dss_device *dss, int port, |
747 | enum omap_channel channel) |
748 | { |
749 | int val; |
750 | |
751 | switch (channel) { |
752 | case OMAP_DSS_CHANNEL_LCD2: |
753 | val = 0; |
754 | break; |
755 | case OMAP_DSS_CHANNEL_DIGIT: |
756 | val = 1; |
757 | break; |
758 | default: |
759 | return -EINVAL; |
760 | } |
761 | |
762 | REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17); |
763 | |
764 | return 0; |
765 | } |
766 | |
767 | static int dss_dpi_select_source_omap5(struct dss_device *dss, int port, |
768 | enum omap_channel channel) |
769 | { |
770 | int val; |
771 | |
772 | switch (channel) { |
773 | case OMAP_DSS_CHANNEL_LCD: |
774 | val = 1; |
775 | break; |
776 | case OMAP_DSS_CHANNEL_LCD2: |
777 | val = 2; |
778 | break; |
779 | case OMAP_DSS_CHANNEL_LCD3: |
780 | val = 3; |
781 | break; |
782 | case OMAP_DSS_CHANNEL_DIGIT: |
783 | val = 0; |
784 | break; |
785 | default: |
786 | return -EINVAL; |
787 | } |
788 | |
789 | REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16); |
790 | |
791 | return 0; |
792 | } |
793 | |
794 | static int dss_dpi_select_source_dra7xx(struct dss_device *dss, int port, |
795 | enum omap_channel channel) |
796 | { |
797 | switch (port) { |
798 | case 0: |
799 | return dss_dpi_select_source_omap5(dss, port, channel); |
800 | case 1: |
801 | if (channel != OMAP_DSS_CHANNEL_LCD2) |
802 | return -EINVAL; |
803 | break; |
804 | case 2: |
805 | if (channel != OMAP_DSS_CHANNEL_LCD3) |
806 | return -EINVAL; |
807 | break; |
808 | default: |
809 | return -EINVAL; |
810 | } |
811 | |
812 | return 0; |
813 | } |
814 | |
815 | int dss_dpi_select_source(struct dss_device *dss, int port, |
816 | enum omap_channel channel) |
817 | { |
818 | return dss->feat->ops->dpi_select_source(dss, port, channel); |
819 | } |
820 | |
821 | static int dss_get_clocks(struct dss_device *dss) |
822 | { |
823 | struct clk *clk; |
824 | |
825 | clk = devm_clk_get(dev: &dss->pdev->dev, id: "fck" ); |
826 | if (IS_ERR(ptr: clk)) { |
827 | DSSERR("can't get clock fck\n" ); |
828 | return PTR_ERR(ptr: clk); |
829 | } |
830 | |
831 | dss->dss_clk = clk; |
832 | |
833 | if (dss->feat->parent_clk_name) { |
834 | clk = clk_get(NULL, id: dss->feat->parent_clk_name); |
835 | if (IS_ERR(ptr: clk)) { |
836 | DSSERR("Failed to get %s\n" , |
837 | dss->feat->parent_clk_name); |
838 | return PTR_ERR(ptr: clk); |
839 | } |
840 | } else { |
841 | clk = NULL; |
842 | } |
843 | |
844 | dss->parent_clk = clk; |
845 | |
846 | return 0; |
847 | } |
848 | |
849 | static void dss_put_clocks(struct dss_device *dss) |
850 | { |
851 | if (dss->parent_clk) |
852 | clk_put(clk: dss->parent_clk); |
853 | } |
854 | |
855 | int dss_runtime_get(struct dss_device *dss) |
856 | { |
857 | int r; |
858 | |
859 | DSSDBG("dss_runtime_get\n" ); |
860 | |
861 | r = pm_runtime_get_sync(dev: &dss->pdev->dev); |
862 | if (WARN_ON(r < 0)) { |
863 | pm_runtime_put_noidle(dev: &dss->pdev->dev); |
864 | return r; |
865 | } |
866 | return 0; |
867 | } |
868 | |
869 | void dss_runtime_put(struct dss_device *dss) |
870 | { |
871 | int r; |
872 | |
873 | DSSDBG("dss_runtime_put\n" ); |
874 | |
875 | r = pm_runtime_put_sync(dev: &dss->pdev->dev); |
876 | WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); |
877 | } |
878 | |
879 | struct dss_device *dss_get_device(struct device *dev) |
880 | { |
881 | return dev_get_drvdata(dev); |
882 | } |
883 | |
884 | /* DEBUGFS */ |
885 | #if defined(CONFIG_OMAP2_DSS_DEBUGFS) |
886 | static int dss_initialize_debugfs(struct dss_device *dss) |
887 | { |
888 | struct dentry *dir; |
889 | |
890 | dir = debugfs_create_dir("omapdss" , NULL); |
891 | if (IS_ERR(dir)) |
892 | return PTR_ERR(dir); |
893 | |
894 | dss->debugfs.root = dir; |
895 | |
896 | return 0; |
897 | } |
898 | |
899 | static void dss_uninitialize_debugfs(struct dss_device *dss) |
900 | { |
901 | debugfs_remove_recursive(dss->debugfs.root); |
902 | } |
903 | |
904 | struct dss_debugfs_entry { |
905 | struct dentry *dentry; |
906 | int (*show_fn)(struct seq_file *s, void *data); |
907 | void *data; |
908 | }; |
909 | |
910 | static int dss_debug_open(struct inode *inode, struct file *file) |
911 | { |
912 | struct dss_debugfs_entry *entry = inode->i_private; |
913 | |
914 | return single_open(file, entry->show_fn, entry->data); |
915 | } |
916 | |
917 | static const struct file_operations dss_debug_fops = { |
918 | .open = dss_debug_open, |
919 | .read = seq_read, |
920 | .llseek = seq_lseek, |
921 | .release = single_release, |
922 | }; |
923 | |
924 | struct dss_debugfs_entry * |
925 | dss_debugfs_create_file(struct dss_device *dss, const char *name, |
926 | int (*show_fn)(struct seq_file *s, void *data), |
927 | void *data) |
928 | { |
929 | struct dss_debugfs_entry *entry; |
930 | |
931 | entry = kzalloc(sizeof(*entry), GFP_KERNEL); |
932 | if (!entry) |
933 | return ERR_PTR(-ENOMEM); |
934 | |
935 | entry->show_fn = show_fn; |
936 | entry->data = data; |
937 | entry->dentry = debugfs_create_file(name, 0444, dss->debugfs.root, |
938 | entry, &dss_debug_fops); |
939 | |
940 | return entry; |
941 | } |
942 | |
943 | void dss_debugfs_remove_file(struct dss_debugfs_entry *entry) |
944 | { |
945 | if (IS_ERR_OR_NULL(entry)) |
946 | return; |
947 | |
948 | debugfs_remove(entry->dentry); |
949 | kfree(entry); |
950 | } |
951 | |
952 | #else /* CONFIG_OMAP2_DSS_DEBUGFS */ |
953 | static inline int dss_initialize_debugfs(struct dss_device *dss) |
954 | { |
955 | return 0; |
956 | } |
957 | static inline void dss_uninitialize_debugfs(struct dss_device *dss) |
958 | { |
959 | } |
960 | #endif /* CONFIG_OMAP2_DSS_DEBUGFS */ |
961 | |
962 | static const struct dss_ops dss_ops_omap2_omap3 = { |
963 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
964 | }; |
965 | |
966 | static const struct dss_ops dss_ops_omap4 = { |
967 | .dpi_select_source = &dss_dpi_select_source_omap4, |
968 | .select_lcd_source = &dss_lcd_clk_mux_omap4, |
969 | }; |
970 | |
971 | static const struct dss_ops dss_ops_omap5 = { |
972 | .dpi_select_source = &dss_dpi_select_source_omap5, |
973 | .select_lcd_source = &dss_lcd_clk_mux_omap5, |
974 | }; |
975 | |
976 | static const struct dss_ops dss_ops_dra7 = { |
977 | .dpi_select_source = &dss_dpi_select_source_dra7xx, |
978 | .select_lcd_source = &dss_lcd_clk_mux_dra7, |
979 | }; |
980 | |
981 | static const enum omap_display_type omap2plus_ports[] = { |
982 | OMAP_DISPLAY_TYPE_DPI, |
983 | }; |
984 | |
985 | static const enum omap_display_type omap34xx_ports[] = { |
986 | OMAP_DISPLAY_TYPE_DPI, |
987 | OMAP_DISPLAY_TYPE_SDI, |
988 | }; |
989 | |
990 | static const enum omap_display_type dra7xx_ports[] = { |
991 | OMAP_DISPLAY_TYPE_DPI, |
992 | OMAP_DISPLAY_TYPE_DPI, |
993 | OMAP_DISPLAY_TYPE_DPI, |
994 | }; |
995 | |
996 | static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { |
997 | /* OMAP_DSS_CHANNEL_LCD */ |
998 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, |
999 | |
1000 | /* OMAP_DSS_CHANNEL_DIGIT */ |
1001 | OMAP_DSS_OUTPUT_VENC, |
1002 | }; |
1003 | |
1004 | static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = { |
1005 | /* OMAP_DSS_CHANNEL_LCD */ |
1006 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | |
1007 | OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1, |
1008 | |
1009 | /* OMAP_DSS_CHANNEL_DIGIT */ |
1010 | OMAP_DSS_OUTPUT_VENC, |
1011 | }; |
1012 | |
1013 | static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = { |
1014 | /* OMAP_DSS_CHANNEL_LCD */ |
1015 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | |
1016 | OMAP_DSS_OUTPUT_DSI1, |
1017 | |
1018 | /* OMAP_DSS_CHANNEL_DIGIT */ |
1019 | OMAP_DSS_OUTPUT_VENC, |
1020 | }; |
1021 | |
1022 | static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = { |
1023 | /* OMAP_DSS_CHANNEL_LCD */ |
1024 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, |
1025 | }; |
1026 | |
1027 | static const enum omap_dss_output_id omap4_dss_supported_outputs[] = { |
1028 | /* OMAP_DSS_CHANNEL_LCD */ |
1029 | OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1, |
1030 | |
1031 | /* OMAP_DSS_CHANNEL_DIGIT */ |
1032 | OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI, |
1033 | |
1034 | /* OMAP_DSS_CHANNEL_LCD2 */ |
1035 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | |
1036 | OMAP_DSS_OUTPUT_DSI2, |
1037 | }; |
1038 | |
1039 | static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { |
1040 | /* OMAP_DSS_CHANNEL_LCD */ |
1041 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | |
1042 | OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2, |
1043 | |
1044 | /* OMAP_DSS_CHANNEL_DIGIT */ |
1045 | OMAP_DSS_OUTPUT_HDMI, |
1046 | |
1047 | /* OMAP_DSS_CHANNEL_LCD2 */ |
1048 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | |
1049 | OMAP_DSS_OUTPUT_DSI1, |
1050 | |
1051 | /* OMAP_DSS_CHANNEL_LCD3 */ |
1052 | OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI | |
1053 | OMAP_DSS_OUTPUT_DSI2, |
1054 | }; |
1055 | |
1056 | static const struct dss_features omap24xx_dss_feats = { |
1057 | .model = DSS_MODEL_OMAP2, |
1058 | /* |
1059 | * fck div max is really 16, but the divider range has gaps. The range |
1060 | * from 1 to 6 has no gaps, so let's use that as a max. |
1061 | */ |
1062 | .fck_div_max = 6, |
1063 | .fck_freq_max = 133000000, |
1064 | .dss_fck_multiplier = 2, |
1065 | .parent_clk_name = "core_ck" , |
1066 | .ports = omap2plus_ports, |
1067 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
1068 | .outputs = omap2_dss_supported_outputs, |
1069 | .ops = &dss_ops_omap2_omap3, |
1070 | .dispc_clk_switch = { .start: 0, .end: 0 }, |
1071 | .has_lcd_clk_src = false, |
1072 | }; |
1073 | |
1074 | static const struct dss_features omap34xx_dss_feats = { |
1075 | .model = DSS_MODEL_OMAP3, |
1076 | .fck_div_max = 16, |
1077 | .fck_freq_max = 173000000, |
1078 | .dss_fck_multiplier = 2, |
1079 | .parent_clk_name = "dpll4_ck" , |
1080 | .ports = omap34xx_ports, |
1081 | .outputs = omap3430_dss_supported_outputs, |
1082 | .num_ports = ARRAY_SIZE(omap34xx_ports), |
1083 | .ops = &dss_ops_omap2_omap3, |
1084 | .dispc_clk_switch = { .start: 0, .end: 0 }, |
1085 | .has_lcd_clk_src = false, |
1086 | }; |
1087 | |
1088 | static const struct dss_features omap3630_dss_feats = { |
1089 | .model = DSS_MODEL_OMAP3, |
1090 | .fck_div_max = 31, |
1091 | .fck_freq_max = 173000000, |
1092 | .dss_fck_multiplier = 1, |
1093 | .parent_clk_name = "dpll4_ck" , |
1094 | .ports = omap2plus_ports, |
1095 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
1096 | .outputs = omap3630_dss_supported_outputs, |
1097 | .ops = &dss_ops_omap2_omap3, |
1098 | .dispc_clk_switch = { .start: 0, .end: 0 }, |
1099 | .has_lcd_clk_src = false, |
1100 | }; |
1101 | |
1102 | static const struct dss_features omap44xx_dss_feats = { |
1103 | .model = DSS_MODEL_OMAP4, |
1104 | .fck_div_max = 32, |
1105 | .fck_freq_max = 186000000, |
1106 | .dss_fck_multiplier = 1, |
1107 | .parent_clk_name = "dpll_per_x2_ck" , |
1108 | .ports = omap2plus_ports, |
1109 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
1110 | .outputs = omap4_dss_supported_outputs, |
1111 | .ops = &dss_ops_omap4, |
1112 | .dispc_clk_switch = { .start: 9, .end: 8 }, |
1113 | .has_lcd_clk_src = true, |
1114 | }; |
1115 | |
1116 | static const struct dss_features omap54xx_dss_feats = { |
1117 | .model = DSS_MODEL_OMAP5, |
1118 | .fck_div_max = 64, |
1119 | .fck_freq_max = 209250000, |
1120 | .dss_fck_multiplier = 1, |
1121 | .parent_clk_name = "dpll_per_x2_ck" , |
1122 | .ports = omap2plus_ports, |
1123 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
1124 | .outputs = omap5_dss_supported_outputs, |
1125 | .ops = &dss_ops_omap5, |
1126 | .dispc_clk_switch = { .start: 9, .end: 7 }, |
1127 | .has_lcd_clk_src = true, |
1128 | }; |
1129 | |
1130 | static const struct dss_features am43xx_dss_feats = { |
1131 | .model = DSS_MODEL_OMAP3, |
1132 | .fck_div_max = 0, |
1133 | .fck_freq_max = 200000000, |
1134 | .dss_fck_multiplier = 0, |
1135 | .parent_clk_name = NULL, |
1136 | .ports = omap2plus_ports, |
1137 | .num_ports = ARRAY_SIZE(omap2plus_ports), |
1138 | .outputs = am43xx_dss_supported_outputs, |
1139 | .ops = &dss_ops_omap2_omap3, |
1140 | .dispc_clk_switch = { .start: 0, .end: 0 }, |
1141 | .has_lcd_clk_src = true, |
1142 | }; |
1143 | |
1144 | static const struct dss_features dra7xx_dss_feats = { |
1145 | .model = DSS_MODEL_DRA7, |
1146 | .fck_div_max = 64, |
1147 | .fck_freq_max = 209250000, |
1148 | .dss_fck_multiplier = 1, |
1149 | .parent_clk_name = "dpll_per_x2_ck" , |
1150 | .ports = dra7xx_ports, |
1151 | .num_ports = ARRAY_SIZE(dra7xx_ports), |
1152 | .outputs = omap5_dss_supported_outputs, |
1153 | .ops = &dss_ops_dra7, |
1154 | .dispc_clk_switch = { .start: 9, .end: 7 }, |
1155 | .has_lcd_clk_src = true, |
1156 | }; |
1157 | |
1158 | static void __dss_uninit_ports(struct dss_device *dss, unsigned int num_ports) |
1159 | { |
1160 | struct platform_device *pdev = dss->pdev; |
1161 | struct device_node *parent = pdev->dev.of_node; |
1162 | struct device_node *port; |
1163 | unsigned int i; |
1164 | |
1165 | for (i = 0; i < num_ports; i++) { |
1166 | port = of_graph_get_port_by_id(node: parent, id: i); |
1167 | if (!port) |
1168 | continue; |
1169 | |
1170 | switch (dss->feat->ports[i]) { |
1171 | case OMAP_DISPLAY_TYPE_DPI: |
1172 | dpi_uninit_port(port); |
1173 | break; |
1174 | case OMAP_DISPLAY_TYPE_SDI: |
1175 | sdi_uninit_port(port); |
1176 | break; |
1177 | default: |
1178 | break; |
1179 | } |
1180 | of_node_put(node: port); |
1181 | } |
1182 | } |
1183 | |
1184 | static int dss_init_ports(struct dss_device *dss) |
1185 | { |
1186 | struct platform_device *pdev = dss->pdev; |
1187 | struct device_node *parent = pdev->dev.of_node; |
1188 | struct device_node *port; |
1189 | unsigned int i; |
1190 | int r; |
1191 | |
1192 | for (i = 0; i < dss->feat->num_ports; i++) { |
1193 | port = of_graph_get_port_by_id(node: parent, id: i); |
1194 | if (!port) |
1195 | continue; |
1196 | |
1197 | switch (dss->feat->ports[i]) { |
1198 | case OMAP_DISPLAY_TYPE_DPI: |
1199 | r = dpi_init_port(dss, pdev, port, dss_model: dss->feat->model); |
1200 | if (r) |
1201 | goto error; |
1202 | break; |
1203 | |
1204 | case OMAP_DISPLAY_TYPE_SDI: |
1205 | r = sdi_init_port(dss, pdev, port); |
1206 | if (r) |
1207 | goto error; |
1208 | break; |
1209 | |
1210 | default: |
1211 | break; |
1212 | } |
1213 | of_node_put(node: port); |
1214 | } |
1215 | |
1216 | return 0; |
1217 | |
1218 | error: |
1219 | of_node_put(node: port); |
1220 | __dss_uninit_ports(dss, num_ports: i); |
1221 | return r; |
1222 | } |
1223 | |
1224 | static void dss_uninit_ports(struct dss_device *dss) |
1225 | { |
1226 | __dss_uninit_ports(dss, num_ports: dss->feat->num_ports); |
1227 | } |
1228 | |
1229 | static int dss_video_pll_probe(struct dss_device *dss) |
1230 | { |
1231 | struct platform_device *pdev = dss->pdev; |
1232 | struct device_node *np = pdev->dev.of_node; |
1233 | struct regulator *pll_regulator; |
1234 | int r; |
1235 | |
1236 | if (!np) |
1237 | return 0; |
1238 | |
1239 | if (of_property_read_bool(np, propname: "syscon-pll-ctrl" )) { |
1240 | dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, |
1241 | property: "syscon-pll-ctrl" ); |
1242 | if (IS_ERR(ptr: dss->syscon_pll_ctrl)) { |
1243 | dev_err(&pdev->dev, |
1244 | "failed to get syscon-pll-ctrl regmap\n" ); |
1245 | return PTR_ERR(ptr: dss->syscon_pll_ctrl); |
1246 | } |
1247 | |
1248 | if (of_property_read_u32_index(np, propname: "syscon-pll-ctrl" , index: 1, |
1249 | out_value: &dss->syscon_pll_ctrl_offset)) { |
1250 | dev_err(&pdev->dev, |
1251 | "failed to get syscon-pll-ctrl offset\n" ); |
1252 | return -EINVAL; |
1253 | } |
1254 | } |
1255 | |
1256 | pll_regulator = devm_regulator_get(dev: &pdev->dev, id: "vdda_video" ); |
1257 | if (IS_ERR(ptr: pll_regulator)) { |
1258 | r = PTR_ERR(ptr: pll_regulator); |
1259 | |
1260 | switch (r) { |
1261 | case -ENOENT: |
1262 | pll_regulator = NULL; |
1263 | break; |
1264 | |
1265 | case -EPROBE_DEFER: |
1266 | return -EPROBE_DEFER; |
1267 | |
1268 | default: |
1269 | DSSERR("can't get DPLL VDDA regulator\n" ); |
1270 | return r; |
1271 | } |
1272 | } |
1273 | |
1274 | if (of_property_match_string(np, propname: "reg-names" , string: "pll1" ) >= 0) { |
1275 | dss->video1_pll = dss_video_pll_init(dss, pdev, id: 0, |
1276 | regulator: pll_regulator); |
1277 | if (IS_ERR(ptr: dss->video1_pll)) |
1278 | return PTR_ERR(ptr: dss->video1_pll); |
1279 | } |
1280 | |
1281 | if (of_property_match_string(np, propname: "reg-names" , string: "pll2" ) >= 0) { |
1282 | dss->video2_pll = dss_video_pll_init(dss, pdev, id: 1, |
1283 | regulator: pll_regulator); |
1284 | if (IS_ERR(ptr: dss->video2_pll)) { |
1285 | dss_video_pll_uninit(pll: dss->video1_pll); |
1286 | return PTR_ERR(ptr: dss->video2_pll); |
1287 | } |
1288 | } |
1289 | |
1290 | return 0; |
1291 | } |
1292 | |
1293 | /* DSS HW IP initialisation */ |
1294 | static const struct of_device_id dss_of_match[] = { |
1295 | { .compatible = "ti,omap2-dss" , .data = &omap24xx_dss_feats }, |
1296 | { .compatible = "ti,omap3-dss" , .data = &omap3630_dss_feats }, |
1297 | { .compatible = "ti,omap4-dss" , .data = &omap44xx_dss_feats }, |
1298 | { .compatible = "ti,omap5-dss" , .data = &omap54xx_dss_feats }, |
1299 | { .compatible = "ti,dra7-dss" , .data = &dra7xx_dss_feats }, |
1300 | {}, |
1301 | }; |
1302 | MODULE_DEVICE_TABLE(of, dss_of_match); |
1303 | |
1304 | static const struct soc_device_attribute dss_soc_devices[] = { |
1305 | { .machine = "OMAP3430/3530" , .data = &omap34xx_dss_feats }, |
1306 | { .machine = "AM35??" , .data = &omap34xx_dss_feats }, |
1307 | { .family = "AM43xx" , .data = &am43xx_dss_feats }, |
1308 | { /* sentinel */ } |
1309 | }; |
1310 | |
1311 | static int dss_bind(struct device *dev) |
1312 | { |
1313 | struct dss_device *dss = dev_get_drvdata(dev); |
1314 | struct platform_device *drm_pdev; |
1315 | struct dss_pdata pdata; |
1316 | int r; |
1317 | |
1318 | r = component_bind_all(parent: dev, NULL); |
1319 | if (r) |
1320 | return r; |
1321 | |
1322 | pm_set_vt_switch(0); |
1323 | |
1324 | pdata.dss = dss; |
1325 | drm_pdev = platform_device_register_data(NULL, name: "omapdrm" , id: 0, |
1326 | data: &pdata, size: sizeof(pdata)); |
1327 | if (IS_ERR(ptr: drm_pdev)) { |
1328 | component_unbind_all(parent: dev, NULL); |
1329 | return PTR_ERR(ptr: drm_pdev); |
1330 | } |
1331 | |
1332 | dss->drm_pdev = drm_pdev; |
1333 | |
1334 | return 0; |
1335 | } |
1336 | |
1337 | static void dss_unbind(struct device *dev) |
1338 | { |
1339 | struct dss_device *dss = dev_get_drvdata(dev); |
1340 | |
1341 | platform_device_unregister(dss->drm_pdev); |
1342 | |
1343 | component_unbind_all(parent: dev, NULL); |
1344 | } |
1345 | |
1346 | static const struct component_master_ops dss_component_ops = { |
1347 | .bind = dss_bind, |
1348 | .unbind = dss_unbind, |
1349 | }; |
1350 | |
1351 | struct dss_component_match_data { |
1352 | struct device *dev; |
1353 | struct component_match **match; |
1354 | }; |
1355 | |
1356 | static int dss_add_child_component(struct device *dev, void *data) |
1357 | { |
1358 | struct dss_component_match_data *cmatch = data; |
1359 | struct component_match **match = cmatch->match; |
1360 | |
1361 | /* |
1362 | * HACK |
1363 | * We don't have a working driver for rfbi, so skip it here always. |
1364 | * Otherwise dss will never get probed successfully, as it will wait |
1365 | * for rfbi to get probed. |
1366 | */ |
1367 | if (strstr(dev_name(dev), "rfbi" )) |
1368 | return 0; |
1369 | |
1370 | /* |
1371 | * Handle possible interconnect target modules defined within the DSS. |
1372 | * The DSS components can be children of an interconnect target module |
1373 | * after the device tree has been updated for the module data. |
1374 | * See also omapdss_boot_init() for compatible fixup. |
1375 | */ |
1376 | if (strstr(dev_name(dev), "target-module" )) |
1377 | return device_for_each_child(dev, data: cmatch, |
1378 | fn: dss_add_child_component); |
1379 | |
1380 | component_match_add(parent: cmatch->dev, matchptr: match, compare: component_compare_dev, compare_data: dev); |
1381 | |
1382 | return 0; |
1383 | } |
1384 | |
1385 | static int dss_probe_hardware(struct dss_device *dss) |
1386 | { |
1387 | u32 rev; |
1388 | int r; |
1389 | |
1390 | r = dss_runtime_get(dss); |
1391 | if (r) |
1392 | return r; |
1393 | |
1394 | dss->dss_clk_rate = clk_get_rate(clk: dss->dss_clk); |
1395 | |
1396 | /* Select DPLL */ |
1397 | REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0); |
1398 | |
1399 | dss_select_dispc_clk_source(dss, clk_src: DSS_CLK_SRC_FCK); |
1400 | |
1401 | #ifdef CONFIG_OMAP2_DSS_VENC |
1402 | REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */ |
1403 | REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
1404 | REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
1405 | #endif |
1406 | dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK; |
1407 | dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK; |
1408 | dss->dispc_clk_source = DSS_CLK_SRC_FCK; |
1409 | dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK; |
1410 | dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK; |
1411 | |
1412 | rev = dss_read_reg(dss, DSS_REVISION); |
1413 | pr_info("OMAP DSS rev %d.%d\n" , FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
1414 | |
1415 | dss_runtime_put(dss); |
1416 | |
1417 | return 0; |
1418 | } |
1419 | |
1420 | static int dss_probe(struct platform_device *pdev) |
1421 | { |
1422 | const struct soc_device_attribute *soc; |
1423 | struct dss_component_match_data cmatch; |
1424 | struct component_match *match = NULL; |
1425 | struct dss_device *dss; |
1426 | int r; |
1427 | |
1428 | dss = kzalloc(size: sizeof(*dss), GFP_KERNEL); |
1429 | if (!dss) |
1430 | return -ENOMEM; |
1431 | |
1432 | dss->pdev = pdev; |
1433 | platform_set_drvdata(pdev, data: dss); |
1434 | |
1435 | r = dma_set_coherent_mask(dev: &pdev->dev, DMA_BIT_MASK(32)); |
1436 | if (r) { |
1437 | dev_err(&pdev->dev, "Failed to set the DMA mask\n" ); |
1438 | goto err_free_dss; |
1439 | } |
1440 | |
1441 | /* |
1442 | * The various OMAP3-based SoCs can't be told apart using the compatible |
1443 | * string, use SoC device matching. |
1444 | */ |
1445 | soc = soc_device_match(matches: dss_soc_devices); |
1446 | if (soc) |
1447 | dss->feat = soc->data; |
1448 | else |
1449 | dss->feat = device_get_match_data(dev: &pdev->dev); |
1450 | |
1451 | /* Map I/O registers, get and setup clocks. */ |
1452 | dss->base = devm_platform_ioremap_resource(pdev, index: 0); |
1453 | if (IS_ERR(ptr: dss->base)) { |
1454 | r = PTR_ERR(ptr: dss->base); |
1455 | goto err_free_dss; |
1456 | } |
1457 | |
1458 | r = dss_get_clocks(dss); |
1459 | if (r) |
1460 | goto err_free_dss; |
1461 | |
1462 | r = dss_setup_default_clock(dss); |
1463 | if (r) |
1464 | goto err_put_clocks; |
1465 | |
1466 | /* Setup the video PLLs and the DPI and SDI ports. */ |
1467 | r = dss_video_pll_probe(dss); |
1468 | if (r) |
1469 | goto err_put_clocks; |
1470 | |
1471 | r = dss_init_ports(dss); |
1472 | if (r) |
1473 | goto err_uninit_plls; |
1474 | |
1475 | /* Enable runtime PM and probe the hardware. */ |
1476 | pm_runtime_enable(dev: &pdev->dev); |
1477 | |
1478 | r = dss_probe_hardware(dss); |
1479 | if (r) |
1480 | goto err_pm_runtime_disable; |
1481 | |
1482 | /* Initialize debugfs. */ |
1483 | r = dss_initialize_debugfs(dss); |
1484 | if (r) |
1485 | goto err_pm_runtime_disable; |
1486 | |
1487 | dss->debugfs.clk = dss_debugfs_create_file(dss, name: "clk" , |
1488 | show_fn: dss_debug_dump_clocks, data: dss); |
1489 | dss->debugfs.dss = dss_debugfs_create_file(dss, name: "dss" , show_fn: dss_dump_regs, |
1490 | data: dss); |
1491 | |
1492 | /* Add all the child devices as components. */ |
1493 | r = of_platform_populate(root: pdev->dev.of_node, NULL, NULL, parent: &pdev->dev); |
1494 | if (r) |
1495 | goto err_uninit_debugfs; |
1496 | |
1497 | omapdss_gather_components(dev: &pdev->dev); |
1498 | |
1499 | cmatch.dev = &pdev->dev; |
1500 | cmatch.match = &match; |
1501 | device_for_each_child(dev: &pdev->dev, data: &cmatch, fn: dss_add_child_component); |
1502 | |
1503 | r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); |
1504 | if (r) |
1505 | goto err_of_depopulate; |
1506 | |
1507 | return 0; |
1508 | |
1509 | err_of_depopulate: |
1510 | of_platform_depopulate(parent: &pdev->dev); |
1511 | |
1512 | err_uninit_debugfs: |
1513 | dss_debugfs_remove_file(entry: dss->debugfs.clk); |
1514 | dss_debugfs_remove_file(entry: dss->debugfs.dss); |
1515 | dss_uninitialize_debugfs(dss); |
1516 | |
1517 | err_pm_runtime_disable: |
1518 | pm_runtime_disable(dev: &pdev->dev); |
1519 | dss_uninit_ports(dss); |
1520 | |
1521 | err_uninit_plls: |
1522 | if (dss->video1_pll) |
1523 | dss_video_pll_uninit(pll: dss->video1_pll); |
1524 | if (dss->video2_pll) |
1525 | dss_video_pll_uninit(pll: dss->video2_pll); |
1526 | |
1527 | err_put_clocks: |
1528 | dss_put_clocks(dss); |
1529 | |
1530 | err_free_dss: |
1531 | kfree(objp: dss); |
1532 | |
1533 | return r; |
1534 | } |
1535 | |
1536 | static void dss_remove(struct platform_device *pdev) |
1537 | { |
1538 | struct dss_device *dss = platform_get_drvdata(pdev); |
1539 | |
1540 | of_platform_depopulate(parent: &pdev->dev); |
1541 | |
1542 | component_master_del(&pdev->dev, &dss_component_ops); |
1543 | |
1544 | dss_debugfs_remove_file(entry: dss->debugfs.clk); |
1545 | dss_debugfs_remove_file(entry: dss->debugfs.dss); |
1546 | dss_uninitialize_debugfs(dss); |
1547 | |
1548 | pm_runtime_disable(dev: &pdev->dev); |
1549 | |
1550 | dss_uninit_ports(dss); |
1551 | |
1552 | if (dss->video1_pll) |
1553 | dss_video_pll_uninit(pll: dss->video1_pll); |
1554 | |
1555 | if (dss->video2_pll) |
1556 | dss_video_pll_uninit(pll: dss->video2_pll); |
1557 | |
1558 | dss_put_clocks(dss); |
1559 | |
1560 | kfree(objp: dss); |
1561 | } |
1562 | |
1563 | static void dss_shutdown(struct platform_device *pdev) |
1564 | { |
1565 | DSSDBG("shutdown\n" ); |
1566 | } |
1567 | |
1568 | static __maybe_unused int dss_runtime_suspend(struct device *dev) |
1569 | { |
1570 | struct dss_device *dss = dev_get_drvdata(dev); |
1571 | |
1572 | dss_save_context(dss); |
1573 | dss_set_min_bus_tput(dev, tput: 0); |
1574 | |
1575 | pinctrl_pm_select_sleep_state(dev); |
1576 | |
1577 | return 0; |
1578 | } |
1579 | |
1580 | static __maybe_unused int dss_runtime_resume(struct device *dev) |
1581 | { |
1582 | struct dss_device *dss = dev_get_drvdata(dev); |
1583 | int r; |
1584 | |
1585 | pinctrl_pm_select_default_state(dev); |
1586 | |
1587 | /* |
1588 | * Set an arbitrarily high tput request to ensure OPP100. |
1589 | * What we should really do is to make a request to stay in OPP100, |
1590 | * without any tput requirements, but that is not currently possible |
1591 | * via the PM layer. |
1592 | */ |
1593 | |
1594 | r = dss_set_min_bus_tput(dev, tput: 1000000000); |
1595 | if (r) |
1596 | return r; |
1597 | |
1598 | dss_restore_context(dss); |
1599 | return 0; |
1600 | } |
1601 | |
1602 | static const struct dev_pm_ops dss_pm_ops = { |
1603 | SET_RUNTIME_PM_OPS(dss_runtime_suspend, dss_runtime_resume, NULL) |
1604 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) |
1605 | }; |
1606 | |
1607 | struct platform_driver omap_dsshw_driver = { |
1608 | .probe = dss_probe, |
1609 | .remove_new = dss_remove, |
1610 | .shutdown = dss_shutdown, |
1611 | .driver = { |
1612 | .name = "omapdss_dss" , |
1613 | .pm = &dss_pm_ops, |
1614 | .of_match_table = dss_of_match, |
1615 | .suppress_bind_attrs = true, |
1616 | }, |
1617 | }; |
1618 | |
1619 | /* INIT */ |
1620 | static struct platform_driver * const omap_dss_drivers[] = { |
1621 | &omap_dsshw_driver, |
1622 | &omap_dispchw_driver, |
1623 | #ifdef CONFIG_OMAP2_DSS_DSI |
1624 | &omap_dsihw_driver, |
1625 | #endif |
1626 | #ifdef CONFIG_OMAP2_DSS_VENC |
1627 | &omap_venchw_driver, |
1628 | #endif |
1629 | #ifdef CONFIG_OMAP4_DSS_HDMI |
1630 | &omapdss_hdmi4hw_driver, |
1631 | #endif |
1632 | #ifdef CONFIG_OMAP5_DSS_HDMI |
1633 | &omapdss_hdmi5hw_driver, |
1634 | #endif |
1635 | }; |
1636 | |
1637 | int __init omap_dss_init(void) |
1638 | { |
1639 | return platform_register_drivers(omap_dss_drivers, |
1640 | ARRAY_SIZE(omap_dss_drivers)); |
1641 | } |
1642 | |
1643 | void omap_dss_exit(void) |
1644 | { |
1645 | platform_unregister_drivers(drivers: omap_dss_drivers, |
1646 | ARRAY_SIZE(omap_dss_drivers)); |
1647 | } |
1648 | |