1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2012 Avionic Design GmbH |
4 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
5 | */ |
6 | |
7 | #include <linux/bitops.h> |
8 | #include <linux/host1x.h> |
9 | #include <linux/idr.h> |
10 | #include <linux/iommu.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/pm_runtime.h> |
14 | |
15 | #include <drm/drm_aperture.h> |
16 | #include <drm/drm_atomic.h> |
17 | #include <drm/drm_atomic_helper.h> |
18 | #include <drm/drm_debugfs.h> |
19 | #include <drm/drm_drv.h> |
20 | #include <drm/drm_fourcc.h> |
21 | #include <drm/drm_framebuffer.h> |
22 | #include <drm/drm_ioctl.h> |
23 | #include <drm/drm_prime.h> |
24 | #include <drm/drm_vblank.h> |
25 | |
26 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
27 | #include <asm/dma-iommu.h> |
28 | #endif |
29 | |
30 | #include "dc.h" |
31 | #include "drm.h" |
32 | #include "gem.h" |
33 | #include "uapi.h" |
34 | |
35 | #define DRIVER_NAME "tegra" |
36 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
37 | #define DRIVER_DATE "20120330" |
38 | #define DRIVER_MAJOR 1 |
39 | #define DRIVER_MINOR 0 |
40 | #define DRIVER_PATCHLEVEL 0 |
41 | |
42 | #define CARVEOUT_SZ SZ_64M |
43 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
44 | |
45 | static int tegra_atomic_check(struct drm_device *drm, |
46 | struct drm_atomic_state *state) |
47 | { |
48 | int err; |
49 | |
50 | err = drm_atomic_helper_check(dev: drm, state); |
51 | if (err < 0) |
52 | return err; |
53 | |
54 | return tegra_display_hub_atomic_check(drm, state); |
55 | } |
56 | |
57 | static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { |
58 | .fb_create = tegra_fb_create, |
59 | .atomic_check = tegra_atomic_check, |
60 | .atomic_commit = drm_atomic_helper_commit, |
61 | }; |
62 | |
63 | static void tegra_atomic_post_commit(struct drm_device *drm, |
64 | struct drm_atomic_state *old_state) |
65 | { |
66 | struct drm_crtc_state *old_crtc_state __maybe_unused; |
67 | struct drm_crtc *crtc; |
68 | unsigned int i; |
69 | |
70 | for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) |
71 | tegra_crtc_atomic_post_commit(crtc, state: old_state); |
72 | } |
73 | |
74 | static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) |
75 | { |
76 | struct drm_device *drm = old_state->dev; |
77 | struct tegra_drm *tegra = drm->dev_private; |
78 | |
79 | if (tegra->hub) { |
80 | bool fence_cookie = dma_fence_begin_signalling(); |
81 | |
82 | drm_atomic_helper_commit_modeset_disables(dev: drm, state: old_state); |
83 | tegra_display_hub_atomic_commit(drm, state: old_state); |
84 | drm_atomic_helper_commit_planes(dev: drm, state: old_state, flags: 0); |
85 | drm_atomic_helper_commit_modeset_enables(dev: drm, old_state); |
86 | drm_atomic_helper_commit_hw_done(state: old_state); |
87 | dma_fence_end_signalling(cookie: fence_cookie); |
88 | drm_atomic_helper_wait_for_vblanks(dev: drm, old_state); |
89 | drm_atomic_helper_cleanup_planes(dev: drm, old_state); |
90 | } else { |
91 | drm_atomic_helper_commit_tail_rpm(state: old_state); |
92 | } |
93 | |
94 | tegra_atomic_post_commit(drm, old_state); |
95 | } |
96 | |
97 | static const struct drm_mode_config_helper_funcs |
98 | tegra_drm_mode_config_helpers = { |
99 | .atomic_commit_tail = tegra_atomic_commit_tail, |
100 | }; |
101 | |
102 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
103 | { |
104 | struct tegra_drm_file *fpriv; |
105 | |
106 | fpriv = kzalloc(size: sizeof(*fpriv), GFP_KERNEL); |
107 | if (!fpriv) |
108 | return -ENOMEM; |
109 | |
110 | idr_init_base(idr: &fpriv->legacy_contexts, base: 1); |
111 | xa_init_flags(xa: &fpriv->contexts, XA_FLAGS_ALLOC1); |
112 | xa_init(xa: &fpriv->syncpoints); |
113 | mutex_init(&fpriv->lock); |
114 | filp->driver_priv = fpriv; |
115 | |
116 | return 0; |
117 | } |
118 | |
119 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
120 | { |
121 | context->client->ops->close_channel(context); |
122 | pm_runtime_put(dev: context->client->base.dev); |
123 | kfree(objp: context); |
124 | } |
125 | |
126 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
127 | struct drm_tegra_reloc __user *src, |
128 | struct drm_device *drm, |
129 | struct drm_file *file) |
130 | { |
131 | u32 cmdbuf, target; |
132 | int err; |
133 | |
134 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
135 | if (err < 0) |
136 | return err; |
137 | |
138 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
139 | if (err < 0) |
140 | return err; |
141 | |
142 | err = get_user(target, &src->target.handle); |
143 | if (err < 0) |
144 | return err; |
145 | |
146 | err = get_user(dest->target.offset, &src->target.offset); |
147 | if (err < 0) |
148 | return err; |
149 | |
150 | err = get_user(dest->shift, &src->shift); |
151 | if (err < 0) |
152 | return err; |
153 | |
154 | dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE; |
155 | |
156 | dest->cmdbuf.bo = tegra_gem_lookup(file, handle: cmdbuf); |
157 | if (!dest->cmdbuf.bo) |
158 | return -ENOENT; |
159 | |
160 | dest->target.bo = tegra_gem_lookup(file, handle: target); |
161 | if (!dest->target.bo) |
162 | return -ENOENT; |
163 | |
164 | return 0; |
165 | } |
166 | |
167 | int tegra_drm_submit(struct tegra_drm_context *context, |
168 | struct drm_tegra_submit *args, struct drm_device *drm, |
169 | struct drm_file *file) |
170 | { |
171 | struct host1x_client *client = &context->client->base; |
172 | unsigned int num_cmdbufs = args->num_cmdbufs; |
173 | unsigned int num_relocs = args->num_relocs; |
174 | struct drm_tegra_cmdbuf __user *user_cmdbufs; |
175 | struct drm_tegra_reloc __user *user_relocs; |
176 | struct drm_tegra_syncpt __user *user_syncpt; |
177 | struct drm_tegra_syncpt syncpt; |
178 | struct host1x *host1x = dev_get_drvdata(dev: drm->dev->parent); |
179 | struct drm_gem_object **refs; |
180 | struct host1x_syncpt *sp = NULL; |
181 | struct host1x_job *job; |
182 | unsigned int num_refs; |
183 | int err; |
184 | |
185 | user_cmdbufs = u64_to_user_ptr(args->cmdbufs); |
186 | user_relocs = u64_to_user_ptr(args->relocs); |
187 | user_syncpt = u64_to_user_ptr(args->syncpts); |
188 | |
189 | /* We don't yet support other than one syncpt_incr struct per submit */ |
190 | if (args->num_syncpts != 1) |
191 | return -EINVAL; |
192 | |
193 | /* We don't yet support waitchks */ |
194 | if (args->num_waitchks != 0) |
195 | return -EINVAL; |
196 | |
197 | job = host1x_job_alloc(ch: context->channel, num_cmdbufs: args->num_cmdbufs, |
198 | num_relocs: args->num_relocs, skip_firewall: false); |
199 | if (!job) |
200 | return -ENOMEM; |
201 | |
202 | job->num_relocs = args->num_relocs; |
203 | job->client = client; |
204 | job->class = client->class; |
205 | job->serialize = true; |
206 | job->syncpt_recovery = true; |
207 | |
208 | /* |
209 | * Track referenced BOs so that they can be unreferenced after the |
210 | * submission is complete. |
211 | */ |
212 | num_refs = num_cmdbufs + num_relocs * 2; |
213 | |
214 | refs = kmalloc_array(n: num_refs, size: sizeof(*refs), GFP_KERNEL); |
215 | if (!refs) { |
216 | err = -ENOMEM; |
217 | goto put; |
218 | } |
219 | |
220 | /* reuse as an iterator later */ |
221 | num_refs = 0; |
222 | |
223 | while (num_cmdbufs) { |
224 | struct drm_tegra_cmdbuf cmdbuf; |
225 | struct host1x_bo *bo; |
226 | struct tegra_bo *obj; |
227 | u64 offset; |
228 | |
229 | if (copy_from_user(to: &cmdbuf, from: user_cmdbufs, n: sizeof(cmdbuf))) { |
230 | err = -EFAULT; |
231 | goto fail; |
232 | } |
233 | |
234 | /* |
235 | * The maximum number of CDMA gather fetches is 16383, a higher |
236 | * value means the words count is malformed. |
237 | */ |
238 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
239 | err = -EINVAL; |
240 | goto fail; |
241 | } |
242 | |
243 | bo = tegra_gem_lookup(file, handle: cmdbuf.handle); |
244 | if (!bo) { |
245 | err = -ENOENT; |
246 | goto fail; |
247 | } |
248 | |
249 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
250 | obj = host1x_to_tegra_bo(bo); |
251 | refs[num_refs++] = &obj->gem; |
252 | |
253 | /* |
254 | * Gather buffer base address must be 4-bytes aligned, |
255 | * unaligned offset is malformed and cause commands stream |
256 | * corruption on the buffer address relocation. |
257 | */ |
258 | if (offset & 3 || offset > obj->gem.size) { |
259 | err = -EINVAL; |
260 | goto fail; |
261 | } |
262 | |
263 | host1x_job_add_gather(job, bo, words: cmdbuf.words, offset: cmdbuf.offset); |
264 | num_cmdbufs--; |
265 | user_cmdbufs++; |
266 | } |
267 | |
268 | /* copy and resolve relocations from submit */ |
269 | while (num_relocs--) { |
270 | struct host1x_reloc *reloc; |
271 | struct tegra_bo *obj; |
272 | |
273 | err = host1x_reloc_copy_from_user(dest: &job->relocs[num_relocs], |
274 | src: &user_relocs[num_relocs], drm, |
275 | file); |
276 | if (err < 0) |
277 | goto fail; |
278 | |
279 | reloc = &job->relocs[num_relocs]; |
280 | obj = host1x_to_tegra_bo(bo: reloc->cmdbuf.bo); |
281 | refs[num_refs++] = &obj->gem; |
282 | |
283 | /* |
284 | * The unaligned cmdbuf offset will cause an unaligned write |
285 | * during of the relocations patching, corrupting the commands |
286 | * stream. |
287 | */ |
288 | if (reloc->cmdbuf.offset & 3 || |
289 | reloc->cmdbuf.offset >= obj->gem.size) { |
290 | err = -EINVAL; |
291 | goto fail; |
292 | } |
293 | |
294 | obj = host1x_to_tegra_bo(bo: reloc->target.bo); |
295 | refs[num_refs++] = &obj->gem; |
296 | |
297 | if (reloc->target.offset >= obj->gem.size) { |
298 | err = -EINVAL; |
299 | goto fail; |
300 | } |
301 | } |
302 | |
303 | if (copy_from_user(to: &syncpt, from: user_syncpt, n: sizeof(syncpt))) { |
304 | err = -EFAULT; |
305 | goto fail; |
306 | } |
307 | |
308 | /* Syncpoint ref will be dropped on job release. */ |
309 | sp = host1x_syncpt_get_by_id(host: host1x, id: syncpt.id); |
310 | if (!sp) { |
311 | err = -ENOENT; |
312 | goto fail; |
313 | } |
314 | |
315 | job->is_addr_reg = context->client->ops->is_addr_reg; |
316 | job->is_valid_class = context->client->ops->is_valid_class; |
317 | job->syncpt_incrs = syncpt.incrs; |
318 | job->syncpt = sp; |
319 | job->timeout = 10000; |
320 | |
321 | if (args->timeout && args->timeout < 10000) |
322 | job->timeout = args->timeout; |
323 | |
324 | err = host1x_job_pin(job, dev: context->client->base.dev); |
325 | if (err) |
326 | goto fail; |
327 | |
328 | err = host1x_job_submit(job); |
329 | if (err) { |
330 | host1x_job_unpin(job); |
331 | goto fail; |
332 | } |
333 | |
334 | args->fence = job->syncpt_end; |
335 | |
336 | fail: |
337 | while (num_refs--) |
338 | drm_gem_object_put(obj: refs[num_refs]); |
339 | |
340 | kfree(objp: refs); |
341 | |
342 | put: |
343 | host1x_job_put(job); |
344 | return err; |
345 | } |
346 | |
347 | |
348 | #ifdef CONFIG_DRM_TEGRA_STAGING |
349 | static int tegra_gem_create(struct drm_device *drm, void *data, |
350 | struct drm_file *file) |
351 | { |
352 | struct drm_tegra_gem_create *args = data; |
353 | struct tegra_bo *bo; |
354 | |
355 | bo = tegra_bo_create_with_handle(file, drm, size: args->size, flags: args->flags, |
356 | handle: &args->handle); |
357 | if (IS_ERR(ptr: bo)) |
358 | return PTR_ERR(ptr: bo); |
359 | |
360 | return 0; |
361 | } |
362 | |
363 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
364 | struct drm_file *file) |
365 | { |
366 | struct drm_tegra_gem_mmap *args = data; |
367 | struct drm_gem_object *gem; |
368 | struct tegra_bo *bo; |
369 | |
370 | gem = drm_gem_object_lookup(filp: file, handle: args->handle); |
371 | if (!gem) |
372 | return -EINVAL; |
373 | |
374 | bo = to_tegra_bo(gem); |
375 | |
376 | args->offset = drm_vma_node_offset_addr(node: &bo->gem.vma_node); |
377 | |
378 | drm_gem_object_put(obj: gem); |
379 | |
380 | return 0; |
381 | } |
382 | |
383 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
384 | struct drm_file *file) |
385 | { |
386 | struct host1x *host = dev_get_drvdata(dev: drm->dev->parent); |
387 | struct drm_tegra_syncpt_read *args = data; |
388 | struct host1x_syncpt *sp; |
389 | |
390 | sp = host1x_syncpt_get_by_id_noref(host, id: args->id); |
391 | if (!sp) |
392 | return -EINVAL; |
393 | |
394 | args->value = host1x_syncpt_read_min(sp); |
395 | return 0; |
396 | } |
397 | |
398 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
399 | struct drm_file *file) |
400 | { |
401 | struct host1x *host1x = dev_get_drvdata(dev: drm->dev->parent); |
402 | struct drm_tegra_syncpt_incr *args = data; |
403 | struct host1x_syncpt *sp; |
404 | |
405 | sp = host1x_syncpt_get_by_id_noref(host: host1x, id: args->id); |
406 | if (!sp) |
407 | return -EINVAL; |
408 | |
409 | return host1x_syncpt_incr(sp); |
410 | } |
411 | |
412 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
413 | struct drm_file *file) |
414 | { |
415 | struct host1x *host1x = dev_get_drvdata(dev: drm->dev->parent); |
416 | struct drm_tegra_syncpt_wait *args = data; |
417 | struct host1x_syncpt *sp; |
418 | |
419 | sp = host1x_syncpt_get_by_id_noref(host: host1x, id: args->id); |
420 | if (!sp) |
421 | return -EINVAL; |
422 | |
423 | return host1x_syncpt_wait(sp, thresh: args->thresh, |
424 | timeout: msecs_to_jiffies(m: args->timeout), |
425 | value: &args->value); |
426 | } |
427 | |
428 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
429 | struct tegra_drm_client *client, |
430 | struct tegra_drm_context *context) |
431 | { |
432 | int err; |
433 | |
434 | err = pm_runtime_resume_and_get(dev: client->base.dev); |
435 | if (err) |
436 | return err; |
437 | |
438 | err = client->ops->open_channel(client, context); |
439 | if (err < 0) { |
440 | pm_runtime_put(dev: client->base.dev); |
441 | return err; |
442 | } |
443 | |
444 | err = idr_alloc(&fpriv->legacy_contexts, ptr: context, start: 1, end: 0, GFP_KERNEL); |
445 | if (err < 0) { |
446 | client->ops->close_channel(context); |
447 | pm_runtime_put(dev: client->base.dev); |
448 | return err; |
449 | } |
450 | |
451 | context->client = client; |
452 | context->id = err; |
453 | |
454 | return 0; |
455 | } |
456 | |
457 | static int tegra_open_channel(struct drm_device *drm, void *data, |
458 | struct drm_file *file) |
459 | { |
460 | struct tegra_drm_file *fpriv = file->driver_priv; |
461 | struct tegra_drm *tegra = drm->dev_private; |
462 | struct drm_tegra_open_channel *args = data; |
463 | struct tegra_drm_context *context; |
464 | struct tegra_drm_client *client; |
465 | int err = -ENODEV; |
466 | |
467 | context = kzalloc(size: sizeof(*context), GFP_KERNEL); |
468 | if (!context) |
469 | return -ENOMEM; |
470 | |
471 | mutex_lock(&fpriv->lock); |
472 | |
473 | list_for_each_entry(client, &tegra->clients, list) |
474 | if (client->base.class == args->client) { |
475 | err = tegra_client_open(fpriv, client, context); |
476 | if (err < 0) |
477 | break; |
478 | |
479 | args->context = context->id; |
480 | break; |
481 | } |
482 | |
483 | if (err < 0) |
484 | kfree(objp: context); |
485 | |
486 | mutex_unlock(lock: &fpriv->lock); |
487 | return err; |
488 | } |
489 | |
490 | static int tegra_close_channel(struct drm_device *drm, void *data, |
491 | struct drm_file *file) |
492 | { |
493 | struct tegra_drm_file *fpriv = file->driver_priv; |
494 | struct drm_tegra_close_channel *args = data; |
495 | struct tegra_drm_context *context; |
496 | int err = 0; |
497 | |
498 | mutex_lock(&fpriv->lock); |
499 | |
500 | context = idr_find(&fpriv->legacy_contexts, id: args->context); |
501 | if (!context) { |
502 | err = -EINVAL; |
503 | goto unlock; |
504 | } |
505 | |
506 | idr_remove(&fpriv->legacy_contexts, id: context->id); |
507 | tegra_drm_context_free(context); |
508 | |
509 | unlock: |
510 | mutex_unlock(lock: &fpriv->lock); |
511 | return err; |
512 | } |
513 | |
514 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
515 | struct drm_file *file) |
516 | { |
517 | struct tegra_drm_file *fpriv = file->driver_priv; |
518 | struct drm_tegra_get_syncpt *args = data; |
519 | struct tegra_drm_context *context; |
520 | struct host1x_syncpt *syncpt; |
521 | int err = 0; |
522 | |
523 | mutex_lock(&fpriv->lock); |
524 | |
525 | context = idr_find(&fpriv->legacy_contexts, id: args->context); |
526 | if (!context) { |
527 | err = -ENODEV; |
528 | goto unlock; |
529 | } |
530 | |
531 | if (args->index >= context->client->base.num_syncpts) { |
532 | err = -EINVAL; |
533 | goto unlock; |
534 | } |
535 | |
536 | syncpt = context->client->base.syncpts[args->index]; |
537 | args->id = host1x_syncpt_id(sp: syncpt); |
538 | |
539 | unlock: |
540 | mutex_unlock(lock: &fpriv->lock); |
541 | return err; |
542 | } |
543 | |
544 | static int tegra_submit(struct drm_device *drm, void *data, |
545 | struct drm_file *file) |
546 | { |
547 | struct tegra_drm_file *fpriv = file->driver_priv; |
548 | struct drm_tegra_submit *args = data; |
549 | struct tegra_drm_context *context; |
550 | int err; |
551 | |
552 | mutex_lock(&fpriv->lock); |
553 | |
554 | context = idr_find(&fpriv->legacy_contexts, id: args->context); |
555 | if (!context) { |
556 | err = -ENODEV; |
557 | goto unlock; |
558 | } |
559 | |
560 | err = context->client->ops->submit(context, args, drm, file); |
561 | |
562 | unlock: |
563 | mutex_unlock(lock: &fpriv->lock); |
564 | return err; |
565 | } |
566 | |
567 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
568 | struct drm_file *file) |
569 | { |
570 | struct tegra_drm_file *fpriv = file->driver_priv; |
571 | struct drm_tegra_get_syncpt_base *args = data; |
572 | struct tegra_drm_context *context; |
573 | struct host1x_syncpt_base *base; |
574 | struct host1x_syncpt *syncpt; |
575 | int err = 0; |
576 | |
577 | mutex_lock(&fpriv->lock); |
578 | |
579 | context = idr_find(&fpriv->legacy_contexts, id: args->context); |
580 | if (!context) { |
581 | err = -ENODEV; |
582 | goto unlock; |
583 | } |
584 | |
585 | if (args->syncpt >= context->client->base.num_syncpts) { |
586 | err = -EINVAL; |
587 | goto unlock; |
588 | } |
589 | |
590 | syncpt = context->client->base.syncpts[args->syncpt]; |
591 | |
592 | base = host1x_syncpt_get_base(sp: syncpt); |
593 | if (!base) { |
594 | err = -ENXIO; |
595 | goto unlock; |
596 | } |
597 | |
598 | args->id = host1x_syncpt_base_id(base); |
599 | |
600 | unlock: |
601 | mutex_unlock(lock: &fpriv->lock); |
602 | return err; |
603 | } |
604 | |
605 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
606 | struct drm_file *file) |
607 | { |
608 | struct drm_tegra_gem_set_tiling *args = data; |
609 | enum tegra_bo_tiling_mode mode; |
610 | struct drm_gem_object *gem; |
611 | unsigned long value = 0; |
612 | struct tegra_bo *bo; |
613 | |
614 | switch (args->mode) { |
615 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
616 | mode = TEGRA_BO_TILING_MODE_PITCH; |
617 | |
618 | if (args->value != 0) |
619 | return -EINVAL; |
620 | |
621 | break; |
622 | |
623 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
624 | mode = TEGRA_BO_TILING_MODE_TILED; |
625 | |
626 | if (args->value != 0) |
627 | return -EINVAL; |
628 | |
629 | break; |
630 | |
631 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
632 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
633 | |
634 | if (args->value > 5) |
635 | return -EINVAL; |
636 | |
637 | value = args->value; |
638 | break; |
639 | |
640 | default: |
641 | return -EINVAL; |
642 | } |
643 | |
644 | gem = drm_gem_object_lookup(filp: file, handle: args->handle); |
645 | if (!gem) |
646 | return -ENOENT; |
647 | |
648 | bo = to_tegra_bo(gem); |
649 | |
650 | bo->tiling.mode = mode; |
651 | bo->tiling.value = value; |
652 | |
653 | drm_gem_object_put(obj: gem); |
654 | |
655 | return 0; |
656 | } |
657 | |
658 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
659 | struct drm_file *file) |
660 | { |
661 | struct drm_tegra_gem_get_tiling *args = data; |
662 | struct drm_gem_object *gem; |
663 | struct tegra_bo *bo; |
664 | int err = 0; |
665 | |
666 | gem = drm_gem_object_lookup(filp: file, handle: args->handle); |
667 | if (!gem) |
668 | return -ENOENT; |
669 | |
670 | bo = to_tegra_bo(gem); |
671 | |
672 | switch (bo->tiling.mode) { |
673 | case TEGRA_BO_TILING_MODE_PITCH: |
674 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
675 | args->value = 0; |
676 | break; |
677 | |
678 | case TEGRA_BO_TILING_MODE_TILED: |
679 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
680 | args->value = 0; |
681 | break; |
682 | |
683 | case TEGRA_BO_TILING_MODE_BLOCK: |
684 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
685 | args->value = bo->tiling.value; |
686 | break; |
687 | |
688 | default: |
689 | err = -EINVAL; |
690 | break; |
691 | } |
692 | |
693 | drm_gem_object_put(obj: gem); |
694 | |
695 | return err; |
696 | } |
697 | |
698 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
699 | struct drm_file *file) |
700 | { |
701 | struct drm_tegra_gem_set_flags *args = data; |
702 | struct drm_gem_object *gem; |
703 | struct tegra_bo *bo; |
704 | |
705 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
706 | return -EINVAL; |
707 | |
708 | gem = drm_gem_object_lookup(filp: file, handle: args->handle); |
709 | if (!gem) |
710 | return -ENOENT; |
711 | |
712 | bo = to_tegra_bo(gem); |
713 | bo->flags = 0; |
714 | |
715 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
716 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
717 | |
718 | drm_gem_object_put(obj: gem); |
719 | |
720 | return 0; |
721 | } |
722 | |
723 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
724 | struct drm_file *file) |
725 | { |
726 | struct drm_tegra_gem_get_flags *args = data; |
727 | struct drm_gem_object *gem; |
728 | struct tegra_bo *bo; |
729 | |
730 | gem = drm_gem_object_lookup(filp: file, handle: args->handle); |
731 | if (!gem) |
732 | return -ENOENT; |
733 | |
734 | bo = to_tegra_bo(gem); |
735 | args->flags = 0; |
736 | |
737 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
738 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
739 | |
740 | drm_gem_object_put(obj: gem); |
741 | |
742 | return 0; |
743 | } |
744 | #endif |
745 | |
746 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
747 | #ifdef CONFIG_DRM_TEGRA_STAGING |
748 | DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open, |
749 | DRM_RENDER_ALLOW), |
750 | DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close, |
751 | DRM_RENDER_ALLOW), |
752 | DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map, |
753 | DRM_RENDER_ALLOW), |
754 | DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap, |
755 | DRM_RENDER_ALLOW), |
756 | DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_SUBMIT, tegra_drm_ioctl_channel_submit, |
757 | DRM_RENDER_ALLOW), |
758 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_ALLOCATE, tegra_drm_ioctl_syncpoint_allocate, |
759 | DRM_RENDER_ALLOW), |
760 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_FREE, tegra_drm_ioctl_syncpoint_free, |
761 | DRM_RENDER_ALLOW), |
762 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_WAIT, tegra_drm_ioctl_syncpoint_wait, |
763 | DRM_RENDER_ALLOW), |
764 | |
765 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_RENDER_ALLOW), |
766 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_RENDER_ALLOW), |
767 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, |
768 | DRM_RENDER_ALLOW), |
769 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, |
770 | DRM_RENDER_ALLOW), |
771 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, |
772 | DRM_RENDER_ALLOW), |
773 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, |
774 | DRM_RENDER_ALLOW), |
775 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, |
776 | DRM_RENDER_ALLOW), |
777 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, |
778 | DRM_RENDER_ALLOW), |
779 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, |
780 | DRM_RENDER_ALLOW), |
781 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, |
782 | DRM_RENDER_ALLOW), |
783 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, |
784 | DRM_RENDER_ALLOW), |
785 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, |
786 | DRM_RENDER_ALLOW), |
787 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, |
788 | DRM_RENDER_ALLOW), |
789 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, |
790 | DRM_RENDER_ALLOW), |
791 | #endif |
792 | }; |
793 | |
794 | static const struct file_operations tegra_drm_fops = { |
795 | .owner = THIS_MODULE, |
796 | .open = drm_open, |
797 | .release = drm_release, |
798 | .unlocked_ioctl = drm_ioctl, |
799 | .mmap = tegra_drm_mmap, |
800 | .poll = drm_poll, |
801 | .read = drm_read, |
802 | .compat_ioctl = drm_compat_ioctl, |
803 | .llseek = noop_llseek, |
804 | }; |
805 | |
806 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
807 | { |
808 | struct tegra_drm_context *context = p; |
809 | |
810 | tegra_drm_context_free(context); |
811 | |
812 | return 0; |
813 | } |
814 | |
815 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
816 | { |
817 | struct tegra_drm_file *fpriv = file->driver_priv; |
818 | |
819 | mutex_lock(&fpriv->lock); |
820 | idr_for_each(&fpriv->legacy_contexts, fn: tegra_drm_context_cleanup, NULL); |
821 | tegra_drm_uapi_close_file(file: fpriv); |
822 | mutex_unlock(lock: &fpriv->lock); |
823 | |
824 | idr_destroy(&fpriv->legacy_contexts); |
825 | mutex_destroy(lock: &fpriv->lock); |
826 | kfree(objp: fpriv); |
827 | } |
828 | |
829 | #ifdef CONFIG_DEBUG_FS |
830 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
831 | { |
832 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
833 | struct drm_device *drm = node->minor->dev; |
834 | struct drm_framebuffer *fb; |
835 | |
836 | mutex_lock(&drm->mode_config.fb_lock); |
837 | |
838 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
839 | seq_printf(m: s, fmt: "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n" , |
840 | fb->base.id, fb->width, fb->height, |
841 | fb->format->depth, |
842 | fb->format->cpp[0] * 8, |
843 | drm_framebuffer_read_refcount(fb)); |
844 | } |
845 | |
846 | mutex_unlock(lock: &drm->mode_config.fb_lock); |
847 | |
848 | return 0; |
849 | } |
850 | |
851 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
852 | { |
853 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
854 | struct drm_device *drm = node->minor->dev; |
855 | struct tegra_drm *tegra = drm->dev_private; |
856 | struct drm_printer p = drm_seq_file_printer(f: s); |
857 | |
858 | if (tegra->domain) { |
859 | mutex_lock(&tegra->mm_lock); |
860 | drm_mm_print(mm: &tegra->mm, p: &p); |
861 | mutex_unlock(lock: &tegra->mm_lock); |
862 | } |
863 | |
864 | return 0; |
865 | } |
866 | |
867 | static struct drm_info_list tegra_debugfs_list[] = { |
868 | { "framebuffers" , tegra_debugfs_framebuffers, 0 }, |
869 | { "iova" , tegra_debugfs_iova, 0 }, |
870 | }; |
871 | |
872 | static void tegra_debugfs_init(struct drm_minor *minor) |
873 | { |
874 | drm_debugfs_create_files(files: tegra_debugfs_list, |
875 | ARRAY_SIZE(tegra_debugfs_list), |
876 | root: minor->debugfs_root, minor); |
877 | } |
878 | #endif |
879 | |
880 | static const struct drm_driver tegra_drm_driver = { |
881 | .driver_features = DRIVER_MODESET | DRIVER_GEM | |
882 | DRIVER_ATOMIC | DRIVER_RENDER | DRIVER_SYNCOBJ, |
883 | .open = tegra_drm_open, |
884 | .postclose = tegra_drm_postclose, |
885 | |
886 | #if defined(CONFIG_DEBUG_FS) |
887 | .debugfs_init = tegra_debugfs_init, |
888 | #endif |
889 | |
890 | .gem_prime_import = tegra_gem_prime_import, |
891 | |
892 | .dumb_create = tegra_bo_dumb_create, |
893 | |
894 | .ioctls = tegra_drm_ioctls, |
895 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
896 | .fops = &tegra_drm_fops, |
897 | |
898 | .name = DRIVER_NAME, |
899 | .desc = DRIVER_DESC, |
900 | .date = DRIVER_DATE, |
901 | .major = DRIVER_MAJOR, |
902 | .minor = DRIVER_MINOR, |
903 | .patchlevel = DRIVER_PATCHLEVEL, |
904 | }; |
905 | |
906 | int tegra_drm_register_client(struct tegra_drm *tegra, |
907 | struct tegra_drm_client *client) |
908 | { |
909 | /* |
910 | * When MLOCKs are implemented, change to allocate a shared channel |
911 | * only when MLOCKs are disabled. |
912 | */ |
913 | client->shared_channel = host1x_channel_request(client: &client->base); |
914 | if (!client->shared_channel) |
915 | return -EBUSY; |
916 | |
917 | mutex_lock(&tegra->clients_lock); |
918 | list_add_tail(new: &client->list, head: &tegra->clients); |
919 | client->drm = tegra; |
920 | mutex_unlock(lock: &tegra->clients_lock); |
921 | |
922 | return 0; |
923 | } |
924 | |
925 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
926 | struct tegra_drm_client *client) |
927 | { |
928 | mutex_lock(&tegra->clients_lock); |
929 | list_del_init(entry: &client->list); |
930 | client->drm = NULL; |
931 | mutex_unlock(lock: &tegra->clients_lock); |
932 | |
933 | if (client->shared_channel) |
934 | host1x_channel_put(channel: client->shared_channel); |
935 | |
936 | return 0; |
937 | } |
938 | |
939 | int host1x_client_iommu_attach(struct host1x_client *client) |
940 | { |
941 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev: client->dev); |
942 | struct drm_device *drm = dev_get_drvdata(dev: client->host); |
943 | struct tegra_drm *tegra = drm->dev_private; |
944 | struct iommu_group *group = NULL; |
945 | int err; |
946 | |
947 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
948 | if (client->dev->archdata.mapping) { |
949 | struct dma_iommu_mapping *mapping = |
950 | to_dma_iommu_mapping(client->dev); |
951 | arm_iommu_detach_device(client->dev); |
952 | arm_iommu_release_mapping(mapping); |
953 | |
954 | domain = iommu_get_domain_for_dev(client->dev); |
955 | } |
956 | #endif |
957 | |
958 | /* |
959 | * If the host1x client is already attached to an IOMMU domain that is |
960 | * not the shared IOMMU domain, don't try to attach it to a different |
961 | * domain. This allows using the IOMMU-backed DMA API. |
962 | */ |
963 | if (domain && domain != tegra->domain) |
964 | return 0; |
965 | |
966 | if (tegra->domain) { |
967 | group = iommu_group_get(dev: client->dev); |
968 | if (!group) |
969 | return -ENODEV; |
970 | |
971 | if (domain != tegra->domain) { |
972 | err = iommu_attach_group(domain: tegra->domain, group); |
973 | if (err < 0) { |
974 | iommu_group_put(group); |
975 | return err; |
976 | } |
977 | } |
978 | |
979 | tegra->use_explicit_iommu = true; |
980 | } |
981 | |
982 | client->group = group; |
983 | |
984 | return 0; |
985 | } |
986 | |
987 | void host1x_client_iommu_detach(struct host1x_client *client) |
988 | { |
989 | struct drm_device *drm = dev_get_drvdata(dev: client->host); |
990 | struct tegra_drm *tegra = drm->dev_private; |
991 | struct iommu_domain *domain; |
992 | |
993 | if (client->group) { |
994 | /* |
995 | * Devices that are part of the same group may no longer be |
996 | * attached to a domain at this point because their group may |
997 | * have been detached by an earlier client. |
998 | */ |
999 | domain = iommu_get_domain_for_dev(dev: client->dev); |
1000 | if (domain) |
1001 | iommu_detach_group(domain: tegra->domain, group: client->group); |
1002 | |
1003 | iommu_group_put(group: client->group); |
1004 | client->group = NULL; |
1005 | } |
1006 | } |
1007 | |
1008 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) |
1009 | { |
1010 | struct iova *alloc; |
1011 | void *virt; |
1012 | gfp_t gfp; |
1013 | int err; |
1014 | |
1015 | if (tegra->domain) |
1016 | size = iova_align(iovad: &tegra->carveout.domain, size); |
1017 | else |
1018 | size = PAGE_ALIGN(size); |
1019 | |
1020 | gfp = GFP_KERNEL | __GFP_ZERO; |
1021 | if (!tegra->domain) { |
1022 | /* |
1023 | * Many units only support 32-bit addresses, even on 64-bit |
1024 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
1025 | * virtual address space, force allocations to be in the |
1026 | * lower 32-bit range. |
1027 | */ |
1028 | gfp |= GFP_DMA; |
1029 | } |
1030 | |
1031 | virt = (void *)__get_free_pages(gfp_mask: gfp, order: get_order(size)); |
1032 | if (!virt) |
1033 | return ERR_PTR(error: -ENOMEM); |
1034 | |
1035 | if (!tegra->domain) { |
1036 | /* |
1037 | * If IOMMU is disabled, devices address physical memory |
1038 | * directly. |
1039 | */ |
1040 | *dma = virt_to_phys(address: virt); |
1041 | return virt; |
1042 | } |
1043 | |
1044 | alloc = alloc_iova(iovad: &tegra->carveout.domain, |
1045 | size: size >> tegra->carveout.shift, |
1046 | limit_pfn: tegra->carveout.limit, size_aligned: true); |
1047 | if (!alloc) { |
1048 | err = -EBUSY; |
1049 | goto free_pages; |
1050 | } |
1051 | |
1052 | *dma = iova_dma_addr(iovad: &tegra->carveout.domain, iova: alloc); |
1053 | err = iommu_map(domain: tegra->domain, iova: *dma, virt_to_phys(address: virt), |
1054 | size, IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); |
1055 | if (err < 0) |
1056 | goto free_iova; |
1057 | |
1058 | return virt; |
1059 | |
1060 | free_iova: |
1061 | __free_iova(iovad: &tegra->carveout.domain, iova: alloc); |
1062 | free_pages: |
1063 | free_pages(addr: (unsigned long)virt, order: get_order(size)); |
1064 | |
1065 | return ERR_PTR(error: err); |
1066 | } |
1067 | |
1068 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
1069 | dma_addr_t dma) |
1070 | { |
1071 | if (tegra->domain) |
1072 | size = iova_align(iovad: &tegra->carveout.domain, size); |
1073 | else |
1074 | size = PAGE_ALIGN(size); |
1075 | |
1076 | if (tegra->domain) { |
1077 | iommu_unmap(domain: tegra->domain, iova: dma, size); |
1078 | free_iova(iovad: &tegra->carveout.domain, |
1079 | pfn: iova_pfn(iovad: &tegra->carveout.domain, iova: dma)); |
1080 | } |
1081 | |
1082 | free_pages(addr: (unsigned long)virt, order: get_order(size)); |
1083 | } |
1084 | |
1085 | static bool host1x_drm_wants_iommu(struct host1x_device *dev) |
1086 | { |
1087 | struct host1x *host1x = dev_get_drvdata(dev: dev->dev.parent); |
1088 | struct iommu_domain *domain; |
1089 | |
1090 | /* Our IOMMU usage policy doesn't currently play well with GART */ |
1091 | if (of_machine_is_compatible(compat: "nvidia,tegra20" )) |
1092 | return false; |
1093 | |
1094 | /* |
1095 | * If the Tegra DRM clients are backed by an IOMMU, push buffers are |
1096 | * likely to be allocated beyond the 32-bit boundary if sufficient |
1097 | * system memory is available. This is problematic on earlier Tegra |
1098 | * generations where host1x supports a maximum of 32 address bits in |
1099 | * the GATHER opcode. In this case, unless host1x is behind an IOMMU |
1100 | * as well it won't be able to process buffers allocated beyond the |
1101 | * 32-bit boundary. |
1102 | * |
1103 | * The DMA API will use bounce buffers in this case, so that could |
1104 | * perhaps still be made to work, even if less efficient, but there |
1105 | * is another catch: in order to perform cache maintenance on pages |
1106 | * allocated for discontiguous buffers we need to map and unmap the |
1107 | * SG table representing these buffers. This is fine for something |
1108 | * small like a push buffer, but it exhausts the bounce buffer pool |
1109 | * (typically on the order of a few MiB) for framebuffers (many MiB |
1110 | * for any modern resolution). |
1111 | * |
1112 | * Work around this by making sure that Tegra DRM clients only use |
1113 | * an IOMMU if the parent host1x also uses an IOMMU. |
1114 | * |
1115 | * Note that there's still a small gap here that we don't cover: if |
1116 | * the DMA API is backed by an IOMMU there's no way to control which |
1117 | * device is attached to an IOMMU and which isn't, except via wiring |
1118 | * up the device tree appropriately. This is considered an problem |
1119 | * of integration, so care must be taken for the DT to be consistent. |
1120 | */ |
1121 | domain = iommu_get_domain_for_dev(dev: dev->dev.parent); |
1122 | |
1123 | /* |
1124 | * Tegra20 and Tegra30 don't support addressing memory beyond the |
1125 | * 32-bit boundary, so the regular GATHER opcodes will always be |
1126 | * sufficient and whether or not the host1x is attached to an IOMMU |
1127 | * doesn't matter. |
1128 | */ |
1129 | if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32)) |
1130 | return true; |
1131 | |
1132 | return domain != NULL; |
1133 | } |
1134 | |
1135 | static int host1x_drm_probe(struct host1x_device *dev) |
1136 | { |
1137 | struct tegra_drm *tegra; |
1138 | struct drm_device *drm; |
1139 | int err; |
1140 | |
1141 | drm = drm_dev_alloc(driver: &tegra_drm_driver, parent: &dev->dev); |
1142 | if (IS_ERR(ptr: drm)) |
1143 | return PTR_ERR(ptr: drm); |
1144 | |
1145 | tegra = kzalloc(size: sizeof(*tegra), GFP_KERNEL); |
1146 | if (!tegra) { |
1147 | err = -ENOMEM; |
1148 | goto put; |
1149 | } |
1150 | |
1151 | if (host1x_drm_wants_iommu(dev) && iommu_present(bus: &platform_bus_type)) { |
1152 | tegra->domain = iommu_domain_alloc(bus: &platform_bus_type); |
1153 | if (!tegra->domain) { |
1154 | err = -ENOMEM; |
1155 | goto free; |
1156 | } |
1157 | |
1158 | err = iova_cache_get(); |
1159 | if (err < 0) |
1160 | goto domain; |
1161 | } |
1162 | |
1163 | mutex_init(&tegra->clients_lock); |
1164 | INIT_LIST_HEAD(list: &tegra->clients); |
1165 | |
1166 | dev_set_drvdata(dev: &dev->dev, data: drm); |
1167 | drm->dev_private = tegra; |
1168 | tegra->drm = drm; |
1169 | |
1170 | drm_mode_config_init(dev: drm); |
1171 | |
1172 | drm->mode_config.min_width = 0; |
1173 | drm->mode_config.min_height = 0; |
1174 | drm->mode_config.max_width = 0; |
1175 | drm->mode_config.max_height = 0; |
1176 | |
1177 | drm->mode_config.normalize_zpos = true; |
1178 | |
1179 | drm->mode_config.funcs = &tegra_drm_mode_config_funcs; |
1180 | drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; |
1181 | |
1182 | drm_kms_helper_poll_init(dev: drm); |
1183 | |
1184 | err = host1x_device_init(device: dev); |
1185 | if (err < 0) |
1186 | goto poll; |
1187 | |
1188 | /* |
1189 | * Now that all display controller have been initialized, the maximum |
1190 | * supported resolution is known and the bitmask for horizontal and |
1191 | * vertical bitfields can be computed. |
1192 | */ |
1193 | tegra->hmask = drm->mode_config.max_width - 1; |
1194 | tegra->vmask = drm->mode_config.max_height - 1; |
1195 | |
1196 | if (tegra->use_explicit_iommu) { |
1197 | u64 carveout_start, carveout_end, gem_start, gem_end; |
1198 | u64 dma_mask = dma_get_mask(dev: &dev->dev); |
1199 | dma_addr_t start, end; |
1200 | unsigned long order; |
1201 | |
1202 | start = tegra->domain->geometry.aperture_start & dma_mask; |
1203 | end = tegra->domain->geometry.aperture_end & dma_mask; |
1204 | |
1205 | gem_start = start; |
1206 | gem_end = end - CARVEOUT_SZ; |
1207 | carveout_start = gem_end + 1; |
1208 | carveout_end = end; |
1209 | |
1210 | order = __ffs(tegra->domain->pgsize_bitmap); |
1211 | init_iova_domain(iovad: &tegra->carveout.domain, granule: 1UL << order, |
1212 | start_pfn: carveout_start >> order); |
1213 | |
1214 | tegra->carveout.shift = iova_shift(iovad: &tegra->carveout.domain); |
1215 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
1216 | |
1217 | drm_mm_init(mm: &tegra->mm, start: gem_start, size: gem_end - gem_start + 1); |
1218 | mutex_init(&tegra->mm_lock); |
1219 | |
1220 | DRM_DEBUG_DRIVER("IOMMU apertures:\n" ); |
1221 | DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n" , gem_start, gem_end); |
1222 | DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n" , carveout_start, |
1223 | carveout_end); |
1224 | } else if (tegra->domain) { |
1225 | iommu_domain_free(domain: tegra->domain); |
1226 | tegra->domain = NULL; |
1227 | iova_cache_put(); |
1228 | } |
1229 | |
1230 | if (tegra->hub) { |
1231 | err = tegra_display_hub_prepare(hub: tegra->hub); |
1232 | if (err < 0) |
1233 | goto device; |
1234 | } |
1235 | |
1236 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
1237 | drm->max_vblank_count = 0xffffffff; |
1238 | |
1239 | err = drm_vblank_init(dev: drm, num_crtcs: drm->mode_config.num_crtc); |
1240 | if (err < 0) |
1241 | goto hub; |
1242 | |
1243 | drm_mode_config_reset(dev: drm); |
1244 | |
1245 | err = drm_aperture_remove_framebuffers(req_driver: &tegra_drm_driver); |
1246 | if (err < 0) |
1247 | goto hub; |
1248 | |
1249 | err = drm_dev_register(dev: drm, flags: 0); |
1250 | if (err < 0) |
1251 | goto hub; |
1252 | |
1253 | tegra_fbdev_setup(drm); |
1254 | |
1255 | return 0; |
1256 | |
1257 | hub: |
1258 | if (tegra->hub) |
1259 | tegra_display_hub_cleanup(hub: tegra->hub); |
1260 | device: |
1261 | if (tegra->domain) { |
1262 | mutex_destroy(lock: &tegra->mm_lock); |
1263 | drm_mm_takedown(mm: &tegra->mm); |
1264 | put_iova_domain(iovad: &tegra->carveout.domain); |
1265 | iova_cache_put(); |
1266 | } |
1267 | |
1268 | host1x_device_exit(device: dev); |
1269 | poll: |
1270 | drm_kms_helper_poll_fini(dev: drm); |
1271 | drm_mode_config_cleanup(dev: drm); |
1272 | domain: |
1273 | if (tegra->domain) |
1274 | iommu_domain_free(domain: tegra->domain); |
1275 | free: |
1276 | kfree(objp: tegra); |
1277 | put: |
1278 | drm_dev_put(dev: drm); |
1279 | return err; |
1280 | } |
1281 | |
1282 | static int host1x_drm_remove(struct host1x_device *dev) |
1283 | { |
1284 | struct drm_device *drm = dev_get_drvdata(dev: &dev->dev); |
1285 | struct tegra_drm *tegra = drm->dev_private; |
1286 | int err; |
1287 | |
1288 | drm_dev_unregister(dev: drm); |
1289 | |
1290 | drm_kms_helper_poll_fini(dev: drm); |
1291 | drm_atomic_helper_shutdown(dev: drm); |
1292 | drm_mode_config_cleanup(dev: drm); |
1293 | |
1294 | if (tegra->hub) |
1295 | tegra_display_hub_cleanup(hub: tegra->hub); |
1296 | |
1297 | err = host1x_device_exit(device: dev); |
1298 | if (err < 0) |
1299 | dev_err(&dev->dev, "host1x device cleanup failed: %d\n" , err); |
1300 | |
1301 | if (tegra->domain) { |
1302 | mutex_destroy(lock: &tegra->mm_lock); |
1303 | drm_mm_takedown(mm: &tegra->mm); |
1304 | put_iova_domain(iovad: &tegra->carveout.domain); |
1305 | iova_cache_put(); |
1306 | iommu_domain_free(domain: tegra->domain); |
1307 | } |
1308 | |
1309 | kfree(objp: tegra); |
1310 | drm_dev_put(dev: drm); |
1311 | |
1312 | return 0; |
1313 | } |
1314 | |
1315 | #ifdef CONFIG_PM_SLEEP |
1316 | static int host1x_drm_suspend(struct device *dev) |
1317 | { |
1318 | struct drm_device *drm = dev_get_drvdata(dev); |
1319 | |
1320 | return drm_mode_config_helper_suspend(dev: drm); |
1321 | } |
1322 | |
1323 | static int host1x_drm_resume(struct device *dev) |
1324 | { |
1325 | struct drm_device *drm = dev_get_drvdata(dev); |
1326 | |
1327 | return drm_mode_config_helper_resume(dev: drm); |
1328 | } |
1329 | #endif |
1330 | |
1331 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
1332 | host1x_drm_resume); |
1333 | |
1334 | static const struct of_device_id host1x_drm_subdevs[] = { |
1335 | { .compatible = "nvidia,tegra20-dc" , }, |
1336 | { .compatible = "nvidia,tegra20-hdmi" , }, |
1337 | { .compatible = "nvidia,tegra20-gr2d" , }, |
1338 | { .compatible = "nvidia,tegra20-gr3d" , }, |
1339 | { .compatible = "nvidia,tegra30-dc" , }, |
1340 | { .compatible = "nvidia,tegra30-hdmi" , }, |
1341 | { .compatible = "nvidia,tegra30-gr2d" , }, |
1342 | { .compatible = "nvidia,tegra30-gr3d" , }, |
1343 | { .compatible = "nvidia,tegra114-dc" , }, |
1344 | { .compatible = "nvidia,tegra114-dsi" , }, |
1345 | { .compatible = "nvidia,tegra114-hdmi" , }, |
1346 | { .compatible = "nvidia,tegra114-gr2d" , }, |
1347 | { .compatible = "nvidia,tegra114-gr3d" , }, |
1348 | { .compatible = "nvidia,tegra124-dc" , }, |
1349 | { .compatible = "nvidia,tegra124-sor" , }, |
1350 | { .compatible = "nvidia,tegra124-hdmi" , }, |
1351 | { .compatible = "nvidia,tegra124-dsi" , }, |
1352 | { .compatible = "nvidia,tegra124-vic" , }, |
1353 | { .compatible = "nvidia,tegra132-dsi" , }, |
1354 | { .compatible = "nvidia,tegra210-dc" , }, |
1355 | { .compatible = "nvidia,tegra210-dsi" , }, |
1356 | { .compatible = "nvidia,tegra210-sor" , }, |
1357 | { .compatible = "nvidia,tegra210-sor1" , }, |
1358 | { .compatible = "nvidia,tegra210-vic" , }, |
1359 | { .compatible = "nvidia,tegra210-nvdec" , }, |
1360 | { .compatible = "nvidia,tegra186-display" , }, |
1361 | { .compatible = "nvidia,tegra186-dc" , }, |
1362 | { .compatible = "nvidia,tegra186-sor" , }, |
1363 | { .compatible = "nvidia,tegra186-sor1" , }, |
1364 | { .compatible = "nvidia,tegra186-vic" , }, |
1365 | { .compatible = "nvidia,tegra186-nvdec" , }, |
1366 | { .compatible = "nvidia,tegra194-display" , }, |
1367 | { .compatible = "nvidia,tegra194-dc" , }, |
1368 | { .compatible = "nvidia,tegra194-sor" , }, |
1369 | { .compatible = "nvidia,tegra194-vic" , }, |
1370 | { .compatible = "nvidia,tegra194-nvdec" , }, |
1371 | { .compatible = "nvidia,tegra234-vic" , }, |
1372 | { .compatible = "nvidia,tegra234-nvdec" , }, |
1373 | { /* sentinel */ } |
1374 | }; |
1375 | |
1376 | static struct host1x_driver host1x_drm_driver = { |
1377 | .driver = { |
1378 | .name = "drm" , |
1379 | .pm = &host1x_drm_pm_ops, |
1380 | }, |
1381 | .probe = host1x_drm_probe, |
1382 | .remove = host1x_drm_remove, |
1383 | .subdevs = host1x_drm_subdevs, |
1384 | }; |
1385 | |
1386 | static struct platform_driver * const drivers[] = { |
1387 | &tegra_display_hub_driver, |
1388 | &tegra_dc_driver, |
1389 | &tegra_hdmi_driver, |
1390 | &tegra_dsi_driver, |
1391 | &tegra_dpaux_driver, |
1392 | &tegra_sor_driver, |
1393 | &tegra_gr2d_driver, |
1394 | &tegra_gr3d_driver, |
1395 | &tegra_vic_driver, |
1396 | &tegra_nvdec_driver, |
1397 | }; |
1398 | |
1399 | static int __init host1x_drm_init(void) |
1400 | { |
1401 | int err; |
1402 | |
1403 | if (drm_firmware_drivers_only()) |
1404 | return -ENODEV; |
1405 | |
1406 | err = host1x_driver_register(&host1x_drm_driver); |
1407 | if (err < 0) |
1408 | return err; |
1409 | |
1410 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
1411 | if (err < 0) |
1412 | goto unregister_host1x; |
1413 | |
1414 | return 0; |
1415 | |
1416 | unregister_host1x: |
1417 | host1x_driver_unregister(driver: &host1x_drm_driver); |
1418 | return err; |
1419 | } |
1420 | module_init(host1x_drm_init); |
1421 | |
1422 | static void __exit host1x_drm_exit(void) |
1423 | { |
1424 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
1425 | host1x_driver_unregister(driver: &host1x_drm_driver); |
1426 | } |
1427 | module_exit(host1x_drm_exit); |
1428 | |
1429 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>" ); |
1430 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver" ); |
1431 | MODULE_LICENSE("GPL v2" ); |
1432 | |