1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (C) 2013 NVIDIA Corporation
4	*/
5
6	#include <linux/clk.h>
7	#include <linux/debugfs.h>
8	#include <linux/delay.h>
9	#include <linux/host1x.h>
10	#include <linux/module.h>
11	#include <linux/of.h>
12	#include <linux/of_platform.h>
13	#include <linux/platform_device.h>
14	#include <linux/pm_runtime.h>
15	#include <linux/regulator/consumer.h>
16	#include <linux/reset.h>
17
18	#include <video/mipi_display.h>
19
20	#include <drm/drm_atomic_helper.h>
21	#include <drm/drm_debugfs.h>
22	#include <drm/drm_file.h>
23	#include <drm/drm_mipi_dsi.h>
24	#include <drm/drm_panel.h>
25	#include <drm/drm_simple_kms_helper.h>
26
27	#include "dc.h"
28	#include "drm.h"
29	#include "dsi.h"
30	#include "mipi-phy.h"
31	#include "trace.h"
32
33	struct tegra_dsi_state {
34	struct drm_connector_state base;
35
36	struct mipi_dphy_timing timing;
37	unsigned long period;
38
39	unsigned int vrefresh;
40	unsigned int lanes;
41	unsigned long pclk;
42	unsigned long bclk;
43
44	enum tegra_dsi_format format;
45	unsigned int mul;
46	unsigned int div;
47	};
48
49	static inline struct tegra_dsi_state *
50	to_dsi_state(struct drm_connector_state *state)
51	{
52	return container_of(state, struct tegra_dsi_state, base);
53	}
54
55	struct tegra_dsi {
56	struct host1x_client client;
57	struct tegra_output output;
58	struct device *dev;
59
60	void __iomem *regs;
61
62	struct reset_control *rst;
63	struct clk *clk_parent;
64	struct clk *clk_lp;
65	struct clk *clk;
66
67	struct drm_info_list *debugfs_files;
68
69	unsigned long flags;
70	enum mipi_dsi_pixel_format format;
71	unsigned int lanes;
72
73	struct tegra_mipi_device *mipi;
74	struct mipi_dsi_host host;
75
76	struct regulator *vdd;
77
78	unsigned int video_fifo_depth;
79	unsigned int host_fifo_depth;
80
81	/* for ganged-mode support */
82	struct tegra_dsi *master;
83	struct tegra_dsi *slave;
84	};
85
86	static inline struct tegra_dsi *
87	host1x_client_to_dsi(struct host1x_client *client)
88	{
89	return container_of(client, struct tegra_dsi, client);
90	}
91
92	static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
93	{
94	return container_of(host, struct tegra_dsi, host);
95	}
96
97	static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
98	{
99	return container_of(output, struct tegra_dsi, output);
100	}
101
102	static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
103	{
104	return to_dsi_state(state: dsi->output.connector.state);
105	}
106
107	static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
108	{
109	u32 value = readl(addr: dsi->regs + (offset << 2));
110
111	trace_dsi_readl(dev: dsi->dev, offset, value);
112
113	return value;
114	}
115
116	static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
117	unsigned int offset)
118	{
119	trace_dsi_writel(dev: dsi->dev, offset, value);
120	writel(val: value, addr: dsi->regs + (offset << 2));
121	}
122
123	#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
124
125	static const struct debugfs_reg32 tegra_dsi_regs[] = {
126	DEBUGFS_REG32(DSI_INCR_SYNCPT),
127	DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
128	DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
129	DEBUGFS_REG32(DSI_CTXSW),
130	DEBUGFS_REG32(DSI_RD_DATA),
131	DEBUGFS_REG32(DSI_WR_DATA),
132	DEBUGFS_REG32(DSI_POWER_CONTROL),
133	DEBUGFS_REG32(DSI_INT_ENABLE),
134	DEBUGFS_REG32(DSI_INT_STATUS),
135	DEBUGFS_REG32(DSI_INT_MASK),
136	DEBUGFS_REG32(DSI_HOST_CONTROL),
137	DEBUGFS_REG32(DSI_CONTROL),
138	DEBUGFS_REG32(DSI_SOL_DELAY),
139	DEBUGFS_REG32(DSI_MAX_THRESHOLD),
140	DEBUGFS_REG32(DSI_TRIGGER),
141	DEBUGFS_REG32(DSI_TX_CRC),
142	DEBUGFS_REG32(DSI_STATUS),
143	DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
144	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
145	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
146	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
147	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
148	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
149	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
150	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
151	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
152	DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
153	DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
154	DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
155	DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
156	DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
157	DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
158	DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
159	DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
160	DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
161	DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
162	DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
163	DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
164	DEBUGFS_REG32(DSI_DCS_CMDS),
165	DEBUGFS_REG32(DSI_PKT_LEN_0_1),
166	DEBUGFS_REG32(DSI_PKT_LEN_2_3),
167	DEBUGFS_REG32(DSI_PKT_LEN_4_5),
168	DEBUGFS_REG32(DSI_PKT_LEN_6_7),
169	DEBUGFS_REG32(DSI_PHY_TIMING_0),
170	DEBUGFS_REG32(DSI_PHY_TIMING_1),
171	DEBUGFS_REG32(DSI_PHY_TIMING_2),
172	DEBUGFS_REG32(DSI_BTA_TIMING),
173	DEBUGFS_REG32(DSI_TIMEOUT_0),
174	DEBUGFS_REG32(DSI_TIMEOUT_1),
175	DEBUGFS_REG32(DSI_TO_TALLY),
176	DEBUGFS_REG32(DSI_PAD_CONTROL_0),
177	DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
178	DEBUGFS_REG32(DSI_PAD_CD_STATUS),
179	DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
180	DEBUGFS_REG32(DSI_PAD_CONTROL_1),
181	DEBUGFS_REG32(DSI_PAD_CONTROL_2),
182	DEBUGFS_REG32(DSI_PAD_CONTROL_3),
183	DEBUGFS_REG32(DSI_PAD_CONTROL_4),
184	DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
185	DEBUGFS_REG32(DSI_GANGED_MODE_START),
186	DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
187	DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
188	DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
189	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
190	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
191	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
192	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
193	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
194	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
195	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
196	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
197	};
198
199	static int tegra_dsi_show_regs(struct seq_file *s, void *data)
200	{
201	struct drm_info_node *node = s->private;
202	struct tegra_dsi *dsi = node->info_ent->data;
203	struct drm_crtc *crtc = dsi->output.encoder.crtc;
204	struct drm_device *drm = node->minor->dev;
205	unsigned int i;
206	int err = 0;
207
208	drm_modeset_lock_all(dev: drm);
209
210	if (!crtc || !crtc->state->active) {
211	err = -EBUSY;
212	goto unlock;
213	}
214
215	for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
216	unsigned int offset = tegra_dsi_regs[i].offset;
217
218	seq_printf(m: s, fmt: "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
219	offset, tegra_dsi_readl(dsi, offset));
220	}
221
222	unlock:
223	drm_modeset_unlock_all(dev: drm);
224	return err;
225	}
226
227	static struct drm_info_list debugfs_files[] = {
228	{ "regs", tegra_dsi_show_regs, 0, NULL },
229	};
230
231	static int tegra_dsi_late_register(struct drm_connector *connector)
232	{
233	struct tegra_output *output = connector_to_output(c: connector);
234	unsigned int i, count = ARRAY_SIZE(debugfs_files);
235	struct drm_minor *minor = connector->dev->primary;
236	struct dentry *root = connector->debugfs_entry;
237	struct tegra_dsi *dsi = to_dsi(output);
238
239	dsi->debugfs_files = kmemdup(p: debugfs_files, size: sizeof(debugfs_files),
240	GFP_KERNEL);
241	if (!dsi->debugfs_files)
242	return -ENOMEM;
243
244	for (i = 0; i < count; i++)
245	dsi->debugfs_files[i].data = dsi;
246
247	drm_debugfs_create_files(files: dsi->debugfs_files, count, root, minor);
248
249	return 0;
250	}
251
252	static void tegra_dsi_early_unregister(struct drm_connector *connector)
253	{
254	struct tegra_output *output = connector_to_output(c: connector);
255	unsigned int count = ARRAY_SIZE(debugfs_files);
256	struct tegra_dsi *dsi = to_dsi(output);
257
258	drm_debugfs_remove_files(files: dsi->debugfs_files, count,
259	root: connector->debugfs_entry,
260	minor: connector->dev->primary);
261	kfree(objp: dsi->debugfs_files);
262	dsi->debugfs_files = NULL;
263	}
264
265	#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
266	#define PKT_LEN0(len) (((len) & 0x07) << 0)
267	#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
268	#define PKT_LEN1(len) (((len) & 0x07) << 10)
269	#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
270	#define PKT_LEN2(len) (((len) & 0x07) << 20)
271
272	#define PKT_LP (1 << 30)
273	#define NUM_PKT_SEQ 12
274
275	/*
276	* non-burst mode with sync pulses
277	*/
278	static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
279	[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
280	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
281	PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
282	PKT_LP,
283	[ 1] = 0,
284	[ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
285	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
286	PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
287	PKT_LP,
288	[ 3] = 0,
289	[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
290	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
291	PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
292	PKT_LP,
293	[ 5] = 0,
294	[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
295	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
296	PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
297	[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
298	PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
299	PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
300	[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
301	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
302	PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
303	PKT_LP,
304	[ 9] = 0,
305	[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
306	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
307	PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
308	[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
309	PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
310	PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
311	};
312
313	/*
314	* non-burst mode with sync events
315	*/
316	static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
317	[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
318	PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
319	PKT_LP,
320	[ 1] = 0,
321	[ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
322	PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
323	PKT_LP,
324	[ 3] = 0,
325	[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
326	PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
327	PKT_LP,
328	[ 5] = 0,
329	[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
330	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
331	PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
332	[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
333	[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
334	PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
335	PKT_LP,
336	[ 9] = 0,
337	[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
338	PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
339	PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
340	[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
341	};
342
343	static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
344	[ 0] = 0,
345	[ 1] = 0,
346	[ 2] = 0,
347	[ 3] = 0,
348	[ 4] = 0,
349	[ 5] = 0,
350	[ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
351	[ 7] = 0,
352	[ 8] = 0,
353	[ 9] = 0,
354	[10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
355	[11] = 0,
356	};
357
358	static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
359	unsigned long period,
360	const struct mipi_dphy_timing *timing)
361	{
362	u32 value;
363
364	value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
365	DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
366	DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
367	DSI_TIMING_FIELD(timing->hsprepare, period, 1);
368	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
369
370	value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
371	DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
372	DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
373	DSI_TIMING_FIELD(timing->lpx, period, 1);
374	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
375
376	value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
377	DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
378	DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
379	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
380
381	value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
382	DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
383	DSI_TIMING_FIELD(timing->tago, period, 1);
384	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
385
386	if (dsi->slave)
387	tegra_dsi_set_phy_timing(dsi: dsi->slave, period, timing);
388	}
389
390	static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
391	unsigned int *mulp, unsigned int *divp)
392	{
393	switch (format) {
394	case MIPI_DSI_FMT_RGB666_PACKED:
395	case MIPI_DSI_FMT_RGB888:
396	*mulp = 3;
397	*divp = 1;
398	break;
399
400	case MIPI_DSI_FMT_RGB565:
401	*mulp = 2;
402	*divp = 1;
403	break;
404
405	case MIPI_DSI_FMT_RGB666:
406	*mulp = 9;
407	*divp = 4;
408	break;
409
410	default:
411	return -EINVAL;
412	}
413
414	return 0;
415	}
416
417	static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
418	enum tegra_dsi_format *fmt)
419	{
420	switch (format) {
421	case MIPI_DSI_FMT_RGB888:
422	*fmt = TEGRA_DSI_FORMAT_24P;
423	break;
424
425	case MIPI_DSI_FMT_RGB666:
426	*fmt = TEGRA_DSI_FORMAT_18NP;
427	break;
428
429	case MIPI_DSI_FMT_RGB666_PACKED:
430	*fmt = TEGRA_DSI_FORMAT_18P;
431	break;
432
433	case MIPI_DSI_FMT_RGB565:
434	*fmt = TEGRA_DSI_FORMAT_16P;
435	break;
436
437	default:
438	return -EINVAL;
439	}
440
441	return 0;
442	}
443
444	static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
445	unsigned int size)
446	{
447	u32 value;
448
449	tegra_dsi_writel(dsi, value: start, DSI_GANGED_MODE_START);
450	tegra_dsi_writel(dsi, value: size << 16 | size, DSI_GANGED_MODE_SIZE);
451
452	value = DSI_GANGED_MODE_CONTROL_ENABLE;
453	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
454	}
455
456	static void tegra_dsi_enable(struct tegra_dsi *dsi)
457	{
458	u32 value;
459
460	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
461	value |= DSI_POWER_CONTROL_ENABLE;
462	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
463
464	if (dsi->slave)
465	tegra_dsi_enable(dsi: dsi->slave);
466	}
467
468	static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
469	{
470	if (dsi->master)
471	return dsi->master->lanes + dsi->lanes;
472
473	if (dsi->slave)
474	return dsi->lanes + dsi->slave->lanes;
475
476	return dsi->lanes;
477	}
478
479	static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
480	const struct drm_display_mode *mode)
481	{
482	unsigned int hact, hsw, hbp, hfp, i, mul, div;
483	struct tegra_dsi_state *state;
484	const u32 *pkt_seq;
485	u32 value;
486
487	/* XXX: pass in state into this function? */
488	if (dsi->master)
489	state = tegra_dsi_get_state(dsi: dsi->master);
490	else
491	state = tegra_dsi_get_state(dsi);
492
493	mul = state->mul;
494	div = state->div;
495
496	if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
497	DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
498	pkt_seq = pkt_seq_video_non_burst_sync_pulses;
499	} else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
500	DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
501	pkt_seq = pkt_seq_video_non_burst_sync_events;
502	} else {
503	DRM_DEBUG_KMS("Command mode\n");
504	pkt_seq = pkt_seq_command_mode;
505	}
506
507	value = DSI_CONTROL_CHANNEL(0) |
508	DSI_CONTROL_FORMAT(state->format) |
509	DSI_CONTROL_LANES(dsi->lanes - 1) |
510	DSI_CONTROL_SOURCE(pipe);
511	tegra_dsi_writel(dsi, value, DSI_CONTROL);
512
513	tegra_dsi_writel(dsi, value: dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
514
515	value = DSI_HOST_CONTROL_HS;
516	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
517
518	value = tegra_dsi_readl(dsi, DSI_CONTROL);
519
520	if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
521	value |= DSI_CONTROL_HS_CLK_CTRL;
522
523	value &= ~DSI_CONTROL_TX_TRIG(3);
524
525	/* enable DCS commands for command mode */
526	if (dsi->flags & MIPI_DSI_MODE_VIDEO)
527	value &= ~DSI_CONTROL_DCS_ENABLE;
528	else
529	value |= DSI_CONTROL_DCS_ENABLE;
530
531	value |= DSI_CONTROL_VIDEO_ENABLE;
532	value &= ~DSI_CONTROL_HOST_ENABLE;
533	tegra_dsi_writel(dsi, value, DSI_CONTROL);
534
535	for (i = 0; i < NUM_PKT_SEQ; i++)
536	tegra_dsi_writel(dsi, value: pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
537
538	if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
539	/* horizontal active pixels */
540	hact = mode->hdisplay * mul / div;
541
542	/* horizontal sync width */
543	hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
544
545	/* horizontal back porch */
546	hbp = (mode->htotal - mode->hsync_end) * mul / div;
547
548	if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
549	hbp += hsw;
550
551	/* horizontal front porch */
552	hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
553
554	/* subtract packet overhead */
555	hsw -= 10;
556	hbp -= 14;
557	hfp -= 8;
558
559	tegra_dsi_writel(dsi, value: hsw << 16 | 0, DSI_PKT_LEN_0_1);
560	tegra_dsi_writel(dsi, value: hact << 16 | hbp, DSI_PKT_LEN_2_3);
561	tegra_dsi_writel(dsi, value: hfp, DSI_PKT_LEN_4_5);
562	tegra_dsi_writel(dsi, value: 0x0f0f << 16, DSI_PKT_LEN_6_7);
563
564	/* set SOL delay (for non-burst mode only) */
565	tegra_dsi_writel(dsi, value: 8 * mul / div, DSI_SOL_DELAY);
566
567	/* TODO: implement ganged mode */
568	} else {
569	u16 bytes;
570
571	if (dsi->master || dsi->slave) {
572	/*
573	* For ganged mode, assume symmetric left-right mode.
574	*/
575	bytes = 1 + (mode->hdisplay / 2) * mul / div;
576	} else {
577	/* 1 byte (DCS command) + pixel data */
578	bytes = 1 + mode->hdisplay * mul / div;
579	}
580
581	tegra_dsi_writel(dsi, value: 0, DSI_PKT_LEN_0_1);
582	tegra_dsi_writel(dsi, value: bytes << 16, DSI_PKT_LEN_2_3);
583	tegra_dsi_writel(dsi, value: bytes << 16, DSI_PKT_LEN_4_5);
584	tegra_dsi_writel(dsi, value: 0, DSI_PKT_LEN_6_7);
585
586	value = MIPI_DCS_WRITE_MEMORY_START << 8 |
587	MIPI_DCS_WRITE_MEMORY_CONTINUE;
588	tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
589
590	/* set SOL delay */
591	if (dsi->master || dsi->slave) {
592	unsigned long delay, bclk, bclk_ganged;
593	unsigned int lanes = state->lanes;
594
595	/* SOL to valid, valid to FIFO and FIFO write delay */
596	delay = 4 + 4 + 2;
597	delay = DIV_ROUND_UP(delay * mul, div * lanes);
598	/* FIFO read delay */
599	delay = delay + 6;
600
601	bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
602	bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
603	value = bclk - bclk_ganged + delay + 20;
604	} else {
605	/* TODO: revisit for non-ganged mode */
606	value = 8 * mul / div;
607	}
608
609	tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
610	}
611
612	if (dsi->slave) {
613	tegra_dsi_configure(dsi: dsi->slave, pipe, mode);
614
615	/*
616	* TODO: Support modes other than symmetrical left-right
617	* split.
618	*/
619	tegra_dsi_ganged_enable(dsi, start: 0, size: mode->hdisplay / 2);
620	tegra_dsi_ganged_enable(dsi: dsi->slave, start: mode->hdisplay / 2,
621	size: mode->hdisplay / 2);
622	}
623	}
624
625	static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
626	{
627	u32 value;
628
629	timeout = jiffies + msecs_to_jiffies(m: timeout);
630
631	while (time_before(jiffies, timeout)) {
632	value = tegra_dsi_readl(dsi, DSI_STATUS);
633	if (value & DSI_STATUS_IDLE)
634	return 0;
635
636	usleep_range(min: 1000, max: 2000);
637	}
638
639	return -ETIMEDOUT;
640	}
641
642	static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
643	{
644	u32 value;
645
646	value = tegra_dsi_readl(dsi, DSI_CONTROL);
647	value &= ~DSI_CONTROL_VIDEO_ENABLE;
648	tegra_dsi_writel(dsi, value, DSI_CONTROL);
649
650	if (dsi->slave)
651	tegra_dsi_video_disable(dsi: dsi->slave);
652	}
653
654	static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
655	{
656	tegra_dsi_writel(dsi, value: 0, DSI_GANGED_MODE_START);
657	tegra_dsi_writel(dsi, value: 0, DSI_GANGED_MODE_SIZE);
658	tegra_dsi_writel(dsi, value: 0, DSI_GANGED_MODE_CONTROL);
659	}
660
661	static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
662	{
663	u32 value;
664
665	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
666	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
667
668	return 0;
669	}
670
671	static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
672	{
673	u32 value;
674	int err;
675
676	/*
677	* XXX Is this still needed? The module reset is deasserted right
678	* before this function is called.
679	*/
680	tegra_dsi_writel(dsi, value: 0, DSI_PAD_CONTROL_0);
681	tegra_dsi_writel(dsi, value: 0, DSI_PAD_CONTROL_1);
682	tegra_dsi_writel(dsi, value: 0, DSI_PAD_CONTROL_2);
683	tegra_dsi_writel(dsi, value: 0, DSI_PAD_CONTROL_3);
684	tegra_dsi_writel(dsi, value: 0, DSI_PAD_CONTROL_4);
685
686	/* start calibration */
687	tegra_dsi_pad_enable(dsi);
688
689	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
690	DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
691	DSI_PAD_OUT_CLK(0x0);
692	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
693
694	value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
695	DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
696	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
697
698	err = tegra_mipi_start_calibration(device: dsi->mipi);
699	if (err < 0)
700	return err;
701
702	return tegra_mipi_finish_calibration(device: dsi->mipi);
703	}
704
705	static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
706	unsigned int vrefresh)
707	{
708	unsigned int timeout;
709	u32 value;
710
711	/* one frame high-speed transmission timeout */
712	timeout = (bclk / vrefresh) / 512;
713	value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
714	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
715
716	/* 2 ms peripheral timeout for panel */
717	timeout = 2 * bclk / 512 * 1000;
718	value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
719	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
720
721	value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
722	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
723
724	if (dsi->slave)
725	tegra_dsi_set_timeout(dsi: dsi->slave, bclk, vrefresh);
726	}
727
728	static void tegra_dsi_disable(struct tegra_dsi *dsi)
729	{
730	u32 value;
731
732	if (dsi->slave) {
733	tegra_dsi_ganged_disable(dsi: dsi->slave);
734	tegra_dsi_ganged_disable(dsi);
735	}
736
737	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
738	value &= ~DSI_POWER_CONTROL_ENABLE;
739	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
740
741	if (dsi->slave)
742	tegra_dsi_disable(dsi: dsi->slave);
743
744	usleep_range(min: 5000, max: 10000);
745	}
746
747	static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
748	{
749	u32 value;
750
751	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
752	value &= ~DSI_POWER_CONTROL_ENABLE;
753	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
754
755	usleep_range(min: 300, max: 1000);
756
757	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
758	value |= DSI_POWER_CONTROL_ENABLE;
759	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
760
761	usleep_range(min: 300, max: 1000);
762
763	value = tegra_dsi_readl(dsi, DSI_TRIGGER);
764	if (value)
765	tegra_dsi_writel(dsi, value: 0, DSI_TRIGGER);
766
767	if (dsi->slave)
768	tegra_dsi_soft_reset(dsi: dsi->slave);
769	}
770
771	static void tegra_dsi_connector_reset(struct drm_connector *connector)
772	{
773	struct tegra_dsi_state *state = kzalloc(size: sizeof(*state), GFP_KERNEL);
774
775	if (!state)
776	return;
777
778	if (connector->state) {
779	__drm_atomic_helper_connector_destroy_state(state: connector->state);
780	kfree(objp: connector->state);
781	}
782
783	__drm_atomic_helper_connector_reset(connector, conn_state: &state->base);
784	}
785
786	static struct drm_connector_state *
787	tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
788	{
789	struct tegra_dsi_state *state = to_dsi_state(state: connector->state);
790	struct tegra_dsi_state *copy;
791
792	copy = kmemdup(p: state, size: sizeof(*state), GFP_KERNEL);
793	if (!copy)
794	return NULL;
795
796	__drm_atomic_helper_connector_duplicate_state(connector,
797	state: &copy->base);
798
799	return &copy->base;
800	}
801
802	static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
803	.reset = tegra_dsi_connector_reset,
804	.detect = tegra_output_connector_detect,
805	.fill_modes = drm_helper_probe_single_connector_modes,
806	.destroy = tegra_output_connector_destroy,
807	.atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
808	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
809	.late_register = tegra_dsi_late_register,
810	.early_unregister = tegra_dsi_early_unregister,
811	};
812
813	static enum drm_mode_status
814	tegra_dsi_connector_mode_valid(struct drm_connector *connector,
815	struct drm_display_mode *mode)
816	{
817	return MODE_OK;
818	}
819
820	static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
821	.get_modes = tegra_output_connector_get_modes,
822	.mode_valid = tegra_dsi_connector_mode_valid,
823	};
824
825	static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
826	{
827	int err;
828
829	if (dsi->slave)
830	tegra_dsi_unprepare(dsi: dsi->slave);
831
832	err = tegra_mipi_disable(device: dsi->mipi);
833	if (err < 0)
834	dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
835	err);
836
837	err = host1x_client_suspend(client: &dsi->client);
838	if (err < 0)
839	dev_err(dsi->dev, "failed to suspend: %d\n", err);
840	}
841
842	static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
843	{
844	struct tegra_output *output = encoder_to_output(e: encoder);
845	struct tegra_dc *dc = to_tegra_dc(crtc: encoder->crtc);
846	struct tegra_dsi *dsi = to_dsi(output);
847	u32 value;
848	int err;
849
850	if (output->panel)
851	drm_panel_disable(panel: output->panel);
852
853	tegra_dsi_video_disable(dsi);
854
855	/*
856	* The following accesses registers of the display controller, so make
857	* sure it's only executed when the output is attached to one.
858	*/
859	if (dc) {
860	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
861	value &= ~DSI_ENABLE;
862	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
863
864	tegra_dc_commit(dc);
865	}
866
867	err = tegra_dsi_wait_idle(dsi, timeout: 100);
868	if (err < 0)
869	dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
870
871	tegra_dsi_soft_reset(dsi);
872
873	if (output->panel)
874	drm_panel_unprepare(panel: output->panel);
875
876	tegra_dsi_disable(dsi);
877
878	tegra_dsi_unprepare(dsi);
879	}
880
881	static int tegra_dsi_prepare(struct tegra_dsi *dsi)
882	{
883	int err;
884
885	err = host1x_client_resume(client: &dsi->client);
886	if (err < 0) {
887	dev_err(dsi->dev, "failed to resume: %d\n", err);
888	return err;
889	}
890
891	err = tegra_mipi_enable(device: dsi->mipi);
892	if (err < 0)
893	dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
894	err);
895
896	err = tegra_dsi_pad_calibrate(dsi);
897	if (err < 0)
898	dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
899
900	if (dsi->slave)
901	tegra_dsi_prepare(dsi: dsi->slave);
902
903	return 0;
904	}
905
906	static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
907	{
908	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
909	struct tegra_output *output = encoder_to_output(e: encoder);
910	struct tegra_dc *dc = to_tegra_dc(crtc: encoder->crtc);
911	struct tegra_dsi *dsi = to_dsi(output);
912	struct tegra_dsi_state *state;
913	u32 value;
914	int err;
915
916	/* If the bootloader enabled DSI it needs to be disabled
917	* in order for the panel initialization commands to be
918	* properly sent.
919	*/
920	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
921
922	if (value & DSI_POWER_CONTROL_ENABLE)
923	tegra_dsi_disable(dsi);
924
925	err = tegra_dsi_prepare(dsi);
926	if (err < 0) {
927	dev_err(dsi->dev, "failed to prepare: %d\n", err);
928	return;
929	}
930
931	state = tegra_dsi_get_state(dsi);
932
933	tegra_dsi_set_timeout(dsi, bclk: state->bclk, vrefresh: state->vrefresh);
934
935	/*
936	* The D-PHY timing fields are expressed in byte-clock cycles, so
937	* multiply the period by 8.
938	*/
939	tegra_dsi_set_phy_timing(dsi, period: state->period * 8, timing: &state->timing);
940
941	if (output->panel)
942	drm_panel_prepare(panel: output->panel);
943
944	tegra_dsi_configure(dsi, pipe: dc->pipe, mode);
945
946	/* enable display controller */
947	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
948	value |= DSI_ENABLE;
949	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
950
951	tegra_dc_commit(dc);
952
953	/* enable DSI controller */
954	tegra_dsi_enable(dsi);
955
956	if (output->panel)
957	drm_panel_enable(panel: output->panel);
958	}
959
960	static int
961	tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
962	struct drm_crtc_state *crtc_state,
963	struct drm_connector_state *conn_state)
964	{
965	struct tegra_output *output = encoder_to_output(e: encoder);
966	struct tegra_dsi_state *state = to_dsi_state(state: conn_state);
967	struct tegra_dc *dc = to_tegra_dc(crtc: conn_state->crtc);
968	struct tegra_dsi *dsi = to_dsi(output);
969	unsigned int scdiv;
970	unsigned long plld;
971	int err;
972
973	state->pclk = crtc_state->mode.clock * 1000;
974
975	err = tegra_dsi_get_muldiv(format: dsi->format, mulp: &state->mul, divp: &state->div);
976	if (err < 0)
977	return err;
978
979	state->lanes = tegra_dsi_get_lanes(dsi);
980
981	err = tegra_dsi_get_format(format: dsi->format, fmt: &state->format);
982	if (err < 0)
983	return err;
984
985	state->vrefresh = drm_mode_vrefresh(mode: &crtc_state->mode);
986
987	/* compute byte clock */
988	state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
989
990	DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
991	state->lanes);
992	DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
993	state->vrefresh);
994	DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
995
996	/*
997	* Compute bit clock and round up to the next MHz.
998	*/
999	plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
1000	state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
1001
1002	err = mipi_dphy_timing_get_default(timing: &state->timing, period: state->period);
1003	if (err < 0)
1004	return err;
1005
1006	err = mipi_dphy_timing_validate(timing: &state->timing, period: state->period);
1007	if (err < 0) {
1008	dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1009	return err;
1010	}
1011
1012	/*
1013	* We divide the frequency by two here, but we make up for that by
1014	* setting the shift clock divider (further below) to half of the
1015	* correct value.
1016	*/
1017	plld /= 2;
1018
1019	/*
1020	* Derive pixel clock from bit clock using the shift clock divider.
1021	* Note that this is only half of what we would expect, but we need
1022	* that to make up for the fact that we divided the bit clock by a
1023	* factor of two above.
1024	*
1025	* It's not clear exactly why this is necessary, but the display is
1026	* not working properly otherwise. Perhaps the PLLs cannot generate
1027	* frequencies sufficiently high.
1028	*/
1029	scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1030
1031	err = tegra_dc_state_setup_clock(dc, crtc_state, clk: dsi->clk_parent,
1032	pclk: plld, div: scdiv);
1033	if (err < 0) {
1034	dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1035	return err;
1036	}
1037
1038	return err;
1039	}
1040
1041	static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1042	.disable = tegra_dsi_encoder_disable,
1043	.enable = tegra_dsi_encoder_enable,
1044	.atomic_check = tegra_dsi_encoder_atomic_check,
1045	};
1046
1047	static int tegra_dsi_init(struct host1x_client *client)
1048	{
1049	struct drm_device *drm = dev_get_drvdata(dev: client->host);
1050	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1051	int err;
1052
1053	/* Gangsters must not register their own outputs. */
1054	if (!dsi->master) {
1055	dsi->output.dev = client->dev;
1056
1057	drm_connector_init(dev: drm, connector: &dsi->output.connector,
1058	funcs: &tegra_dsi_connector_funcs,
1059	DRM_MODE_CONNECTOR_DSI);
1060	drm_connector_helper_add(connector: &dsi->output.connector,
1061	funcs: &tegra_dsi_connector_helper_funcs);
1062	dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1063
1064	drm_simple_encoder_init(dev: drm, encoder: &dsi->output.encoder,
1065	DRM_MODE_ENCODER_DSI);
1066	drm_encoder_helper_add(encoder: &dsi->output.encoder,
1067	funcs: &tegra_dsi_encoder_helper_funcs);
1068
1069	drm_connector_attach_encoder(connector: &dsi->output.connector,
1070	encoder: &dsi->output.encoder);
1071	drm_connector_register(connector: &dsi->output.connector);
1072
1073	err = tegra_output_init(drm, output: &dsi->output);
1074	if (err < 0)
1075	dev_err(dsi->dev, "failed to initialize output: %d\n",
1076	err);
1077
1078	dsi->output.encoder.possible_crtcs = 0x3;
1079	}
1080
1081	return 0;
1082	}
1083
1084	static int tegra_dsi_exit(struct host1x_client *client)
1085	{
1086	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1087
1088	tegra_output_exit(output: &dsi->output);
1089
1090	return 0;
1091	}
1092
1093	static int tegra_dsi_runtime_suspend(struct host1x_client *client)
1094	{
1095	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1096	struct device *dev = client->dev;
1097	int err;
1098
1099	if (dsi->rst) {
1100	err = reset_control_assert(rstc: dsi->rst);
1101	if (err < 0) {
1102	dev_err(dev, "failed to assert reset: %d\n", err);
1103	return err;
1104	}
1105	}
1106
1107	usleep_range(min: 1000, max: 2000);
1108
1109	clk_disable_unprepare(clk: dsi->clk_lp);
1110	clk_disable_unprepare(clk: dsi->clk);
1111
1112	regulator_disable(regulator: dsi->vdd);
1113	pm_runtime_put_sync(dev);
1114
1115	return 0;
1116	}
1117
1118	static int tegra_dsi_runtime_resume(struct host1x_client *client)
1119	{
1120	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1121	struct device *dev = client->dev;
1122	int err;
1123
1124	err = pm_runtime_resume_and_get(dev);
1125	if (err < 0) {
1126	dev_err(dev, "failed to get runtime PM: %d\n", err);
1127	return err;
1128	}
1129
1130	err = regulator_enable(regulator: dsi->vdd);
1131	if (err < 0) {
1132	dev_err(dev, "failed to enable VDD supply: %d\n", err);
1133	goto put_rpm;
1134	}
1135
1136	err = clk_prepare_enable(clk: dsi->clk);
1137	if (err < 0) {
1138	dev_err(dev, "cannot enable DSI clock: %d\n", err);
1139	goto disable_vdd;
1140	}
1141
1142	err = clk_prepare_enable(clk: dsi->clk_lp);
1143	if (err < 0) {
1144	dev_err(dev, "cannot enable low-power clock: %d\n", err);
1145	goto disable_clk;
1146	}
1147
1148	usleep_range(min: 1000, max: 2000);
1149
1150	if (dsi->rst) {
1151	err = reset_control_deassert(rstc: dsi->rst);
1152	if (err < 0) {
1153	dev_err(dev, "cannot assert reset: %d\n", err);
1154	goto disable_clk_lp;
1155	}
1156	}
1157
1158	return 0;
1159
1160	disable_clk_lp:
1161	clk_disable_unprepare(clk: dsi->clk_lp);
1162	disable_clk:
1163	clk_disable_unprepare(clk: dsi->clk);
1164	disable_vdd:
1165	regulator_disable(regulator: dsi->vdd);
1166	put_rpm:
1167	pm_runtime_put_sync(dev);
1168	return err;
1169	}
1170
1171	static const struct host1x_client_ops dsi_client_ops = {
1172	.init = tegra_dsi_init,
1173	.exit = tegra_dsi_exit,
1174	.suspend = tegra_dsi_runtime_suspend,
1175	.resume = tegra_dsi_runtime_resume,
1176	};
1177
1178	static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1179	{
1180	struct clk *parent;
1181	int err;
1182
1183	parent = clk_get_parent(clk: dsi->clk);
1184	if (!parent)
1185	return -EINVAL;
1186
1187	err = clk_set_parent(clk: parent, parent: dsi->clk_parent);
1188	if (err < 0)
1189	return err;
1190
1191	return 0;
1192	}
1193
1194	static const char * const error_report[16] = {
1195	"SoT Error",
1196	"SoT Sync Error",
1197	"EoT Sync Error",
1198	"Escape Mode Entry Command Error",
1199	"Low-Power Transmit Sync Error",
1200	"Peripheral Timeout Error",
1201	"False Control Error",
1202	"Contention Detected",
1203	"ECC Error, single-bit",
1204	"ECC Error, multi-bit",
1205	"Checksum Error",
1206	"DSI Data Type Not Recognized",
1207	"DSI VC ID Invalid",
1208	"Invalid Transmission Length",
1209	"Reserved",
1210	"DSI Protocol Violation",
1211	};
1212
1213	static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1214	const struct mipi_dsi_msg *msg,
1215	size_t count)
1216	{
1217	u8 *rx = msg->rx_buf;
1218	unsigned int i, j, k;
1219	size_t size = 0;
1220	u16 errors;
1221	u32 value;
1222
1223	/* read and parse packet header */
1224	value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1225
1226	switch (value & 0x3f) {
1227	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1228	errors = (value >> 8) & 0xffff;
1229	dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1230	errors);
1231	for (i = 0; i < ARRAY_SIZE(error_report); i++)
1232	if (errors & BIT(i))
1233	dev_dbg(dsi->dev, " %2u: %s\n", i,
1234	error_report[i]);
1235	break;
1236
1237	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1238	rx[0] = (value >> 8) & 0xff;
1239	size = 1;
1240	break;
1241
1242	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1243	rx[0] = (value >> 8) & 0xff;
1244	rx[1] = (value >> 16) & 0xff;
1245	size = 2;
1246	break;
1247
1248	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1249	size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1250	break;
1251
1252	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1253	size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1254	break;
1255
1256	default:
1257	dev_err(dsi->dev, "unhandled response type: %02x\n",
1258	value & 0x3f);
1259	return -EPROTO;
1260	}
1261
1262	size = min(size, msg->rx_len);
1263
1264	if (msg->rx_buf && size > 0) {
1265	for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1266	u8 *rx = msg->rx_buf + j;
1267
1268	value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1269
1270	for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1271	rx[j + k] = (value >> (k << 3)) & 0xff;
1272	}
1273	}
1274
1275	return size;
1276	}
1277
1278	static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1279	{
1280	tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1281
1282	timeout = jiffies + msecs_to_jiffies(m: timeout);
1283
1284	while (time_before(jiffies, timeout)) {
1285	u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1286	if ((value & DSI_TRIGGER_HOST) == 0)
1287	return 0;
1288
1289	usleep_range(min: 1000, max: 2000);
1290	}
1291
1292	DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1293	return -ETIMEDOUT;
1294	}
1295
1296	static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1297	unsigned long timeout)
1298	{
1299	timeout = jiffies + msecs_to_jiffies(m: 250);
1300
1301	while (time_before(jiffies, timeout)) {
1302	u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1303	u8 count = value & 0x1f;
1304
1305	if (count > 0)
1306	return count;
1307
1308	usleep_range(min: 1000, max: 2000);
1309	}
1310
1311	DRM_DEBUG_KMS("peripheral returned no data\n");
1312	return -ETIMEDOUT;
1313	}
1314
1315	static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1316	const void *buffer, size_t size)
1317	{
1318	const u8 *buf = buffer;
1319	size_t i, j;
1320	u32 value;
1321
1322	for (j = 0; j < size; j += 4) {
1323	value = 0;
1324
1325	for (i = 0; i < 4 && j + i < size; i++)
1326	value |= buf[j + i] << (i << 3);
1327
1328	tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1329	}
1330	}
1331
1332	static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1333	const struct mipi_dsi_msg *msg)
1334	{
1335	struct tegra_dsi *dsi = host_to_tegra(host);
1336	struct mipi_dsi_packet packet;
1337	const u8 *header;
1338	size_t count;
1339	ssize_t err;
1340	u32 value;
1341
1342	err = mipi_dsi_create_packet(packet: &packet, msg);
1343	if (err < 0)
1344	return err;
1345
1346	header = packet.header;
1347
1348	/* maximum FIFO depth is 1920 words */
1349	if (packet.size > dsi->video_fifo_depth * 4)
1350	return -ENOSPC;
1351
1352	/* reset underflow/overflow flags */
1353	value = tegra_dsi_readl(dsi, DSI_STATUS);
1354	if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1355	value = DSI_HOST_CONTROL_FIFO_RESET;
1356	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1357	usleep_range(min: 10, max: 20);
1358	}
1359
1360	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1361	value |= DSI_POWER_CONTROL_ENABLE;
1362	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1363
1364	usleep_range(min: 5000, max: 10000);
1365
1366	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1367	DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1368
1369	if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1370	value |= DSI_HOST_CONTROL_HS;
1371
1372	/*
1373	* The host FIFO has a maximum of 64 words, so larger transmissions
1374	* need to use the video FIFO.
1375	*/
1376	if (packet.size > dsi->host_fifo_depth * 4)
1377	value |= DSI_HOST_CONTROL_FIFO_SEL;
1378
1379	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1380
1381	/*
1382	* For reads and messages with explicitly requested ACK, generate a
1383	* BTA sequence after the transmission of the packet.
1384	*/
1385	if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1386	(msg->rx_buf && msg->rx_len > 0)) {
1387	value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1388	value |= DSI_HOST_CONTROL_PKT_BTA;
1389	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1390	}
1391
1392	value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1393	tegra_dsi_writel(dsi, value, DSI_CONTROL);
1394
1395	/* write packet header, ECC is generated by hardware */
1396	value = header[2] << 16 | header[1] << 8 | header[0];
1397	tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1398
1399	/* write payload (if any) */
1400	if (packet.payload_length > 0)
1401	tegra_dsi_writesl(dsi, DSI_WR_DATA, buffer: packet.payload,
1402	size: packet.payload_length);
1403
1404	err = tegra_dsi_transmit(dsi, timeout: 250);
1405	if (err < 0)
1406	return err;
1407
1408	if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1409	(msg->rx_buf && msg->rx_len > 0)) {
1410	err = tegra_dsi_wait_for_response(dsi, timeout: 250);
1411	if (err < 0)
1412	return err;
1413
1414	count = err;
1415
1416	value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1417	switch (value) {
1418	case 0x84:
1419	/*
1420	dev_dbg(dsi->dev, "ACK\n");
1421	*/
1422	break;
1423
1424	case 0x87:
1425	/*
1426	dev_dbg(dsi->dev, "ESCAPE\n");
1427	*/
1428	break;
1429
1430	default:
1431	dev_err(dsi->dev, "unknown status: %08x\n", value);
1432	break;
1433	}
1434
1435	if (count > 1) {
1436	err = tegra_dsi_read_response(dsi, msg, count);
1437	if (err < 0)
1438	dev_err(dsi->dev,
1439	"failed to parse response: %zd\n",
1440	err);
1441	else {
1442	/*
1443	* For read commands, return the number of
1444	* bytes returned by the peripheral.
1445	*/
1446	count = err;
1447	}
1448	}
1449	} else {
1450	/*
1451	* For write commands, we have transmitted the 4-byte header
1452	* plus the variable-length payload.
1453	*/
1454	count = 4 + packet.payload_length;
1455	}
1456
1457	return count;
1458	}
1459
1460	static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1461	{
1462	struct clk *parent;
1463	int err;
1464
1465	/* make sure both DSI controllers share the same PLL */
1466	parent = clk_get_parent(clk: dsi->slave->clk);
1467	if (!parent)
1468	return -EINVAL;
1469
1470	err = clk_set_parent(clk: parent, parent: dsi->clk_parent);
1471	if (err < 0)
1472	return err;
1473
1474	return 0;
1475	}
1476
1477	static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1478	struct mipi_dsi_device *device)
1479	{
1480	struct tegra_dsi *dsi = host_to_tegra(host);
1481
1482	dsi->flags = device->mode_flags;
1483	dsi->format = device->format;
1484	dsi->lanes = device->lanes;
1485
1486	if (dsi->slave) {
1487	int err;
1488
1489	dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1490	dev_name(&device->dev));
1491
1492	err = tegra_dsi_ganged_setup(dsi);
1493	if (err < 0) {
1494	dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1495	err);
1496	return err;
1497	}
1498	}
1499
1500	/*
1501	* Slaves don't have a panel associated with them, so they provide
1502	* merely the second channel.
1503	*/
1504	if (!dsi->master) {
1505	struct tegra_output *output = &dsi->output;
1506
1507	output->panel = of_drm_find_panel(np: device->dev.of_node);
1508	if (IS_ERR(ptr: output->panel))
1509	output->panel = NULL;
1510
1511	if (output->panel && output->connector.dev)
1512	drm_helper_hpd_irq_event(dev: output->connector.dev);
1513	}
1514
1515	return 0;
1516	}
1517
1518	static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1519	struct mipi_dsi_device *device)
1520	{
1521	struct tegra_dsi *dsi = host_to_tegra(host);
1522	struct tegra_output *output = &dsi->output;
1523
1524	if (output->panel && &device->dev == output->panel->dev) {
1525	output->panel = NULL;
1526
1527	if (output->connector.dev)
1528	drm_helper_hpd_irq_event(dev: output->connector.dev);
1529	}
1530
1531	return 0;
1532	}
1533
1534	static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1535	.attach = tegra_dsi_host_attach,
1536	.detach = tegra_dsi_host_detach,
1537	.transfer = tegra_dsi_host_transfer,
1538	};
1539
1540	static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1541	{
1542	struct device_node *np;
1543
1544	np = of_parse_phandle(np: dsi->dev->of_node, phandle_name: "nvidia,ganged-mode", index: 0);
1545	if (np) {
1546	struct platform_device *gangster = of_find_device_by_node(np);
1547
1548	dsi->slave = platform_get_drvdata(pdev: gangster);
1549	of_node_put(node: np);
1550
1551	if (!dsi->slave) {
1552	put_device(dev: &gangster->dev);
1553	return -EPROBE_DEFER;
1554	}
1555
1556	dsi->slave->master = dsi;
1557	}
1558
1559	return 0;
1560	}
1561
1562	static int tegra_dsi_probe(struct platform_device *pdev)
1563	{
1564	struct tegra_dsi *dsi;
1565	struct resource *regs;
1566	int err;
1567
1568	dsi = devm_kzalloc(dev: &pdev->dev, size: sizeof(*dsi), GFP_KERNEL);
1569	if (!dsi)
1570	return -ENOMEM;
1571
1572	dsi->output.dev = dsi->dev = &pdev->dev;
1573	dsi->video_fifo_depth = 1920;
1574	dsi->host_fifo_depth = 64;
1575
1576	err = tegra_dsi_ganged_probe(dsi);
1577	if (err < 0)
1578	return err;
1579
1580	err = tegra_output_probe(output: &dsi->output);
1581	if (err < 0)
1582	return err;
1583
1584	dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1585
1586	/*
1587	* Assume these values by default. When a DSI peripheral driver
1588	* attaches to the DSI host, the parameters will be taken from
1589	* the attached device.
1590	*/
1591	dsi->flags = MIPI_DSI_MODE_VIDEO;
1592	dsi->format = MIPI_DSI_FMT_RGB888;
1593	dsi->lanes = 4;
1594
1595	if (!pdev->dev.pm_domain) {
1596	dsi->rst = devm_reset_control_get(dev: &pdev->dev, id: "dsi");
1597	if (IS_ERR(ptr: dsi->rst))
1598	return PTR_ERR(ptr: dsi->rst);
1599	}
1600
1601	dsi->clk = devm_clk_get(dev: &pdev->dev, NULL);
1602	if (IS_ERR(ptr: dsi->clk))
1603	return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: dsi->clk),
1604	fmt: "cannot get DSI clock\n");
1605
1606	dsi->clk_lp = devm_clk_get(dev: &pdev->dev, id: "lp");
1607	if (IS_ERR(ptr: dsi->clk_lp))
1608	return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: dsi->clk_lp),
1609	fmt: "cannot get low-power clock\n");
1610
1611	dsi->clk_parent = devm_clk_get(dev: &pdev->dev, id: "parent");
1612	if (IS_ERR(ptr: dsi->clk_parent))
1613	return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: dsi->clk_parent),
1614	fmt: "cannot get parent clock\n");
1615
1616	dsi->vdd = devm_regulator_get(dev: &pdev->dev, id: "avdd-dsi-csi");
1617	if (IS_ERR(ptr: dsi->vdd))
1618	return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: dsi->vdd),
1619	fmt: "cannot get VDD supply\n");
1620
1621	err = tegra_dsi_setup_clocks(dsi);
1622	if (err < 0) {
1623	dev_err(&pdev->dev, "cannot setup clocks\n");
1624	return err;
1625	}
1626
1627	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1628	dsi->regs = devm_ioremap_resource(dev: &pdev->dev, res: regs);
1629	if (IS_ERR(ptr: dsi->regs))
1630	return PTR_ERR(ptr: dsi->regs);
1631
1632	dsi->mipi = tegra_mipi_request(device: &pdev->dev, np: pdev->dev.of_node);
1633	if (IS_ERR(ptr: dsi->mipi))
1634	return PTR_ERR(ptr: dsi->mipi);
1635
1636	dsi->host.ops = &tegra_dsi_host_ops;
1637	dsi->host.dev = &pdev->dev;
1638
1639	err = mipi_dsi_host_register(host: &dsi->host);
1640	if (err < 0) {
1641	dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1642	goto mipi_free;
1643	}
1644
1645	platform_set_drvdata(pdev, data: dsi);
1646	pm_runtime_enable(dev: &pdev->dev);
1647
1648	INIT_LIST_HEAD(list: &dsi->client.list);
1649	dsi->client.ops = &dsi_client_ops;
1650	dsi->client.dev = &pdev->dev;
1651
1652	err = host1x_client_register(&dsi->client);
1653	if (err < 0) {
1654	dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1655	err);
1656	goto unregister;
1657	}
1658
1659	return 0;
1660
1661	unregister:
1662	mipi_dsi_host_unregister(host: &dsi->host);
1663	mipi_free:
1664	tegra_mipi_free(device: dsi->mipi);
1665	return err;
1666	}
1667
1668	static void tegra_dsi_remove(struct platform_device *pdev)
1669	{
1670	struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1671
1672	pm_runtime_disable(dev: &pdev->dev);
1673
1674	host1x_client_unregister(client: &dsi->client);
1675
1676	tegra_output_remove(output: &dsi->output);
1677
1678	mipi_dsi_host_unregister(host: &dsi->host);
1679	tegra_mipi_free(device: dsi->mipi);
1680	}
1681
1682	static const struct of_device_id tegra_dsi_of_match[] = {
1683	{ .compatible = "nvidia,tegra210-dsi", },
1684	{ .compatible = "nvidia,tegra132-dsi", },
1685	{ .compatible = "nvidia,tegra124-dsi", },
1686	{ .compatible = "nvidia,tegra114-dsi", },
1687	{ },
1688	};
1689	MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1690
1691	struct platform_driver tegra_dsi_driver = {
1692	.driver = {
1693	.name = "tegra-dsi",
1694	.of_match_table = tegra_dsi_of_match,
1695	},
1696	.probe = tegra_dsi_probe,
1697	.remove_new = tegra_dsi_remove,
1698	};
1699