1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // Copyright (C) 2014 Broadcom Corporation |
3 | |
4 | #include <linux/delay.h> |
5 | #include <linux/i2c.h> |
6 | #include <linux/interrupt.h> |
7 | #include <linux/io.h> |
8 | #include <linux/kernel.h> |
9 | #include <linux/module.h> |
10 | #include <linux/of.h> |
11 | #include <linux/platform_device.h> |
12 | #include <linux/slab.h> |
13 | |
14 | #define IDM_CTRL_DIRECT_OFFSET 0x00 |
15 | #define CFG_OFFSET 0x00 |
16 | #define CFG_RESET_SHIFT 31 |
17 | #define CFG_EN_SHIFT 30 |
18 | #define CFG_SLAVE_ADDR_0_SHIFT 28 |
19 | #define CFG_M_RETRY_CNT_SHIFT 16 |
20 | #define CFG_M_RETRY_CNT_MASK 0x0f |
21 | |
22 | #define TIM_CFG_OFFSET 0x04 |
23 | #define TIM_CFG_MODE_400_SHIFT 31 |
24 | #define TIM_RAND_SLAVE_STRETCH_SHIFT 24 |
25 | #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f |
26 | #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16 |
27 | #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f |
28 | |
29 | #define S_CFG_SMBUS_ADDR_OFFSET 0x08 |
30 | #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31 |
31 | #define S_CFG_NIC_SMB_ADDR3_SHIFT 24 |
32 | #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f |
33 | #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23 |
34 | #define S_CFG_NIC_SMB_ADDR2_SHIFT 16 |
35 | #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f |
36 | #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15 |
37 | #define S_CFG_NIC_SMB_ADDR1_SHIFT 8 |
38 | #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f |
39 | #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7 |
40 | #define S_CFG_NIC_SMB_ADDR0_SHIFT 0 |
41 | #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f |
42 | |
43 | #define M_FIFO_CTRL_OFFSET 0x0c |
44 | #define M_FIFO_RX_FLUSH_SHIFT 31 |
45 | #define M_FIFO_TX_FLUSH_SHIFT 30 |
46 | #define M_FIFO_RX_CNT_SHIFT 16 |
47 | #define M_FIFO_RX_CNT_MASK 0x7f |
48 | #define M_FIFO_RX_THLD_SHIFT 8 |
49 | #define M_FIFO_RX_THLD_MASK 0x3f |
50 | |
51 | #define S_FIFO_CTRL_OFFSET 0x10 |
52 | #define S_FIFO_RX_FLUSH_SHIFT 31 |
53 | #define S_FIFO_TX_FLUSH_SHIFT 30 |
54 | #define S_FIFO_RX_CNT_SHIFT 16 |
55 | #define S_FIFO_RX_CNT_MASK 0x7f |
56 | #define S_FIFO_RX_THLD_SHIFT 8 |
57 | #define S_FIFO_RX_THLD_MASK 0x3f |
58 | |
59 | #define M_CMD_OFFSET 0x30 |
60 | #define M_CMD_START_BUSY_SHIFT 31 |
61 | #define M_CMD_STATUS_SHIFT 25 |
62 | #define M_CMD_STATUS_MASK 0x07 |
63 | #define M_CMD_STATUS_SUCCESS 0x0 |
64 | #define M_CMD_STATUS_LOST_ARB 0x1 |
65 | #define M_CMD_STATUS_NACK_ADDR 0x2 |
66 | #define M_CMD_STATUS_NACK_DATA 0x3 |
67 | #define M_CMD_STATUS_TIMEOUT 0x4 |
68 | #define M_CMD_STATUS_FIFO_UNDERRUN 0x5 |
69 | #define M_CMD_STATUS_RX_FIFO_FULL 0x6 |
70 | #define M_CMD_PROTOCOL_SHIFT 9 |
71 | #define M_CMD_PROTOCOL_MASK 0xf |
72 | #define M_CMD_PROTOCOL_QUICK 0x0 |
73 | #define M_CMD_PROTOCOL_BLK_WR 0x7 |
74 | #define M_CMD_PROTOCOL_BLK_RD 0x8 |
75 | #define M_CMD_PROTOCOL_PROCESS 0xa |
76 | #define M_CMD_PEC_SHIFT 8 |
77 | #define M_CMD_RD_CNT_SHIFT 0 |
78 | #define M_CMD_RD_CNT_MASK 0xff |
79 | |
80 | #define S_CMD_OFFSET 0x34 |
81 | #define S_CMD_START_BUSY_SHIFT 31 |
82 | #define S_CMD_STATUS_SHIFT 23 |
83 | #define S_CMD_STATUS_MASK 0x07 |
84 | #define S_CMD_STATUS_SUCCESS 0x0 |
85 | #define S_CMD_STATUS_TIMEOUT 0x5 |
86 | #define S_CMD_STATUS_MASTER_ABORT 0x7 |
87 | |
88 | #define IE_OFFSET 0x38 |
89 | #define IE_M_RX_FIFO_FULL_SHIFT 31 |
90 | #define IE_M_RX_THLD_SHIFT 30 |
91 | #define IE_M_START_BUSY_SHIFT 28 |
92 | #define IE_M_TX_UNDERRUN_SHIFT 27 |
93 | #define IE_S_RX_FIFO_FULL_SHIFT 26 |
94 | #define IE_S_RX_THLD_SHIFT 25 |
95 | #define IE_S_RX_EVENT_SHIFT 24 |
96 | #define IE_S_START_BUSY_SHIFT 23 |
97 | #define IE_S_TX_UNDERRUN_SHIFT 22 |
98 | #define IE_S_RD_EVENT_SHIFT 21 |
99 | |
100 | #define IS_OFFSET 0x3c |
101 | #define IS_M_RX_FIFO_FULL_SHIFT 31 |
102 | #define IS_M_RX_THLD_SHIFT 30 |
103 | #define IS_M_START_BUSY_SHIFT 28 |
104 | #define IS_M_TX_UNDERRUN_SHIFT 27 |
105 | #define IS_S_RX_FIFO_FULL_SHIFT 26 |
106 | #define IS_S_RX_THLD_SHIFT 25 |
107 | #define IS_S_RX_EVENT_SHIFT 24 |
108 | #define IS_S_START_BUSY_SHIFT 23 |
109 | #define IS_S_TX_UNDERRUN_SHIFT 22 |
110 | #define IS_S_RD_EVENT_SHIFT 21 |
111 | |
112 | #define M_TX_OFFSET 0x40 |
113 | #define M_TX_WR_STATUS_SHIFT 31 |
114 | #define M_TX_DATA_SHIFT 0 |
115 | #define M_TX_DATA_MASK 0xff |
116 | |
117 | #define M_RX_OFFSET 0x44 |
118 | #define M_RX_STATUS_SHIFT 30 |
119 | #define M_RX_STATUS_MASK 0x03 |
120 | #define M_RX_PEC_ERR_SHIFT 29 |
121 | #define M_RX_DATA_SHIFT 0 |
122 | #define M_RX_DATA_MASK 0xff |
123 | |
124 | #define S_TX_OFFSET 0x48 |
125 | #define S_TX_WR_STATUS_SHIFT 31 |
126 | #define S_TX_DATA_SHIFT 0 |
127 | #define S_TX_DATA_MASK 0xff |
128 | |
129 | #define S_RX_OFFSET 0x4c |
130 | #define S_RX_STATUS_SHIFT 30 |
131 | #define S_RX_STATUS_MASK 0x03 |
132 | #define S_RX_PEC_ERR_SHIFT 29 |
133 | #define S_RX_DATA_SHIFT 0 |
134 | #define S_RX_DATA_MASK 0xff |
135 | |
136 | #define I2C_TIMEOUT_MSEC 50000 |
137 | #define M_TX_RX_FIFO_SIZE 64 |
138 | #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) |
139 | |
140 | #define M_RX_MAX_READ_LEN 255 |
141 | #define M_RX_FIFO_THLD_VALUE 50 |
142 | |
143 | #define IE_M_ALL_INTERRUPT_SHIFT 27 |
144 | #define IE_M_ALL_INTERRUPT_MASK 0x1e |
145 | |
146 | #define SLAVE_READ_WRITE_BIT_MASK 0x1 |
147 | #define SLAVE_READ_WRITE_BIT_SHIFT 0x1 |
148 | #define SLAVE_MAX_SIZE_TRANSACTION 64 |
149 | #define SLAVE_CLOCK_STRETCH_TIME 25 |
150 | |
151 | #define IE_S_ALL_INTERRUPT_SHIFT 21 |
152 | #define IE_S_ALL_INTERRUPT_MASK 0x3f |
153 | /* |
154 | * It takes ~18us to reading 10bytes of data, hence to keep tasklet |
155 | * running for less time, max slave read per tasklet is set to 10 bytes. |
156 | */ |
157 | #define MAX_SLAVE_RX_PER_INT 10 |
158 | |
159 | enum i2c_slave_read_status { |
160 | I2C_SLAVE_RX_FIFO_EMPTY = 0, |
161 | I2C_SLAVE_RX_START, |
162 | I2C_SLAVE_RX_DATA, |
163 | I2C_SLAVE_RX_END, |
164 | }; |
165 | |
166 | enum bus_speed_index { |
167 | I2C_SPD_100K = 0, |
168 | I2C_SPD_400K, |
169 | }; |
170 | |
171 | enum bcm_iproc_i2c_type { |
172 | IPROC_I2C, |
173 | IPROC_I2C_NIC |
174 | }; |
175 | |
176 | struct bcm_iproc_i2c_dev { |
177 | struct device *device; |
178 | enum bcm_iproc_i2c_type type; |
179 | int irq; |
180 | |
181 | void __iomem *base; |
182 | void __iomem *idm_base; |
183 | |
184 | u32 ape_addr_mask; |
185 | |
186 | /* lock for indirect access through IDM */ |
187 | spinlock_t idm_lock; |
188 | |
189 | struct i2c_adapter adapter; |
190 | unsigned int bus_speed; |
191 | |
192 | struct completion done; |
193 | int xfer_is_done; |
194 | |
195 | struct i2c_msg *msg; |
196 | |
197 | struct i2c_client *slave; |
198 | |
199 | /* bytes that have been transferred */ |
200 | unsigned int tx_bytes; |
201 | /* bytes that have been read */ |
202 | unsigned int rx_bytes; |
203 | unsigned int thld_bytes; |
204 | |
205 | bool slave_rx_only; |
206 | bool rx_start_rcvd; |
207 | bool slave_read_complete; |
208 | u32 tx_underrun; |
209 | u32 slave_int_mask; |
210 | struct tasklet_struct slave_rx_tasklet; |
211 | }; |
212 | |
213 | /* tasklet to process slave rx data */ |
214 | static void slave_rx_tasklet_fn(unsigned long); |
215 | |
216 | /* |
217 | * Can be expanded in the future if more interrupt status bits are utilized |
218 | */ |
219 | #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ |
220 | | BIT(IS_M_RX_THLD_SHIFT)) |
221 | |
222 | #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ |
223 | | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\ |
224 | | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\ |
225 | | BIT(IS_S_RX_THLD_SHIFT)) |
226 | |
227 | static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); |
228 | static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); |
229 | static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, |
230 | bool enable); |
231 | |
232 | static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, |
233 | u32 offset) |
234 | { |
235 | u32 val; |
236 | unsigned long flags; |
237 | |
238 | if (iproc_i2c->idm_base) { |
239 | spin_lock_irqsave(&iproc_i2c->idm_lock, flags); |
240 | writel(val: iproc_i2c->ape_addr_mask, |
241 | addr: iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); |
242 | val = readl(addr: iproc_i2c->base + offset); |
243 | spin_unlock_irqrestore(lock: &iproc_i2c->idm_lock, flags); |
244 | } else { |
245 | val = readl(addr: iproc_i2c->base + offset); |
246 | } |
247 | |
248 | return val; |
249 | } |
250 | |
251 | static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, |
252 | u32 offset, u32 val) |
253 | { |
254 | unsigned long flags; |
255 | |
256 | if (iproc_i2c->idm_base) { |
257 | spin_lock_irqsave(&iproc_i2c->idm_lock, flags); |
258 | writel(val: iproc_i2c->ape_addr_mask, |
259 | addr: iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); |
260 | writel(val, addr: iproc_i2c->base + offset); |
261 | spin_unlock_irqrestore(lock: &iproc_i2c->idm_lock, flags); |
262 | } else { |
263 | writel(val, addr: iproc_i2c->base + offset); |
264 | } |
265 | } |
266 | |
267 | static void bcm_iproc_i2c_slave_init( |
268 | struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) |
269 | { |
270 | u32 val; |
271 | |
272 | iproc_i2c->tx_underrun = 0; |
273 | if (need_reset) { |
274 | /* put controller in reset */ |
275 | val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); |
276 | val |= BIT(CFG_RESET_SHIFT); |
277 | iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); |
278 | |
279 | /* wait 100 usec per spec */ |
280 | udelay(100); |
281 | |
282 | /* bring controller out of reset */ |
283 | val &= ~(BIT(CFG_RESET_SHIFT)); |
284 | iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); |
285 | } |
286 | |
287 | /* flush TX/RX FIFOs */ |
288 | val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); |
289 | iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); |
290 | |
291 | /* Maximum slave stretch time */ |
292 | val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); |
293 | val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); |
294 | val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); |
295 | iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); |
296 | |
297 | /* Configure the slave address */ |
298 | val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); |
299 | val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); |
300 | val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); |
301 | val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); |
302 | iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); |
303 | |
304 | /* clear all pending slave interrupts */ |
305 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); |
306 | |
307 | /* Enable interrupt register to indicate a valid byte in receive fifo */ |
308 | val = BIT(IE_S_RX_EVENT_SHIFT); |
309 | /* Enable interrupt register to indicate Slave Rx FIFO Full */ |
310 | val |= BIT(IE_S_RX_FIFO_FULL_SHIFT); |
311 | /* Enable interrupt register to indicate a Master read transaction */ |
312 | val |= BIT(IE_S_RD_EVENT_SHIFT); |
313 | /* Enable interrupt register for the Slave BUSY command */ |
314 | val |= BIT(IE_S_START_BUSY_SHIFT); |
315 | iproc_i2c->slave_int_mask = val; |
316 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); |
317 | } |
318 | |
319 | static bool bcm_iproc_i2c_check_slave_status |
320 | (struct bcm_iproc_i2c_dev *iproc_i2c, u32 status) |
321 | { |
322 | u32 val; |
323 | bool recover = false; |
324 | |
325 | /* check slave transmit status only if slave is transmitting */ |
326 | if (!iproc_i2c->slave_rx_only) { |
327 | val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); |
328 | /* status is valid only when START_BUSY is cleared */ |
329 | if (!(val & BIT(S_CMD_START_BUSY_SHIFT))) { |
330 | val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; |
331 | if (val == S_CMD_STATUS_TIMEOUT || |
332 | val == S_CMD_STATUS_MASTER_ABORT) { |
333 | dev_warn(iproc_i2c->device, |
334 | (val == S_CMD_STATUS_TIMEOUT) ? |
335 | "slave random stretch time timeout\n" : |
336 | "Master aborted read transaction\n" ); |
337 | recover = true; |
338 | } |
339 | } |
340 | } |
341 | |
342 | /* RX_EVENT is not valid when START_BUSY is set */ |
343 | if ((status & BIT(IS_S_RX_EVENT_SHIFT)) && |
344 | (status & BIT(IS_S_START_BUSY_SHIFT))) { |
345 | dev_warn(iproc_i2c->device, "Slave aborted read transaction\n" ); |
346 | recover = true; |
347 | } |
348 | |
349 | if (recover) { |
350 | /* re-initialize i2c for recovery */ |
351 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false); |
352 | bcm_iproc_i2c_slave_init(iproc_i2c, need_reset: true); |
353 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true); |
354 | } |
355 | |
356 | return recover; |
357 | } |
358 | |
359 | static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c) |
360 | { |
361 | u8 rx_data, rx_status; |
362 | u32 rx_bytes = 0; |
363 | u32 val; |
364 | |
365 | while (rx_bytes < MAX_SLAVE_RX_PER_INT) { |
366 | val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); |
367 | rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; |
368 | rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); |
369 | |
370 | if (rx_status == I2C_SLAVE_RX_START) { |
371 | /* Start of SMBUS Master write */ |
372 | i2c_slave_event(client: iproc_i2c->slave, |
373 | event: I2C_SLAVE_WRITE_REQUESTED, val: &rx_data); |
374 | iproc_i2c->rx_start_rcvd = true; |
375 | iproc_i2c->slave_read_complete = false; |
376 | } else if (rx_status == I2C_SLAVE_RX_DATA && |
377 | iproc_i2c->rx_start_rcvd) { |
378 | /* Middle of SMBUS Master write */ |
379 | i2c_slave_event(client: iproc_i2c->slave, |
380 | event: I2C_SLAVE_WRITE_RECEIVED, val: &rx_data); |
381 | } else if (rx_status == I2C_SLAVE_RX_END && |
382 | iproc_i2c->rx_start_rcvd) { |
383 | /* End of SMBUS Master write */ |
384 | if (iproc_i2c->slave_rx_only) |
385 | i2c_slave_event(client: iproc_i2c->slave, |
386 | event: I2C_SLAVE_WRITE_RECEIVED, |
387 | val: &rx_data); |
388 | |
389 | i2c_slave_event(client: iproc_i2c->slave, event: I2C_SLAVE_STOP, |
390 | val: &rx_data); |
391 | } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) { |
392 | iproc_i2c->rx_start_rcvd = false; |
393 | iproc_i2c->slave_read_complete = true; |
394 | break; |
395 | } |
396 | |
397 | rx_bytes++; |
398 | } |
399 | } |
400 | |
401 | static void slave_rx_tasklet_fn(unsigned long data) |
402 | { |
403 | struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data; |
404 | u32 int_clr; |
405 | |
406 | bcm_iproc_i2c_slave_read(iproc_i2c); |
407 | |
408 | /* clear pending IS_S_RX_EVENT_SHIFT interrupt */ |
409 | int_clr = BIT(IS_S_RX_EVENT_SHIFT); |
410 | |
411 | if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) { |
412 | /* |
413 | * In case of single byte master-read request, |
414 | * IS_S_TX_UNDERRUN_SHIFT event is generated before |
415 | * IS_S_START_BUSY_SHIFT event. Hence start slave data send |
416 | * from first IS_S_TX_UNDERRUN_SHIFT event. |
417 | * |
418 | * This means don't send any data from slave when |
419 | * IS_S_RD_EVENT_SHIFT event is generated else it will increment |
420 | * eeprom or other backend slave driver read pointer twice. |
421 | */ |
422 | iproc_i2c->tx_underrun = 0; |
423 | iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT); |
424 | |
425 | /* clear IS_S_RD_EVENT_SHIFT interrupt */ |
426 | int_clr |= BIT(IS_S_RD_EVENT_SHIFT); |
427 | } |
428 | |
429 | /* clear slave interrupt */ |
430 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: int_clr); |
431 | /* enable slave interrupts */ |
432 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: iproc_i2c->slave_int_mask); |
433 | } |
434 | |
435 | static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, |
436 | u32 status) |
437 | { |
438 | u32 val; |
439 | u8 value; |
440 | |
441 | |
442 | if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) { |
443 | iproc_i2c->tx_underrun++; |
444 | if (iproc_i2c->tx_underrun == 1) |
445 | /* Start of SMBUS for Master Read */ |
446 | i2c_slave_event(client: iproc_i2c->slave, |
447 | event: I2C_SLAVE_READ_REQUESTED, |
448 | val: &value); |
449 | else |
450 | /* Master read other than start */ |
451 | i2c_slave_event(client: iproc_i2c->slave, |
452 | event: I2C_SLAVE_READ_PROCESSED, |
453 | val: &value); |
454 | |
455 | iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val: value); |
456 | /* start transfer */ |
457 | val = BIT(S_CMD_START_BUSY_SHIFT); |
458 | iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); |
459 | |
460 | /* clear interrupt */ |
461 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, |
462 | BIT(IS_S_TX_UNDERRUN_SHIFT)); |
463 | } |
464 | |
465 | /* Stop received from master in case of master read transaction */ |
466 | if (status & BIT(IS_S_START_BUSY_SHIFT)) { |
467 | /* |
468 | * Disable interrupt for TX FIFO becomes empty and |
469 | * less than PKT_LENGTH bytes were output on the SMBUS |
470 | */ |
471 | iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); |
472 | val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
473 | val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); |
474 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); |
475 | |
476 | /* End of SMBUS for Master Read */ |
477 | val = BIT(S_TX_WR_STATUS_SHIFT); |
478 | iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val); |
479 | |
480 | val = BIT(S_CMD_START_BUSY_SHIFT); |
481 | iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); |
482 | |
483 | /* flush TX FIFOs */ |
484 | val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET); |
485 | val |= (BIT(S_FIFO_TX_FLUSH_SHIFT)); |
486 | iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); |
487 | |
488 | i2c_slave_event(client: iproc_i2c->slave, event: I2C_SLAVE_STOP, val: &value); |
489 | |
490 | /* clear interrupt */ |
491 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, |
492 | BIT(IS_S_START_BUSY_SHIFT)); |
493 | } |
494 | |
495 | /* if the controller has been reset, immediately return from the ISR */ |
496 | if (bcm_iproc_i2c_check_slave_status(iproc_i2c, status)) |
497 | return true; |
498 | |
499 | /* |
500 | * Slave events in case of master-write, master-write-read and, |
501 | * master-read |
502 | * |
503 | * Master-write : only IS_S_RX_EVENT_SHIFT event |
504 | * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT |
505 | * events |
506 | * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT |
507 | * events or only IS_S_RD_EVENT_SHIFT |
508 | * |
509 | * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt |
510 | * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes |
511 | * full. This can happen if Master issues write requests of more than |
512 | * 64 bytes. |
513 | */ |
514 | if (status & BIT(IS_S_RX_EVENT_SHIFT) || |
515 | status & BIT(IS_S_RD_EVENT_SHIFT) || |
516 | status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) { |
517 | /* disable slave interrupts */ |
518 | val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
519 | val &= ~iproc_i2c->slave_int_mask; |
520 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); |
521 | |
522 | if (status & BIT(IS_S_RD_EVENT_SHIFT)) |
523 | /* Master-write-read request */ |
524 | iproc_i2c->slave_rx_only = false; |
525 | else |
526 | /* Master-write request only */ |
527 | iproc_i2c->slave_rx_only = true; |
528 | |
529 | /* schedule tasklet to read data later */ |
530 | tasklet_schedule(t: &iproc_i2c->slave_rx_tasklet); |
531 | |
532 | /* clear IS_S_RX_FIFO_FULL_SHIFT interrupt */ |
533 | if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) { |
534 | val = BIT(IS_S_RX_FIFO_FULL_SHIFT); |
535 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val); |
536 | } |
537 | } |
538 | |
539 | return true; |
540 | } |
541 | |
542 | static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) |
543 | { |
544 | struct i2c_msg *msg = iproc_i2c->msg; |
545 | uint32_t val; |
546 | |
547 | /* Read valid data from RX FIFO */ |
548 | while (iproc_i2c->rx_bytes < msg->len) { |
549 | val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET); |
550 | |
551 | /* rx fifo empty */ |
552 | if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) |
553 | break; |
554 | |
555 | msg->buf[iproc_i2c->rx_bytes] = |
556 | (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK; |
557 | iproc_i2c->rx_bytes++; |
558 | } |
559 | } |
560 | |
561 | static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) |
562 | { |
563 | struct i2c_msg *msg = iproc_i2c->msg; |
564 | unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; |
565 | unsigned int i; |
566 | u32 val; |
567 | |
568 | /* can only fill up to the FIFO size */ |
569 | tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); |
570 | for (i = 0; i < tx_bytes; i++) { |
571 | /* start from where we left over */ |
572 | unsigned int idx = iproc_i2c->tx_bytes + i; |
573 | |
574 | val = msg->buf[idx]; |
575 | |
576 | /* mark the last byte */ |
577 | if (idx == msg->len - 1) { |
578 | val |= BIT(M_TX_WR_STATUS_SHIFT); |
579 | |
580 | if (iproc_i2c->irq) { |
581 | u32 tmp; |
582 | |
583 | /* |
584 | * Since this is the last byte, we should now |
585 | * disable TX FIFO underrun interrupt |
586 | */ |
587 | tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
588 | tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); |
589 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, |
590 | val: tmp); |
591 | } |
592 | } |
593 | |
594 | /* load data into TX FIFO */ |
595 | iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); |
596 | } |
597 | |
598 | /* update number of transferred bytes */ |
599 | iproc_i2c->tx_bytes += tx_bytes; |
600 | } |
601 | |
602 | static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) |
603 | { |
604 | struct i2c_msg *msg = iproc_i2c->msg; |
605 | u32 bytes_left, val; |
606 | |
607 | bcm_iproc_i2c_read_valid_bytes(iproc_i2c); |
608 | bytes_left = msg->len - iproc_i2c->rx_bytes; |
609 | if (bytes_left == 0) { |
610 | if (iproc_i2c->irq) { |
611 | /* finished reading all data, disable rx thld event */ |
612 | val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
613 | val &= ~BIT(IS_M_RX_THLD_SHIFT); |
614 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); |
615 | } |
616 | } else if (bytes_left < iproc_i2c->thld_bytes) { |
617 | /* set bytes left as threshold */ |
618 | val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); |
619 | val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); |
620 | val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); |
621 | iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); |
622 | iproc_i2c->thld_bytes = bytes_left; |
623 | } |
624 | /* |
625 | * bytes_left >= iproc_i2c->thld_bytes, |
626 | * hence no need to change the THRESHOLD SET. |
627 | * It will remain as iproc_i2c->thld_bytes itself |
628 | */ |
629 | } |
630 | |
631 | static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, |
632 | u32 status) |
633 | { |
634 | /* TX FIFO is empty and we have more data to send */ |
635 | if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) |
636 | bcm_iproc_i2c_send(iproc_i2c); |
637 | |
638 | /* RX FIFO threshold is reached and data needs to be read out */ |
639 | if (status & BIT(IS_M_RX_THLD_SHIFT)) |
640 | bcm_iproc_i2c_read(iproc_i2c); |
641 | |
642 | /* transfer is done */ |
643 | if (status & BIT(IS_M_START_BUSY_SHIFT)) { |
644 | iproc_i2c->xfer_is_done = 1; |
645 | if (iproc_i2c->irq) |
646 | complete(&iproc_i2c->done); |
647 | } |
648 | } |
649 | |
650 | static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) |
651 | { |
652 | struct bcm_iproc_i2c_dev *iproc_i2c = data; |
653 | u32 slave_status; |
654 | u32 status; |
655 | bool ret; |
656 | |
657 | status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET); |
658 | /* process only slave interrupt which are enabled */ |
659 | slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) & |
660 | ISR_MASK_SLAVE; |
661 | |
662 | if (slave_status) { |
663 | ret = bcm_iproc_i2c_slave_isr(iproc_i2c, status: slave_status); |
664 | if (ret) |
665 | return IRQ_HANDLED; |
666 | else |
667 | return IRQ_NONE; |
668 | } |
669 | |
670 | status &= ISR_MASK; |
671 | if (!status) |
672 | return IRQ_NONE; |
673 | |
674 | /* process all master based events */ |
675 | bcm_iproc_i2c_process_m_event(iproc_i2c, status); |
676 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: status); |
677 | |
678 | return IRQ_HANDLED; |
679 | } |
680 | |
681 | static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) |
682 | { |
683 | u32 val; |
684 | |
685 | /* put controller in reset */ |
686 | val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); |
687 | val |= BIT(CFG_RESET_SHIFT); |
688 | val &= ~(BIT(CFG_EN_SHIFT)); |
689 | iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); |
690 | |
691 | /* wait 100 usec per spec */ |
692 | udelay(100); |
693 | |
694 | /* bring controller out of reset */ |
695 | val &= ~(BIT(CFG_RESET_SHIFT)); |
696 | iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); |
697 | |
698 | /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ |
699 | val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); |
700 | iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); |
701 | /* disable all interrupts */ |
702 | val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
703 | val &= ~(IE_M_ALL_INTERRUPT_MASK << |
704 | IE_M_ALL_INTERRUPT_SHIFT); |
705 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); |
706 | |
707 | /* clear all pending interrupts */ |
708 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: 0xffffffff); |
709 | |
710 | return 0; |
711 | } |
712 | |
713 | static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, |
714 | bool enable) |
715 | { |
716 | u32 val; |
717 | |
718 | val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); |
719 | if (enable) |
720 | val |= BIT(CFG_EN_SHIFT); |
721 | else |
722 | val &= ~BIT(CFG_EN_SHIFT); |
723 | iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); |
724 | } |
725 | |
726 | static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, |
727 | struct i2c_msg *msg) |
728 | { |
729 | u32 val; |
730 | |
731 | val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); |
732 | val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; |
733 | |
734 | switch (val) { |
735 | case M_CMD_STATUS_SUCCESS: |
736 | return 0; |
737 | |
738 | case M_CMD_STATUS_LOST_ARB: |
739 | dev_dbg(iproc_i2c->device, "lost bus arbitration\n" ); |
740 | return -EAGAIN; |
741 | |
742 | case M_CMD_STATUS_NACK_ADDR: |
743 | dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n" , msg->addr); |
744 | return -ENXIO; |
745 | |
746 | case M_CMD_STATUS_NACK_DATA: |
747 | dev_dbg(iproc_i2c->device, "NAK data\n" ); |
748 | return -ENXIO; |
749 | |
750 | case M_CMD_STATUS_TIMEOUT: |
751 | dev_dbg(iproc_i2c->device, "bus timeout\n" ); |
752 | return -ETIMEDOUT; |
753 | |
754 | case M_CMD_STATUS_FIFO_UNDERRUN: |
755 | dev_dbg(iproc_i2c->device, "FIFO under-run\n" ); |
756 | return -ENXIO; |
757 | |
758 | case M_CMD_STATUS_RX_FIFO_FULL: |
759 | dev_dbg(iproc_i2c->device, "RX FIFO full\n" ); |
760 | return -ETIMEDOUT; |
761 | |
762 | default: |
763 | dev_dbg(iproc_i2c->device, "unknown error code=%d\n" , val); |
764 | |
765 | /* re-initialize i2c for recovery */ |
766 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false); |
767 | bcm_iproc_i2c_init(iproc_i2c); |
768 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true); |
769 | |
770 | return -EIO; |
771 | } |
772 | } |
773 | |
774 | static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, |
775 | struct i2c_msg *msg, |
776 | u32 cmd) |
777 | { |
778 | unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); |
779 | u32 val, status; |
780 | int ret; |
781 | |
782 | iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, val: cmd); |
783 | |
784 | if (iproc_i2c->irq) { |
785 | time_left = wait_for_completion_timeout(x: &iproc_i2c->done, |
786 | timeout: time_left); |
787 | /* disable all interrupts */ |
788 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: 0); |
789 | /* read it back to flush the write */ |
790 | iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
791 | /* make sure the interrupt handler isn't running */ |
792 | synchronize_irq(irq: iproc_i2c->irq); |
793 | |
794 | } else { /* polling mode */ |
795 | unsigned long timeout = jiffies + time_left; |
796 | |
797 | do { |
798 | status = iproc_i2c_rd_reg(iproc_i2c, |
799 | IS_OFFSET) & ISR_MASK; |
800 | bcm_iproc_i2c_process_m_event(iproc_i2c, status); |
801 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val: status); |
802 | |
803 | if (time_after(jiffies, timeout)) { |
804 | time_left = 0; |
805 | break; |
806 | } |
807 | |
808 | cpu_relax(); |
809 | cond_resched(); |
810 | } while (!iproc_i2c->xfer_is_done); |
811 | } |
812 | |
813 | if (!time_left && !iproc_i2c->xfer_is_done) { |
814 | dev_err(iproc_i2c->device, "transaction timed out\n" ); |
815 | |
816 | /* flush both TX/RX FIFOs */ |
817 | val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); |
818 | iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); |
819 | return -ETIMEDOUT; |
820 | } |
821 | |
822 | ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); |
823 | if (ret) { |
824 | /* flush both TX/RX FIFOs */ |
825 | val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); |
826 | iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); |
827 | return ret; |
828 | } |
829 | |
830 | return 0; |
831 | } |
832 | |
833 | /* |
834 | * If 'process_call' is true, then this is a multi-msg transfer that requires |
835 | * a repeated start between the messages. |
836 | * More specifically, it must be a write (reg) followed by a read (data). |
837 | * The i2c quirks are set to enforce this rule. |
838 | */ |
839 | static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, |
840 | struct i2c_msg *msgs, bool process_call) |
841 | { |
842 | int i; |
843 | u8 addr; |
844 | u32 val, tmp, val_intr_en; |
845 | unsigned int tx_bytes; |
846 | struct i2c_msg *msg = &msgs[0]; |
847 | |
848 | /* check if bus is busy */ |
849 | if (!!(iproc_i2c_rd_reg(iproc_i2c, |
850 | M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { |
851 | dev_warn(iproc_i2c->device, "bus is busy\n" ); |
852 | return -EBUSY; |
853 | } |
854 | |
855 | iproc_i2c->msg = msg; |
856 | |
857 | /* format and load slave address into the TX FIFO */ |
858 | addr = i2c_8bit_addr_from_msg(msg); |
859 | iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val: addr); |
860 | |
861 | /* |
862 | * For a write transaction, load data into the TX FIFO. Only allow |
863 | * loading up to TX FIFO size - 1 bytes of data since the first byte |
864 | * has been used up by the slave address |
865 | */ |
866 | tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1); |
867 | if (!(msg->flags & I2C_M_RD)) { |
868 | for (i = 0; i < tx_bytes; i++) { |
869 | val = msg->buf[i]; |
870 | |
871 | /* mark the last byte */ |
872 | if (!process_call && (i == msg->len - 1)) |
873 | val |= BIT(M_TX_WR_STATUS_SHIFT); |
874 | |
875 | iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); |
876 | } |
877 | iproc_i2c->tx_bytes = tx_bytes; |
878 | } |
879 | |
880 | /* Process the read message if this is process call */ |
881 | if (process_call) { |
882 | msg++; |
883 | iproc_i2c->msg = msg; /* point to second msg */ |
884 | |
885 | /* |
886 | * The last byte to be sent out should be a slave |
887 | * address with read operation |
888 | */ |
889 | addr = i2c_8bit_addr_from_msg(msg); |
890 | /* mark it the last byte out */ |
891 | val = addr | BIT(M_TX_WR_STATUS_SHIFT); |
892 | iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); |
893 | } |
894 | |
895 | /* mark as incomplete before starting the transaction */ |
896 | if (iproc_i2c->irq) |
897 | reinit_completion(x: &iproc_i2c->done); |
898 | |
899 | iproc_i2c->xfer_is_done = 0; |
900 | |
901 | /* |
902 | * Enable the "start busy" interrupt, which will be triggered after the |
903 | * transaction is done, i.e., the internal start_busy bit, transitions |
904 | * from 1 to 0. |
905 | */ |
906 | val_intr_en = BIT(IE_M_START_BUSY_SHIFT); |
907 | |
908 | /* |
909 | * If TX data size is larger than the TX FIFO, need to enable TX |
910 | * underrun interrupt, which will be triggerred when the TX FIFO is |
911 | * empty. When that happens we can then pump more data into the FIFO |
912 | */ |
913 | if (!process_call && !(msg->flags & I2C_M_RD) && |
914 | msg->len > iproc_i2c->tx_bytes) |
915 | val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); |
916 | |
917 | /* |
918 | * Now we can activate the transfer. For a read operation, specify the |
919 | * number of bytes to read |
920 | */ |
921 | val = BIT(M_CMD_START_BUSY_SHIFT); |
922 | |
923 | if (msg->len == 0) { |
924 | /* SMBUS QUICK Command (Read/Write) */ |
925 | val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT); |
926 | } else if (msg->flags & I2C_M_RD) { |
927 | u32 protocol; |
928 | |
929 | iproc_i2c->rx_bytes = 0; |
930 | if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) |
931 | iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; |
932 | else |
933 | iproc_i2c->thld_bytes = msg->len; |
934 | |
935 | /* set threshold value */ |
936 | tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); |
937 | tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); |
938 | tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; |
939 | iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val: tmp); |
940 | |
941 | /* enable the RX threshold interrupt */ |
942 | val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); |
943 | |
944 | protocol = process_call ? |
945 | M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD; |
946 | |
947 | val |= (protocol << M_CMD_PROTOCOL_SHIFT) | |
948 | (msg->len << M_CMD_RD_CNT_SHIFT); |
949 | } else { |
950 | val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); |
951 | } |
952 | |
953 | if (iproc_i2c->irq) |
954 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: val_intr_en); |
955 | |
956 | return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, cmd: val); |
957 | } |
958 | |
959 | static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, |
960 | struct i2c_msg msgs[], int num) |
961 | { |
962 | struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap: adapter); |
963 | bool process_call = false; |
964 | int ret; |
965 | |
966 | if (num == 2) { |
967 | /* Repeated start, use process call */ |
968 | process_call = true; |
969 | if (msgs[1].flags & I2C_M_NOSTART) { |
970 | dev_err(iproc_i2c->device, "Invalid repeated start\n" ); |
971 | return -EOPNOTSUPP; |
972 | } |
973 | } |
974 | |
975 | ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call); |
976 | if (ret) { |
977 | dev_dbg(iproc_i2c->device, "xfer failed\n" ); |
978 | return ret; |
979 | } |
980 | |
981 | return num; |
982 | } |
983 | |
984 | static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) |
985 | { |
986 | u32 val; |
987 | |
988 | val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
989 | |
990 | if (adap->algo->reg_slave) |
991 | val |= I2C_FUNC_SLAVE; |
992 | |
993 | return val; |
994 | } |
995 | |
996 | static struct i2c_algorithm bcm_iproc_algo = { |
997 | .master_xfer = bcm_iproc_i2c_xfer, |
998 | .functionality = bcm_iproc_i2c_functionality, |
999 | .reg_slave = bcm_iproc_i2c_reg_slave, |
1000 | .unreg_slave = bcm_iproc_i2c_unreg_slave, |
1001 | }; |
1002 | |
1003 | static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { |
1004 | .flags = I2C_AQ_COMB_WRITE_THEN_READ, |
1005 | .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE, |
1006 | .max_read_len = M_RX_MAX_READ_LEN, |
1007 | }; |
1008 | |
1009 | static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) |
1010 | { |
1011 | unsigned int bus_speed; |
1012 | u32 val; |
1013 | int ret = of_property_read_u32(np: iproc_i2c->device->of_node, |
1014 | propname: "clock-frequency" , out_value: &bus_speed); |
1015 | if (ret < 0) { |
1016 | dev_info(iproc_i2c->device, |
1017 | "unable to interpret clock-frequency DT property\n" ); |
1018 | bus_speed = I2C_MAX_STANDARD_MODE_FREQ; |
1019 | } |
1020 | |
1021 | if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) { |
1022 | dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n" , |
1023 | bus_speed); |
1024 | dev_err(iproc_i2c->device, |
1025 | "valid speeds are 100khz and 400khz\n" ); |
1026 | return -EINVAL; |
1027 | } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) { |
1028 | bus_speed = I2C_MAX_STANDARD_MODE_FREQ; |
1029 | } else { |
1030 | bus_speed = I2C_MAX_FAST_MODE_FREQ; |
1031 | } |
1032 | |
1033 | iproc_i2c->bus_speed = bus_speed; |
1034 | val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); |
1035 | val &= ~BIT(TIM_CFG_MODE_400_SHIFT); |
1036 | val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT; |
1037 | iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); |
1038 | |
1039 | dev_info(iproc_i2c->device, "bus set to %u Hz\n" , bus_speed); |
1040 | |
1041 | return 0; |
1042 | } |
1043 | |
1044 | static int bcm_iproc_i2c_probe(struct platform_device *pdev) |
1045 | { |
1046 | int irq, ret = 0; |
1047 | struct bcm_iproc_i2c_dev *iproc_i2c; |
1048 | struct i2c_adapter *adap; |
1049 | |
1050 | iproc_i2c = devm_kzalloc(dev: &pdev->dev, size: sizeof(*iproc_i2c), |
1051 | GFP_KERNEL); |
1052 | if (!iproc_i2c) |
1053 | return -ENOMEM; |
1054 | |
1055 | platform_set_drvdata(pdev, data: iproc_i2c); |
1056 | iproc_i2c->device = &pdev->dev; |
1057 | iproc_i2c->type = |
1058 | (enum bcm_iproc_i2c_type)of_device_get_match_data(dev: &pdev->dev); |
1059 | init_completion(x: &iproc_i2c->done); |
1060 | |
1061 | iproc_i2c->base = devm_platform_ioremap_resource(pdev, index: 0); |
1062 | if (IS_ERR(ptr: iproc_i2c->base)) |
1063 | return PTR_ERR(ptr: iproc_i2c->base); |
1064 | |
1065 | if (iproc_i2c->type == IPROC_I2C_NIC) { |
1066 | iproc_i2c->idm_base = devm_platform_ioremap_resource(pdev, index: 1); |
1067 | if (IS_ERR(ptr: iproc_i2c->idm_base)) |
1068 | return PTR_ERR(ptr: iproc_i2c->idm_base); |
1069 | |
1070 | ret = of_property_read_u32(np: iproc_i2c->device->of_node, |
1071 | propname: "brcm,ape-hsls-addr-mask" , |
1072 | out_value: &iproc_i2c->ape_addr_mask); |
1073 | if (ret < 0) { |
1074 | dev_err(iproc_i2c->device, |
1075 | "'brcm,ape-hsls-addr-mask' missing\n" ); |
1076 | return -EINVAL; |
1077 | } |
1078 | |
1079 | spin_lock_init(&iproc_i2c->idm_lock); |
1080 | |
1081 | /* no slave support */ |
1082 | bcm_iproc_algo.reg_slave = NULL; |
1083 | bcm_iproc_algo.unreg_slave = NULL; |
1084 | } |
1085 | |
1086 | ret = bcm_iproc_i2c_init(iproc_i2c); |
1087 | if (ret) |
1088 | return ret; |
1089 | |
1090 | ret = bcm_iproc_i2c_cfg_speed(iproc_i2c); |
1091 | if (ret) |
1092 | return ret; |
1093 | |
1094 | irq = platform_get_irq(pdev, 0); |
1095 | if (irq > 0) { |
1096 | ret = devm_request_irq(dev: iproc_i2c->device, irq, |
1097 | handler: bcm_iproc_i2c_isr, irqflags: 0, devname: pdev->name, |
1098 | dev_id: iproc_i2c); |
1099 | if (ret < 0) { |
1100 | dev_err(iproc_i2c->device, |
1101 | "unable to request irq %i\n" , irq); |
1102 | return ret; |
1103 | } |
1104 | |
1105 | iproc_i2c->irq = irq; |
1106 | } else { |
1107 | dev_warn(iproc_i2c->device, |
1108 | "no irq resource, falling back to poll mode\n" ); |
1109 | } |
1110 | |
1111 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true); |
1112 | |
1113 | adap = &iproc_i2c->adapter; |
1114 | i2c_set_adapdata(adap, data: iproc_i2c); |
1115 | snprintf(buf: adap->name, size: sizeof(adap->name), |
1116 | fmt: "Broadcom iProc (%s)" , |
1117 | of_node_full_name(np: iproc_i2c->device->of_node)); |
1118 | adap->algo = &bcm_iproc_algo; |
1119 | adap->quirks = &bcm_iproc_i2c_quirks; |
1120 | adap->dev.parent = &pdev->dev; |
1121 | adap->dev.of_node = pdev->dev.of_node; |
1122 | |
1123 | return i2c_add_adapter(adap); |
1124 | } |
1125 | |
1126 | static void bcm_iproc_i2c_remove(struct platform_device *pdev) |
1127 | { |
1128 | struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); |
1129 | |
1130 | if (iproc_i2c->irq) { |
1131 | /* |
1132 | * Make sure there's no pending interrupt when we remove the |
1133 | * adapter |
1134 | */ |
1135 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: 0); |
1136 | iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
1137 | synchronize_irq(irq: iproc_i2c->irq); |
1138 | } |
1139 | |
1140 | i2c_del_adapter(adap: &iproc_i2c->adapter); |
1141 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false); |
1142 | } |
1143 | |
1144 | static int bcm_iproc_i2c_suspend(struct device *dev) |
1145 | { |
1146 | struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); |
1147 | |
1148 | if (iproc_i2c->irq) { |
1149 | /* |
1150 | * Make sure there's no pending interrupt when we go into |
1151 | * suspend |
1152 | */ |
1153 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: 0); |
1154 | iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
1155 | synchronize_irq(irq: iproc_i2c->irq); |
1156 | } |
1157 | |
1158 | /* now disable the controller */ |
1159 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: false); |
1160 | |
1161 | return 0; |
1162 | } |
1163 | |
1164 | static int bcm_iproc_i2c_resume(struct device *dev) |
1165 | { |
1166 | struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); |
1167 | int ret; |
1168 | u32 val; |
1169 | |
1170 | /* |
1171 | * Power domain could have been shut off completely in system deep |
1172 | * sleep, so re-initialize the block here |
1173 | */ |
1174 | ret = bcm_iproc_i2c_init(iproc_i2c); |
1175 | if (ret) |
1176 | return ret; |
1177 | |
1178 | /* configure to the desired bus speed */ |
1179 | val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); |
1180 | val &= ~BIT(TIM_CFG_MODE_400_SHIFT); |
1181 | val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT; |
1182 | iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); |
1183 | |
1184 | bcm_iproc_i2c_enable_disable(iproc_i2c, enable: true); |
1185 | |
1186 | return 0; |
1187 | } |
1188 | |
1189 | static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = { |
1190 | .suspend_late = &bcm_iproc_i2c_suspend, |
1191 | .resume_early = &bcm_iproc_i2c_resume |
1192 | }; |
1193 | |
1194 | static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) |
1195 | { |
1196 | struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap: slave->adapter); |
1197 | |
1198 | if (iproc_i2c->slave) |
1199 | return -EBUSY; |
1200 | |
1201 | if (slave->flags & I2C_CLIENT_TEN) |
1202 | return -EAFNOSUPPORT; |
1203 | |
1204 | iproc_i2c->slave = slave; |
1205 | |
1206 | tasklet_init(t: &iproc_i2c->slave_rx_tasklet, func: slave_rx_tasklet_fn, |
1207 | data: (unsigned long)iproc_i2c); |
1208 | |
1209 | bcm_iproc_i2c_slave_init(iproc_i2c, need_reset: false); |
1210 | return 0; |
1211 | } |
1212 | |
1213 | static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) |
1214 | { |
1215 | u32 tmp; |
1216 | struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap: slave->adapter); |
1217 | |
1218 | if (!iproc_i2c->slave) |
1219 | return -EINVAL; |
1220 | |
1221 | disable_irq(irq: iproc_i2c->irq); |
1222 | |
1223 | tasklet_kill(t: &iproc_i2c->slave_rx_tasklet); |
1224 | |
1225 | /* disable all slave interrupts */ |
1226 | tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); |
1227 | tmp &= ~(IE_S_ALL_INTERRUPT_MASK << |
1228 | IE_S_ALL_INTERRUPT_SHIFT); |
1229 | iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val: tmp); |
1230 | |
1231 | /* Erase the slave address programmed */ |
1232 | tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); |
1233 | tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); |
1234 | iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val: tmp); |
1235 | |
1236 | /* flush TX/RX FIFOs */ |
1237 | tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); |
1238 | iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val: tmp); |
1239 | |
1240 | /* clear all pending slave interrupts */ |
1241 | iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); |
1242 | |
1243 | iproc_i2c->slave = NULL; |
1244 | |
1245 | enable_irq(irq: iproc_i2c->irq); |
1246 | |
1247 | return 0; |
1248 | } |
1249 | |
1250 | static const struct of_device_id bcm_iproc_i2c_of_match[] = { |
1251 | { |
1252 | .compatible = "brcm,iproc-i2c" , |
1253 | .data = (int *)IPROC_I2C, |
1254 | }, { |
1255 | .compatible = "brcm,iproc-nic-i2c" , |
1256 | .data = (int *)IPROC_I2C_NIC, |
1257 | }, |
1258 | { /* sentinel */ } |
1259 | }; |
1260 | MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); |
1261 | |
1262 | static struct platform_driver bcm_iproc_i2c_driver = { |
1263 | .driver = { |
1264 | .name = "bcm-iproc-i2c" , |
1265 | .of_match_table = bcm_iproc_i2c_of_match, |
1266 | .pm = pm_sleep_ptr(&bcm_iproc_i2c_pm_ops), |
1267 | }, |
1268 | .probe = bcm_iproc_i2c_probe, |
1269 | .remove_new = bcm_iproc_i2c_remove, |
1270 | }; |
1271 | module_platform_driver(bcm_iproc_i2c_driver); |
1272 | |
1273 | MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>" ); |
1274 | MODULE_DESCRIPTION("Broadcom iProc I2C Driver" ); |
1275 | MODULE_LICENSE("GPL v2" ); |
1276 | |