1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2009 ST-Ericsson SA |
4 | * Copyright (C) 2009 STMicroelectronics |
5 | * |
6 | * I2C master mode controller driver, used in Nomadik 8815 |
7 | * and Ux500 platforms. |
8 | * |
9 | * The Mobileye EyeQ5 platform is also supported; it uses |
10 | * the same Ux500/DB8500 IP block with two quirks: |
11 | * - The memory bus only supports 32-bit accesses. |
12 | * - A register must be configured for the I2C speed mode; |
13 | * it is located in a shared register region called OLB. |
14 | * |
15 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> |
16 | * Author: Sachin Verma <sachin.verma@st.com> |
17 | */ |
18 | #include <linux/amba/bus.h> |
19 | #include <linux/bitfield.h> |
20 | #include <linux/clk.h> |
21 | #include <linux/err.h> |
22 | #include <linux/i2c.h> |
23 | #include <linux/init.h> |
24 | #include <linux/interrupt.h> |
25 | #include <linux/io.h> |
26 | #include <linux/mfd/syscon.h> |
27 | #include <linux/module.h> |
28 | #include <linux/of.h> |
29 | #include <linux/pinctrl/consumer.h> |
30 | #include <linux/pm_runtime.h> |
31 | #include <linux/regmap.h> |
32 | #include <linux/slab.h> |
33 | |
34 | #define DRIVER_NAME "nmk-i2c" |
35 | |
36 | /* I2C Controller register offsets */ |
37 | #define I2C_CR (0x000) |
38 | #define I2C_SCR (0x004) |
39 | #define I2C_HSMCR (0x008) |
40 | #define I2C_MCR (0x00C) |
41 | #define I2C_TFR (0x010) |
42 | #define I2C_SR (0x014) |
43 | #define I2C_RFR (0x018) |
44 | #define I2C_TFTR (0x01C) |
45 | #define I2C_RFTR (0x020) |
46 | #define I2C_DMAR (0x024) |
47 | #define I2C_BRCR (0x028) |
48 | #define I2C_IMSCR (0x02C) |
49 | #define I2C_RISR (0x030) |
50 | #define I2C_MISR (0x034) |
51 | #define I2C_ICR (0x038) |
52 | |
53 | /* Control registers */ |
54 | #define I2C_CR_PE BIT(0) /* Peripheral Enable */ |
55 | #define I2C_CR_OM GENMASK(2, 1) /* Operating mode */ |
56 | #define I2C_CR_SAM BIT(3) /* Slave addressing mode */ |
57 | #define I2C_CR_SM GENMASK(5, 4) /* Speed mode */ |
58 | #define I2C_CR_SGCM BIT(6) /* Slave general call mode */ |
59 | #define I2C_CR_FTX BIT(7) /* Flush Transmit */ |
60 | #define I2C_CR_FRX BIT(8) /* Flush Receive */ |
61 | #define I2C_CR_DMA_TX_EN BIT(9) /* DMA Tx enable */ |
62 | #define I2C_CR_DMA_RX_EN BIT(10) /* DMA Rx Enable */ |
63 | #define I2C_CR_DMA_SLE BIT(11) /* DMA sync. logic enable */ |
64 | #define I2C_CR_LM BIT(12) /* Loopback mode */ |
65 | #define I2C_CR_FON GENMASK(14, 13) /* Filtering on */ |
66 | #define I2C_CR_FS GENMASK(16, 15) /* Force stop enable */ |
67 | |
68 | /* Slave control register (SCR) */ |
69 | #define I2C_SCR_SLSU GENMASK(31, 16) /* Slave data setup time */ |
70 | |
71 | /* Master controller (MCR) register */ |
72 | #define I2C_MCR_OP BIT(0) /* Operation */ |
73 | #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */ |
74 | #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */ |
75 | #define I2C_MCR_SB BIT(11) /* Extended address */ |
76 | #define I2C_MCR_AM GENMASK(13, 12) /* Address type */ |
77 | #define I2C_MCR_STOP BIT(14) /* Stop condition */ |
78 | #define I2C_MCR_LENGTH GENMASK(25, 15) /* Transaction length */ |
79 | |
80 | /* Status register (SR) */ |
81 | #define I2C_SR_OP GENMASK(1, 0) /* Operation */ |
82 | #define I2C_SR_STATUS GENMASK(3, 2) /* controller status */ |
83 | #define I2C_SR_CAUSE GENMASK(6, 4) /* Abort cause */ |
84 | #define I2C_SR_TYPE GENMASK(8, 7) /* Receive type */ |
85 | #define I2C_SR_LENGTH GENMASK(19, 9) /* Transfer length */ |
86 | |
87 | /* Baud-rate counter register (BRCR) */ |
88 | #define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */ |
89 | #define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */ |
90 | |
91 | /* Interrupt mask set/clear (IMSCR) bits */ |
92 | #define I2C_IT_TXFE BIT(0) |
93 | #define I2C_IT_TXFNE BIT(1) |
94 | #define I2C_IT_TXFF BIT(2) |
95 | #define I2C_IT_TXFOVR BIT(3) |
96 | #define I2C_IT_RXFE BIT(4) |
97 | #define I2C_IT_RXFNF BIT(5) |
98 | #define I2C_IT_RXFF BIT(6) |
99 | #define I2C_IT_RFSR BIT(16) |
100 | #define I2C_IT_RFSE BIT(17) |
101 | #define I2C_IT_WTSR BIT(18) |
102 | #define I2C_IT_MTD BIT(19) |
103 | #define I2C_IT_STD BIT(20) |
104 | #define I2C_IT_MAL BIT(24) |
105 | #define I2C_IT_BERR BIT(25) |
106 | #define I2C_IT_MTDWS BIT(28) |
107 | |
108 | /* some bits in ICR are reserved */ |
109 | #define I2C_CLEAR_ALL_INTS 0x131f007f |
110 | |
111 | /* maximum threshold value */ |
112 | #define MAX_I2C_FIFO_THRESHOLD 15 |
113 | |
114 | enum i2c_freq_mode { |
115 | I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */ |
116 | I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */ |
117 | I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */ |
118 | I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */ |
119 | }; |
120 | |
121 | /* Mobileye EyeQ5 offset into a shared register region (called OLB) */ |
122 | #define NMK_I2C_EYEQ5_OLB_IOCR2 0x0B8 |
123 | |
124 | enum i2c_eyeq5_speed { |
125 | I2C_EYEQ5_SPEED_FAST, |
126 | I2C_EYEQ5_SPEED_FAST_PLUS, |
127 | I2C_EYEQ5_SPEED_HIGH_SPEED, |
128 | }; |
129 | |
130 | /** |
131 | * struct i2c_vendor_data - per-vendor variations |
132 | * @has_mtdws: variant has the MTDWS bit |
133 | * @fifodepth: variant FIFO depth |
134 | */ |
135 | struct i2c_vendor_data { |
136 | bool has_mtdws; |
137 | u32 fifodepth; |
138 | }; |
139 | |
140 | enum i2c_status { |
141 | I2C_NOP, |
142 | I2C_ON_GOING, |
143 | I2C_OK, |
144 | I2C_ABORT |
145 | }; |
146 | |
147 | /* operation */ |
148 | enum i2c_operation { |
149 | I2C_NO_OPERATION = 0xff, |
150 | I2C_WRITE = 0x00, |
151 | I2C_READ = 0x01 |
152 | }; |
153 | |
154 | enum i2c_operating_mode { |
155 | I2C_OM_SLAVE, |
156 | I2C_OM_MASTER, |
157 | I2C_OM_MASTER_OR_SLAVE, |
158 | }; |
159 | |
160 | /** |
161 | * struct i2c_nmk_client - client specific data |
162 | * @slave_adr: 7-bit slave address |
163 | * @count: no. bytes to be transferred |
164 | * @buffer: client data buffer |
165 | * @xfer_bytes: bytes transferred till now |
166 | * @operation: current I2C operation |
167 | */ |
168 | struct i2c_nmk_client { |
169 | unsigned short slave_adr; |
170 | unsigned long count; |
171 | unsigned char *buffer; |
172 | unsigned long xfer_bytes; |
173 | enum i2c_operation operation; |
174 | }; |
175 | |
176 | /** |
177 | * struct nmk_i2c_dev - private data structure of the controller. |
178 | * @vendor: vendor data for this variant. |
179 | * @adev: parent amba device. |
180 | * @adap: corresponding I2C adapter. |
181 | * @irq: interrupt line for the controller. |
182 | * @virtbase: virtual io memory area. |
183 | * @clk: hardware i2c block clock. |
184 | * @cli: holder of client specific data. |
185 | * @clk_freq: clock frequency for the operation mode |
186 | * @tft: Tx FIFO Threshold in bytes |
187 | * @rft: Rx FIFO Threshold in bytes |
188 | * @timeout_usecs: Slave response timeout |
189 | * @sm: speed mode |
190 | * @stop: stop condition. |
191 | * @xfer_wq: xfer done wait queue. |
192 | * @xfer_done: xfer done boolean. |
193 | * @result: controller propogated result. |
194 | * @has_32b_bus: controller is on a bus that only supports 32-bit accesses. |
195 | */ |
196 | struct nmk_i2c_dev { |
197 | struct i2c_vendor_data *vendor; |
198 | struct amba_device *adev; |
199 | struct i2c_adapter adap; |
200 | int irq; |
201 | void __iomem *virtbase; |
202 | struct clk *clk; |
203 | struct i2c_nmk_client cli; |
204 | u32 clk_freq; |
205 | unsigned char tft; |
206 | unsigned char rft; |
207 | u32 timeout_usecs; |
208 | enum i2c_freq_mode sm; |
209 | int stop; |
210 | struct wait_queue_head xfer_wq; |
211 | bool xfer_done; |
212 | int result; |
213 | bool has_32b_bus; |
214 | }; |
215 | |
216 | /* controller's abort causes */ |
217 | static const char *abort_causes[] = { |
218 | "no ack received after address transmission" , |
219 | "no ack received during data phase" , |
220 | "ack received after xmission of master code" , |
221 | "master lost arbitration" , |
222 | "slave restarts" , |
223 | "slave reset" , |
224 | "overflow, maxsize is 2047 bytes" , |
225 | }; |
226 | |
227 | static inline void i2c_set_bit(void __iomem *reg, u32 mask) |
228 | { |
229 | writel(readl(addr: reg) | mask, addr: reg); |
230 | } |
231 | |
232 | static inline void i2c_clr_bit(void __iomem *reg, u32 mask) |
233 | { |
234 | writel(readl(addr: reg) & ~mask, addr: reg); |
235 | } |
236 | |
237 | static inline u8 nmk_i2c_readb(const struct nmk_i2c_dev *priv, |
238 | unsigned long reg) |
239 | { |
240 | if (priv->has_32b_bus) |
241 | return readl(addr: priv->virtbase + reg); |
242 | else |
243 | return readb(addr: priv->virtbase + reg); |
244 | } |
245 | |
246 | static inline void nmk_i2c_writeb(const struct nmk_i2c_dev *priv, u32 val, |
247 | unsigned long reg) |
248 | { |
249 | if (priv->has_32b_bus) |
250 | writel(val, addr: priv->virtbase + reg); |
251 | else |
252 | writeb(val, addr: priv->virtbase + reg); |
253 | } |
254 | |
255 | /** |
256 | * flush_i2c_fifo() - This function flushes the I2C FIFO |
257 | * @priv: private data of I2C Driver |
258 | * |
259 | * This function flushes the I2C Tx and Rx FIFOs. It returns |
260 | * 0 on successful flushing of FIFO |
261 | */ |
262 | static int flush_i2c_fifo(struct nmk_i2c_dev *priv) |
263 | { |
264 | #define LOOP_ATTEMPTS 10 |
265 | ktime_t timeout; |
266 | int i; |
267 | |
268 | /* |
269 | * flush the transmit and receive FIFO. The flushing |
270 | * operation takes several cycles before to be completed. |
271 | * On the completion, the I2C internal logic clears these |
272 | * bits, until then no one must access Tx, Rx FIFO and |
273 | * should poll on these bits waiting for the completion. |
274 | */ |
275 | writel(val: (I2C_CR_FTX | I2C_CR_FRX), addr: priv->virtbase + I2C_CR); |
276 | |
277 | for (i = 0; i < LOOP_ATTEMPTS; i++) { |
278 | timeout = ktime_add_us(kt: ktime_get(), usec: priv->timeout_usecs); |
279 | |
280 | while (ktime_after(cmp1: timeout, cmp2: ktime_get())) { |
281 | if ((readl(addr: priv->virtbase + I2C_CR) & |
282 | (I2C_CR_FTX | I2C_CR_FRX)) == 0) |
283 | return 0; |
284 | } |
285 | } |
286 | |
287 | dev_err(&priv->adev->dev, |
288 | "flushing operation timed out giving up after %d attempts" , |
289 | LOOP_ATTEMPTS); |
290 | |
291 | return -ETIMEDOUT; |
292 | } |
293 | |
294 | /** |
295 | * disable_all_interrupts() - Disable all interrupts of this I2c Bus |
296 | * @priv: private data of I2C Driver |
297 | */ |
298 | static void disable_all_interrupts(struct nmk_i2c_dev *priv) |
299 | { |
300 | writel(val: 0, addr: priv->virtbase + I2C_IMSCR); |
301 | } |
302 | |
303 | /** |
304 | * clear_all_interrupts() - Clear all interrupts of I2C Controller |
305 | * @priv: private data of I2C Driver |
306 | */ |
307 | static void clear_all_interrupts(struct nmk_i2c_dev *priv) |
308 | { |
309 | writel(I2C_CLEAR_ALL_INTS, addr: priv->virtbase + I2C_ICR); |
310 | } |
311 | |
312 | /** |
313 | * init_hw() - initialize the I2C hardware |
314 | * @priv: private data of I2C Driver |
315 | */ |
316 | static int init_hw(struct nmk_i2c_dev *priv) |
317 | { |
318 | int stat; |
319 | |
320 | stat = flush_i2c_fifo(priv); |
321 | if (stat) |
322 | goto exit; |
323 | |
324 | /* disable the controller */ |
325 | i2c_clr_bit(reg: priv->virtbase + I2C_CR, I2C_CR_PE); |
326 | |
327 | disable_all_interrupts(priv); |
328 | |
329 | clear_all_interrupts(priv); |
330 | |
331 | priv->cli.operation = I2C_NO_OPERATION; |
332 | |
333 | exit: |
334 | return stat; |
335 | } |
336 | |
337 | /* enable peripheral, master mode operation */ |
338 | #define DEFAULT_I2C_REG_CR (FIELD_PREP(I2C_CR_OM, I2C_OM_MASTER) | I2C_CR_PE) |
339 | |
340 | /* grab top three bits from extended I2C addresses */ |
341 | #define ADR_3MSB_BITS GENMASK(9, 7) |
342 | |
343 | /** |
344 | * load_i2c_mcr_reg() - load the MCR register |
345 | * @priv: private data of controller |
346 | * @flags: message flags |
347 | */ |
348 | static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags) |
349 | { |
350 | u32 mcr = 0; |
351 | unsigned short slave_adr_3msb_bits; |
352 | |
353 | mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr); |
354 | |
355 | if (unlikely(flags & I2C_M_TEN)) { |
356 | /* 10-bit address transaction */ |
357 | mcr |= FIELD_PREP(I2C_MCR_AM, 2); |
358 | /* |
359 | * Get the top 3 bits. |
360 | * EA10 represents extended address in MCR. This includes |
361 | * the extension (MSB bits) of the 7 bit address loaded |
362 | * in A7 |
363 | */ |
364 | slave_adr_3msb_bits = FIELD_GET(ADR_3MSB_BITS, |
365 | priv->cli.slave_adr); |
366 | |
367 | mcr |= FIELD_PREP(I2C_MCR_EA10, slave_adr_3msb_bits); |
368 | } else { |
369 | /* 7-bit address transaction */ |
370 | mcr |= FIELD_PREP(I2C_MCR_AM, 1); |
371 | } |
372 | |
373 | /* start byte procedure not applied */ |
374 | mcr |= FIELD_PREP(I2C_MCR_SB, 0); |
375 | |
376 | /* check the operation, master read/write? */ |
377 | if (priv->cli.operation == I2C_WRITE) |
378 | mcr |= FIELD_PREP(I2C_MCR_OP, I2C_WRITE); |
379 | else |
380 | mcr |= FIELD_PREP(I2C_MCR_OP, I2C_READ); |
381 | |
382 | /* stop or repeated start? */ |
383 | if (priv->stop) |
384 | mcr |= FIELD_PREP(I2C_MCR_STOP, 1); |
385 | else |
386 | mcr &= ~FIELD_PREP(I2C_MCR_STOP, 1); |
387 | |
388 | mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count); |
389 | |
390 | return mcr; |
391 | } |
392 | |
393 | /** |
394 | * setup_i2c_controller() - setup the controller |
395 | * @priv: private data of controller |
396 | */ |
397 | static void setup_i2c_controller(struct nmk_i2c_dev *priv) |
398 | { |
399 | u32 brcr1, brcr2; |
400 | u32 i2c_clk, div; |
401 | u32 ns; |
402 | u16 slsu; |
403 | |
404 | writel(val: 0x0, addr: priv->virtbase + I2C_CR); |
405 | writel(val: 0x0, addr: priv->virtbase + I2C_HSMCR); |
406 | writel(val: 0x0, addr: priv->virtbase + I2C_TFTR); |
407 | writel(val: 0x0, addr: priv->virtbase + I2C_RFTR); |
408 | writel(val: 0x0, addr: priv->virtbase + I2C_DMAR); |
409 | |
410 | i2c_clk = clk_get_rate(clk: priv->clk); |
411 | |
412 | /* |
413 | * set the slsu: |
414 | * |
415 | * slsu defines the data setup time after SCL clock |
416 | * stretching in terms of i2c clk cycles + 1 (zero means |
417 | * "wait one cycle"), the needed setup time for the three |
418 | * modes are 250ns, 100ns, 10ns respectively. |
419 | * |
420 | * As the time for one cycle T in nanoseconds is |
421 | * T = (1/f) * 1000000000 => |
422 | * slsu = cycles / (1000000000 / f) + 1 |
423 | */ |
424 | ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk); |
425 | switch (priv->sm) { |
426 | case I2C_FREQ_MODE_FAST: |
427 | case I2C_FREQ_MODE_FAST_PLUS: |
428 | slsu = DIV_ROUND_UP(100, ns); /* Fast */ |
429 | break; |
430 | case I2C_FREQ_MODE_HIGH_SPEED: |
431 | slsu = DIV_ROUND_UP(10, ns); /* High */ |
432 | break; |
433 | case I2C_FREQ_MODE_STANDARD: |
434 | default: |
435 | slsu = DIV_ROUND_UP(250, ns); /* Standard */ |
436 | break; |
437 | } |
438 | slsu += 1; |
439 | |
440 | dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n" , slsu); |
441 | writel(FIELD_PREP(I2C_SCR_SLSU, slsu), addr: priv->virtbase + I2C_SCR); |
442 | |
443 | /* |
444 | * The spec says, in case of std. mode the divider is |
445 | * 2 whereas it is 3 for fast and fastplus mode of |
446 | * operation. TODO - high speed support. |
447 | */ |
448 | div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2; |
449 | |
450 | /* |
451 | * generate the mask for baud rate counters. The controller |
452 | * has two baud rate counters. One is used for High speed |
453 | * operation, and the other is for std, fast mode, fast mode |
454 | * plus operation. Currently we do not supprt high speed mode |
455 | * so set brcr1 to 0. |
456 | */ |
457 | brcr1 = FIELD_PREP(I2C_BRCR_BRCNT1, 0); |
458 | brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2, i2c_clk / (priv->clk_freq * div)); |
459 | |
460 | /* set the baud rate counter register */ |
461 | writel(val: (brcr1 | brcr2), addr: priv->virtbase + I2C_BRCR); |
462 | |
463 | /* |
464 | * set the speed mode. Currently we support |
465 | * only standard and fast mode of operation |
466 | * TODO - support for fast mode plus (up to 1Mb/s) |
467 | * and high speed (up to 3.4 Mb/s) |
468 | */ |
469 | if (priv->sm > I2C_FREQ_MODE_FAST) { |
470 | dev_err(&priv->adev->dev, |
471 | "do not support this mode defaulting to std. mode\n" ); |
472 | brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2, |
473 | i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2)); |
474 | writel(val: (brcr1 | brcr2), addr: priv->virtbase + I2C_BRCR); |
475 | writel(FIELD_PREP(I2C_CR_SM, I2C_FREQ_MODE_STANDARD), |
476 | addr: priv->virtbase + I2C_CR); |
477 | } |
478 | writel(FIELD_PREP(I2C_CR_SM, priv->sm), addr: priv->virtbase + I2C_CR); |
479 | |
480 | /* set the Tx and Rx FIFO threshold */ |
481 | writel(val: priv->tft, addr: priv->virtbase + I2C_TFTR); |
482 | writel(val: priv->rft, addr: priv->virtbase + I2C_RFTR); |
483 | } |
484 | |
485 | static bool nmk_i2c_wait_xfer_done(struct nmk_i2c_dev *priv) |
486 | { |
487 | if (priv->timeout_usecs < jiffies_to_usecs(j: 1)) { |
488 | unsigned long timeout_usecs = priv->timeout_usecs; |
489 | ktime_t timeout = ktime_set(secs: 0, nsecs: timeout_usecs * NSEC_PER_USEC); |
490 | |
491 | wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout); |
492 | } else { |
493 | unsigned long timeout = usecs_to_jiffies(u: priv->timeout_usecs); |
494 | |
495 | wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout); |
496 | } |
497 | |
498 | return priv->xfer_done; |
499 | } |
500 | |
501 | /** |
502 | * read_i2c() - Read from I2C client device |
503 | * @priv: private data of I2C Driver |
504 | * @flags: message flags |
505 | * |
506 | * This function reads from i2c client device when controller is in |
507 | * master mode. There is a completion timeout. If there is no transfer |
508 | * before timeout error is returned. |
509 | */ |
510 | static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) |
511 | { |
512 | u32 mcr, irq_mask; |
513 | int status = 0; |
514 | bool xfer_done; |
515 | |
516 | mcr = load_i2c_mcr_reg(priv, flags); |
517 | writel(val: mcr, addr: priv->virtbase + I2C_MCR); |
518 | |
519 | /* load the current CR value */ |
520 | writel(readl(addr: priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, |
521 | addr: priv->virtbase + I2C_CR); |
522 | |
523 | /* enable the controller */ |
524 | i2c_set_bit(reg: priv->virtbase + I2C_CR, I2C_CR_PE); |
525 | |
526 | init_waitqueue_head(&priv->xfer_wq); |
527 | priv->xfer_done = false; |
528 | |
529 | /* enable interrupts by setting the mask */ |
530 | irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | |
531 | I2C_IT_MAL | I2C_IT_BERR); |
532 | |
533 | if (priv->stop || !priv->vendor->has_mtdws) |
534 | irq_mask |= I2C_IT_MTD; |
535 | else |
536 | irq_mask |= I2C_IT_MTDWS; |
537 | |
538 | irq_mask &= I2C_CLEAR_ALL_INTS; |
539 | |
540 | writel(readl(addr: priv->virtbase + I2C_IMSCR) | irq_mask, |
541 | addr: priv->virtbase + I2C_IMSCR); |
542 | |
543 | xfer_done = nmk_i2c_wait_xfer_done(priv); |
544 | |
545 | if (!xfer_done) { |
546 | /* Controller timed out */ |
547 | dev_err(&priv->adev->dev, "read from slave 0x%x timed out\n" , |
548 | priv->cli.slave_adr); |
549 | status = -ETIMEDOUT; |
550 | } |
551 | return status; |
552 | } |
553 | |
554 | static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes) |
555 | { |
556 | int count; |
557 | |
558 | for (count = (no_bytes - 2); |
559 | (count > 0) && |
560 | (priv->cli.count != 0); |
561 | count--) { |
562 | /* write to the Tx FIFO */ |
563 | nmk_i2c_writeb(priv, val: *priv->cli.buffer, I2C_TFR); |
564 | priv->cli.buffer++; |
565 | priv->cli.count--; |
566 | priv->cli.xfer_bytes++; |
567 | } |
568 | |
569 | } |
570 | |
571 | /** |
572 | * write_i2c() - Write data to I2C client. |
573 | * @priv: private data of I2C Driver |
574 | * @flags: message flags |
575 | * |
576 | * This function writes data to I2C client |
577 | */ |
578 | static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) |
579 | { |
580 | u32 mcr, irq_mask; |
581 | u32 status = 0; |
582 | bool xfer_done; |
583 | |
584 | mcr = load_i2c_mcr_reg(priv, flags); |
585 | |
586 | writel(val: mcr, addr: priv->virtbase + I2C_MCR); |
587 | |
588 | /* load the current CR value */ |
589 | writel(readl(addr: priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, |
590 | addr: priv->virtbase + I2C_CR); |
591 | |
592 | /* enable the controller */ |
593 | i2c_set_bit(reg: priv->virtbase + I2C_CR, I2C_CR_PE); |
594 | |
595 | init_waitqueue_head(&priv->xfer_wq); |
596 | priv->xfer_done = false; |
597 | |
598 | /* enable interrupts by settings the masks */ |
599 | irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); |
600 | |
601 | /* Fill the TX FIFO with transmit data */ |
602 | fill_tx_fifo(priv, MAX_I2C_FIFO_THRESHOLD); |
603 | |
604 | if (priv->cli.count != 0) |
605 | irq_mask |= I2C_IT_TXFNE; |
606 | |
607 | /* |
608 | * check if we want to transfer a single or multiple bytes, if so |
609 | * set the MTDWS bit (Master Transaction Done Without Stop) |
610 | * to start repeated start operation |
611 | */ |
612 | if (priv->stop || !priv->vendor->has_mtdws) |
613 | irq_mask |= I2C_IT_MTD; |
614 | else |
615 | irq_mask |= I2C_IT_MTDWS; |
616 | |
617 | irq_mask &= I2C_CLEAR_ALL_INTS; |
618 | |
619 | writel(readl(addr: priv->virtbase + I2C_IMSCR) | irq_mask, |
620 | addr: priv->virtbase + I2C_IMSCR); |
621 | |
622 | xfer_done = nmk_i2c_wait_xfer_done(priv); |
623 | |
624 | if (!xfer_done) { |
625 | /* Controller timed out */ |
626 | dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n" , |
627 | priv->cli.slave_adr); |
628 | status = -ETIMEDOUT; |
629 | } |
630 | |
631 | return status; |
632 | } |
633 | |
634 | /** |
635 | * nmk_i2c_xfer_one() - transmit a single I2C message |
636 | * @priv: device with a message encoded into it |
637 | * @flags: message flags |
638 | */ |
639 | static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags) |
640 | { |
641 | int status; |
642 | |
643 | if (flags & I2C_M_RD) { |
644 | /* read operation */ |
645 | priv->cli.operation = I2C_READ; |
646 | status = read_i2c(priv, flags); |
647 | } else { |
648 | /* write operation */ |
649 | priv->cli.operation = I2C_WRITE; |
650 | status = write_i2c(priv, flags); |
651 | } |
652 | |
653 | if (status || priv->result) { |
654 | u32 i2c_sr; |
655 | u32 cause; |
656 | |
657 | i2c_sr = readl(addr: priv->virtbase + I2C_SR); |
658 | if (FIELD_GET(I2C_SR_STATUS, i2c_sr) == I2C_ABORT) { |
659 | cause = FIELD_GET(I2C_SR_CAUSE, i2c_sr); |
660 | dev_err(&priv->adev->dev, "%s\n" , |
661 | cause >= ARRAY_SIZE(abort_causes) ? |
662 | "unknown reason" : |
663 | abort_causes[cause]); |
664 | } |
665 | |
666 | init_hw(priv); |
667 | |
668 | status = status ? status : priv->result; |
669 | } |
670 | |
671 | return status; |
672 | } |
673 | |
674 | /** |
675 | * nmk_i2c_xfer() - I2C transfer function used by kernel framework |
676 | * @i2c_adap: Adapter pointer to the controller |
677 | * @msgs: Pointer to data to be written. |
678 | * @num_msgs: Number of messages to be executed |
679 | * |
680 | * This is the function called by the generic kernel i2c_transfer() |
681 | * or i2c_smbus...() API calls. Note that this code is protected by the |
682 | * semaphore set in the kernel i2c_transfer() function. |
683 | * |
684 | * NOTE: |
685 | * READ TRANSFER : We impose a restriction of the first message to be the |
686 | * index message for any read transaction. |
687 | * - a no index is coded as '0', |
688 | * - 2byte big endian index is coded as '3' |
689 | * !!! msg[0].buf holds the actual index. |
690 | * This is compatible with generic messages of smbus emulator |
691 | * that send a one byte index. |
692 | * eg. a I2C transation to read 2 bytes from index 0 |
693 | * idx = 0; |
694 | * msg[0].addr = client->addr; |
695 | * msg[0].flags = 0x0; |
696 | * msg[0].len = 1; |
697 | * msg[0].buf = &idx; |
698 | * |
699 | * msg[1].addr = client->addr; |
700 | * msg[1].flags = I2C_M_RD; |
701 | * msg[1].len = 2; |
702 | * msg[1].buf = rd_buff |
703 | * i2c_transfer(adap, msg, 2); |
704 | * |
705 | * WRITE TRANSFER : The I2C standard interface interprets all data as payload. |
706 | * If you want to emulate an SMBUS write transaction put the |
707 | * index as first byte(or first and second) in the payload. |
708 | * eg. a I2C transation to write 2 bytes from index 1 |
709 | * wr_buff[0] = 0x1; |
710 | * wr_buff[1] = 0x23; |
711 | * wr_buff[2] = 0x46; |
712 | * msg[0].flags = 0x0; |
713 | * msg[0].len = 3; |
714 | * msg[0].buf = wr_buff; |
715 | * i2c_transfer(adap, msg, 1); |
716 | * |
717 | * To read or write a block of data (multiple bytes) using SMBUS emulation |
718 | * please use the i2c_smbus_read_i2c_block_data() |
719 | * or i2c_smbus_write_i2c_block_data() API |
720 | */ |
721 | static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, |
722 | struct i2c_msg msgs[], int num_msgs) |
723 | { |
724 | int status = 0; |
725 | int i; |
726 | struct nmk_i2c_dev *priv = i2c_get_adapdata(adap: i2c_adap); |
727 | int j; |
728 | |
729 | pm_runtime_get_sync(dev: &priv->adev->dev); |
730 | |
731 | /* Attempt three times to send the message queue */ |
732 | for (j = 0; j < 3; j++) { |
733 | /* setup the i2c controller */ |
734 | setup_i2c_controller(priv); |
735 | |
736 | for (i = 0; i < num_msgs; i++) { |
737 | priv->cli.slave_adr = msgs[i].addr; |
738 | priv->cli.buffer = msgs[i].buf; |
739 | priv->cli.count = msgs[i].len; |
740 | priv->stop = (i < (num_msgs - 1)) ? 0 : 1; |
741 | priv->result = 0; |
742 | |
743 | status = nmk_i2c_xfer_one(priv, flags: msgs[i].flags); |
744 | if (status != 0) |
745 | break; |
746 | } |
747 | if (status == 0) |
748 | break; |
749 | } |
750 | |
751 | pm_runtime_put_sync(dev: &priv->adev->dev); |
752 | |
753 | /* return the no. messages processed */ |
754 | if (status) |
755 | return status; |
756 | else |
757 | return num_msgs; |
758 | } |
759 | |
760 | /** |
761 | * disable_interrupts() - disable the interrupts |
762 | * @priv: private data of controller |
763 | * @irq: interrupt number |
764 | */ |
765 | static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq) |
766 | { |
767 | irq &= I2C_CLEAR_ALL_INTS; |
768 | writel(readl(addr: priv->virtbase + I2C_IMSCR) & ~irq, |
769 | addr: priv->virtbase + I2C_IMSCR); |
770 | return 0; |
771 | } |
772 | |
773 | /** |
774 | * i2c_irq_handler() - interrupt routine |
775 | * @irq: interrupt number |
776 | * @arg: data passed to the handler |
777 | * |
778 | * This is the interrupt handler for the i2c driver. Currently |
779 | * it handles the major interrupts like Rx & Tx FIFO management |
780 | * interrupts, master transaction interrupts, arbitration and |
781 | * bus error interrupts. The rest of the interrupts are treated as |
782 | * unhandled. |
783 | */ |
784 | static irqreturn_t i2c_irq_handler(int irq, void *arg) |
785 | { |
786 | struct nmk_i2c_dev *priv = arg; |
787 | struct device *dev = &priv->adev->dev; |
788 | u32 tft, rft; |
789 | u32 count; |
790 | u32 misr, src; |
791 | |
792 | /* load Tx FIFO and Rx FIFO threshold values */ |
793 | tft = readl(addr: priv->virtbase + I2C_TFTR); |
794 | rft = readl(addr: priv->virtbase + I2C_RFTR); |
795 | |
796 | /* read interrupt status register */ |
797 | misr = readl(addr: priv->virtbase + I2C_MISR); |
798 | |
799 | src = __ffs(misr); |
800 | switch (BIT(src)) { |
801 | |
802 | /* Transmit FIFO nearly empty interrupt */ |
803 | case I2C_IT_TXFNE: |
804 | { |
805 | if (priv->cli.operation == I2C_READ) { |
806 | /* |
807 | * in read operation why do we care for writing? |
808 | * so disable the Transmit FIFO interrupt |
809 | */ |
810 | disable_interrupts(priv, I2C_IT_TXFNE); |
811 | } else { |
812 | fill_tx_fifo(priv, no_bytes: (MAX_I2C_FIFO_THRESHOLD - tft)); |
813 | /* |
814 | * if done, close the transfer by disabling the |
815 | * corresponding TXFNE interrupt |
816 | */ |
817 | if (priv->cli.count == 0) |
818 | disable_interrupts(priv, I2C_IT_TXFNE); |
819 | } |
820 | } |
821 | break; |
822 | |
823 | /* |
824 | * Rx FIFO nearly full interrupt. |
825 | * This is set when the numer of entries in Rx FIFO is |
826 | * greater or equal than the threshold value programmed |
827 | * in RFT |
828 | */ |
829 | case I2C_IT_RXFNF: |
830 | for (count = rft; count > 0; count--) { |
831 | /* Read the Rx FIFO */ |
832 | *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR); |
833 | priv->cli.buffer++; |
834 | } |
835 | priv->cli.count -= rft; |
836 | priv->cli.xfer_bytes += rft; |
837 | break; |
838 | |
839 | /* Rx FIFO full */ |
840 | case I2C_IT_RXFF: |
841 | for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { |
842 | *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR); |
843 | priv->cli.buffer++; |
844 | } |
845 | priv->cli.count -= MAX_I2C_FIFO_THRESHOLD; |
846 | priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; |
847 | break; |
848 | |
849 | /* Master Transaction Done with/without stop */ |
850 | case I2C_IT_MTD: |
851 | case I2C_IT_MTDWS: |
852 | if (priv->cli.operation == I2C_READ) { |
853 | while (!(readl(addr: priv->virtbase + I2C_RISR) |
854 | & I2C_IT_RXFE)) { |
855 | if (priv->cli.count == 0) |
856 | break; |
857 | *priv->cli.buffer = |
858 | nmk_i2c_readb(priv, I2C_RFR); |
859 | priv->cli.buffer++; |
860 | priv->cli.count--; |
861 | priv->cli.xfer_bytes++; |
862 | } |
863 | } |
864 | |
865 | disable_all_interrupts(priv); |
866 | clear_all_interrupts(priv); |
867 | |
868 | if (priv->cli.count) { |
869 | priv->result = -EIO; |
870 | dev_err(dev, "%lu bytes still remain to be xfered\n" , |
871 | priv->cli.count); |
872 | init_hw(priv); |
873 | } |
874 | priv->xfer_done = true; |
875 | wake_up(&priv->xfer_wq); |
876 | |
877 | |
878 | break; |
879 | |
880 | /* Master Arbitration lost interrupt */ |
881 | case I2C_IT_MAL: |
882 | priv->result = -EIO; |
883 | init_hw(priv); |
884 | |
885 | i2c_set_bit(reg: priv->virtbase + I2C_ICR, I2C_IT_MAL); |
886 | priv->xfer_done = true; |
887 | wake_up(&priv->xfer_wq); |
888 | |
889 | |
890 | break; |
891 | |
892 | /* |
893 | * Bus Error interrupt. |
894 | * This happens when an unexpected start/stop condition occurs |
895 | * during the transaction. |
896 | */ |
897 | case I2C_IT_BERR: |
898 | { |
899 | u32 sr; |
900 | |
901 | sr = readl(addr: priv->virtbase + I2C_SR); |
902 | priv->result = -EIO; |
903 | if (FIELD_GET(I2C_SR_STATUS, sr) == I2C_ABORT) |
904 | init_hw(priv); |
905 | |
906 | i2c_set_bit(reg: priv->virtbase + I2C_ICR, I2C_IT_BERR); |
907 | priv->xfer_done = true; |
908 | wake_up(&priv->xfer_wq); |
909 | |
910 | } |
911 | break; |
912 | |
913 | /* |
914 | * Tx FIFO overrun interrupt. |
915 | * This is set when a write operation in Tx FIFO is performed and |
916 | * the Tx FIFO is full. |
917 | */ |
918 | case I2C_IT_TXFOVR: |
919 | priv->result = -EIO; |
920 | init_hw(priv); |
921 | |
922 | dev_err(dev, "Tx Fifo Over run\n" ); |
923 | priv->xfer_done = true; |
924 | wake_up(&priv->xfer_wq); |
925 | |
926 | |
927 | break; |
928 | |
929 | /* unhandled interrupts by this driver - TODO*/ |
930 | case I2C_IT_TXFE: |
931 | case I2C_IT_TXFF: |
932 | case I2C_IT_RXFE: |
933 | case I2C_IT_RFSR: |
934 | case I2C_IT_RFSE: |
935 | case I2C_IT_WTSR: |
936 | case I2C_IT_STD: |
937 | dev_err(dev, "unhandled Interrupt\n" ); |
938 | break; |
939 | default: |
940 | dev_err(dev, "spurious Interrupt..\n" ); |
941 | break; |
942 | } |
943 | |
944 | return IRQ_HANDLED; |
945 | } |
946 | |
947 | static int nmk_i2c_suspend_late(struct device *dev) |
948 | { |
949 | int ret; |
950 | |
951 | ret = pm_runtime_force_suspend(dev); |
952 | if (ret) |
953 | return ret; |
954 | |
955 | pinctrl_pm_select_sleep_state(dev); |
956 | return 0; |
957 | } |
958 | |
959 | static int nmk_i2c_resume_early(struct device *dev) |
960 | { |
961 | return pm_runtime_force_resume(dev); |
962 | } |
963 | |
964 | static int nmk_i2c_runtime_suspend(struct device *dev) |
965 | { |
966 | struct amba_device *adev = to_amba_device(dev); |
967 | struct nmk_i2c_dev *priv = amba_get_drvdata(adev); |
968 | |
969 | clk_disable_unprepare(clk: priv->clk); |
970 | pinctrl_pm_select_idle_state(dev); |
971 | return 0; |
972 | } |
973 | |
974 | static int nmk_i2c_runtime_resume(struct device *dev) |
975 | { |
976 | struct amba_device *adev = to_amba_device(dev); |
977 | struct nmk_i2c_dev *priv = amba_get_drvdata(adev); |
978 | int ret; |
979 | |
980 | ret = clk_prepare_enable(clk: priv->clk); |
981 | if (ret) { |
982 | dev_err(dev, "can't prepare_enable clock\n" ); |
983 | return ret; |
984 | } |
985 | |
986 | pinctrl_pm_select_default_state(dev); |
987 | |
988 | ret = init_hw(priv); |
989 | if (ret) { |
990 | clk_disable_unprepare(clk: priv->clk); |
991 | pinctrl_pm_select_idle_state(dev); |
992 | } |
993 | |
994 | return ret; |
995 | } |
996 | |
997 | static const struct dev_pm_ops nmk_i2c_pm = { |
998 | LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early) |
999 | RUNTIME_PM_OPS(nmk_i2c_runtime_suspend, nmk_i2c_runtime_resume, NULL) |
1000 | }; |
1001 | |
1002 | static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) |
1003 | { |
1004 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; |
1005 | } |
1006 | |
1007 | static const struct i2c_algorithm nmk_i2c_algo = { |
1008 | .master_xfer = nmk_i2c_xfer, |
1009 | .functionality = nmk_i2c_functionality |
1010 | }; |
1011 | |
1012 | static void nmk_i2c_of_probe(struct device_node *np, |
1013 | struct nmk_i2c_dev *priv) |
1014 | { |
1015 | u32 timeout_usecs; |
1016 | |
1017 | /* Default to 100 kHz if no frequency is given in the node */ |
1018 | if (of_property_read_u32(np, propname: "clock-frequency" , out_value: &priv->clk_freq)) |
1019 | priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ; |
1020 | |
1021 | /* This driver only supports 'standard' and 'fast' modes of operation. */ |
1022 | if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) |
1023 | priv->sm = I2C_FREQ_MODE_STANDARD; |
1024 | else |
1025 | priv->sm = I2C_FREQ_MODE_FAST; |
1026 | priv->tft = 1; /* Tx FIFO threshold */ |
1027 | priv->rft = 8; /* Rx FIFO threshold */ |
1028 | |
1029 | /* Slave response timeout */ |
1030 | if (!of_property_read_u32(np, propname: "i2c-transfer-timeout-us" , out_value: &timeout_usecs)) |
1031 | priv->timeout_usecs = timeout_usecs; |
1032 | else |
1033 | priv->timeout_usecs = 200 * USEC_PER_MSEC; |
1034 | } |
1035 | |
1036 | static const unsigned int nmk_i2c_eyeq5_masks[] = { |
1037 | GENMASK(5, 4), |
1038 | GENMASK(7, 6), |
1039 | GENMASK(9, 8), |
1040 | GENMASK(11, 10), |
1041 | GENMASK(13, 12), |
1042 | }; |
1043 | |
1044 | static int nmk_i2c_eyeq5_probe(struct nmk_i2c_dev *priv) |
1045 | { |
1046 | struct device *dev = &priv->adev->dev; |
1047 | struct device_node *np = dev->of_node; |
1048 | unsigned int mask, speed_mode; |
1049 | struct regmap *olb; |
1050 | unsigned int id; |
1051 | |
1052 | priv->has_32b_bus = true; |
1053 | |
1054 | olb = syscon_regmap_lookup_by_phandle_args(np, property: "mobileye,olb" , arg_count: 1, out_args: &id); |
1055 | if (IS_ERR(ptr: olb)) |
1056 | return PTR_ERR(ptr: olb); |
1057 | if (id >= ARRAY_SIZE(nmk_i2c_eyeq5_masks)) |
1058 | return -ENOENT; |
1059 | |
1060 | if (priv->clk_freq <= 400000) |
1061 | speed_mode = I2C_EYEQ5_SPEED_FAST; |
1062 | else if (priv->clk_freq <= 1000000) |
1063 | speed_mode = I2C_EYEQ5_SPEED_FAST_PLUS; |
1064 | else |
1065 | speed_mode = I2C_EYEQ5_SPEED_HIGH_SPEED; |
1066 | |
1067 | mask = nmk_i2c_eyeq5_masks[id]; |
1068 | regmap_update_bits(map: olb, NMK_I2C_EYEQ5_OLB_IOCR2, |
1069 | mask, val: speed_mode << __fls(word: mask)); |
1070 | |
1071 | return 0; |
1072 | } |
1073 | |
1074 | static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) |
1075 | { |
1076 | int ret = 0; |
1077 | struct nmk_i2c_dev *priv; |
1078 | struct device_node *np = adev->dev.of_node; |
1079 | struct device *dev = &adev->dev; |
1080 | struct i2c_adapter *adap; |
1081 | struct i2c_vendor_data *vendor = id->data; |
1082 | u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; |
1083 | |
1084 | priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL); |
1085 | if (!priv) |
1086 | return -ENOMEM; |
1087 | |
1088 | priv->vendor = vendor; |
1089 | priv->adev = adev; |
1090 | priv->has_32b_bus = false; |
1091 | nmk_i2c_of_probe(np, priv); |
1092 | |
1093 | if (of_device_is_compatible(device: np, "mobileye,eyeq5-i2c" )) { |
1094 | ret = nmk_i2c_eyeq5_probe(priv); |
1095 | if (ret) |
1096 | return dev_err_probe(dev, err: ret, fmt: "failed OLB lookup\n" ); |
1097 | } |
1098 | |
1099 | if (priv->tft > max_fifo_threshold) { |
1100 | dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n" , |
1101 | priv->tft, max_fifo_threshold); |
1102 | priv->tft = max_fifo_threshold; |
1103 | } |
1104 | |
1105 | if (priv->rft > max_fifo_threshold) { |
1106 | dev_warn(dev, "requested RX FIFO threshold %u, adjusted down to %u\n" , |
1107 | priv->rft, max_fifo_threshold); |
1108 | priv->rft = max_fifo_threshold; |
1109 | } |
1110 | |
1111 | amba_set_drvdata(adev, priv); |
1112 | |
1113 | priv->virtbase = devm_ioremap(dev, offset: adev->res.start, |
1114 | size: resource_size(res: &adev->res)); |
1115 | if (!priv->virtbase) |
1116 | return -ENOMEM; |
1117 | |
1118 | priv->irq = adev->irq[0]; |
1119 | ret = devm_request_irq(dev, irq: priv->irq, handler: i2c_irq_handler, irqflags: 0, |
1120 | DRIVER_NAME, dev_id: priv); |
1121 | if (ret) |
1122 | return dev_err_probe(dev, err: ret, |
1123 | fmt: "cannot claim the irq %d\n" , priv->irq); |
1124 | |
1125 | priv->clk = devm_clk_get_enabled(dev, NULL); |
1126 | if (IS_ERR(ptr: priv->clk)) |
1127 | return dev_err_probe(dev, err: PTR_ERR(ptr: priv->clk), |
1128 | fmt: "could enable i2c clock\n" ); |
1129 | |
1130 | init_hw(priv); |
1131 | |
1132 | adap = &priv->adap; |
1133 | adap->dev.of_node = np; |
1134 | adap->dev.parent = dev; |
1135 | adap->owner = THIS_MODULE; |
1136 | adap->class = I2C_CLASS_DEPRECATED; |
1137 | adap->algo = &nmk_i2c_algo; |
1138 | adap->timeout = usecs_to_jiffies(u: priv->timeout_usecs); |
1139 | snprintf(buf: adap->name, size: sizeof(adap->name), |
1140 | fmt: "Nomadik I2C at %pR" , &adev->res); |
1141 | |
1142 | i2c_set_adapdata(adap, data: priv); |
1143 | |
1144 | dev_info(dev, |
1145 | "initialize %s on virtual base %p\n" , |
1146 | adap->name, priv->virtbase); |
1147 | |
1148 | ret = i2c_add_adapter(adap); |
1149 | if (ret) |
1150 | return ret; |
1151 | |
1152 | pm_runtime_put(dev); |
1153 | |
1154 | return 0; |
1155 | } |
1156 | |
1157 | static void nmk_i2c_remove(struct amba_device *adev) |
1158 | { |
1159 | struct nmk_i2c_dev *priv = amba_get_drvdata(adev); |
1160 | |
1161 | i2c_del_adapter(adap: &priv->adap); |
1162 | flush_i2c_fifo(priv); |
1163 | disable_all_interrupts(priv); |
1164 | clear_all_interrupts(priv); |
1165 | /* disable the controller */ |
1166 | i2c_clr_bit(reg: priv->virtbase + I2C_CR, I2C_CR_PE); |
1167 | } |
1168 | |
1169 | static struct i2c_vendor_data vendor_stn8815 = { |
1170 | .has_mtdws = false, |
1171 | .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ |
1172 | }; |
1173 | |
1174 | static struct i2c_vendor_data vendor_db8500 = { |
1175 | .has_mtdws = true, |
1176 | .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ |
1177 | }; |
1178 | |
1179 | static const struct amba_id nmk_i2c_ids[] = { |
1180 | { |
1181 | .id = 0x00180024, |
1182 | .mask = 0x00ffffff, |
1183 | .data = &vendor_stn8815, |
1184 | }, |
1185 | { |
1186 | .id = 0x00380024, |
1187 | .mask = 0x00ffffff, |
1188 | .data = &vendor_db8500, |
1189 | }, |
1190 | {}, |
1191 | }; |
1192 | |
1193 | MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); |
1194 | |
1195 | static struct amba_driver nmk_i2c_driver = { |
1196 | .drv = { |
1197 | .owner = THIS_MODULE, |
1198 | .name = DRIVER_NAME, |
1199 | .pm = pm_ptr(&nmk_i2c_pm), |
1200 | }, |
1201 | .id_table = nmk_i2c_ids, |
1202 | .probe = nmk_i2c_probe, |
1203 | .remove = nmk_i2c_remove, |
1204 | }; |
1205 | |
1206 | static int __init nmk_i2c_init(void) |
1207 | { |
1208 | return amba_driver_register(drv: &nmk_i2c_driver); |
1209 | } |
1210 | |
1211 | static void __exit nmk_i2c_exit(void) |
1212 | { |
1213 | amba_driver_unregister(drv: &nmk_i2c_driver); |
1214 | } |
1215 | |
1216 | subsys_initcall(nmk_i2c_init); |
1217 | module_exit(nmk_i2c_exit); |
1218 | |
1219 | MODULE_AUTHOR("Sachin Verma" ); |
1220 | MODULE_AUTHOR("Srinidhi KASAGAR" ); |
1221 | MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver" ); |
1222 | MODULE_LICENSE("GPL" ); |
1223 | |