1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * i2c_adap_pxa.c |
4 | * |
5 | * I2C adapter for the PXA I2C bus access. |
6 | * |
7 | * Copyright (C) 2002 Intrinsyc Software Inc. |
8 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. |
9 | * |
10 | * History: |
11 | * Apr 2002: Initial version [CS] |
12 | * Jun 2002: Properly separated algo/adap [FB] |
13 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] |
14 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] |
15 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] |
16 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] |
17 | * Feb 2005: Rework slave mode handling [RMK] |
18 | */ |
19 | #include <linux/clk.h> |
20 | #include <linux/delay.h> |
21 | #include <linux/err.h> |
22 | #include <linux/errno.h> |
23 | #include <linux/gpio/consumer.h> |
24 | #include <linux/i2c.h> |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> |
27 | #include <linux/io.h> |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> |
30 | #include <linux/of.h> |
31 | #include <linux/of_device.h> |
32 | #include <linux/pinctrl/consumer.h> |
33 | #include <linux/platform_device.h> |
34 | #include <linux/platform_data/i2c-pxa.h> |
35 | #include <linux/property.h> |
36 | #include <linux/slab.h> |
37 | |
38 | /* I2C register field definitions */ |
39 | #define IBMR_SDAS (1 << 0) |
40 | #define IBMR_SCLS (1 << 1) |
41 | |
42 | #define ICR_START (1 << 0) /* start bit */ |
43 | #define ICR_STOP (1 << 1) /* stop bit */ |
44 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ |
45 | #define ICR_TB (1 << 3) /* transfer byte bit */ |
46 | #define ICR_MA (1 << 4) /* master abort */ |
47 | #define ICR_SCLE (1 << 5) /* master clock enable */ |
48 | #define ICR_IUE (1 << 6) /* unit enable */ |
49 | #define ICR_GCD (1 << 7) /* general call disable */ |
50 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ |
51 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ |
52 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ |
53 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ |
54 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ |
55 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ |
56 | #define ICR_UR (1 << 14) /* unit reset */ |
57 | #define ICR_FM (1 << 15) /* fast mode */ |
58 | #define ICR_HS (1 << 16) /* High Speed mode */ |
59 | #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */ |
60 | #define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */ |
61 | #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */ |
62 | |
63 | #define ISR_RWM (1 << 0) /* read/write mode */ |
64 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ |
65 | #define ISR_UB (1 << 2) /* unit busy */ |
66 | #define ISR_IBB (1 << 3) /* bus busy */ |
67 | #define ISR_SSD (1 << 4) /* slave stop detected */ |
68 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ |
69 | #define ISR_ITE (1 << 6) /* tx buffer empty */ |
70 | #define ISR_IRF (1 << 7) /* rx buffer full */ |
71 | #define ISR_GCAD (1 << 8) /* general call address detected */ |
72 | #define ISR_SAD (1 << 9) /* slave address detected */ |
73 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ |
74 | |
75 | #define ILCR_SLV_SHIFT 0 |
76 | #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT) |
77 | #define ILCR_FLV_SHIFT 9 |
78 | #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT) |
79 | #define ILCR_HLVL_SHIFT 18 |
80 | #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT) |
81 | #define ILCR_HLVH_SHIFT 27 |
82 | #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT) |
83 | |
84 | #define IWCR_CNT_SHIFT 0 |
85 | #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT) |
86 | #define IWCR_HS_CNT1_SHIFT 5 |
87 | #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT) |
88 | #define IWCR_HS_CNT2_SHIFT 10 |
89 | #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT) |
90 | |
91 | /* need a longer timeout if we're dealing with the fact we may well be |
92 | * looking at a multi-master environment |
93 | */ |
94 | #define DEF_TIMEOUT 32 |
95 | |
96 | #define NO_SLAVE (-ENXIO) |
97 | #define BUS_ERROR (-EREMOTEIO) |
98 | #define XFER_NAKED (-ECONNREFUSED) |
99 | #define I2C_RETRY (-2000) /* an error has occurred retry transmit */ |
100 | |
101 | /* ICR initialize bit values |
102 | * |
103 | * 15 FM 0 (100 kHz operation) |
104 | * 14 UR 0 (No unit reset) |
105 | * 13 SADIE 0 (Disables the unit from interrupting on slave addresses |
106 | * matching its slave address) |
107 | * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration |
108 | * in master mode) |
109 | * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) |
110 | * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) |
111 | * 9 IRFIE 1 (Enable interrupts from full buffer received) |
112 | * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) |
113 | * 7 GCD 1 (Disables i2c unit response to general call messages as a slave) |
114 | * 6 IUE 0 (Disable unit until we change settings) |
115 | * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL) |
116 | * 4 MA 0 (Only send stop with the ICR stop bit) |
117 | * 3 TB 0 (We are not transmitting a byte initially) |
118 | * 2 ACKNAK 0 (Send an ACK after the unit receives a byte) |
119 | * 1 STOP 0 (Do not send a STOP) |
120 | * 0 START 0 (Do not send a START) |
121 | */ |
122 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) |
123 | |
124 | /* I2C status register init values |
125 | * |
126 | * 10 BED 1 (Clear bus error detected) |
127 | * 9 SAD 1 (Clear slave address detected) |
128 | * 7 IRF 1 (Clear IDBR Receive Full) |
129 | * 6 ITE 1 (Clear IDBR Transmit Empty) |
130 | * 5 ALD 1 (Clear Arbitration Loss Detected) |
131 | * 4 SSD 1 (Clear Slave Stop Detected) |
132 | */ |
133 | #define I2C_ISR_INIT 0x7FF /* status register init */ |
134 | |
135 | struct pxa_reg_layout { |
136 | u32 ibmr; |
137 | u32 idbr; |
138 | u32 icr; |
139 | u32 isr; |
140 | u32 isar; |
141 | u32 ilcr; |
142 | u32 iwcr; |
143 | u32 fm; |
144 | u32 hs; |
145 | }; |
146 | |
147 | enum pxa_i2c_types { |
148 | REGS_PXA2XX, |
149 | REGS_PXA3XX, |
150 | REGS_CE4100, |
151 | REGS_PXA910, |
152 | REGS_A3700, |
153 | }; |
154 | |
155 | /* I2C register layout definitions */ |
156 | static struct pxa_reg_layout pxa_reg_layout[] = { |
157 | [REGS_PXA2XX] = { |
158 | .ibmr = 0x00, |
159 | .idbr = 0x08, |
160 | .icr = 0x10, |
161 | .isr = 0x18, |
162 | .isar = 0x20, |
163 | .fm = ICR_FM, |
164 | .hs = ICR_HS, |
165 | }, |
166 | [REGS_PXA3XX] = { |
167 | .ibmr = 0x00, |
168 | .idbr = 0x04, |
169 | .icr = 0x08, |
170 | .isr = 0x0c, |
171 | .isar = 0x10, |
172 | .fm = ICR_FM, |
173 | .hs = ICR_HS, |
174 | }, |
175 | [REGS_CE4100] = { |
176 | .ibmr = 0x14, |
177 | .idbr = 0x0c, |
178 | .icr = 0x00, |
179 | .isr = 0x04, |
180 | /* no isar register */ |
181 | .fm = ICR_FM, |
182 | .hs = ICR_HS, |
183 | }, |
184 | [REGS_PXA910] = { |
185 | .ibmr = 0x00, |
186 | .idbr = 0x08, |
187 | .icr = 0x10, |
188 | .isr = 0x18, |
189 | .isar = 0x20, |
190 | .ilcr = 0x28, |
191 | .iwcr = 0x30, |
192 | .fm = ICR_FM, |
193 | .hs = ICR_HS, |
194 | }, |
195 | [REGS_A3700] = { |
196 | .ibmr = 0x00, |
197 | .idbr = 0x04, |
198 | .icr = 0x08, |
199 | .isr = 0x0c, |
200 | .isar = 0x10, |
201 | .fm = ICR_A3700_FM, |
202 | .hs = ICR_A3700_HS, |
203 | }, |
204 | }; |
205 | |
206 | static const struct of_device_id i2c_pxa_dt_ids[] = { |
207 | { .compatible = "mrvl,pxa-i2c" , .data = (void *)REGS_PXA2XX }, |
208 | { .compatible = "mrvl,pwri2c" , .data = (void *)REGS_PXA3XX }, |
209 | { .compatible = "mrvl,mmp-twsi" , .data = (void *)REGS_PXA910 }, |
210 | { .compatible = "marvell,armada-3700-i2c" , .data = (void *)REGS_A3700 }, |
211 | {} |
212 | }; |
213 | MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); |
214 | |
215 | static const struct platform_device_id i2c_pxa_id_table[] = { |
216 | { "pxa2xx-i2c" , REGS_PXA2XX }, |
217 | { "pxa3xx-pwri2c" , REGS_PXA3XX }, |
218 | { "ce4100-i2c" , REGS_CE4100 }, |
219 | { "pxa910-i2c" , REGS_PXA910 }, |
220 | { "armada-3700-i2c" , REGS_A3700 }, |
221 | { }, |
222 | }; |
223 | MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); |
224 | |
225 | struct pxa_i2c { |
226 | spinlock_t lock; |
227 | wait_queue_head_t wait; |
228 | struct i2c_msg *msg; |
229 | unsigned int msg_num; |
230 | unsigned int msg_idx; |
231 | unsigned int msg_ptr; |
232 | unsigned int slave_addr; |
233 | unsigned int req_slave_addr; |
234 | |
235 | struct i2c_adapter adap; |
236 | struct clk *clk; |
237 | #ifdef CONFIG_I2C_PXA_SLAVE |
238 | struct i2c_client *slave; |
239 | #endif |
240 | |
241 | unsigned int irqlogidx; |
242 | u32 isrlog[32]; |
243 | u32 icrlog[32]; |
244 | |
245 | void __iomem *reg_base; |
246 | void __iomem *reg_ibmr; |
247 | void __iomem *reg_idbr; |
248 | void __iomem *reg_icr; |
249 | void __iomem *reg_isr; |
250 | void __iomem *reg_isar; |
251 | void __iomem *reg_ilcr; |
252 | void __iomem *reg_iwcr; |
253 | |
254 | unsigned long iobase; |
255 | unsigned long iosize; |
256 | |
257 | int irq; |
258 | unsigned int use_pio :1; |
259 | unsigned int fast_mode :1; |
260 | unsigned int high_mode:1; |
261 | unsigned char master_code; |
262 | unsigned long rate; |
263 | bool highmode_enter; |
264 | u32 fm_mask; |
265 | u32 hs_mask; |
266 | |
267 | struct i2c_bus_recovery_info recovery; |
268 | struct pinctrl *pinctrl; |
269 | struct pinctrl_state *pinctrl_default; |
270 | struct pinctrl_state *pinctrl_recovery; |
271 | }; |
272 | |
273 | #define _IBMR(i2c) ((i2c)->reg_ibmr) |
274 | #define _IDBR(i2c) ((i2c)->reg_idbr) |
275 | #define _ICR(i2c) ((i2c)->reg_icr) |
276 | #define _ISR(i2c) ((i2c)->reg_isr) |
277 | #define _ISAR(i2c) ((i2c)->reg_isar) |
278 | #define _ILCR(i2c) ((i2c)->reg_ilcr) |
279 | #define _IWCR(i2c) ((i2c)->reg_iwcr) |
280 | |
281 | /* |
282 | * I2C Slave mode address |
283 | */ |
284 | #define I2C_PXA_SLAVE_ADDR 0x1 |
285 | |
286 | #ifdef DEBUG |
287 | |
288 | struct bits { |
289 | u32 mask; |
290 | const char *set; |
291 | const char *unset; |
292 | }; |
293 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
294 | |
295 | static inline void |
296 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) |
297 | { |
298 | printk("%s %08x:" , prefix, val); |
299 | while (num--) { |
300 | const char *str = val & bits->mask ? bits->set : bits->unset; |
301 | if (str) |
302 | pr_cont(" %s" , str); |
303 | bits++; |
304 | } |
305 | pr_cont("\n" ); |
306 | } |
307 | |
308 | static const struct bits isr_bits[] = { |
309 | PXA_BIT(ISR_RWM, "RX" , "TX" ), |
310 | PXA_BIT(ISR_ACKNAK, "NAK" , "ACK" ), |
311 | PXA_BIT(ISR_UB, "Bsy" , "Rdy" ), |
312 | PXA_BIT(ISR_IBB, "BusBsy" , "BusRdy" ), |
313 | PXA_BIT(ISR_SSD, "SlaveStop" , NULL), |
314 | PXA_BIT(ISR_ALD, "ALD" , NULL), |
315 | PXA_BIT(ISR_ITE, "TxEmpty" , NULL), |
316 | PXA_BIT(ISR_IRF, "RxFull" , NULL), |
317 | PXA_BIT(ISR_GCAD, "GenCall" , NULL), |
318 | PXA_BIT(ISR_SAD, "SlaveAddr" , NULL), |
319 | PXA_BIT(ISR_BED, "BusErr" , NULL), |
320 | }; |
321 | |
322 | static void decode_ISR(unsigned int val) |
323 | { |
324 | decode_bits(KERN_DEBUG "ISR" , bits: isr_bits, ARRAY_SIZE(isr_bits), val); |
325 | } |
326 | |
327 | #ifdef CONFIG_I2C_PXA_SLAVE |
328 | static const struct bits icr_bits[] = { |
329 | PXA_BIT(ICR_START, "START" , NULL), |
330 | PXA_BIT(ICR_STOP, "STOP" , NULL), |
331 | PXA_BIT(ICR_ACKNAK, "ACKNAK" , NULL), |
332 | PXA_BIT(ICR_TB, "TB" , NULL), |
333 | PXA_BIT(ICR_MA, "MA" , NULL), |
334 | PXA_BIT(ICR_SCLE, "SCLE" , "scle" ), |
335 | PXA_BIT(ICR_IUE, "IUE" , "iue" ), |
336 | PXA_BIT(ICR_GCD, "GCD" , NULL), |
337 | PXA_BIT(ICR_ITEIE, "ITEIE" , NULL), |
338 | PXA_BIT(ICR_IRFIE, "IRFIE" , NULL), |
339 | PXA_BIT(ICR_BEIE, "BEIE" , NULL), |
340 | PXA_BIT(ICR_SSDIE, "SSDIE" , NULL), |
341 | PXA_BIT(ICR_ALDIE, "ALDIE" , NULL), |
342 | PXA_BIT(ICR_SADIE, "SADIE" , NULL), |
343 | PXA_BIT(ICR_UR, "UR" , "ur" ), |
344 | }; |
345 | |
346 | static void decode_ICR(unsigned int val) |
347 | { |
348 | decode_bits(KERN_DEBUG "ICR" , bits: icr_bits, ARRAY_SIZE(icr_bits), val); |
349 | } |
350 | #endif |
351 | |
352 | static unsigned int i2c_debug = DEBUG; |
353 | |
354 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) |
355 | { |
356 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n" , fname, lno, |
357 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
358 | } |
359 | |
360 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) |
361 | |
362 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) |
363 | { |
364 | unsigned int i; |
365 | struct device *dev = &i2c->adap.dev; |
366 | |
367 | dev_err(dev, "slave_0x%x error: %s\n" , |
368 | i2c->req_slave_addr >> 1, why); |
369 | dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n" , |
370 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); |
371 | dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n" , |
372 | readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)), |
373 | readl(_ISR(i2c))); |
374 | dev_err(dev, "log:" ); |
375 | for (i = 0; i < i2c->irqlogidx; i++) |
376 | pr_cont(" [%03x:%05x]" , i2c->isrlog[i], i2c->icrlog[i]); |
377 | pr_cont("\n" ); |
378 | } |
379 | |
380 | #else /* ifdef DEBUG */ |
381 | |
382 | #define i2c_debug 0 |
383 | |
384 | #define show_state(i2c) do { } while (0) |
385 | #define decode_ISR(val) do { } while (0) |
386 | #define decode_ICR(val) do { } while (0) |
387 | #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) |
388 | |
389 | #endif /* ifdef DEBUG / else */ |
390 | |
391 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); |
392 | |
393 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) |
394 | { |
395 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
396 | } |
397 | |
398 | static void i2c_pxa_abort(struct pxa_i2c *i2c) |
399 | { |
400 | int i = 250; |
401 | |
402 | if (i2c_pxa_is_slavemode(i2c)) { |
403 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n" , __func__); |
404 | return; |
405 | } |
406 | |
407 | while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) { |
408 | unsigned long icr = readl(_ICR(i2c)); |
409 | |
410 | icr &= ~ICR_START; |
411 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; |
412 | |
413 | writel(val: icr, _ICR(i2c)); |
414 | |
415 | show_state(i2c); |
416 | |
417 | mdelay(1); |
418 | i --; |
419 | } |
420 | |
421 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
422 | _ICR(i2c)); |
423 | } |
424 | |
425 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) |
426 | { |
427 | int timeout = DEF_TIMEOUT; |
428 | u32 isr; |
429 | |
430 | while (1) { |
431 | isr = readl(_ISR(i2c)); |
432 | if (!(isr & (ISR_IBB | ISR_UB))) |
433 | return 0; |
434 | |
435 | if (isr & ISR_SAD) |
436 | timeout += 4; |
437 | |
438 | if (!timeout--) |
439 | break; |
440 | |
441 | msleep(msecs: 2); |
442 | show_state(i2c); |
443 | } |
444 | |
445 | show_state(i2c); |
446 | |
447 | return I2C_RETRY; |
448 | } |
449 | |
450 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) |
451 | { |
452 | unsigned long timeout = jiffies + HZ*4; |
453 | |
454 | while (time_before(jiffies, timeout)) { |
455 | if (i2c_debug > 1) |
456 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n" , |
457 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
458 | |
459 | if (readl(_ISR(i2c)) & ISR_SAD) { |
460 | if (i2c_debug > 0) |
461 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n" , __func__); |
462 | goto out; |
463 | } |
464 | |
465 | /* wait for unit and bus being not busy, and we also do a |
466 | * quick check of the i2c lines themselves to ensure they've |
467 | * gone high... |
468 | */ |
469 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && |
470 | readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) { |
471 | if (i2c_debug > 0) |
472 | dev_dbg(&i2c->adap.dev, "%s: done\n" , __func__); |
473 | return 1; |
474 | } |
475 | |
476 | msleep(msecs: 1); |
477 | } |
478 | |
479 | if (i2c_debug > 0) |
480 | dev_dbg(&i2c->adap.dev, "%s: did not free\n" , __func__); |
481 | out: |
482 | return 0; |
483 | } |
484 | |
485 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) |
486 | { |
487 | if (i2c_debug) |
488 | dev_dbg(&i2c->adap.dev, "setting to bus master\n" ); |
489 | |
490 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
491 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n" , __func__); |
492 | if (!i2c_pxa_wait_master(i2c)) { |
493 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n" , __func__); |
494 | return I2C_RETRY; |
495 | } |
496 | } |
497 | |
498 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
499 | return 0; |
500 | } |
501 | |
502 | #ifdef CONFIG_I2C_PXA_SLAVE |
503 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) |
504 | { |
505 | unsigned long timeout = jiffies + HZ*1; |
506 | |
507 | /* wait for stop */ |
508 | |
509 | show_state(i2c); |
510 | |
511 | while (time_before(jiffies, timeout)) { |
512 | if (i2c_debug > 1) |
513 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n" , |
514 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
515 | |
516 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
517 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || |
518 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { |
519 | if (i2c_debug > 1) |
520 | dev_dbg(&i2c->adap.dev, "%s: done\n" , __func__); |
521 | return 1; |
522 | } |
523 | |
524 | msleep(msecs: 1); |
525 | } |
526 | |
527 | if (i2c_debug > 0) |
528 | dev_dbg(&i2c->adap.dev, "%s: did not free\n" , __func__); |
529 | return 0; |
530 | } |
531 | |
532 | /* |
533 | * clear the hold on the bus, and take of anything else |
534 | * that has been configured |
535 | */ |
536 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) |
537 | { |
538 | show_state(i2c); |
539 | |
540 | if (errcode < 0) { |
541 | udelay(100); /* simple delay */ |
542 | } else { |
543 | /* we need to wait for the stop condition to end */ |
544 | |
545 | /* if we where in stop, then clear... */ |
546 | if (readl(_ICR(i2c)) & ICR_STOP) { |
547 | udelay(100); |
548 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
549 | } |
550 | |
551 | if (!i2c_pxa_wait_slave(i2c)) { |
552 | dev_err(&i2c->adap.dev, "%s: wait timedout\n" , |
553 | __func__); |
554 | return; |
555 | } |
556 | } |
557 | |
558 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
559 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
560 | |
561 | if (i2c_debug) { |
562 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n" , readl(_ICR(i2c)), readl(_ISR(i2c))); |
563 | decode_ICR(readl(_ICR(i2c))); |
564 | } |
565 | } |
566 | #else |
567 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) |
568 | #endif |
569 | |
570 | static void i2c_pxa_do_reset(struct pxa_i2c *i2c) |
571 | { |
572 | /* reset according to 9.8 */ |
573 | writel(ICR_UR, _ICR(i2c)); |
574 | writel(I2C_ISR_INIT, _ISR(i2c)); |
575 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); |
576 | |
577 | if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE)) |
578 | writel(val: i2c->slave_addr, _ISAR(i2c)); |
579 | |
580 | /* set control register values */ |
581 | writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c)); |
582 | writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c)); |
583 | |
584 | #ifdef CONFIG_I2C_PXA_SLAVE |
585 | dev_info(&i2c->adap.dev, "Enabling slave mode\n" ); |
586 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
587 | #endif |
588 | |
589 | i2c_pxa_set_slave(i2c, errcode: 0); |
590 | } |
591 | |
592 | static void i2c_pxa_enable(struct pxa_i2c *i2c) |
593 | { |
594 | /* enable unit */ |
595 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
596 | udelay(100); |
597 | } |
598 | |
599 | static void i2c_pxa_reset(struct pxa_i2c *i2c) |
600 | { |
601 | pr_debug("Resetting I2C Controller Unit\n" ); |
602 | |
603 | /* abort any transfer currently under way */ |
604 | i2c_pxa_abort(i2c); |
605 | i2c_pxa_do_reset(i2c); |
606 | i2c_pxa_enable(i2c); |
607 | } |
608 | |
609 | |
610 | #ifdef CONFIG_I2C_PXA_SLAVE |
611 | /* |
612 | * PXA I2C Slave mode |
613 | */ |
614 | |
615 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) |
616 | { |
617 | if (isr & ISR_BED) { |
618 | /* what should we do here? */ |
619 | } else { |
620 | u8 byte = 0; |
621 | |
622 | if (i2c->slave != NULL) |
623 | i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_READ_PROCESSED, |
624 | val: &byte); |
625 | |
626 | writel(val: byte, _IDBR(i2c)); |
627 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ |
628 | } |
629 | } |
630 | |
631 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) |
632 | { |
633 | u8 byte = readl(_IDBR(i2c)); |
634 | |
635 | if (i2c->slave != NULL) |
636 | i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_WRITE_RECEIVED, val: &byte); |
637 | |
638 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
639 | } |
640 | |
641 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) |
642 | { |
643 | int timeout; |
644 | |
645 | if (i2c_debug > 0) |
646 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n" , |
647 | (isr & ISR_RWM) ? 'r' : 't'); |
648 | |
649 | if (i2c->slave != NULL) { |
650 | if (isr & ISR_RWM) { |
651 | u8 byte = 0; |
652 | |
653 | i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_READ_REQUESTED, |
654 | val: &byte); |
655 | writel(val: byte, _IDBR(i2c)); |
656 | } else { |
657 | i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_WRITE_REQUESTED, |
658 | NULL); |
659 | } |
660 | } |
661 | |
662 | /* |
663 | * slave could interrupt in the middle of us generating a |
664 | * start condition... if this happens, we'd better back off |
665 | * and stop holding the poor thing up |
666 | */ |
667 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
668 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
669 | |
670 | timeout = 0x10000; |
671 | |
672 | while (1) { |
673 | if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS) |
674 | break; |
675 | |
676 | timeout--; |
677 | |
678 | if (timeout <= 0) { |
679 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n" ); |
680 | break; |
681 | } |
682 | } |
683 | |
684 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
685 | } |
686 | |
687 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) |
688 | { |
689 | if (i2c_debug > 2) |
690 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n" ); |
691 | |
692 | if (i2c->slave != NULL) |
693 | i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_STOP, NULL); |
694 | |
695 | if (i2c_debug > 2) |
696 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n" ); |
697 | |
698 | /* |
699 | * If we have a master-mode message waiting, |
700 | * kick it off now that the slave has completed. |
701 | */ |
702 | if (i2c->msg) |
703 | i2c_pxa_master_complete(i2c, I2C_RETRY); |
704 | } |
705 | |
706 | static int i2c_pxa_slave_reg(struct i2c_client *slave) |
707 | { |
708 | struct pxa_i2c *i2c = slave->adapter->algo_data; |
709 | |
710 | if (i2c->slave) |
711 | return -EBUSY; |
712 | |
713 | if (!i2c->reg_isar) |
714 | return -EAFNOSUPPORT; |
715 | |
716 | i2c->slave = slave; |
717 | i2c->slave_addr = slave->addr; |
718 | |
719 | writel(val: i2c->slave_addr, _ISAR(i2c)); |
720 | |
721 | return 0; |
722 | } |
723 | |
724 | static int i2c_pxa_slave_unreg(struct i2c_client *slave) |
725 | { |
726 | struct pxa_i2c *i2c = slave->adapter->algo_data; |
727 | |
728 | WARN_ON(!i2c->slave); |
729 | |
730 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; |
731 | writel(val: i2c->slave_addr, _ISAR(i2c)); |
732 | |
733 | i2c->slave = NULL; |
734 | |
735 | return 0; |
736 | } |
737 | #else |
738 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) |
739 | { |
740 | if (isr & ISR_BED) { |
741 | /* what should we do here? */ |
742 | } else { |
743 | writel(0, _IDBR(i2c)); |
744 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
745 | } |
746 | } |
747 | |
748 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) |
749 | { |
750 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
751 | } |
752 | |
753 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) |
754 | { |
755 | int timeout; |
756 | |
757 | /* |
758 | * slave could interrupt in the middle of us generating a |
759 | * start condition... if this happens, we'd better back off |
760 | * and stop holding the poor thing up |
761 | */ |
762 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
763 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
764 | |
765 | timeout = 0x10000; |
766 | |
767 | while (1) { |
768 | if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS) |
769 | break; |
770 | |
771 | timeout--; |
772 | |
773 | if (timeout <= 0) { |
774 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n" ); |
775 | break; |
776 | } |
777 | } |
778 | |
779 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
780 | } |
781 | |
782 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) |
783 | { |
784 | if (i2c->msg) |
785 | i2c_pxa_master_complete(i2c, I2C_RETRY); |
786 | } |
787 | #endif |
788 | |
789 | /* |
790 | * PXA I2C Master mode |
791 | */ |
792 | |
793 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) |
794 | { |
795 | u32 icr; |
796 | |
797 | /* |
798 | * Step 1: target slave address into IDBR |
799 | */ |
800 | i2c->req_slave_addr = i2c_8bit_addr_from_msg(msg: i2c->msg); |
801 | writel(val: i2c->req_slave_addr, _IDBR(i2c)); |
802 | |
803 | /* |
804 | * Step 2: initiate the write. |
805 | */ |
806 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
807 | writel(val: icr | ICR_START | ICR_TB, _ICR(i2c)); |
808 | } |
809 | |
810 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
811 | { |
812 | u32 icr; |
813 | |
814 | /* Clear the START, STOP, ACK, TB and MA flags */ |
815 | icr = readl(_ICR(i2c)); |
816 | icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA); |
817 | writel(val: icr, _ICR(i2c)); |
818 | } |
819 | |
820 | /* |
821 | * PXA I2C send master code |
822 | * 1. Load master code to IDBR and send it. |
823 | * Note for HS mode, set ICR [GPIOEN]. |
824 | * 2. Wait until win arbitration. |
825 | */ |
826 | static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c) |
827 | { |
828 | u32 icr; |
829 | long timeout; |
830 | |
831 | spin_lock_irq(lock: &i2c->lock); |
832 | i2c->highmode_enter = true; |
833 | writel(val: i2c->master_code, _IDBR(i2c)); |
834 | |
835 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
836 | icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE; |
837 | writel(val: icr, _ICR(i2c)); |
838 | |
839 | spin_unlock_irq(lock: &i2c->lock); |
840 | timeout = wait_event_timeout(i2c->wait, |
841 | i2c->highmode_enter == false, HZ * 1); |
842 | |
843 | i2c->highmode_enter = false; |
844 | |
845 | return (timeout == 0) ? I2C_RETRY : 0; |
846 | } |
847 | |
848 | /* |
849 | * i2c_pxa_master_complete - complete the message and wake up. |
850 | */ |
851 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) |
852 | { |
853 | i2c->msg_ptr = 0; |
854 | i2c->msg = NULL; |
855 | i2c->msg_idx ++; |
856 | i2c->msg_num = 0; |
857 | if (ret) |
858 | i2c->msg_idx = ret; |
859 | if (!i2c->use_pio) |
860 | wake_up(&i2c->wait); |
861 | } |
862 | |
863 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) |
864 | { |
865 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
866 | |
867 | again: |
868 | /* |
869 | * If ISR_ALD is set, we lost arbitration. |
870 | */ |
871 | if (isr & ISR_ALD) { |
872 | /* |
873 | * Do we need to do anything here? The PXA docs |
874 | * are vague about what happens. |
875 | */ |
876 | i2c_pxa_scream_blue_murder(i2c, why: "ALD set" ); |
877 | |
878 | /* |
879 | * We ignore this error. We seem to see spurious ALDs |
880 | * for seemingly no reason. If we handle them as I think |
881 | * they should, we end up causing an I2C error, which |
882 | * is painful for some systems. |
883 | */ |
884 | return; /* ignore */ |
885 | } |
886 | |
887 | if ((isr & ISR_BED) && |
888 | (!((i2c->msg->flags & I2C_M_IGNORE_NAK) && |
889 | (isr & ISR_ACKNAK)))) { |
890 | int ret = BUS_ERROR; |
891 | |
892 | /* |
893 | * I2C bus error - either the device NAK'd us, or |
894 | * something more serious happened. If we were NAK'd |
895 | * on the initial address phase, we can retry. |
896 | */ |
897 | if (isr & ISR_ACKNAK) { |
898 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) |
899 | ret = NO_SLAVE; |
900 | else |
901 | ret = XFER_NAKED; |
902 | } |
903 | i2c_pxa_master_complete(i2c, ret); |
904 | } else if (isr & ISR_RWM) { |
905 | /* |
906 | * Read mode. We have just sent the address byte, and |
907 | * now we must initiate the transfer. |
908 | */ |
909 | if (i2c->msg_ptr == i2c->msg->len - 1 && |
910 | i2c->msg_idx == i2c->msg_num - 1) |
911 | icr |= ICR_STOP | ICR_ACKNAK; |
912 | |
913 | icr |= ICR_ALDIE | ICR_TB; |
914 | } else if (i2c->msg_ptr < i2c->msg->len) { |
915 | /* |
916 | * Write mode. Write the next data byte. |
917 | */ |
918 | writel(val: i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
919 | |
920 | icr |= ICR_ALDIE | ICR_TB; |
921 | |
922 | /* |
923 | * If this is the last byte of the last message or last byte |
924 | * of any message with I2C_M_STOP (e.g. SCCB), send a STOP. |
925 | */ |
926 | if ((i2c->msg_ptr == i2c->msg->len) && |
927 | ((i2c->msg->flags & I2C_M_STOP) || |
928 | (i2c->msg_idx == i2c->msg_num - 1))) |
929 | icr |= ICR_STOP; |
930 | |
931 | } else if (i2c->msg_idx < i2c->msg_num - 1) { |
932 | /* |
933 | * Next segment of the message. |
934 | */ |
935 | i2c->msg_ptr = 0; |
936 | i2c->msg_idx ++; |
937 | i2c->msg++; |
938 | |
939 | /* |
940 | * If we aren't doing a repeated start and address, |
941 | * go back and try to send the next byte. Note that |
942 | * we do not support switching the R/W direction here. |
943 | */ |
944 | if (i2c->msg->flags & I2C_M_NOSTART) |
945 | goto again; |
946 | |
947 | /* |
948 | * Write the next address. |
949 | */ |
950 | i2c->req_slave_addr = i2c_8bit_addr_from_msg(msg: i2c->msg); |
951 | writel(val: i2c->req_slave_addr, _IDBR(i2c)); |
952 | |
953 | /* |
954 | * And trigger a repeated start, and send the byte. |
955 | */ |
956 | icr &= ~ICR_ALDIE; |
957 | icr |= ICR_START | ICR_TB; |
958 | } else { |
959 | if (i2c->msg->len == 0) |
960 | icr |= ICR_MA; |
961 | i2c_pxa_master_complete(i2c, ret: 0); |
962 | } |
963 | |
964 | i2c->icrlog[i2c->irqlogidx-1] = icr; |
965 | |
966 | writel(val: icr, _ICR(i2c)); |
967 | show_state(i2c); |
968 | } |
969 | |
970 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) |
971 | { |
972 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
973 | |
974 | /* |
975 | * Read the byte. |
976 | */ |
977 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
978 | |
979 | if (i2c->msg_ptr < i2c->msg->len) { |
980 | /* |
981 | * If this is the last byte of the last |
982 | * message, send a STOP. |
983 | */ |
984 | if (i2c->msg_ptr == i2c->msg->len - 1) |
985 | icr |= ICR_STOP | ICR_ACKNAK; |
986 | |
987 | icr |= ICR_ALDIE | ICR_TB; |
988 | } else { |
989 | i2c_pxa_master_complete(i2c, ret: 0); |
990 | } |
991 | |
992 | i2c->icrlog[i2c->irqlogidx-1] = icr; |
993 | |
994 | writel(val: icr, _ICR(i2c)); |
995 | } |
996 | |
997 | #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ |
998 | ISR_SAD | ISR_BED) |
999 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
1000 | { |
1001 | struct pxa_i2c *i2c = dev_id; |
1002 | u32 isr = readl(_ISR(i2c)); |
1003 | |
1004 | if (!(isr & VALID_INT_SOURCE)) |
1005 | return IRQ_NONE; |
1006 | |
1007 | if (i2c_debug > 2 && 0) { |
1008 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n" , |
1009 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
1010 | decode_ISR(val: isr); |
1011 | } |
1012 | |
1013 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
1014 | i2c->isrlog[i2c->irqlogidx++] = isr; |
1015 | |
1016 | show_state(i2c); |
1017 | |
1018 | /* |
1019 | * Always clear all pending IRQs. |
1020 | */ |
1021 | writel(val: isr & VALID_INT_SOURCE, _ISR(i2c)); |
1022 | |
1023 | if (isr & ISR_SAD) |
1024 | i2c_pxa_slave_start(i2c, isr); |
1025 | if (isr & ISR_SSD) |
1026 | i2c_pxa_slave_stop(i2c); |
1027 | |
1028 | if (i2c_pxa_is_slavemode(i2c)) { |
1029 | if (isr & ISR_ITE) |
1030 | i2c_pxa_slave_txempty(i2c, isr); |
1031 | if (isr & ISR_IRF) |
1032 | i2c_pxa_slave_rxfull(i2c, isr); |
1033 | } else if (i2c->msg && (!i2c->highmode_enter)) { |
1034 | if (isr & ISR_ITE) |
1035 | i2c_pxa_irq_txempty(i2c, isr); |
1036 | if (isr & ISR_IRF) |
1037 | i2c_pxa_irq_rxfull(i2c, isr); |
1038 | } else if ((isr & ISR_ITE) && i2c->highmode_enter) { |
1039 | i2c->highmode_enter = false; |
1040 | wake_up(&i2c->wait); |
1041 | } else { |
1042 | i2c_pxa_scream_blue_murder(i2c, why: "spurious irq" ); |
1043 | } |
1044 | |
1045 | return IRQ_HANDLED; |
1046 | } |
1047 | |
1048 | /* |
1049 | * We are protected by the adapter bus mutex. |
1050 | */ |
1051 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) |
1052 | { |
1053 | long timeout; |
1054 | int ret; |
1055 | |
1056 | /* |
1057 | * Wait for the bus to become free. |
1058 | */ |
1059 | ret = i2c_pxa_wait_bus_not_busy(i2c); |
1060 | if (ret) { |
1061 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n" ); |
1062 | i2c_recover_bus(adap: &i2c->adap); |
1063 | goto out; |
1064 | } |
1065 | |
1066 | /* |
1067 | * Set master mode. |
1068 | */ |
1069 | ret = i2c_pxa_set_master(i2c); |
1070 | if (ret) { |
1071 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n" , ret); |
1072 | goto out; |
1073 | } |
1074 | |
1075 | if (i2c->high_mode) { |
1076 | ret = i2c_pxa_send_mastercode(i2c); |
1077 | if (ret) { |
1078 | dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n" ); |
1079 | goto out; |
1080 | } |
1081 | } |
1082 | |
1083 | spin_lock_irq(lock: &i2c->lock); |
1084 | |
1085 | i2c->msg = msg; |
1086 | i2c->msg_num = num; |
1087 | i2c->msg_idx = 0; |
1088 | i2c->msg_ptr = 0; |
1089 | i2c->irqlogidx = 0; |
1090 | |
1091 | i2c_pxa_start_message(i2c); |
1092 | |
1093 | spin_unlock_irq(lock: &i2c->lock); |
1094 | |
1095 | /* |
1096 | * The rest of the processing occurs in the interrupt handler. |
1097 | */ |
1098 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
1099 | i2c_pxa_stop_message(i2c); |
1100 | |
1101 | /* |
1102 | * We place the return code in i2c->msg_idx. |
1103 | */ |
1104 | ret = i2c->msg_idx; |
1105 | |
1106 | if (!timeout && i2c->msg_num) { |
1107 | i2c_pxa_scream_blue_murder(i2c, why: "timeout with active message" ); |
1108 | i2c_recover_bus(adap: &i2c->adap); |
1109 | ret = I2C_RETRY; |
1110 | } |
1111 | |
1112 | out: |
1113 | return ret; |
1114 | } |
1115 | |
1116 | static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c, |
1117 | struct i2c_msg *msgs, int num, |
1118 | int (*xfer)(struct pxa_i2c *, |
1119 | struct i2c_msg *, int num)) |
1120 | { |
1121 | int ret, i; |
1122 | |
1123 | for (i = 0; ; ) { |
1124 | ret = xfer(i2c, msgs, num); |
1125 | if (ret != I2C_RETRY && ret != NO_SLAVE) |
1126 | goto out; |
1127 | if (++i >= i2c->adap.retries) |
1128 | break; |
1129 | |
1130 | if (i2c_debug) |
1131 | dev_dbg(&i2c->adap.dev, "Retrying transmission\n" ); |
1132 | udelay(100); |
1133 | } |
1134 | if (ret != NO_SLAVE) |
1135 | i2c_pxa_scream_blue_murder(i2c, why: "exhausted retries" ); |
1136 | ret = -EREMOTEIO; |
1137 | out: |
1138 | i2c_pxa_set_slave(i2c, errcode: ret); |
1139 | return ret; |
1140 | } |
1141 | |
1142 | static int i2c_pxa_xfer(struct i2c_adapter *adap, |
1143 | struct i2c_msg msgs[], int num) |
1144 | { |
1145 | struct pxa_i2c *i2c = adap->algo_data; |
1146 | |
1147 | return i2c_pxa_internal_xfer(i2c, msgs, num, xfer: i2c_pxa_do_xfer); |
1148 | } |
1149 | |
1150 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
1151 | { |
1152 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
1153 | I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART; |
1154 | } |
1155 | |
1156 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
1157 | .master_xfer = i2c_pxa_xfer, |
1158 | .functionality = i2c_pxa_functionality, |
1159 | #ifdef CONFIG_I2C_PXA_SLAVE |
1160 | .reg_slave = i2c_pxa_slave_reg, |
1161 | .unreg_slave = i2c_pxa_slave_unreg, |
1162 | #endif |
1163 | }; |
1164 | |
1165 | /* Non-interrupt mode support */ |
1166 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
1167 | { |
1168 | /* make timeout the same as for interrupt based functions */ |
1169 | long timeout = 2 * DEF_TIMEOUT; |
1170 | |
1171 | /* |
1172 | * Wait for the bus to become free. |
1173 | */ |
1174 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) |
1175 | udelay(1000); |
1176 | |
1177 | if (timeout < 0) { |
1178 | show_state(i2c); |
1179 | dev_err(&i2c->adap.dev, |
1180 | "i2c_pxa: timeout waiting for bus free (set_master)\n" ); |
1181 | return I2C_RETRY; |
1182 | } |
1183 | |
1184 | /* |
1185 | * Set master mode. |
1186 | */ |
1187 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
1188 | |
1189 | return 0; |
1190 | } |
1191 | |
1192 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, |
1193 | struct i2c_msg *msg, int num) |
1194 | { |
1195 | unsigned long timeout = 500000; /* 5 seconds */ |
1196 | int ret = 0; |
1197 | |
1198 | ret = i2c_pxa_pio_set_master(i2c); |
1199 | if (ret) |
1200 | goto out; |
1201 | |
1202 | i2c->msg = msg; |
1203 | i2c->msg_num = num; |
1204 | i2c->msg_idx = 0; |
1205 | i2c->msg_ptr = 0; |
1206 | i2c->irqlogidx = 0; |
1207 | |
1208 | i2c_pxa_start_message(i2c); |
1209 | |
1210 | while (i2c->msg_num > 0 && --timeout) { |
1211 | i2c_pxa_handler(this_irq: 0, dev_id: i2c); |
1212 | udelay(10); |
1213 | } |
1214 | |
1215 | i2c_pxa_stop_message(i2c); |
1216 | |
1217 | /* |
1218 | * We place the return code in i2c->msg_idx. |
1219 | */ |
1220 | ret = i2c->msg_idx; |
1221 | |
1222 | out: |
1223 | if (timeout == 0) { |
1224 | i2c_pxa_scream_blue_murder(i2c, why: "timeout (do_pio_xfer)" ); |
1225 | ret = I2C_RETRY; |
1226 | } |
1227 | |
1228 | return ret; |
1229 | } |
1230 | |
1231 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
1232 | struct i2c_msg msgs[], int num) |
1233 | { |
1234 | struct pxa_i2c *i2c = adap->algo_data; |
1235 | |
1236 | /* If the I2C controller is disabled we need to reset it |
1237 | (probably due to a suspend/resume destroying state). We do |
1238 | this here as we can then avoid worrying about resuming the |
1239 | controller before its users. */ |
1240 | if (!(readl(_ICR(i2c)) & ICR_IUE)) |
1241 | i2c_pxa_reset(i2c); |
1242 | |
1243 | return i2c_pxa_internal_xfer(i2c, msgs, num, xfer: i2c_pxa_do_pio_xfer); |
1244 | } |
1245 | |
1246 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
1247 | .master_xfer = i2c_pxa_pio_xfer, |
1248 | .functionality = i2c_pxa_functionality, |
1249 | #ifdef CONFIG_I2C_PXA_SLAVE |
1250 | .reg_slave = i2c_pxa_slave_reg, |
1251 | .unreg_slave = i2c_pxa_slave_unreg, |
1252 | #endif |
1253 | }; |
1254 | |
1255 | static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, |
1256 | enum pxa_i2c_types *i2c_types) |
1257 | { |
1258 | struct device_node *np = pdev->dev.of_node; |
1259 | |
1260 | if (!pdev->dev.of_node) |
1261 | return 1; |
1262 | |
1263 | /* For device tree we always use the dynamic or alias-assigned ID */ |
1264 | i2c->adap.nr = -1; |
1265 | |
1266 | i2c->use_pio = of_property_read_bool(np, propname: "mrvl,i2c-polling" ); |
1267 | i2c->fast_mode = of_property_read_bool(np, propname: "mrvl,i2c-fast-mode" ); |
1268 | |
1269 | *i2c_types = (enum pxa_i2c_types)device_get_match_data(dev: &pdev->dev); |
1270 | |
1271 | return 0; |
1272 | } |
1273 | |
1274 | static int i2c_pxa_probe_pdata(struct platform_device *pdev, |
1275 | struct pxa_i2c *i2c, |
1276 | enum pxa_i2c_types *i2c_types) |
1277 | { |
1278 | struct i2c_pxa_platform_data *plat = dev_get_platdata(dev: &pdev->dev); |
1279 | const struct platform_device_id *id = platform_get_device_id(pdev); |
1280 | |
1281 | *i2c_types = id->driver_data; |
1282 | if (plat) { |
1283 | i2c->use_pio = plat->use_pio; |
1284 | i2c->fast_mode = plat->fast_mode; |
1285 | i2c->high_mode = plat->high_mode; |
1286 | i2c->master_code = plat->master_code; |
1287 | if (!i2c->master_code) |
1288 | i2c->master_code = 0xe; |
1289 | i2c->rate = plat->rate; |
1290 | } |
1291 | return 0; |
1292 | } |
1293 | |
1294 | static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap) |
1295 | { |
1296 | struct pxa_i2c *i2c = adap->algo_data; |
1297 | u32 ibmr = readl(_IBMR(i2c)); |
1298 | |
1299 | /* |
1300 | * Program the GPIOs to reflect the current I2C bus state while |
1301 | * we transition to recovery; this avoids glitching the bus. |
1302 | */ |
1303 | gpiod_set_value(desc: i2c->recovery.scl_gpiod, value: ibmr & IBMR_SCLS); |
1304 | gpiod_set_value(desc: i2c->recovery.sda_gpiod, value: ibmr & IBMR_SDAS); |
1305 | |
1306 | WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery)); |
1307 | } |
1308 | |
1309 | static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap) |
1310 | { |
1311 | struct pxa_i2c *i2c = adap->algo_data; |
1312 | u32 isr; |
1313 | |
1314 | /* |
1315 | * The bus should now be free. Clear up the I2C controller before |
1316 | * handing control of the bus back to avoid the bus changing state. |
1317 | */ |
1318 | isr = readl(_ISR(i2c)); |
1319 | if (isr & (ISR_UB | ISR_IBB)) { |
1320 | dev_dbg(&i2c->adap.dev, |
1321 | "recovery: resetting controller, ISR=0x%08x\n" , isr); |
1322 | i2c_pxa_do_reset(i2c); |
1323 | } |
1324 | |
1325 | WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default)); |
1326 | |
1327 | dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n" , |
1328 | readl(_IBMR(i2c)), readl(_ISR(i2c))); |
1329 | |
1330 | i2c_pxa_enable(i2c); |
1331 | } |
1332 | |
1333 | static int i2c_pxa_init_recovery(struct pxa_i2c *i2c) |
1334 | { |
1335 | struct i2c_bus_recovery_info *bri = &i2c->recovery; |
1336 | struct device *dev = i2c->adap.dev.parent; |
1337 | |
1338 | /* |
1339 | * When slave mode is enabled, we are not the only master on the bus. |
1340 | * Bus recovery can only be performed when we are the master, which |
1341 | * we can't be certain of. Therefore, when slave mode is enabled, do |
1342 | * not configure bus recovery. |
1343 | */ |
1344 | if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE)) |
1345 | return 0; |
1346 | |
1347 | i2c->pinctrl = devm_pinctrl_get(dev); |
1348 | if (PTR_ERR(ptr: i2c->pinctrl) == -ENODEV) |
1349 | i2c->pinctrl = NULL; |
1350 | if (IS_ERR(ptr: i2c->pinctrl)) |
1351 | return PTR_ERR(ptr: i2c->pinctrl); |
1352 | |
1353 | if (!i2c->pinctrl) |
1354 | return 0; |
1355 | |
1356 | i2c->pinctrl_default = pinctrl_lookup_state(p: i2c->pinctrl, |
1357 | PINCTRL_STATE_DEFAULT); |
1358 | i2c->pinctrl_recovery = pinctrl_lookup_state(p: i2c->pinctrl, name: "recovery" ); |
1359 | |
1360 | if (IS_ERR(ptr: i2c->pinctrl_default) || IS_ERR(ptr: i2c->pinctrl_recovery)) { |
1361 | dev_info(dev, "missing pinmux recovery information: %ld %ld\n" , |
1362 | PTR_ERR(i2c->pinctrl_default), |
1363 | PTR_ERR(i2c->pinctrl_recovery)); |
1364 | return 0; |
1365 | } |
1366 | |
1367 | /* |
1368 | * Claiming GPIOs can influence the pinmux state, and may glitch the |
1369 | * I2C bus. Do this carefully. |
1370 | */ |
1371 | bri->scl_gpiod = devm_gpiod_get(dev, con_id: "scl" , flags: GPIOD_OUT_HIGH_OPEN_DRAIN); |
1372 | if (bri->scl_gpiod == ERR_PTR(error: -EPROBE_DEFER)) |
1373 | return -EPROBE_DEFER; |
1374 | if (IS_ERR(ptr: bri->scl_gpiod)) { |
1375 | dev_info(dev, "missing scl gpio recovery information: %pe\n" , |
1376 | bri->scl_gpiod); |
1377 | return 0; |
1378 | } |
1379 | |
1380 | /* |
1381 | * We have SCL. Pull SCL low and wait a bit so that SDA glitches |
1382 | * have no effect. |
1383 | */ |
1384 | gpiod_direction_output(desc: bri->scl_gpiod, value: 0); |
1385 | udelay(10); |
1386 | bri->sda_gpiod = devm_gpiod_get(dev, con_id: "sda" , flags: GPIOD_OUT_HIGH_OPEN_DRAIN); |
1387 | |
1388 | /* Wait a bit in case of a SDA glitch, and then release SCL. */ |
1389 | udelay(10); |
1390 | gpiod_direction_output(desc: bri->scl_gpiod, value: 1); |
1391 | |
1392 | if (bri->sda_gpiod == ERR_PTR(error: -EPROBE_DEFER)) |
1393 | return -EPROBE_DEFER; |
1394 | |
1395 | if (IS_ERR(ptr: bri->sda_gpiod)) { |
1396 | dev_info(dev, "missing sda gpio recovery information: %pe\n" , |
1397 | bri->sda_gpiod); |
1398 | return 0; |
1399 | } |
1400 | |
1401 | bri->prepare_recovery = i2c_pxa_prepare_recovery; |
1402 | bri->unprepare_recovery = i2c_pxa_unprepare_recovery; |
1403 | bri->recover_bus = i2c_generic_scl_recovery; |
1404 | |
1405 | i2c->adap.bus_recovery_info = bri; |
1406 | |
1407 | /* |
1408 | * Claiming GPIOs can change the pinmux state, which confuses the |
1409 | * pinctrl since pinctrl's idea of the current setting is unaffected |
1410 | * by the pinmux change caused by claiming the GPIO. Work around that |
1411 | * by switching pinctrl to the GPIO state here. We do it this way to |
1412 | * avoid glitching the I2C bus. |
1413 | */ |
1414 | pinctrl_select_state(p: i2c->pinctrl, s: i2c->pinctrl_recovery); |
1415 | |
1416 | return pinctrl_select_state(p: i2c->pinctrl, s: i2c->pinctrl_default); |
1417 | } |
1418 | |
1419 | static int i2c_pxa_probe(struct platform_device *dev) |
1420 | { |
1421 | struct i2c_pxa_platform_data *plat = dev_get_platdata(dev: &dev->dev); |
1422 | enum pxa_i2c_types i2c_type; |
1423 | struct pxa_i2c *i2c; |
1424 | struct resource *res; |
1425 | int ret, irq; |
1426 | |
1427 | i2c = devm_kzalloc(dev: &dev->dev, size: sizeof(struct pxa_i2c), GFP_KERNEL); |
1428 | if (!i2c) |
1429 | return -ENOMEM; |
1430 | |
1431 | /* Default adapter num to device id; i2c_pxa_probe_dt can override. */ |
1432 | i2c->adap.nr = dev->id; |
1433 | i2c->adap.owner = THIS_MODULE; |
1434 | i2c->adap.retries = 5; |
1435 | i2c->adap.algo_data = i2c; |
1436 | i2c->adap.dev.parent = &dev->dev; |
1437 | #ifdef CONFIG_OF |
1438 | i2c->adap.dev.of_node = dev->dev.of_node; |
1439 | #endif |
1440 | |
1441 | i2c->reg_base = devm_platform_get_and_ioremap_resource(pdev: dev, index: 0, res: &res); |
1442 | if (IS_ERR(ptr: i2c->reg_base)) |
1443 | return PTR_ERR(ptr: i2c->reg_base); |
1444 | |
1445 | irq = platform_get_irq(dev, 0); |
1446 | if (irq < 0) |
1447 | return irq; |
1448 | |
1449 | ret = i2c_pxa_init_recovery(i2c); |
1450 | if (ret) |
1451 | return ret; |
1452 | |
1453 | ret = i2c_pxa_probe_dt(pdev: dev, i2c, i2c_types: &i2c_type); |
1454 | if (ret > 0) |
1455 | ret = i2c_pxa_probe_pdata(pdev: dev, i2c, i2c_types: &i2c_type); |
1456 | if (ret < 0) |
1457 | return ret; |
1458 | |
1459 | spin_lock_init(&i2c->lock); |
1460 | init_waitqueue_head(&i2c->wait); |
1461 | |
1462 | strscpy(i2c->adap.name, "pxa_i2c-i2c" , sizeof(i2c->adap.name)); |
1463 | |
1464 | i2c->clk = devm_clk_get(dev: &dev->dev, NULL); |
1465 | if (IS_ERR(ptr: i2c->clk)) |
1466 | return dev_err_probe(dev: &dev->dev, err: PTR_ERR(ptr: i2c->clk), |
1467 | fmt: "failed to get the clk\n" ); |
1468 | |
1469 | i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; |
1470 | i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; |
1471 | i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; |
1472 | i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; |
1473 | i2c->fm_mask = pxa_reg_layout[i2c_type].fm; |
1474 | i2c->hs_mask = pxa_reg_layout[i2c_type].hs; |
1475 | |
1476 | if (i2c_type != REGS_CE4100) |
1477 | i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; |
1478 | |
1479 | if (i2c_type == REGS_PXA910) { |
1480 | i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr; |
1481 | i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr; |
1482 | } |
1483 | |
1484 | i2c->iobase = res->start; |
1485 | i2c->iosize = resource_size(res); |
1486 | |
1487 | i2c->irq = irq; |
1488 | |
1489 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; |
1490 | i2c->highmode_enter = false; |
1491 | |
1492 | if (plat) { |
1493 | i2c->adap.class = plat->class; |
1494 | } |
1495 | |
1496 | if (i2c->high_mode) { |
1497 | if (i2c->rate) { |
1498 | clk_set_rate(clk: i2c->clk, rate: i2c->rate); |
1499 | pr_info("i2c: <%s> set rate to %ld\n" , |
1500 | i2c->adap.name, clk_get_rate(i2c->clk)); |
1501 | } else |
1502 | pr_warn("i2c: <%s> clock rate not set\n" , |
1503 | i2c->adap.name); |
1504 | } |
1505 | |
1506 | clk_prepare_enable(clk: i2c->clk); |
1507 | |
1508 | if (i2c->use_pio) { |
1509 | i2c->adap.algo = &i2c_pxa_pio_algorithm; |
1510 | } else { |
1511 | i2c->adap.algo = &i2c_pxa_algorithm; |
1512 | ret = devm_request_irq(dev: &dev->dev, irq, handler: i2c_pxa_handler, |
1513 | IRQF_SHARED | IRQF_NO_SUSPEND, |
1514 | devname: dev_name(dev: &dev->dev), dev_id: i2c); |
1515 | if (ret) { |
1516 | dev_err(&dev->dev, "failed to request irq: %d\n" , ret); |
1517 | goto ereqirq; |
1518 | } |
1519 | } |
1520 | |
1521 | i2c_pxa_reset(i2c); |
1522 | |
1523 | ret = i2c_add_numbered_adapter(adap: &i2c->adap); |
1524 | if (ret < 0) |
1525 | goto ereqirq; |
1526 | |
1527 | platform_set_drvdata(pdev: dev, data: i2c); |
1528 | |
1529 | #ifdef CONFIG_I2C_PXA_SLAVE |
1530 | dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n" , |
1531 | i2c->slave_addr); |
1532 | #else |
1533 | dev_info(&i2c->adap.dev, " PXA I2C adapter\n" ); |
1534 | #endif |
1535 | return 0; |
1536 | |
1537 | ereqirq: |
1538 | clk_disable_unprepare(clk: i2c->clk); |
1539 | return ret; |
1540 | } |
1541 | |
1542 | static void i2c_pxa_remove(struct platform_device *dev) |
1543 | { |
1544 | struct pxa_i2c *i2c = platform_get_drvdata(pdev: dev); |
1545 | |
1546 | i2c_del_adapter(adap: &i2c->adap); |
1547 | |
1548 | clk_disable_unprepare(clk: i2c->clk); |
1549 | } |
1550 | |
1551 | static int i2c_pxa_suspend_noirq(struct device *dev) |
1552 | { |
1553 | struct pxa_i2c *i2c = dev_get_drvdata(dev); |
1554 | |
1555 | clk_disable(clk: i2c->clk); |
1556 | |
1557 | return 0; |
1558 | } |
1559 | |
1560 | static int i2c_pxa_resume_noirq(struct device *dev) |
1561 | { |
1562 | struct pxa_i2c *i2c = dev_get_drvdata(dev); |
1563 | |
1564 | clk_enable(clk: i2c->clk); |
1565 | i2c_pxa_reset(i2c); |
1566 | |
1567 | return 0; |
1568 | } |
1569 | |
1570 | static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { |
1571 | .suspend_noirq = i2c_pxa_suspend_noirq, |
1572 | .resume_noirq = i2c_pxa_resume_noirq, |
1573 | }; |
1574 | |
1575 | static struct platform_driver i2c_pxa_driver = { |
1576 | .probe = i2c_pxa_probe, |
1577 | .remove_new = i2c_pxa_remove, |
1578 | .driver = { |
1579 | .name = "pxa2xx-i2c" , |
1580 | .pm = pm_sleep_ptr(&i2c_pxa_dev_pm_ops), |
1581 | .of_match_table = i2c_pxa_dt_ids, |
1582 | }, |
1583 | .id_table = i2c_pxa_id_table, |
1584 | }; |
1585 | |
1586 | static int __init i2c_adap_pxa_init(void) |
1587 | { |
1588 | return platform_driver_register(&i2c_pxa_driver); |
1589 | } |
1590 | |
1591 | static void __exit i2c_adap_pxa_exit(void) |
1592 | { |
1593 | platform_driver_unregister(&i2c_pxa_driver); |
1594 | } |
1595 | |
1596 | MODULE_LICENSE("GPL" ); |
1597 | |
1598 | subsys_initcall(i2c_adap_pxa_init); |
1599 | module_exit(i2c_adap_pxa_exit); |
1600 | |