1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Wondermedia I2C Master Mode Driver
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 *
7 * Derived from GPLv2+ licensed source:
8 * - Copyright (C) 2008 WonderMedia Technologies, Inc.
9 */
10
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/i2c.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/platform_device.h>
22
23#define REG_CR 0x00
24#define REG_TCR 0x02
25#define REG_CSR 0x04
26#define REG_ISR 0x06
27#define REG_IMR 0x08
28#define REG_CDR 0x0A
29#define REG_TR 0x0C
30#define REG_MCR 0x0E
31#define REG_SLAVE_CR 0x10
32#define REG_SLAVE_SR 0x12
33#define REG_SLAVE_ISR 0x14
34#define REG_SLAVE_IMR 0x16
35#define REG_SLAVE_DR 0x18
36#define REG_SLAVE_TR 0x1A
37
38/* REG_CR Bit fields */
39#define CR_TX_NEXT_ACK 0x0000
40#define CR_ENABLE 0x0001
41#define CR_TX_NEXT_NO_ACK 0x0002
42#define CR_TX_END 0x0004
43#define CR_CPU_RDY 0x0008
44#define SLAV_MODE_SEL 0x8000
45
46/* REG_TCR Bit fields */
47#define TCR_STANDARD_MODE 0x0000
48#define TCR_MASTER_WRITE 0x0000
49#define TCR_HS_MODE 0x2000
50#define TCR_MASTER_READ 0x4000
51#define TCR_FAST_MODE 0x8000
52#define TCR_SLAVE_ADDR_MASK 0x007F
53
54/* REG_ISR Bit fields */
55#define ISR_NACK_ADDR 0x0001
56#define ISR_BYTE_END 0x0002
57#define ISR_SCL_TIMEOUT 0x0004
58#define ISR_WRITE_ALL 0x0007
59
60/* REG_IMR Bit fields */
61#define IMR_ENABLE_ALL 0x0007
62
63/* REG_CSR Bit fields */
64#define CSR_RCV_NOT_ACK 0x0001
65#define CSR_RCV_ACK_MASK 0x0001
66#define CSR_READY_MASK 0x0002
67
68/* REG_TR */
69#define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
70#define TR_STD 0x0064
71#define TR_HS 0x0019
72
73/* REG_MCR */
74#define MCR_APB_96M 7
75#define MCR_APB_166M 12
76
77#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
78
79struct wmt_i2c_dev {
80 struct i2c_adapter adapter;
81 struct completion complete;
82 struct device *dev;
83 void __iomem *base;
84 struct clk *clk;
85 u16 tcr;
86 int irq;
87 u16 cmd_status;
88};
89
90static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
91{
92 unsigned long timeout;
93
94 timeout = jiffies + WMT_I2C_TIMEOUT;
95 while (!(readw(addr: i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
96 if (time_after(jiffies, timeout)) {
97 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
98 return -EBUSY;
99 }
100 msleep(msecs: 20);
101 }
102
103 return 0;
104}
105
106static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
107{
108 int ret = 0;
109 unsigned long wait_result;
110
111 wait_result = wait_for_completion_timeout(x: &i2c_dev->complete,
112 timeout: msecs_to_jiffies(m: 500));
113 if (!wait_result)
114 return -ETIMEDOUT;
115
116 if (i2c_dev->cmd_status & ISR_NACK_ADDR)
117 ret = -EIO;
118
119 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
120 ret = -ETIMEDOUT;
121
122 return ret;
123}
124
125static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg,
126 int last)
127{
128 u16 val, tcr_val = i2c_dev->tcr;
129 int ret;
130 int xfer_len = 0;
131
132 if (pmsg->len == 0) {
133 /*
134 * We still need to run through the while (..) once, so
135 * start at -1 and break out early from the loop
136 */
137 xfer_len = -1;
138 writew(val: 0, addr: i2c_dev->base + REG_CDR);
139 } else {
140 writew(val: pmsg->buf[0] & 0xFF, addr: i2c_dev->base + REG_CDR);
141 }
142
143 if (!(pmsg->flags & I2C_M_NOSTART)) {
144 val = readw(addr: i2c_dev->base + REG_CR);
145 val &= ~CR_TX_END;
146 val |= CR_CPU_RDY;
147 writew(val, addr: i2c_dev->base + REG_CR);
148 }
149
150 reinit_completion(x: &i2c_dev->complete);
151
152 tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
153
154 writew(val: tcr_val, addr: i2c_dev->base + REG_TCR);
155
156 if (pmsg->flags & I2C_M_NOSTART) {
157 val = readw(addr: i2c_dev->base + REG_CR);
158 val |= CR_CPU_RDY;
159 writew(val, addr: i2c_dev->base + REG_CR);
160 }
161
162 while (xfer_len < pmsg->len) {
163 ret = wmt_check_status(i2c_dev);
164 if (ret)
165 return ret;
166
167 xfer_len++;
168
169 val = readw(addr: i2c_dev->base + REG_CSR);
170 if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
171 dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
172 return -EIO;
173 }
174
175 if (pmsg->len == 0) {
176 val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
177 writew(val, addr: i2c_dev->base + REG_CR);
178 break;
179 }
180
181 if (xfer_len == pmsg->len) {
182 if (last != 1)
183 writew(CR_ENABLE, addr: i2c_dev->base + REG_CR);
184 } else {
185 writew(val: pmsg->buf[xfer_len] & 0xFF, addr: i2c_dev->base +
186 REG_CDR);
187 writew(CR_CPU_RDY | CR_ENABLE, addr: i2c_dev->base + REG_CR);
188 }
189 }
190
191 return 0;
192}
193
194static int wmt_i2c_read(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg)
195{
196 u16 val, tcr_val = i2c_dev->tcr;
197 int ret;
198 u32 xfer_len = 0;
199
200 val = readw(addr: i2c_dev->base + REG_CR);
201 val &= ~(CR_TX_END | CR_TX_NEXT_NO_ACK);
202
203 if (!(pmsg->flags & I2C_M_NOSTART))
204 val |= CR_CPU_RDY;
205
206 if (pmsg->len == 1)
207 val |= CR_TX_NEXT_NO_ACK;
208
209 writew(val, addr: i2c_dev->base + REG_CR);
210
211 reinit_completion(x: &i2c_dev->complete);
212
213 tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
214
215 writew(val: tcr_val, addr: i2c_dev->base + REG_TCR);
216
217 if (pmsg->flags & I2C_M_NOSTART) {
218 val = readw(addr: i2c_dev->base + REG_CR);
219 val |= CR_CPU_RDY;
220 writew(val, addr: i2c_dev->base + REG_CR);
221 }
222
223 while (xfer_len < pmsg->len) {
224 ret = wmt_check_status(i2c_dev);
225 if (ret)
226 return ret;
227
228 pmsg->buf[xfer_len] = readw(addr: i2c_dev->base + REG_CDR) >> 8;
229 xfer_len++;
230
231 val = readw(addr: i2c_dev->base + REG_CR) | CR_CPU_RDY;
232 if (xfer_len == pmsg->len - 1)
233 val |= CR_TX_NEXT_NO_ACK;
234 writew(val, addr: i2c_dev->base + REG_CR);
235 }
236
237 return 0;
238}
239
240static int wmt_i2c_xfer(struct i2c_adapter *adap,
241 struct i2c_msg msgs[],
242 int num)
243{
244 struct i2c_msg *pmsg;
245 int i;
246 int ret = 0;
247 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
248
249 for (i = 0; ret >= 0 && i < num; i++) {
250 pmsg = &msgs[i];
251 if (!(pmsg->flags & I2C_M_NOSTART)) {
252 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
253 if (ret < 0)
254 return ret;
255 }
256
257 if (pmsg->flags & I2C_M_RD)
258 ret = wmt_i2c_read(i2c_dev, pmsg);
259 else
260 ret = wmt_i2c_write(i2c_dev, pmsg, last: (i + 1) == num);
261 }
262
263 return (ret < 0) ? ret : i;
264}
265
266static u32 wmt_i2c_func(struct i2c_adapter *adap)
267{
268 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
269}
270
271static const struct i2c_algorithm wmt_i2c_algo = {
272 .master_xfer = wmt_i2c_xfer,
273 .functionality = wmt_i2c_func,
274};
275
276static irqreturn_t wmt_i2c_isr(int irq, void *data)
277{
278 struct wmt_i2c_dev *i2c_dev = data;
279
280 /* save the status and write-clear it */
281 i2c_dev->cmd_status = readw(addr: i2c_dev->base + REG_ISR);
282 writew(val: i2c_dev->cmd_status, addr: i2c_dev->base + REG_ISR);
283
284 complete(&i2c_dev->complete);
285
286 return IRQ_HANDLED;
287}
288
289static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
290{
291 int err;
292
293 err = clk_prepare_enable(clk: i2c_dev->clk);
294 if (err) {
295 dev_err(i2c_dev->dev, "failed to enable clock\n");
296 return err;
297 }
298
299 err = clk_set_rate(clk: i2c_dev->clk, rate: 20000000);
300 if (err) {
301 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
302 clk_disable_unprepare(clk: i2c_dev->clk);
303 return err;
304 }
305
306 writew(val: 0, addr: i2c_dev->base + REG_CR);
307 writew(MCR_APB_166M, addr: i2c_dev->base + REG_MCR);
308 writew(ISR_WRITE_ALL, addr: i2c_dev->base + REG_ISR);
309 writew(IMR_ENABLE_ALL, addr: i2c_dev->base + REG_IMR);
310 writew(CR_ENABLE, addr: i2c_dev->base + REG_CR);
311 readw(addr: i2c_dev->base + REG_CSR); /* read clear */
312 writew(ISR_WRITE_ALL, addr: i2c_dev->base + REG_ISR);
313
314 if (i2c_dev->tcr == TCR_FAST_MODE)
315 writew(SCL_TIMEOUT(128) | TR_HS, addr: i2c_dev->base + REG_TR);
316 else
317 writew(SCL_TIMEOUT(128) | TR_STD, addr: i2c_dev->base + REG_TR);
318
319 return 0;
320}
321
322static int wmt_i2c_probe(struct platform_device *pdev)
323{
324 struct device_node *np = pdev->dev.of_node;
325 struct wmt_i2c_dev *i2c_dev;
326 struct i2c_adapter *adap;
327 int err;
328 u32 clk_rate;
329
330 i2c_dev = devm_kzalloc(dev: &pdev->dev, size: sizeof(*i2c_dev), GFP_KERNEL);
331 if (!i2c_dev)
332 return -ENOMEM;
333
334 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, index: 0, NULL);
335 if (IS_ERR(ptr: i2c_dev->base))
336 return PTR_ERR(ptr: i2c_dev->base);
337
338 i2c_dev->irq = irq_of_parse_and_map(node: np, index: 0);
339 if (!i2c_dev->irq) {
340 dev_err(&pdev->dev, "irq missing or invalid\n");
341 return -EINVAL;
342 }
343
344 i2c_dev->clk = of_clk_get(np, index: 0);
345 if (IS_ERR(ptr: i2c_dev->clk)) {
346 dev_err(&pdev->dev, "unable to request clock\n");
347 return PTR_ERR(ptr: i2c_dev->clk);
348 }
349
350 err = of_property_read_u32(np, propname: "clock-frequency", out_value: &clk_rate);
351 if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ))
352 i2c_dev->tcr = TCR_FAST_MODE;
353
354 i2c_dev->dev = &pdev->dev;
355
356 err = devm_request_irq(dev: &pdev->dev, irq: i2c_dev->irq, handler: wmt_i2c_isr, irqflags: 0,
357 devname: "i2c", dev_id: i2c_dev);
358 if (err) {
359 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
360 return err;
361 }
362
363 adap = &i2c_dev->adapter;
364 i2c_set_adapdata(adap, data: i2c_dev);
365 strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
366 adap->owner = THIS_MODULE;
367 adap->algo = &wmt_i2c_algo;
368 adap->dev.parent = &pdev->dev;
369 adap->dev.of_node = pdev->dev.of_node;
370
371 init_completion(x: &i2c_dev->complete);
372
373 err = wmt_i2c_reset_hardware(i2c_dev);
374 if (err) {
375 dev_err(&pdev->dev, "error initializing hardware\n");
376 return err;
377 }
378
379 err = i2c_add_adapter(adap);
380 if (err)
381 goto err_disable_clk;
382
383 platform_set_drvdata(pdev, data: i2c_dev);
384
385 return 0;
386
387err_disable_clk:
388 clk_disable_unprepare(clk: i2c_dev->clk);
389 return err;
390}
391
392static void wmt_i2c_remove(struct platform_device *pdev)
393{
394 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
395
396 /* Disable interrupts, clock and delete adapter */
397 writew(val: 0, addr: i2c_dev->base + REG_IMR);
398 clk_disable_unprepare(clk: i2c_dev->clk);
399 i2c_del_adapter(adap: &i2c_dev->adapter);
400}
401
402static const struct of_device_id wmt_i2c_dt_ids[] = {
403 { .compatible = "wm,wm8505-i2c" },
404 { /* Sentinel */ },
405};
406
407static struct platform_driver wmt_i2c_driver = {
408 .probe = wmt_i2c_probe,
409 .remove_new = wmt_i2c_remove,
410 .driver = {
411 .name = "wmt-i2c",
412 .of_match_table = wmt_i2c_dt_ids,
413 },
414};
415
416module_platform_driver(wmt_i2c_driver);
417
418MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
419MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
420MODULE_LICENSE("GPL");
421MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
422

source code of linux/drivers/i2c/busses/i2c-wmt.c