1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (C) 2013 STMicroelectronics Limited |
4 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> |
5 | */ |
6 | #include <linux/kernel.h> |
7 | #include <linux/clk.h> |
8 | #include <linux/interrupt.h> |
9 | #include <linux/module.h> |
10 | #include <linux/of.h> |
11 | #include <linux/platform_device.h> |
12 | #include <linux/reset.h> |
13 | #include <media/rc-core.h> |
14 | #include <linux/pinctrl/consumer.h> |
15 | #include <linux/pm_wakeirq.h> |
16 | |
17 | struct st_rc_device { |
18 | struct device *dev; |
19 | int irq; |
20 | int irq_wake; |
21 | struct clk *sys_clock; |
22 | void __iomem *base; /* Register base address */ |
23 | void __iomem *rx_base;/* RX Register base address */ |
24 | struct rc_dev *rdev; |
25 | bool overclocking; |
26 | int sample_mult; |
27 | int sample_div; |
28 | bool rxuhfmode; |
29 | struct reset_control *rstc; |
30 | }; |
31 | |
32 | /* Registers */ |
33 | #define IRB_SAMPLE_RATE_COMM 0x64 /* sample freq divisor*/ |
34 | #define IRB_CLOCK_SEL 0x70 /* clock select */ |
35 | #define IRB_CLOCK_SEL_STATUS 0x74 /* clock status */ |
36 | /* IRB IR/UHF receiver registers */ |
37 | #define IRB_RX_ON 0x40 /* pulse time capture */ |
38 | #define IRB_RX_SYS 0X44 /* sym period capture */ |
39 | #define IRB_RX_INT_EN 0x48 /* IRQ enable (R/W) */ |
40 | #define IRB_RX_INT_STATUS 0x4c /* IRQ status (R/W) */ |
41 | #define IRB_RX_EN 0x50 /* Receive enable */ |
42 | #define IRB_MAX_SYM_PERIOD 0x54 /* max sym value */ |
43 | #define IRB_RX_INT_CLEAR 0x58 /* overrun status */ |
44 | #define IRB_RX_STATUS 0x6c /* receive status */ |
45 | #define IRB_RX_NOISE_SUPPR 0x5c /* noise suppression */ |
46 | #define IRB_RX_POLARITY_INV 0x68 /* polarity inverter */ |
47 | |
48 | /* |
49 | * IRQ set: Enable full FIFO 1 -> bit 3; |
50 | * Enable overrun IRQ 1 -> bit 2; |
51 | * Enable last symbol IRQ 1 -> bit 1: |
52 | * Enable RX interrupt 1 -> bit 0; |
53 | */ |
54 | #define IRB_RX_INTS 0x0f |
55 | #define IRB_RX_OVERRUN_INT 0x04 |
56 | /* maximum symbol period (microsecs),timeout to detect end of symbol train */ |
57 | #define MAX_SYMB_TIME 0x5000 |
58 | #define IRB_SAMPLE_FREQ 10000000 |
59 | #define IRB_FIFO_NOT_EMPTY 0xff00 |
60 | #define IRB_OVERFLOW 0x4 |
61 | #define IRB_TIMEOUT 0xffff |
62 | #define IR_ST_NAME "st-rc" |
63 | |
64 | static void st_rc_send_lirc_timeout(struct rc_dev *rdev) |
65 | { |
66 | struct ir_raw_event ev = { .timeout = true, .duration = rdev->timeout }; |
67 | ir_raw_event_store(dev: rdev, ev: &ev); |
68 | } |
69 | |
70 | /* |
71 | * RX graphical example to better understand the difference between ST IR block |
72 | * output and standard definition used by LIRC (and most of the world!) |
73 | * |
74 | * mark mark |
75 | * |-IRB_RX_ON-| |-IRB_RX_ON-| |
76 | * ___ ___ ___ ___ ___ ___ _ |
77 | * | | | | | | | | | | | | | |
78 | * | | | | | | space 0 | | | | | | space 1 | |
79 | * _____| |__| |__| |____________________________| |__| |__| |_____________| |
80 | * |
81 | * |--------------- IRB_RX_SYS -------------|------ IRB_RX_SYS -------| |
82 | * |
83 | * |------------- encoding bit 0 -----------|---- encoding bit 1 -----| |
84 | * |
85 | * ST hardware returns mark (IRB_RX_ON) and total symbol time (IRB_RX_SYS), so |
86 | * convert to standard mark/space we have to calculate space=(IRB_RX_SYS-mark) |
87 | * The mark time represents the amount of time the carrier (usually 36-40kHz) |
88 | * is detected.The above examples shows Pulse Width Modulation encoding where |
89 | * bit 0 is represented by space>mark. |
90 | */ |
91 | |
92 | static irqreturn_t st_rc_rx_interrupt(int irq, void *data) |
93 | { |
94 | unsigned long timeout; |
95 | unsigned int symbol, mark = 0; |
96 | struct st_rc_device *dev = data; |
97 | int last_symbol = 0; |
98 | u32 status, int_status; |
99 | struct ir_raw_event ev = {}; |
100 | |
101 | if (dev->irq_wake) |
102 | pm_wakeup_event(dev: dev->dev, msec: 0); |
103 | |
104 | /* FIXME: is 10ms good enough ? */ |
105 | timeout = jiffies + msecs_to_jiffies(m: 10); |
106 | do { |
107 | status = readl(addr: dev->rx_base + IRB_RX_STATUS); |
108 | if (!(status & (IRB_FIFO_NOT_EMPTY | IRB_OVERFLOW))) |
109 | break; |
110 | |
111 | int_status = readl(addr: dev->rx_base + IRB_RX_INT_STATUS); |
112 | if (unlikely(int_status & IRB_RX_OVERRUN_INT)) { |
113 | /* discard the entire collection in case of errors! */ |
114 | ir_raw_event_overflow(dev: dev->rdev); |
115 | dev_info(dev->dev, "IR RX overrun\n" ); |
116 | writel(IRB_RX_OVERRUN_INT, |
117 | addr: dev->rx_base + IRB_RX_INT_CLEAR); |
118 | continue; |
119 | } |
120 | |
121 | symbol = readl(addr: dev->rx_base + IRB_RX_SYS); |
122 | mark = readl(addr: dev->rx_base + IRB_RX_ON); |
123 | |
124 | if (symbol == IRB_TIMEOUT) |
125 | last_symbol = 1; |
126 | |
127 | /* Ignore any noise */ |
128 | if ((mark > 2) && (symbol > 1)) { |
129 | symbol -= mark; |
130 | if (dev->overclocking) { /* adjustments to timings */ |
131 | symbol *= dev->sample_mult; |
132 | symbol /= dev->sample_div; |
133 | mark *= dev->sample_mult; |
134 | mark /= dev->sample_div; |
135 | } |
136 | |
137 | ev.duration = mark; |
138 | ev.pulse = true; |
139 | ir_raw_event_store(dev: dev->rdev, ev: &ev); |
140 | |
141 | if (!last_symbol) { |
142 | ev.duration = symbol; |
143 | ev.pulse = false; |
144 | ir_raw_event_store(dev: dev->rdev, ev: &ev); |
145 | } else { |
146 | st_rc_send_lirc_timeout(rdev: dev->rdev); |
147 | } |
148 | |
149 | } |
150 | last_symbol = 0; |
151 | } while (time_is_after_jiffies(timeout)); |
152 | |
153 | writel(IRB_RX_INTS, addr: dev->rx_base + IRB_RX_INT_CLEAR); |
154 | |
155 | /* Empty software fifo */ |
156 | ir_raw_event_handle(dev: dev->rdev); |
157 | return IRQ_HANDLED; |
158 | } |
159 | |
160 | static int st_rc_hardware_init(struct st_rc_device *dev) |
161 | { |
162 | int ret; |
163 | int baseclock, freqdiff; |
164 | unsigned int rx_max_symbol_per = MAX_SYMB_TIME; |
165 | unsigned int rx_sampling_freq_div; |
166 | |
167 | /* Enable the IP */ |
168 | reset_control_deassert(rstc: dev->rstc); |
169 | |
170 | ret = clk_prepare_enable(clk: dev->sys_clock); |
171 | if (ret) { |
172 | dev_err(dev->dev, "Failed to prepare/enable system clock\n" ); |
173 | return ret; |
174 | } |
175 | |
176 | baseclock = clk_get_rate(clk: dev->sys_clock); |
177 | |
178 | /* IRB input pins are inverted internally from high to low. */ |
179 | writel(val: 1, addr: dev->rx_base + IRB_RX_POLARITY_INV); |
180 | |
181 | rx_sampling_freq_div = baseclock / IRB_SAMPLE_FREQ; |
182 | writel(val: rx_sampling_freq_div, addr: dev->base + IRB_SAMPLE_RATE_COMM); |
183 | |
184 | freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ); |
185 | if (freqdiff) { /* over clocking, workout the adjustment factors */ |
186 | dev->overclocking = true; |
187 | dev->sample_mult = 1000; |
188 | dev->sample_div = baseclock / (10000 * rx_sampling_freq_div); |
189 | rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div; |
190 | } |
191 | |
192 | writel(val: rx_max_symbol_per, addr: dev->rx_base + IRB_MAX_SYM_PERIOD); |
193 | |
194 | return 0; |
195 | } |
196 | |
197 | static void st_rc_remove(struct platform_device *pdev) |
198 | { |
199 | struct st_rc_device *rc_dev = platform_get_drvdata(pdev); |
200 | |
201 | dev_pm_clear_wake_irq(dev: &pdev->dev); |
202 | device_init_wakeup(dev: &pdev->dev, enable: false); |
203 | clk_disable_unprepare(clk: rc_dev->sys_clock); |
204 | rc_unregister_device(dev: rc_dev->rdev); |
205 | } |
206 | |
207 | static int st_rc_open(struct rc_dev *rdev) |
208 | { |
209 | struct st_rc_device *dev = rdev->priv; |
210 | unsigned long flags; |
211 | local_irq_save(flags); |
212 | /* enable interrupts and receiver */ |
213 | writel(IRB_RX_INTS, addr: dev->rx_base + IRB_RX_INT_EN); |
214 | writel(val: 0x01, addr: dev->rx_base + IRB_RX_EN); |
215 | local_irq_restore(flags); |
216 | |
217 | return 0; |
218 | } |
219 | |
220 | static void st_rc_close(struct rc_dev *rdev) |
221 | { |
222 | struct st_rc_device *dev = rdev->priv; |
223 | /* disable interrupts and receiver */ |
224 | writel(val: 0x00, addr: dev->rx_base + IRB_RX_EN); |
225 | writel(val: 0x00, addr: dev->rx_base + IRB_RX_INT_EN); |
226 | } |
227 | |
228 | static int st_rc_probe(struct platform_device *pdev) |
229 | { |
230 | int ret = -EINVAL; |
231 | struct rc_dev *rdev; |
232 | struct device *dev = &pdev->dev; |
233 | struct st_rc_device *rc_dev; |
234 | struct device_node *np = pdev->dev.of_node; |
235 | const char *rx_mode; |
236 | |
237 | rc_dev = devm_kzalloc(dev, size: sizeof(struct st_rc_device), GFP_KERNEL); |
238 | |
239 | if (!rc_dev) |
240 | return -ENOMEM; |
241 | |
242 | rdev = rc_allocate_device(RC_DRIVER_IR_RAW); |
243 | |
244 | if (!rdev) |
245 | return -ENOMEM; |
246 | |
247 | if (np && !of_property_read_string(np, propname: "rx-mode" , out_string: &rx_mode)) { |
248 | |
249 | if (!strcmp(rx_mode, "uhf" )) { |
250 | rc_dev->rxuhfmode = true; |
251 | } else if (!strcmp(rx_mode, "infrared" )) { |
252 | rc_dev->rxuhfmode = false; |
253 | } else { |
254 | dev_err(dev, "Unsupported rx mode [%s]\n" , rx_mode); |
255 | goto err; |
256 | } |
257 | |
258 | } else { |
259 | goto err; |
260 | } |
261 | |
262 | rc_dev->sys_clock = devm_clk_get(dev, NULL); |
263 | if (IS_ERR(ptr: rc_dev->sys_clock)) { |
264 | dev_err(dev, "System clock not found\n" ); |
265 | ret = PTR_ERR(ptr: rc_dev->sys_clock); |
266 | goto err; |
267 | } |
268 | |
269 | rc_dev->irq = platform_get_irq(pdev, 0); |
270 | if (rc_dev->irq < 0) { |
271 | ret = rc_dev->irq; |
272 | goto err; |
273 | } |
274 | |
275 | rc_dev->base = devm_platform_ioremap_resource(pdev, index: 0); |
276 | if (IS_ERR(ptr: rc_dev->base)) { |
277 | ret = PTR_ERR(ptr: rc_dev->base); |
278 | goto err; |
279 | } |
280 | |
281 | if (rc_dev->rxuhfmode) |
282 | rc_dev->rx_base = rc_dev->base + 0x40; |
283 | else |
284 | rc_dev->rx_base = rc_dev->base; |
285 | |
286 | rc_dev->rstc = reset_control_get_optional_exclusive(dev, NULL); |
287 | if (IS_ERR(ptr: rc_dev->rstc)) { |
288 | ret = PTR_ERR(ptr: rc_dev->rstc); |
289 | goto err; |
290 | } |
291 | |
292 | rc_dev->dev = dev; |
293 | platform_set_drvdata(pdev, data: rc_dev); |
294 | ret = st_rc_hardware_init(dev: rc_dev); |
295 | if (ret) |
296 | goto err; |
297 | |
298 | rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
299 | /* rx sampling rate is 10Mhz */ |
300 | rdev->rx_resolution = 100; |
301 | rdev->timeout = MAX_SYMB_TIME; |
302 | rdev->priv = rc_dev; |
303 | rdev->open = st_rc_open; |
304 | rdev->close = st_rc_close; |
305 | rdev->driver_name = IR_ST_NAME; |
306 | rdev->map_name = RC_MAP_EMPTY; |
307 | rdev->device_name = "ST Remote Control Receiver" ; |
308 | |
309 | ret = rc_register_device(dev: rdev); |
310 | if (ret < 0) |
311 | goto clkerr; |
312 | |
313 | rc_dev->rdev = rdev; |
314 | if (devm_request_irq(dev, irq: rc_dev->irq, handler: st_rc_rx_interrupt, |
315 | irqflags: 0, IR_ST_NAME, dev_id: rc_dev) < 0) { |
316 | dev_err(dev, "IRQ %d register failed\n" , rc_dev->irq); |
317 | ret = -EINVAL; |
318 | goto rcerr; |
319 | } |
320 | |
321 | /* enable wake via this device */ |
322 | device_init_wakeup(dev, enable: true); |
323 | dev_pm_set_wake_irq(dev, irq: rc_dev->irq); |
324 | |
325 | /* |
326 | * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW |
327 | * lircd expects a long space first before a signal train to sync. |
328 | */ |
329 | st_rc_send_lirc_timeout(rdev); |
330 | |
331 | dev_info(dev, "setup in %s mode\n" , rc_dev->rxuhfmode ? "UHF" : "IR" ); |
332 | |
333 | return ret; |
334 | rcerr: |
335 | rc_unregister_device(dev: rdev); |
336 | rdev = NULL; |
337 | clkerr: |
338 | clk_disable_unprepare(clk: rc_dev->sys_clock); |
339 | err: |
340 | rc_free_device(dev: rdev); |
341 | dev_err(dev, "Unable to register device (%d)\n" , ret); |
342 | return ret; |
343 | } |
344 | |
345 | #ifdef CONFIG_PM_SLEEP |
346 | static int st_rc_suspend(struct device *dev) |
347 | { |
348 | struct st_rc_device *rc_dev = dev_get_drvdata(dev); |
349 | |
350 | if (device_may_wakeup(dev)) { |
351 | if (!enable_irq_wake(irq: rc_dev->irq)) |
352 | rc_dev->irq_wake = 1; |
353 | else |
354 | return -EINVAL; |
355 | } else { |
356 | pinctrl_pm_select_sleep_state(dev); |
357 | writel(val: 0x00, addr: rc_dev->rx_base + IRB_RX_EN); |
358 | writel(val: 0x00, addr: rc_dev->rx_base + IRB_RX_INT_EN); |
359 | clk_disable_unprepare(clk: rc_dev->sys_clock); |
360 | reset_control_assert(rstc: rc_dev->rstc); |
361 | } |
362 | |
363 | return 0; |
364 | } |
365 | |
366 | static int st_rc_resume(struct device *dev) |
367 | { |
368 | int ret; |
369 | struct st_rc_device *rc_dev = dev_get_drvdata(dev); |
370 | struct rc_dev *rdev = rc_dev->rdev; |
371 | |
372 | if (rc_dev->irq_wake) { |
373 | disable_irq_wake(irq: rc_dev->irq); |
374 | rc_dev->irq_wake = 0; |
375 | } else { |
376 | pinctrl_pm_select_default_state(dev); |
377 | ret = st_rc_hardware_init(dev: rc_dev); |
378 | if (ret) |
379 | return ret; |
380 | |
381 | if (rdev->users) { |
382 | writel(IRB_RX_INTS, addr: rc_dev->rx_base + IRB_RX_INT_EN); |
383 | writel(val: 0x01, addr: rc_dev->rx_base + IRB_RX_EN); |
384 | } |
385 | } |
386 | |
387 | return 0; |
388 | } |
389 | |
390 | #endif |
391 | |
392 | static SIMPLE_DEV_PM_OPS(st_rc_pm_ops, st_rc_suspend, st_rc_resume); |
393 | |
394 | #ifdef CONFIG_OF |
395 | static const struct of_device_id st_rc_match[] = { |
396 | { .compatible = "st,comms-irb" , }, |
397 | {}, |
398 | }; |
399 | |
400 | MODULE_DEVICE_TABLE(of, st_rc_match); |
401 | #endif |
402 | |
403 | static struct platform_driver st_rc_driver = { |
404 | .driver = { |
405 | .name = IR_ST_NAME, |
406 | .of_match_table = of_match_ptr(st_rc_match), |
407 | .pm = &st_rc_pm_ops, |
408 | }, |
409 | .probe = st_rc_probe, |
410 | .remove_new = st_rc_remove, |
411 | }; |
412 | |
413 | module_platform_driver(st_rc_driver); |
414 | |
415 | MODULE_DESCRIPTION("RC Transceiver driver for STMicroelectronics platforms" ); |
416 | MODULE_AUTHOR("STMicroelectronics (R&D) Ltd" ); |
417 | MODULE_LICENSE("GPL" ); |
418 | |