1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef BCM63XX_ENET_H_ |
3 | #define BCM63XX_ENET_H_ |
4 | |
5 | #include <linux/types.h> |
6 | #include <linux/mii.h> |
7 | #include <linux/mutex.h> |
8 | #include <linux/phy.h> |
9 | #include <linux/platform_device.h> |
10 | |
11 | #include <bcm63xx_regs.h> |
12 | #include <bcm63xx_io.h> |
13 | #include <bcm63xx_iudma.h> |
14 | |
15 | /* default number of descriptor */ |
16 | #define BCMENET_DEF_RX_DESC 64 |
17 | #define BCMENET_DEF_TX_DESC 32 |
18 | |
19 | /* maximum burst len for dma (4 bytes unit) */ |
20 | #define BCMENET_DMA_MAXBURST 16 |
21 | #define BCMENETSW_DMA_MAXBURST 8 |
22 | |
23 | /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value |
24 | * must be low enough so that a DMA transfer of above burst length can |
25 | * not overflow the fifo */ |
26 | #define BCMENET_TX_FIFO_TRESH 32 |
27 | |
28 | /* |
29 | * hardware maximum rx/tx packet size including FCS, max mtu is |
30 | * actually 2047, but if we set max rx size register to 2047 we won't |
31 | * get overflow information if packet size is 2048 or above |
32 | */ |
33 | #define BCMENET_MAX_MTU 2046 |
34 | |
35 | /* |
36 | * MIB Counters register definitions |
37 | */ |
38 | #define ETH_MIB_TX_GD_OCTETS 0 |
39 | #define ETH_MIB_TX_GD_PKTS 1 |
40 | #define ETH_MIB_TX_ALL_OCTETS 2 |
41 | #define ETH_MIB_TX_ALL_PKTS 3 |
42 | #define ETH_MIB_TX_BRDCAST 4 |
43 | #define ETH_MIB_TX_MULT 5 |
44 | #define ETH_MIB_TX_64 6 |
45 | #define ETH_MIB_TX_65_127 7 |
46 | #define ETH_MIB_TX_128_255 8 |
47 | #define ETH_MIB_TX_256_511 9 |
48 | #define ETH_MIB_TX_512_1023 10 |
49 | #define ETH_MIB_TX_1024_MAX 11 |
50 | #define ETH_MIB_TX_JAB 12 |
51 | #define ETH_MIB_TX_OVR 13 |
52 | #define ETH_MIB_TX_FRAG 14 |
53 | #define ETH_MIB_TX_UNDERRUN 15 |
54 | #define ETH_MIB_TX_COL 16 |
55 | #define ETH_MIB_TX_1_COL 17 |
56 | #define ETH_MIB_TX_M_COL 18 |
57 | #define ETH_MIB_TX_EX_COL 19 |
58 | #define ETH_MIB_TX_LATE 20 |
59 | #define ETH_MIB_TX_DEF 21 |
60 | #define ETH_MIB_TX_CRS 22 |
61 | #define ETH_MIB_TX_PAUSE 23 |
62 | |
63 | #define ETH_MIB_RX_GD_OCTETS 32 |
64 | #define ETH_MIB_RX_GD_PKTS 33 |
65 | #define ETH_MIB_RX_ALL_OCTETS 34 |
66 | #define ETH_MIB_RX_ALL_PKTS 35 |
67 | #define ETH_MIB_RX_BRDCAST 36 |
68 | #define ETH_MIB_RX_MULT 37 |
69 | #define ETH_MIB_RX_64 38 |
70 | #define ETH_MIB_RX_65_127 39 |
71 | #define ETH_MIB_RX_128_255 40 |
72 | #define ETH_MIB_RX_256_511 41 |
73 | #define ETH_MIB_RX_512_1023 42 |
74 | #define ETH_MIB_RX_1024_MAX 43 |
75 | #define ETH_MIB_RX_JAB 44 |
76 | #define ETH_MIB_RX_OVR 45 |
77 | #define ETH_MIB_RX_FRAG 46 |
78 | #define ETH_MIB_RX_DROP 47 |
79 | #define ETH_MIB_RX_CRC_ALIGN 48 |
80 | #define ETH_MIB_RX_UND 49 |
81 | #define ETH_MIB_RX_CRC 50 |
82 | #define ETH_MIB_RX_ALIGN 51 |
83 | #define ETH_MIB_RX_SYM 52 |
84 | #define ETH_MIB_RX_PAUSE 53 |
85 | #define ETH_MIB_RX_CNTRL 54 |
86 | |
87 | |
88 | /* |
89 | * SW MIB Counters register definitions |
90 | */ |
91 | #define ETHSW_MIB_TX_ALL_OCT 0 |
92 | #define ETHSW_MIB_TX_DROP_PKTS 2 |
93 | #define ETHSW_MIB_TX_QOS_PKTS 3 |
94 | #define ETHSW_MIB_TX_BRDCAST 4 |
95 | #define ETHSW_MIB_TX_MULT 5 |
96 | #define ETHSW_MIB_TX_UNI 6 |
97 | #define ETHSW_MIB_TX_COL 7 |
98 | #define ETHSW_MIB_TX_1_COL 8 |
99 | #define ETHSW_MIB_TX_M_COL 9 |
100 | #define ETHSW_MIB_TX_DEF 10 |
101 | #define ETHSW_MIB_TX_LATE 11 |
102 | #define ETHSW_MIB_TX_EX_COL 12 |
103 | #define ETHSW_MIB_TX_PAUSE 14 |
104 | #define ETHSW_MIB_TX_QOS_OCT 15 |
105 | |
106 | #define ETHSW_MIB_RX_ALL_OCT 17 |
107 | #define ETHSW_MIB_RX_UND 19 |
108 | #define ETHSW_MIB_RX_PAUSE 20 |
109 | #define ETHSW_MIB_RX_64 21 |
110 | #define ETHSW_MIB_RX_65_127 22 |
111 | #define ETHSW_MIB_RX_128_255 23 |
112 | #define ETHSW_MIB_RX_256_511 24 |
113 | #define ETHSW_MIB_RX_512_1023 25 |
114 | #define ETHSW_MIB_RX_1024_1522 26 |
115 | #define ETHSW_MIB_RX_OVR 27 |
116 | #define ETHSW_MIB_RX_JAB 28 |
117 | #define ETHSW_MIB_RX_ALIGN 29 |
118 | #define ETHSW_MIB_RX_CRC 30 |
119 | #define ETHSW_MIB_RX_GD_OCT 31 |
120 | #define ETHSW_MIB_RX_DROP 33 |
121 | #define ETHSW_MIB_RX_UNI 34 |
122 | #define ETHSW_MIB_RX_MULT 35 |
123 | #define ETHSW_MIB_RX_BRDCAST 36 |
124 | #define ETHSW_MIB_RX_SA_CHANGE 37 |
125 | #define ETHSW_MIB_RX_FRAG 38 |
126 | #define ETHSW_MIB_RX_OVR_DISC 39 |
127 | #define ETHSW_MIB_RX_SYM 40 |
128 | #define ETHSW_MIB_RX_QOS_PKTS 41 |
129 | #define ETHSW_MIB_RX_QOS_OCT 42 |
130 | #define ETHSW_MIB_RX_1523_2047 44 |
131 | #define ETHSW_MIB_RX_2048_4095 45 |
132 | #define ETHSW_MIB_RX_4096_8191 46 |
133 | #define ETHSW_MIB_RX_8192_9728 47 |
134 | |
135 | |
136 | struct bcm_enet_mib_counters { |
137 | u64 tx_gd_octets; |
138 | u32 tx_gd_pkts; |
139 | u32 tx_all_octets; |
140 | u32 tx_all_pkts; |
141 | u32 tx_unicast; |
142 | u32 tx_brdcast; |
143 | u32 tx_mult; |
144 | u32 tx_64; |
145 | u32 tx_65_127; |
146 | u32 tx_128_255; |
147 | u32 tx_256_511; |
148 | u32 tx_512_1023; |
149 | u32 tx_1024_max; |
150 | u32 tx_1523_2047; |
151 | u32 tx_2048_4095; |
152 | u32 tx_4096_8191; |
153 | u32 tx_8192_9728; |
154 | u32 tx_jab; |
155 | u32 tx_drop; |
156 | u32 tx_ovr; |
157 | u32 tx_frag; |
158 | u32 tx_underrun; |
159 | u32 tx_col; |
160 | u32 tx_1_col; |
161 | u32 tx_m_col; |
162 | u32 tx_ex_col; |
163 | u32 tx_late; |
164 | u32 tx_def; |
165 | u32 tx_crs; |
166 | u32 tx_pause; |
167 | u64 rx_gd_octets; |
168 | u32 rx_gd_pkts; |
169 | u32 rx_all_octets; |
170 | u32 rx_all_pkts; |
171 | u32 rx_brdcast; |
172 | u32 rx_unicast; |
173 | u32 rx_mult; |
174 | u32 rx_64; |
175 | u32 rx_65_127; |
176 | u32 rx_128_255; |
177 | u32 rx_256_511; |
178 | u32 rx_512_1023; |
179 | u32 rx_1024_max; |
180 | u32 rx_jab; |
181 | u32 rx_ovr; |
182 | u32 rx_frag; |
183 | u32 rx_drop; |
184 | u32 rx_crc_align; |
185 | u32 rx_und; |
186 | u32 rx_crc; |
187 | u32 rx_align; |
188 | u32 rx_sym; |
189 | u32 rx_pause; |
190 | u32 rx_cntrl; |
191 | }; |
192 | |
193 | |
194 | struct bcm_enet_priv { |
195 | |
196 | /* base remapped address of device */ |
197 | void __iomem *base; |
198 | |
199 | /* mac irq, rx_dma irq, tx_dma irq */ |
200 | int irq; |
201 | int irq_rx; |
202 | int irq_tx; |
203 | |
204 | /* hw view of rx & tx dma ring */ |
205 | dma_addr_t rx_desc_dma; |
206 | dma_addr_t tx_desc_dma; |
207 | |
208 | /* allocated size (in bytes) for rx & tx dma ring */ |
209 | unsigned int rx_desc_alloc_size; |
210 | unsigned int tx_desc_alloc_size; |
211 | |
212 | |
213 | struct napi_struct napi; |
214 | |
215 | /* dma channel id for rx */ |
216 | int rx_chan; |
217 | |
218 | /* number of dma desc in rx ring */ |
219 | int rx_ring_size; |
220 | |
221 | /* cpu view of rx dma ring */ |
222 | struct bcm_enet_desc *rx_desc_cpu; |
223 | |
224 | /* current number of armed descriptor given to hardware for rx */ |
225 | int rx_desc_count; |
226 | |
227 | /* next rx descriptor to fetch from hardware */ |
228 | int rx_curr_desc; |
229 | |
230 | /* next dirty rx descriptor to refill */ |
231 | int rx_dirty_desc; |
232 | |
233 | /* size of allocated rx buffers */ |
234 | unsigned int rx_buf_size; |
235 | |
236 | /* allocated rx buffer offset */ |
237 | unsigned int rx_buf_offset; |
238 | |
239 | /* size of allocated rx frag */ |
240 | unsigned int rx_frag_size; |
241 | |
242 | /* list of buffer given to hw for rx */ |
243 | void **rx_buf; |
244 | |
245 | /* used when rx skb allocation failed, so we defer rx queue |
246 | * refill */ |
247 | struct timer_list rx_timeout; |
248 | |
249 | /* lock rx_timeout against rx normal operation */ |
250 | spinlock_t rx_lock; |
251 | |
252 | |
253 | /* dma channel id for tx */ |
254 | int tx_chan; |
255 | |
256 | /* number of dma desc in tx ring */ |
257 | int tx_ring_size; |
258 | |
259 | /* maximum dma burst size */ |
260 | int dma_maxburst; |
261 | |
262 | /* cpu view of rx dma ring */ |
263 | struct bcm_enet_desc *tx_desc_cpu; |
264 | |
265 | /* number of available descriptor for tx */ |
266 | int tx_desc_count; |
267 | |
268 | /* next tx descriptor avaiable */ |
269 | int tx_curr_desc; |
270 | |
271 | /* next dirty tx descriptor to reclaim */ |
272 | int tx_dirty_desc; |
273 | |
274 | /* list of skb given to hw for tx */ |
275 | struct sk_buff **tx_skb; |
276 | |
277 | /* lock used by tx reclaim and xmit */ |
278 | spinlock_t tx_lock; |
279 | |
280 | |
281 | /* set if internal phy is ignored and external mii interface |
282 | * is selected */ |
283 | int use_external_mii; |
284 | |
285 | /* set if a phy is connected, phy address must be known, |
286 | * probing is not possible */ |
287 | int has_phy; |
288 | int phy_id; |
289 | |
290 | /* set if connected phy has an associated irq */ |
291 | int has_phy_interrupt; |
292 | int phy_interrupt; |
293 | |
294 | /* used when a phy is connected (phylib used) */ |
295 | struct mii_bus *mii_bus; |
296 | int old_link; |
297 | int old_duplex; |
298 | int old_pause; |
299 | |
300 | /* used when no phy is connected */ |
301 | int force_speed_100; |
302 | int force_duplex_full; |
303 | |
304 | /* pause parameters */ |
305 | int pause_auto; |
306 | int pause_rx; |
307 | int pause_tx; |
308 | |
309 | /* stats */ |
310 | struct bcm_enet_mib_counters mib; |
311 | |
312 | /* after mib interrupt, mib registers update is done in this |
313 | * work queue */ |
314 | struct work_struct mib_update_task; |
315 | |
316 | /* lock mib update between userspace request and workqueue */ |
317 | struct mutex mib_update_lock; |
318 | |
319 | /* mac clock */ |
320 | struct clk *mac_clk; |
321 | |
322 | /* phy clock if internal phy is used */ |
323 | struct clk *phy_clk; |
324 | |
325 | /* network device reference */ |
326 | struct net_device *net_dev; |
327 | |
328 | /* platform device reference */ |
329 | struct platform_device *pdev; |
330 | |
331 | /* maximum hardware transmit/receive size */ |
332 | unsigned int hw_mtu; |
333 | |
334 | bool enet_is_sw; |
335 | |
336 | /* port mapping for switch devices */ |
337 | int num_ports; |
338 | struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; |
339 | int sw_port_link[ENETSW_MAX_PORT]; |
340 | |
341 | /* used to poll switch port state */ |
342 | struct timer_list swphy_poll; |
343 | spinlock_t enetsw_mdio_lock; |
344 | |
345 | /* dma channel enable mask */ |
346 | u32 dma_chan_en_mask; |
347 | |
348 | /* dma channel interrupt mask */ |
349 | u32 dma_chan_int_mask; |
350 | |
351 | /* DMA engine has internal SRAM */ |
352 | bool dma_has_sram; |
353 | |
354 | /* dma channel width */ |
355 | unsigned int dma_chan_width; |
356 | |
357 | /* dma descriptor shift value */ |
358 | unsigned int dma_desc_shift; |
359 | }; |
360 | |
361 | |
362 | #endif /* ! BCM63XX_ENET_H_ */ |
363 | |