1// SPDX-License-Identifier: GPL-2.0-or-later
2/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3/*
4 Copyright (c) 2001, 2002 by D-Link Corporation
5 Written by Edward Peng.<edward_peng@dlink.com.tw>
6 Created 03-May-2001, base on Linux' sundance.c.
7
8*/
9
10#include "dl2k.h"
11#include <linux/dma-mapping.h>
12
13#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
14#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
15#define dw8(reg, val) iowrite8(val, ioaddr + (reg))
16#define dr32(reg) ioread32(ioaddr + (reg))
17#define dr16(reg) ioread16(ioaddr + (reg))
18#define dr8(reg) ioread8(ioaddr + (reg))
19
20#define MAX_UNITS 8
21static int mtu[MAX_UNITS];
22static int vlan[MAX_UNITS];
23static int jumbo[MAX_UNITS];
24static char *media[MAX_UNITS];
25static int tx_flow=-1;
26static int rx_flow=-1;
27static int copy_thresh;
28static int rx_coalesce=10; /* Rx frame count each interrupt */
29static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
30static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
31
32
33MODULE_AUTHOR ("Edward Peng");
34MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
35MODULE_LICENSE("GPL");
36module_param_array(mtu, int, NULL, 0);
37module_param_array(media, charp, NULL, 0);
38module_param_array(vlan, int, NULL, 0);
39module_param_array(jumbo, int, NULL, 0);
40module_param(tx_flow, int, 0);
41module_param(rx_flow, int, 0);
42module_param(copy_thresh, int, 0);
43module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
44module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
45module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
46
47
48/* Enable the default interrupts */
49#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
50 UpdateStats | LinkEvent)
51
52static void dl2k_enable_int(struct netdev_private *np)
53{
54 void __iomem *ioaddr = np->ioaddr;
55
56 dw16(IntEnable, DEFAULT_INTR);
57}
58
59static const int max_intrloop = 50;
60static const int multicast_filter_limit = 0x40;
61
62static int rio_open (struct net_device *dev);
63static void rio_timer (struct timer_list *t);
64static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
65static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
66static irqreturn_t rio_interrupt (int irq, void *dev_instance);
67static void rio_free_tx (struct net_device *dev, int irq);
68static void tx_error (struct net_device *dev, int tx_status);
69static int receive_packet (struct net_device *dev);
70static void rio_error (struct net_device *dev, int int_status);
71static void set_multicast (struct net_device *dev);
72static struct net_device_stats *get_stats (struct net_device *dev);
73static int clear_stats (struct net_device *dev);
74static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
75static int rio_close (struct net_device *dev);
76static int find_miiphy (struct net_device *dev);
77static int parse_eeprom (struct net_device *dev);
78static int read_eeprom (struct netdev_private *, int eep_addr);
79static int mii_wait_link (struct net_device *dev, int wait);
80static int mii_set_media (struct net_device *dev);
81static int mii_get_media (struct net_device *dev);
82static int mii_set_media_pcs (struct net_device *dev);
83static int mii_get_media_pcs (struct net_device *dev);
84static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
85static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
86 u16 data);
87
88static const struct ethtool_ops ethtool_ops;
89
90static const struct net_device_ops netdev_ops = {
91 .ndo_open = rio_open,
92 .ndo_start_xmit = start_xmit,
93 .ndo_stop = rio_close,
94 .ndo_get_stats = get_stats,
95 .ndo_validate_addr = eth_validate_addr,
96 .ndo_set_mac_address = eth_mac_addr,
97 .ndo_set_rx_mode = set_multicast,
98 .ndo_eth_ioctl = rio_ioctl,
99 .ndo_tx_timeout = rio_tx_timeout,
100};
101
102static int
103rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
104{
105 struct net_device *dev;
106 struct netdev_private *np;
107 static int card_idx;
108 int chip_idx = ent->driver_data;
109 int err, irq;
110 void __iomem *ioaddr;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 err = pci_enable_device (pdev);
115 if (err)
116 return err;
117
118 irq = pdev->irq;
119 err = pci_request_regions (pdev, "dl2k");
120 if (err)
121 goto err_out_disable;
122
123 pci_set_master (pdev);
124
125 err = -ENOMEM;
126
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev)
129 goto err_out_res;
130 SET_NETDEV_DEV(dev, &pdev->dev);
131
132 np = netdev_priv(dev);
133
134 /* IO registers range. */
135 ioaddr = pci_iomap(pdev, 0, 0);
136 if (!ioaddr)
137 goto err_out_dev;
138 np->eeprom_addr = ioaddr;
139
140#ifdef MEM_MAPPING
141 /* MM registers range. */
142 ioaddr = pci_iomap(pdev, 1, 0);
143 if (!ioaddr)
144 goto err_out_iounmap;
145#endif
146 np->ioaddr = ioaddr;
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149 spin_lock_init (&np->tx_lock);
150 spin_lock_init (&np->rx_lock);
151
152 /* Parse manual configuration */
153 np->an_enable = 1;
154 np->tx_coalesce = 1;
155 if (card_idx < MAX_UNITS) {
156 if (media[card_idx] != NULL) {
157 np->an_enable = 0;
158 if (strcmp (media[card_idx], "auto") == 0 ||
159 strcmp (media[card_idx], "autosense") == 0 ||
160 strcmp (media[card_idx], "0") == 0 ) {
161 np->an_enable = 2;
162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
163 strcmp (media[card_idx], "4") == 0) {
164 np->speed = 100;
165 np->full_duplex = 1;
166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
167 strcmp (media[card_idx], "3") == 0) {
168 np->speed = 100;
169 np->full_duplex = 0;
170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
171 strcmp (media[card_idx], "2") == 0) {
172 np->speed = 10;
173 np->full_duplex = 1;
174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
175 strcmp (media[card_idx], "1") == 0) {
176 np->speed = 10;
177 np->full_duplex = 0;
178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
179 strcmp (media[card_idx], "6") == 0) {
180 np->speed=1000;
181 np->full_duplex=1;
182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
183 strcmp (media[card_idx], "5") == 0) {
184 np->speed = 1000;
185 np->full_duplex = 0;
186 } else {
187 np->an_enable = 1;
188 }
189 }
190 if (jumbo[card_idx] != 0) {
191 np->jumbo = 1;
192 dev->mtu = MAX_JUMBO;
193 } else {
194 np->jumbo = 0;
195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
196 dev->mtu = mtu[card_idx];
197 }
198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
199 vlan[card_idx] : 0;
200 if (rx_coalesce > 0 && rx_timeout > 0) {
201 np->rx_coalesce = rx_coalesce;
202 np->rx_timeout = rx_timeout;
203 np->coalesce = 1;
204 }
205 np->tx_flow = (tx_flow == 0) ? 0 : 1;
206 np->rx_flow = (rx_flow == 0) ? 0 : 1;
207
208 if (tx_coalesce < 1)
209 tx_coalesce = 1;
210 else if (tx_coalesce > TX_RING_SIZE-1)
211 tx_coalesce = TX_RING_SIZE - 1;
212 }
213 dev->netdev_ops = &netdev_ops;
214 dev->watchdog_timeo = TX_TIMEOUT;
215 dev->ethtool_ops = &ethtool_ops;
216#if 0
217 dev->features = NETIF_F_IP_CSUM;
218#endif
219 /* MTU range: 68 - 1536 or 8000 */
220 dev->min_mtu = ETH_MIN_MTU;
221 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
222
223 pci_set_drvdata (pdev, dev);
224
225 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
226 GFP_KERNEL);
227 if (!ring_space)
228 goto err_out_iounmap;
229 np->tx_ring = ring_space;
230 np->tx_ring_dma = ring_dma;
231
232 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
233 GFP_KERNEL);
234 if (!ring_space)
235 goto err_out_unmap_tx;
236 np->rx_ring = ring_space;
237 np->rx_ring_dma = ring_dma;
238
239 /* Parse eeprom data */
240 parse_eeprom (dev);
241
242 /* Find PHY address */
243 err = find_miiphy (dev);
244 if (err)
245 goto err_out_unmap_rx;
246
247 /* Fiber device? */
248 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
249 np->link_status = 0;
250 /* Set media and reset PHY */
251 if (np->phy_media) {
252 /* default Auto-Negotiation for fiber deivices */
253 if (np->an_enable == 2) {
254 np->an_enable = 1;
255 }
256 } else {
257 /* Auto-Negotiation is mandatory for 1000BASE-T,
258 IEEE 802.3ab Annex 28D page 14 */
259 if (np->speed == 1000)
260 np->an_enable = 1;
261 }
262
263 err = register_netdev (dev);
264 if (err)
265 goto err_out_unmap_rx;
266
267 card_idx++;
268
269 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
270 dev->name, np->name, dev->dev_addr, irq);
271 if (tx_coalesce > 1)
272 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
273 tx_coalesce);
274 if (np->coalesce)
275 printk(KERN_INFO
276 "rx_coalesce:\t%d packets\n"
277 "rx_timeout: \t%d ns\n",
278 np->rx_coalesce, np->rx_timeout*640);
279 if (np->vlan)
280 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
281 return 0;
282
283err_out_unmap_rx:
284 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
285 np->rx_ring_dma);
286err_out_unmap_tx:
287 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
288 np->tx_ring_dma);
289err_out_iounmap:
290#ifdef MEM_MAPPING
291 pci_iounmap(pdev, np->ioaddr);
292#endif
293 pci_iounmap(pdev, np->eeprom_addr);
294err_out_dev:
295 free_netdev (dev);
296err_out_res:
297 pci_release_regions (pdev);
298err_out_disable:
299 pci_disable_device (pdev);
300 return err;
301}
302
303static int
304find_miiphy (struct net_device *dev)
305{
306 struct netdev_private *np = netdev_priv(dev);
307 int i, phy_found = 0;
308
309 np->phy_addr = 1;
310
311 for (i = 31; i >= 0; i--) {
312 int mii_status = mii_read (dev, i, 1);
313 if (mii_status != 0xffff && mii_status != 0x0000) {
314 np->phy_addr = i;
315 phy_found++;
316 }
317 }
318 if (!phy_found) {
319 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
320 return -ENODEV;
321 }
322 return 0;
323}
324
325static int
326parse_eeprom (struct net_device *dev)
327{
328 struct netdev_private *np = netdev_priv(dev);
329 void __iomem *ioaddr = np->ioaddr;
330 int i, j;
331 u8 sromdata[256];
332 u8 *psib;
333 u32 crc;
334 PSROM_t psrom = (PSROM_t) sromdata;
335
336 int cid, next;
337
338 for (i = 0; i < 128; i++)
339 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
340
341 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
342 /* Check CRC */
343 crc = ~ether_crc_le (256 - 4, sromdata);
344 if (psrom->crc != cpu_to_le32(crc)) {
345 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
346 dev->name);
347 return -1;
348 }
349 }
350
351 /* Set MAC address */
352 eth_hw_addr_set(dev, psrom->mac_addr);
353
354 if (np->chip_id == CHIP_IP1000A) {
355 np->led_mode = psrom->led_mode;
356 return 0;
357 }
358
359 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
360 return 0;
361 }
362
363 /* Parse Software Information Block */
364 i = 0x30;
365 psib = (u8 *) sromdata;
366 do {
367 cid = psib[i++];
368 next = psib[i++];
369 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
370 printk (KERN_ERR "Cell data error\n");
371 return -1;
372 }
373 switch (cid) {
374 case 0: /* Format version */
375 break;
376 case 1: /* End of cell */
377 return 0;
378 case 2: /* Duplex Polarity */
379 np->duplex_polarity = psib[i];
380 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
381 break;
382 case 3: /* Wake Polarity */
383 np->wake_polarity = psib[i];
384 break;
385 case 9: /* Adapter description */
386 j = (next - i > 255) ? 255 : next - i;
387 memcpy (np->name, &(psib[i]), j);
388 break;
389 case 4:
390 case 5:
391 case 6:
392 case 7:
393 case 8: /* Reversed */
394 break;
395 default: /* Unknown cell */
396 return -1;
397 }
398 i = next;
399 } while (1);
400
401 return 0;
402}
403
404static void rio_set_led_mode(struct net_device *dev)
405{
406 struct netdev_private *np = netdev_priv(dev);
407 void __iomem *ioaddr = np->ioaddr;
408 u32 mode;
409
410 if (np->chip_id != CHIP_IP1000A)
411 return;
412
413 mode = dr32(ASICCtrl);
414 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
415
416 if (np->led_mode & 0x01)
417 mode |= IPG_AC_LED_MODE;
418 if (np->led_mode & 0x02)
419 mode |= IPG_AC_LED_MODE_BIT_1;
420 if (np->led_mode & 0x08)
421 mode |= IPG_AC_LED_SPEED;
422
423 dw32(ASICCtrl, mode);
424}
425
426static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
427{
428 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
429}
430
431static void free_list(struct net_device *dev)
432{
433 struct netdev_private *np = netdev_priv(dev);
434 struct sk_buff *skb;
435 int i;
436
437 /* Free all the skbuffs in the queue. */
438 for (i = 0; i < RX_RING_SIZE; i++) {
439 skb = np->rx_skbuff[i];
440 if (skb) {
441 dma_unmap_single(&np->pdev->dev,
442 desc_to_dma(&np->rx_ring[i]),
443 skb->len, DMA_FROM_DEVICE);
444 dev_kfree_skb(skb);
445 np->rx_skbuff[i] = NULL;
446 }
447 np->rx_ring[i].status = 0;
448 np->rx_ring[i].fraginfo = 0;
449 }
450 for (i = 0; i < TX_RING_SIZE; i++) {
451 skb = np->tx_skbuff[i];
452 if (skb) {
453 dma_unmap_single(&np->pdev->dev,
454 desc_to_dma(&np->tx_ring[i]),
455 skb->len, DMA_TO_DEVICE);
456 dev_kfree_skb(skb);
457 np->tx_skbuff[i] = NULL;
458 }
459 }
460}
461
462static void rio_reset_ring(struct netdev_private *np)
463{
464 int i;
465
466 np->cur_rx = 0;
467 np->cur_tx = 0;
468 np->old_rx = 0;
469 np->old_tx = 0;
470
471 for (i = 0; i < TX_RING_SIZE; i++)
472 np->tx_ring[i].status = cpu_to_le64(TFDDone);
473
474 for (i = 0; i < RX_RING_SIZE; i++)
475 np->rx_ring[i].status = 0;
476}
477
478 /* allocate and initialize Tx and Rx descriptors */
479static int alloc_list(struct net_device *dev)
480{
481 struct netdev_private *np = netdev_priv(dev);
482 int i;
483
484 rio_reset_ring(np);
485 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
486
487 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
488 for (i = 0; i < TX_RING_SIZE; i++) {
489 np->tx_skbuff[i] = NULL;
490 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
491 ((i + 1) % TX_RING_SIZE) *
492 sizeof(struct netdev_desc));
493 }
494
495 /* Initialize Rx descriptors & allocate buffers */
496 for (i = 0; i < RX_RING_SIZE; i++) {
497 /* Allocated fixed size of skbuff */
498 struct sk_buff *skb;
499
500 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
501 np->rx_skbuff[i] = skb;
502 if (!skb) {
503 free_list(dev);
504 return -ENOMEM;
505 }
506
507 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
508 ((i + 1) % RX_RING_SIZE) *
509 sizeof(struct netdev_desc));
510 /* Rubicon now supports 40 bits of addressing space. */
511 np->rx_ring[i].fraginfo =
512 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
513 np->rx_buf_sz, DMA_FROM_DEVICE));
514 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
515 }
516
517 return 0;
518}
519
520static void rio_hw_init(struct net_device *dev)
521{
522 struct netdev_private *np = netdev_priv(dev);
523 void __iomem *ioaddr = np->ioaddr;
524 int i;
525 u16 macctrl;
526
527 /* Reset all logic functions */
528 dw16(ASICCtrl + 2,
529 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
530 mdelay(10);
531
532 rio_set_led_mode(dev);
533
534 /* DebugCtrl bit 4, 5, 9 must set */
535 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
536
537 if (np->chip_id == CHIP_IP1000A &&
538 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
539 /* PHY magic taken from ipg driver, undocumented registers */
540 mii_write(dev, np->phy_addr, 31, 0x0001);
541 mii_write(dev, np->phy_addr, 27, 0x01e0);
542 mii_write(dev, np->phy_addr, 31, 0x0002);
543 mii_write(dev, np->phy_addr, 27, 0xeb8e);
544 mii_write(dev, np->phy_addr, 31, 0x0000);
545 mii_write(dev, np->phy_addr, 30, 0x005e);
546 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
547 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
548 }
549
550 if (np->phy_media)
551 mii_set_media_pcs(dev);
552 else
553 mii_set_media(dev);
554
555 /* Jumbo frame */
556 if (np->jumbo != 0)
557 dw16(MaxFrameSize, MAX_JUMBO+14);
558
559 /* Set RFDListPtr */
560 dw32(RFDListPtr0, np->rx_ring_dma);
561 dw32(RFDListPtr1, 0);
562
563 /* Set station address */
564 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
565 * too. However, it doesn't work on IP1000A so we use 16-bit access.
566 */
567 for (i = 0; i < 3; i++)
568 dw16(StationAddr0 + 2 * i,
569 cpu_to_le16(((const u16 *)dev->dev_addr)[i]));
570
571 set_multicast (dev);
572 if (np->coalesce) {
573 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
574 }
575 /* Set RIO to poll every N*320nsec. */
576 dw8(RxDMAPollPeriod, 0x20);
577 dw8(TxDMAPollPeriod, 0xff);
578 dw8(RxDMABurstThresh, 0x30);
579 dw8(RxDMAUrgentThresh, 0x30);
580 dw32(RmonStatMask, 0x0007ffff);
581 /* clear statistics */
582 clear_stats (dev);
583
584 /* VLAN supported */
585 if (np->vlan) {
586 /* priority field in RxDMAIntCtrl */
587 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
588 /* VLANId */
589 dw16(VLANId, np->vlan);
590 /* Length/Type should be 0x8100 */
591 dw32(VLANTag, 0x8100 << 16 | np->vlan);
592 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
593 VLAN information tagged by TFC' VID, CFI fields. */
594 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
595 }
596
597 /* Start Tx/Rx */
598 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
599
600 macctrl = 0;
601 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
602 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
603 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
604 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
605 dw16(MACCtrl, macctrl);
606}
607
608static void rio_hw_stop(struct net_device *dev)
609{
610 struct netdev_private *np = netdev_priv(dev);
611 void __iomem *ioaddr = np->ioaddr;
612
613 /* Disable interrupts */
614 dw16(IntEnable, 0);
615
616 /* Stop Tx and Rx logics */
617 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
618}
619
620static int rio_open(struct net_device *dev)
621{
622 struct netdev_private *np = netdev_priv(dev);
623 const int irq = np->pdev->irq;
624 int i;
625
626 i = alloc_list(dev);
627 if (i)
628 return i;
629
630 rio_hw_init(dev);
631
632 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
633 if (i) {
634 rio_hw_stop(dev);
635 free_list(dev);
636 return i;
637 }
638
639 timer_setup(&np->timer, rio_timer, 0);
640 np->timer.expires = jiffies + 1 * HZ;
641 add_timer(&np->timer);
642
643 netif_start_queue (dev);
644
645 dl2k_enable_int(np);
646 return 0;
647}
648
649static void
650rio_timer (struct timer_list *t)
651{
652 struct netdev_private *np = from_timer(np, t, timer);
653 struct net_device *dev = pci_get_drvdata(np->pdev);
654 unsigned int entry;
655 int next_tick = 1*HZ;
656 unsigned long flags;
657
658 spin_lock_irqsave(&np->rx_lock, flags);
659 /* Recover rx ring exhausted error */
660 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
661 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
662 /* Re-allocate skbuffs to fill the descriptor ring */
663 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
664 struct sk_buff *skb;
665 entry = np->old_rx % RX_RING_SIZE;
666 /* Dropped packets don't need to re-allocate */
667 if (np->rx_skbuff[entry] == NULL) {
668 skb = netdev_alloc_skb_ip_align(dev,
669 np->rx_buf_sz);
670 if (skb == NULL) {
671 np->rx_ring[entry].fraginfo = 0;
672 printk (KERN_INFO
673 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
674 dev->name, entry);
675 break;
676 }
677 np->rx_skbuff[entry] = skb;
678 np->rx_ring[entry].fraginfo =
679 cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
680 np->rx_buf_sz, DMA_FROM_DEVICE));
681 }
682 np->rx_ring[entry].fraginfo |=
683 cpu_to_le64((u64)np->rx_buf_sz << 48);
684 np->rx_ring[entry].status = 0;
685 } /* end for */
686 } /* end if */
687 spin_unlock_irqrestore (&np->rx_lock, flags);
688 np->timer.expires = jiffies + next_tick;
689 add_timer(&np->timer);
690}
691
692static void
693rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
694{
695 struct netdev_private *np = netdev_priv(dev);
696 void __iomem *ioaddr = np->ioaddr;
697
698 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
699 dev->name, dr32(TxStatus));
700 rio_free_tx(dev, 0);
701 dev->if_port = 0;
702 netif_trans_update(dev); /* prevent tx timeout */
703}
704
705static netdev_tx_t
706start_xmit (struct sk_buff *skb, struct net_device *dev)
707{
708 struct netdev_private *np = netdev_priv(dev);
709 void __iomem *ioaddr = np->ioaddr;
710 struct netdev_desc *txdesc;
711 unsigned entry;
712 u64 tfc_vlan_tag = 0;
713
714 if (np->link_status == 0) { /* Link Down */
715 dev_kfree_skb(skb);
716 return NETDEV_TX_OK;
717 }
718 entry = np->cur_tx % TX_RING_SIZE;
719 np->tx_skbuff[entry] = skb;
720 txdesc = &np->tx_ring[entry];
721
722#if 0
723 if (skb->ip_summed == CHECKSUM_PARTIAL) {
724 txdesc->status |=
725 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
726 IPChecksumEnable);
727 }
728#endif
729 if (np->vlan) {
730 tfc_vlan_tag = VLANTagInsert |
731 ((u64)np->vlan << 32) |
732 ((u64)skb->priority << 45);
733 }
734 txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
735 skb->len, DMA_TO_DEVICE));
736 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
737
738 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
739 * Work around: Always use 1 descriptor in 10Mbps mode */
740 if (entry % np->tx_coalesce == 0 || np->speed == 10)
741 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
742 WordAlignDisable |
743 TxDMAIndicate |
744 (1 << FragCountShift));
745 else
746 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
747 WordAlignDisable |
748 (1 << FragCountShift));
749
750 /* TxDMAPollNow */
751 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
752 /* Schedule ISR */
753 dw32(CountDown, 10000);
754 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
755 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
756 < TX_QUEUE_LEN - 1 && np->speed != 10) {
757 /* do nothing */
758 } else if (!netif_queue_stopped(dev)) {
759 netif_stop_queue (dev);
760 }
761
762 /* The first TFDListPtr */
763 if (!dr32(TFDListPtr0)) {
764 dw32(TFDListPtr0, np->tx_ring_dma +
765 entry * sizeof (struct netdev_desc));
766 dw32(TFDListPtr1, 0);
767 }
768
769 return NETDEV_TX_OK;
770}
771
772static irqreturn_t
773rio_interrupt (int irq, void *dev_instance)
774{
775 struct net_device *dev = dev_instance;
776 struct netdev_private *np = netdev_priv(dev);
777 void __iomem *ioaddr = np->ioaddr;
778 unsigned int_status;
779 int cnt = max_intrloop;
780 int handled = 0;
781
782 while (1) {
783 int_status = dr16(IntStatus);
784 dw16(IntStatus, int_status);
785 int_status &= DEFAULT_INTR;
786 if (int_status == 0 || --cnt < 0)
787 break;
788 handled = 1;
789 /* Processing received packets */
790 if (int_status & RxDMAComplete)
791 receive_packet (dev);
792 /* TxDMAComplete interrupt */
793 if ((int_status & (TxDMAComplete|IntRequested))) {
794 int tx_status;
795 tx_status = dr32(TxStatus);
796 if (tx_status & 0x01)
797 tx_error (dev, tx_status);
798 /* Free used tx skbuffs */
799 rio_free_tx (dev, 1);
800 }
801
802 /* Handle uncommon events */
803 if (int_status &
804 (HostError | LinkEvent | UpdateStats))
805 rio_error (dev, int_status);
806 }
807 if (np->cur_tx != np->old_tx)
808 dw32(CountDown, 100);
809 return IRQ_RETVAL(handled);
810}
811
812static void
813rio_free_tx (struct net_device *dev, int irq)
814{
815 struct netdev_private *np = netdev_priv(dev);
816 int entry = np->old_tx % TX_RING_SIZE;
817 int tx_use = 0;
818 unsigned long flag = 0;
819
820 if (irq)
821 spin_lock(&np->tx_lock);
822 else
823 spin_lock_irqsave(&np->tx_lock, flag);
824
825 /* Free used tx skbuffs */
826 while (entry != np->cur_tx) {
827 struct sk_buff *skb;
828
829 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
830 break;
831 skb = np->tx_skbuff[entry];
832 dma_unmap_single(&np->pdev->dev,
833 desc_to_dma(&np->tx_ring[entry]), skb->len,
834 DMA_TO_DEVICE);
835 if (irq)
836 dev_consume_skb_irq(skb);
837 else
838 dev_kfree_skb(skb);
839
840 np->tx_skbuff[entry] = NULL;
841 entry = (entry + 1) % TX_RING_SIZE;
842 tx_use++;
843 }
844 if (irq)
845 spin_unlock(&np->tx_lock);
846 else
847 spin_unlock_irqrestore(&np->tx_lock, flag);
848 np->old_tx = entry;
849
850 /* If the ring is no longer full, clear tx_full and
851 call netif_wake_queue() */
852
853 if (netif_queue_stopped(dev) &&
854 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
855 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
856 netif_wake_queue (dev);
857 }
858}
859
860static void
861tx_error (struct net_device *dev, int tx_status)
862{
863 struct netdev_private *np = netdev_priv(dev);
864 void __iomem *ioaddr = np->ioaddr;
865 int frame_id;
866 int i;
867
868 frame_id = (tx_status & 0xffff0000);
869 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
870 dev->name, tx_status, frame_id);
871 dev->stats.tx_errors++;
872 /* Ttransmit Underrun */
873 if (tx_status & 0x10) {
874 dev->stats.tx_fifo_errors++;
875 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
876 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
877 dw16(ASICCtrl + 2,
878 TxReset | DMAReset | FIFOReset | NetworkReset);
879 /* Wait for ResetBusy bit clear */
880 for (i = 50; i > 0; i--) {
881 if (!(dr16(ASICCtrl + 2) & ResetBusy))
882 break;
883 mdelay (1);
884 }
885 rio_set_led_mode(dev);
886 rio_free_tx (dev, 1);
887 /* Reset TFDListPtr */
888 dw32(TFDListPtr0, np->tx_ring_dma +
889 np->old_tx * sizeof (struct netdev_desc));
890 dw32(TFDListPtr1, 0);
891
892 /* Let TxStartThresh stay default value */
893 }
894 /* Late Collision */
895 if (tx_status & 0x04) {
896 dev->stats.tx_fifo_errors++;
897 /* TxReset and clear FIFO */
898 dw16(ASICCtrl + 2, TxReset | FIFOReset);
899 /* Wait reset done */
900 for (i = 50; i > 0; i--) {
901 if (!(dr16(ASICCtrl + 2) & ResetBusy))
902 break;
903 mdelay (1);
904 }
905 rio_set_led_mode(dev);
906 /* Let TxStartThresh stay default value */
907 }
908 /* Maximum Collisions */
909 if (tx_status & 0x08)
910 dev->stats.collisions++;
911 /* Restart the Tx */
912 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
913}
914
915static int
916receive_packet (struct net_device *dev)
917{
918 struct netdev_private *np = netdev_priv(dev);
919 int entry = np->cur_rx % RX_RING_SIZE;
920 int cnt = 30;
921
922 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
923 while (1) {
924 struct netdev_desc *desc = &np->rx_ring[entry];
925 int pkt_len;
926 u64 frame_status;
927
928 if (!(desc->status & cpu_to_le64(RFDDone)) ||
929 !(desc->status & cpu_to_le64(FrameStart)) ||
930 !(desc->status & cpu_to_le64(FrameEnd)))
931 break;
932
933 /* Chip omits the CRC. */
934 frame_status = le64_to_cpu(desc->status);
935 pkt_len = frame_status & 0xffff;
936 if (--cnt < 0)
937 break;
938 /* Update rx error statistics, drop packet. */
939 if (frame_status & RFS_Errors) {
940 dev->stats.rx_errors++;
941 if (frame_status & (RxRuntFrame | RxLengthError))
942 dev->stats.rx_length_errors++;
943 if (frame_status & RxFCSError)
944 dev->stats.rx_crc_errors++;
945 if (frame_status & RxAlignmentError && np->speed != 1000)
946 dev->stats.rx_frame_errors++;
947 if (frame_status & RxFIFOOverrun)
948 dev->stats.rx_fifo_errors++;
949 } else {
950 struct sk_buff *skb;
951
952 /* Small skbuffs for short packets */
953 if (pkt_len > copy_thresh) {
954 dma_unmap_single(&np->pdev->dev,
955 desc_to_dma(desc),
956 np->rx_buf_sz,
957 DMA_FROM_DEVICE);
958 skb_put (skb = np->rx_skbuff[entry], pkt_len);
959 np->rx_skbuff[entry] = NULL;
960 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
961 dma_sync_single_for_cpu(&np->pdev->dev,
962 desc_to_dma(desc),
963 np->rx_buf_sz,
964 DMA_FROM_DEVICE);
965 skb_copy_to_linear_data (skb,
966 np->rx_skbuff[entry]->data,
967 pkt_len);
968 skb_put (skb, pkt_len);
969 dma_sync_single_for_device(&np->pdev->dev,
970 desc_to_dma(desc),
971 np->rx_buf_sz,
972 DMA_FROM_DEVICE);
973 }
974 skb->protocol = eth_type_trans (skb, dev);
975#if 0
976 /* Checksum done by hw, but csum value unavailable. */
977 if (np->pdev->pci_rev_id >= 0x0c &&
978 !(frame_status & (TCPError | UDPError | IPError))) {
979 skb->ip_summed = CHECKSUM_UNNECESSARY;
980 }
981#endif
982 netif_rx (skb);
983 }
984 entry = (entry + 1) % RX_RING_SIZE;
985 }
986 spin_lock(&np->rx_lock);
987 np->cur_rx = entry;
988 /* Re-allocate skbuffs to fill the descriptor ring */
989 entry = np->old_rx;
990 while (entry != np->cur_rx) {
991 struct sk_buff *skb;
992 /* Dropped packets don't need to re-allocate */
993 if (np->rx_skbuff[entry] == NULL) {
994 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
995 if (skb == NULL) {
996 np->rx_ring[entry].fraginfo = 0;
997 printk (KERN_INFO
998 "%s: receive_packet: "
999 "Unable to re-allocate Rx skbuff.#%d\n",
1000 dev->name, entry);
1001 break;
1002 }
1003 np->rx_skbuff[entry] = skb;
1004 np->rx_ring[entry].fraginfo =
1005 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
1006 np->rx_buf_sz, DMA_FROM_DEVICE));
1007 }
1008 np->rx_ring[entry].fraginfo |=
1009 cpu_to_le64((u64)np->rx_buf_sz << 48);
1010 np->rx_ring[entry].status = 0;
1011 entry = (entry + 1) % RX_RING_SIZE;
1012 }
1013 np->old_rx = entry;
1014 spin_unlock(&np->rx_lock);
1015 return 0;
1016}
1017
1018static void
1019rio_error (struct net_device *dev, int int_status)
1020{
1021 struct netdev_private *np = netdev_priv(dev);
1022 void __iomem *ioaddr = np->ioaddr;
1023 u16 macctrl;
1024
1025 /* Link change event */
1026 if (int_status & LinkEvent) {
1027 if (mii_wait_link (dev, 10) == 0) {
1028 printk (KERN_INFO "%s: Link up\n", dev->name);
1029 if (np->phy_media)
1030 mii_get_media_pcs (dev);
1031 else
1032 mii_get_media (dev);
1033 if (np->speed == 1000)
1034 np->tx_coalesce = tx_coalesce;
1035 else
1036 np->tx_coalesce = 1;
1037 macctrl = 0;
1038 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1039 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1040 macctrl |= (np->tx_flow) ?
1041 TxFlowControlEnable : 0;
1042 macctrl |= (np->rx_flow) ?
1043 RxFlowControlEnable : 0;
1044 dw16(MACCtrl, macctrl);
1045 np->link_status = 1;
1046 netif_carrier_on(dev);
1047 } else {
1048 printk (KERN_INFO "%s: Link off\n", dev->name);
1049 np->link_status = 0;
1050 netif_carrier_off(dev);
1051 }
1052 }
1053
1054 /* UpdateStats statistics registers */
1055 if (int_status & UpdateStats) {
1056 get_stats (dev);
1057 }
1058
1059 /* PCI Error, a catastronphic error related to the bus interface
1060 occurs, set GlobalReset and HostReset to reset. */
1061 if (int_status & HostError) {
1062 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1063 dev->name, int_status);
1064 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1065 mdelay (500);
1066 rio_set_led_mode(dev);
1067 }
1068}
1069
1070static struct net_device_stats *
1071get_stats (struct net_device *dev)
1072{
1073 struct netdev_private *np = netdev_priv(dev);
1074 void __iomem *ioaddr = np->ioaddr;
1075#ifdef MEM_MAPPING
1076 int i;
1077#endif
1078 unsigned int stat_reg;
1079
1080 /* All statistics registers need to be acknowledged,
1081 else statistic overflow could cause problems */
1082
1083 dev->stats.rx_packets += dr32(FramesRcvOk);
1084 dev->stats.tx_packets += dr32(FramesXmtOk);
1085 dev->stats.rx_bytes += dr32(OctetRcvOk);
1086 dev->stats.tx_bytes += dr32(OctetXmtOk);
1087
1088 dev->stats.multicast = dr32(McstFramesRcvdOk);
1089 dev->stats.collisions += dr32(SingleColFrames)
1090 + dr32(MultiColFrames);
1091
1092 /* detailed tx errors */
1093 stat_reg = dr16(FramesAbortXSColls);
1094 dev->stats.tx_aborted_errors += stat_reg;
1095 dev->stats.tx_errors += stat_reg;
1096
1097 stat_reg = dr16(CarrierSenseErrors);
1098 dev->stats.tx_carrier_errors += stat_reg;
1099 dev->stats.tx_errors += stat_reg;
1100
1101 /* Clear all other statistic register. */
1102 dr32(McstOctetXmtOk);
1103 dr16(BcstFramesXmtdOk);
1104 dr32(McstFramesXmtdOk);
1105 dr16(BcstFramesRcvdOk);
1106 dr16(MacControlFramesRcvd);
1107 dr16(FrameTooLongErrors);
1108 dr16(InRangeLengthErrors);
1109 dr16(FramesCheckSeqErrors);
1110 dr16(FramesLostRxErrors);
1111 dr32(McstOctetXmtOk);
1112 dr32(BcstOctetXmtOk);
1113 dr32(McstFramesXmtdOk);
1114 dr32(FramesWDeferredXmt);
1115 dr32(LateCollisions);
1116 dr16(BcstFramesXmtdOk);
1117 dr16(MacControlFramesXmtd);
1118 dr16(FramesWEXDeferal);
1119
1120#ifdef MEM_MAPPING
1121 for (i = 0x100; i <= 0x150; i += 4)
1122 dr32(i);
1123#endif
1124 dr16(TxJumboFrames);
1125 dr16(RxJumboFrames);
1126 dr16(TCPCheckSumErrors);
1127 dr16(UDPCheckSumErrors);
1128 dr16(IPCheckSumErrors);
1129 return &dev->stats;
1130}
1131
1132static int
1133clear_stats (struct net_device *dev)
1134{
1135 struct netdev_private *np = netdev_priv(dev);
1136 void __iomem *ioaddr = np->ioaddr;
1137#ifdef MEM_MAPPING
1138 int i;
1139#endif
1140
1141 /* All statistics registers need to be acknowledged,
1142 else statistic overflow could cause problems */
1143 dr32(FramesRcvOk);
1144 dr32(FramesXmtOk);
1145 dr32(OctetRcvOk);
1146 dr32(OctetXmtOk);
1147
1148 dr32(McstFramesRcvdOk);
1149 dr32(SingleColFrames);
1150 dr32(MultiColFrames);
1151 dr32(LateCollisions);
1152 /* detailed rx errors */
1153 dr16(FrameTooLongErrors);
1154 dr16(InRangeLengthErrors);
1155 dr16(FramesCheckSeqErrors);
1156 dr16(FramesLostRxErrors);
1157
1158 /* detailed tx errors */
1159 dr16(FramesAbortXSColls);
1160 dr16(CarrierSenseErrors);
1161
1162 /* Clear all other statistic register. */
1163 dr32(McstOctetXmtOk);
1164 dr16(BcstFramesXmtdOk);
1165 dr32(McstFramesXmtdOk);
1166 dr16(BcstFramesRcvdOk);
1167 dr16(MacControlFramesRcvd);
1168 dr32(McstOctetXmtOk);
1169 dr32(BcstOctetXmtOk);
1170 dr32(McstFramesXmtdOk);
1171 dr32(FramesWDeferredXmt);
1172 dr16(BcstFramesXmtdOk);
1173 dr16(MacControlFramesXmtd);
1174 dr16(FramesWEXDeferal);
1175#ifdef MEM_MAPPING
1176 for (i = 0x100; i <= 0x150; i += 4)
1177 dr32(i);
1178#endif
1179 dr16(TxJumboFrames);
1180 dr16(RxJumboFrames);
1181 dr16(TCPCheckSumErrors);
1182 dr16(UDPCheckSumErrors);
1183 dr16(IPCheckSumErrors);
1184 return 0;
1185}
1186
1187static void
1188set_multicast (struct net_device *dev)
1189{
1190 struct netdev_private *np = netdev_priv(dev);
1191 void __iomem *ioaddr = np->ioaddr;
1192 u32 hash_table[2];
1193 u16 rx_mode = 0;
1194
1195 hash_table[0] = hash_table[1] = 0;
1196 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1197 hash_table[1] |= 0x02000000;
1198 if (dev->flags & IFF_PROMISC) {
1199 /* Receive all frames promiscuously. */
1200 rx_mode = ReceiveAllFrames;
1201 } else if ((dev->flags & IFF_ALLMULTI) ||
1202 (netdev_mc_count(dev) > multicast_filter_limit)) {
1203 /* Receive broadcast and multicast frames */
1204 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1205 } else if (!netdev_mc_empty(dev)) {
1206 struct netdev_hw_addr *ha;
1207 /* Receive broadcast frames and multicast frames filtering
1208 by Hashtable */
1209 rx_mode =
1210 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1211 netdev_for_each_mc_addr(ha, dev) {
1212 int bit, index = 0;
1213 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1214 /* The inverted high significant 6 bits of CRC are
1215 used as an index to hashtable */
1216 for (bit = 0; bit < 6; bit++)
1217 if (crc & (1 << (31 - bit)))
1218 index |= (1 << bit);
1219 hash_table[index / 32] |= (1 << (index % 32));
1220 }
1221 } else {
1222 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1223 }
1224 if (np->vlan) {
1225 /* ReceiveVLANMatch field in ReceiveMode */
1226 rx_mode |= ReceiveVLANMatch;
1227 }
1228
1229 dw32(HashTable0, hash_table[0]);
1230 dw32(HashTable1, hash_table[1]);
1231 dw16(ReceiveMode, rx_mode);
1232}
1233
1234static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1235{
1236 struct netdev_private *np = netdev_priv(dev);
1237
1238 strlcpy(info->driver, "dl2k", sizeof(info->driver));
1239 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1240}
1241
1242static int rio_get_link_ksettings(struct net_device *dev,
1243 struct ethtool_link_ksettings *cmd)
1244{
1245 struct netdev_private *np = netdev_priv(dev);
1246 u32 supported, advertising;
1247
1248 if (np->phy_media) {
1249 /* fiber device */
1250 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1251 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1252 cmd->base.port = PORT_FIBRE;
1253 } else {
1254 /* copper device */
1255 supported = SUPPORTED_10baseT_Half |
1256 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1257 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1258 SUPPORTED_Autoneg | SUPPORTED_MII;
1259 advertising = ADVERTISED_10baseT_Half |
1260 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1261 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1262 ADVERTISED_Autoneg | ADVERTISED_MII;
1263 cmd->base.port = PORT_MII;
1264 }
1265 if (np->link_status) {
1266 cmd->base.speed = np->speed;
1267 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1268 } else {
1269 cmd->base.speed = SPEED_UNKNOWN;
1270 cmd->base.duplex = DUPLEX_UNKNOWN;
1271 }
1272 if (np->an_enable)
1273 cmd->base.autoneg = AUTONEG_ENABLE;
1274 else
1275 cmd->base.autoneg = AUTONEG_DISABLE;
1276
1277 cmd->base.phy_address = np->phy_addr;
1278
1279 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1280 supported);
1281 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1282 advertising);
1283
1284 return 0;
1285}
1286
1287static int rio_set_link_ksettings(struct net_device *dev,
1288 const struct ethtool_link_ksettings *cmd)
1289{
1290 struct netdev_private *np = netdev_priv(dev);
1291 u32 speed = cmd->base.speed;
1292 u8 duplex = cmd->base.duplex;
1293
1294 netif_carrier_off(dev);
1295 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1296 if (np->an_enable) {
1297 return 0;
1298 } else {
1299 np->an_enable = 1;
1300 mii_set_media(dev);
1301 return 0;
1302 }
1303 } else {
1304 np->an_enable = 0;
1305 if (np->speed == 1000) {
1306 speed = SPEED_100;
1307 duplex = DUPLEX_FULL;
1308 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1309 }
1310 switch (speed) {
1311 case SPEED_10:
1312 np->speed = 10;
1313 np->full_duplex = (duplex == DUPLEX_FULL);
1314 break;
1315 case SPEED_100:
1316 np->speed = 100;
1317 np->full_duplex = (duplex == DUPLEX_FULL);
1318 break;
1319 case SPEED_1000: /* not supported */
1320 default:
1321 return -EINVAL;
1322 }
1323 mii_set_media(dev);
1324 }
1325 return 0;
1326}
1327
1328static u32 rio_get_link(struct net_device *dev)
1329{
1330 struct netdev_private *np = netdev_priv(dev);
1331 return np->link_status;
1332}
1333
1334static const struct ethtool_ops ethtool_ops = {
1335 .get_drvinfo = rio_get_drvinfo,
1336 .get_link = rio_get_link,
1337 .get_link_ksettings = rio_get_link_ksettings,
1338 .set_link_ksettings = rio_set_link_ksettings,
1339};
1340
1341static int
1342rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1343{
1344 int phy_addr;
1345 struct netdev_private *np = netdev_priv(dev);
1346 struct mii_ioctl_data *miidata = if_mii(rq);
1347
1348 phy_addr = np->phy_addr;
1349 switch (cmd) {
1350 case SIOCGMIIPHY:
1351 miidata->phy_id = phy_addr;
1352 break;
1353 case SIOCGMIIREG:
1354 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1355 break;
1356 case SIOCSMIIREG:
1357 if (!capable(CAP_NET_ADMIN))
1358 return -EPERM;
1359 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1360 break;
1361 default:
1362 return -EOPNOTSUPP;
1363 }
1364 return 0;
1365}
1366
1367#define EEP_READ 0x0200
1368#define EEP_BUSY 0x8000
1369/* Read the EEPROM word */
1370/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1371static int read_eeprom(struct netdev_private *np, int eep_addr)
1372{
1373 void __iomem *ioaddr = np->eeprom_addr;
1374 int i = 1000;
1375
1376 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1377 while (i-- > 0) {
1378 if (!(dr16(EepromCtrl) & EEP_BUSY))
1379 return dr16(EepromData);
1380 }
1381 return 0;
1382}
1383
1384enum phy_ctrl_bits {
1385 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1386 MII_DUPLEX = 0x08,
1387};
1388
1389#define mii_delay() dr8(PhyCtrl)
1390static void
1391mii_sendbit (struct net_device *dev, u32 data)
1392{
1393 struct netdev_private *np = netdev_priv(dev);
1394 void __iomem *ioaddr = np->ioaddr;
1395
1396 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1397 dw8(PhyCtrl, data);
1398 mii_delay ();
1399 dw8(PhyCtrl, data | MII_CLK);
1400 mii_delay ();
1401}
1402
1403static int
1404mii_getbit (struct net_device *dev)
1405{
1406 struct netdev_private *np = netdev_priv(dev);
1407 void __iomem *ioaddr = np->ioaddr;
1408 u8 data;
1409
1410 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1411 dw8(PhyCtrl, data);
1412 mii_delay ();
1413 dw8(PhyCtrl, data | MII_CLK);
1414 mii_delay ();
1415 return (dr8(PhyCtrl) >> 1) & 1;
1416}
1417
1418static void
1419mii_send_bits (struct net_device *dev, u32 data, int len)
1420{
1421 int i;
1422
1423 for (i = len - 1; i >= 0; i--) {
1424 mii_sendbit (dev, data & (1 << i));
1425 }
1426}
1427
1428static int
1429mii_read (struct net_device *dev, int phy_addr, int reg_num)
1430{
1431 u32 cmd;
1432 int i;
1433 u32 retval = 0;
1434
1435 /* Preamble */
1436 mii_send_bits (dev, 0xffffffff, 32);
1437 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1438 /* ST,OP = 0110'b for read operation */
1439 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1440 mii_send_bits (dev, cmd, 14);
1441 /* Turnaround */
1442 if (mii_getbit (dev))
1443 goto err_out;
1444 /* Read data */
1445 for (i = 0; i < 16; i++) {
1446 retval |= mii_getbit (dev);
1447 retval <<= 1;
1448 }
1449 /* End cycle */
1450 mii_getbit (dev);
1451 return (retval >> 1) & 0xffff;
1452
1453 err_out:
1454 return 0;
1455}
1456static int
1457mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1458{
1459 u32 cmd;
1460
1461 /* Preamble */
1462 mii_send_bits (dev, 0xffffffff, 32);
1463 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1464 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1465 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1466 mii_send_bits (dev, cmd, 32);
1467 /* End cycle */
1468 mii_getbit (dev);
1469 return 0;
1470}
1471static int
1472mii_wait_link (struct net_device *dev, int wait)
1473{
1474 __u16 bmsr;
1475 int phy_addr;
1476 struct netdev_private *np;
1477
1478 np = netdev_priv(dev);
1479 phy_addr = np->phy_addr;
1480
1481 do {
1482 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1483 if (bmsr & BMSR_LSTATUS)
1484 return 0;
1485 mdelay (1);
1486 } while (--wait > 0);
1487 return -1;
1488}
1489static int
1490mii_get_media (struct net_device *dev)
1491{
1492 __u16 negotiate;
1493 __u16 bmsr;
1494 __u16 mscr;
1495 __u16 mssr;
1496 int phy_addr;
1497 struct netdev_private *np;
1498
1499 np = netdev_priv(dev);
1500 phy_addr = np->phy_addr;
1501
1502 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1503 if (np->an_enable) {
1504 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1505 /* Auto-Negotiation not completed */
1506 return -1;
1507 }
1508 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1509 mii_read (dev, phy_addr, MII_LPA);
1510 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1511 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1512 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1513 np->speed = 1000;
1514 np->full_duplex = 1;
1515 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1516 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1517 np->speed = 1000;
1518 np->full_duplex = 0;
1519 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1520 } else if (negotiate & ADVERTISE_100FULL) {
1521 np->speed = 100;
1522 np->full_duplex = 1;
1523 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1524 } else if (negotiate & ADVERTISE_100HALF) {
1525 np->speed = 100;
1526 np->full_duplex = 0;
1527 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1528 } else if (negotiate & ADVERTISE_10FULL) {
1529 np->speed = 10;
1530 np->full_duplex = 1;
1531 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1532 } else if (negotiate & ADVERTISE_10HALF) {
1533 np->speed = 10;
1534 np->full_duplex = 0;
1535 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1536 }
1537 if (negotiate & ADVERTISE_PAUSE_CAP) {
1538 np->tx_flow &= 1;
1539 np->rx_flow &= 1;
1540 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1541 np->tx_flow = 0;
1542 np->rx_flow &= 1;
1543 }
1544 /* else tx_flow, rx_flow = user select */
1545 } else {
1546 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1547 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1548 case BMCR_SPEED1000:
1549 printk (KERN_INFO "Operating at 1000 Mbps, ");
1550 break;
1551 case BMCR_SPEED100:
1552 printk (KERN_INFO "Operating at 100 Mbps, ");
1553 break;
1554 case 0:
1555 printk (KERN_INFO "Operating at 10 Mbps, ");
1556 }
1557 if (bmcr & BMCR_FULLDPLX) {
1558 printk (KERN_CONT "Full duplex\n");
1559 } else {
1560 printk (KERN_CONT "Half duplex\n");
1561 }
1562 }
1563 if (np->tx_flow)
1564 printk(KERN_INFO "Enable Tx Flow Control\n");
1565 else
1566 printk(KERN_INFO "Disable Tx Flow Control\n");
1567 if (np->rx_flow)
1568 printk(KERN_INFO "Enable Rx Flow Control\n");
1569 else
1570 printk(KERN_INFO "Disable Rx Flow Control\n");
1571
1572 return 0;
1573}
1574
1575static int
1576mii_set_media (struct net_device *dev)
1577{
1578 __u16 pscr;
1579 __u16 bmcr;
1580 __u16 bmsr;
1581 __u16 anar;
1582 int phy_addr;
1583 struct netdev_private *np;
1584 np = netdev_priv(dev);
1585 phy_addr = np->phy_addr;
1586
1587 /* Does user set speed? */
1588 if (np->an_enable) {
1589 /* Advertise capabilities */
1590 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1591 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1592 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1593 ADVERTISE_100HALF | ADVERTISE_10HALF |
1594 ADVERTISE_100BASE4);
1595 if (bmsr & BMSR_100FULL)
1596 anar |= ADVERTISE_100FULL;
1597 if (bmsr & BMSR_100HALF)
1598 anar |= ADVERTISE_100HALF;
1599 if (bmsr & BMSR_100BASE4)
1600 anar |= ADVERTISE_100BASE4;
1601 if (bmsr & BMSR_10FULL)
1602 anar |= ADVERTISE_10FULL;
1603 if (bmsr & BMSR_10HALF)
1604 anar |= ADVERTISE_10HALF;
1605 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1606 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1607
1608 /* Enable Auto crossover */
1609 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1610 pscr |= 3 << 5; /* 11'b */
1611 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1612
1613 /* Soft reset PHY */
1614 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1615 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1616 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1617 mdelay(1);
1618 } else {
1619 /* Force speed setting */
1620 /* 1) Disable Auto crossover */
1621 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1622 pscr &= ~(3 << 5);
1623 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1624
1625 /* 2) PHY Reset */
1626 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1627 bmcr |= BMCR_RESET;
1628 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1629
1630 /* 3) Power Down */
1631 bmcr = 0x1940; /* must be 0x1940 */
1632 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1633 mdelay (100); /* wait a certain time */
1634
1635 /* 4) Advertise nothing */
1636 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1637
1638 /* 5) Set media and Power Up */
1639 bmcr = BMCR_PDOWN;
1640 if (np->speed == 100) {
1641 bmcr |= BMCR_SPEED100;
1642 printk (KERN_INFO "Manual 100 Mbps, ");
1643 } else if (np->speed == 10) {
1644 printk (KERN_INFO "Manual 10 Mbps, ");
1645 }
1646 if (np->full_duplex) {
1647 bmcr |= BMCR_FULLDPLX;
1648 printk (KERN_CONT "Full duplex\n");
1649 } else {
1650 printk (KERN_CONT "Half duplex\n");
1651 }
1652#if 0
1653 /* Set 1000BaseT Master/Slave setting */
1654 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1655 mscr |= MII_MSCR_CFG_ENABLE;
1656 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1657#endif
1658 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1659 mdelay(10);
1660 }
1661 return 0;
1662}
1663
1664static int
1665mii_get_media_pcs (struct net_device *dev)
1666{
1667 __u16 negotiate;
1668 __u16 bmsr;
1669 int phy_addr;
1670 struct netdev_private *np;
1671
1672 np = netdev_priv(dev);
1673 phy_addr = np->phy_addr;
1674
1675 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1676 if (np->an_enable) {
1677 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1678 /* Auto-Negotiation not completed */
1679 return -1;
1680 }
1681 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1682 mii_read (dev, phy_addr, PCS_ANLPAR);
1683 np->speed = 1000;
1684 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1685 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1686 np->full_duplex = 1;
1687 } else {
1688 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1689 np->full_duplex = 0;
1690 }
1691 if (negotiate & PCS_ANAR_PAUSE) {
1692 np->tx_flow &= 1;
1693 np->rx_flow &= 1;
1694 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1695 np->tx_flow = 0;
1696 np->rx_flow &= 1;
1697 }
1698 /* else tx_flow, rx_flow = user select */
1699 } else {
1700 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1701 printk (KERN_INFO "Operating at 1000 Mbps, ");
1702 if (bmcr & BMCR_FULLDPLX) {
1703 printk (KERN_CONT "Full duplex\n");
1704 } else {
1705 printk (KERN_CONT "Half duplex\n");
1706 }
1707 }
1708 if (np->tx_flow)
1709 printk(KERN_INFO "Enable Tx Flow Control\n");
1710 else
1711 printk(KERN_INFO "Disable Tx Flow Control\n");
1712 if (np->rx_flow)
1713 printk(KERN_INFO "Enable Rx Flow Control\n");
1714 else
1715 printk(KERN_INFO "Disable Rx Flow Control\n");
1716
1717 return 0;
1718}
1719
1720static int
1721mii_set_media_pcs (struct net_device *dev)
1722{
1723 __u16 bmcr;
1724 __u16 esr;
1725 __u16 anar;
1726 int phy_addr;
1727 struct netdev_private *np;
1728 np = netdev_priv(dev);
1729 phy_addr = np->phy_addr;
1730
1731 /* Auto-Negotiation? */
1732 if (np->an_enable) {
1733 /* Advertise capabilities */
1734 esr = mii_read (dev, phy_addr, PCS_ESR);
1735 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1736 ~PCS_ANAR_HALF_DUPLEX &
1737 ~PCS_ANAR_FULL_DUPLEX;
1738 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1739 anar |= PCS_ANAR_HALF_DUPLEX;
1740 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1741 anar |= PCS_ANAR_FULL_DUPLEX;
1742 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1743 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1744
1745 /* Soft reset PHY */
1746 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1747 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1748 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1749 mdelay(1);
1750 } else {
1751 /* Force speed setting */
1752 /* PHY Reset */
1753 bmcr = BMCR_RESET;
1754 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1755 mdelay(10);
1756 if (np->full_duplex) {
1757 bmcr = BMCR_FULLDPLX;
1758 printk (KERN_INFO "Manual full duplex\n");
1759 } else {
1760 bmcr = 0;
1761 printk (KERN_INFO "Manual half duplex\n");
1762 }
1763 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1764 mdelay(10);
1765
1766 /* Advertise nothing */
1767 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1768 }
1769 return 0;
1770}
1771
1772
1773static int
1774rio_close (struct net_device *dev)
1775{
1776 struct netdev_private *np = netdev_priv(dev);
1777 struct pci_dev *pdev = np->pdev;
1778
1779 netif_stop_queue (dev);
1780
1781 rio_hw_stop(dev);
1782
1783 free_irq(pdev->irq, dev);
1784 del_timer_sync (&np->timer);
1785
1786 free_list(dev);
1787
1788 return 0;
1789}
1790
1791static void
1792rio_remove1 (struct pci_dev *pdev)
1793{
1794 struct net_device *dev = pci_get_drvdata (pdev);
1795
1796 if (dev) {
1797 struct netdev_private *np = netdev_priv(dev);
1798
1799 unregister_netdev (dev);
1800 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
1801 np->rx_ring_dma);
1802 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
1803 np->tx_ring_dma);
1804#ifdef MEM_MAPPING
1805 pci_iounmap(pdev, np->ioaddr);
1806#endif
1807 pci_iounmap(pdev, np->eeprom_addr);
1808 free_netdev (dev);
1809 pci_release_regions (pdev);
1810 pci_disable_device (pdev);
1811 }
1812}
1813
1814#ifdef CONFIG_PM_SLEEP
1815static int rio_suspend(struct device *device)
1816{
1817 struct net_device *dev = dev_get_drvdata(device);
1818 struct netdev_private *np = netdev_priv(dev);
1819
1820 if (!netif_running(dev))
1821 return 0;
1822
1823 netif_device_detach(dev);
1824 del_timer_sync(&np->timer);
1825 rio_hw_stop(dev);
1826
1827 return 0;
1828}
1829
1830static int rio_resume(struct device *device)
1831{
1832 struct net_device *dev = dev_get_drvdata(device);
1833 struct netdev_private *np = netdev_priv(dev);
1834
1835 if (!netif_running(dev))
1836 return 0;
1837
1838 rio_reset_ring(np);
1839 rio_hw_init(dev);
1840 np->timer.expires = jiffies + 1 * HZ;
1841 add_timer(&np->timer);
1842 netif_device_attach(dev);
1843 dl2k_enable_int(np);
1844
1845 return 0;
1846}
1847
1848static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1849#define RIO_PM_OPS (&rio_pm_ops)
1850
1851#else
1852
1853#define RIO_PM_OPS NULL
1854
1855#endif /* CONFIG_PM_SLEEP */
1856
1857static struct pci_driver rio_driver = {
1858 .name = "dl2k",
1859 .id_table = rio_pci_tbl,
1860 .probe = rio_probe1,
1861 .remove = rio_remove1,
1862 .driver.pm = RIO_PM_OPS,
1863};
1864
1865module_pci_driver(rio_driver);
1866
1867/* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */
1868

source code of linux/drivers/net/ethernet/dlink/dl2k.c