1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
2 | /* Copyright 2017-2019 NXP */ |
3 | |
4 | #include <linux/timer.h> |
5 | #include <linux/pci.h> |
6 | #include <linux/netdevice.h> |
7 | #include <linux/etherdevice.h> |
8 | #include <linux/dma-mapping.h> |
9 | #include <linux/skbuff.h> |
10 | #include <linux/ethtool.h> |
11 | #include <linux/if_vlan.h> |
12 | #include <linux/phylink.h> |
13 | #include <linux/dim.h> |
14 | #include <net/xdp.h> |
15 | |
16 | #include "enetc_hw.h" |
17 | |
18 | #define ENETC_MAC_MAXFRM_SIZE 9600 |
19 | #define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \ |
20 | (ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN)) |
21 | |
22 | #define ENETC_CBD_DATA_MEM_ALIGN 64 |
23 | |
24 | struct enetc_tx_swbd { |
25 | union { |
26 | struct sk_buff *skb; |
27 | struct xdp_frame *xdp_frame; |
28 | }; |
29 | dma_addr_t dma; |
30 | struct page *page; /* valid only if is_xdp_tx */ |
31 | u16 page_offset; /* valid only if is_xdp_tx */ |
32 | u16 len; |
33 | enum dma_data_direction dir; |
34 | u8 is_dma_page:1; |
35 | u8 check_wb:1; |
36 | u8 do_twostep_tstamp:1; |
37 | u8 is_eof:1; |
38 | u8 is_xdp_tx:1; |
39 | u8 is_xdp_redirect:1; |
40 | u8 qbv_en:1; |
41 | }; |
42 | |
43 | #define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE |
44 | #define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */ |
45 | #define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */ |
46 | #define ENETC_RXB_DMA_SIZE \ |
47 | (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD) |
48 | #define ENETC_RXB_DMA_SIZE_XDP \ |
49 | (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - XDP_PACKET_HEADROOM) |
50 | |
51 | struct enetc_rx_swbd { |
52 | dma_addr_t dma; |
53 | struct page *page; |
54 | u16 page_offset; |
55 | enum dma_data_direction dir; |
56 | u16 len; |
57 | }; |
58 | |
59 | /* ENETC overhead: optional extension BD + 1 BD gap */ |
60 | #define ENETC_TXBDS_NEEDED(val) ((val) + 2) |
61 | /* max # of chained Tx BDs is 15, including head and extension BD */ |
62 | #define ENETC_MAX_SKB_FRAGS 13 |
63 | #define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1) |
64 | |
65 | struct enetc_ring_stats { |
66 | unsigned int packets; |
67 | unsigned int bytes; |
68 | unsigned int rx_alloc_errs; |
69 | unsigned int xdp_drops; |
70 | unsigned int xdp_tx; |
71 | unsigned int xdp_tx_drops; |
72 | unsigned int xdp_redirect; |
73 | unsigned int xdp_redirect_failures; |
74 | unsigned int recycles; |
75 | unsigned int recycle_failures; |
76 | unsigned int win_drop; |
77 | }; |
78 | |
79 | struct enetc_xdp_data { |
80 | struct xdp_rxq_info rxq; |
81 | struct bpf_prog *prog; |
82 | int xdp_tx_in_flight; |
83 | }; |
84 | |
85 | #define ENETC_RX_RING_DEFAULT_SIZE 2048 |
86 | #define ENETC_TX_RING_DEFAULT_SIZE 2048 |
87 | #define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2) |
88 | |
89 | struct enetc_bdr_resource { |
90 | /* Input arguments saved for teardown */ |
91 | struct device *dev; /* for DMA mapping */ |
92 | size_t bd_count; |
93 | size_t bd_size; |
94 | |
95 | /* Resource proper */ |
96 | void *bd_base; /* points to Rx or Tx BD ring */ |
97 | dma_addr_t bd_dma_base; |
98 | union { |
99 | struct enetc_tx_swbd *tx_swbd; |
100 | struct enetc_rx_swbd *rx_swbd; |
101 | }; |
102 | char *; |
103 | dma_addr_t ; |
104 | }; |
105 | |
106 | struct enetc_bdr { |
107 | struct device *dev; /* for DMA mapping */ |
108 | struct net_device *ndev; |
109 | void *bd_base; /* points to Rx or Tx BD ring */ |
110 | union { |
111 | void __iomem *tpir; |
112 | void __iomem *rcir; |
113 | }; |
114 | u16 index; |
115 | u16 prio; |
116 | int bd_count; /* # of BDs */ |
117 | int next_to_use; |
118 | int next_to_clean; |
119 | union { |
120 | struct enetc_tx_swbd *tx_swbd; |
121 | struct enetc_rx_swbd *rx_swbd; |
122 | }; |
123 | union { |
124 | void __iomem *tcir; /* Tx */ |
125 | int next_to_alloc; /* Rx */ |
126 | }; |
127 | void __iomem *idr; /* Interrupt Detect Register pointer */ |
128 | |
129 | int buffer_offset; |
130 | struct enetc_xdp_data xdp; |
131 | |
132 | struct enetc_ring_stats stats; |
133 | |
134 | dma_addr_t bd_dma_base; |
135 | u8 tsd_enable; /* Time specific departure */ |
136 | bool ext_en; /* enable h/w descriptor extensions */ |
137 | |
138 | /* DMA buffer for TSO headers */ |
139 | char *; |
140 | dma_addr_t ; |
141 | } ____cacheline_aligned_in_smp; |
142 | |
143 | static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i) |
144 | { |
145 | if (unlikely(++*i == bdr->bd_count)) |
146 | *i = 0; |
147 | } |
148 | |
149 | static inline int enetc_bd_unused(struct enetc_bdr *bdr) |
150 | { |
151 | if (bdr->next_to_clean > bdr->next_to_use) |
152 | return bdr->next_to_clean - bdr->next_to_use - 1; |
153 | |
154 | return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; |
155 | } |
156 | |
157 | static inline int enetc_swbd_unused(struct enetc_bdr *bdr) |
158 | { |
159 | if (bdr->next_to_clean > bdr->next_to_alloc) |
160 | return bdr->next_to_clean - bdr->next_to_alloc - 1; |
161 | |
162 | return bdr->bd_count + bdr->next_to_clean - bdr->next_to_alloc - 1; |
163 | } |
164 | |
165 | /* Control BD ring */ |
166 | #define ENETC_CBDR_DEFAULT_SIZE 64 |
167 | struct enetc_cbdr { |
168 | void *bd_base; /* points to Rx or Tx BD ring */ |
169 | void __iomem *pir; |
170 | void __iomem *cir; |
171 | void __iomem *mr; /* mode register */ |
172 | |
173 | int bd_count; /* # of BDs */ |
174 | int next_to_use; |
175 | int next_to_clean; |
176 | |
177 | dma_addr_t bd_dma_base; |
178 | struct device *dma_dev; |
179 | }; |
180 | |
181 | #define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i])) |
182 | |
183 | static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i) |
184 | { |
185 | int hw_idx = i; |
186 | |
187 | #ifdef CONFIG_FSL_ENETC_PTP_CLOCK |
188 | if (rx_ring->ext_en) |
189 | hw_idx = 2 * i; |
190 | #endif |
191 | return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]); |
192 | } |
193 | |
194 | static inline void enetc_rxbd_next(struct enetc_bdr *rx_ring, |
195 | union enetc_rx_bd **old_rxbd, int *old_index) |
196 | { |
197 | union enetc_rx_bd *new_rxbd = *old_rxbd; |
198 | int new_index = *old_index; |
199 | |
200 | new_rxbd++; |
201 | |
202 | #ifdef CONFIG_FSL_ENETC_PTP_CLOCK |
203 | if (rx_ring->ext_en) |
204 | new_rxbd++; |
205 | #endif |
206 | |
207 | if (unlikely(++new_index == rx_ring->bd_count)) { |
208 | new_rxbd = rx_ring->bd_base; |
209 | new_index = 0; |
210 | } |
211 | |
212 | *old_rxbd = new_rxbd; |
213 | *old_index = new_index; |
214 | } |
215 | |
216 | static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd) |
217 | { |
218 | return ++rxbd; |
219 | } |
220 | |
221 | struct enetc_msg_swbd { |
222 | void *vaddr; |
223 | dma_addr_t dma; |
224 | int size; |
225 | }; |
226 | |
227 | #define ENETC_REV1 0x1 |
228 | enum enetc_errata { |
229 | ENETC_ERR_VLAN_ISOL = BIT(0), |
230 | ENETC_ERR_UCMCSWP = BIT(1), |
231 | }; |
232 | |
233 | #define ENETC_SI_F_PSFP BIT(0) |
234 | #define ENETC_SI_F_QBV BIT(1) |
235 | #define ENETC_SI_F_QBU BIT(2) |
236 | |
237 | /* PCI IEP device data */ |
238 | struct enetc_si { |
239 | struct pci_dev *pdev; |
240 | struct enetc_hw hw; |
241 | enum enetc_errata errata; |
242 | |
243 | struct net_device *ndev; /* back ref. */ |
244 | |
245 | struct enetc_cbdr cbd_ring; |
246 | |
247 | int num_rx_rings; /* how many rings are available in the SI */ |
248 | int num_tx_rings; |
249 | int num_fs_entries; |
250 | int ; /* number of RSS buckets */ |
251 | unsigned short pad; |
252 | int hw_features; |
253 | }; |
254 | |
255 | #define ENETC_SI_ALIGN 32 |
256 | |
257 | static inline void *enetc_si_priv(const struct enetc_si *si) |
258 | { |
259 | return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN); |
260 | } |
261 | |
262 | static inline bool enetc_si_is_pf(struct enetc_si *si) |
263 | { |
264 | return !!(si->hw.port); |
265 | } |
266 | |
267 | static inline int enetc_pf_to_port(struct pci_dev *pf_pdev) |
268 | { |
269 | switch (pf_pdev->devfn) { |
270 | case 0: |
271 | return 0; |
272 | case 1: |
273 | return 1; |
274 | case 2: |
275 | return 2; |
276 | case 6: |
277 | return 3; |
278 | default: |
279 | return -1; |
280 | } |
281 | } |
282 | |
283 | #define ENETC_MAX_NUM_TXQS 8 |
284 | #define ENETC_INT_NAME_MAX (IFNAMSIZ + 8) |
285 | |
286 | struct enetc_int_vector { |
287 | void __iomem *rbier; |
288 | void __iomem *tbier_base; |
289 | void __iomem *ricr1; |
290 | unsigned long tx_rings_map; |
291 | int count_tx_rings; |
292 | u32 rx_ictt; |
293 | u16 comp_cnt; |
294 | bool rx_dim_en, rx_napi_work; |
295 | struct napi_struct napi ____cacheline_aligned_in_smp; |
296 | struct dim rx_dim ____cacheline_aligned_in_smp; |
297 | char name[ENETC_INT_NAME_MAX]; |
298 | |
299 | struct enetc_bdr rx_ring; |
300 | struct enetc_bdr tx_ring[] __counted_by(count_tx_rings); |
301 | } ____cacheline_aligned_in_smp; |
302 | |
303 | struct enetc_cls_rule { |
304 | struct ethtool_rx_flow_spec fs; |
305 | int used; |
306 | }; |
307 | |
308 | #define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */ |
309 | struct psfp_cap { |
310 | u32 max_streamid; |
311 | u32 max_psfp_filter; |
312 | u32 max_psfp_gate; |
313 | u32 max_psfp_gatelist; |
314 | u32 max_psfp_meter; |
315 | }; |
316 | |
317 | #define ENETC_F_TX_TSTAMP_MASK 0xff |
318 | enum enetc_active_offloads { |
319 | /* 8 bits reserved for TX timestamp types (hwtstamp_tx_types) */ |
320 | ENETC_F_TX_TSTAMP = BIT(0), |
321 | ENETC_F_TX_ONESTEP_SYNC_TSTAMP = BIT(1), |
322 | |
323 | ENETC_F_RX_TSTAMP = BIT(8), |
324 | ENETC_F_QBV = BIT(9), |
325 | ENETC_F_QCI = BIT(10), |
326 | ENETC_F_QBU = BIT(11), |
327 | }; |
328 | |
329 | enum enetc_flags_bit { |
330 | ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS = 0, |
331 | }; |
332 | |
333 | /* interrupt coalescing modes */ |
334 | enum enetc_ic_mode { |
335 | /* one interrupt per frame */ |
336 | ENETC_IC_NONE = 0, |
337 | /* activated when int coalescing time is set to a non-0 value */ |
338 | ENETC_IC_RX_MANUAL = BIT(0), |
339 | ENETC_IC_TX_MANUAL = BIT(1), |
340 | /* use dynamic interrupt moderation */ |
341 | ENETC_IC_RX_ADAPTIVE = BIT(2), |
342 | }; |
343 | |
344 | #define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2) |
345 | #define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2) |
346 | #define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600) |
347 | |
348 | struct enetc_ndev_priv { |
349 | struct net_device *ndev; |
350 | struct device *dev; /* dma-mapping device */ |
351 | struct enetc_si *si; |
352 | |
353 | int bdr_int_num; /* number of Rx/Tx ring interrupts */ |
354 | struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT]; |
355 | u16 num_rx_rings, num_tx_rings; |
356 | u16 rx_bd_count, tx_bd_count; |
357 | |
358 | u16 msg_enable; |
359 | |
360 | u8 preemptible_tcs; |
361 | |
362 | enum enetc_active_offloads active_offloads; |
363 | |
364 | u32 speed; /* store speed for compare update pspeed */ |
365 | |
366 | struct enetc_bdr **xdp_tx_ring; |
367 | struct enetc_bdr *tx_ring[16]; |
368 | struct enetc_bdr *rx_ring[16]; |
369 | const struct enetc_bdr_resource *tx_res; |
370 | const struct enetc_bdr_resource *rx_res; |
371 | |
372 | struct enetc_cls_rule *cls_rules; |
373 | |
374 | struct psfp_cap psfp_cap; |
375 | |
376 | /* Minimum number of TX queues required by the network stack */ |
377 | unsigned int min_num_stack_tx_queues; |
378 | |
379 | struct phylink *phylink; |
380 | int ic_mode; |
381 | u32 tx_ictt; |
382 | |
383 | struct bpf_prog *xdp_prog; |
384 | |
385 | unsigned long flags; |
386 | |
387 | struct work_struct tx_onestep_tstamp; |
388 | struct sk_buff_head tx_skbs; |
389 | |
390 | /* Serialize access to MAC Merge state between ethtool requests |
391 | * and link state updates |
392 | */ |
393 | struct mutex mm_lock; |
394 | }; |
395 | |
396 | /* Messaging */ |
397 | |
398 | /* VF-PF set primary MAC address message format */ |
399 | struct enetc_msg_cmd_set_primary_mac { |
400 | struct enetc_msg_cmd_header ; |
401 | struct sockaddr mac; |
402 | }; |
403 | |
404 | #define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i])) |
405 | |
406 | #define ENETC_CBDR_TIMEOUT 1000 /* usecs */ |
407 | |
408 | /* PTP driver exports */ |
409 | extern int enetc_phc_index; |
410 | |
411 | /* SI common */ |
412 | u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg); |
413 | void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val); |
414 | int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv); |
415 | void enetc_pci_remove(struct pci_dev *pdev); |
416 | int enetc_alloc_msix(struct enetc_ndev_priv *priv); |
417 | void enetc_free_msix(struct enetc_ndev_priv *priv); |
418 | void enetc_get_si_caps(struct enetc_si *si); |
419 | void enetc_init_si_rings_params(struct enetc_ndev_priv *priv); |
420 | int enetc_alloc_si_resources(struct enetc_ndev_priv *priv); |
421 | void enetc_free_si_resources(struct enetc_ndev_priv *priv); |
422 | int enetc_configure_si(struct enetc_ndev_priv *priv); |
423 | |
424 | int enetc_open(struct net_device *ndev); |
425 | int enetc_close(struct net_device *ndev); |
426 | void enetc_start(struct net_device *ndev); |
427 | void enetc_stop(struct net_device *ndev); |
428 | netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev); |
429 | struct net_device_stats *enetc_get_stats(struct net_device *ndev); |
430 | void enetc_set_features(struct net_device *ndev, netdev_features_t features); |
431 | int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd); |
432 | int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data); |
433 | void enetc_reset_tc_mqprio(struct net_device *ndev); |
434 | int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf); |
435 | int enetc_xdp_xmit(struct net_device *ndev, int num_frames, |
436 | struct xdp_frame **frames, u32 flags); |
437 | |
438 | /* ethtool */ |
439 | void enetc_set_ethtool_ops(struct net_device *ndev); |
440 | void enetc_mm_link_state_update(struct enetc_ndev_priv *priv, bool link); |
441 | void enetc_mm_commit_preemptible_tcs(struct enetc_ndev_priv *priv); |
442 | |
443 | /* control buffer descriptor ring (CBDR) */ |
444 | int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count, |
445 | struct enetc_cbdr *cbdr); |
446 | void enetc_teardown_cbdr(struct enetc_cbdr *cbdr); |
447 | int enetc_set_mac_flt_entry(struct enetc_si *si, int index, |
448 | char *mac_addr, int si_map); |
449 | int enetc_clear_mac_flt_entry(struct enetc_si *si, int index); |
450 | int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, |
451 | int index); |
452 | void (struct enetc_hw *hw, const u8 *bytes); |
453 | int (struct enetc_si *si, u32 *table, int count); |
454 | int (struct enetc_si *si, const u32 *table, int count); |
455 | int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd); |
456 | |
457 | static inline void *enetc_cbd_alloc_data_mem(struct enetc_si *si, |
458 | struct enetc_cbd *cbd, |
459 | int size, dma_addr_t *dma, |
460 | void **data_align) |
461 | { |
462 | struct enetc_cbdr *ring = &si->cbd_ring; |
463 | dma_addr_t dma_align; |
464 | void *data; |
465 | |
466 | data = dma_alloc_coherent(dev: ring->dma_dev, |
467 | size: size + ENETC_CBD_DATA_MEM_ALIGN, |
468 | dma_handle: dma, GFP_KERNEL); |
469 | if (!data) { |
470 | dev_err(ring->dma_dev, "CBD alloc data memory failed!\n" ); |
471 | return NULL; |
472 | } |
473 | |
474 | dma_align = ALIGN(*dma, ENETC_CBD_DATA_MEM_ALIGN); |
475 | *data_align = PTR_ALIGN(data, ENETC_CBD_DATA_MEM_ALIGN); |
476 | |
477 | cbd->addr[0] = cpu_to_le32(lower_32_bits(dma_align)); |
478 | cbd->addr[1] = cpu_to_le32(upper_32_bits(dma_align)); |
479 | cbd->length = cpu_to_le16(size); |
480 | |
481 | return data; |
482 | } |
483 | |
484 | static inline void enetc_cbd_free_data_mem(struct enetc_si *si, int size, |
485 | void *data, dma_addr_t *dma) |
486 | { |
487 | struct enetc_cbdr *ring = &si->cbd_ring; |
488 | |
489 | dma_free_coherent(dev: ring->dma_dev, size: size + ENETC_CBD_DATA_MEM_ALIGN, |
490 | cpu_addr: data, dma_handle: *dma); |
491 | } |
492 | |
493 | void enetc_reset_ptcmsdur(struct enetc_hw *hw); |
494 | void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *queue_max_sdu); |
495 | |
496 | #ifdef CONFIG_FSL_ENETC_QOS |
497 | int enetc_qos_query_caps(struct net_device *ndev, void *type_data); |
498 | int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data); |
499 | void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed); |
500 | int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data); |
501 | int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data); |
502 | int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
503 | void *cb_priv); |
504 | int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data); |
505 | int enetc_psfp_init(struct enetc_ndev_priv *priv); |
506 | int enetc_psfp_clean(struct enetc_ndev_priv *priv); |
507 | int enetc_set_psfp(struct net_device *ndev, bool en); |
508 | |
509 | static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv) |
510 | { |
511 | struct enetc_hw *hw = &priv->si->hw; |
512 | u32 reg; |
513 | |
514 | reg = enetc_port_rd(hw, ENETC_PSIDCAPR); |
515 | priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK; |
516 | /* Port stream filter capability */ |
517 | reg = enetc_port_rd(hw, ENETC_PSFCAPR); |
518 | priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK; |
519 | /* Port stream gate capability */ |
520 | reg = enetc_port_rd(hw, ENETC_PSGCAPR); |
521 | priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK); |
522 | priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16; |
523 | /* Port flow meter capability */ |
524 | reg = enetc_port_rd(hw, ENETC_PFMCAPR); |
525 | priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK; |
526 | } |
527 | |
528 | static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) |
529 | { |
530 | struct enetc_hw *hw = &priv->si->hw; |
531 | int err; |
532 | |
533 | enetc_get_max_cap(priv); |
534 | |
535 | err = enetc_psfp_init(priv); |
536 | if (err) |
537 | return err; |
538 | |
539 | enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) | |
540 | ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS | |
541 | ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC); |
542 | |
543 | return 0; |
544 | } |
545 | |
546 | static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) |
547 | { |
548 | struct enetc_hw *hw = &priv->si->hw; |
549 | int err; |
550 | |
551 | err = enetc_psfp_clean(priv); |
552 | if (err) |
553 | return err; |
554 | |
555 | enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) & |
556 | ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS & |
557 | ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC); |
558 | |
559 | memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap)); |
560 | |
561 | return 0; |
562 | } |
563 | |
564 | #else |
565 | #define enetc_qos_query_caps(ndev, type_data) -EOPNOTSUPP |
566 | #define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP |
567 | #define enetc_sched_speed_set(priv, speed) (void)0 |
568 | #define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP |
569 | #define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP |
570 | #define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP |
571 | #define enetc_setup_tc_block_cb NULL |
572 | |
573 | #define enetc_get_max_cap(p) \ |
574 | memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap)) |
575 | |
576 | static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) |
577 | { |
578 | return 0; |
579 | } |
580 | |
581 | static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) |
582 | { |
583 | return 0; |
584 | } |
585 | |
586 | static inline int enetc_set_psfp(struct net_device *ndev, bool en) |
587 | { |
588 | return 0; |
589 | } |
590 | #endif |
591 | |