1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright(c) 1999 - 2018 Intel Corporation. */ |
3 | |
4 | #ifndef _IXGBE_COMMON_H_ |
5 | #define _IXGBE_COMMON_H_ |
6 | |
7 | #include "ixgbe_type.h" |
8 | #include "ixgbe.h" |
9 | |
10 | u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw); |
11 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); |
12 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); |
13 | s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw); |
14 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw); |
15 | s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, |
16 | u32 pba_num_size); |
17 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); |
18 | enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status); |
19 | enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status); |
20 | s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); |
21 | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw); |
22 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); |
23 | |
24 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); |
25 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); |
26 | s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw); |
27 | |
28 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); |
29 | s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); |
30 | s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
31 | u16 words, u16 *data); |
32 | s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); |
33 | s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, |
34 | u16 words, u16 *data); |
35 | s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data); |
36 | s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, |
37 | u16 words, u16 *data); |
38 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
39 | u16 *data); |
40 | s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
41 | u16 words, u16 *data); |
42 | s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); |
43 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
44 | u16 *checksum_val); |
45 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); |
46 | |
47 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, |
48 | u32 enable_addr); |
49 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index); |
50 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); |
51 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, |
52 | struct net_device *netdev); |
53 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); |
54 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); |
55 | s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw); |
56 | s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw); |
57 | s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); |
58 | s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw); |
59 | s32 ixgbe_setup_fc_generic(struct ixgbe_hw *); |
60 | bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); |
61 | void ixgbe_fc_autoneg(struct ixgbe_hw *hw); |
62 | |
63 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask); |
64 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask); |
65 | s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr); |
66 | s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
67 | s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq); |
68 | s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
69 | s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw); |
70 | s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, |
71 | u32 vind, bool vlan_on, bool vlvf_bypass); |
72 | s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw); |
73 | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, |
74 | ixgbe_link_speed *speed, |
75 | bool *link_up, bool link_up_wait_to_complete); |
76 | s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, |
77 | u16 *wwpn_prefix); |
78 | |
79 | s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val); |
80 | s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked); |
81 | |
82 | s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); |
83 | s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); |
84 | void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); |
85 | void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); |
86 | s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps); |
87 | s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, |
88 | u8 build, u8 ver, u16 len, const char *str); |
89 | u8 ixgbe_calculate_checksum(u8 *buffer, u32 length); |
90 | s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length, |
91 | u32 timeout, bool return_data); |
92 | s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 len, u32 timeout); |
93 | s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, |
94 | u32 (*data)[FW_PHY_ACT_DATA_COUNT]); |
95 | void ixgbe_clear_tx_pending(struct ixgbe_hw *hw); |
96 | bool ixgbe_mng_present(struct ixgbe_hw *hw); |
97 | bool ixgbe_mng_enabled(struct ixgbe_hw *hw); |
98 | |
99 | void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, |
100 | u32 headroom, int strategy); |
101 | |
102 | extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT]; |
103 | |
104 | #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 |
105 | #define IXGBE_EMC_INTERNAL_DATA 0x00 |
106 | #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 |
107 | #define IXGBE_EMC_DIODE1_DATA 0x01 |
108 | #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 |
109 | #define IXGBE_EMC_DIODE2_DATA 0x23 |
110 | #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A |
111 | #define IXGBE_EMC_DIODE3_DATA 0x2A |
112 | #define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30 |
113 | |
114 | s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw); |
115 | s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw); |
116 | void ixgbe_get_etk_id(struct ixgbe_hw *hw, |
117 | struct ixgbe_nvm_version *nvm_ver); |
118 | void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, |
119 | struct ixgbe_nvm_version *nvm_ver); |
120 | void ixgbe_get_orom_version(struct ixgbe_hw *hw, |
121 | struct ixgbe_nvm_version *nvm_ver); |
122 | void ixgbe_disable_rx_generic(struct ixgbe_hw *hw); |
123 | void ixgbe_enable_rx_generic(struct ixgbe_hw *hw); |
124 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
125 | ixgbe_link_speed speed, |
126 | bool autoneg_wait_to_complete); |
127 | void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, |
128 | ixgbe_link_speed speed); |
129 | |
130 | #define IXGBE_FAILED_READ_RETRIES 5 |
131 | #define IXGBE_FAILED_READ_REG 0xffffffffU |
132 | #define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU |
133 | #define IXGBE_FAILED_READ_CFG_WORD 0xffffU |
134 | |
135 | u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg); |
136 | void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value); |
137 | |
138 | static inline bool ixgbe_removed(void __iomem *addr) |
139 | { |
140 | return unlikely(!addr); |
141 | } |
142 | |
143 | static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) |
144 | { |
145 | u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); |
146 | |
147 | if (ixgbe_removed(addr: reg_addr)) |
148 | return; |
149 | writel(val: value, addr: reg_addr + reg); |
150 | } |
151 | #define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value)) |
152 | |
153 | #ifndef writeq |
154 | #define writeq writeq |
155 | static inline void writeq(u64 val, void __iomem *addr) |
156 | { |
157 | writel((u32)val, addr); |
158 | writel((u32)(val >> 32), addr + 4); |
159 | } |
160 | #endif |
161 | |
162 | static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value) |
163 | { |
164 | u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); |
165 | |
166 | if (ixgbe_removed(addr: reg_addr)) |
167 | return; |
168 | writeq(val: value, addr: reg_addr + reg); |
169 | } |
170 | #define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value)) |
171 | |
172 | u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg); |
173 | #define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg)) |
174 | |
175 | #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \ |
176 | ixgbe_write_reg((a), (reg) + ((offset) << 2), (value)) |
177 | |
178 | #define IXGBE_READ_REG_ARRAY(a, reg, offset) \ |
179 | ixgbe_read_reg((a), (reg) + ((offset) << 2)) |
180 | |
181 | #define IXGBE_WRITE_FLUSH(a) ixgbe_read_reg((a), IXGBE_STATUS) |
182 | |
183 | #define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev) |
184 | |
185 | #define hw_dbg(hw, format, arg...) \ |
186 | netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg) |
187 | #define hw_err(hw, format, arg...) \ |
188 | netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg) |
189 | #define e_dev_info(format, arg...) \ |
190 | dev_info(&adapter->pdev->dev, format, ## arg) |
191 | #define e_dev_warn(format, arg...) \ |
192 | dev_warn(&adapter->pdev->dev, format, ## arg) |
193 | #define e_dev_err(format, arg...) \ |
194 | dev_err(&adapter->pdev->dev, format, ## arg) |
195 | #define e_dev_notice(format, arg...) \ |
196 | dev_notice(&adapter->pdev->dev, format, ## arg) |
197 | #define e_info(msglvl, format, arg...) \ |
198 | netif_info(adapter, msglvl, adapter->netdev, format, ## arg) |
199 | #define e_err(msglvl, format, arg...) \ |
200 | netif_err(adapter, msglvl, adapter->netdev, format, ## arg) |
201 | #define e_warn(msglvl, format, arg...) \ |
202 | netif_warn(adapter, msglvl, adapter->netdev, format, ## arg) |
203 | #define e_crit(msglvl, format, arg...) \ |
204 | netif_crit(adapter, msglvl, adapter->netdev, format, ## arg) |
205 | #endif /* IXGBE_COMMON */ |
206 | |