1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2024 Intel Corporation. */
3
4#ifndef _IXGBE_H_
5#define _IXGBE_H_
6
7#include <linux/bitops.h>
8#include <linux/types.h>
9#include <linux/pci.h>
10#include <linux/netdevice.h>
11#include <linux/cpumask.h>
12#include <linux/if_vlan.h>
13#include <linux/jiffies.h>
14#include <linux/phy.h>
15
16#include <linux/timecounter.h>
17#include <linux/net_tstamp.h>
18#include <linux/ptp_clock_kernel.h>
19
20#include <net/devlink.h>
21
22#include "ixgbe_type.h"
23#include "ixgbe_common.h"
24#include "ixgbe_dcb.h"
25#include "ixgbe_e610.h"
26#if IS_ENABLED(CONFIG_FCOE)
27#define IXGBE_FCOE
28#include "ixgbe_fcoe.h"
29#endif /* IS_ENABLED(CONFIG_FCOE) */
30#ifdef CONFIG_IXGBE_DCA
31#include <linux/dca.h>
32#endif
33#include "ixgbe_ipsec.h"
34
35#include <net/xdp.h>
36
37/* common prefix used by pr_<> macros */
38#undef pr_fmt
39#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40
41/* TX/RX descriptor defines */
42#define IXGBE_DEFAULT_TXD 512
43#define IXGBE_DEFAULT_TX_WORK 256
44#define IXGBE_MAX_TXD_82598 4096
45#define IXGBE_MAX_TXD_82599 8192
46#define IXGBE_MAX_TXD_X540 8192
47#define IXGBE_MAX_TXD_X550 32768
48#define IXGBE_MIN_TXD 64
49
50#if (PAGE_SIZE < 8192)
51#define IXGBE_DEFAULT_RXD 512
52#else
53#define IXGBE_DEFAULT_RXD 128
54#endif
55#define IXGBE_MAX_RXD_82598 4096
56#define IXGBE_MAX_RXD_82599 8192
57#define IXGBE_MAX_RXD_X540 8192
58#define IXGBE_MAX_RXD_X550 32768
59#define IXGBE_MIN_RXD 64
60
61/* flow control */
62#define IXGBE_MIN_FCRTL 0x40
63#define IXGBE_MAX_FCRTL 0x7FF80
64#define IXGBE_MIN_FCRTH 0x600
65#define IXGBE_MAX_FCRTH 0x7FFF0
66#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
67#define IXGBE_MIN_FCPAUSE 0
68#define IXGBE_MAX_FCPAUSE 0xFFFF
69
70/* Supported Rx Buffer Sizes */
71#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
72#define IXGBE_RXBUFFER_1536 1536
73#define IXGBE_RXBUFFER_2K 2048
74#define IXGBE_RXBUFFER_3K 3072
75#define IXGBE_RXBUFFER_4K 4096
76#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
77
78#define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
79
80/* Attempt to maximize the headroom available for incoming frames. We
81 * use a 2K buffer for receives and need 1536/1534 to store the data for
82 * the frame. This leaves us with 512 bytes of room. From that we need
83 * to deduct the space needed for the shared info and the padding needed
84 * to IP align the frame.
85 *
86 * Note: For cache line sizes 256 or larger this value is going to end
87 * up negative. In these cases we should fall back to the 3K
88 * buffers.
89 */
90#if (PAGE_SIZE < 8192)
91#define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN)
92#define IXGBE_2K_TOO_SMALL_WITH_PADDING \
93((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K))
94
95static inline int ixgbe_compute_pad(int rx_buf_len)
96{
97 int page_size, pad_size;
98
99 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
100 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
101
102 return pad_size;
103}
104
105static inline int ixgbe_skb_pad(void)
106{
107 int rx_buf_len;
108
109 /* If a 2K buffer cannot handle a standard Ethernet frame then
110 * optimize padding for a 3K buffer instead of a 1.5K buffer.
111 *
112 * For a 3K buffer we need to add enough padding to allow for
113 * tailroom due to NET_IP_ALIGN possibly shifting us out of
114 * cache-line alignment.
115 */
116 if (IXGBE_2K_TOO_SMALL_WITH_PADDING)
117 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN);
118 else
119 rx_buf_len = IXGBE_RXBUFFER_1536;
120
121 /* if needed make room for NET_IP_ALIGN */
122 rx_buf_len -= NET_IP_ALIGN;
123
124 return ixgbe_compute_pad(rx_buf_len);
125}
126
127#define IXGBE_SKB_PAD ixgbe_skb_pad()
128#else
129#define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
130#endif
131
132/*
133 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
134 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
135 * this adds up to 448 bytes of extra data.
136 *
137 * Since netdev_alloc_skb now allocates a page fragment we can use a value
138 * of 256 and the resultant skb will have a truesize of 960 or less.
139 */
140#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
141
142/* How many Rx Buffers do we bundle into one write to the hardware ? */
143#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
144
145#define IXGBE_RX_DMA_ATTR \
146 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
147
148enum ixgbe_tx_flags {
149 /* cmd_type flags */
150 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
151 IXGBE_TX_FLAGS_TSO = 0x02,
152 IXGBE_TX_FLAGS_TSTAMP = 0x04,
153
154 /* olinfo flags */
155 IXGBE_TX_FLAGS_CC = 0x08,
156 IXGBE_TX_FLAGS_IPV4 = 0x10,
157 IXGBE_TX_FLAGS_CSUM = 0x20,
158 IXGBE_TX_FLAGS_IPSEC = 0x40,
159
160 /* software defined flags */
161 IXGBE_TX_FLAGS_SW_VLAN = 0x80,
162 IXGBE_TX_FLAGS_FCOE = 0x100,
163};
164
165/* VLAN info */
166#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
167#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
168#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
169#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
170
171#define IXGBE_MAX_VF_MC_ENTRIES 30
172#define IXGBE_MAX_VF_FUNCTIONS 64
173#define IXGBE_MAX_VFTA_ENTRIES 128
174#define MAX_EMULATION_MAC_ADDRS 16
175#define IXGBE_MAX_PF_MACVLANS 15
176#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
177#define IXGBE_82599_VF_DEVICE_ID 0x10ED
178#define IXGBE_X540_VF_DEVICE_ID 0x1515
179#define IXGBE_E610_VF_DEVICE_ID 0x57AD
180
181#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
182 { \
183 u32 current_counter = IXGBE_READ_REG(hw, reg); \
184 if (current_counter < last_counter) \
185 counter += 0x100000000LL; \
186 last_counter = current_counter; \
187 counter &= 0xFFFFFFFF00000000LL; \
188 counter |= current_counter; \
189 }
190
191#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
192 { \
193 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
194 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
195 u64 current_counter = (current_counter_msb << 32) | \
196 current_counter_lsb; \
197 if (current_counter < last_counter) \
198 counter += 0x1000000000LL; \
199 last_counter = current_counter; \
200 counter &= 0xFFFFFFF000000000LL; \
201 counter |= current_counter; \
202 }
203
204struct vf_stats {
205 u64 gprc;
206 u64 gorc;
207 u64 gptc;
208 u64 gotc;
209 u64 mprc;
210};
211
212struct vf_data_storage {
213 struct pci_dev *vfdev;
214 unsigned char vf_mac_addresses[ETH_ALEN];
215 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
216 u16 num_vf_mc_hashes;
217 bool clear_to_send;
218 struct vf_stats vfstats;
219 struct vf_stats last_vfstats;
220 struct vf_stats saved_rst_vfstats;
221 bool pf_set_mac;
222 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
223 u16 pf_qos;
224 u16 tx_rate;
225 int link_enable;
226 int link_state;
227 u8 spoofchk_enabled;
228 bool rss_query_enabled;
229 u8 trusted;
230 int xcast_mode;
231 unsigned int vf_api;
232 u8 primary_abort_count;
233};
234
235enum ixgbevf_xcast_modes {
236 IXGBEVF_XCAST_MODE_NONE = 0,
237 IXGBEVF_XCAST_MODE_MULTI,
238 IXGBEVF_XCAST_MODE_ALLMULTI,
239 IXGBEVF_XCAST_MODE_PROMISC,
240};
241
242struct vf_macvlans {
243 struct list_head l;
244 int vf;
245 bool free;
246 bool is_macvlan;
247 u8 vf_macvlan[ETH_ALEN];
248};
249
250#define IXGBE_MAX_TXD_PWR 14
251#define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
252
253/* Tx Descriptors needed, worst case */
254#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
255#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
256
257/* wrapper around a pointer to a socket buffer,
258 * so a DMA handle can be stored along with the buffer */
259struct ixgbe_tx_buffer {
260 union ixgbe_adv_tx_desc *next_to_watch;
261 unsigned long time_stamp;
262 union {
263 struct sk_buff *skb;
264 struct xdp_frame *xdpf;
265 };
266 unsigned int bytecount;
267 unsigned short gso_segs;
268 __be16 protocol;
269 DEFINE_DMA_UNMAP_ADDR(dma);
270 DEFINE_DMA_UNMAP_LEN(len);
271 u32 tx_flags;
272};
273
274struct ixgbe_rx_buffer {
275 union {
276 struct {
277 struct sk_buff *skb;
278 dma_addr_t dma;
279 struct page *page;
280 __u32 page_offset;
281 __u16 pagecnt_bias;
282 };
283 struct {
284 bool discard;
285 struct xdp_buff *xdp;
286 };
287 };
288};
289
290struct ixgbe_queue_stats {
291 u64 packets;
292 u64 bytes;
293};
294
295struct ixgbe_tx_queue_stats {
296 u64 restart_queue;
297 u64 tx_busy;
298 u64 tx_done_old;
299};
300
301struct ixgbe_rx_queue_stats {
302 u64 rsc_count;
303 u64 rsc_flush;
304 u64 non_eop_descs;
305 u64 alloc_rx_page;
306 u64 alloc_rx_page_failed;
307 u64 alloc_rx_buff_failed;
308 u64 csum_err;
309};
310
311#define IXGBE_TS_HDR_LEN 8
312
313enum ixgbe_ring_state_t {
314 __IXGBE_RX_3K_BUFFER,
315 __IXGBE_RX_BUILD_SKB_ENABLED,
316 __IXGBE_RX_RSC_ENABLED,
317 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
318 __IXGBE_RX_FCOE,
319 __IXGBE_TX_FDIR_INIT_DONE,
320 __IXGBE_TX_XPS_INIT_DONE,
321 __IXGBE_TX_DETECT_HANG,
322 __IXGBE_HANG_CHECK_ARMED,
323 __IXGBE_TX_XDP_RING,
324 __IXGBE_TX_DISABLED,
325};
326
327#define ring_uses_build_skb(ring) \
328 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state)
329
330struct ixgbe_fwd_adapter {
331 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
332 struct net_device *netdev;
333 unsigned int tx_base_queue;
334 unsigned int rx_base_queue;
335 int pool;
336};
337
338#define check_for_tx_hang(ring) \
339 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
340#define set_check_for_tx_hang(ring) \
341 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
342#define clear_check_for_tx_hang(ring) \
343 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
344#define ring_is_rsc_enabled(ring) \
345 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
346#define set_ring_rsc_enabled(ring) \
347 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
348#define clear_ring_rsc_enabled(ring) \
349 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
350#define ring_is_xdp(ring) \
351 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
352#define set_ring_xdp(ring) \
353 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
354#define clear_ring_xdp(ring) \
355 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
356struct ixgbe_ring {
357 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
358 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
359 struct net_device *netdev; /* netdev ring belongs to */
360 struct bpf_prog *xdp_prog;
361 struct device *dev; /* device for DMA mapping */
362 void *desc; /* descriptor ring memory */
363 union {
364 struct ixgbe_tx_buffer *tx_buffer_info;
365 struct ixgbe_rx_buffer *rx_buffer_info;
366 };
367 unsigned long state;
368 u8 __iomem *tail;
369 dma_addr_t dma; /* phys. address of descriptor ring */
370 unsigned int size; /* length in bytes */
371
372 u16 count; /* amount of descriptors */
373
374 u8 queue_index; /* needed for multiqueue queue management */
375 u8 reg_idx; /* holds the special value that gets
376 * the hardware register offset
377 * associated with this ring, which is
378 * different for DCB and RSS modes
379 */
380 u16 next_to_use;
381 u16 next_to_clean;
382
383 unsigned long last_rx_timestamp;
384
385 union {
386 u16 next_to_alloc;
387 struct {
388 u8 atr_sample_rate;
389 u8 atr_count;
390 };
391 };
392
393 u8 dcb_tc;
394 struct ixgbe_queue_stats stats;
395 struct u64_stats_sync syncp;
396 union {
397 struct ixgbe_tx_queue_stats tx_stats;
398 struct ixgbe_rx_queue_stats rx_stats;
399 };
400 u16 rx_offset;
401 struct xdp_rxq_info xdp_rxq;
402 spinlock_t tx_lock; /* used in XDP mode */
403 struct xsk_buff_pool *xsk_pool;
404 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */
405 u16 rx_buf_len;
406} ____cacheline_internodealigned_in_smp;
407
408enum ixgbe_ring_f_enum {
409 RING_F_NONE = 0,
410 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
411 RING_F_RSS,
412 RING_F_FDIR,
413#ifdef IXGBE_FCOE
414 RING_F_FCOE,
415#endif /* IXGBE_FCOE */
416
417 RING_F_ARRAY_SIZE /* must be last in enum set */
418};
419
420#define IXGBE_MAX_RSS_INDICES 16
421#define IXGBE_MAX_RSS_INDICES_X550 63
422#define IXGBE_MAX_VMDQ_INDICES 64
423#define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
424#define IXGBE_MAX_FCOE_INDICES 8
425#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
426#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
427#define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1)
428#define IXGBE_MAX_L2A_QUEUES 4
429#define IXGBE_BAD_L2A_QUEUE 3
430#define IXGBE_MAX_MACVLANS 63
431
432DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key);
433
434struct ixgbe_ring_feature {
435 u16 limit; /* upper limit on feature indices */
436 u16 indices; /* current value of indices */
437 u16 mask; /* Mask used for feature to ring mapping */
438 u16 offset; /* offset to start of feature */
439} ____cacheline_internodealigned_in_smp;
440
441#define IXGBE_82599_VMDQ_8Q_MASK 0x78
442#define IXGBE_82599_VMDQ_4Q_MASK 0x7C
443#define IXGBE_82599_VMDQ_2Q_MASK 0x7E
444
445/*
446 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
447 * this is twice the size of a half page we need to double the page order
448 * for FCoE enabled Rx queues.
449 */
450static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
451{
452 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
453 return IXGBE_RXBUFFER_3K;
454#if (PAGE_SIZE < 8192)
455 if (ring_uses_build_skb(ring))
456 return IXGBE_MAX_2K_FRAME_BUILD_SKB;
457#endif
458 return IXGBE_RXBUFFER_2K;
459}
460
461static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
462{
463#if (PAGE_SIZE < 8192)
464 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
465 return 1;
466#endif
467 return 0;
468}
469#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
470
471#define IXGBE_ITR_ADAPTIVE_MIN_INC 2
472#define IXGBE_ITR_ADAPTIVE_MIN_USECS 10
473#define IXGBE_ITR_ADAPTIVE_MAX_USECS 126
474#define IXGBE_ITR_ADAPTIVE_LATENCY 0x80
475#define IXGBE_ITR_ADAPTIVE_BULK 0x00
476
477struct ixgbe_ring_container {
478 struct ixgbe_ring *ring; /* pointer to linked list of rings */
479 unsigned long next_update; /* jiffies value of last update */
480 unsigned int total_bytes; /* total bytes processed this int */
481 unsigned int total_packets; /* total packets processed this int */
482 u16 work_limit; /* total work allowed per interrupt */
483 u8 count; /* total number of rings in vector */
484 u8 itr; /* current ITR setting for ring */
485};
486
487/* iterator for handling rings in ring container */
488#define ixgbe_for_each_ring(pos, head) \
489 for (pos = (head).ring; pos != NULL; pos = pos->next)
490
491#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
492 ? 8 : 1)
493#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
494
495/* MAX_Q_VECTORS of these are allocated,
496 * but we only use one per queue-specific vector.
497 */
498struct ixgbe_q_vector {
499 struct ixgbe_adapter *adapter;
500#ifdef CONFIG_IXGBE_DCA
501 int cpu; /* CPU for DCA */
502#endif
503 u16 v_idx; /* index of q_vector within array, also used for
504 * finding the bit in EICR and friends that
505 * represents the vector for this ring */
506 u16 itr; /* Interrupt throttle rate written to EITR */
507 struct ixgbe_ring_container rx, tx;
508
509 struct napi_struct napi;
510 cpumask_t affinity_mask;
511 int numa_node;
512 struct rcu_head rcu; /* to avoid race with update stats on free */
513 char name[IFNAMSIZ + 9];
514
515 /* for dynamic allocation of rings associated with this q_vector */
516 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp;
517};
518
519#ifdef CONFIG_IXGBE_HWMON
520
521#define IXGBE_HWMON_TYPE_LOC 0
522#define IXGBE_HWMON_TYPE_TEMP 1
523#define IXGBE_HWMON_TYPE_CAUTION 2
524#define IXGBE_HWMON_TYPE_MAX 3
525
526struct hwmon_attr {
527 struct device_attribute dev_attr;
528 struct ixgbe_hw *hw;
529 struct ixgbe_thermal_diode_data *sensor;
530 char name[12];
531};
532
533struct hwmon_buff {
534 struct attribute_group group;
535 const struct attribute_group *groups[2];
536 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
537 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
538 unsigned int n_hwmon;
539};
540#endif /* CONFIG_IXGBE_HWMON */
541
542/*
543 * microsecond values for various ITR rates shifted by 2 to fit itr register
544 * with the first 3 bits reserved 0
545 */
546#define IXGBE_MIN_RSC_ITR 24
547#define IXGBE_100K_ITR 40
548#define IXGBE_20K_ITR 200
549#define IXGBE_12K_ITR 336
550
551/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
552static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
553 const u32 stat_err_bits)
554{
555 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
556}
557
558static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
559{
560 u16 ntc = ring->next_to_clean;
561 u16 ntu = ring->next_to_use;
562
563 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
564}
565
566#define IXGBE_RX_DESC(R, i) \
567 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
568#define IXGBE_TX_DESC(R, i) \
569 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
570#define IXGBE_TX_CTXTDESC(R, i) \
571 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
572
573#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
574#ifdef IXGBE_FCOE
575/* Use 3K as the baby jumbo frame size for FCoE */
576#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
577#endif /* IXGBE_FCOE */
578
579#define OTHER_VECTOR 1
580#define NON_Q_VECTORS (OTHER_VECTOR)
581
582#define MAX_MSIX_VECTORS_82599 64
583#define MAX_Q_VECTORS_82599 64
584#define MAX_MSIX_VECTORS_82598 18
585#define MAX_Q_VECTORS_82598 16
586
587struct ixgbe_mac_addr {
588 u8 addr[ETH_ALEN];
589 u16 pool;
590 u16 state; /* bitmask */
591};
592
593#define IXGBE_MAC_STATE_DEFAULT 0x1
594#define IXGBE_MAC_STATE_MODIFIED 0x2
595#define IXGBE_MAC_STATE_IN_USE 0x4
596
597#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
598#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
599
600#define MIN_MSIX_Q_VECTORS 1
601#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
602
603/* default to trying for four seconds */
604#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
605#define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
606
607#define IXGBE_PRIMARY_ABORT_LIMIT 5
608
609/* board specific private data structure */
610struct ixgbe_adapter {
611 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
612 /* OS defined structs */
613 struct net_device *netdev;
614 struct bpf_prog *xdp_prog;
615 struct pci_dev *pdev;
616 struct mii_bus *mii_bus;
617 struct devlink *devlink;
618 struct devlink_port devlink_port;
619 struct devlink_region *nvm_region;
620 struct devlink_region *sram_region;
621 struct devlink_region *devcaps_region;
622
623 unsigned long state;
624
625 /* Some features need tri-state capability,
626 * thus the additional *_CAPABLE flags.
627 */
628 u32 flags;
629#define IXGBE_FLAG_MSI_ENABLED BIT(1)
630#define IXGBE_FLAG_MSIX_ENABLED BIT(3)
631#define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
632#define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
633#define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
634#define IXGBE_FLAG_DCA_ENABLED BIT(8)
635#define IXGBE_FLAG_DCA_CAPABLE BIT(9)
636#define IXGBE_FLAG_IMIR_ENABLED BIT(10)
637#define IXGBE_FLAG_MQ_CAPABLE BIT(11)
638#define IXGBE_FLAG_DCB_ENABLED BIT(12)
639#define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
640#define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
641#define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
642#define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
643#define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
644#define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
645#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
646#define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
647#define IXGBE_FLAG_FCOE_ENABLED BIT(21)
648#define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
649#define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
650#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
651#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
652#define IXGBE_FLAG_DCB_CAPABLE BIT(27)
653
654 u32 flags2;
655#define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
656#define IXGBE_FLAG2_RSC_ENABLED BIT(1)
657#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
658#define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
659#define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
660#define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
661#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
662#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
663#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
664#define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
665#define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
666#define IXGBE_FLAG2_FW_ASYNC_EVENT BIT(12)
667#define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
668#define IXGBE_FLAG2_EEE_CAPABLE BIT(14)
669#define IXGBE_FLAG2_EEE_ENABLED BIT(15)
670#define IXGBE_FLAG2_RX_LEGACY BIT(16)
671#define IXGBE_FLAG2_IPSEC_ENABLED BIT(17)
672#define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18)
673#define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19)
674#define IXGBE_FLAG2_PHY_FW_LOAD_FAILED BIT(20)
675#define IXGBE_FLAG2_NO_MEDIA BIT(21)
676#define IXGBE_FLAG2_MOD_POWER_UNSUPPORTED BIT(22)
677#define IXGBE_FLAG2_API_MISMATCH BIT(23)
678#define IXGBE_FLAG2_FW_ROLLBACK BIT(24)
679
680 /* Tx fast path data */
681 int num_tx_queues;
682 u16 tx_itr_setting;
683 u16 tx_work_limit;
684 u64 tx_ipsec;
685
686 /* Rx fast path data */
687 int num_rx_queues;
688 u16 rx_itr_setting;
689 u64 rx_ipsec;
690
691 /* Port number used to identify VXLAN traffic */
692 __be16 vxlan_port;
693 __be16 geneve_port;
694
695 /* XDP */
696 int num_xdp_queues;
697 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS];
698 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */
699
700 /* TX */
701 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
702
703 u64 restart_queue;
704 u64 lsc_int;
705 u32 tx_timeout_count;
706
707 /* RX */
708 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
709 int num_rx_pools; /* == num_rx_queues in 82598 */
710 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
711 u64 hw_csum_rx_error;
712 u64 hw_rx_no_dma_resources;
713 u64 rsc_total_count;
714 u64 rsc_total_flush;
715 u64 non_eop_descs;
716 u32 alloc_rx_page;
717 u32 alloc_rx_page_failed;
718 u32 alloc_rx_buff_failed;
719
720 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
721
722 /* DCB parameters */
723 struct ieee_pfc *ixgbe_ieee_pfc;
724 struct ieee_ets *ixgbe_ieee_ets;
725 struct ixgbe_dcb_config dcb_cfg;
726 struct ixgbe_dcb_config temp_dcb_cfg;
727 u8 hw_tcs;
728 u8 dcb_set_bitmap;
729 u8 dcbx_cap;
730 enum ixgbe_fc_mode last_lfc_mode;
731
732 int num_q_vectors; /* current number of q_vectors for device */
733 int max_q_vectors; /* true count of q_vectors for device */
734 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
735 struct msix_entry *msix_entries;
736
737 u32 test_icr;
738 struct ixgbe_ring test_tx_ring;
739 struct ixgbe_ring test_rx_ring;
740
741 /* structs defined in ixgbe_hw.h */
742 struct ixgbe_hw hw;
743 u16 msg_enable;
744 struct ixgbe_hw_stats stats;
745
746 u64 tx_busy;
747 unsigned int tx_ring_count;
748 unsigned int xdp_ring_count;
749 unsigned int rx_ring_count;
750
751 u32 link_speed;
752 bool link_up;
753 unsigned long sfp_poll_time;
754 unsigned long link_check_timeout;
755
756 struct timer_list service_timer;
757 struct work_struct service_task;
758
759 struct hlist_head fdir_filter_list;
760 unsigned long fdir_overflow; /* number of times ATR was backed off */
761 union ixgbe_atr_input fdir_mask;
762 int fdir_filter_count;
763 u32 fdir_pballoc;
764 u32 atr_sample_rate;
765 spinlock_t fdir_perfect_lock;
766
767 bool fw_emp_reset_disabled;
768
769#ifdef IXGBE_FCOE
770 struct ixgbe_fcoe fcoe;
771#endif /* IXGBE_FCOE */
772 u8 __iomem *io_addr; /* Mainly for iounmap use */
773 u32 wol;
774
775 u16 bridge_mode;
776
777 char eeprom_id[NVM_VER_SIZE];
778 u16 eeprom_cap;
779
780 u32 interrupt_event;
781 u32 led_reg;
782
783 struct ptp_clock *ptp_clock;
784 struct ptp_clock_info ptp_caps;
785 struct work_struct ptp_tx_work;
786 struct sk_buff *ptp_tx_skb;
787 struct hwtstamp_config tstamp_config;
788 unsigned long ptp_tx_start;
789 unsigned long last_overflow_check;
790 unsigned long last_rx_ptp_check;
791 unsigned long last_rx_timestamp;
792 spinlock_t tmreg_lock;
793 struct cyclecounter hw_cc;
794 struct timecounter hw_tc;
795 u32 base_incval;
796 u32 tx_hwtstamp_timeouts;
797 u32 tx_hwtstamp_skipped;
798 u32 rx_hwtstamp_cleared;
799 void (*ptp_setup_sdp)(struct ixgbe_adapter *);
800
801 /* SR-IOV */
802 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
803 unsigned int num_vfs;
804 struct vf_data_storage *vfinfo;
805 int vf_rate_link_speed;
806 struct vf_macvlans vf_mvs;
807 struct vf_macvlans *mv_list;
808
809 u32 timer_event_accumulator;
810 u32 vferr_refcount;
811 struct ixgbe_mac_addr *mac_table;
812 struct kobject *info_kobj;
813 u16 lse_mask;
814#ifdef CONFIG_IXGBE_HWMON
815 struct hwmon_buff *ixgbe_hwmon_buff;
816#endif /* CONFIG_IXGBE_HWMON */
817#ifdef CONFIG_DEBUG_FS
818 struct dentry *ixgbe_dbg_adapter;
819#endif /*CONFIG_DEBUG_FS*/
820
821 u8 default_up;
822 /* Bitmask indicating in use pools */
823 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1);
824
825#define IXGBE_MAX_LINK_HANDLE 10
826 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
827 unsigned long tables;
828
829/* maximum number of RETA entries among all devices supported by ixgbe
830 * driver: currently it's x550 device in non-SRIOV mode
831 */
832#define IXGBE_MAX_RETA_ENTRIES 512
833 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
834
835#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
836 u32 *rss_key;
837
838#ifdef CONFIG_IXGBE_IPSEC
839 struct ixgbe_ipsec *ipsec;
840#endif /* CONFIG_IXGBE_IPSEC */
841 spinlock_t vfs_lock;
842};
843
844struct ixgbe_netdevice_priv {
845 struct ixgbe_adapter *adapter;
846};
847
848static inline struct ixgbe_adapter *ixgbe_from_netdev(struct net_device *netdev)
849{
850 struct ixgbe_netdevice_priv *priv = netdev_priv(dev: netdev);
851
852 return priv->adapter;
853}
854
855static inline int ixgbe_determine_xdp_q_idx(int cpu)
856{
857 if (static_key_enabled(&ixgbe_xdp_locking_key))
858 return cpu % IXGBE_MAX_XDP_QS;
859 else
860 return cpu;
861}
862
863static inline
864struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter)
865{
866 int index = ixgbe_determine_xdp_q_idx(smp_processor_id());
867
868 return adapter->xdp_ring[index];
869}
870
871static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
872{
873 switch (adapter->hw.mac.type) {
874 case ixgbe_mac_82598EB:
875 case ixgbe_mac_82599EB:
876 case ixgbe_mac_X540:
877 return IXGBE_MAX_RSS_INDICES;
878 case ixgbe_mac_X550:
879 case ixgbe_mac_X550EM_x:
880 case ixgbe_mac_x550em_a:
881 case ixgbe_mac_e610:
882 return IXGBE_MAX_RSS_INDICES_X550;
883 default:
884 return 0;
885 }
886}
887
888struct ixgbe_fdir_filter {
889 struct hlist_node fdir_node;
890 union ixgbe_atr_input filter;
891 u16 sw_idx;
892 u64 action;
893};
894
895enum ixgbe_state_t {
896 __IXGBE_TESTING,
897 __IXGBE_RESETTING,
898 __IXGBE_DOWN,
899 __IXGBE_DISABLED,
900 __IXGBE_REMOVING,
901 __IXGBE_SERVICE_SCHED,
902 __IXGBE_SERVICE_INITED,
903 __IXGBE_IN_SFP_INIT,
904 __IXGBE_PTP_RUNNING,
905 __IXGBE_PTP_TX_IN_PROGRESS,
906 __IXGBE_RESET_REQUESTED,
907 __IXGBE_PHY_INIT_COMPLETE,
908};
909
910struct ixgbe_cb {
911 union { /* Union defining head/tail partner */
912 struct sk_buff *head;
913 struct sk_buff *tail;
914 };
915 dma_addr_t dma;
916 u16 append_cnt;
917 bool page_released;
918};
919#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
920
921enum ixgbe_boards {
922 board_82598,
923 board_82599,
924 board_X540,
925 board_X550,
926 board_X550EM_x,
927 board_x550em_x_fw,
928 board_x550em_a,
929 board_x550em_a_fw,
930 board_e610,
931};
932
933extern const struct ixgbe_info ixgbe_82598_info;
934extern const struct ixgbe_info ixgbe_82599_info;
935extern const struct ixgbe_info ixgbe_X540_info;
936extern const struct ixgbe_info ixgbe_X550_info;
937extern const struct ixgbe_info ixgbe_X550EM_x_info;
938extern const struct ixgbe_info ixgbe_x550em_x_fw_info;
939extern const struct ixgbe_info ixgbe_x550em_a_info;
940extern const struct ixgbe_info ixgbe_x550em_a_fw_info;
941extern const struct ixgbe_info ixgbe_e610_info;
942#ifdef CONFIG_IXGBE_DCB
943extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops;
944#endif
945
946extern char ixgbe_driver_name[];
947#ifdef IXGBE_FCOE
948extern char ixgbe_default_device_descr[];
949#endif /* IXGBE_FCOE */
950
951int ixgbe_open(struct net_device *netdev);
952int ixgbe_close(struct net_device *netdev);
953void ixgbe_up(struct ixgbe_adapter *adapter);
954void ixgbe_down(struct ixgbe_adapter *adapter);
955void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
956void ixgbe_reset(struct ixgbe_adapter *adapter);
957void ixgbe_set_ethtool_ops(struct net_device *netdev);
958int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
959int ixgbe_setup_tx_resources(struct ixgbe_ring *);
960void ixgbe_free_rx_resources(struct ixgbe_ring *);
961void ixgbe_free_tx_resources(struct ixgbe_ring *);
962void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
963void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
964void ixgbe_disable_rx(struct ixgbe_adapter *adapter);
965void ixgbe_disable_tx(struct ixgbe_adapter *adapter);
966void ixgbe_update_stats(struct ixgbe_adapter *adapter);
967int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
968bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
969 u16 subdevice_id);
970void ixgbe_set_fw_version_e610(struct ixgbe_adapter *adapter);
971void ixgbe_refresh_fw_version(struct ixgbe_adapter *adapter);
972#ifdef CONFIG_PCI_IOV
973void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
974#endif
975int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
976 const u8 *addr, u16 queue);
977int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
978 const u8 *addr, u16 queue);
979void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
980void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
981netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
982 struct ixgbe_ring *);
983void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
984void ixgbe_write_eitr(struct ixgbe_q_vector *);
985int ixgbe_poll(struct napi_struct *napi, int budget);
986int ethtool_ioctl(struct ifreq *ifr);
987int ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
988int ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
989int ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
990int ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
991 union ixgbe_atr_hash_dword input,
992 union ixgbe_atr_hash_dword common,
993 u8 queue);
994int ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
995 union ixgbe_atr_input *input_mask);
996int ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
997 union ixgbe_atr_input *input,
998 u16 soft_id, u8 queue);
999int ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1000 union ixgbe_atr_input *input,
1001 u16 soft_id);
1002void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1003 union ixgbe_atr_input *mask);
1004int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
1005 struct ixgbe_fdir_filter *input,
1006 u16 sw_idx);
1007void ixgbe_set_rx_mode(struct net_device *netdev);
1008#ifdef CONFIG_IXGBE_DCB
1009void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
1010#endif
1011int ixgbe_setup_tc(struct net_device *dev, u8 tc);
1012void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
1013void ixgbe_do_reset(struct net_device *netdev);
1014#ifdef CONFIG_IXGBE_HWMON
1015void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
1016int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
1017#endif /* CONFIG_IXGBE_HWMON */
1018#ifdef IXGBE_FCOE
1019void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
1020int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
1021 u8 *hdr_len);
1022int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
1023 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
1024int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
1025 struct scatterlist *sgl, unsigned int sgc);
1026int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
1027 struct scatterlist *sgl, unsigned int sgc);
1028int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
1029int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
1030void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
1031int ixgbe_fcoe_enable(struct net_device *netdev);
1032int ixgbe_fcoe_disable(struct net_device *netdev);
1033int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
1034int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
1035 struct netdev_fcoe_hbainfo *info);
1036u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
1037#endif /* IXGBE_FCOE */
1038#ifdef CONFIG_DEBUG_FS
1039void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
1040void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
1041void ixgbe_dbg_init(void);
1042void ixgbe_dbg_exit(void);
1043#else
1044static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
1045static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
1046static inline void ixgbe_dbg_init(void) {}
1047static inline void ixgbe_dbg_exit(void) {}
1048#endif /* CONFIG_DEBUG_FS */
1049static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
1050{
1051 return netdev_get_tx_queue(dev: ring->netdev, index: ring->queue_index);
1052}
1053
1054void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
1055void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
1056void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
1057void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
1058void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
1059void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter);
1060void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
1061void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
1062static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
1063 union ixgbe_adv_rx_desc *rx_desc,
1064 struct sk_buff *skb)
1065{
1066 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
1067 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
1068 return;
1069 }
1070
1071 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1072 return;
1073
1074 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
1075
1076 /* Update the last_rx_timestamp timer in order to enable watchdog check
1077 * for error case of latched timestamp on a dropped packet.
1078 */
1079 rx_ring->last_rx_timestamp = jiffies;
1080}
1081
1082int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1083int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1084void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
1085void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
1086void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
1087#ifdef CONFIG_PCI_IOV
1088void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
1089#endif
1090
1091netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
1092 struct ixgbe_adapter *adapter,
1093 struct ixgbe_ring *tx_ring);
1094u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
1095void ixgbe_store_key(struct ixgbe_adapter *adapter);
1096void ixgbe_store_reta(struct ixgbe_adapter *adapter);
1097int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1098 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
1099#ifdef CONFIG_IXGBE_IPSEC
1100void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
1101void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter);
1102void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter);
1103void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1104 union ixgbe_adv_rx_desc *rx_desc,
1105 struct sk_buff *skb);
1106int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
1107 struct ixgbe_ipsec_tx_data *itd);
1108void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf);
1109int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1110int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1111#else
1112static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { }
1113static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { }
1114static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { }
1115static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1116 union ixgbe_adv_rx_desc *rx_desc,
1117 struct sk_buff *skb) { }
1118static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring,
1119 struct ixgbe_tx_buffer *first,
1120 struct ixgbe_ipsec_tx_data *itd) { return 0; }
1121static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter,
1122 u32 vf) { }
1123static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter,
1124 u32 *mbuf, u32 vf) { return -EACCES; }
1125static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter,
1126 u32 *mbuf, u32 vf) { return -EACCES; }
1127#endif /* CONFIG_IXGBE_IPSEC */
1128
1129static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter)
1130{
1131 return !!adapter->xdp_prog;
1132}
1133
1134#endif /* _IXGBE_H_ */
1135

Provided by KDAB

Privacy Policy
Improve your Profiling and Debugging skills
Find out more

source code of linux/drivers/net/ethernet/intel/ixgbe/ixgbe.h