1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 */
5
6#ifndef AM65_CPSW_NUSS_H_
7#define AM65_CPSW_NUSS_H_
8
9#include <linux/if_ether.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
13#include <linux/phylink.h>
14#include <linux/platform_device.h>
15#include <linux/soc/ti/k3-ringacc.h>
16#include <net/devlink.h>
17#include <net/xdp.h>
18#include "am65-cpsw-qos.h"
19
20struct am65_cpts;
21
22#define HOST_PORT_NUM 0
23
24#define AM65_CPSW_MAX_QUEUES 8 /* both TX & RX */
25
26#define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014
27
28struct am65_cpsw_slave_data {
29 bool mac_only;
30 struct cpsw_sl *mac_sl;
31 struct device_node *port_np;
32 phy_interface_t phy_if;
33 struct phy *ifphy;
34 struct phy *serdes_phy;
35 bool rx_pause;
36 bool tx_pause;
37 u8 mac_addr[ETH_ALEN];
38 int port_vlan;
39 struct phylink *phylink;
40 struct phylink_config phylink_config;
41};
42
43struct am65_cpsw_port {
44 struct am65_cpsw_common *common;
45 struct net_device *ndev;
46 const char *name;
47 u32 port_id;
48 void __iomem *port_base;
49 void __iomem *sgmii_base;
50 void __iomem *stat_base;
51 void __iomem *fetch_ram_base;
52 bool disabled;
53 struct am65_cpsw_slave_data slave;
54 bool tx_ts_enabled;
55 bool rx_ts_enabled;
56 struct am65_cpsw_qos qos;
57 struct devlink_port devlink_port;
58 struct bpf_prog *xdp_prog;
59 struct xdp_rxq_info xdp_rxq[AM65_CPSW_MAX_QUEUES];
60 /* Only for suspend resume context */
61 u32 vid_context;
62};
63
64enum am65_cpsw_tx_buf_type {
65 AM65_CPSW_TX_BUF_TYPE_SKB,
66 AM65_CPSW_TX_BUF_TYPE_XDP_TX,
67 AM65_CPSW_TX_BUF_TYPE_XDP_NDO,
68};
69
70struct am65_cpsw_host {
71 struct am65_cpsw_common *common;
72 void __iomem *port_base;
73 void __iomem *stat_base;
74 /* Only for suspend resume context */
75 u32 vid_context;
76};
77
78struct am65_cpsw_tx_chn {
79 struct device *dma_dev;
80 struct napi_struct napi_tx;
81 struct am65_cpsw_common *common;
82 struct k3_cppi_desc_pool *desc_pool;
83 struct k3_udma_glue_tx_channel *tx_chn;
84 spinlock_t lock; /* protect TX rings in multi-port mode */
85 struct hrtimer tx_hrtimer;
86 unsigned long tx_pace_timeout;
87 int irq;
88 u32 id;
89 u32 descs_num;
90 unsigned char dsize_log2;
91 char tx_chn_name[128];
92 u32 rate_mbps;
93};
94
95struct am65_cpsw_rx_flow {
96 u32 id;
97 struct napi_struct napi_rx;
98 struct am65_cpsw_common *common;
99 int irq;
100 bool irq_disabled;
101 struct hrtimer rx_hrtimer;
102 unsigned long rx_pace_timeout;
103 struct page_pool *page_pool;
104 char name[32];
105};
106
107struct am65_cpsw_tx_swdata {
108 struct net_device *ndev;
109 union {
110 struct sk_buff *skb;
111 struct xdp_frame *xdpf;
112 };
113};
114
115struct am65_cpsw_swdata {
116 u32 flow_id;
117 struct page *page;
118};
119
120struct am65_cpsw_rx_chn {
121 struct device *dev;
122 struct device *dma_dev;
123 struct k3_cppi_desc_pool *desc_pool;
124 struct k3_udma_glue_rx_channel *rx_chn;
125 u32 descs_num;
126 unsigned char dsize_log2;
127 struct am65_cpsw_rx_flow flows[AM65_CPSW_MAX_QUEUES];
128};
129
130#define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
131#define AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ BIT(1)
132
133struct am65_cpsw_pdata {
134 u32 quirks;
135 u64 extra_modes;
136 enum k3_ring_mode fdqring_mode;
137 const char *ale_dev_id;
138};
139
140enum cpsw_devlink_param_id {
141 AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
142 AM65_CPSW_DL_PARAM_SWITCH_MODE,
143};
144
145struct am65_cpsw_devlink {
146 struct am65_cpsw_common *common;
147};
148
149struct am65_cpsw_common {
150 struct device *dev;
151 struct device *mdio_dev;
152 struct am65_cpsw_pdata pdata;
153
154 void __iomem *ss_base;
155 void __iomem *cpsw_base;
156
157 u32 port_num;
158 struct am65_cpsw_host host;
159 struct am65_cpsw_port *ports;
160 u32 disabled_ports_mask;
161 struct net_device *dma_ndev;
162
163 int usage_count; /* number of opened ports */
164 struct cpsw_ale *ale;
165 int tx_ch_num;
166 u32 tx_ch_rate_msk;
167 u32 rx_flow_id_base;
168
169 struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_QUEUES];
170 struct completion tdown_complete;
171 atomic_t tdown_cnt;
172
173 int rx_ch_num_flows;
174 struct am65_cpsw_rx_chn rx_chns;
175
176 u32 nuss_ver;
177 u32 cpsw_ver;
178 unsigned long bus_freq;
179 bool pf_p0_rx_ptype_rrobin;
180 struct am65_cpts *cpts;
181 int est_enabled;
182 bool iet_enabled;
183
184 bool is_emac_mode;
185 u16 br_members;
186 int default_vlan;
187 struct devlink *devlink;
188 struct net_device *hw_bridge_dev;
189 struct notifier_block am65_cpsw_netdevice_nb;
190 unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
191 /* only for suspend/resume context restore */
192 u32 *ale_context;
193};
194
195struct am65_cpsw_ndev_priv {
196 u32 msg_enable;
197 struct am65_cpsw_port *port;
198 bool offload_fwd_mark;
199 /* Serialize access to MAC Merge state between ethtool requests
200 * and link state updates
201 */
202 struct mutex mm_lock;
203};
204
205#define am65_ndev_to_priv(ndev) \
206 ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
207#define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
208#define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
209#define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
210
211#define am65_common_get_host(common) (&(common)->host)
212#define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
213
214#define am65_cpsw_napi_to_rx_flow(pnapi) \
215 container_of(pnapi, struct am65_cpsw_rx_flow, napi_rx)
216#define am65_cpsw_napi_to_tx_chn(pnapi) \
217 container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
218
219#define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
220
221#define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
222
223extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
224
225void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
226int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common,
227 int num_tx, int num_rx);
228
229bool am65_cpsw_port_dev_check(const struct net_device *dev);
230
231#endif /* AM65_CPSW_NUSS_H_ */
232

source code of linux/drivers/net/ethernet/ti/am65-cpsw-nuss.h