1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Broadcom UniMAC MDIO bus controller driver |
4 | * |
5 | * Copyright (C) 2014-2017 Broadcom |
6 | */ |
7 | |
8 | #include <linux/clk.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/io.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> |
14 | #include <linux/of_mdio.h> |
15 | #include <linux/of_platform.h> |
16 | #include <linux/phy.h> |
17 | #include <linux/platform_data/mdio-bcm-unimac.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/sched.h> |
20 | |
21 | #define MDIO_CMD 0x00 |
22 | #define MDIO_START_BUSY (1 << 29) |
23 | #define MDIO_READ_FAIL (1 << 28) |
24 | #define MDIO_RD (2 << 26) |
25 | #define MDIO_WR (1 << 26) |
26 | #define MDIO_PMD_SHIFT 21 |
27 | #define MDIO_PMD_MASK 0x1F |
28 | #define MDIO_REG_SHIFT 16 |
29 | #define MDIO_REG_MASK 0x1F |
30 | |
31 | #define MDIO_CFG 0x04 |
32 | #define MDIO_C22 (1 << 0) |
33 | #define MDIO_C45 0 |
34 | #define MDIO_CLK_DIV_SHIFT 4 |
35 | #define MDIO_CLK_DIV_MASK 0x3F |
36 | #define MDIO_SUPP_PREAMBLE (1 << 12) |
37 | |
38 | struct unimac_mdio_priv { |
39 | struct mii_bus *mii_bus; |
40 | void __iomem *base; |
41 | int (*wait_func) (void *wait_func_data); |
42 | void *wait_func_data; |
43 | struct clk *clk; |
44 | u32 clk_freq; |
45 | }; |
46 | |
47 | static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset) |
48 | { |
49 | /* MIPS chips strapped for BE will automagically configure the |
50 | * peripheral registers for CPU-native byte order. |
51 | */ |
52 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
53 | return __raw_readl(addr: priv->base + offset); |
54 | else |
55 | return readl_relaxed(priv->base + offset); |
56 | } |
57 | |
58 | static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val, |
59 | u32 offset) |
60 | { |
61 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
62 | __raw_writel(val, addr: priv->base + offset); |
63 | else |
64 | writel_relaxed(val, priv->base + offset); |
65 | } |
66 | |
67 | static inline void unimac_mdio_start(struct unimac_mdio_priv *priv) |
68 | { |
69 | u32 reg; |
70 | |
71 | reg = unimac_mdio_readl(priv, MDIO_CMD); |
72 | reg |= MDIO_START_BUSY; |
73 | unimac_mdio_writel(priv, val: reg, MDIO_CMD); |
74 | } |
75 | |
76 | static int unimac_mdio_poll(void *wait_func_data) |
77 | { |
78 | struct unimac_mdio_priv *priv = wait_func_data; |
79 | u32 val; |
80 | |
81 | /* |
82 | * C22 transactions should take ~25 usec, will need to adjust |
83 | * if C45 support is added. |
84 | */ |
85 | udelay(30); |
86 | |
87 | return read_poll_timeout(unimac_mdio_readl, val, !(val & MDIO_START_BUSY), |
88 | 2000, 100000, false, priv, MDIO_CMD); |
89 | } |
90 | |
91 | static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg) |
92 | { |
93 | struct unimac_mdio_priv *priv = bus->priv; |
94 | int ret; |
95 | u32 cmd; |
96 | |
97 | ret = clk_prepare_enable(clk: priv->clk); |
98 | if (ret) |
99 | return ret; |
100 | |
101 | /* Prepare the read operation */ |
102 | cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); |
103 | unimac_mdio_writel(priv, val: cmd, MDIO_CMD); |
104 | |
105 | /* Start MDIO transaction */ |
106 | unimac_mdio_start(priv); |
107 | |
108 | ret = priv->wait_func(priv->wait_func_data); |
109 | if (ret) |
110 | goto out; |
111 | |
112 | cmd = unimac_mdio_readl(priv, MDIO_CMD); |
113 | |
114 | /* Some broken devices are known not to release the line during |
115 | * turn-around, e.g: Broadcom BCM53125 external switches, so check for |
116 | * that condition here and ignore the MDIO controller read failure |
117 | * indication. |
118 | */ |
119 | if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL)) { |
120 | ret = -EIO; |
121 | goto out; |
122 | } |
123 | |
124 | ret = cmd & 0xffff; |
125 | out: |
126 | clk_disable_unprepare(clk: priv->clk); |
127 | return ret; |
128 | } |
129 | |
130 | static int unimac_mdio_write(struct mii_bus *bus, int phy_id, |
131 | int reg, u16 val) |
132 | { |
133 | struct unimac_mdio_priv *priv = bus->priv; |
134 | u32 cmd; |
135 | int ret; |
136 | |
137 | ret = clk_prepare_enable(clk: priv->clk); |
138 | if (ret) |
139 | return ret; |
140 | |
141 | /* Prepare the write operation */ |
142 | cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | |
143 | (reg << MDIO_REG_SHIFT) | (0xffff & val); |
144 | unimac_mdio_writel(priv, val: cmd, MDIO_CMD); |
145 | |
146 | unimac_mdio_start(priv); |
147 | |
148 | ret = priv->wait_func(priv->wait_func_data); |
149 | clk_disable_unprepare(clk: priv->clk); |
150 | |
151 | return ret; |
152 | } |
153 | |
154 | /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with |
155 | * their internal MDIO management controller making them fail to successfully |
156 | * be read from or written to for the first transaction. We insert a dummy |
157 | * BMSR read here to make sure that phy_get_device() and get_phy_id() can |
158 | * correctly read the PHY MII_PHYSID1/2 registers and successfully register a |
159 | * PHY device for this peripheral. |
160 | * |
161 | * Once the PHY driver is registered, we can workaround subsequent reads from |
162 | * there (e.g: during system-wide power management). |
163 | * |
164 | * bus->reset is invoked before mdiobus_scan during mdiobus_register and is |
165 | * therefore the right location to stick that workaround. Since we do not want |
166 | * to read from non-existing PHYs, we either use bus->phy_mask or do a manual |
167 | * Device Tree scan to limit the search area. |
168 | */ |
169 | static int unimac_mdio_reset(struct mii_bus *bus) |
170 | { |
171 | struct device_node *np = bus->dev.of_node; |
172 | struct device_node *child; |
173 | u32 read_mask = 0; |
174 | int addr; |
175 | |
176 | if (!np) { |
177 | read_mask = ~bus->phy_mask; |
178 | } else { |
179 | for_each_available_child_of_node(np, child) { |
180 | addr = of_mdio_parse_addr(dev: &bus->dev, np: child); |
181 | if (addr < 0) |
182 | continue; |
183 | |
184 | read_mask |= 1 << addr; |
185 | } |
186 | } |
187 | |
188 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { |
189 | if (read_mask & 1 << addr) { |
190 | dev_dbg(&bus->dev, "Workaround for PHY @ %d\n" , addr); |
191 | mdiobus_read(bus, addr, MII_BMSR); |
192 | } |
193 | } |
194 | |
195 | return 0; |
196 | } |
197 | |
198 | static int unimac_mdio_clk_set(struct unimac_mdio_priv *priv) |
199 | { |
200 | unsigned long rate; |
201 | u32 reg, div; |
202 | int ret; |
203 | |
204 | /* Keep the hardware default values */ |
205 | if (!priv->clk_freq) |
206 | return 0; |
207 | |
208 | ret = clk_prepare_enable(clk: priv->clk); |
209 | if (ret) |
210 | return ret; |
211 | |
212 | if (!priv->clk) |
213 | rate = 250000000; |
214 | else |
215 | rate = clk_get_rate(clk: priv->clk); |
216 | |
217 | div = (rate / (2 * priv->clk_freq)) - 1; |
218 | if (div & ~MDIO_CLK_DIV_MASK) { |
219 | pr_warn("Incorrect MDIO clock frequency, ignoring\n" ); |
220 | ret = 0; |
221 | goto out; |
222 | } |
223 | |
224 | /* The MDIO clock is the reference clock (typically 250Mhz) divided by |
225 | * 2 x (MDIO_CLK_DIV + 1) |
226 | */ |
227 | reg = unimac_mdio_readl(priv, MDIO_CFG); |
228 | reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT); |
229 | reg |= div << MDIO_CLK_DIV_SHIFT; |
230 | unimac_mdio_writel(priv, val: reg, MDIO_CFG); |
231 | out: |
232 | clk_disable_unprepare(clk: priv->clk); |
233 | return ret; |
234 | } |
235 | |
236 | static int unimac_mdio_probe(struct platform_device *pdev) |
237 | { |
238 | struct unimac_mdio_pdata *pdata = pdev->dev.platform_data; |
239 | struct unimac_mdio_priv *priv; |
240 | struct device_node *np; |
241 | struct mii_bus *bus; |
242 | struct resource *r; |
243 | int ret; |
244 | |
245 | np = pdev->dev.of_node; |
246 | |
247 | priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL); |
248 | if (!priv) |
249 | return -ENOMEM; |
250 | |
251 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
252 | if (!r) |
253 | return -EINVAL; |
254 | |
255 | /* Just ioremap, as this MDIO block is usually integrated into an |
256 | * Ethernet MAC controller register range |
257 | */ |
258 | priv->base = devm_ioremap(dev: &pdev->dev, offset: r->start, size: resource_size(res: r)); |
259 | if (!priv->base) { |
260 | dev_err(&pdev->dev, "failed to remap register\n" ); |
261 | return -ENOMEM; |
262 | } |
263 | |
264 | if (of_property_read_u32(np, propname: "clock-frequency" , out_value: &priv->clk_freq)) |
265 | priv->clk_freq = 0; |
266 | |
267 | priv->mii_bus = mdiobus_alloc(); |
268 | if (!priv->mii_bus) |
269 | return -ENOMEM; |
270 | |
271 | bus = priv->mii_bus; |
272 | bus->priv = priv; |
273 | if (pdata) { |
274 | bus->name = pdata->bus_name; |
275 | priv->wait_func = pdata->wait_func; |
276 | priv->wait_func_data = pdata->wait_func_data; |
277 | bus->phy_mask = ~pdata->phy_mask; |
278 | priv->clk = pdata->clk; |
279 | } else { |
280 | bus->name = "unimac MII bus" ; |
281 | priv->wait_func_data = priv; |
282 | priv->wait_func = unimac_mdio_poll; |
283 | priv->clk = devm_clk_get_optional(dev: &pdev->dev, NULL); |
284 | } |
285 | |
286 | if (IS_ERR(ptr: priv->clk)) { |
287 | ret = PTR_ERR(ptr: priv->clk); |
288 | goto out_mdio_free; |
289 | } |
290 | |
291 | bus->parent = &pdev->dev; |
292 | bus->read = unimac_mdio_read; |
293 | bus->write = unimac_mdio_write; |
294 | bus->reset = unimac_mdio_reset; |
295 | snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "%s-%d" , pdev->name, pdev->id); |
296 | |
297 | ret = unimac_mdio_clk_set(priv); |
298 | if (ret) |
299 | goto out_mdio_free; |
300 | |
301 | ret = of_mdiobus_register(mdio: bus, np); |
302 | if (ret) { |
303 | dev_err(&pdev->dev, "MDIO bus registration failed\n" ); |
304 | goto out_mdio_free; |
305 | } |
306 | |
307 | platform_set_drvdata(pdev, data: priv); |
308 | |
309 | dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n" ); |
310 | |
311 | return 0; |
312 | |
313 | out_mdio_free: |
314 | mdiobus_free(bus); |
315 | return ret; |
316 | } |
317 | |
318 | static void unimac_mdio_remove(struct platform_device *pdev) |
319 | { |
320 | struct unimac_mdio_priv *priv = platform_get_drvdata(pdev); |
321 | |
322 | mdiobus_unregister(bus: priv->mii_bus); |
323 | mdiobus_free(bus: priv->mii_bus); |
324 | } |
325 | |
326 | static int __maybe_unused unimac_mdio_resume(struct device *d) |
327 | { |
328 | struct unimac_mdio_priv *priv = dev_get_drvdata(dev: d); |
329 | |
330 | return unimac_mdio_clk_set(priv); |
331 | } |
332 | |
333 | static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops, |
334 | NULL, unimac_mdio_resume); |
335 | |
336 | static const struct of_device_id unimac_mdio_ids[] = { |
337 | { .compatible = "brcm,asp-v2.2-mdio" , }, |
338 | { .compatible = "brcm,asp-v2.1-mdio" , }, |
339 | { .compatible = "brcm,asp-v2.0-mdio" , }, |
340 | { .compatible = "brcm,genet-mdio-v5" , }, |
341 | { .compatible = "brcm,genet-mdio-v4" , }, |
342 | { .compatible = "brcm,genet-mdio-v3" , }, |
343 | { .compatible = "brcm,genet-mdio-v2" , }, |
344 | { .compatible = "brcm,genet-mdio-v1" , }, |
345 | { .compatible = "brcm,unimac-mdio" , }, |
346 | { /* sentinel */ }, |
347 | }; |
348 | MODULE_DEVICE_TABLE(of, unimac_mdio_ids); |
349 | |
350 | static struct platform_driver unimac_mdio_driver = { |
351 | .driver = { |
352 | .name = UNIMAC_MDIO_DRV_NAME, |
353 | .of_match_table = unimac_mdio_ids, |
354 | .pm = &unimac_mdio_pm_ops, |
355 | }, |
356 | .probe = unimac_mdio_probe, |
357 | .remove_new = unimac_mdio_remove, |
358 | }; |
359 | module_platform_driver(unimac_mdio_driver); |
360 | |
361 | MODULE_AUTHOR("Broadcom Corporation" ); |
362 | MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller" ); |
363 | MODULE_LICENSE("GPL" ); |
364 | MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME); |
365 | |